Digital MEMS Vibration Sensor with Embedded RF Transceiver ADIS16000/ADIS16229 Data Sheet FEATURES GENERAL DESCRIPTION Wireless vibration system, 902.5 MHz to 927.5 MHz Clear channel assessment and packet collision avoidance Error detection and correction in radio frequency (RF) protocol Programmable RF output power Gateway node (ADIS16000) SPI to RF function Manage up to 6 sensor nodes Sensor node (ADIS16229) Dual axis, 18 g MEMS accelerometer 5.5 kHz sensor resonant frequency Digital FFT range settings: 1 g, 5 g, 10 g, and 20 g Sample rate up to 20 kSPS Programmable wake-up capture, update cycle times 512-point, real valued FFT Rectangular, Hanning, and flat top window options Programmable decimation filter, 11 rate settings Multirecord capture for selected filter settings Manual capture mode for time domain data collection Programmable FFT averaging of up to 255 averages Record storage: 14 FFT records on two axes (x and y) Programmable alarms, 6 spectral bands, 2 levels Adjustable response delay to reduce false alarms Internal self-test with status flags Digital temperature and power supply measurements Identification registers: serial number, device ID, user ID 37.8 mm x 22.8 mm x 8.8 mm MCML package (ADIS16000) 37.8 mm x 22.8 mm x 13.5 mm MCML package (ADIS16229) Single-supply operation: 3.0 V to 3.6 V Operating temperature range of -40C to +85C The ADIS16000 and ADIS16229 enable the creation of a simple wireless vibration sensing network for a wide variety of industrial equipment applications. The ADIS16000 provides the gateway function, which manages the network, while the ADIS16229 provides the remote sensing function. B SO LE TE The ADIS16229 iSensor(R) is a complete wireless vibration sensor node that combines dual axis acceleration sensing with advanced time domain and frequency domain signal processing. Time domain signal processing includes a programmable decimation filter and selectable windowing function. Frequency domain processing includes a 512-point, real valued fast Fourier transform (FFT); FFT magnitude averaging; and programmable spectral alarms. The FFT record storage system offers users the ability to track changes over time and capture FFTs with multiple decimation filter settings. APPLICATIONS O Vibration analysis Condition monitoring Machine health Instrumentation and diagnostics Safety shutoff sensing Rev. 0 The dynamic range, bandwidth, sample rate, and noise performance of the ADIS16229 are well suited for a wide variety of machine health and production equipment monitoring systems. This device also provides a number of wireless configuration parameters, enabling a wide level of flexibility in managing the trade-off between battery life and communication frequency. The ADIS16000 serial peripheral interface (SPI) provides simple connectivity with most embedded processor platforms, and the SMA connector interface enables the use of many different antennas. This module supports up to six ADIS16229 devices at one time, using a proprietary wireless protocol. The ADIS16000 module is available in a 37.8 mm x 22.8 mm x 8.8 mm multichip chip module laminate (MCML) structure, and the ADIS16229 is available in a 37.8 mm x 22.8 mm x 13.5 mm MCML structure. Both have an SMA connector for simple antenna connection, have two mounting holes for simple installation, and support operation over a -40C to +85C temperature range. The ADIS16000 also includes a standard 1 mm, 14-pin connector for connecting to an embedded processor system. The ADIS16229 provides a lead structure that enables simple connection with battery leads. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADIS16000/ADIS16229 Data Sheet TABLE OF CONTENTS FFT ............................................................................................... 21 Applications ....................................................................................... 1 FFT Averaging ............................................................................ 22 General Description ......................................................................... 1 Recording Times ........................................................................ 22 Revision History ............................................................................... 2 Data Records ............................................................................... 22 Functional Block Diagrams ............................................................. 3 FFT Record Flash Endurance ................................................... 22 Specifications..................................................................................... 4 Sensor Node Spectral Alarms ....................................................... 23 Timing Specifications .................................................................. 6 Alarm Definition ........................................................................ 23 Absolute Maximum Ratings............................................................ 7 Alarm Indicator Signals ............................................................. 24 Thermal Resistance ...................................................................... 7 Alarm Flags and Conditions ..................................................... 24 ESD Caution .................................................................................. 7 Alarm Status ................................................................................ 25 Pin Configurations and Function Descriptions ........................... 8 Worst-Case Condition Monitoring.......................................... 25 Theory of Operation ...................................................................... 10 Reading Output Data ..................................................................... 26 Sensing Element ......................................................................... 10 Reading Data from the Data Buffer ......................................... 26 Signal Processing ........................................................................ 10 Accessing FFT Record Data ...................................................... 26 LE TE Features .............................................................................................. 1 Data Format ................................................................................ 27 Gateway Communication.......................................................... 11 Real-Time Data Collection ....................................................... 27 Basic Operation of the ADIS16000 .............................................. 12 Power Supply/Temperature ....................................................... 27 SPI Write Commands ................................................................ 12 FFT Event Header ...................................................................... 28 SPI Read Commands ................................................................. 12 System Tools .................................................................................... 29 B SO Sensor Communication ............................................................. 10 Network Management ................................................................... 15 Global Commands ..................................................................... 29 Sensor Node Recording Mode and Signal Processing ............... 18 Device Identification.................................................................. 29 Recording Mode ......................................................................... 18 System Flags ................................................................................ 30 Spectral Record Production ...................................................... 19 Self-Test ....................................................................................... 30 Sample Rate and Filtering ......................................................... 19 Flash Memory Management ..................................................... 30 Dynamic Range and Sensitivity ................................................ 20 Outline Dimensions ....................................................................... 31 Dynamic Range Settings............................................................ 21 Ordering Guide .......................................................................... 32 PreFFT Windowing .................................................................... 21 O REVISION HISTORY 8/13--Revision 0: Initial Version Rev. 0 | Page 2 of 32 Data Sheet ADIS16000/ADIS16229 FUNCTIONAL BLOCK DIAGRAMS VDD RST REGISTERS CS SCLK DO1 DO2 ANTENNA WIRELESS TRANSCEIVER PROCESSOR SPI DIN ADIS16000 11483-001 DATA RECORDS DOUT Figure 1. ADIS16000 Block Diagram ANTENNA DATA RECORDS BUFFER CONFIGURATION REGISTERS FFT FILTER/ WINDOW ADC MEMS ACCELEROMETER LE ADIS16229 O B SO Figure 2. ADIS16229 Block Diagram Rev. 0 | Page 3 of 32 11483-002 PROCESSOR TE WIRELESS TRANSCEIVER VDD ADIS16000/ADIS16229 Data Sheet SPECIFICATIONS TA = -40C to +85C, VDD = 3.3 V, unless otherwise noted. Table 1. O Reset Recovery 6 TA = 25C TA = 25C, 0 g to 20 g range setting TA = 25C TA = 25C -40C TA +85C With respect to full scale 18 Sleep Mode Recovery SAMPLE RATE Clock Accuracy TRANSCEIVER Receiver Sensitivity Transmission Power Typ Max 0.3052 0.6104 0.3 0.2 4 2.3 0.01 With respect to package mounting holes TA = 25C -40C TA +85C 6 1.25 1 TA = 25C, 20.48 kHz sample rate, time domain TA = 25C, 10 Hz to 1 kHz 5% flatness, see Figure 21 2 11 0.248 840 5.5 0.7 x VDD B SO Offset Temperature Coefficient Output Noise Output Noise Density Bandwidth Sensor Resonant Frequency LOGIC INPUTS 2 (ADIS16000) Input High Voltage, VINH Input Low Voltage, VINL Input Leakage Current RST, SCLK Input Capacitance, CIN DIGITAL OUTPUTS2 (ADIS16000) Output High Voltage, VOH Output Low Voltage, VOL FLASH MEMORY Endurance 3 Data Retention 4 START-UP TIME 5 Initial Startup Min TE Nonlinearity Cross-Axis Sensitivity Alignment Error Offset Error Test Conditions/Comments LE Parameter ACCELEROMETERS (ADIS16229) Measurement Range 1 Sensitivity, FFT Sensitivity, Time Domain Sensitivity Error ISOURCE = 1 mA ISINK = 1 mA TJ = 85C, see Figure 25 0.2 x VDD 0.01 0.1 10 VDD - 0.4 0.36 20,000 20 ADIS16000 ADIS16229 ADIS16000 ADIS16229 ADIS16229 Internal sample rate Rev. 0 | Page 4 of 32 V V A mA pF V V ms ms ms ms ms kSPS % -92 -18 g mg/LSB mg/LSB % % % % Degrees g g mg/C mg rms mg/Hz Hz kHz Cycles Years 80 150 80 80 25 20 3 -40C TA +85C Unit -10.5 dBm dBm Data Sheet Parameter POWER SUPPLY Power Supply Current, ADIS16000 Test Conditions/Comments Operating voltage range, VDD Transmission mode, 10 dBm, 25C Transmission mode, -1 dBm, 25C Receive mode, 25C Transmission mode, 10 dBm, 25C Transmission mode, 10 dBm, -40C to +85C Transmission mode, -1 dBm, 25C Transmission mode, -1 dBm, -40C to +85C Receive mode, 25C Receive mode, -40C to +85C Data capture mode, no transceiver activity, 25C Sleep mode, TA = 25C Min 3.0 4 Typ 3.3 37 18 20 39 37.5 19 19.5 20.5 21.5 7.2 2.5 Max 3.6 41 26 26 TE Power Supply Current, ADIS16229 ADIS16000/ADIS16229 Unit V mA mA mA mA mA mA mA mA mA mA A The maximum range depends on the frequency of vibration. The digital input/output signals are 5 V tolerant. 3 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at -40C, +25C, +85C, and +125C. 4 Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22, Method A117. Retention lifetime depends on junction temperature. 5 The start-up times presented reflect the time it takes for data collection to begin. 6 Applies to the reset line (RST = 0) and the software reset command (GLOB_CMD_G[7] = 1). The RST pin must be held low for at least 10 s. 1 O B SO LE 2 Rev. 0 | Page 5 of 32 ADIS16000/ADIS16229 Data Sheet TIMING SPECIFICATIONS TA = 25C, VDD = 3.3 V, unless otherwise noted. See Figure 3 and Figure 4. Table 2. Parameter fSCLK tSTALL tCS Description SCLK frequency Stall time CS to SCLK edge Min tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS SCLK low pulse width, not shown in figures SCLK high pulse width, not shown in figures Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time, not shown in figures Data output rise time, not shown in figures SCLK rise time SCLK fall time Data output valid after CS edge, not shown in figures CS high after SCLK edge Max 2.5 Unit MHz s ns 30 12.9 500 500 ns ns ns ns ns ns ns ns ns ns ns 47.4 TE 25.8 12.9 10.6 10.6 10.6 10.6 32.0 32.0 32.0 32.0 59.8 12.9 LE Timing Diagrams tSR CS tSF B SO tCS 1 SCLK Typ 2 3 4 5 6 tSFS 15 16 tDAV MSB DB14 DB13 tDSU DIN R/W A6 DB12 DB11 A4 A3 DB10 DB2 DB1 LSB tDHD A5 A2 D2 D1 11483-003 DOUT LSB O Figure 3. SPI Timing and Sequence tSTALL 11483-004 CS SCLK Figure 4. DIN Bit Sequence Rev. 0 | Page 6 of 32 Data Sheet ADIS16000/ADIS16229 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Rating 2000 g 2000 g -0.3 V to +3.96 V -0.3 V to +3.96 V -0.3 V to +3.96 V Table 4. Package Characteristics Package Type 14-Pin MCML JA 31C/W JC 11C/W ESD CAUTION -40C to +85C -65C to +150C O B SO LE Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TE Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Temperature Operating Temperature Range Storage Temperature Range Rev. 0 | Page 7 of 32 Device Weight 6.5 grams ADIS16000/ADIS16229 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS PIN 1 PIN 2 TE 11483-005 PIN 14 Figure 5. ADIS16000 Pin Locations ADIS16000 CS SCLK DOUT DO2 GND VDD 11 9 7 5 3 1 14 12 10 8 6 4 2 DIN DNC DNC DNC GND VDD B SO NOTES 1. THIS REPRESENTATION DISPLAYS THE TOP VIEW WHEN THE CONNECTOR IS VISIBLE AND FACING UP. 2. MATING CONNECTOR: ML-14-4 OR EQUIVALENT. 3. DNC = DO NOT CONNECT. 11483-006 LE DO1 13 RST TOP VIEW (Not to Scale) Figure 6. ADIS16000 Pin Configuration Table 5. ADIS16000 Pin Function Descriptions Mnemonic VDD GND DO2 DNC DOUT Type 1 S S O N/A O 9 11 12 13 14 SCLK CS DIN DO1 RST I I I O I 1 O Pin No. 1, 2 3, 4 5 6, 8, 10 7 Description Power Supply, 3.3 V. Ground. Digital Output Line 2. Do not connect to these pins. SPI, Data Output. When CS is low, DOUT is an output, and when CS is high, DOUT goes into a three-state, high impedance mode. SPI, Serial Clock. SPI, Chip Select. SPI, Data Input. Digital Output Line 1. Reset, Active Low. S = supply, O = output, I = input, and N/A = not applicable. Rev. 0 | Page 8 of 32 Data Sheet ADIS16000/ADIS16229 11483-107 PIN 2 PIN 1 Table 6. ADIS16229 Pin Function Descriptions Pin No. 1 2 Type 1 S S LE S = supply. Description Power Supply, 3.3 V Ground O B SO 1 Mnemonic VDD GND TE Figure 7. ADIS16229 Pin Locations Rev. 0 | Page 9 of 32 ADIS16000/ADIS16229 Data Sheet THEORY OF OPERATION ANCHOR MOVABLE FRAME PLATE CAPACITORS FIXED PLATES UNIT SENSING CELL SENSING ELEMENT ANCHOR Figure 8. MEMS Sensor Diagram Digital vibration sensing in the ADIS16229 starts with a MEMS accelerometer core on two different axes. Accelerometers translate linear changes in velocity into a representative electrical signal, using a micromechanical system like the one shown in Figure 8. The mechanical part of this system includes two different frames, one fixed and one moving, that have a series of plates to form a variable, differential capacitive network. When experiencing the force associated with gravity or acceleration, the moving frame changes its physical position with respect to the fixed frame, which results in a change in capacitance. Tiny springs tether the moving frame to the fixed frame and govern the relationship between acceleration and physical displacement. A modulation signal on the moving plate feeds through each capacitive path into the fixed frame plates and into a demodulation circuit, which produces the electrical signal that is proportional to the acceleration acting on the device. SIGNAL PROCESSING LE Figure 10 offers a simplified block diagram for the ADIS16229. The signal processing stage includes time-domain data capture, digital decimation/filtering, windowing, FFT analysis, FFT averaging, and record storage. See Figure 18 for more details on the signal processing operation. SENSOR COMMUNICATION The ADIS16000 provides access to the ADIS16229 through dedicated pages in the register structure. When the ADIS16000 communicates with a remote ADIS16229, it copies all configuration information in these registers to their respective locations in the ADIS16229 and acquires all of the data in the output registers and data records of the ADIS16229. B SO ADIS16229 BATTERY ANTENNA ADIS16229 BATTERY ANTENNA GATEWAY NODE MEMS SENSOR ADC SENSOR NODES Figure 9. Star Wireless Network Example PROCESSING DATA BUFFER SPI AND REGISTERS RECORDS Figure 10. ADIS16229 Simplified Block Diagram Rev. 0 | Page 10 of 32 WIRELESS INTERFACE ANTENNA 11483-010 O ADIS16000 ANTENNA 11483-009 EMBEDDED PROCESSOR 11483-007 UNIT FORCING CELL MOVING PLATE TE ACCELERATION The ADIS16000 is the gateway node, and the ADIS16229 serves as the remote sensor node in a wireless vibration monitoring system. Using a proprietary wireless protocol, one ADIS16000 can support up to six ADIS16229 nodes at one time in a local star network configuration (see Figure 9). As the gateway node, the SPI interface of the ADIS16000 provides access to an addressable register map that manages configuration parameters (gateway and sensor node), remote alarm flags, and remote vibration data. The SPI interface of the ADIS16000 enables simple connection to most embedded processors, and its standard SMA connector supports direct connection to a wide variety of antennas. The ADIS16229 requires only an antenna and battery to start up and connect with the ADIS16000 to begin operation. Data Sheet ADIS16000/ADIS16229 Dual Memory Structure SPI Interface The user registers provide addressing for all input/output operations in the SPI interface. The control registers use a dual memory structure (see Figure 11). The controller uses static random access memory (SRAM) registers for normal operation, including user configuration commands. The flash memory provides nonvolatile storage for control registers that have flash backup (see Table 10 and Table 11). When the device powers on or resets, the flash memory contents load into the SRAM, and the device starts producing data according to the configuration in the control registers. Storing configuration data in the flash memory requires a manual flash update command. For the ADIS16000, set DIN = 0x8000 (access Page 0), then set DIN = 0x9240 (set GLOB_CMD_S[6] = 1). For a remote ADIS16229, use the following steps to update its flash: Register Organization 1. 2. 3. 4. Turn to its page (for example, set DIN = 0x8001 to access Sensor Node 1). Set DIN = 0xB640 (GLOB_CMD_S[6] = 1). Set DIN = 0x8000 (turn to Page 0). Set DIN = 0x9202 (GLOB_CMD_G[1] = 1). LE The memory map for the ADIS16000 contains seven pages of user accessible registers, which enable simple organization of both local (gateway) and remote (sensor) functions. Each page has a page control register (PAGE_ID), which is located at Address 0x00. The contents in this location contain the number that represents the active page. For example, if Address 0x00 has 0x05 in it, Page 5 is the active page. Change the active page assignment by writing a new value (between 0x00 and 0x06) to Address 0x00. For example, write 0x02 to Address 0x00 (DIN = 0x8002) to gain access to the registers in Page 2. B SO Each 16-bit register has its own unique bit assignment and two addresses: one for its upper byte and one for its lower byte. Table 10 and Table 11 provide more details on these memory maps, which list each register, along with its function and lower byte address. Table 7. ADIS16000 Register Map Page Organization Function Gateway configuration Sensor Node 1 Sensor Node 2 Sensor Node 3 Sensor Node 4 Sensor Node 5 Sensor Node 6 Reference Table 10 Table 11 Table 11 Table 11 Table 11 Table 11 Table 11 O PAGE_ID 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 Rev. 0 | Page 11 of 32 MANUAL FLASH BACKUP NONVOLATILE FLASH MEMORY (NO SPI ACCESS) VOLATILE SRAM (SPI ACCESS) START-UP RESET Figure 11. SRAM and Flash Memory Diagram 11483-008 The data collection and configuration command uses the SPI, which consists of four wires. The chip select (CS) signal activates the SPI interface, and the serial clock (SCLK) synchronizes the serial data lines. Input commands clock into the DIN pin, one bit at a time, on the SCLK rising edge. Output data clocks out of the DOUT pin on the SCLK falling edge. Because the ADIS16000 serves only as an SPI slave, the DOUT contents reflect the information requested using a DIN command. TE GATEWAY COMMUNICATION ADIS16000/ADIS16229 Data Sheet BASIC OPERATION OF THE ADIS16000 When the ADIS16000 has appropriate power on the VDD pin, it automatically begins a self-initialization process. When this process is completed, the SPI interface is activated and provides access to its register structure. The SPI interface supports connectivity with most embedded processor platforms, using the connection diagram in Figure 12. The factory default configuration for DO1 provides a busy indicator signal that indicates when to avoid SPI communication requests. 9 MOSI 12 MISO 7 DOUT IRQ2 5 DO2 IRQ1 13 DO1 9 8 7 6 5 4 3 2 1 0 LOWER BYTE SPI WRITE COMMANDS User control registers govern many internal operations. The DIN bit sequence in Figure 16 provides the ability to write to these registers, one byte at a time. Some configuration changes and functions require only one write cycle. For example, set PAGE_ID[7:0] = 1 (DIN = 0x8001) to select Page 1 of the register map. ADIS16000 SCLK DIN CS 4 SCLK LE 3 Figure 12. Electrical Hook-Up Diagram DIN Figure 14. SPI Sequence for Selecting Page 1 for Access (DIN = 0x8001) Table 8. Generic Master Processor Pin Names and Functions SPI READ COMMANDS Function Slave select Serial clock Master output, slave input Master input, slave output Interrupt request inputs (optional) A single register read requires two 16-bit SPI cycles that also use the bit assignments shown in Figure 16. The first sequence sets R/W = 0 and communicates the target address (Bits[A6:A0]). Bits[D7:D0] are don't care bits for a read DIN sequence. DOUT clocks out the requested register contents during the second sequence. The second sequence can also use DIN to set up the next read. Figure 15 provides a signal diagram for all four SPI signals while reading the PROD_ID_G. In this diagram, DIN = 0x1600 and DOUT reflects the decimal equivalent of 16,000. B SO Pin Name SS SCLK MOSI MISO IRQ1, IRQ2 10 11483-013 SCLK CS 11 TE 11 12 Figure 13. Generic Register Bit Definitions 2 1 SS 13 UPPER BYTE I/O LINES ARE COMPATIBLE WITH 3.3V 3.3V OR 5V LOGIC LEVELS SYSTEM PROCESSOR SPI MASTER 14 11483-012 15 11483-011 VDD Table 10 and Table 11 provide lists of user registers with their lower byte addresses. Each register consists of two bytes, each of which has its own unique 7-bit address. Figure 13 relates the bits of each register to their upper and lower addresses. The ADIS16000 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 16. Table 9 provides a list of the most common settings that require attention to initialize a processor serial port for the ADIS16000 SPI interface. Table 9. Generic Master Processor SPI Settings Description ADIS16000 operates as slave Bit rate setting Clock polarity/phase (CPOL = 1, CPHA = 1) Bit sequence Shift register/data length SCLK MSB First 16-Bit DOUT DOUT = 0011 1110 1000 0000 = 0x3E80 = 16,000 = PROD_ID_G Figure 15. Example SPI Read, PROD_ID_G (Page 0), Second Sequence CS SCLK R/W DB15 A6 A5 A4 A3 A2 A1 A0 DB14 DB13 DB12 DB11 DB10 DB9 DB8 D7 D6 D5 D4 D3 D2 D1 D0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 NOTES 1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0). Figure 16. Example SPI Read Sequence Rev. 0 | Page 12 of 32 R/W DB15 A6 A5 DB14 DB13 11483-015 DIN DOUT 11483-014 DIN O Processor Setting Master SCLK Rate 2.5 MHz SPI Mode 3 CS Data Sheet ADIS16000/ADIS16229 Table 10. User Register Memory Map, PAGE_ID = 0x0000 Address 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C Default1 0x0000 0x1234 N/A 0x0000 0x0008 N/A N/A N/A 0x0000 N/A 0x0000 0x3E80 N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0008 0x0000 Function Page identifier Network identifier, unique to a network Flash update counter Network error indicators Transmission power control, gateway Received signal strength Output, temperature Output, supply voltage FCC test support modes System commands Data to sensor nodes Product identifier, ADIS16000 Reserved Lot Identifier 1 Lot Identifier 2 Reserved Reserved Reserved Serial number, lot specific Reserved Reserved General-purpose output control Diagnostics, status flags TE Flash Backup1 N/A Yes Yes No Yes No No No Yes No No Yes No No No No No No No No No Yes No N/A = not applicable. B SO 1 Access 1 Read/write Read/write Read only Read only Read/write Read only Read only Read only Read/write Write only Read/write Read only N/A Read only Read only N/A N/A N/A Read only N/A N/A Read/write Read only LE Register Name PAGE_ID NETWORK_ID FLASH_CNT_G NW_ERROR_STAT TX_PWR_CTRL_G RSSI_G TEMP_OUT_G SUPPLY_OUT_G TEST_MODE GLOB_CMD_G CMD_DATA PROD_ID_G Reserved LOT_ID1_G LOT_ID2_G Reserved Reserved Reserved SERIAL_NUM_G Reserved Reserved GPO_CTRL DIAG_STAT_G Reference Table 7 Table 14 Table 87 Table 26 Table 18 Table 16 Table 67 Table 64 Table 23 Table 13 Table 12 Table 80 Table 76 Table 78 Table 82 Table 84 Table 85 Table 11. User Register Memory Map, PAGE_ID 0x0001 (Registers Representing Remote ADIS16229 Units) Access 1 Read/write Read only Read only Read only Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write N/A Read/write Read/write Read/write Flash Backup1 N/A Yes Yes No No No No Yes Yes No No No No Yes Yes No Yes Yes Yes Address 0x00 0x02 0x04 0x06 0x08 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 Default1, 2 N/A N/A N/A N/A N/A N/A N/A 0x0108 0x0101 0x0000 0x0000 N/A N/A 0x1102 0x00FF N/A 0x0000 0x0000 0x0000 ALM_Y_MAG1 Read/write Yes 0x26 0x0000 ALM_X_MAG2 Read/write Yes 0x28 0x0000 O Register Name PAGE_ID SENS_ID FLASH_CNT_S X_BUF Y_BUF TEMP_OUT_S SUPPLY_OUT_S FFT_AVG1 FFT_AVG2 BUF_PNTR REC_PNTR X_SENS Y_SENS REC_CTRL1 REC_CTRL2 Reserved ALM_F_LOW ALM_F_HIGH ALM_X_MAG1 Function Page identifier Sensor identifier Status, flash memory write count Output, buffer for x-axis acceleration data Output, buffer for y-axis acceleration data Output, temperature during capture Output, power supply during capture Control, FFT average, SR0 and SR1 Control, FFT average, SR2 and SR3 Control, buffer address pointer Control, record address pointer Control, x-axis scale correction factor Control, y-axis scale correction factor Record control register Record control register Reserved Spectral alarm band, low frequency Spectral alarm band, high frequency Spectral alarm band, X-Axis Alarm Trigger Level 1 magnitude Spectral alarm band, Y-Axis Alarm Trigger Level 1 magnitude Spectral alarm band, X-Axis Alarm Trigger Level 2 magnitude Rev. 0 | Page 13 of 32 Reference Table 7 Table 15 Table 88 Table 60 Table 61 Table 68 Table 65 Table 35 Table 36 Table 58 Table 59 Table 33 Table 34 Table 28 Table 31 Table 44 Table 45 Table 46 Table 47 Table 48 ADIS16000/ADIS16229 Data Sheet Flash Backup1 Yes Address 0x2A Default1, 2 0x0000 ALM_PNTR ALM_S_MAG ALM_CTRL AVG_CNT DIAG_STAT_S GLOB_CMD_S ALM_X_STAT ALM_Y_STAT ALM_X_PEAK ALM_Y_PEAK TIME_STMP_L TIME_STMP_H ALM_X_FREQ ALM_Y_FREQ PROD_ID_S REC_FLSH_CNT REC_INFO1 REC_INFO2 REC_CNTR PKT_TIME_L PKT_TIME_H PKT_ERROR_STAT TX_PWR_CTRL_S RSSI_S RF_MODE UPDAT_INT INT_SCL Reserved USER_SCR Reserved LOT_ID1_S LOT_ID2_S Reserved Reserved Read/write Read/write Read/write Read/write Read only Write only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read only Read/write Read only Read/write Read/write Read/write N/A Read only N/A Read only Read only N/A N/A No Yes Yes Yes No No No No No No No No No No Yes No No No No No No No Yes No Yes Yes Yes N/A Yes N/A Yes Yes N/A N/A 0x2C 0x2E 0x30 0x32 0x34 0x36 0x38 0x3A 0x3C 0x3E 0x40 0x42 0x44 0x46 0x48 0x4A 0x4C 0x4E 0x50 0x52 0x54 0x56 0x58 0x5A 0x5C 0x5E 0x60 0x62 0x64 0x66 0x68 0x6A 0x6C 0x6E 0x0000 0x0000 0x0080 0x9630 0x0000 N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x3F65 N/A 0x0008 0x0000 0x0000 N/A N/A 0x0000 0x0008 N/A 0x0000 0x0FA0 0x0001 N/A 0x0000 N/A N/A N/A N/A N/A 2 B SO O 1 Function Spectral alarm band, Y-Axis Alarm Trigger Level 2 magnitude Spectral alarm band pointer Alarm, system alarm trigger level Alarm, control register Sample rate control (average count) System status register Global command register Alarm, x-axis status register Alarm, y-axis status register Alarm, x-axis peak level Alarm, y-axis peak level Time stamp, low integer Time stamp, high integer Alarm frequency of x-axis ALM_X_PEAK Alarm frequency of y-axis ALM_Y_PEAK Product identification register Flash write cycle count Record Settings 1 Record Settings 2 Record counter Received packet time stamp, low integer Received packet time stamp, high integer Missed packets/error indicator Transmission power control Received signal strength indicator Wireless communication configuration Update interval Update interval scale Reserved User scratch register Reserved Lot Identification Code 1 Lot Identification Code 2 Reserved Reserved TE Access 1 Read/write LE Register Name ALM_Y_MAG2 N/A = not applicable. All registers in Page 1, Page 2, Page 3, Page 4, Page 5, and Page 6 read 0x0000 prior to connecting with the ADIS16229. Rev. 0 | Page 14 of 32 Reference Table 49 Table 43 Table 50 Table 42 Table 29 Table 86 Table 75 Table 51 Table 52 Table 53 Table 54 Table 73 Table 74 Table 55 Table 56 Table 81 Table 40 Table 71 Table 72 Table 38 Table 24 Table 25 Table 27 Table 19 Table 17 Table 20 Table 21 Table 22 Table 83 Table 77 Table 79 Data Sheet ADIS16000/ADIS16229 NETWORK MANAGEMENT 1. 2. Set GLOB_CMD_G[0] = 1 (DIN = 0x9201, in Page 0). Wait 500 s and then write the node number (between 0 and 6) to the CMD_DATA register. Table 12. CMD_DATA, Page 0, Low Byte Address = 0x14, Read/Write Description (Default = 0x0000) Not used Sensor node for GLOB_CMD_G[1] and GLOB_CMD_G[0] commands, range = 000 (0) to 110 (6) B SO Bits [15:4] [3:0] Table 13. GLOB_CMD_G, Page 0, Low Byte Address = 0x12, Write Only Bits 15 14 13 12 Bits [15:8] [7:0] 10 9 8 7 6 5 4 3 2 1 0 Description (Default = 0x1234) User configurable (no internal function) User configurable, 8-bit network identification number The SENS_ID register (see Table 15) contains the value 0x0000 when a particular page in the ADIS16000 memory map is not managing a specific ADIS16229 connection. When a page is managing a connection with an ADIS16229, the lower byte indicates the assigned node number within the network. Description (Default = Not Applicable) Remove the sensor node identified by the CMD_DATA register Not used Request current configuration and payload from the sensor node identified by the CMD_DATA register Manual update of alarm registers for the sensor node identified by the CMD_DATA register Read alarm registers from the sensor node identified by the CMD_DATA register Transfer alarm configuration from ADIS16000 page to remote sensor registers Not used Remove sensor node in CMD_DATA from the network Software reset Save registers to flash memory Flash test, compare sum of flash memory with factory value Clear DIAG_STAT_G register Restore factory register settings, including capture buffer and alarm registers Not used Update sensor node in CMD_DATA register, in one of the manual modes Add sensor node in CMD_DATA to the network Table 15. SENS_ID, Page 1 to Page 6, Low Byte Address = 0x02, Read Only Bits [15:8] [7:0] Description (Default = Not Applicable) When connected, it is 0xAD. Sensor node number. When connected, the range is 0 to 6. Receiver Signal Strength The RSSI_G and RSSI_S registers (see Table 16 and Table 17) provide tools for tuning the transmission power control at each location. Keep the transmission power high enough to maintain at least -92 dBm in these registers for best communication reliability. Table 16. RSSI_G, Page 0, Low Byte Address = 0x0A, Read Only Bits [15:0] O 11 Table 14. NETWORK_ID, Page 0, Low Byte Address = 0x02, Read/Write LE After this second step, the connection process can take up to 10 seconds after writing this code. Removing a sensor from the network uses a similar two-step process: write the sensor node number to the CMD_DATA register, and then set GLOB_CMD_G[8] = 1 (DIN = 0x9301, Page 0). Set GLOB_CMD_G[1] = 1 (DIN = 0x9202) to initialize an update of all of the registers, except those associated with the spectral alarms. Set GLOB_CMD_G[12] = 1 (DIN = 0x9310) to update all of the alarm registers, after configuring them. Separating this function helps manage the flash memory endurance. The NETWORK_ID register (see Table 14) provides a user configurable identification number in its lower byte and provides a separate 8-bit number for application-specific information that does not influence the operation of the ADIS16000. TE When the ADIS16000 and the ADIS16229 have an appropriate supply voltage across their VDD and GND pins, they both selfinitialize and prepare themselves for connecting. After completing this process, the ADIS16229 starts sending connection requests to any available ADIS16000 devices within range. The system microcontroller manages the response of the ADIS16000 to these requests, using the CMD_DATA (see Table 12) and GLOB_CMD_G registers (see Table 13), which are both in Page 0 of the ADIS16000. Adding an ADIS16229 network requires the following two steps: Description (Default = Not Applicable) Received signal strength. This is a 16-bit twos complement number, where 0x0000 represents 0 dBm and each LSB represents 1 dBm of change in the received signal strength. Examples include the following: 0x0001 = +1 dBm. 0xFFFF = -1 dBm. 0xFFA0 = -92 dBm. Table 17. RSSI_S, Page 1 to Page 6, Low Byte Address = 0x5A, Read Only Bits [15:0] Rev. 0 | Page 15 of 32 Description (Default = Not Applicable) Received signal strength. This is a 16-bit twos complement number, where 0x0000 represents 0 dBm and each LSB represents 1 dBm of change in the received signal strength. Examples include the following: 0x0001 = +1 dBm. 0xFFFF = -1 dBm. 0xFFA0 = -92 dBm. ADIS16000/ADIS16229 Data Sheet Transmission Power Control Wireless Configuration Both the ADIS16000 and ADIS16229 units provide controls for transmission power in the TX_PWR_CTRL_G (see Table 18) and TX_PWR_CTRL_S (see Table 19) registers. The registers provide users with the ability to optimize the transmission power for battery optimization and to manage interference influence on other networks. Note that compliance with FCC Part 15.247 involves limiting the transmission power to -1 dBm. The RF_MODE register (see Table 20) provides a number of important wireless configuration parameters. Note that when the transmission power exceeds -1 dBm and the update period is less than 10 seconds, FCC Part 15.247 requires the use of frequency hopping. Table 18. TX_PWR_CTRL_G, Page 0, Low Byte Address = 0x08, Read/Write Bits [15:12] [11] [10] [9:7] [6] [5:2] [1] [0] The UPDAT_INT and INT_SCL registers (see Table 21 and Table 22) establish the time between wake-up events, where the remote ADIS16229 captures data, analyzes it, and communicates the information. LE [7:5] [4:0] Description (Default = 0x0008) Not used (don't care). Channel frequency. This is a 6-bit, offset binary number that selects one of 51 channel frequencies. The lowest setting, 000000 (binary for 0 LSB), represents 902.5 MHz, and each LSB represents an increase of 0.5 MHz. The maximum setting, 110010 (binary for 50 LSB), selects a channel frequency of 927.5 MHz. Not used (don't care). Transmission power setting. This is a 5-bit, offset binary number that selects the transmission power in the gateway node. The lowest setting, 00000 (binary for 0 LSB), selects a transmission power of -15.5 dBm, and each LSB increases the transmission power by +1.7 dBm. The maximum setting, 01111, selects a transmission power of 10 dBm. Description (Default = 0x0000) Not used (don't care) Continuous transmission mode (single-channel, per TX_PWR_CTRL_S, see Table 19) Continuous frequency hopping mode Not used (don't care) Frequency hopping (0 = disable, 1 = enable) Not used (don't care) Update gateway on alarm only (0 = disable, 1 = enable) Not used (don't care) TE Bits [15:14] [13:8] Table 20. RF_MODE, Page 1 to Page 6, Low Byte Address = 0x5C, Read/Write Table 21. UPDAT_INT, Page 1 to Page 6, Low Byte Address = 0x5E, Read/Write Bits [15:0] Bits [15:14] [13:8] Table 22. INT_SCL, Page 1 to Page 6, Low Byte Address = 0x60, Read/Write Description (Default = 0x0008) Not used (don't care). Channel frequency. This is a 6-bit, offset binary number that selects one of 51 channel frequencies. The lowest setting, 000000 (binary for 0 LSB), represents 902.5 MHz, and each LSB represents an increase of 0.5 MHz. The maximum setting, 110010 (binary for 50 LSB), selects a channel frequency of 927.5 MHz. Not used (don't care). Transmission power setting. This is a 5-bit, offset binary number that selects the transmission power in the gateway node. The lowest setting, 00000 (binary for 0 LSB), selects a transmission power of -15.5 dBm, and each LSB increases the transmission power by +1.7 dBm. The maximum setting, 01111, selects a transmission power of 10 dBm. O [7:5] [4:0] B SO Table 19. TX_PWR_CTRL_S, Page 1 to Page 6, Low Byte Address = 0x58, Read/Write Bits [15:2] [1:0] Description (Default = 0x0FA0) Offset binary number, scale factor set by INT_SCL register Description (Default = 0x0001) Not used (don't care) Scale factor 00 = 30.52 s/LSB, maximum = 2 seconds 01 = 0.488 ms/LSB, maximum = 31.98 seconds 10 = 1/128 sec/LSB, maximum = 512 seconds 11 = 1 sec/LSB, maximum = 18.2 hours The TEST_MODE register (see Table 23) provides specific test modes for FCC testing. Table 23. TEST_MODE, Page 0, Low Byte Address = 0x10, Read/Write Bits [15:12] 11 10 [9:0] Rev. 0 | Page 16 of 32 Description (Default = 0x0000) Not used Continuous transmission mode (single-channel, per TX_PWR_CTRL_G, see Table 18) Continuous frequency hopping mode Not used Data Sheet ADIS16000/ADIS16229 The PKT_TIME_H (upper word) and PKT_TIME_L (lower word) registers provide a 32-bit timer for tracking the relative times associated with packet transmission times. When the timer reaches its maximum value of 0xFFFFFFFF, it automatically starts over at 0x00000000. Table 24. PKT_TIME_L, Page 1 to Page 6, Low Byte Address = 0x52, Read Only Bits [15:0] Description (Default = Not Applicable) Offset binary number, lower word, 1 LSB = 0.488 ms Table 25. PKT_TIME_H, Page 1 to Page 6, Low Byte Address = 0x54, Read Only Bits [15:0] Description (Default = Not Applicable) Offset binary number, upper word Description (Default = 0x0000) Not used Invalid packet received Received packet from an unknown device Packet synchronization failure from the most recent received packet Not used Packet length mismatch Missing packet Packets received out of sync Failure to receive acknowledgment from a sensor node Low signal strength from a sensor node, read RSSI_S register for power level of this signal (see Table 17) CRC mismatch error associated with the most recent packet from the sensor node packet O 0 Description (Default = 0x0000) Not used Received packet from an unknown device Packet synchronization failure from the most recent received packet Not used Packet length mismatch Missing packet Packets received out of sync Failure to receive acknowledgment from a sensor node Low signal strength from a sensor node, read RSSI_S register for power level of this signal (see Table 17) CRC mismatch error associated with the most recent packet from the sensor node packet LE [7:6] 5 4 3 2 1 [7:6] 5 4 3 2 1 B SO Bits [15:11] 10 9 8 Bits [15:10] 9 8 0 The NW_ERROR_STAT register (see Table 26) provides all of the error flags associated with the wireless communication. Table 26. NW_ERROR_STAT, Page 0, Low Byte Address = 0x06, Read Only Table 27. PKT_ERROR_STAT, Page 1 to Page 6, Low Byte Address = 0x56, Read Only TE Communication Tools Rev. 0 | Page 17 of 32 ADIS16000/ADIS16229 Data Sheet SENSOR NODE RECORDING MODE AND SIGNAL PROCESSING RECORDING MODE Real-Time Mode Set REC_CTRL1[1:0] = 11 to place the device into real-time mode. In this mode, the device samples only one axis, at a rate of 5 kSPS, and provides data on its output register at the SR0 sample rate setting in AVG_CNT[3:0] (see Table 29). Select the axis of measurement in this mode by reading its assigned register. For example, select the x-axis by reading X_BUF, using DIN = 0x0600. See Table 60 or Table 61 for more information on the x_BUF registers. No other ADIS16229 nodes are able to communicate with the ADIS16000 when one of the ADIS16229 nodes is in real-time mode. Table 28. REC_CTRL1, Page 1 to Page 6, Low Byte Address = 0x1A, Read/Write LE The recording mode selection establishes the data type (time or frequency domain), trigger type (manual or automatic), and data collection (captured or real time). The REC_CTRL1[1:0] bits (see Table 28) provide four operating modes: manual FFT, automatic FFT, manual time capture, and real time. After REC_CTRL1 is set, the manual FFT, automatic FFT, and manual time capture modes require a start command to start acquiring a spectral or time domain record. All of these modes automatically trigger when the sensor receives the configuration packet from the gateway. Set GLOB_CMD_S[11] = 1 to halt the operation and wait for further instructions from the ADIS16000. This data goes through all time domain signal processing, except the preFFT windowing, prior to loading into the data buffer for user access. When the data record is complete, the device transmits the data to the ADIS16000 and waits for another start command. TE The ADIS16229 provides a complete sensing system for recording and monitoring vibration data. Figure 17 provides a simplified block diagram for the signal processing associated with spectral record acquisition on both axes (x and y). User registers provide controls for data type (time or frequency), trigger mode (manual or automatic), collection mode (real time or capture), sample rates and filtering, windowing, FFT averaging, spectral alarms, and input/output management. 11 10 B SO Set REC_CTRL1[1:0] = 00 to place the device in manual FFT mode, which triggers a single FFT cycle. When the spectral record is complete, the device transmits the data to the ADIS16000 and waits for another start command. Automatic FFT Mode 9 Set REC_CTRL1[1:0] = 01 to place the device in automatic FFT mode. Use the UPDAT_INT and INT_SCL registers to establish the period between wake-up times, which triggers data capture, FFT computation, and analysis. Manual Time Capture Mode O Set REC_CTRL1[1:0] = 10 to place the device into manual time capture mode, which results in triggering a single time domain data capture. When the device operates in this mode, 512 samples of time domain data are loaded into the buffer for each axis. MEMS ADC 8 7 [6:4] [3:2] [1:0] 1 Description (Default = 0x1102) Not used (don't care) Window setting; 00 = rectangular, 01 = Hanning, 10 = flat top, 11 = N/A1 SR3: 1 = enabled for FFT, 0 = disabled; Sample rate = 20,000 / 2AVG_CNT[15:12] (see Table 29) SR2: 1 = enabled for FFT, 0 = disabled; Sample rate = 20,000 / 2AVG_CNT[11:8] (see Table 29) SR1: 1 = enabled for FFT, 0 = disabled; Sample rate = 20,000 / 2AVG_CNT[7:4] (see Table 29) SR0: 1 = enabled for FFT, 0 = disabled; Sample rate = 20,000 / 2AVG_CNT[3:0] (see Table 29) Power-down between each recording, 1 = enabled Not used (don't care) Storage method; 00 = none, 01 = alarm trigger, 10 = all, 11 = N/A1 Recording mode; 00 = manual FFT, 01 = automatic FFT, 10 = manual time capture, 11 = real-time sampling/data access N/A = not applicable. PROCESSING DATA BUFFER RECORDS Figure 17. Simplified Block Diagram Rev. 0 | Page 18 of 32 SPI AND REGISTERS 11483-016 Manual FFT Mode Bits [15:14] [13:12] Data Sheet ADIS16000/ADIS16229 Table 29) provides the settings for the four different sample rate options in REC_CTRL1[11:8] (SRx in Table 28). All four options are available when using the manual FFT, automatic FFT, and manual time capture modes. When more than one sample rate option is enabled while the device is in one of the manual modes, the device produces a spectral record for one SRx at a time, starting with the lowest number. After completing the spectral record for one SRx option, the device waits for another start command before producing a spectral record for the next SRx option that is enabled in REC_CTRL1[11:8]. When more than one sample rate option is enabled while the device is in the automatic FFT mode, the device produces a spectral record for one SRx option and then waits for the next automatic trigger, which occurs based on the UPDAT_INT and INT_SCL registers (see Table 21 and Table 22). See Figure 19 for more details on how multiple SRx options influence data collection and spectral record production. When real-time mode is used, the output data rate reflects the SR0 setting. SPECTRAL RECORD PRODUCTION The ADIS16229 produces a spectral record by taking a time record of data on both axes, then scaling, windowing, and performing an FFT process on each time record. This process is repeated for a programmable number of FFT averages, with the FFT result of each cycle accumulating in the data buffer. After completing the selected number of cycles, the FFT averaging process completes by scaling the data buffer contents. Then the data buffer contents are available to the SPI and output data registers. SAMPLE RATE AND FILTERING LE TE The sample rate for each axis is 20 kSPS. The internal ADC samples both axes in a time-interleaving pattern (x1, y1, x2, y2, and so on) that provides even distribution of data across the data record. The averaging/decimating filter provides a control for the final sample rate in the time record. By averaging and decimating the time domain data, this filter provides the ability to focus the spectral record on lower bandwidths, producing finer frequency resolution in each FFT frequency bin. The AVG_CNT register (see FFT RECORDS--NONVOLATILE FLASH MEMORY RANGE-SCALE SETTING Ks= AMAX / 215 AMAX = PEAK FROM REC_CTRL2[7:0] FFT FFT RECORD RECORD 0 1 SENSITIVITY ADJUSTMENT X_SENS AND Y_SENS SAMPLE RATE SETTING REC_CTRL1[11:8] Ks WINDOW SETTING REC_CTRL1[13:12] B SO 1 NA 20.48kSPS xK K=1 WINDOW /N A m = REC_CNTR NF = # OF AVERAGES NF = FFT_AVG Na FFT FFT AVERAGE (NF) DATA BUFFER Figure 18. Signal Flow Diagram, REC_CTRL1[1:0] = 00 or 01, FFT Analysis Modes 512 SAMPLES FFT1 RECORD 1 SR0 TRIGGER SPI/DO/TIMER X512 Y512 PWR2 TEMP2 512 SAMPLES FFT2 512 SAMPLES RECORD 1 SR1 TRIGGER SPI/DO/TIMER DATA RDY DATA CAPTURE FFTN RECORD 1 SR2 TRIGGER SPI/DO/TIMER DATA RDY FFT AVG PWR TEMP FFT RECORD AVG AVG RECORD 1 SR3 TRIGGER SPI/DO/TIMER DATA RDY DATA RDY Figure 19. Spectral Record Production, with All SRx Settings Enabled Rev. 0 | Page 19 of 32 RECORDS 11483-018 O X1 Y1 X2 Y2 FFT RECORD 13 SPI REGISTER ACCESS 11483-017 DUAL AXIS MEMS ACCEL Ko FFT RECORD m ADIS16000/ADIS16229 Data Sheet Table 30 provides a list of SRx settings available in the AVG_CNT register (see Table 29), along with the resulting sample rates, FFT bin widths, bandwidth, and estimated total noise. Note that each SRx setting also has associated range settings in the REC_CTRL2 register (see Table 31) and the FFT averaging settings that are shown in the FFT_AVG1 and FFT_AVG2 registers (see Table 35 and Table 36, respectively). Table 29. AVG_CNT, Page 1 to Page 6, Low Byte Address = 0x32, Read/Write 16 Bandwidth (Hz) 10,000 5,000 2,500 1,250 625 313 156 78 39 20 10 14g PEAK RESPONSE 12 10 8 LE Bin Width (Hz) 39.1 19.5 9.8 4.9 2.4 1.2 0.6 0.3 0.2 0.1 0.0 6 4 2 2g PEAK RESPONSE 0 1000 2000 4000 5000 6000 FREQUENCY (Hz) Figure 20. Peak Magnitude vs. Frequency B SO Sample Rate, fS (SPS) 20,000 10,000 5,000 2,500 1,250 625 313 156 78 39 20 O SRx Setting 0 1 2 3 4 5 6 7 8 9 10 14 16g PEAK RESPONSE 11483-019 Table 30. Sample Rate Settings and Filter Performance 18g PEAK RESPONSE 1.4 1.3 1.2 1.1 1.0 +3 0.9 0.8 MEAN 0.7 0.6 100 -3 1000 FREQUENCY (Hz) Figure 21. Magnitude/Frequency Response Rev. 0 | Page 20 of 32 5000 11483-020 [3:0] 18 TE [7:4] 20 PEAK MAGNITUDE (g) [11:8] Description (Default = 0x9630) Sample Rate Option 3 (SR3), binary (0 to 10), SR3 option sample rate = 20,000 / 2AVG_CNT[15:12] Sample Rate Option 2 (SR2), binary (0 to 10), SR2 option sample rate = 20,000 / 2AVG_CNT[11:8] Sample Rate Option 1 (SR1), binary (0 to 10), SR1 option sample rate = 20,000 / 2AVG_CNT[7:4] Sample Rate Option 0 (SR0), binary (0 to 10), SR0 option sample rate = 20,000 / 2AVG_CNT[3:0] The range of the ADIS16229 accelerometers depends on the frequency of the vibration. The accelerometers have a selfresonant frequency of 5.5 kHz, and the signal conditioning circuit applies a single-pole, low-pass filter (2.5 kHz) to the response. The self-resonant behavior of the accelerometer influences the relationship between vibration frequency and dynamic range. Figure 20 displays the response to peak input amplitudes, assuming a sinusoidal vibration signature at each frequency. The accelerometer resonance and low-pass filter also influence the magnitude response, as shown in Figure 21. MAGNITUDE (g) Bits [15:12] DYNAMIC RANGE AND SENSITIVITY Data Sheet ADIS16000/ADIS16229 DYNAMIC RANGE SETTINGS Scale Adjustment REC_CTRL2 (see Table 31) provides four range settings that are associated with each sample rate option, SRx. The range options referenced in REC_CTRL2 reflect the maximum dynamic range, which occurs at the lower part of the frequency range and does not account for the decrease in range (see Figure 20). For example, set REC_CTRL2[5:4] = 10 (DIN = 0x9C20) to set the peak acceleration (AMAX) to 10 g on the SR2 sample rate option. These settings optimize FFT precision and sensitivity when monitoring lower magnitude vibrations. For each range setting in Table 31, this stage scales the time domain data so that the maximum value equates to 215 LSBs for time domain data and 216 LSBs for frequency domain data. The x_SENS registers (see Table 33 and Table 34) provide a fine-scale adjustment function for each axis. The following equation describes how to use measured and ideal values to calculate the scale factor for each register in LSBs: Table 31. REC_CTRL2, Page 1 to Page 6, Low Byte Address = 0x1C, Read/Write [5:4] [3:2] [1:0] Description (Default = 0x00FF) Not used (don't care) Measurement range, SR3; 11 = 1 g, 10 = 5 g, 01 = 10 g, 00 = 20 g Measurement range, SR2; 11 = 1 g, 10 = 5 g, 01 = 10 g, 00 = 20 g Measurement range, SR1; 11 = 1 g, 10 = 5 g, 01 = 10 g, 00 = 20 g Measurement range, SR0; 11 = 1 g, 10 = 5 g, 01 = 10 g, 00 = 20 g Table 32. Range Settings and LSB Weights Time Mode (mg/LSB) 0.0305 0.1526 0.3052 0.6104 O Range Setting (g) 0 to 1 0 to 5 0 to 10 0 to 20 TE These registers contain correction factors, which come from the factory calibration process. The calibration process records accelerometer output in four different orientations and computes the correction factors for each register. These registers also provide write access for in-system adjustment. Gravity provides a common stimulus for this type of correction process. Use both +1 g and -1 g orientations to reduce the effect of offset on this measurement. In this case, the ideal measurement is 2 g, and the measured value is the difference of the accelerometer measurements at +1 g and -1 g orientations. The factoryprogrammed values are stored in flash memory and are restored by setting GLOB_CMD_S[3] = 1 (DIN = 0xB604). See Table 75. Table 33. X_SENS, Page 1 to Page 6, Low Byte Address = 0x16, Read/Write B SO Bits [15:8] [7:6] where: aXI is the ideal x-axis value. aXM is the actual x-axis measurement. LE Note that the maximum range for each setting is 1 LSB smaller than the listed maximum. For example, the maximum number of codes in the frequency domain analysis is 216 - 1, or 65,535. When using a range setting of 1 g in one of the FFT modes, the maximum measurement is equal to 1 g times 216 - 1, divided by 216. See Table 32 for the resolution associated with each setting and Figure 18 for the location of this operation in the signal flow diagram. The real-time mode automatically uses the 20 g range setting. 18 SCFx = a XI 1 x 2 a XM FFT Mode (mg/LSB) 0.0153 0.0763 0.1526 0.3052 Bits [15:0] Description (Default = Not Applicable) X-axis scale correction factor (SCFx), twos complement Table 34. Y_SENS, Page 1 to Page 6, Low Byte Address = 0x18, Read/Write Bits [15:0] Description (Default = Not Applicable) Y-axis scale correction factor (SCFy), twos complement PREFFT WINDOWING REC_CTRL1[13:12] provides three options for preFFT windowing of time data. For example, set REC_CTRL1[13:12] = 01 to use the Hanning window, which offers the best amplitude resolution of the peaks between frequency bins and minimal broadening of peak amplitudes. The rectangular and flat top windows are also available because they are common windowing options for vibration monitoring. The flat top window provides accurate amplitude resolution with a trade-off of broadening the peak amplitudes. FFT The FFT process converts each 512-sample time record into a 256-point spectral record that provides magnitude vs. frequency data. Rev. 0 | Page 21 of 32 ADIS16000/ADIS16229 Data Sheet FFT AVERAGING The FFT averaging function combines multiple FFT records to reduce the variation of the FFT noise floor, enabling detection of lower vibration levels. Each SRx option in the REC_CTRL1 register has its own FFT average control, which establishes the number of FFT records to average into the final FFT record. To enable this function, write the number of averages for each SRx option that is enabled in the REC_CTRL1 register to the FFT_AVGx registers. For example, set FFT_AVG2[15:8] = 0x10 (DIN = 0x9110) to set the number of FFT averages to 16 for the SR3 sample rate option. Bits [15:8] [7:0] Description (Default = 0x0108) FFT averages for a single record, SR1 sample rate, NF in Figure 18; range = 1 to 255, binary FFT averages for a single record, SR0 sample rate, NF in Figure 18; range = 1 to 255, binary [7:0] Description (Default = 0x0101) FFT averages for a single record, SR3 sample rate, NF in Figure 18; range = 1 to 255, binary FFT averages for a single record, SR2 sample rate, NF in Figure 18; range = 1 to 255, binary Table 38. REC_CNTR, Page 1 to Page 6, Low Byte Address = 0x50, Read Only B SO RECORDING TIMES When using automatic FFT mode, the automatic recording period (UPDAT_INT, see Table 21) must be greater than the total recording time. Use the following equations to calculate the recording time: Manual time mode tR = tS + tPT + tST + tAST FFT modes After the ADIS16229 finishes processing the FFT data, it stores the data into the data buffer, where it is available for external access using the SPI and x_BUF registers (see Table 60 and Table 61). REC_CTRL1[3:2] (see Table 28) provides programmable conditions for writing buffer data into the FFT records, which are in nonvolatile flash memory locations. Set REC_CTRL1[3:2] = 01 to store buffer data into the flash memory records only when an alarm condition is met. Set REC_CTRL1[3:2] = 10 to store every set of FFT data into the flash memory locations. The flash memory record provides space for a total of 14 records. Each record stored in flash memory contains a header and frequency domain (FFT) data from both axes, x and y. When all 14 records are full, new records do not load into the flash memory. The REC_CNTR register (see Table 38) provides a running count for the number of records that are stored. Set GLOB_CMD_S[8] = 1 (DIN = 0xB701) to clear all of the records in flash memory. LE Table 36. FFT_AVG2, Page 1 to Page 6, Low Byte Address = 0x10, Read/Write Bits [15:8] DATA RECORDS TE Table 35. FFT_AVG1, Page 1 to Page 6, Low Byte Address = 0x0E, Read/Write applies only when the alarms are enabled in ALM_CTRL[3:0] (see Table 42 for more information). For systems that cannot use DO1 to monitor the status of these operations, understanding the recording time helps predict when data is available. Note that when using automatic FFT mode, the automatic recording period (UPDAT_INT, see Table 21) must be greater than the total recording time. tR = NF x (tS + tPT + tFFT) + tST + tAST O Table 37 provides a list of the processing times and settings used in these equations. Table 37. Typical Processing Times Function Sample Time, tS Processing Time, tPT Storage Time, tST Alarm Scan Time, tAST Number of FFT Averages, NF FFT Time, tFFT Time (ms) 1 / fS, per AVG_CNT 18.7 120.0 2.21 Per FFT_AVG1, FFT_AVG2 32.7 Bits [15:5] [4:0] Description (Default = 0x0000) Not used Total number of records taken; range = 0 to 13, binary When used in conjunction with automatic trigger mode and record storage, FFT analysis for each sample rate option requires no additional inputs. Depending on the number of FFT averages, the time between each sample rate selection may be quite large. Note that selecting multiple sample rates reduces the number of records available for each sample rate setting, as shown in Table 39. Table 39. Available Records per Sample Rate Selected Number of Sample Rates Selected 1 2 3 4 Available Records 14 7 4 3 FFT RECORD FLASH ENDURANCE The REC_FLSH_CNT register (see Table 40) increments when all 14 records contain FFT data. The storage time (tST) applies only when a storage method is selected in REC_CTRL1[3:2] (see Table 28 for more details about the record storage settings). The alarm scan time (tAST) Table 40. REC_FLSH_CNT, Page 1 to Page 6, Low Byte Address = 0x4A, Read Only Bits [15:0] Rev. 0 | Page 22 of 32 Description (Default = Not Applicable) Flash write cycle count; record data only, binary Data Sheet ADIS16000/ADIS16229 SENSOR NODE SPECTRAL ALARMS Description Alarm frequency band, lower limit Alarm frequency band, upper limit X-axis Alarm Trigger Level 1 (warning) Y-axis Alarm Trigger Level 1 (warning) X-axis Alarm Trigger Level 2 (fault) Y-axis Alarm Trigger Level 2 (fault) Alarm pointer System alarm trigger level Alarm configuration Alarm status X-axis alarm status Y-axis alarm status X-axis alarm peak Y-axis alarm peak X-axis alarm frequency of peak alarm Y-axis alarm frequency of peak alarm B SO The ALM_CTRL register (see Table 42) provides control bits that enable the spectral alarms of each axis, configures the system alarm, sets the record delay for the spectral alarms, and configures the clearing function for the DIAG_STAT_S error flags (see Table 86). Table 42. ALM_CTRL, Page 1 to Page 6, Low Byte Address = 0x30, Read/Write Bits [15:12] [11:8] Description (Default = 0x0080) Not used. Response delay; range = 0 to 15. Represents the number of spectral records for each spectral alarm before a spectral alarm flag is set high. Latch DIAG_STAT_S error flags. Requires a clear status command (GLOB_CMD_S[4]) to reset the flags to 0. 1 = enabled, 0 = disabled. Enable DO1 as an Alarm 1 output indicator and enable DO2 as an Alarm 2 output indicator. 1 = enabled, 0 = disabled. System alarm comparison polarity. 1 = trigger when less than ALM_S_MAG[15:0]. 0 = trigger when greater than ALM_S_MAG[15:0]. System alarm. 1 = temperature, 0 = power supply. Alarm S enable (ALM_S_MAG). 1 = enabled, 0 = disabled. Not used. Alarm Y enable (ALM_Y_MAG). 1 = enabled, 0 = disabled. Alarm X enable (ALM_X_MAG). 1 = enabled, 0 = disabled. O 7 6 5 4 3 2 1 0 ALM_F_LOW ALM_x_MAG2 ALM_F_HIGH ALM_x_MAG1 1 2 3 4 5 6 FREQUENCY 11483-021 Address 0x20 0x22 0x24 0x26 0x28 0x2A 0x2C 0x2E 0x30 0x34 0x38 0x3A 0x3C 0x3E 0x44 0x46 LE Register ALM_F_LOW ALM_F_HIGH ALM_X_MAG1 ALM_Y_MAG1 ALM_X_MAG2 ALM_Y_MAG2 ALM_PNTR ALM_S_MAG ALM_CTRL DIAG_STAT_S ALM_X_STAT ALM_Y_STAT ALM_X_PEAK ALM_Y_PEAK ALM_X_FREQ ALM_Y_FREQ The alarm function provides six programmable spectral bands, as shown in Figure 22. Each spectral alarm band has lower and upper frequency definitions for all of the sample rate options (SRx). It also has two independent trigger level settings, which are useful for systems that value warning and fault condition indicators. TE Table 41. Alarm Function Register Summary ALARM DEFINITION MAGNITUDE The alarm function offers six spectral bands for alarm detection. Each spectral band has high and low frequency definitions, along with two different trigger thresholds (Alarm 1 and Alarm 2) for each accelerometer axis. Table 41 provides a summary of each register used to configure the alarm function. Figure 22. Spectral Band Alarm Setting Example, ALM_PNTR = 0x03 Select the spectral band for configuration by writing its number (1 to 6) to ALM_PNTR[2:0] (see Table 43). Then select the sample rate option using ALM_PNTR[9:8]. This number represents a binary number, which corresponds to the x in the SRx sample rates option associated with REC_CTRL1[11:8] (see Table 28). For example, set ALM_PNTR[7:0] = 0x05 (DIN = 0xAC05) to select Alarm Spectral Band 5, and set ALM_PNTR[15:8] = 0x02 (DIN = 0xAC02) to select the SR2 sample rate option. Table 43. ALM_PNTR, Pages 1 to 6, Low Byte Address = 0x2C, Read/Write Bits [15:10] [9:8] [7:3] [2:0] Rev. 0 | Page 23 of 32 Description (Default = 0x0000) Not used Sample rate option; range = 0 to 3 for SR0 to SR3 Not used Spectral band number; range = 1 to 6 ADIS16000/ADIS16229 Data Sheet After the spectral band and sample rate settings are set, program the lower and upper frequency boundaries by writing their bin numbers to the ALM_F_LOW register (see Table 44) and ALM_F_HIGH register (see Table 45). Use the bin width definitions listed in Table 30 to convert a frequency into a bin number for this definition. Calculate the bin number by dividing the frequency by the bin width associated with the sample rate setting. For example, if the sample rate is 5000 Hz and the lower band frequency is 400 Hz, divide that number by the bin width of 10 Hz to arrive at the 40th bin as the lower band setting. Then set ALM_F_LOW[7:0] = 0x28 (DIN = 0xA028) to establish 400 Hz as the lower frequency for the 5000 SPS sample rate setting. Description (Default = 0x0000) Not used Lower frequency, bin number; range = 0 to 255 Alarm Trigger Settings Table 48. ALM_X_MAG2, Page 1 to Page 6, Low Byte Address = 0x28, Read/Write Bits [15:0] Description (Default = 0x0000) X-Axis Alarm Trigger Level 2, 16-bit unsigned (see Table 31 and Table 32 for the scale factor) Table 49. ALM_Y_MAG2, Page 1 to Page 6, Low Byte Address = 0x2A, Read/Write Description (Default = 0x0000) Y-Axis Alarm Trigger Level 2, 16-bit unsigned (see Table 31 and Table 32 for the scale factor) Bits [15:0] Description (Default = 0x0000) System alarm trigger level, data format matches target from ALM_CTRL[4] (see Table 42) LE Description (Default = 0x0000) Not used Upper frequency, bin number; range = 0 to 255 Description (Default = 0x0000) Y-Axis Alarm Trigger Level 1, 16-bit unsigned (see Table 31 and Table 32 for the scale factor) Table 50. ALM_S_MAG, Page 1 to Page 6, Low Byte Address = 0x2E, Read/Write Table 45. ALM_F_HIGH, Page 1 to Page 6, Low Byte Address = 0x22, Read/Write Bits [15:8] [7:0] Bits [15:0] Bits [15:0] Table 44. ALM_F_LOW, Page 1 to Page 6, Low Byte Address = 0x20, Read/Write Bits [15:8] [7:0] Table 47. ALM_Y_MAG1, Page 1 to Page 6, Low Byte Address = 0x26, Read/Write TE Alarm Band Frequency Definitions Enable Alarm Settings O B SO The ALM_x_MAG1 and ALM_x_MAG2 registers (see Table 46 to Table 49) provide two independent trigger settings for both axes of acceleration data. They use the data format established by the range settings in the REC_CTRL2 register (see Table 31) and recording mode in REC_CTRL1[1:0] (see Table 28). For example, when using the 0 g to 1 g mode for FFT analysis, 32,768 LSB is the closest setting to 500 mg. Therefore, set ALM_Y_MAG2 = 0x8000 (DIN = 0xAB80, 0xAA00) to set the critical alarm to 500 mg, when using the 0 g to 1 g range option in REC_CTRL2 for FFT records. See Table 31 and Table 32 for more information about formatting each trigger level. Note that the trigger settings associated with Alarm 2 must be greater than the trigger settings for Alarm 1. In other words, the alarm magnitude settings must meet the following criteria: Before configuring the spectral alarm registers, clear their current contents by setting GLOB_CMD_S[9] = 1 (DIN = 0xB702). After completing the spectral alarm band definitions, save the settings by setting GLOB_CMD_S[12] = 1 (DIN = 0xB710). The device ignores the save command if any of these locations has already been written to. ALM_X_MAG2 > ALM_X_MAG1 ALM_Y_MAG2 > ALM_Y_MAG1 Table 46. ALM_X_MAG1, Page 1 to Page 6, Low Byte Address = 0x24, Read/Write Bits [15:0] Description (Default = 0x0000) X-Axis Alarm Trigger Level 1, 16-bit unsigned (see Table 31 and Table 32 for the scale factor) ALARM INDICATOR SIGNALS GPO_CTRL[5:0] (see Table 84) and ALM_CTRL[6] (see Table 42) provide controls for establishing DO1 and DO2 as dedicated alarm output indicator signals. Use GPO_CTRL[5:0] to select the alarm function for DO1 and/or DO2, then set ALM_CTRL[6] = 1 to enable DO1 to serve as an Alarm 1 indicator and DO2 as an Alarm 2 indicator. This setting establishes DO1 to indicate Alarm 1 (warning) conditions and DO2 to indicate Alarm 2 (critical) conditions. ALARM FLAGS AND CONDITIONS The FFT header (see Table 70) contains both generic alarm flags (DIAG_STAT_S, see Table 86) and spectral band-specific alarm flags (ALM_x_STAT, see Table 51 and Table 52). The FFT header also contains magnitude (ALM_x_PEAK, see Table 53 and Table 54) and frequency information (ALM_x_FREQ, see Table 55 and Table 56) associated with the highest magnitude of vibration content in the record. Rev. 0 | Page 24 of 32 Data Sheet ADIS16000/ADIS16229 ALARM STATUS WORST-CASE CONDITION MONITORING The ALM_x_STAT registers (see Table 51 and Table 52) provide alarm bits for each spectral band on the current sample rate option. The ALM_x_PEAK registers (see Table 53 and Table 54) contain the peak magnitude for the worst-case alarm condition in each axis. The ALM_x_FREQ registers (see Table 55 and Table 56) contain the frequency bin number for the worst-case alarm condition. Description (Default = 0x0000) Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm Not used Most critical alarm condition, spectral band; range = 1 to 6 Table 52. ALM_Y_STAT, Page 1 to Page 6, Low Byte Address = 0x3A, Read Only Bits [15:0] Description (Default = 0x0000) Alarm peak, x-axis, accelerometer data format Table 54. ALM_Y_PEAK, Page 1 to Page 6, Low Byte Address = 0x3E, Read Only Bits [15:0] Description (Default = 0x0000) Alarm peak, y-axis, accelerometer data format Table 55. ALM_X_FREQ, Page 1 to Page 6, Low Byte Address = 0x44, Read Only Bits [15:8] [7:0] B SO Description (Default = 0x0000) Alarm 2 on Band 6; 1 = alarm set, 0 = no alarm Alarm 1 on Band 6; 1 = alarm set, 0 = no alarm Alarm 2 on Band 5; 1 = alarm set, 0 = no alarm Alarm 1 on Band 5; 1 = alarm set, 0 = no alarm Alarm 2 on Band 4; 1 = alarm set, 0 = no alarm Alarm 1 on Band 4; 1 = alarm set, 0 = no alarm Alarm 2 on Band 3; 1 = alarm set, 0 = no alarm Alarm 1 on Band 3; 1 = alarm set, 0 = no alarm Alarm 2 on Band 2; 1 = alarm set, 0 = no alarm Alarm 1 on Band 2; 1 = alarm set, 0 = no alarm Alarm 2 on Band 1; 1 = alarm set, 0 = no alarm Alarm 1 on Band 1; 1 = alarm set, 0 = no alarm Not used Most critical alarm condition, spectral band; range = 1 to 6 Description (Default = 0x0000) Not used Alarm frequency of x-axis peak alarm level, FFT bin number; range = 0 to 255 Table 56. ALM_Y_FREQ, Page 1 to Page 6, Low Byte Address = 0x46, Read Only Bits [15:8] [7:0] O Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 [2:0] Table 53. ALM_X_PEAK, Page 1 to Page 6, Low Byte Address = 0x3C, Read Only LE Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 [2:0] TE Table 51. ALM_X_STAT, Page 1 to Page 6, Low Byte Address = 0x38, Read Only Rev. 0 | Page 25 of 32 Description (Default = 0x0000) Not used Alarm frequency of y-axis peak alarm level, FFT bin number; range = 0 to 255 ADIS16000/ADIS16229 Data Sheet READING OUTPUT DATA After the ADIS16229 updates the ADIS16000 with its data, the data is available in the data buffer and FFT records, if selected. In manual time capture mode, the record for each axis contains 512 samples. In manual and automatic FFT mode, each record contains the 256-point FFT result for each accelerometer axis. Table 57 provides a summary of registers that provide access to processed sensor data. DATA IN BUFFERS LOAD INTO USER OUTPUT REGISTERS X_BUF Y_BUF 0 BUF_PNTR X-AXIS Y-AXIS ACCELEROMETER ACCELEROMETER DATA DATA BUFFER BUFFER Table 57. Output Data Registers (Sensor Nodes) Description Internal temperature Power supply Data buffer index pointer FFT record index pointer X-axis accelerometer data Y-axis accelerometer data FFT record retrieve command Time stamp, lower word Time stamp, upper word FFT record header information FFT record header information FFT ANALYSIS INTERNAL SAMPLING SYSTEM SAMPLES, PROCESSES, AND STORES DATA IN DATA BUFFERS. TEMP_OUT 11483-022 SUPPLY_OUT Figure 23. Data Buffer Structure and Operation Table 58. BUF_PNTR, Page 1 to Page 6, Low Byte Address = 0x12, Read/Write Description (Default = 0x0000) Not used Data bits; range = 0 to 255 (FFT), 0 to 511 (time) ACCESSING FFT RECORD DATA The FFT records can be stored in flash memory. The REC_PNTR register (see Table 59) and GLOB_CMD_S[13] (see Table 75) provide access to the FFT records, as shown in Figure 24. For example, set REC_PNTR[7:0] = 0x0A (DIN = 0x940A) and GLOB_CMD_S[13] = 1 (DIN = 0xB720) to load FFT Record 10 in the FFT buffer for SPI/register access. B SO After completing a spectral record and updating each data buffer, the ADIS16000 loads the first data sample from each data buffer into the x_BUF registers (see Table 60 and Table 61) and sets the buffer index pointer in the BUF_PNTR register (see Table 58) to 0x0000. The index pointer determines which data samples load into the x_BUF registers. For example, writing 0x009F to the BUF_PNTR register (DIN = 0x9300, DIN = 0x929F) causes the 160th sample in each data buffer location to load into the x_BUF registers. The index pointer increments with every x_BUF read command, which causes the next set of capture data to load into each capture buffer register automatically. This enables an efficient method for reading all 256 samples in a record, using sequential read commands, without having to manipulate the BUF_PNTR register. Bits [15:9] [8:0] Table 59. REC_PNTR, Page 1 to Page 6, Low Byte Address = 0x14, Read/Write O Bits [15:4] [3:0] Description (Default = 0x0000) Not used (don't care) Data bits FFT RECORD 0 X Y FFT HEADER 0 FFT RECORD 1 X Y FFT HEADER 1 m = REC_PNTR GLOB_CMD_S[13] = 1 FFT RECORD m X Y FFT HEADER m DATA BUFFER X, Y FFT HEADER REGISTERS FFT RECORD 15 X SPI REGISTERS Figure 24. FFT Record Access Rev. 0 | Page 26 of 32 Y FFT HEADER 15 11483-023 READING DATA FROM THE DATA BUFFER 256/512 TE Address 0x0A 0x0C 0x12 0x14 0x06 0x08 0x36 0x40 0x42 0x4C 0x4E LE Register TEMP_OUT_S SUPPLY_OUT_S BUF_PNTR REC_PNTR X_BUF Y_BUF GLOB_CMD_S TIME_STMP_L TIME_STMP_H REC_INFO1 REC_INFO2 Data Sheet ADIS16000/ADIS16229 DATA FORMAT POWER SUPPLY/TEMPERATURE Table 60 and Table 61 list the bit assignments for the x_BUF registers. The acceleration data format depends on the range scale setting in REC_CTRL2 (see Table 31) and the recording mode settings in REC_CTRL1 (see Table 28). Table 62 provides some data formatting examples for the FFT mode, and Table 63 offers some data formatting examples for the 16-bit, twos complement format used in manual time mode. Both the ADIS16000 and the ADIS16229 offer power supply and temperature measurements. The ADIS16229 performs these measurements at the end of each spectral record, while the ADIS16000 does so continuously. The power supply measurements (SUPPLY_OUT_x, see Table 64 and Table 65) come from averaging a data record of 256 samples (50 kSPS). The temperature measurements (TEMP_OUT_x, see Table 67 and Table 68) come from averaging a data record of 64 samples, which cover a total time of 1.7 ms. When using real-time mode, these registers update only when this mode starts. Table 60. X_BUF, Page 1 to Page 6, Low Byte Address = 0x06, Read Only Description (Default = Not Applicable) Buffer for x-axis acceleration data See Table 32 for scale sensitivity Format = twos complement (time), binary (FFT) Table 64. SUPPLY_OUT_G, Page 0, Low Byte Address = 0x0E, Read Only TE Bits [15:0] Bits [15:0] Table 61. Y_BUF, Page 1 to Page 6, Low Byte Address = 0x08, Read Only Table 65. SUPPLY_OUT_S, Page 1 to Page 6, Low Byte Address = 0x0C, Read Only Description (Default = Not Applicable) Buffer for y-axis acceleration data See Table 32 for scale sensitivity Format = twos complement (time), binary (FFT) Bits [15:0] Table 66. Power Supply Data Format Examples Table 62. FFT Mode, 5 g Range, Data Format Examples LSB 65,535 100 2 1 0 Hex 0xFFFF 0x0064 0x0002 0x0001 0x0000 Binary 1111 1111 1111 1111 0000 0000 0110 0100 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 B SO Acceleration (mg) 4,999.9237 100 x 5 / 65,536 2 x 5 / 65,536 1 x 5 / 65,536 0 Table 63. Manual Time Mode, 5 g Range, Data Format Examples LSB 32,767 6,554 2 1 0 -1 -2 -6554 -32,768 Hex 0x7FFF 0x199A 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xE666 0x8000 O Acceleration (mg) 4999.847 ~1000 2 x 5 / 32,768 1 x 5 / 32,768 0 -1 x +5 / +32,768 -2 x +5 / +32,768 ~-1000 -5000 Description (Default = Not Applicable) Power supply, binary, 3.3 V = 0x1D46, 0.44 mV/LSB LE Bits [15:0] Description (Default = Not Applicable) Power supply, binary, 3.3 V = 0x1D46, 0.44 mV/LSB Binary 1111 1111 1111 1111 0001 0001 10011010 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1110 0110 0110 0110 1000 0000 0000 0000 REAL-TIME DATA COLLECTION When using real-time mode, select the output channel by reading the associated x_BUF register. For example, set DIN = 0x0880 to select the y-axis sensor for sampling. After selecting the channel, use the data ready signal to trigger subsequent data reading of the Y_BUF register. In this mode, use the time domain data formatting for a range setting of 20 g, as shown in Table 32. Supply Level (V) 3.6 3.3 + 0.00044 3.3 3.3 - 0.00044 3.15 LSB 8182 7501 7500 7499 7159 Hex 0x1FF6 0x1D4D 0x1D4C 0x1D4B 0x1BF7 Binary 0001 1111 1111 0110 0001 1101 0100 1101 0001 1101 0100 1100 0001 1101 0100 1011 0001 1011 1111 0111 Table 67. TEMP_OUT_G, Page 0, Low Byte Address = 0x0C, Read Only Bits [15:0] Description (Default = Not Applicable) Temperature data, offset binary, 4584 LSB = 0C, -0.0815C/LSB Table 68. TEMP_OUT_S, Page 1 to Page 6, Low Byte Address = 0x0A, Read Only Bits [15:0] Description (Default = Not Applicable) Temperature data, offset binary, 4584 LSB = 0C, -0.0815C/LSB Table 69. Internal Temperature Data Format Examples Temperature (C) 125 0 + 0.0815 0 0 - 0.0815 -40 Rev. 0 | Page 27 of 32 LSB 3050 4583 4584 4585 5075 Hex 0x0BEA 0x11E7 0x11E8 0x11E9 0x13D3 Binary 0000 1011 1110 1010 0001 0001 1110 0111 0001 0001 1110 1000 0001 0001 1110 1001 0001 0011 1101 0011 ADIS16000/ADIS16229 Data Sheet FFT EVENT HEADER Each FFT record has an FFT header containing information that fills all of the registers listed in Table 70. The information in these registers contains recording time, record configuration settings, status/error flags, and several alarm outputs. The registers listed in Table 70 update with every record event and also update with record-specific information when using GLOB_CMD_S[13] (see Table 75) to retrieve a data set from the FFT record in flash memory. The REC_INFO1 register (see Table 71) and the REC_INFO2 register (see Table 72) capture the settings associated with the current FFT record. Table 71. REC_INFO1, Page 1 to Page 6, Low Byte Address = 0x4C, Read Only Bits [15:14] [13:12] Table 70. FFT Header Register Information Description Alarm status X-axis alarm status Y-axis alarm status X-axis alarm peak Y-axis alarm peak Time stamp, lower word Time stamp, upper word X-axis alarm frequency of peak alarm Y-axis alarm frequency of peak alarm FFT record header information FFT record header information [11:10] TE Address 0x34 0x38 0x3A 0x3C 0x3E 0x40 0x42 0x44 0x46 0x4C 0x4E [9:8] [7:0] Table 72. REC_INFO2, Page 1 to Page 6, Low Byte Address = 0x4E, Read Only Bits [15:4] [3:0] Description (Default = 0x0000) Not used (don't care) AVG_CNT setting LE Register DIAG_STAT_S ALM_X_STAT ALM_Y_STAT ALM_X_PEAK ALM_Y_PEAK TIME_STMP_L TIME_STMP_H ALM_X_FREQ ALM_Y_FREQ REC_INFO1 REC_INFO2 Description (Default = 0x0008) Sample rate option; 00 = SR0, 01 = SR1, 10 = SR2, 11 = SR3 Window setting; 00 = rectangular, 01 = Hanning, 10 = flat top, 11 = not applicable Signal range; 00 = 1 g, 01 = 5 g, 10 = 10 g, 11 = 20 g Not used (don't care) FFT averages; range = 0 to 255 The TIME_STMP_x registers (see Table 73 and Table 74) provide a relative time stamp that identifies the time for the current FFT record. B SO Table 73. TIME_STMP_L, Page 1 to Page 6, Low Byte Address = 0x40, Read Only Bits [15:0] Description (Default = 0x0000) Record time stamp, low integer, binary, seconds Table 74. TIME_STMP_H, Page 1 to Page 6, Low Byte Address = 0x42, Read Only O Bits [15:0] Rev. 0 | Page 28 of 32 Description (Default = 0x0000) Record time stamp, high integer, binary, seconds Data Sheet ADIS16000/ADIS16229 SYSTEM TOOLS GLOBAL COMMANDS The GLOB_CMD_S register (see Table 75) provides an array of single write commands for convenience. Setting the assigned bit to 1 activates each function. When the function completes, the bit restores itself to 0. For example, clear the capture buffers by setting GLOB_CMD_S[8] = 1 (DIN = 0xB701). All of the commands in the GLOB_CMD_S register require that the power supply be within normal limits for the execution times listed in Table 75. 4 3 2 1 0 Table 80. PROD_ID_G, Page 0, Low Byte Address = 0x16, Read Only Bits [15:0] Bits [15:0] Description (Default = Not Applicable) Serial number, lot specific Table 83 shows a blank register that is available for writing userspecific identification. Table 83. USER_SCR, Page 1 to Page 6, Low Byte Address = 0x64, Read Only Bits [15:0] O Description (Default = Not Applicable) Lot identification code Description (Default = Not Applicable) Lot identification code Table 78. LOT_ID2_G, Page 0, Low Byte Address = 0x1C, Read Only Description (Default = 0x0000) User scratch register Table 84. GPO_CTRL, Page 0, Low Byte Address = 0x2A, Read/Write Bits [15:6] [5:4] [3:2] Table 77. LOT_ID1_S, Page 1 to Page 6, Low Byte Address = 0x68, Read Only Bits [15:0] Description (Default = 0x3F65) 0x3F65 = 16,229 Table 82. SERIAL_NUM_G, Page 0, Low Byte Address = 0x24, Read Only Table 76. LOT_ID1_G, Page 0, Low Byte Address = 0x1A, Read Only Bits [15:0] Description (Default = 0x3E80) 0x3E80 = 16,000 TE Bits [15:0] DEVICE IDENTIFICATION Bits [15:0] Description (Default = Not Applicable) Lot identification code LE Description (Default = Not Applicable) Clear autonull correction Retrieve spectral alarm band information from the ALM_PNTR setting Retrieve record data from flash memory Save spectral alarm band registers to SRAM Record start/stop Set BUF_PNTR = 0x0000 Clear spectral alarm band registers from flash memory Clear records Software reset Save registers to flash memory Flash test, compare sum of flash memory with factory value Clear DIAG_STAT_S register Restore factory register settings and clear the capture buffers Self-test, result in DIAG_STAT_S[5] Power-down Autonull B SO 13 12 11 10 9 8 7 6 5 Bits [15:0] Table 81. PROD_ID_S, Page 1 to Page 6, Low Byte Address = 0x48, Read Only Table 75. GLOB_CMD_S, Page 1 to Page 6, Low Byte Address = 0x36, Write Only Bits 15 14 Table 79. LOT_ID2_S, Page 1 to Page 6, Low Byte Address = 0x6A, Read Only 1 0 Description (Default = Not Applicable) Lot identification code Rev. 0 | Page 29 of 32 Description (Default = 0x0008) Not used DO2 function selection 00 = general-purpose 01 = alarm indicator 10 = busy indicator/data ready (real-time mode) 11 = not used DO1 function selection 00 = general-purpose 01 = alarm indicator 10 = busy indicator/data ready (real-time mode) 11 = not used DO2 polarity 1 = active high 0 = active low DO1 polarity 1 = active high 0 = active low ADIS16000/ADIS16229 Data Sheet SYSTEM FLAGS SELF-TEST Critical system flags are in the DIAG_STAT_x registers (see Table 85 and Table 86) for each ADIS16229. These flags indicate various indicators for monitoring the network. Multiple flags in these registers can be high at one time, and the flags persist (that is, go high again, after clearing) when the error conditions continue to exist. The flags in DIAG_STAT_S[6:0] remain in a latch condition until the problem clears or the flags are cleared using GLOB_CMD_S[4]. All of the alarm flags in the upper byte (DIAG_STAT_S[15:8] latch if ALM_CTRL[7] = 1 (see Table 42). Set GLOB_CMD_S[2] = 1 (DIN = 0xB602) (see Table 75) to run an automatic self-test routine, which reports a pass/fail result to DIAG_STAT_S[5] (see Table 85). Table 87. FLASH_CNT_G, Page 0, Low Byte Address = 0x04, Read Only 5 4 3 2 1 0 Table 88. FLASH_CNT_S, Page 1 to Page 6, Low Byte Address = 0x04, Read Only Bits [15:0] 600 O Description (Default = 0x0000) Not used System alarm; 1 = error condition exists, 0 = no error Not used Alarm 2, Y-axis; 1 = alarm condition, 0 = no alarm Alarm 2, X-axis; 1 = alarm condition, 0 = no alarm Not used Alarm 1, Y-axis; 1 = alarm condition, 0 = no alarm Alarm 1, X-axis; 1 = alarm condition, 0 = no alarm Not used Flash memory failure, from GLOB_CMD_S[5] test (see Table 75) Self-test (1 = fail, 0 = pass) Record process interrupted Not used Flash update failure Power supply > 3.625 V Power supply < 2.0 V Description (Default = Not Applicable) Binary counter for writing to flash memory 450 300 150 0 30 40 55 70 85 100 125 135 150 JUNCTION TEMPERATURE (C) Figure 25. Flash Memory Data Retention vs. Junction Temperature Rev. 0 | Page 30 of 32 11483-024 Table 86. DIAG_STAT_S, Page 1 to Page 6, Low Byte Address = 0x34, Read Only Bits 15 14 13 12 11 10 9 8 7 6 Description (Default = Not Applicable) Binary counter for writing to flash memory LE Bits [15:0] RETENTION (Years) [5:4] 3 2 1 0 Description (Default = 0x0000) Not used System alarm; 1 = alarm condition Sensor Node 6 new data; 1 = new data received Sensor Node 5 new data; 1 = new data received Sensor Node 4 new data; 1 = new data received Sensor Node 3 new data; 1 = new data received Sensor Node 2 new data; 1 = new data received Sensor Node 1 new data; 1 = new data received Command completion; 1 = completed Flash memory failure, from GLOB_CMD_S[5] test (see Table 75) Not used SPI communication; 1 = SCLKs multiple of 16 Flash update failure Power supply > 3.625 V Power supply < 2.0 V B SO Bits 15 14 13 12 11 10 9 8 7 6 Set GLOB_CMD_S[5] = 1 (DIN = 0xB620) to run an internal checksum test on the flash memory, which reports a pass/fail result to DIAG_STAT_S[6]. The FLASH_CNT_S register (see Table 87) provides a running count of flash memory write cycles in each ADIS16229. This is a tool for managing the endurance of the flash memory. The FLASH_CNT_G (see Table 87) register provides this function for the ADIS16000 as well. Figure 25 quantifies the relationship between data retention and junction temperature. TE Table 85. DIAG_STAT_G, Page 0, Low Byte Address = 0x2C, Read Only FLASH MEMORY MANAGEMENT Data Sheet ADIS16000/ADIS16229 OUTLINE DIMENSIONS 23.00 22.80 22.60 5.37 BSC 11.40 BSC 1.727 1.600 1.473 DETAIL A 38.00 37.80 37.60 TE 4.50 BSC 47.75 47.35 46.95 O 3.60 BSC LE O 7.14 BSC B SO 9.00 BSC TOP VIEW SIDE VIEW 14.60 BSC 11.40 BSC 1.00 BSC PITCH 7.54 BSC 8.77 BSC 1.00 BSC 0.50 BCS END VIEW 0.30 BCS SQ DETAIL A Figure 26. 14-Pin Connector Multichip Chip Module Laminate [MCML] (ML-14-4) Dimensions shown in millimeters Rev. 0 | Page 31 of 32 06-13-2013-A O 6.00 BCS ADIS16000/ADIS16229 Data Sheet 23.00 22.80 22.60 3.50 BSC 15.80 BSC 10.60 BSC 1.727 1.600 1.473 O 2.70 BSC (3 PLCS) 3.50 BSC 38.00 37.80 37.60 TE 30.80 BSC 47.75 47.35 46.95 7.50 BSC LE 3.94 BSC 1.27 BSC B SO 2.54 BSC TOP VIEW SIDE VIEW 13.50 BSC O END VIEW 06-16-2013-A 11.40 BSC Figure 27. 2-Pin Multichip Chip Module Laminate [MCML] (ML-2-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADIS16000AMLZ ADIS16229AMLZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 14-Pin Connector Multichip Chip Module Laminate [MCML] 2-Pin Multichip Chip Module Laminate [MCML] Z = RoHS Compliant Part. (c)2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11483-0-8/13(0) Rev. 0 | Page 32 of 32 Package Option ML-14-4 ML-2-1