Precision JFET, High Speed,
Dual Operational Amplifier
OP249
Rev. G
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1989–2010 Analog Devices, Inc. All rights reserved.
FEATURES
Fast slew rate: 22 V/μs typical
Settling time (0.01%): 1.2 μs maximum
Offset voltage: 200 μV typical
High open-loop gain: 1000 V/mV minimum
Low total harmonic distortion: 0.002% typical
APPLICATIONS
Output amplifier for fast DACs
Signal processing
Instrumentation amplifiers
Fast sample-and-holds
Active filters
Low distortion audio amplifiers
Input buffer for ADCs
Servo controllers
PIN CONFIGURATIONS
O
UT A
1
–IN A
2
+IN A
3
V–
4
V+
8
OUT B
7
–IN B
6
+IN B
5
OP249
A
B
00296-001
Figure 1. 8-Lead CERDIP (Q-8) and
8-Lead PDIP (N-8)
+IN A
1
V–
2
+IN B
3
–IN B
4
–IN A
8
OUT A
7
V+
6
OUT B
5
A
B
OP249
00296-002
Figure 2. 8-Lead SOIC (R-8)
GENERAL DESCRIPTION
The OP249 is a high speed, precision dual JFET op amp, similar
to the popular single op amp. The OP249 outperforms available
dual amplifiers by providing superior speed with excellent dc
performance. Ultrahigh open-loop gain (1 kV/mV minimum),
low offset voltage, and superb gain linearity makes the OP249
the industry’s first true precision, dual high speed amplifier.
With a slew rate of 22 V/μs typical and a fast settling time of less
than 1.2 μs maximum to 0.01%, the OP249 is an ideal choice for
high speed bipolar DAC and ADC applications. The excellent
dc performance of the OP249 allows the full accuracy of high
resolution CMOS DACs to be realized.
Symmetrical slew rate, even when driving large load, such as,
600 Ω or 200 pF of capacitance and ultralow distortion, make
the OP249 ideal for professional audio applications, active filters,
high speed integrators, servo systems, and buffer amplifiers.
10
0%
100
90
870ns
500ns10mV
00296-003
0.01
0
.001
20 100 1k 10k 20k
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 10kΩ
A
V
= 1
00296-004
10
0%
100
90
5V 1µs
00296-005
Figure 3. Fast Settling (0.01%) Figure 4. Low Distortion, AV = 1, RL = 10 kΩ Figure 5. Excellent Output Drive, RL = 600 Ω
OP249
Rev. G | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics ............................................................. 3
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Typical Performance Characteristics ..............................................7
Applications Information .............................................................. 13
Open-Loop Gain Linearity ....................................................... 14
Offset Voltage Adjustment ........................................................ 14
Settling Time ............................................................................... 14
DAC Output Amplifier .............................................................. 15
Discussion on Driving ADCs ................................................... 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
4/10—Rev. F to Rev. G
Changes to Features Section and General Description Section . 1
Changes to Offset Voltage Parameter, Table 1 .............................. 3
Deleted Long Term Offset Voltage Parameter and
Note 1, Table 1 ................................................................................... 3
Changes to Offset Voltage Parameter, Offset Voltage
Temperature Coefficient Parameter, and Note 1, Table 3 ........... 5
Delete OP249F Columns, Table 3 ................................................... 5
Changes to Offset Voltage Parameter and Offset Voltage
Temperature Coefficient Parameter, Table 4 ................................. 5
Inserted OP249F Columns, Table 4 ............................................... 5
Changes to Discussion on Driving ADCs Section ..................... 16
Deleted Figure 52 and Figure 53 ................................................... 17
5/07—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 3 and Table 4 ....................................................... 5
Changes to Table 5 ............................................................................ 6
Changes to Figure 31 ...................................................................... 11
Changes to Figure 37 and Figure 38 ............................................. 12
Deleted OP249 SPICE Macro-Model Section ............................ 14
Deleted Figure 18; Renumbered Sequentially ............................ 14
Deleted Table I ................................................................................ 15
Changes to Discussion on Driving ADCs Section ..................... 17
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
9/01—Rev. D to Rev. E
Edits to Features and Pin Connections .......................................... 1
Edits to Electrical Characteristics .............................................. 2, 3
Edits to Absolute Maximum Ratings, Package Type, and
Ordering Guide .................................................................................. 4
Deleted Wafer Test Limits and Dice Characteristics Section ...... 5
Edits to Typical Performance Characteristics ................................ 8
Edits to Macro-Model Figure ........................................................ 15
Edits to Outline Dimensions ......................................................... 17
OP249
Rev. G | Page 3 of 20
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions
OP249A OP249F
Unit Min Typ Max Min Typ Max
Offset Voltage VOS VCM = 0 V 0.2 0.75 0.2 0.9 mV
Offset Stability 1.5 1.5 µV/month
Input Bias Current IB VCM = 0 V, TA = 25°C 30 75 30 75 pA
Input Offset Current IOS VCM = 0 V, TA = 25°C 6 25 6 25 pA
Input Voltage Range1 IVR 12.5 12.5 V
±11 ±11 V
−12.5 –12.5 V
Common-Mode Rejection CMR VCM = ±11 V 80 90 80 90 dB
Power-Supply Rejection Ratio PSRR VS = ± 4.5 V to ±18 V 12 31.6 12 50 µV/V
Large Signal Voltage Gain AVO VO = ±10 V, RL = 2 kΩ 1000 1400 500 1200 V/mV
Output Voltage Swing VO RL = 2 kΩ 12.5 12.5 V
±12.0 ±12.0 V
−12.5 –12.5 V
Short-Circuit Current Limit ISC Output shorted to
ground
36 36 mA
±20 ±50 ±20 ±50 mA
−33 –33 mA
Supply Current ISY No load, VO = 0 V 5.6 7.0 5.6 7.0 mA
Slew Rate SR RL = 2 kΩ, CL = 50 pF 18 22 18 22 V/µs
Gain Bandwidth Product2 GBW 3.5 4.7 3.5 4.7 MHz
Settling Time tS 10 V step 0.01%3 0.9 1.2 0.9 1.2 µs
Phase Margin ΘM 0 dB gain 55 55 Degrees
Differential Input Impedance ZIN 1012||6 1012||6 Ω||pF
Open-Loop Output Resistance RO 35 35 Ω
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 2 µV p-p
Voltage Noise Density en fO = 10 Hz 75 75 nV/√Hz
f
O = 100 Hz 26 26 nV/√Hz
f
O = 1 kHz 17 17 nV/√Hz
f
O = 10 kHz 16 16 nV/√Hz
Current Noise Density in fO = 1 kHz 0.003 0.003 pA/√Hz
Voltage Supply Range VS ±4.5 ±15 ±18 ±4.5 ±15 ±18 V
1 Guaranteed by CMR test.
2 Guaranteed by design.
3 Settling time is sample tested.
OP249
Rev. G | Page 4 of 20
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions
OP249G
Unit Min Typ Max
Offset Voltage VOS VCM = 0 V 0.4 2.0 mV
Input Bias Current IB VCM = 0 V, TA = 25°C 40 75 pA
Input Offset Current IOS VCM = 0 V TA = 25°C 10 25 pA
Input Voltage Range1 IVR 12.5 V
±11 V
−12.0 V
Common-Mode Rejection CMR VCM = ±11 V 76 90 dB
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 12 50 µV/V
Large Signal Voltage Gain AVO VO = ±10 V; RL = 2 kΩ 500 1100 V/mV
Output Voltage Swing VO RL = 2 kΩ 12.5 V
±12.0 V
−12.5 V
Short-Circuit Current Limit ISC Output shorted to ground 36 mA
±20 ±50 mA
−33 mA
Supply Current ISY No load; VO = 0 V 5.6 7.0 mA
Slew Rate SR RL = 2 kΩ, CL = 50 pF 18 22 V/µs
Gain Bandwidth Product2 GBW 4.7 MHz
Settling Time tS 10 V step 0.01% 0.9 1.2 µs
Phase Margin ΘM 0 dB gain 55 Degree
Differential Input Impedance ZIN 1012||6 Ω||pF
Open-Loop Output Resistance RO 35 Ω
Voltage Noise en p-p 0.1 Hz to 10 Hz 2 V p-p
Voltage Noise Density en fO = 10 Hz 75 nV/√Hz
f
O = 100 Hz 26 nV/√Hz
f
O = 1 kHz 17 nV/√Hz
f
O = 10 kHz 16 nV/√Hz
Current Noise Density in fO = 1 kHz 0.003 pA/√Hz
Voltage Supply Range VS ±4.5 ±15 ±18 V
1 Guaranteed by CMR test.
2 Guaranteed by design.
OP249
Rev. G | Page 5 of 20
VS = ±15 V, −55°C ≤ TA ≤ +125°C for A grade, unless otherwise noted.
Table 3.
Parameter Symbol Conditions
OP249A
Unit
Min Typ Max
Offset Voltage VOS VCM = 0 V 0.12 1.0 mV
Offset Voltage Temperature Coefficient TCVOS VCM = 0 V 1 10 µV/°C
Input Bias Current1 I
B 4 20 nA
Input Offset Current1 I
OS 0.04 4 nA
Input Voltage Range2 IVR 12.5 V
±11 V
−12.5 V
Common-Mode Rejection CMR VCM = ±11 V 76 110 dB
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 5 50 µV/V
Large Signal Voltage Gain AVO RL = 2 kΩ; VO = ±10 V 500 1400 V/mV
Output Voltage Swing VO RL = 2 kΩ 12.5 V
±12 V
−12.5 V
Supply Current ISY No load, VO = 0 V 5.6 7.0 mA
1 TA = 125°C.
2 Guaranteed by CMR test.
VS = ±15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 4.
Parameter Symbol Conditions
OP249F OP249G
Unit
Min Typ Max Min Typ Max
Offset Voltage VOS VCM = 0 V 0.5 1.1 1.0 3.6 mV
Offset Voltage Temperature Coefficient TCVOS V
CM = 0 V 2.2 12 6 25 µV/°C
Input Bias Current1 I
B 0.3 4.0 0.5 4.5 nA
Input Offset Current1 I
OS 0.02 1.2 0.04 1.5 nA
Input Voltage Range2 IVR 12.5 12.5 V
±11 ±11 V
−12.5 −12.5 V
Common-Mode Rejection CMR VCM = ±11 V 80 90 76 95 dB
Power Supply Rejection Ratio PSRR VS = ±4.5 V to ±18 V 7 100 10 100 µV/V
Large Signal Voltage Gain AVO RL = 2 kΩ; VO = ±10 V 250 1200 250 1200 V/mV
Output Voltage Swing VO RL = 2 kΩ 12.5 12.5 V
±12 ±12.0 V
−12.5 −12.5 V
Supply Current ISY No load, VO = 0 V 5.6 7.0 5.6 7.0 mA
1 TA = 85°C.
2 Guaranteed by CMR test.
OP249
Rev. G | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter1 Rating
Supply Voltage ±18 V
Input Voltage2 ±18 V
Differential Input Voltage2 36 V
Output Short-Circuit Duration Indefinite
Storage Temperature Range −65°C to +175°C
Operating Temperature Range
OP249A (Q) −55°C to +125°C
OP249F (Q) −40°C to +85°C
OP249G (N, R) −40°C to +85°C
Junction Temperature Range
OP249A (Q), OP249F (Q) −65°C to +175°C
OP249G (N, R) −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
1 Absolute maximum ratings apply to packaged parts, unless otherwise noted.
2 For supply voltages less than ±18 V, the absolute maximum input voltage is
equal to the supply voltage.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6. Thermal Resistance
Package Type θJA1 θ
JC Unit
8-Lead CERDIP (Q) 134 12 °C/W
8-Lead PDIP (N) 96 37 °C/W
8-Lead SOIC (R) 150 41 °C/W
1 θJA is specified for worst-case mounting conditions, that is, θJA is specified for
device in socket for CERDIP and PDIP packages; θJA is specified for device
soldered to printed circuit board for SOIC package.
ESD CAUTION
OP249
Rev. G | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
120
100
80
60
40
20
0
–20
0
45
90
135
180
225
T
A
= 25°C
V
S
= ±15V
R
L
= 2kΩ
FREQUENCY (Hz)
OPEN-LOOP GAIN (dB)
PHASE (°C)
1k 10k 100k 1M 10M 100M
GAIN
PHASE
Θm = 55
0
0296-006
Figure 6. Open-Loop Gain, Phase vs. Frequency
65
60
45
55
50
10
8
2
6
4
PHASE MARGIN (°C)
VS = ±15V
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
GAIN BANDWIDTH PRODUCT (MHz)
GBW
Θm
0
0296-007
Figure 7. Phase Margin, Gain Bandwidth Product vs. Temperature
140
120
100
80
60
40
20
0
FREQUENCY (Hz)
100 1k 10k 100k 1M 10M
TA = 25°C
VS = ±15V
COMMON-MODE REJECTION (dB)
00296-008
Figure 8. Common-Mode Rejection vs. Frequency
120
100
80
60
40
20
0
T
A
= 25°C
V
S
= ±15V
+PSRR
–PSRR
POWER SUPPLY REJECTION (dB)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M
00296-009
Figure 9. Power Supply Rejection vs. Frequency
28
26
24
–SR
22
20
18
16
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
+SR
SLEW RATE (V/µs)
V
S
= ±15V
R
L
= 2kΩ
C
L
= 50pF
00296-010
Figure 10. Slew Rate vs. Temperature
28
26
24
22
20
18
16
DIFFERENTIAL INPUT VOLTAGE (V)
0 0.2 0.4 0.6 0.8 1.0
SLEW RATE (V/µs)
T
A
= 25°C
V
S
= ±15V
R
L
= 2kΩ
00296-011
Figure 11. Slew Rate vs. Differential Input Voltage
OP249
Rev. G | Page 8 of 20
35
30
25
20
15
10
5
CAPACITIVE LOAD (pF)
0 100 200 300 400 500
SLEW RATE (V/µs)
T
A
= 25°C
V
S
= ±15V
NEGATIVE
POSITIVE
00296-012
Figure 12. Slew Rate vs. Capacitive Load
–10
–8
–6
–4
–2
0
2
4
6
8
10
0.01%
0.01%
0.1%
0.1%
TA = 25°C
VS = ±15V
AVCL = 1
SETTLING TIME (ns)
0 200 400 600 800 1000
OUTPUT STEP SIZE (V)
00296-013
Figure 13. Step Size vs. Settling Time
100
80
60
40
20
0
VOLTAGE NOISE DENSITY (nV/ Hz)
T
A
= 25°C
V
S
= ±15V
FREQUENCY (Hz)
0 100 1k 10k
00296-014
Figure 14. Voltage Noise Density vs. Frequency
0.01
0.001
20 100 1k 10k 20k
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 10kΩ
A
V
= 1
00296-015
Figure 15. Distortion vs. Frequency
0.01
0.001
20 100 1k 10k 20k
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 2kΩ
A
V
= 1
00296-016
Figure 16. Distortion vs. Frequency
0.01
0.001
20 100 1k 10k 20k
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 600Ω
A
V
= 1
00296-017
Figure 17. Distortion vs. Frequency
OP249
Rev. G | Page 9 of 20
0.1
0.01
20 100 1k 10k 20k
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 10kΩ
A
V
= 1
00296-018
Figure 18. Distortion vs. Frequency
0.1
0.01
20 100 1k 10k 20k
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 2kΩ
A
V
= 10
00296-019
Figure 19. Distortion vs. Frequency
0.1
0.01
20 100 1k 10k 20k
T
A
= 25°C
V
S
= ±15V
V
O
= 10V p-p
R
L
= 600kΩ
A
V
= 10
00296-020
Figure 20. Distortion vs. Frequency
BANDWIDTH (0.1Hz TO 10Hz)
T
A
= 25°C, V
S
= ±15V
+1µV
–1µV
500mV 1s
00296-021
Figure 21. Low Frequency Noise
10
0
–10
60
50
40
30
20
–20
T
A
= 25°C
V
S
= ±15V
A
VCL
= 100
A
VCL
= 10
A
VCL
= 5
A
VCL
= 1
FREQUENCY (Hz)
1k 10k 100k 1M 10M 100M
CLOSED-LOOP GAIN (dB)
00296-022
Figure 22. Closed-Loop Gain vs. Frequency
10
0
50
40
30
20
FREQUENCY (Hz)
100 1k 10k 100k 1M 10M
IMPEDANCE (Ω)
T
A
= 25°C
V
S
= ±15V
A
VCL
= 1
A
VCL
= 10
A
VCL
= 100
00296-023
Figure 23. Closed-Loop Output Impedance vs. Frequency
OP249
Rev. G | Page 10 of 20
25
20
15
10
0
1k
30
5
1M 10M
FREQUENCY (Hz)
OUTPUT VOLTAGE (V p-p)
AD8512
AD712
OP249
00296-024
Figure 24. Output Voltage vs. Frequency
60
50
40
30
20
10
0
70
80
90
LOAD CAPACITANCE (pF)
0 100 200 300 400 500
OVERSHOOT (%)
A
VCL
= 1
POSITIVE EDGE
A
VCL
= 5
A
VCL
= 1
NEGATIVE EDGE
V
S
= ±15V
R
L
= 2kΩ
V
IN
= 100mV p-p
00296-025
Figure 25. Small Overshoot vs. Load Capacitance
14
12
10
8
0
16
6
4
2
LOAD RESISTANCE (Ω)
100 1k 10k
MAXIMUM OUTPUT SWING (V)
+V
OHM
= |–V
OHM
|
T
A
= 25°C
V
S
= ±15V
00296-026
Figure 26. Maximum Output Voltage Swing vs. Load Resistance
–20
–15
–10
–5
0
5
10
15
20
0 ±5 ±10 ±15 ±20
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE SWING (V)
TA = 25°C
RL = 2kΩ
00296-027
Figure 27. Output Voltage Swing vs. Supply Voltage
5.2
5.4
5.6
5.8
6.0
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
V
S
= ±15V
NO LOAD
SUPPLY CURRENT (mA)
00296-028
Figure 28. Supply Current vs. Temperature
5.0
5.2
5.4
5.6
5.8
6.0
SUPPLY VOLTAGE (V)
0 5 10 15 20
SUPPLY CURRENT (mA)
T
A
= –55°C
T
A
= +125°C
T
A
= +25°C
00296-029
Figure 29. Supply Current vs. Supply Voltage
OP249
Rev. G | Page 11 of 20
UNITS
160
180
140
120
100
80
60
40
20
0
–1000 –800 –600 –400 –200 0 200 400 600 800 1000
VOS (µV)
TA = 25°C
VS = ±15V
415 × OP249
(830 OP AMPS)
00296-030
Figure 30. VOS Distribution (N-8)
UNITS
240
300
210
180
150
120
90
60
30
0
270
024681012141618202224
TCVOS (µV/°C)
VS = ±15V
–40°C TO +85°C
(830 OP AMPS)
00296-031
Figure 31. TCVOS Distribution (N-8)
50
20
30
0
40
10
TIME AFTER POWER APPLIED (Minutes)
01234
OFFSET VOLTAGE (µV)
5
V
S
= ±15V
00296-032
Figure 32. Offset Voltage Warm-Up Drift
100
1k
10k
10
1
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
VS = ±15V
VCM = 0V
INPUT BIAS CURRENT (pA)
00296-033
Figure 33. Input Bias Current vs. Temperature
COMMON-MODE VOLTAGE (V)
–15 –10 –5 0 5 10 15
10
4
10
3
10
2
10
1
10
0
T
A
= 25°C
V
S
= ±15V
BIAS CURRENT (pA)
00296-034
Figure 34. Bias Current vs. Common-Mode Voltage
50
20
30
0
40
10
INPUT BIAS CURRENT (pA)
T
A
= 25°C
V
S
= ±15V
TIME AFTER POWER APPLIED (Minutes)
02468
00296-035
10
Figure 35. Bias Current Warm-Up Drift
OP249
Rev. G | Page 12 of 20
80
20
0
40
60
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
INPUT OFFSET CURRENT (pA)
T
A
= 25°C
V
CM
= 0V
00296-036
Figure 36. Input Offset Current vs. Temperature
12000
4000
2000
0
6000
8000
10000
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
OPEN-LOOP GAIN (V/mV)
V
S
= ±15V
R
L
= 10kΩ
R
L
= 2kΩ
00296-037
Figure 37. Open-Loop Gain vs. Temperature
80
20
0
40
60
SINK
SHORT-CIRCUIT OUTPUT CURRENT (mA)
V
S
= ±15V
TEMPERATURE (°C)
–75 –50 –25 0 25 50 75 100 125
SOURCE
00296-038
Figure 38. Short-Circuit Output Current vs. Junction Temperature
OP249
Rev. G | Page 13 of 20
APPLICATIONS INFORMATION
+IN
V
+
V
OUT
V–
–IN
0
0296-039
Figure 39. Simplified Schematic (1/2 OP249)
+3V
+18V
+3V 5kΩ
5kΩ
1/2
OP249
1/2
OP249
2
1
3
6
54
8
7
–18V
0
0296-040
Figure 40. Burn-In Circuit
The OP249 represents a reliable JFET amplifier design,
featuring an excellent combination of dc precision and high
speed. A rugged output stage provides the ability to drive a
600 Ω load and still maintain a clean ac response. The OP249
features a large signal response that is more linear and symmetric
than previously available JFET input amplifiers. Figure 41
compares the large signal response of the OP249 to other
industry-standard dual JFET amplifiers.
Typically, the slewing performance of the JFET amplifier is
specified as a number of V/μs. There is no discussion on the
quality, that is, linearity and symmetry of the slewing response.
10
0%
100
90
A) OP249
10
0%
100
90
B) LT1057
10
0%
100
90
C) AD712
1µs5V
1µs5V
1µs5V
00296-041
Figure 41. Large-Signal Transient Response,
AV = 1, VIN = 20 V p-p, ZL = 2 kΩ//200 pF, VS = ±15 V
The OP249 was carefully designed to provide symmetrically
matched slew characteristics in both the negative and positive
directions, even when driving a large output load.
The slewing limitation of the amplifier determines the
maximum frequency at which a sinusoidal output can be
obtained without significant distortion. However, it is important
to note that the nonsymmetric slewing typical of previously
available JFET amplifiers adds a higher series of harmonic
energy content to the resulting response—and an additional
dc output component. Examples of potential problems of
nonsymmetric slewing behavior can be in audio amplifier
applications, where a natural low distortion sound quality is
desired and in servo or signal processing systems where a net
dc offset cannot be tolerated. The linear and symmetric slewing
feature of the OP249 makes it an ideal choice for applications
that exceed the full power bandwidth range of the amplifier.
OP249
Rev. G | Page 14 of 20
10
0%
100
90
50mV 1µs
00296-042
Figure 42. Small-Signal Transient Response,
AV = 1, ZL = 2 kΩ||100 pF, No Compensation, VS = ±15 V
As with most JFET input amplifiers, the output of the OP249
can undergo phase inversion if either input exceeds the specified
input voltage range. Phase inversion does not damage the
amplifier, nor does it cause an internal latch-up condition.
Supply decoupling should be used to overcome inductance and
resistance associated with supply lines to the amplifier. A 0.1 μF
and a 10 μF capacitor should be placed between each supply pin
and ground.
OPEN-LOOP GAIN LINEARITY
The OP249 has both an extremely high open-loop gain of
1 kV/mV minimum and constant gain linearity, which enhances its
dc precision and provides superb accuracy in high closed-loop
gain applications. Figure 43 illustrates the typical open-loop
gain linearity—high gain accuracy is assured, even when
driving a 600 Ω load.
OFFSET VOLTAGE ADJUSTMENT
The inherent low offset voltage of the OP249 makes offset
adjustments unnecessary in most applications. However, where
a lower offset error is required, balancing can be performed
with simple external circuitry, as shown in Figure 44 and Figure 45.
HORIZONTAL 5V/DIV
OUTPUT CHARGE
VERTICAL 50µV/DIV
INPUT VARIATION
00296-043
Figure 43. Open-Loop Gain Linearity; Variation in Open-Loop Gain Results in
Errors in High Closed-Loop Gain Circuits; RL = 600 Ω, VS = ±15 V
+V R3
R4
R2
R1
V
OS
ADJUST RANGE = ±V
V
OUT
V
IN
–V
1/2
OP249
R2
31Ω
R5
5
0kΩ
R1
200kΩ
00296-044
Figure 44. Offset Adjustment for Inverting Amplifier Configuration
+
V
R5
V
OS
ADJUST RANGE = ±V R2
R1
1 + R5
R4 IF R2 << R4
R5
R4 + R2
R4
V
OUT
–V
V
IN
R3
50kΩ
R2
33Ω
R1
200kΩ
1/2
OP249
GAIN = = 1 +
V
OUT
V
IN
=
00296-045
Figure 45. Offset Adjustment for Noninverting Amplifier Configuration
In Figure 44, the offset adjustment is made by supplying a small
voltage at the noninverting input of the amplifier. Resistors R1
and R2 attenuate the potentiometer voltage, providing a ±2.5 mV
(with VS = ±15 V) adjustment range, referred to the input.
Figure 45 shows the offset adjustment for the noninverting
amplifier configuration, also providing a ±2.5 mV adjustment
range. As shown in the equations in Figure 45, if R4 is not much
greater than R2, a resulting closed-loop gain error must be
accounted for.
SETTLING TIME
The settling time is the time between when the input signal begins
to change and when the output permanently enters a prescribed
error band. The error bands on the output are 5 mV and 0.5 mV,
respectively, for 0.1% and 0.01% accuracy.
Figure 46 shows the settling time of the OP249, which is typically
870 ns. Moreover, problems in settling response, such as thermal
tails and long-term ringing, are nonexistent.
10
0%
100
90
500ns10mV
870ns
00296-046
Figure 46. Settling Characteristics of the OP249 to 0.01%
OP249
Rev. G | Page 15 of 20
DAC OUTPUT AMPLIFIER Because the DAC output capacitance appears at the inputs of
the op amp, it is essential that the amplifier be adequately
compensated. Compensation increases the phase margin and
ensures an optimal overall settling response. The required lead
compensation is achieved with Capacitor C in Figure 48.
Unity-gain stability, a low offset voltage of 300 μV typical, and a
fast settling time of 870 ns to 0.01%, makes the OP249 an ideal
amplifier for fast DACs.
For CMOS DAC applications, the low offset voltage of the OP249
results in excellent linearity performance. CMOS DACs, such as
the PM7545, typically have a code-dependent output resistance
variation between 11 kΩ and 33 kΩ. The change in output
resistance, in conjunction with the 11 kΩ feedback resistor, results
in a noise gain change, which causes variations in the offset
error, increasing linearity errors. The OP249 features low offset
voltage error, minimizing this effect and maintaining 12-bit
linearity performance over the full-scale range of the converter.
+15V
PM7545
12
500Ω
75Ω
AGND
DGND
DATA INPUT
REFERENCE
OR V
IN
V
DD
0.1µF
V
OUT
V
DD
R
FB
OUT
1
DB
11
TO DB
0
19
18 20
3
V
REF
C
33pF
–15V
1
23
28
4
0.1µF
0.1µF
1
1/2
OP249
00296-047
Figure 47. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance—Unipolar Operation
+15V
PM7545
500Ω
75Ω
AGND
DGND
12
DATA INPUT
VOUT
0.1µF
–15V
1/2
OP249
1/2
OP249
7
5
64
R5
10kΩ
1%
R4
20kΩ
1%
R3
10kΩ
1%
1
8
2
3
1
2
3
0.1µF
C
33pF
VDD
0.1µF
REFERENCE
OR VIN
DB11 TO DB0
OUT1
RFB
VDD
VREF
18 20
19
00296-048
Figure 48. Fast Settling and Low Offset Error of the OP249 Enhances CMOS DAC Performance—Bipolar Operation
OP249
Rev. G | Page 16 of 20
10
0%
100
90
500mV 1µs
4µs
10
0%
100
90
500mV 1µs
4µs
A
C = 5pF
RESPONSE IS GROSSLY UNDERDAMPED,
AND EXHIBITS RINGING
B
C = 15pF
FAST RISE TIME CHARACTERISTICS, BUT AT EXPENSE
OF SLIGHT PEAKING IN RESPONSE
00296-049
Figure 49. Effect of Altering Compensation from Circuit in Figure 47—PM7545 CMOS DAC with 1/2 OP249, Unipolar Operation;
Critically Damped Response Is Obtained with C ≈ 33 pF
Figure 49 illustrates the effect of altering the compensation on
the output response of the circuit in Figure 47. Compensation is
required to address the combined effect of the output capacitance
of the DAC, the input capacitance of the op amp, and any stray
capacitance. Slight adjustments to the compensation capacitor may
be required to optimize settling response for any given application.
The settling time of the combination of the current output DAC
and the op amp can be approximated by
22 AMPtDACtTOTALt SSS
The actual overall settling time is affected by the noise gain of
the amplifier, the applied compensation, and the equivalent
input capacitance at the input of the amplifier.
DISCUSSION ON DRIVING ADCs
Settling characteristics of op amps also include the ability of the
amplifier to recover, that is, settle, from a transient current output
load condition. An example of this includes an op amp driving
the input from a SAR-type ADC. Although the comparison
point of the converter is usually diode clamped, the input swing
of plus-and-minus a diode drop still gives rise to a significant
modulation of input current. If the closed-loop output impedance
is low enough and bandwidth of the amplifier is sufficiently
large, the output settles before the converter makes a comparison
decision, which prevents linearity errors or missing codes.
Figure 50 shows a settling measurement circuit for evaluating
recovery from an output current transient. An output disturbing
current generator provides the transient change in output load
current of 1 mA.
+15
V
+15V
1.5kΩ
1N4148
220Ω
1.8kΩ
2N3904
1kΩ
*
*
T
TL INPUT
+15V
2N2907
7A13 PLUG-IN
7A13 PLUG-IN
300pF
1/2
OP249
+
1kΩ
|V
REF
|
ΔI
OUT
=
–15V
0.1µF
0.1µF
0.1µF
10µF
V
REF
0.01µF
1kΩ
0.47µF
3
2
8
1
4
*
DECOUPLE CLOSE TOGETHER ON GROUND
PLANE WITH SHORT LEAD LENGTHS.
00296-050
Figure 50. Transient Output Impedance Test Fixture
As seen in Figure 51, the OP249 has an extremely fast recovery
of 247 ns (to 0.01%) for a 1 mA load transient. The performance
makes it an ideal amplifier for data acquisition systems.
10
0%
100
90
100ns2V2mV
247.4ns
OP249
Rev. G | Page 18 of 20
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.055 (1.40)
MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
14
58
Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
OP249AZ −55°C to +125°C 8-Lead CERDIP Q-8
OP249FZ −40°C to +85°C 8-Lead CERDIP Q-8
OP249GP −40°C to +85°C 8-Lead PDIP N-8
OP249GPZ −40°C to +85°C 8-Lead PDIP N-8
OP249GS −40°C to +85°C 8-Lead SOIC_N R-8
OP249GS-REEL −40°C to +85°C 8-Lead SOIC_N R-8
OP249GS-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
OP249GSZ −40°C to +85°C 8-Lead SOIC_N R-8
OP249GSZ-REEL −40°C to +85°C 8-Lead SOIC_N R-8
OP249GSZ-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8
1 Z = RoHS Compliant Part.
For military processed devices, see the standard microcircuit drawings (SMD) available at www.dscc.dla.mil/programs/milspec/default.asp.
Table 7.
SMD Part Number Analog Devices, Inc. Equivalent
5962-9151901M2A OP249ARCMDA
5962-9151901MPA OP249AZMDA
OP249
Rev. G | Page 19 of 20
NOTES
OP249
Rev. G | Page 20 of 20
NOTES
©1989–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00296-0-4/10(G)
