Figure 9.1.1 An Un-illuminated Seven-Segment Display and Nine Illumination Patterns Corresponding to Decimal Digits
The anodes of the seven LEDs forming each digit are tied together into one “common anode” circuit node, but the LED cathodes remain separate,
as shown in Fig 18. The common anode signals are available as eight “digit enable” input signals to the 8-digit display. The cathodes of similar
segments on all four displays are connected into seven circuit nodes labeled CA through CG. For example, the eight “D” cathodes from the eight
digits are grouped together into a single circuit node called “CD.” These seven cathode signals are available as inputs to the 8-digit display. This
signal connection scheme creates a multiplexed display, where the cathode signals are common to all digits but they can only illuminate the
segments of the digit whose corresponding anode signal is asserted.
To illuminate a segment, the anode should be driven high while the cathode is driven low. However, since the Nexys A7 uses transistors to drive
enough current into the common anode point, the anode enables are inverted. Therefore, both the AN0..7 and the CA..G/DP signals are driven low
when active.
Figure 9.1.2 Common Anode Circuit Node
A scanning display controller circuit can be used to show an eight-digit number on this display. This circuit drives the anode signals and
corresponding cathode patterns of each digit in a repeating, continuous succession at an update rate that is faster than the human eye can detect.
Each digit is illuminated just one-eighth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the
digit appears continuously illuminated. If the update, or “refresh”, rate is slowed to around 45Hz, a flicker can be noticed in the display.
For each of the four digits to appear bright and continuously illuminated, all eight digits should be driven once every 1 to 16ms, for a refresh
frequency of about 1 KHz to 60Hz. For example, in a 62.5Hz refresh scheme, the entire display would be refreshed once every 16ms, and each digit
would be illuminated for 1/8 of the refresh cycle, or 2ms. The controller must drive low the cathodes with the correct pattern when the
corresponding anode signal is driven high. To illustrate the process, if AN0 is asserted while CB and CC are asserted, then a “1” will be displayed in
digit position 1. Then, if AN1 is asserted while CA, CB, and CC are asserted, a “7” will be displayed in digit position 2. If AN0, CB, and CC are driven for
4ms, and then AN1, CA, CB, and CC are driven for 4ms in an endless succession, the display will show “71” in the first two digits. An example timing
diagram for a four-digit controller is shown in Figure 9.1.3.
Figure 9.1.3 Four Digit Scanning Display Controller Timing Diagram
The Nexys A7 board contains two tri-color LEDs. Each tri-color LED has three input signals that drive the cathodes of three smaller internal LEDs:
one red, one blue, and one green. Driving the signal corresponding to one of these colors high will illuminate the internal LED. The input signals
are driven by the FPGA through a transistor, which inverts the signals. Therefore, to light up the tri-color LED, the corresponding signals need to be
driven high. The tri-color LED will emit a color dependent on the combination of internal LEDs that are currently being illuminated. For example, if
the red and blue signals are driven high, and green is driven low, the tri-color LED will emit a purple color.
Note: Digilent strongly recommends the use of pulse-width modulation (PWM) when driving the tri-color LEDs (for information on PWM, see
section 15.1 Pulse Density Modulation (PDM)). Driving any of the inputs to a steady logic ‘1’ will result in the LED being illuminated at an
uncomfortably bright level. You can avoid this by ensuring that none of the tri-color signals are driven with more than a 50% duty cycle. Using
PWM also greatly expands the potential color palette of the tri-color led. Individually adjusting the duty cycle of each color between 50% and 0%
causes the different colors to be illuminated at different intensities, allowing virtually any color to be displayed.
The Pmod ports are arranged in a 2×6 right-angle, and are 100-mil female connectors that mate with standard 2×6 pin headers. Each 12-pin Pmod
port provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Figure 10.1. The VCC and
Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without
9.2 Tri-Color LED
10 Pmod Ports