MO SEL VITELIC
1
V43658R04V(L)
3.3 VOLT 8M x 64 LOW PROFILE
UNBUFFERED SDRAM MODULE
PRELIMINARY
V43658R04V(L) Rev. 1.0 October 2001
Features
■168 Pin Unbuffered 8,388,608 x 64 bit
Oganization SDRAM DIMM
■Utilizes High Performance 128 Mbit, 8M x 16
SDRAM in TSOPII-54 Packages
■Fully PC Board Layout Compatible to INTEL’S
Rev 1.0 Module Specification
■Single +3.3V (± 0.3V) Power Supply
■Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
■Auto Refresh (CBR) and Self Refresh
■All Inputs, Outputs are LVTTL Compatible
■4096 Refresh Cycles every 64 ms
■Serial Present Detect (SPD)
■SDRAM Performance
Description
The V43658R04V(L) memory module is
organized 8,388,608 x 64 bits in a 168 pin dual in
line memory module (DIMM). The 8M x 64 memory
module uses 4 Mosel-Vitelic 8M x 16 SDRAM. The
x64 modules are ideal for use in high performance
computer systems where increased memory
density and fast access times are required.
Part Number Speed
Grade Configuration
V43658R04VXTG-75L -75, CL=3
(133 MHz) 8M x 64
V43658R04VXTG-75PCL -75PC, CL=2,3
(133 MHz) 8M x 64
V43658R04VXTG-10PCL -10PC, CL=2,3
(100 MHz) 8M x 64
2
V43658R04V(L) Rev. 1.0 October 2001
MO SEL VITELIC
V43658R04V(L)
Pin Configurations (Front Side/Back Side)
Notes:
* These pinsare not used in this module.
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VSS
I/O1
I/O2
I/O3
I/O4
VCC
I/O5
I/O6
I/O7
I/O8
I/O9
VSS
I/O10
I/O11
I/O12
I/O13
I/O14
VCC
I/O15
I/O16
CBO*
CB1*
VSS
NC
NC
VCC
WE
DQM0
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
DQM1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10(AP)
BA1
VCC
VCC
CLK0
VSS
DU
CS2
DQM2
DQM3
DU
VCC
NC
NC
CB2*
CB3*
VSS
I/O17
I/O18
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O19
I/O20
VCC
I/O21
NC
DU
CKE1
VSS
I/O22
I/O23
I/O24
VSS
I/O25
I/O26
I/O27
I/O28
VCC
I/O29
I/O30
I/O31
I/O32
VSS
CLK2
NC
WP
SDA
SCL
VCC
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
VSS
I/O33
I/O34
I/O35
I/O36
VCC
I/O37
I/O38
I/O39
I/O40
I/O41
VSS
I/O42
I/O43
I/O44
I/O45
I/O46
VCC
I/O47
I/O48
CB4*
CB5*
VSS
NC
NC
VCC
CAS
DQM4
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
DQM5
CS1
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
NC
VSS
CKE0
CS3
DQM6
DQM7
DU
VCC
NC
NC
CB6*
CB7*
VSS
I/O49
I/O50
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
I/O51
I/O52
VCC
I/O53
NC
DU
NC
VSS
I/O54
I/O55
I/O56
VSS
I/O57
I/O58
I/O59
I/O60
VCC
I/O61
I/O62
I/O63
I/O64
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Pin Names
A0–A11 Address Inputs
I/O1–I/O64 Data Inputs/Outputs
RAS Row Address Strobe
CAS Column Address Strobe
WE Read/Write Input
BA0, BA1 Bank Selects
CKE0, CKE1 Clock Enable
CS0–CS3Chip Select
CLK0–CLK3 Clock Input
DQM0–DQM7 Data Mask
VCC Power (+3.3 Volts)
VSS Ground
SCL Clock for Presence Detect
SDA Serial Data OUT for Presence
Detect
SA0–A2 Serial Data IN for Presence
Detect
CB0–CB7 Check Bits (x72 Organization)
NC No Connection
DU Don’t Use
MO SEL VITELIC
V43658R04V(L)
3
V43658R04V(L) Rev.1.0 October 2001
Part Number Information
Block Diagram
V 4 3 65 8 R 0 4 V X T G -XX (L)
SDRAM
3.3V WIDTH
DEPTH
168-pins unbuffered DIMM
X16 COMPONENT
REFRESH
RATE 4K 4BANKS
LVTTL
COMPONENT
REV LEVEL
COMPONENT
PACKAGE, T=TSOP
LEAD FINISH
G=GOLD
SPEED
75PC = PC133 CL2,3
MOSEL VITELIC
MANUFACTURED 75 = PC133 CL3
10PC = PC100 CL2 Low Profile
Module
DQM0
I/O1–I/O8
CS0
CS2
WE
WE
WE: SDRAM D0–D3
CKE: SDRAM D0–D3
RAS: SDRAM D0–D3
A(11:0): SDRAM D0–D3
BA0, BA1: SDRAM D0–D3
CKE0
RAS
CAS
WE
A(11:0)
BA0, BA1
CAS: SDRAM D0–D3
C0–C7
Two 0.1µF capacitors
per each SDRAM
D0–D3
D0–D3
VCC
VSS
SCL0
SA2
SA1
SA0
CLK0/2
SDA
WP
D0/D2
D1/D3
E2PROM SPD (256 WORD X 8 BITS)
47K
10
LDQM
I/O1–I/O8
UDQM
I/O9–I/O16
CS
D0
10
DQM1
I/O9–I/O16 10
DQM4
I/O33–I/O40
WE
LDQM
I/O1–I/O8
UDQM
I/O9–I/O16
CS
D2
10
DQM5
I/O41–I/O48 10
DQM2
I/O17–I/O24
WE
LDQM
I/O1–I/O8
UDQM
I/O9–I/O16
CS
D1
10
DQM3
I/O25–I/O32 10
DQM6
I/O49–I/O56
WE
LDQM
I/O1–I/O8
UDQM
I/O9–I/O16
CS
D3
10
DQM7
I/O57–I/O64 10
CLK1/3
10pF
10
15pF
4
V43658R04V(L) Rev. 1.0 October 2001
MO SEL VITELIC
V43658R04V(L)
Serial Presence Detect Information
A serial presence detect storage device -
E2PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintotheE
2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
SPD Table
Byte Num-
ber Function Described SPD Entry Value
Hex Value
-75PC -75 -10PC
0 Number of SPD bytes 128 80 80 80
1 Total bytes in Serial PD 256 08 08 08
2MemoryType SDRAM 040404
3 Number of Row Addresses (without BS bits) 12 0C 0C 0C
4 Number of Column Addresses (for x16
SDRAM) 9 090909
5 Number of DIMM Banks 1 01 01 01
6 Module Data Width 64 40 40 40
7 Module Data Width (continued) 0 00 00 00
8 Module Interface Levels LVTTL 01 01 01
9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0
10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60
11 Dimm Config (Error Det/Corr.) none 00 00 00
12 Refresh Rate/Type Self-Refresh, 15.6µs808080
13SDRAMwidth,Primary x16 101010
14 Error Checking SDRAM Data Width n/a / x8 00 00 00
15 MinimumClockDelayfromBacktoBackRan-
dom Column Address tccd =1CLK 010101
16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F
17 Number of SDRAM Banks 4 04 04 04
18 Supported CAS Latencies CL = 3, 2 06 06 06
19 CS Latencies CS Latency=0010101
20 WE Latencies WL=0 010101
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E
23 Minimum Clock Cycle Time at CAS Latency =
27.5 ns/10.0 ns 75 A0 A0
24 Maximum Data Access Time from Clock for
CL = 2 5.4 ns/6.0 ns 54 60 60
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00
26 Maximum Data Access Time from Clock at CL
=1 Not Supported 00 00 00
27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14
MO SEL VITELIC
V43658R04V(L)
5
V43658R04V(L) Rev.1.0 October 2001
DC Characteristics
TA=0°Cto70°C; VSS =0V;V
DD,V
DDQ =3.3V±0.3V
28 Minimum Row Active to Row Active Delay
tRRD
14 ns/15 ns/16 ns 0E 0F 10
29 Minimum RAS to CAS Delay tRCD 15 ns/20 ns 0F 14 14
30 Minimum RAS Pulse Width tRAS 42 ns/45 ns 2A 2D 2D
31 Module Bank Density (Per Bank) 64 MByte 10 10 10
32 SDRAM Input Setup Time 1.5 ns/2.0 ns 15 15 20
33 SDRAM Input Hold Time 0.8 ns/1.0 ns 08 08 10
34 SDRAM Data Input Setup Time 1.5 ns/2.0 ns 15 15 20
35 SDRAM Data Input Hold Time 0.8 ns/1.0 ns 08 08 10
62-61 Superset Information (May be used in Future) 00 00 00
62 SPD Revision Revision 2/1.2 02 02 12
63 Checksum for Bytes 0 - 62 D1 16 84
64 Manufacturer’s JEDEC ID Code Mosel Vitelic 40 40 40
65-71 Manufacturer’s JEDEC ID Code (cont.) 00 00 00
72 Manufacturing Location
73-90 Module Part Number (ASCII) V43658R04V(L)
91-92 PCB Identification Code
93 Assembly Manufacturing Date (Year)
94 Assembly Manufacturing Date (Week)
95-98 Assembly Serial Number
99-125 Reserved 00 00 00
126 Intel Specification for Frequency 64 64 64
127 Supported frequency
128+ Unused Storage Location 00 00 00
Symbol Parameter
Limit Values
UnitMin. Max.
VIH Input High Voltage 2.0 VCC+0.3 V
VIL Input Low Voltage –0.5 0.8 V
VOH Output High Voltage (IOUT =–2.0 mA) 2.4 —V
VOL Output Low Voltage (IOUT =2.0mA) —0.4 V
SPD (Continued)Table
Byte Num-
ber Function Described SPD Entry Value
Hex Value
-75PC -75 -10PC
6
V43658R04V(L) Rev. 1.0 October 2001
MO SEL VITELIC
V43658R04V(L)
Capacitance
TA=0°Cto70°C; VDD =3.3V± 0.3V, f = 1 MHz
Absolute Maximum Ratings
II(L) Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V) –40 40 µA
IO(L) Output leakage current
(DQ is disabled, 0V < VOUT <V
CC)–40 40 µA
Symbol Parameter
Limit Values
UnitMax. 8M x 64
CI1 Input Capacitance (A0 to A11, RAS,CAS,WE)60pF
CI2 Input Capacitance (CS0-CS3)30pF
CICL Input Capacitance (CLK0-CLK3) 22 pF
CI3 Input Capacitance (CKE0, CKE1) 50 pF
CI4 Input Capacitance (DQM0-DQM7) 15 pF
CIO Input/Output Capacitance (I/O1-I/064) 15 pF
CSC Input Capacitance (SCL, SA0-2) 8 pF
CSD Input/Output Capacitance (SA0-SA2) 10 pF
Parameter Max. Units
VoltageonVDDSupplyRelativetoV
SS -1 to 4.6 V
VoltageonInputRelativetoV
SS -1 to 4.6 V
Operating Temperature 0to+70 °C
Storage Temperature -55to125 °C
Power Dissipation 4W
Symbol Parameter
Limit Values
UnitMin. Max.
MO SEL VITELIC
V43658R04V(L)
7
V43658R04V(L) Rev.1.0 October 2001
Notes:
1. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input
signals are changed one time during tCK.
2. These parameter depend on output loading. Specified values are obtained with output open.
Operating Currents
TA=0°Cto70°C, VCC =3.3V±0.3V (Recommended operating conditions otherwise noted)
Symbol Parameter & Test Condition
Max.
Unit Note
-75PC
/-75 -10PC
ICC1 Operating Current
tRC =t
RCMIN.,t
CK=t
CKMIN.
Active-precharge command cycling,
without Burst Operation
1 bank operation 680 600 mA 7
ICC2P Precharge Standby Current in Power Down Mode
CS=VIH,CKE≤VIL(max)
tCK =min. 6 6 mA 7
ICC2PS tCK = Infinity 4 4 mA 7
ICC2N Precharge Standby Current in Non-Power Down Mode
CS=VIH,CKE≥VIL(max)
tCK = min. 180 140 mA
ICC2NS tCK = Infinity 20 20 mA
ICC3N No Operating Current
tCK =min,CS=V
IH(min)
bank ; active state ( 4 banks)
CKE>= VIH(MIN.) 220 180 mA
ICC3P CKE <= VIL(MAX.)
(Power down mode) 40 40 mA
ICC4 Burst Operating Current
tCK =min
Read/Write command cycling
440 360 mA 7,8
ICC5 Auto Refresh Current
tCK =min
Auto Refresh command cycling
1000 840 mA 7
ICC6 Self Refresh Current
Self Refresh Mode, CKE=<0.2V 66mA
L-version 3.2 3.2 mA
8
V43658R04V(L) Rev. 1.0 October 2001
MO SEL VITELIC
V43658R04V(L)
AC Characteristics 3,4
TA=0°to 70°C; VSS =0V;V
CC =3.3V±0.3V, tT=1ns
# Symbol Parameter
Limit Values
Unit Note
-75PC -75 -10PC
Min. Max. Min. Max. Min. Max.
Clock and Clock Enable
1t
CK Clock Cycle Time
CAS Latency = 3
CAS Latency = 2 7.5
7.5 7.5
10 10
10 ns
ns
2f
CK System frequency
CAS Latency = 3
CAS Latency = 2 –
–133
133 –
–133
100 –
–100
100 MHz
MHz
3t
AC Clock Access Time
CAS Latency = 3
CAS Latency = 2 –
–5.4
6–
–5.4
6–
–6
6ns
ns
4,5
4t
CH Clock High Pulse Width 2.5 –2.5 –3–ns 6
5t
CL Clock Low Pulse Width 2.5 –2.5 –3–ns 6
6t
CS Input Setup time 1.5 –1.5 –2–ns 7
7t
CH Input Hold Time 0.8 –0.8 –1–ns 7
8t
CKSP CKE Setup Time (Power down mode) 2 –2–2–ns 8
9t
CKSR CKE Setup Time (Self Refresh Exit) 8 –8–8–ns 9
10 tTTransition time (rise and fall) 1 –1–1–ns
Common Parameters
11 tRCD RAS to CAS delay 15 –20 –20 –ns
12 tRC Cycle Time 70 120k 70 120k 70 120k ns
13 tRAS Active Command Period 42 –45 –45 –ns
14 tRP Precharge Time 15 –20 –20 –ns
15 tRRD Bank to Bank Delay Time 14 –15 –20 –ns
16 tCCD CAS to CAS delay time (same bank) 1–1–1–CLK
Refresh Cycle
17 tSREX Self Refresh Exit Time 10 –10 –10 –ns 9
18 tREF Refresh Period (4096 cycles) 64 –64 –64 –ms 8
Read Cycle
19 tOH Data Out Hold Time 3 –3–3–ns 4
20 tLZ Data Out to Low Impedance Time 0 –0–0–ns
21 tHZ Data Out to High Impedance Time 3 7.5 3 7.5 3 8 ns 10
22 tDQZ DQM Data Out Disable Latency 2 –2–2–CLK
Write Cycle
23 tDPL Data input to Precharge (write recovery) 1 –1–1–CLK
24 tDAL Data In to Active/refresh 5 –5–5–CLK 11
25 tDQW DQM Write Mask Latency 0 –0–0–CLK
MO SEL VITELIC
V43658R04V(L)
9
V43658R04V(L) Rev.1.0 October 2001
Notes:
1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No
Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module
bank.
2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).
3. All AC characteristics are shown for device level.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed
by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.
4. ACtiming tests have VIL =0.4VandVIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition
time is measured between VIH and VIL. All AC measurements assume tT= 1 ns with the AC output load circuit
shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with
a input signal of 1V / ns edge rate between 0.8V and 2.0V.
5. If clock rising time is longer than 1 ns, a time (tT/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5V
7. If tTis longer than 1 ns, a time (tT-1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be
given to “wake-up”the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high.
Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command
is registered.
10. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels.
11. tDAL is equivalent to tDPL +t
RP.
1.4V
1.4V
tSETUP tHOLD
tAC tAC
tLZ tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+1.4V
50 Ohm
2.4V
0.4V
tT
tCL
tCH
I/O
Measurement conditions for
tac and toh
50 pF
10
V43658R04V(L) Rev. 1.0 October 2001
MO SEL VITELIC
V43658R04V(L)
Package Diagram
SDRAM DIMM LOW-PROFILE Module Package
0.250
(6.350)
Detail A
0.123 ± .005
(3.125 ± .125)
0.250
(6.350)
Detail B
0.123 ± 0.005
(3.125 ± 0.125)
0.079 ± 0.004
(2.000 ± 0.100)
0.079 ± 0.004
(2.000 ± 0.100)
Tolerances : ± 0.005(.13) unless otherwise specified
0.100 Max
0.050 ± 0.0039
(1.270 ± 0.10)
0.200 Min
(5.08 Min)
(2.54 Max)
5.250
5.014
Units : Inches (Millimeters)
R 0.079
(R 2.000)
0.250
(6.350)
1.450
(36.830)
2.150
(54.61)
0.118
(3.000)
0.350
0.100 Min
(2.540 Min)
0.700
(17.780)
.118DIA ± 0.004
(3.000DIA ± 0.100)
(8.890)
A B C
0.250
(6.350)
.450
(11.430) 4.550
(115.57)
0.157 ± 0.004
(4.000 ± 0.100)
0.089
(2.26)
(127.350)
(133.350)
1.000
(25.40)
0.118
(3.000)
0.050
0.008 ± 0.006
(0.200 ± 0.150)
(1.270)
0.100 Min
(2.540 Min)
Detail C
0.039 ± 0.002
(1.000 ± 0.050)
MO SEL VITELIC
V43658R04V(L)
11
V43658R04V(L) Rev.1.0 October 2001
CL = 3 or 2 (CLK)
tRCD = 3 or 2 (CLK)
tRP = 3 or 2 (CLK) tAC = 5.4 ns
XXXU
UNBUF FERED DIMM
PC133 54
JEDEC SPD Revision 2
2
V436616R24XXX-XX 128MB CLX
PC133U-XXX-542-A
XXXX-XXXXXX
Assembly in Taiwan
A
Gerber file ® PC100 x 16 Based
-- -
Part Number
Module Density
DIMM manufacture date code
CAS Latency
2 = CL2
3 = CL3
Criteria of PC100 or PC133
(refer to MVI datasheet)
V436516R04VXXX-XX(L)128MB CLX
16
V43658R04VXXX-XX(L) 64MB CLX
XXXX-XXXXXX
Lable Information
MO SEL VITELIC
WORLDWIDE OFFICES V43658R04V(L)
© Copyright , MOSEL VITELIC Inc. Printed in U.S.A.
MOSEL VITELIC
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461
The information in this document is subject to change without
notice.
MOSEL VITELIC makes no commitment to update or keep cur-
rent the information contained in this document. No part of this
document may be copied or reproduced in any form or by any
means without the prior written consent of MOSEL-VITELIC.
MOSEL VITELIC subjects its products to normal quality control
sampling techniques which are intended to provide an assurance
of high quality products suitable for usual commercial applica-
tions. MOSEL VITELIC does not do testing appropriate to provide
100% product quality assurance and does not assume any liabil-
ity for consequential or incidental arising from any use of its prod-
ucts. If such products are to be used in applications in which
personal injury might occur from failure, purchaser must do its
own quality assurance testing appropriate to such applications.
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