4
V43658R04V(L) Rev. 1.0 October 2001
MO SEL VITELIC
V43658R04V(L)
Serial Presence Detect Information
A serial presence detect storage device -
E2PROM - is assembled onto the module. Informa-
tion about the module configuration, speed, etc. is
writtenintotheE
2PROM device during module pro-
duction using a serial presence detect protocol (I2C
synchronous 2-wire bus)
SPD Table
Byte Num-
ber Function Described SPD Entry Value
Hex Value
-75PC -75 -10PC
0 Number of SPD bytes 128 80 80 80
1 Total bytes in Serial PD 256 08 08 08
2MemoryType SDRAM 040404
3 Number of Row Addresses (without BS bits) 12 0C 0C 0C
4 Number of Column Addresses (for x16
SDRAM) 9 090909
5 Number of DIMM Banks 1 01 01 01
6 Module Data Width 64 40 40 40
7 Module Data Width (continued) 0 00 00 00
8 Module Interface Levels LVTTL 01 01 01
9 SDRAM Cycle Time at CL=3 7.5 ns/10.0 ns 75 75 A0
10 SDRAM Access Time from Clock at CL=3 5.4 ns/6.0 ns 54 54 60
11 Dimm Config (Error Det/Corr.) none 00 00 00
12 Refresh Rate/Type Self-Refresh, 15.6µs808080
13SDRAMwidth,Primary x16 101010
14 Error Checking SDRAM Data Width n/a / x8 00 00 00
15 MinimumClockDelayfromBacktoBackRan-
dom Column Address tccd =1CLK 010101
16 Burst Length Supported 1, 2, 4, 8 0F 0F 0F
17 Number of SDRAM Banks 4 04 04 04
18 Supported CAS Latencies CL = 3, 2 06 06 06
19 CS Latencies CS Latency=0010101
20 WE Latencies WL=0 010101
21 SDRAM DIMM Module Attributes Non Buffered/Non Reg. 00 00 00
22 SDRAM Device Attributes: General Vcc tol ± 10% 0E 0E 0E
23 Minimum Clock Cycle Time at CAS Latency =
27.5 ns/10.0 ns 75 A0 A0
24 Maximum Data Access Time from Clock for
CL = 2 5.4 ns/6.0 ns 54 60 60
25 Minimum Clock Cycle Time at CL = 1 Not Supported 00 00 00
26 Maximum Data Access Time from Clock at CL
=1 Not Supported 00 00 00
27 Minimum Row Precharge Time 15 ns/20 ns 0F 14 14