HITACHI/ LOGIC/ARRAYS/M B7E D MM 4496203 00244339 O02? MPHITe HM514260A/AL, HM51S4260A/AL Series _ 262,144-Word x 16-Bit Dynamic Random Access Memory @ DESCRIPTION @ FEATURES The Hitachi HM514260A/AL are CMOS dynamic RAM or- Single 5V (+ 10%) ganized as 262,144-word x 16-bit. HM514260A/AL have re- High Speed alized higher density, higher performance and various func- Access Time ............. 70 ns/80 ns/100 ns (max) tions by employing 0.8 ~m CMOS process technology and Low Power Dissipation some new CMOS circuit design technologies. The Active Mode ....... 825 mW/770 mW/688 mW (max) HM514260A/AL offer fast page mode as a high speed ac- Standby Mode ............ 11 mW (max) cess mode. 4.1 mW (max) (L-Version) Multiplexed address input permits the HM514260A/AL to * Fast Page Mode Capability be packaged in standard 400 mil 40-pin plastic SOJ, stan- 512 Refresh Cycles ..........-.. eee 8 ms dard 475 mil 40-pin plastic ZIP and standard 400 mil 40-pin 128 ms (L-Version) plastic TSOPII. 2 TAS Byte Control Internal refresh timer enables HM51S4260A/AL self re- * 2 Variations of Refresh fresh operation. RAS Only Refresh CAS Before RAS Refresh * Battery Back-up Operation (L-Version) * Self-Refresh Operation (HM51S4260A/AL) @ ORDERING INFORMATION Part No. Access Time Package Part No. Access Time Package HM514260AJ-7 70ns 400 mil 40-pin HMS5184260AJ-7 70 ns 400 mil 40-pin HM514260AJ-8 80 ns Plastic SOJ HM51S84260AJ-8 80ns Plastic SOJ HMS14260AJ-10 100 ns (CP-40DA) HMS1S4260AJ-10 100 ns (CP-40DA) HM514260AZ-7 70 ns 475 mil 40-pin HMS5184260AZ-7 70 ns 475 mil 40-pin HMS14260AZ-8 80 ns Plastic ZIP HMS51S4260AZ-8 80 ns Plastic ZIP HMS514260AZ-10 100 ns (ZP-40) HM5154260AZ-10 100 ns (ZP-40) HMS14260ATT-7 70 ns 400 mil 40-pin HMS51S4260ATT-7 70 ns 400 mil 40-pin HM514260ATT-8 80 ns Plastic TSOPII HM51S4260ATT-8 80 ns Plastic TSOP! HMS514260ATT-10 100 ns (TTP-40D8) HM5184260ATT-10 100 ns (TTP-40DB) HM514260ARR-7 70 ns 400 mit 40-pin HM51S4260ARR-7 70 ns 400 mil 40-pin HM514260ARR-8 80 ns Plastic TSOPII HM51S4260ARR-8 80 ns Plastic TSOPH HM514260ARR-10 100 ns (TTP-40DB) HMS51S4260ARR-10 100 ns (TTP-40DB) HM514260ALJ-7 70 ns 400 mil 40-pin HMS51S4260ALJ-7 70 ns 400 mil 40-pin HM514260ALJ-8 80 ns Plastic SOJ HMS51S4260ALJ-8 80 ns Plastic SOJ HM514260ALJ-10 100 ns (CP-40DA) HMS51S4260ALJ-10 100 ns (CP-40DA) HM514260ALZ-7 70 ns 475 mil 40-pin HM51S4260ALZ-7 70 ns 475 mil 40-pin HM514260ALZ-8 80 ns Plastic ZIP HM51S4260ALZ-8 80 ns Plastic ZIP HMS514260ALZ-10 100 ns (ZP-40) HM51S4260ALZ-10 100 ns (ZP-40) HMS14260ALTT-7 70 ns 400 mil 40-pin HM51S4260ALTT-7 70 ns 400 mil 40-pin HM514260ALTT-8 80 ns Plastic TSOPIE HM51S4260ALTT-8 80 ns Plastic TSOPIT HMS514260ALTT-10 100 ns (FTP-40DB) HM5iS4260ALTT-10 100 ns (TTP-40DB) HM514260ALRR-7 70 ns 400 mil 40-pin HMS51S4260ALRR-7 70 ns 400 mil 40-pin HMS514260ALRR-8 80 ns Plastic TSOPII HMS51S4260ALRR-8 80 ns Plastic TSOPII HM514260ALRR-10 100 ns (TTP-40DB) HMS1S4260ALRR-10 100 ns (TTP-40DB) HITACHI 124 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300HITACHI/ LOGIC/ARRAYS/M &7E D MM 4496203 0024434 Th3 ME HIT2 HM514260A/AL, HM51S4260A/AL Series @ PIN ARRANGEMENT HM514260AJ/ALI Series HMS514260AZ/ALZ Series HM514260ATT/ALTT Series HMS51S4260AJ/ALJ Series HM51S4260AZ/ALZ Series HMS51S4260ATT/ALTT Series Vee C1 4000 Veg | Vec C10 40[ Vss voo C2 39[0 voIs voo 2 ; Vor voo C2 39[Jv01s vor C]3 380 vo14 vou 4 5 vor (3 sep rors vo2 C4 37) vo13 vor 6 7 ves vee SB yor2 vo3 Cs 36 vou WO 8 9 O15 Vee 16 351 Ves Vec Cle 350] Vs ss, 4 11 Vee vos C17 aatjvon wos 17 3419 vor! vO2 14 13 01 vos Cla asfQvoi0 vos Cle 33[7) voto Vic 46 15/03 vos Cle s2{7) vos vos C9 3210 vos ce 17 O04 vo7 C10 31{9 voa YOS 18 vo7 C110 311 vos vO7 20 19 06 nc (11 30 NC NC 22 21 NC d Ln NC Cie 29() LCAS RAS 24 . Ne Ne Clie wo CeRE we (13 281) UCAS AO 26 ~ Cc 27 Al we (13 28) Ucas RASC 14 271) OE A228 20 A RasCha zoe 3 No (115 26(5 As Vee 30 31 Ves ne C15 2s As Ao (16 250) A7 A432 33 AS ao C16 25, 7 Ail (17 24) AG 46 HK 35 A7 ar (hz 24[T1A6 a2 Chia 230) AS Ag __ 36 37 OF az 18 5d = Az C9 221 AS Ne se 39 [CAS ee oe ia Vec (20 211 Vss 00134~1 00134--2 T Vi 00134-3 (Top View) (Bottom View) (Top View) HM514260ARR/ALRR Series @ PIN DESCRIPTION HMS51S4260ARR/ALRR Series - - Pin Name Function Vss (10 4019 Voc Ag-Ag Address Input yois 2 3919 yoo Row Address Ag-Ag vos (3 38D vor Column Address Ag~Ag vo13s (4 370 vo2 Refresh Address Ag-Ag voi2 Cs 360) vos 1/09-1/015 Data-in/Data-out vss q 6 35 5 Vee RAS Row Address Strobe voi 7 340 vos vor Gs 3300 vos UCAS/LCAS Column Address Strobe vog 9 321 vos WE Read/Write Enable vos (10 310) v07 OE Output Enable Vcc Power ( + 5V) Vv. Ground nc (11 301 nc ss LCAS CJ 12 29[) NC UCAS CJ 13 2800 WE SE Cia 270) RAS as (15 260) nc a7 C16 250) Ao 46 017 247 a1 as C18 23) a2 Aa C19 22D) a3 ss (20 2100 vee 00134-4 (Top View) HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 125yey Aesny Aoweyy 4 952 Row Decoder} Jeposeg UUNjOD Sg OV vey Aeiny Aoway 4 9Sz v Selector wey Aesy Aowey 9SZ A6,A7,A8| Oecoder| itt wey Aeuy Aowey 4 95z Row |Row 0 Jepo2eG UWNIOD 9 SNE O/ ey Aeiny Aoweyy 4 952 yey Aes Mowey 952 JE9podaq UWNIOD 2 Ng OVI Selector tt Selector vew Avary Aowey 4 952 Decoder Row seporeg UWWNOD 9 Sng OM ey Aeuy Aiowey 952 mm 4496203 0024435 ATT MB HITe yNaID yeseydueg Address A4,AS lund jeseydued rey Aevy Moway 4 9Sz2 Peripheral Circuit Row Decoder sepozeg UWNjOD F Sg OI ey Aesy Aoweyy 952 A0,A1,A2,A3 | itit wey Aeny Aowey 95Z Selector Jeposeg UWnNjOD SNg OVI ley Aesry Aowoyy 4 952 s8poreg WUUN/OD 9 SNg O/| wep Aeswsy Aowey 4 952 ey Aeny Aoway y 9S5z IF [ete ted CO | Address rey Aeuy Mowoy 4 952 Decode HM514260A/AL, HM51S4260A/AL Series @ BLOCK DIAGRAM sepogeg UWINIOD SNg Oy| rey Aeny Aowey 95z [os [Ee vor J HITACHI/ LOGIC/ARRAYS/M BE D 0134-5 HITACHE Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 126HITACHI/ LOGIC/ARRAYS/M b?E D MM@ 44964203 00244364 836 MB HIT2 HM514260A/AL, HM51S4260A/AL Series @ TRUTH TABLE Inputs Vo . a = = Operation RAS LCAS UCAS WE OE 1/Q9-1/07 1/0g-1/O015 H H H H H High-Z High-Z Standby L H H H H High-Z High-Z Refresh L L H H L Dout High-Z Lower Byte Read L H L H L High-Z Dout Upper Byte Read L L L H L Dout Dout Word Read L L H L H Din Dont Care Lower Byte Write L H L L H Dont Care Din Upper Byte Write L L L L H D, Din Word Write L L L H H High-Z High-Z HtoL L H - High-Z High-Z CBR Refresh HtoL H L - _ High-Z High-Z or HtoL L L _ High-Z High-Z Self Refresh @ ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on Any Pin Relative to Vs Vr ~10to +7.0 v Supply Voltage Relative to Vsg Vec 10to +7.0 v Short Circuit Output Current Tout 50 mA Power Dissipation Pr 1.0 Ww Operating Temperature Topr Oto +70 C Storage Temperature Tstg 55to + 125 c @ ELECTRICAL CHARACTERISTICS * Recommended DC Operating Conditions (Ta = Oto + 70C)2 Parameter Symbol Min Typ Max Unit Note Supply Voltage Vss 0 0 0 v Voc 4.5 5.0 5.5 Vv 1 Input High Voltage Vin 2.4 _ 6.5 Vv 1 Input Low (1/0 Pin) VIL 10 _ 0.8 Vv 1 Voltage (Others) Vit 2.0 = 0.8 v 1 Notes: 1. All voltage referenced to Vsg, 2. The supply voltage with all Vcc pins must be on the same level. The supply voltage with all Vgg pins must be on the same level. HITACHI Hitachi America, Ltd. * Hitachi Plaza e 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (41 5) 589-8300 127HITACHI/ LOGIC/ARRAYS/M &7E D MM 4Y49be03 O0e4437? P?e MB HITe HM514260A/AL, HM51S4260A/AL Series DC Electrical Characteristics (Ta = 0 to +70C, Voc = 5V 10%, Vgg = OV) HMS14260A/AL-7 | HM514260A/AL-8 | HM514260A/AL-10 Parameter | Symbol| HM51S4260A/AL-7 HMS51S4260A/AL-8 | HM51S4260A/AL-10 | Unit Test Conditions Note Min Max Min Max Min Max Operating RAS Cycling Current Icci _ 150 _ 140 - 125 mA | LCAS or UCAS Cycling 1,2 tre = min TTL Interface 2 _ 2 _ 2 mA | RAS, LCAS, UCAS = Vin Dout = High-Z Standby out s Current CMOS Interface Ioc2 _ 1 _ 1 _ 1 mA RAS, LCAS, UCAS, WE OE 2 Vcc 0.2V, Dout = High-Z CMOS Interface Standby c =e AG WE Current _ 200 200 200 pA RAS, ] LCAS, OE, WE (L-Version) UCAS 2 Vcc 0.2V, Dout = High-Z RAS Only = mn Refresh Current Iec3 _ 140 _ 130 _ 110 mA |tpc = min 2 RAS = Vin. Standby lees 5 _ 5 _ 5 | mA |ECAS or UCAS = Viz. 1 Current Dout = Enable CAS Before RAS Refresh Iece _ 140 _ 130 _ 110 mA }trc = min 2 Current Fast Page Mode = mi Current Tec? _ 130 _ 120 _ 110 mA |tpc = min 1,3 Battery Back-up Standby: CMOS Interface Current Dour = High-Z (Standby with Icocio _ 300 _ 300 _ 300 pA | CBR Refresh: trc = 250 ps 4 CBR Refresh) tras S | ys, LCAS, UCAS = Vit (L-Version) WE, OE = Vin Self-Refresh CMOS Interface Mode Current _ 1 _ 1 _ 1 mA | RAS, LCAS, UCAS < 0.2V (HMS51S4260A) 1 Dout = High-Z 1 Self-Refresh ce CMOS Interface Mode Current _ 200 200 200 pA | RAS, LCAS, UCAS < 0.2V (HMS51S4260AL) Dour = High-Z Input Leakage _ _ _ 7 Current Tur 10 10 10 10 10 10 pA jOV < Vin $ 6.5V Output Leakage _ _ _ OV < Vout S 6.5V Current ILo 10 10 10 10 10 10 pA Dout = Disable Output High . Voltage e Vou 24 Vec 214 Voc 24 Voc | V |HighIou = 5.0mA Output Low _ Voltage VoL 0 0.4 0 0.4 0 04 V | Low [guy = 4.2 mA Notes: 1. Ic depends on output load condition when the device is selected. cc max is specified at the output open condition. 1 2. Address can be changed < 1 time while RAS = Vj. 3. Address can be changed < 1 time while LCAS and UCAS = Vin. 4. Vin. 2 Voc 0.2V,0 < Viz $ 0.2V. Address can be changed = ! time while RAS = Vy. 5. All the Vcc pins shall be supplied with the same voltage. All the Vsg pins shall be supplied with the same voltage. HITACHE 128 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1 819 (415) 589-8300HITACHI/ LOGIC/ARRAYS/M b?7E D Me 449b6e03 G0e4438 09 ME HIT2 Capacitance (Ta = 25C, Voc = 5V 10%) HM514260A/AL, HM51S4260A/AL Series Parameter Symbol Typ Max Unit Note Input Capacitance (Address) Ch - pF Input Capacitance (Clocks) Cp _ pF Output Capacitance (Data-in, Data-out) Cryo pF 1,2 Notes: 1. Capacitance measured with Boonton 2. UCAS and UCAS = Vij to disable Dour. * AC Characteristics (T, = 0 to +70C, Voc = 5V +10%, Veg = OV)1. 14, 15, 17, 18 Test Conditions input rise and fall times: 5 ns Input timing reference levels: 0.8V, 2.4V Read, Write, Read-Modity-Write and Refresh Cycles (Common Parameters) Meter or effective capacitance measuring method. * Output load: 2 TTL gate + C_ (100 pF) (Including scope and jig) HMS14260A/AL-7 HM514260A/AL-8 HMS514260A/AL-10 Parameter Symbol |_HMS1S4260A/AL-7_ | HMS1S4260A/AL-8 | HMS1S4260A/AL-10 | Unit | Note Min Max Min Max Min Max Random Read or Write Cycle Time | tac 130 150 180 - ns RAS Precharge Time trp 50 7) _ 70 ns RAS Pulse Width tras 70 10000 80 10000 100 10000 ns CAS Pulse Width tcas 20 10000 20 10000 25 10000 | ns | 23 Row Address Setup Time tasR 0 0 _ 0 - ns Row Address Hold Time (RAH 10 _ 10 _ 15 _ ns Column Address Setup Time tasc 0 0 _ 0 - ns 19 Column Address Hold Time tcaH 15 - 15 _ 20 - ns 19 RAS to CAS Delay Time trop 20 50 20 60 25 75 ns 8 RAS to Column Address Delay Time | trap 15 35 15 40 20 55 ns 9 RAS Hold Time trsH 20 _ 20 25 ns CAS Hold Time tesy 70 _ 80 100 _ ns CAS to RAS Precharge Time tcrp 15 _ 15 _ 15 _ ns | 20,24 OE to Din Delay Time topp 20 20 25 _ ns OE Delay Time from Dj, tpz0 0 0 _ 0 ns CAS Setup Time from Dj, tozc 0 _ _ 0 _ ns Transition Time (Rise and Fall) ty 3 50 50 3 50 ns 7 Refresh Period tREF _ 8 - 8 _ 8 ms Refresh Period (L-Version) trRer 128 _ 128 _ 128 ms HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 129HITACHI LOGIC/ARRAYS/M bB?E D HM514260A/AL, HM51S4260A/AL Series Mm 4496203 00204439 SYS MBHITe Read Cycle HM514260A/AL-7 HM514260A/AL-8 HMS514260A/AL-10 Parameter Symbol HMS51S4260A/AL-7 HM51S4260A/AL-8 HMS1S4260A/AL-10 | Unit | Note Min Max Min Max Min Max Access Time from RAS tRAC 70 80 _ 100 ns 2,3 Access Time from CAS tcac _ 20 20 25 ns | 3,4,13 Access Time from Address taa - 35 - 40 _ 45 ns } 3,5,13 Access Time from OE toac = 20 _ 20 25 ns 23 Read Command Setup Time tres 0 0 _ 0 - ns 19 Read Command Hold Time to CAS | trcH 0 _ 0 _ 0 - ns 16, 19 Read Command Hold Time toRAS | tra 0 _ 0 = 0 _ ns 16 Column Address to RAS Lead Time | trav 35 40 ~ 45 _ ns Output Buffer Turn-off Time tOFF1 0 15 0 15 0 20 ns 6 Output Buffer Turn-off to OE torF2 0 15 0 15 0 20 ns 6 GAS to Dj, Delay Time tepp 15 _ 15 _ 20 _ ns Write Cycle HMS14260A/AL-7 HMS14260A/AL-8 HM514260A/AL-10 Parameter Symbol HMS5154260A/AL-7 HM51S4260A/AL-8 HM51S4260A/AL-10 | Unit | Note Min Max Min Max Min Max Write Command Setup Time twes 0 _ 0 _ 0 _ ns | 10,19 Write Command Hold Time twcH 15 _ 15 _ 20 _ ns 19 Write Command Pulse Width twp 10 _ 10 _ 20 _ ns Write Command to RAS Lead Time | tpwi 20 _ 20 _ 25 _ ns Write Command to CAS Lead Time | tcwL 20 20 _ 25 _ ns 21 Data-in Setup Time tps 0 _ 0 _ 0 _ ns 1 Data-in Hold Time tpH 15 15 20 _ ns i CAS to OE Delay Time tcop _ 0 0 0 ns 23 Read-Modify-Write Cycle HMS514260A/AL-7 HMS514260A/AL-8 HMS514260A/AL-10 Parameter Symbol |__HMS5 184260A/AL-7 HMS51S84260A/AL-8 HMS51S4260A/AL-10 | Unit | Note Min Max Min Max Min Max Read-Modify-Write Cycle Time trwe 180 _ 200 _ 245 _ ns RAS to WE Delay Time trwD 95 105 135 _ ns 10 CAS to WE Delay Time tcwD 45 45 _ 60 ns 10 Column Address to WE Delay Time | tawp 60 _ 65 _ 80 _ ns 10, 13 OE Hold Time from WE toEH 20 20 25 ns HITACHE 130 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HITACHI/ LOGIC/ARRAYS/M b7E D MM 4494203 0024440 247 MBHIT2 Refresh Cycle HM514260A/AL, HM51S4260A/AL Series HMS514260A/AL-7 HMS514260A/AL-8 HMS514260A/AL-10 Parameter Symbol | HM51S4260A/AL-7 HMS51S4260A/AL-8 HMS51S4260A/AL-10_ | Unit | Note Min Max Min Max Min Max CAS bere eas Refresh Cycle) 'CSR 0 a 10 a 10 ~ ns 19 CAS betore BAS Refresh Cycle) CHR 10 a 10 ~ 10 ~ ns 20 RAS Precharge to CAS Hold Time trpec 10 10 ~ 10 = ns 19 CAS Precharge Time in Normal Mode tcpn 10 10 _ 10 _ ns 22 Fast Page Mode Cycle HMS14260A/AL-7 HMS514260A/AL-8 HMS514260A/AL-10 Parameter Symbol | HM51S4260A/AL-7 HMS51S4260A/AL-8 HMS51S4260A/AL-10 | Unit} Note Min Max Min Max Min Max Fast Page Mode Cycle Time tpc 45 _ 50 _ 55 _ ns Fast Page Mode CAS Precharge Time tcp 10 _ 10 ~~ 10 ns 22 Fast Page Mode RAS Pulse Width tRASC _ 100000 _ 100000 100600 ns 12 Access Time from CAS Precharge tacp 40 _ 45 ~ 50 ns | 3, 13,20 RAS Hold Time from CAS Precharge | tricp 40 45 _ 50 _ ns Fast Page Mode Read-Modify-Write Cycle CAS Precharge to WE tcpw 65 _ 70 85 _ ns Delay Time Cle te Mode Read-Modify-Write trom 95 _ 100 _ 110 _ ns Self-Refresh Mode HMS1S4260A/AL-7 HMS51S4260A/AL-8 HMS1S84260A/AL-10 ; Parameter Symbol - - - Unit | Note Min Max Min Max Min Max RAS Pulse Width (Self-Refresh) tRASS 100 _ 100 _ 100 _ ps RAS Precharge Time (Self-Refresh) | tpps 130 150 180 _ ns CAS Hold Time (Self-Refresh) tcus 50 50 50 _ ns 21 HITACHI Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 131HITACHI/ LOGIC/ARRAYS/M B?7E D MM 4496203 DOC444L 1T3 ME HITe HM514260A/AL, HM51S4260A/AL Series Notes: 1. AC measurements assume tr = 5 ns. 2. Assumes that tpcp S$ trcp (max) and trap S trap (max). If tcp or trap is greater than the maximum recommended value shown in this table, trac exceeds the value shown. \ . Measured with a load circuit equivalent to 2 TTL loads and 100 pF. . Assumes that tpcp 2 trop (max) and trap *% trap (max). . Assumes that tpcp * trop (max) and trap 2 trap (max). . torr (max) defines the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. Vip (min) and Vy, (max) are reference levels for measuring timing of input signals. Also, transition times are measured between Vyy and Vy. 8. Operation with the trcp (max) limit insures that trac (max) can be met, tpcp (max) is specified as a reference point only, if tpcp is greater than the specified tap (max) limit, then access time is controlled exclusively by tcac. 9. Operation with the trap (max) limit insures that trac (max) can be met, trap (max) is specified as a reference point only, if trap is greater than the specified trap (max) limit, then access time is controlled exclusively by taa- 10. twos, trwp. tcwp and tawp are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: if twcs 2 twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tpwp = tnwp (min), tewp 2 tcwp (min), tawp 2 tawp (min) and tcpw 2 tcpw (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or a read-modify-write cycle. 12. trasc defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longer of ta, or tcac OF tacp. 14. An initial pause of 100 ps is required after power up followed by a minimum of eight initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, GE must disable output buffer prior to applying data to the device. 16. Either trcy or try must be satisfied for a read cycle. 17. When both LCAS and UCAS go low at the same time, all 16-bits data are written into the device. LCAS and UCAS cannot be staggered within the same write/read cycles. 18. All the Vcc and Vsg pins shall be supplied with the same voltages. 19. tase tca tres: tacH: twos twcH tcsR and trpc are determined by the earlier falling edge of UCAS or LCAS. 20. tcrp, tcHR tacp and tcpw are determined by the later rising edge of UCAS or LCAS. 21. tow and tcys should be satisfied by both UCAS and LCAS. 22. tcpy and tcp are determined by the time that both UCAS and LCAS are high. 23. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large Vcc/Vsg line noise, which causes to degrade Viy (min)/Vy_ (max) level. 24. topp is planned to be improved to match the standard DRAM specifications. 25. If you use distributed CBR refresh mode with 15.6 ys interval in normal read/write cycle, CBR refresh should be executed within 15.6 us immediately after exiting from and before entering into self refresh mode. 26. IF you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 ps interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 27. Repetitive self refresh mode without refreshing ail memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. Ru & Ww HITACHE 132 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300HITACHI LOGIC/ARRAYS/M B7E D MM 4494203 OO284442 O3T MH HIT2 HM514260A/AL, HM51S4260A/AL Series Notes Concerning 2CAS Control Please do not separate the UCAS/LCAS operation timing intentionally. However skew between UCAS/LGAS are allowed under the following conditions. (1) Each of the UGAS/LCAS should satisfy the timing specifications individually. (2) Different operation mode for upper/lower byte is not allowed: such as following. m fo Delayed write UCAS \ / Early write LCAS \ / (3) Closely separated upper/lower byte control is not allowed. However when the condition (tcp < tuL) is satisfied, fast page mode can be performed. = \ / FA 00194-6 tuL 00194-7 HITACHI . Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 133HITACHI/ LOGIC/ARRAYS/M B7E D M@ 4496203 0024443 T?7b MB HITc HM514260A/AL, HM51S4260A/AL Series @ TIMING WAVEFORMS Read Cycle UCAS LCAS Address Dout Din : Don't care 00134~8 HITACHE 134 Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Paint Pkwy. Brisbane, CA 94005-1819 * (415) 589-8300HITACHI/ LOGIC/ARRAYS/M B7E D MM 4496203 0004444 40e MB HITe HM514260A/AL, HM51S4260A/AL Series * Early Write Cycle ARS OL fl--BEo\ Boman Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 135HITACHI/ LOGIC/ARRAYS/M &67E D MM 4996203 O0OC4445 849 MB HITe HM514260A/AL, HM5154260A/AL Series Delayed Write Cycle tac tRas 1. trp y RAS N 3 X 'cSH tere tT treo tRSH UCAS + tcas A LCAS K j tasR tasc tow. | TRWL t RAW {CAH tres twp Y e yy / WIM tou tos | toze top togH tozo Dout \ invali tcon ro torr2 Ey E GJYy . VA : Don't care ** Invalid Dout comes out, when OE is low level. 00134~10 HITACHE 136 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HITACHI/ LOGIC/ARRAYS/M B7E D MM 4494203 OO2444L 785 MM HIT2 HM514260A/AL, HM51S4260A/AL Series * Read-Modify-Write Cycle {T UCAS LCAS Address Din Dout GF : Don't care 00194-11 HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 137HITACHI LOGIC/ARRAYS/M BPE D MM 4496203 002444? b11 MM HIT2 HM514260A/AL, HM51S4260A/AL Series RAS Only Refresh Cycle tac tras | trap aN a. nas i | Ke tt 'crp tcRP treo UCAS Y, y LCAS Address | High-Z Dout OE. WE : Don't care an : Don't care *** Refresh address ; AO - AS (AX0 AX8) 00134-12 138 HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HITACHI LOGIC/ARRAYS/M G7E D MM 4496203 OOC4448 558 MP HITe HM514260A/AL, HM51S4260A/AL Series CAS Before RAS Refresh Cycle trac . tac tap tras, trp tRas , , tmp fC t~CsSCYXN fF RAS } \ N \ tt taPrc tRPC ICRP topn_| csr] |tcua, , tcpn | jtcsr tcHR ; UCAS f \ | K LCAS / Z K torFi High-Z Dout 2 epPr . Yi Don't care ** WE : Dontcare 00134-13 HITACHE Hitachi America, Ltd. * Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 139HITACHI/ LOGIC/ARRAYS/M bE D MM 4456203 00204449 444 MB HIT2 HM514260A/AL, HM51S4260A/AL Series Fast Page Mode Read Cycle tRASC tap oy trHcP x RAS N 4 'T. tASH tornp tcsH tp : taco, cas tcp tcas. | tcp CAS ueas 1 yw oN & NY LCAS K J k r t RAD tcaH | RRAL 'CAH tasc tase TaSAI |tRAH tasc ASC tCAH a y 7, Yy Address Row .column ,Column column Yy YY L tacs tracs (RRH tres tRcH 'RCH tRCH % y Z yw Z 7; al | RZ toze "cod toze a tpze tend coo Din High-Z UY High-Z j High-Z Y tooo [] tcac teac tcac tooo tAA tAA tAA TRAC lace tace torFy FOFHT 70 oo of 4 Oout ~{ Deut x -{ Dout ) toac A KA topo tozo tpz0. ! } toac torF2 tOFF2 * J ; 5 WL ' toac * WY : Don't care 00194-14 HITACHI 140 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300HITACHI/ LOGIC/ARRAYS/M B7E D MM 4454203 0024450 106 MHITe HM514260A/AL, HM51S4260A/AL Series Fast Page Mode Early Write Cycle trasc tar _ y RAS N \__ 7 tcsH tee tASH Sg taco teas tcp tcas, | tcp teas, ,_ tcrp UCAS N ae * fi N } LCAS NZ tasr| |tran tasc| | 'CAH tase] |'CAH tase | [tcax Address = SES t t twest [tween "wes wes} [Swen TWweH "Wr. Wz tos tos tos tou LY Din Wy yy Dout High-Z OE : Dontcare VA : Don't care 00134-15 HITACHI Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300 141HITACHI/ LOGIC/ARRAYS/M b?7E D MM 4496203 002445) O42 MB HITe HM514260A/AL, HM51S4260A/AL Series Fast Page Mode Delayed Write Cycle trRasc Y RAS \ K _ A 'cSH 'RSH tT tee < rtm trep tcas tcp; {CAS | tee tas CRP UCAS ; LCAS K lA Address tow. twe Bin _+{ Dout tooo ral \ VA: Don't care 00194-16 142 HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300HITACHI/ LOGIC/ARRAYS/M b7E D MM 4496203 0024452 T89 MM HIT? HM514260A/AL, HM51S4260A/AL Series * Fast Page Mode Read-Modify-Write Cycle nm trasc {Rp yy ms OL 4 taco tec i cre top tep a | UCAS Y you LCAS trap N K t RAH tasR 1CAH asc asc 7 y Address Row Column YY YH t tawo cw fe tres tcwo R Pil tawo__| [we al \ p tos toze} | toac ton toz ToH Din High-z Din Din TAA trac tozo toac} toeH lorH Dout torr torre torre tozol_| ! {pz0 _ y rT y GE / tooo topo tonp La "CA: Dent care 00134-17 HITACHE Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300 143HITACHI LOGIC/ARRAYS/M B7E D MM@ 4496203 0024453 915 MBP HITe HM514260A/AL, HM51S4260A/AL Series * Self Refresh Cycle trp tRASS | tRPS AS _j Nh 4 \ vers 7 . r . : Don't care WE OE : Don'tcare 00134-18 The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1. Please do not use tpass timing, 10 ws < trass < 100 us. During this period, the device is in transition state from normal operation mode to self refresh mode. If tpass = 100 ys, then RAS precharge time should use tgp instead of trp. 2. IF you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 512 cycles of distributed CBR refresh with 15.6 xs interval should be executed within 8 ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6 js interval in normal read/write cycle, CBR refresh should be executed within 15.6 ps immediately after exiting from and before entering into self refresh mode. 4. Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. HITACHE 144 Hitachi America, Ltd. Hitachi Plaza 2000 Sierra Point Pkwy. Brisbane, CA 94005-1819 (415) 589-8300