AS7C36432-6QC - Alliance Semiconductor

ALLIANCE SEMICONDUCTOR 1

High Performance

64K×32

CMOS SRAM

AS7C36432

64K×32 Synchronous burst SRAM

Features

• Organization: 65,536 words × 32 bits

• Fully synchronous pipelined operation

• Flow-through option

• Fast clocking speed: 100/75/66 MHz

• Fast clock to data access: 5.5/6/7 ns

• Self-timed write cycle

• On-chip address, control, and data registers

• Byte write enable & global write enable control

• Asynchronous output enable control

•ADSP

, ADSC, ADV, MODE burst control pins

•Pentium

TM or PowerPCTM count sequence

• Transparent logic support for 1 or 2 CPUs

•Single 3.3 ± 0.3V power supply

• 5V safe inputs

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

Logic block diagram

64K×32

Memory

array

Burst logic

CLK

CLR

Address

CLK

I/O[32:25]

CLK

Byte Write

registers

I/O[24:17]

CLK

Byte Write

registers

I/O[16:9]

CLK

Byte Write

registers

I/O[8:1]

CLK

Byte Write

registers

Enable

CLK

Enable

CLK

delay

CE#

Output

registers Input

registers

Power

down

DATA [32:1]

3232

161416

WE4

ADV

ADSC

ADSP

CLK

CE1

CE2

CE3

WE3

WE2

WE1

A[15:0]

MODE

CLK CLK

Pin arrangement

I/O16

I/O17

VCCQ

GNDQ

I/O18

I/O19

I/O20

I/O21

GNDQ

VCCQ

I/O22

I/O23

VCC

GND

I/O24

I/O25

VCCQ

GNDQ

I/O26

I/O27

I/O28

I/O29

GNDQ

VCCQ

I/O30

I/O31

I/O15

I/O14

VCCQ

GNDQ

I/O13

I/O12

I/O11

I/O10

GNDQ

VCCQ

I/O09

I/O08

GND

VCC

I/O07

I/O06

VCCQ

GNDQ

I/O05

I/O04

I/O03

I/O02

GNDQ

VCCQ

I/O01

I/O00

MODE

GND

VCC

A10

A11

A12

A13

A14

A15

100

CE1

CE2

WE3

WE2

WE1

WE0

CE3

VCC

GND

CLK

GWE

BWE

ADSC

ADSP

ADV

AS7C36432

PQFP (14mm × 20mm)

TQFP (14mm × 20mm)

Selection guide

7C36432-5 7C36432-6 7C36432-7 Unit

Minimum cycle time 10 13.3 15 ns

Maximum clock frequency 100 75 66 MHz

Maximum pipelined clock access time 5.5 6 7 ns

Maximum operating current 300 275 250 mA

Maximum standby current 30 30 30 mA

Maximum CMOS standby current (DC) 8 8 6 mA

Preliminary information

AS7C36432

Preliminary information

Functional description

The AS7C36432 is a high performance CMOS 1 Mbit synchronous Static Random Access Memory (SRAM) organized as 65,536 words × 32

bits and incorporates a 2-bit burst counter and output register. It is designed for high performance 3.3V PentiumTM, PowerPCTM, and Cyrix

cache applications.

Fast cycle times of 10/13/15 ns with clock access times (tCD) of 5.5/6/7 ns are ideal for 100, 75, and 66 MHz bus frequencies. Three chip

enable inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the

processor address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled Low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation the data

accessed by the current address, registered in the address registers by the positive edge of CLK, are carried to the data-out registers and

driven on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on

all subsequent clock edges. Address is incremented internally for the next access of the burst when WE is sampled High, ADV is sampled

Low, and both address strobes are High. Burst operation is selectable with the MODE input. With MODE unconnected or driven High, burst

operations use a Pentium/486 count sequence. With MODE driven Low the device uses a linear count sequence, suitable for PowerPC and

many other applications (refer to the Burst sequence table on page 2).

Write cycles are performed by disabling the output buffers with OE and asserting WE. A global write enable GWE writes all 32 bits

regardless of the state of individual WE0–WE3 inputs. Alternately, when GWE is High, one or more bytes may be written by asserting BWE

and the appropriate individual byte WE signal(s). WE0 controls I/O0-I/O7; WE1 controls I/O8-I/O15; WE2 controls I/O16-I/O23; and

WE3 controls I/O24-I/O31.

WE is ignored on the clock edge that samples ADSP Low, but is sampled on all subsequent clock edges. Output buffers are disabled when WE

is sampled Low (regardless of OE). Data is clocked into the data input register when WE is sampled Low. Address is incremented internally

to the next burst of address if WE and ADV are sampled Low.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP follow.

• ADSP must be sampled High when ADSC is sampled Low to initiate a cycle with ADSC.

•WE

signals are sampled on the clock edge that samples ADSC Low (and ADSP High).

• Master chip select CE1 blocks ADSP, but not ADSC.

The AS7C36432 incorporates a flow-through feature which makes the output registers transparent. Tying the FT pin low enables flow-

through mode and disables pipelined operation. The ZZ sleep mode in the AS7C36432 reduces power consumption in standby mode. The

device operates from a single 3.3V±0.3V supply. The AS7C36432 is packaged in a 100-pin 14×20 mm PQFP or TQFP package.

Burst sequence table

Note: The burst sequence wraps around to its initial state upon completion.

Mode = High/No Connect

Pentium Count Sequence

Mode = Low

Linear Count Sequence

Start address 00 01 10 11 00 01 10 11

Second address 01 00 11 10 01 10 11 00

Third address 10 11 00 01 10 11 00 01

Fourth address 11 10 01 00 11 00 01 10

Write enable truth table (per byte)

Key: X = Don’t Care, L = Low, H = High.

† Valid read.

GWE BWE WEn WRITEn

LXXT

XLLT

HHXF

HL HF

†

Asynchronous truth table

Note: For write cycles that follow read cycles, output buffers must be dis-

abled with OE to prevent data bus contention.

Key: L = Low, H = High.

OE I/O [31:0]

L Read data

H High Z

AS7C36432

Preliminary information

Signal descriptions

Absolute maximum ratings

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute max-

imum rating conditions may affect reliability.

Capacitance 1

Signal I/O Properties Description

CLK I CLOCK Clock. All inputs except OE are synchronous to this clock.

A0–A15 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

I/O0–I/O31 I/O SYNC Data. Driven as output when the chip is enabled and OE is active.

CE1 ISYNC Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE1 is

inactive, ADSP is blocked. Refer to the SYNCHRONOUS TRUTH TABLE for more information.

CE2, CE3 ISYNC Synchronous chip enables. Active High and active Low, respectively. Sampled on clock edges

when ADSC is active or when CE1 and ADSP are active.

ADSP I SYNC Address strobe processor. Asserted Low to load a new bus address or to enter standby mode.

ADSC I SYNC Address strobe controller. Asserted Low to load a new address or to enter standby mode.

ADV I SYNC Advance. Asserted Low to continue burst read/write.

GWE ISYNC default

= High

Global write enable. Asserted Low to write all 32 bits. When High, BWE and WE0–WE3

control write enable. This signal is internally pulled High.

BWE ISYNC default

= Low

Byte write enable. Asserted Low with GWE = High to enable effect of WE0–WE3 inputs. This

signal is internally pulled Low.

WE0–WE3 ISYNC

Write enables. Used to control write of individual bytes when GWE = High and BWE = Low.

If any of WE0–WE3 is active with GWE = High and BWE = Low the cycle is a write cycle. If

all WE0–WE3 are inactive the cycle is a read cycle.

OE I ASYNC Asynchronous output enable. I/O pins are driven when OE is active and the chip is

synchronously enabled.

MODE I

STATIC

default =

High

Count mode. When driven High, count sequence follows Intel XOR convention. When driven

Low, count sequence follows Motorola/linear convention. This signal is internally pulled High.18

FT I STATIC Flow-through mode.When low, enables flow-through mode. Connect to VCC if unused or for

pipelined operation.

ZZ I ASYNC Sleep. Places device in low power mode; data is retained. Connect to GND if unused.19

Parameter Symbol Min Max Unit

Power supply voltage relative to GND VCC –0.5 +4.6 V

Input voltage relative to GND (input pins) VIN –0.5 VCC + 0.5 V

Input voltage relative to GND (I/O pins) –0.5 VCCQ + 0.5 V

Power dissipation PD–1.2W

DC output current IOUT –30mA

Storage temperature (plastic) Tstg –65 +150 oC

Temperature under bias Tbias –65 +135 oC

Parameter Symbol Signals Test conditions Max Unit

Input capacitance CIN Address and control pins, MODE, ZZ Vin = 0V 5 pF

I/O capacitance CI/O I/O pins Vin = Vout = 0V 7 pF

AS7C36432

Preliminary information

Synchronous truth table

Key: X = Don’t Care, L = Low, H = High, T = TRUE, F = FALSE.

† See write enable truth table for detailed information.

DC operating conditions

*FT and ZZ pins have internal pull-up and pull-down resistors, respectively, which create 150µA of input leakage;

BWE, GWE, and MODE create 50µA of input leakage.

CE1 CE2 CE3 ADSP ADSC ADV WRITEn†OE Address accessed CLK Operation

H X X X L X X X NA L to H Deselect

L L X L X X X X NA L to H Deselect

L L X H L X X X NA L to H Deselect

L X H L X X X X NA L to H Deselect

L X H H L X X X NA L to H Deselect

L H L L X X F L External L to H Begin read

L H L L X X F H External L to H Begin read

L H L H L X F L External L to H Begin read

L H L H L X F H External L to H Begin read

XXXHHLF L Next L to HCont. read

XXXHHLF HNext L to HCont. read

XXXHHHF LCurrent L to H Suspend read

XXXHHHF HCurrent L to H Suspend read

H X X X H L F L Next L to H Cont. read

H X X X H L F H Next L to H Cont. read

H X X X H H F L Current L to H Suspend read

H X X X H H F H Current L to H Suspend read

L H L H L X T X External L to H Begin write

XXXHHLT XNext L to HCont. write

H X X X H L T X Next L to H Cont. write

XXXHHHT HCurrent L to H Suspend write

H X X X H H T H Current L to H Suspend write

Parameter Symbol Test conditions

-5 -6 -7

UnitMin Max Min Max Min Max

Input leakage current* | ILI | VCC = Max, Vin = GND to VCC –2–2–2µA

Output leakage current | ILO | OE ≥ VIH, VCC = Max,

Vout = GND to VCC –2–2–2µA

Operating power supply

current ICC14 CE1 = VIL, CE2 = VIH, CE3 = VIL,

f = fmax, Iout = 0 mA –300–275–250mA

Standby power supply

current

ISB Deselected, f = fmax –30–30–30mA

SB1 Deselected, f = 0,

all VIN ≤ 0.2V or ≥ VCC - 0.2V –8–8–6mA

SB2 ZZ > VIH –4–4–4mA

Output voltage VOL IOL = 5 mA, VCC = Max – 0.4 – 0.4 – 0.4 V

VOH IOH = –5 mA, VCC = Min 2.4 – 2.4 – 2.4 – V

AS7C36432

Preliminary information

Recommended operating conditions Applicable to all portions of this specification unless otherwise noted.

Package dimensions

PCB land pattern

* VIL min = –2.0V for pulse width less than tRC/2.

Parameter Symbol Min Nominal Max Unit

Supply voltage VCC 3.0 3.3 3.6 V

GND 0.0 0.0 0.0 V

I/O supply voltage VCCQ 3.0 3.3 3.6 V

GNDQ0.0 0.0 0.0 V

Input voltage

Address and

control pins

VIH 2.0 – 5.5 V

VIL –0.5*–0.8V

I/O pins VIH 2.0 – VCC+0.5 V

VIL -0.5*–0.8

Ambient operating temperature Ta0 – 70 °C

100 Lead Quad Flatpack

PQFP (14mm × 20mm)

DHd

L1 L

PQFP TQFP

Min Max Min Max

JEDEC MO–108 MO–136

A1 0.25 0.45 0.05 0.15

A2 2.57 2.87 1.35 1.45

b 0.200.400.220.38

c 0.100.200.090.20

D 13.90 14.10 13.90 14.10

e 0.65 0.65

E 19.90 20.10 19.90 20.10

Hd 17.00 17.40 15.90 16.10

He 23.00 23.40 21.90 22.10

L 0.650.950.450.75

L1 1.60 1.00

q0°10°0°7°

This land pattern accommodates

both PQFP and TQFP packages.

Notes

1 Pad requirement to accommodate two package types is larger than for one package type.

2 All dimensioning and tolerancing conform to ANSI Y14.5M-1982. Dimensions in mm.

3 Datums A--B and --D-- to be determined from the center two leads.

4 Based on the surface mount Design and Land Pattern Standard in IPC-SM-782 rev. A,

subsection 11.3, 8/93 for PQFP.

YD1

Symbol Description

TQFP/PQFP

Min Max

C1 Reference 15.98 ref.

C2 Reference 21.98 ref.

D1 Reference 12.35 ref.

D2 Reference 18.85 ref.

e Pad pitch 0.65

G1 Pad inner dimension 13.69 13.79

G2 Pad inner dimension 19.69 19.79

N Pad count 100

X Pad width 0.35 0.38

Y Pad length 2.24 ref.

Z1 Pad outer dimension 18.16 18.26

Z2 Pad outer dimension 24.16 24.26

AS7C36432

Preliminary information

Timing characteristics over operating range

Notes

Parameter Symbol

-5 -6 -7

Unit NotesMin Max Min Max Min Max

Cycle time (pipelined mode) tCYC 10 - 13 - 15 - ns

Clock access time (pipelined mode) tCD -5.5- 6 - 7 ns

Cycle time (flow-through mode) tCYC -14-18-20ns

Clock access time (flow-through mode) tCDF -12.5- 13 - 14 ns

Output enable to data valid tOE -4-5-6 ns3

Clock High to output Low-Z tLZC 2-2-2- ns5, 8, 15

Output hold from clock High tOH 2-2-2- ns5, 8

Output enable Low to output Low-Z tLZOE 2-2-2- ns5, 8, 15

Output enable High to output High Z tHZOE - 4.5 - 5 - 6 ns 5, 8, 15

Clock High to output High Z tHZC - 4.5 - 5 - 6 ns 5, 8, 15

Clock High pulse width tCH 3 - 4.5 - 5.5 - ns

Clock Low pulse width tCL 3 - 4.5 - 5.5 - ns

Address setup to clock High tAS 2 - 2.5 - 2.5 - ns 9, 10

Address strobe setup to clock High tSS 2 - 2.5 - 2.5 - ns 9, 10

Data setup to clock High tDS 2 - 2.5 - 2.5 - ns 9, 10

Write setup to clock High tWS 2 - 2.5 - 2.5 - ns 9, 10

Address advance setup to clock High tADVS 2 - 2.5 - 2.5 - ns 9, 10

Chip select setup to clock High tCSS 2 - 2.5 - 2.5 - ns 9, 10

Address hold from clock High tAH 0.5 - 0.5 - 0.5 - ns 9, 10

Address status hold from clock High tSH 0.5 - 0.5 - 0.5 - ns 9, 10

Data hold from clock High tDH 0.5 - 0.5 - 0.5 - ns 9, 10

Write hold from clock High tWH 0.5 - 0.5 - 0.5 - ns 9, 10

Address advance hold from clock High tADVH 0.5 - 0.5 - 0.5 - ns 9, 10

Chip select hold from clock High tCSH 0.5 - 0.5 - 0.5 - ns 9, 10

Output rise time (unloaded) tR1-1-1-V/ns5

Output fall time (unloaded) tF1-1-1-V/ns5

ZZ High to snooze mode tZZ tCYC -t

CYC -t

CYC -ns

Snooze mode recovery tZZR -t

CYC -t

CYC ns

1 This parameter is guaranteed but not tested.

2 For test conditions, see AC Test Conditions, Figures A, B, C.

3OE

state is “don’t care” when a byte write enable is sampled Low.

4 This parameter is sampled and not 100% tested.

5 Read cycle is defined as byte write enables all High or ADSP Low for

required setup and hold times. Write cycle is defined as at least one byte

write enable Low and ADSP High for required setup and hold times.

6 This is a synchronous device. All addresses must meet the specified setup

and hold times for all rising edges of CLK when either ADSP or ADSC is

Low and chip enabled. All other synchronous inputs must meet the setup

and hold times with stable logic levels for all rising edges of CLK when

chip is enabled. Chip enable must be valid at each rising edge of CLK

with either ADSP or ADSC Low to remain enabled.

7 Typical values measured at 3.3V, 25°C and 20 ns cycle time.

8 All voltages referenced to GND.

9 Overshoot: VIH ≤ +6.0V for t ≤ tCYC/2

Undershoot: VIL ≥ –2.0V for t ≤ tCYC/2

Power up: VIH ≤ +6.0V and VCC ≤ 3.1V for t ≤ 200 ms

10 ICC given with no output current. ICC increases with faster cycle times

and greater output loading.

11 Transitions are measured ±500 mV from steady state voltage. Output

loading specified with CL = 5 pF as in Figure C.

12 tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature

and voltage.

13 Deselect = device inactive, in powered-down mode. Otherwise device

active (not in powered-down mode).

14 Mode pin exhibits input leakage current of ±10µA in linear burst mode

and has an internal pull-up.

15 At least two clock cycles are required for entry or exit from sleep mode

after ZZ assertion. ZZ specifications to comply with Intel documentation.

AS7C36432

Preliminary information

Key to switching waveforms

Read waveform

Note: ⊕ = XOR when MODE = High/No Connect; ⊕ = ADD when MODE = Low. Refer to Burst sequence table on page 2.

WE[0: 3] is don’t care.

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Undefined output/don’t care

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Falling input

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Rising input

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tCYC

tCH tCL

tSS

tSH

tAS

tAH

tWS

tADVS

tOH

CLK

ADSP

ADSC

Address

GWE, BWE

CE1, CE3

ADV

DOUT

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tCSS

tCSH

tHZC

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tLZOE

tCD

tLZC

tOE

tWH

tADVH

tHZOE

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tSS

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tSH

LOAD NEW ADDRESS

ADV INSERTS WAIT STATES

Q(A2⊕10) Q(A2⊕11) Q(A3)Q(A2) Q(A2⊕01) Q(A3⊕01) Q(A3⊕10) Q(A3⊕11)Q(A1)

A2A1 A3

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CE2

(pipel ined mode)

DOUT Q(A2⊕10)Q(A2⊕11)Q(A3)Q(A2) Q(A2⊕01) Q(A3⊕01) Q(A3⊕10) Q(A3⊕11)Q(A1)

(flow-through mode)

tHZC

tCDF

tOE tLZOE

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AS7C36432

Preliminary information

Write waveform

Note: ⊕ = XOR when MODE = High/No Connect; ⊕ = ADD when MODE = Low. Refer to Burst sequence table on page 2.

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tCYC

tCL

tSS

tSH

tSS

tSH

tAS

tAH

tWS

tWH

tCSS

tADVS

tDS

tDH

CLK

ADSP

ADSC

Address

CE1, CE3

ADV

Data In

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tCSH

tADVH

D(A2⊕01) D(A2⊕10) D(A3)D(A2) D(A2⊕01) D(A3⊕01) D(A3⊕10)

D(A1) D(A2⊕11)

ADV S USPENDS BURST

ADSC LOADS N EW ADDRESS

A1 A2 A3

tCH

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CE2

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WE[0:3]

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AS7C36432

Preliminary information

Read/write waveform

Note: ⊕ = XOR when MODE = High/No Connect; ⊕ = ADD when MODE = Low. Refer to Burst sequence table on page 2.

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tCH

tCYC

tCL

tSS

tSH

tAS

tAH

tWS

tWH

tADVS

tDS

tDH

tOH

CLK

ADSP

Address

CE1, CE3

ADV

DIN

DOUT

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tLZC

tADVH

tLZOE

tOE

tCD

Q(A1) Q(A3⊕01)

D(A2)

Q(A3) Q(A3⊕10) Q(A3⊕11)

A1 A2 A3

CE2

tHZOE

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(pipeline mode)

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DOUT Q(A1) Q(A3⊕01)Q(A3) Q(A3⊕10)

(flow-through mode)

tCDF

AS7C36432

Preliminary information

AC test conditions

Typical DC and AC electrical characteristics

Power-down waveform 19 (preliminary information)

351Ω5 pF*

317Ω

Dout

GND

+3.3V

Figure C: Output load(B)

*including scope

and jig capacitance

Z0=50Ω

Dout

50ΩVL=1.5V

Figure B: Output load (A)

30 pF*

Figure A: Input waveform for tLZC, tLZOE, tHZOE, tHZC

10%

90%

GND

90%

10%

+3.0V

• Output Load: see Figure B,

except for tLZC, tLZOE, tHZOE, tHZC see Figure C.

• Input pulse level: GND to 3V. See Figure A.

• Input rise and fall time (Measured at 0.3V and 2.7V): 2 ns. See Figure A.

• Input and output timing reference levels: 1.5V.

Suppl y voltage (V)

3.0 3.6

3.3

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply current ICC, ISB

Ambient temperature (°C)

–15 60 85

3510

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC, ISB

Normalized supply current ICC, ISB

vs. ambient temperature Ta

vs. supply voltage VCC

ICC

ISB

ICC

ISB

Ambient temperature (°C)

-55 80 125

35-10

0.2

0.04

625

Normalized ISB1 (log scale)

Normal ized su p ply current ISB1

vs. ambient temperature Ta

VCC = 3.30V

Supply vol tage (V)

3.0 3.6

3.3

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Normalized access time

Normalized access time tCD

Ambient temperature (°C)

–15 80 85

3510

0.8

0.9

1.1

1.2

1.0

1.3

1.4

1.5

Normalized access time

Normalized access time tCD

Cycle frequency (MHz)

060

4020

0.0

0.2

0.6

0.8

0.4

1.0

1.2

1.4

Normalized ICC

Normalized s upply current ICC

vs. ambient t emperature Tavs. cycle frequency 1/tCYC

vs. supply voltage VCC

VCC = 3.3V

Ta = 25°C

VCC = 3.3VTa = 25°C

AAAA

CLK

ADSP, ADSC

ICC

tZZ

tZZR

AS7C36432

Preliminary information

Application connectivity examples

Figure A: Pentium 512KB single bank cache

AS7C36432 ordering information

AS7C36432 part numbering system

Package \ Min access time 5.5 ns 6 ns 7 ns

PQFP AS7C36432-5QC AS7C36432-6QC AS7C36432-7QC

TQFP AS7C36432-5TQC AS7C36432-6TQC AS7C36432-7TQC

AS7C 3 6432 –XX XX C

SRAM prefix 3 = 3.3V supply Device number Minimum pipeline

access time

Package: Q = PQFP

TQ = TQFP

Commercial temperature range,

0°C to 70 °C

ADSP

I/O [63:32]

A[18:03]

ADSC

ADV

CE1

CE2

CE3

GWE BWE WE[3:0]

MODE

WE[7:0]

ADR[18:03]

ADSC

ADV

ADPS

D [63:00]

Pentium

Cache

ADSP

I/O [31:00]

A[18:03]

ADSC

ADV

CE1

CE2

CE3

GWE BWE WE[3:0]

MODE

Controller

N/C

AS7C36432

BE[0:3] BE[4:7]

AS7C36432F

DOMESTIC REPS

ALABAMA

Concord Component Reps

190 Lime Quarry, Suite #102

Madison, AL 35758

(205) 772-8883

ARKANSAS

Southern States Marketing

1702 N. Collins Blvd., Suite

#250

Richardson, TX 75080

(214) 238-7500

CALIFORNIA

North:

Brooks Technical Group

883 N. Shoreline Blvd.

Mountain View, CA 94043

(415) 960-3880

South:

Action Technical Sales

2137 Newcastle Avenue

Cardiff, CA 92007-1824

(619) 634-1488

Competitive Technology

16253 Laguna Canyon Road

Suite #160

Irvine, CA 92718.

(714) 450-0170

COLORADO

Technology Sales

1720 South Bellaire Street

Suite #910

Denver, CO 80222

(303) 692-8835

CONNECTICUT

Kitchen & Kutchin Associates

154 State St.

North Haven, CT 06473

(203) 239-0212

DELAWARE

Electro Tech

621 E. Germantown Pike,

Suite #202

Norristown, PA 19401-2454

(610) 272-2125

FLORIDA

Micro-Electronic Components

Corp.

400 Fairway Drive, Suite #107

Deerfield Beach, FL 33441

(954) 426-8944

Micro-Electronic Components

Corp.

822 Riverbend Blvd.

Longwood, FL 32779

(407) 682-9602

Micro-Electronic Components

Corp.

10637 Harborside Drive, North

Largo, FL 34643

(813) 393-5011

GEORGIA

Concord Component Reps

6825 Jimmy Carter Blvd. 1303

Norcross, GA 30071

(770) 416-9597

HAWAII

Brooks Technical Group

883 N. Shoreline Blvd.

Mountain View, CA 94043

(415) 960-3880

IDAHO

ES/Chase

6655 SW Hampton, Suite #120

Tigard, OR 97223

(503) 684-8500

ILLINOIS

El-Mech

3511 N. Cicero Avenue

Chicago, IL 60641

(312) 794-9100

CenTech

3751 Pennridge Dr., Suite #107

Bridgeton, MO 63044

(314) 291-4230

INDIANA

CC Electro Sales

1843 N. Meridian Street

Indianapolis, IN 46202-1411

(317) 921-5000

KANSAS

CenTech

10312 East 63rd Terrace

Raytown, MO 64133

(816) 358-8100

KENTUCKY

CC Electro Sales

1843 N. Meridian Street

Indianapolis, IN 46202-1411

(317) 921-5000

LOUISIANA

Southern States Marketing

13831 NW Freeway, Suite #151

Houston, TX 77040

(713) 895-8533

Southern States Marketing

1702 N. Collins Blvd., Suite

#250

Richardson, TX 75080

(214) 238-7500

MAINE

Kitchen & Kutchin Associates

87 Cambridge Street

Burlington, MA 01803

(617) 229-2660

MARYLAND

Chesapeake Technology

3905 National Drive, Suite #425

Burtonsville, MD 20866

(301) 236-0530

MASSACHUSETTS

Kitchen & Kutchin Associates

87 Cambridge Street

Burlington, MA 01803

(617) 229-2660

MICHIGAN

Enco Group

799 Industrial Court

Bloomfield Hills, MI 48302

(810) 338-8600

MINNESOTA

D.A. Case Associates

4620 W. 77th Street Suite #250

Minneapolis, MN 55435

(612) 831-6777

MISSOURI

CenTech

3751 Pennridge Dr., Suite #107

Bridgeton, MO 63044

(314) 291-4230

CenTech

10312 East 63rd Terrace

Raytown, MO 64133

(816) 358-8100

MISSISSIPPI

Concord Component Reps

190 Lime Quarry, Suite #102

Madison, AL 35758

(205) 772-8883

MONTANA

ES/Chase

6655 SW Hampton, Suite #120

Tigard, OR 97223

(503) 684-8500

NEBRASKA

CenTech

10312 East 63rd Terrace

Raytown, MO 64133

(816) 358-8100

NEVADA

Brooks Technical Group

883 N. Shoreline Blvd.

Mountain View, CA 94043

(415) 960-3880

NEW HAMPSHIRE

Kitchen & Kutchin Associates

87 Cambridge Street

Burlington, MA 01803

(617) 229-2660

NEW JERSEY

ERA Associates

354 Veterans Memorial Hwy

Commack, NY 11725

(800) 645-5500

Electro Tech

621 E. Germantown Pike

Suite #202

Norristown, PA 19401-2454

(610) 272-2125

NEW YORK

ERA Associates

354 Veterans Memorial Hwy

Commack, NY 11725

(516) 543-0510

Tri-Tech Electronics

1043 Front Street

Binghamton, NY 13905

(607) 722-3580

Tri-Tech Electronics

349 W. Commercial Street

Suite #2585

East Rochester, NY 14445

(716) 385-6500

NORTH CAROLINA

Concord Component Reps

10608 Dunhill Terrace

Raleigh, NC 27615

(919) 846-3441

NORTH DAKOTA

D.A. Case Associates

4620 W. 77th Street Suite #250

Minneapolis, MN 55435

(612) 831-6777

OHIO

Midwest Marketing Associates

5001 Mayfield Road Suite #319

Lyndhurst, OH 44124

(216) 381-8575

Midwest Marketing Associates

30 Marco Lane

Dayton, OH 45458

(513) 433-2511

OKLAHOMA

Southern States Marketing

1702 N. Collins Blvd., Suite

#250

Richardson, TX 75080

(214) 238-7500

OREGON

ES/Chase

6655 SW Hampton, Suite #120

Tigard, OR 97223

(503) 684-8500

PENNSYLVANIA

Electro Tech

621 E. Germantown Pike

Suite #202

Norristown, PA 19401-2454

(610) 272-2125

Midwest Marketing Associates

5001 Mayfield Road Suite #319

Lyndhurst, OH 44124

(216) 381-8575

RHODE ISLAND

Kitchen & Kutchin Associates

87 Cambridge Street

Burlington, MA 01803

(617) 229-2660

SOUTH CAROLINA

Concord Component Reps

10608 Dunhill Terrace

Raleigh, NC 27615

(919) 846-3441

SOUTH DAKOTA

D.A. Case Associates

4620 W. 77th Street

Suite #250

Minneapolis, MN 55435

(612) 831-6777

TENNESSEE

Concord Component Reps

190 Lime Quarry, Suite #102

Madison, AL 35758

(205) 772-8883

TEXAS

Southern States Marketing

400 Anderson Lane

Suite #118

Austin, TX 78752

(512) 835-5822

Southern States Marketing

13831 NW Freeway

Suite #151

Houston, TX 77040

(713) 895-8533

Southern States Marketing

1702 N. Collins Blvd.

Suite #250

Richardson, TX 75080

(214) 238-7500

UTAH

Charles Fields & Associates

103 East 650 North

Bountiful, UT 84010

(801) 299-8228

VERMONT

Kitchen & Kutchin Associates

87 Cambridge Street

Burlington, MA 01803

(617) 229-2660

VIRGINIA

Chesapeake Technology

3905 National Drive

Suite #425

Burtonsville, MD 20866

(301) 236-0530

WASHINGTON

ES/Chase

12025 115th Avenue NE

Suite #200

Kirkland, WA 98034

(206) 823-9535

WEST VIRGINIA

Chesapeake Technology

3905 National Drive

Suite #425

Burtonsville, MD 20866

(301) 236-0530

WISCONSIN

D.A. Case Associates

4620 W. 77th Street

Suite #250

Minneapolis, MN 55435

(612) 831-6777

WYOMING

Technology Sales

1720 South Bellaire Street

Suite #910

Denver, CO 80222

(303) 692-8835

INTERNATIONAL

REPS

AUSTRALIA

ACD

14 Melrich Road, Unit 1

Bayswater, Victoria 3153

+61-3-9762-7644

R&D Electronics

4 Plane Tree Avenue

Dingley, Victoria 3172

+61-3-9558-0444

CANADA

J-Squared Technologies

4170 Still Creek Dr. Suite #200

Burnaby, British Columbia

V5C 6C6

(604) 473-4666

J-Squared Technologies

2723 37th Avenue NE

Suite #206

Calgary, Alberta T1Y 5R8

(403) 291-6755

J-Squared Technologies

300 March Road, Wuite 501

Kanata, Ontario K2K 2E2

(613) 592-9540

J-Squared Technologies

3395 American Dr.

Bldg. 306 Unit 2

Mississauga, Ontario L4V 1T4

(905) 672-2030

J-Squared Technologies

100 Alexis Nihon, Suite #960

St. Laurent, Quebec H4M 4P5

(514) 747-1211

EUROPE

Brit Comp Sales Ltd.

1 Brooklands Road

Weybridge, Surrey

KIT13 0SD England

+44-1932 347077

+44-1932 346256

Munich, Germany

+49-894488496

Athismons, France

+33-1-69387678

interACTIVE

Epos House

263 Heage Road

Ripley, Derbyshire

DE5 3GH England

+44-1773-740263

Ramtec Int’l B.V.

Holland, Spain, Italy

Belgium, Hungary, Russia

+31-2526-21222

HONG KONG

Eastele Technology, Ltd.

A16, 6/F.,

Proficient Ind Centre

6 Wang Kwun Road

Kowloon Bay

+852-2798-8860

INDIA

Priya Electronics

San Jose, CA USA

(408) 954-1866

Satcom Sales and Services

201/2, 2nd Floor,

Azam Complex

Shivam Road, Baghamberpet

Hyderabad 500 013

+91-40-761-4675

ISRAEL

Eldis Technologies

36 Kehilat St.

Herzlia 46382 Israel

+972-9-562-666

JAPAN

Bussan Micro Electronics Corp.

Sowa Gotanda Bldg.

7-18, Higashi Gotanda

2-Chome

Shinagawa-ku, Tokyo 141

+81-3-5421-1730

Rohm Corporation

R&D Division/

Advanced Tech 21-

Saiin Mizosaki-cho Ukyo-ku

Kyoto 615

+81-75-311-2121

KOREA

FM Korea

6th Fl. Bando Bldg.

48-1, Banpo-dong, Seocho-ku

Seoul 137 140 Korea

+822-596-3880

fm@ktnet.co.kr

Woo Young Tech Co., Ltd.

5th Floor Koami Bldg., 13-31

Yoido-dong, Youngdeungpo-ku

Seoul, Korea

+822-369-7099

MALAYSIA

Exertec Pte Ltd.

Blk 1A/14/07 Sunnyville

No. 1 Jalan Batu Uban

Gelugor, Penang 11700 Malaysia

+60-4-657-9592

PUERTO RICO

MEC/Caribe

P.O. Box 5038

Caguas, PR 00726

(787) 746-9897

SINGAPORE

Exertec Pte Ltd.

5 Kallang Sector #04-01

349279 Singapore

+65-749-1349

TAIWAN

ASTL

Room A3, 10th Fl.

No. 58 Sec. 1

Ming-Sheng Road

Taipei, Taiwan R.O.C.

+886-2-521-2363

Golden Way

7F-3, 75, Hsin Tai Wu Road

Sec. 1, His-Chih

Taipei-Hsien Taiwan R.O.C.

+886-2-698-1868 x505

Puteam International

9F-5, 391 Sec. 4 Hsin-Yi Road

Taipei, Taiwan R.O.C.

+886-2-729-0373

SALES OFFICES

HEADQUARTERS

Alliance Semiconductor

San Jose, CA

Tel: (408) 383-4900

Fax: (408) 383-4999

BBS: (408) 383-4994

NORTHEAST AREA

Alliance Semiconductor

Boston, MA

(617) 239-8127

TECHNICAL CENTER

TAIWAN

Alliance Semiconductor

11F, NO.66, Sec. 2

Jang Kuao N. Road

Taipei, Taiwan R.O.C.

Tel:+886-2-516-7995

Fax:+886-2-517-4928

alliance@netra.wow.net.tw

Alliance Semiconductor reserves the right to make changes in this data sheet at any time to improve design and supply the best product possible. Publication of advance information does not constitute a

committment to produce or supply the product described. The company cannot assume responsibility for circuits shown or represent that they are free from patent infringement. Alliance products are not

authorized for use as critical components in life support devices or systems without the express written approval of the president of Alliance. ProMotion® and the Alliance logo are registered trademarks

of Alliance Semiconductor Corporation. All other trademarks are property of their respective holders.

ALLIANCE SEMICONDUCTOR

3099 North First Street San Jose, CA 95134 Tel (408) 383-4900 Fax (408) 383-4999 BBS: (408) 383-4994 www.alsc.com

Representatives and sales offices