PUL BE she . MOTOROLA ewcCS1400186/0 a SEMICONDUCTOR So TECHNICAL DATA MCCS146818B MCCS156818B Advance Information Real Time Clock plus SRAM Real Time Clock plus SRAM Module CMOS MCCS146818BP MCCS156818BP MCCS146818BFN MCCS156818BDW P SUFFIX FN SUFFIX DW SUFFIX PLASTIC PLASTIC SOG CASE 709 CASE 776 CASE 751F MCCS146818BM MCCS146818B1M MCCS156818BM MCCS156818B1M M SUFFIX MODULE CASE 905 MCCS is a trademark of Motorola, Inc. IBM, PC/AT are trademarks of International Business Machines Corp. Intel is a registered trademark of Intel, Inc. This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA REV 2 | (Replaces MCCS146818B/D Rev 1 and MCCS146818B1M/D Rev 1.) MOTOROLA INC., 1992TABLE OF CONTENTS Paragraph Page Number Title Number SECTION 1 INTRODUCTION SECTION 2 ELECTRICAL CHARACTERISTICS 2.1 MAXIMUM RATINGS (Voltage referenced to VSS) ...........0. cece eee eee 7 2.2 THERMAL CHARACTERISTICS ............0 00 cece cece ccc eee e eee eeeee 7 2.3 DC ELECTRICAL CHARACTERISTICS (VBATT = 3.0 V, VDD = 0 V, Ta = 25C, Stand-by Mode) .................0. 8 2.4 DC ELECTRICAL CHARACTERISTICS (VDD = 4.75 to 5.25 V, TA = 0 to 70C, Voltages Referenced to VSS) ........ 8 2.5 BUS TIMING (Vpp = 4.5 to 5.5 V, CL = 130 pF, Ta = Oto 70C) ................ 9 2.6 SWITCHING CHARACTERISTICS (Vpp = 4.5 to 5.5 V, TA = Oto 70C) ......... 9 SECTION 3 PIN DESCRIPTIONS SECTION 4 REGISTER DESCRIPTIONS 4.1 INTRODUCTION 2.2.2.2... 62 e cece e cree been nnennees 18 4.2 REGISTER A READ/WRITE ($0A) ............. 000 cece eee eee eens 18 4.3 REGISTER B READ/WRITE ($0B) ...........0..0.. 0.000 ccc eee eee 20 4.4 REGISTER C READ ONLY ($0C) ............ 00. c eee eee eens 21 4.5 REGISTER D READ ONLY ($0D) ............ 0.0 c cece eee eee eens 22 SECTION 5 FUNCTIONAL DESCRIPTION 5.1 ADDRESS MAP .......... 0.00 ccc cent enn n eee teen eenees 23 5.2 TIME, CALENDAR, AND ALARM LOCATIONS ...............0 000 eee eee 23 5.3 STATIC CMOS SRAM .......... 00000. e eee enna 24 5.4 POWER DOWN CONSIDERATIONS ........00.0 0000.0. c cece eens 25 5.5 UPDATE CYCLE .... ccc cee teen enue nennnes 25 5.6 DIVIDER STAGES .... 0.0 ccc n ene e een enes 26 5.7 SQUARE-WAVE OUTPUT SELECTION .......... 00. cece cece eens 26 5.8 INTERRUPTS . 0.0... cece een tent ene n enn nenee 27 5.9 PERIODIC INTERRUPT SELECTION .......... 0.0... c cece cee ee eee ene 28 2 MCCS146818B e MCCS156818B REAL TIME CLOCK FAMILY MOTOROLATABLE OF CONTENTS (Continued) Paragraph Page Number Title Number SECTION 6 APPLICATION INFORMATION 6.1 MCCS1X6818B APPLICATIONS ..........00 00.000 cece ees 29 6.2 MODULE APPLICATIONS ......0..0. 00. ccc cc ccc eee cee teeter eee tenes 31 SECTION 7 PACKAGE DIMENSIONS 7.1 P SUFFIX, PLASTIC DIP (Case 709-02) ........ 0. ccc cece teens 33 7.2 FN SUFFIX, PQCC (Case 776-02) ...... 0... ccc teens 34 7.3 DW SUFFIX, SOG (Case 751F-03) ..... 0... ccc ee eee eens 35 7.4 MODULE (Case 905-01) 2.0... ccc ene ee nents 35 SECTION 8 ORDERING INFORMATION MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 3LIST OF ILLUSTRATIONS Figure Number Title 1.1 Block Diagram ........ 0. . cece teen ee eee eens 2.1 Read/Write Timing for Motorola Bus Cycle .....................0-5. 2.2 Intel Bus Read Cycle 20... cette ene ees 2.3 Intel Bus Write Cycle ..... 0.0.20 eee nes 2.4 IRQ Release Delay ........ 0... ccc ccc eee e nnn eees 2.5 Power-Up Timing ......... 0... ccc ccc eee ent t nett eens 3.1 Pin AssignmentS ........ 00... cece eee ee eee eee eens 3.2 Oscillator Input Configurations ............... 0.20 3.3 Crystal Equivalent Circuit ..... 0.0.02. eects 5.1 Address Map ..... 0... cece ern e ete nennees 5.2 Update Ended and Periodic Relationships ......................005 6.1 IBM/INTEL Application Circuit Multiplexed Bus IBM PC/AT Intel 80X86 Multiplexed Bus Microprocessors ..................:- 6.2 18B Interfaced with Motorola Compatible Multiplexed Bus ........... 6.3 IBM/INTEL Application Circuit Multiplexed Bus IBM PC/AT Intel 80X86 Multiplexed Bus Microprocessors ..................-- LIST OF TABLES Table Number Title 4.1 Divider Configurations ............ 0... c ccc cece 4.2 Periodic Interrupt and Square Wave Output Frequency .............. 5.1 Time, Calendar, and Alarm Data Modes ....................0.0000. 4 MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY Page Number MOTOROLASECTION 1 INTRODUCTION The MCCS146818B and MCCS156818B Real-Time Clock family, referred to in this document as the 18B, is compatible with the DS1285/1287/1287A line. The MCCS146818BM/B1M and MCCS156818BM/B1M devices include a crystal and lithium cell battery encapsulated into a module. These devices include the unique MOTEL concept for use with both Motorola and Intel microprocessor timing cycles. These devices combine five important features: 1) a complete time-of-day clock with alarm and a one hundred year calendar, 2) a programmable interrupt for alarm and timing functions, 3) a square wave generation circuit, 4) 114 bytes of ultra low power SRAM, and 5) the modules need no external parts. The MCCS146818B family interfaces with 1-MHz. processor buses and the MCCS156818B family with 2-MHz processor buses, while consuming very little power, allowing the module battery to last a long period of time. The real time clock plus SRAM has two distinct uses. First, it is a CMOS part that includes all the common battery backed-up functions such as SRAM, time, and calendar. Second, the devices may be used with a CMOS microprocessor to relieve the processor of the timekeeping workload, and to extend the available SRAM of the MPU. In addition the module includes a 32.768-kHz crystal and lithium cell encapsulated into the module. The only difference between the two RTCMs is that the 18B1M is able to erase (set to $FF) all of the built-in general-purpose SRAM by momentarily grounding the RCLR, while the device is in standby mode. This feature is not available on the 18BM. General Features e Pin compatible with DS1285 e Counts seconds, minutes, hours, days, day of the week, date of month and year with leap year compensation e Binary or BCD data representation e 12/24 hour mode e Daylight savings time option e Multiplexed bus for pin efficiency e Interfaced with software as 128 bytes of SRAM 14 bytes of clock and control registers 114 bytes of general-purpose SRAM e Programmable square wave signal e Three interrupts are separately software maskable and testable Time-of-day alarm Timed interrupt, once per second to once per day End of clock update cycle e Operating temperature range 0 to 70C e Digital inputs/outputs are TTL, NMOS, and CMOS compatible e Application information included in Section 6.0 MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 5Module Features Ultra long battery life (see Section 6.2 Item 3) Drop-in replacement for IBM PC/AT computer clock calendar (BM only) Pin for pin compatible with DS1287A/DS1287 18B1M equipped with SRAM clear function No external parts required 1 minute per month accuracy at room temperature mm bb LL 32 KH osc! ~~ = 4 E82 gn Lt 8g oO osc VRT RSO-RS3 _ POWER PERIODIC INTERRUPT/SQUARE WAVE 5 p CYCLE SELECTOR (1 OF 13 SELECTOR) AND ~~ SENSE Vpp > circulT ENABLE | SQUARE WAVE OUT aby f+ | REGISTERS A, B, C, D RESET al 4 BYTES bs 1Hz em SQW D oO i RW >} ' AS-7>4 BUS CLOCK, ALARM, INTERFACE CLOCK/ CALENDAR SRAM CALENDAR (10 BYTES) ADO-AD? ) UPDATE MOT BCD/ RCLR* > BINARY ;<? INCREMENT USER SRAM (114 BYTES) NOTE: Items inside dotted box are on only the module versions of this device. *Signal not available on MCCS1 X6818BM. Figure 1.1. Block Diagram 6 MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLASECTION 2 ELECTRICAL CHARACTERISTICS 2.1 MAXIMUM RATINGS (Voltage referenced to Vss, see Note 1) Parameter Symbol Value Unit Supply Voltage VpD 5.5 Vv All Input Voltages Except OSC1 Vin - 0.5 to Vpp + 0.5 Vv Current Drain per Pin Excluding Vpp and Vss lin +15 mA Storage Temperature 18B Tstg 65 to + 150 C 18B1M/18BM 0 to+ 70 NOTES: 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the limits in the Electrical Characteristics table or pin descriptions section. 2. These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, itis advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high impedance circuits. For proper operation it is recommended that Vin and Voyutbe constrained to the range VSS <(Vin Or Vout) < VDD. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either Vss or Vpp). 2.2 THERMAL CHARACTERISTICS Characteristic Package Symbol Value Unit Thermal Resistances PDIP ReJA 66 C/W ReJc 20 PQCC ReJA 100 C/W ReJc 23 SOG ReJA TBD C/W Rec TBD Module ReJA TBD C/W Rec TBD TBD = To be determined. MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY2.3 DC ELECTRICAL CHARACTERISTICS (VBATT = 3.0 V, VoD = 0 V, Ta = 25C, Stand-by Mode) 1. All outputs except IRQ. IRQ has an open drain. 2. MOT has a 20 kQ pulldown resistor. RCLR has a 20 kQ pullup resistor. MCCS146818B * MCCS156818B REAL TIME CLOCK FAMILY Guaranteed Limits MCCS146818B MCCS156818B Characteristics Symbol Min Max Min Max Unit Range of Operation fose 32.76750 | 32.76850 | 32.76750 | 32.76850 | kHz (see Figure 3.2 for BP and BFN) Input Ignored, Outputs Three-Stated, Oscillator Enabled VBATT Standby Current IBATT 700 500 nA 2.4 DC ELECTRICAL CHARACTERISTICS (VDD = 4.75 to 5.25 V, Ta = 0 to 70C, Voltages Referenced to Vss) Guaranteed Limits Test MCCS146818B MCCS156818B Characteristics Conditions | Symbol Min Max Min Max Unit Output Voltage IOH =lOL < VOL _ 0.1 _ 0.1 Vv (ADO-AD7, SQW) 10 pA VOH | Vpp-0.1 Vpp - 0.1 _ Output High Voltage lIoH=1.0MA | VOH 2.4 _ 2.4 Vv (see Note 1) Output Low Voltage lor =4.0mA,] VoL _ 0.4 _ 0.4 Vv All Outputs Input High Voltage VIH 2.2 Vpp + 0.3 2.2 Vpp + 0.3 Vv (ADO-AD7, DS, MOT, AS, R/W, CS, RESET) Input Low Voltage VIL -0.3 + 0.8 -0.3 + 0.8 Vv (ADO-AD7, DS, R/W, CS, MOT, RESET, AS) All Other Inputs lin 1.0 1.0 HA (Input Pulldown) (see Note 2) Three-State Leakage | Vss < Vout < loz +10 +10 HA VDD Open Drain Leakage _ +10 _ +10 nA Power Supply Current Bus Idle IDD 10 _ 10 mA XTAL on Pins 2 and 3 Squarewave Out Disabled NOTES: MOTOROLA2.5 BUS TIMING (Vpp = 4.5 to 5.5 V, CL = 130 pF, Ta = 0 to 70C) Guaranteed Limits MCCS146818B | MCCS156818B Num. Characteristics Symbol Min Max Min Max Unit 1 Cycle Time teye 450 450 _ ns 2 Pulse Width, DS Low or R/W High tWEL 150 _ 150 _ ns 3 | Pulse Width, DS High or R/W Low tWEH 240 = 240 = ns 4 Input Rise and Fall Time tr, tf _ 30 _ 30 ns 8 | R/WHold Time from DS Going Low tRWH 10 10 = ns 13 | R/W Setup Time Before DS tRWS 80 80 = ns 14 | Chip Select Setup Time Before DS or tcs 10 _ 10 _ ns WR or RD 15 Chip Select Hold Time from DS tCH 0 _ 0 _ ns 18 Read Data Hold Time tDHR 10 80 10 80 ns 21 Write Data Hold Time tpHW 0 _ 0 _ ns 24 Multiplexed Address Valid Time to taSL 30 30 ns AS/ALE Fall 25 Multiplexed Address Hold Time tAHL 10 10 _ ns 26 | Delay Time DS to AS/ALE Rise taSD 20 _ 20 _ ns 27 Pulse Width, AS/ALE High tPASH 40 40 _ ns 28 | Delay Time, AS/ALE Going Low to DS tASED 30 _ 30 _ ns Change or WR Change 30 | Peripheral Output Data or WR Change tDDR 20 240 20 240 ns Delay Time from DS or RD 31 Peripheral Data Setup Time tpsw 75 _ 75 _ ns 2.6 SWITCHING CHARACTERISTICS (Vpp = 4.5 to 5.5 V, Ta = 0 to 70C) Guaranteed Limits MCCS146818B | MCCS156818B Num. Description Symbol Min Max Min Max Unit 33 | RESET Pulse Width tRWL 5 = 5 us 34 | RESET Delay Time tRLH 5 5 = us 35 | IRQ Release from DS tIRDS 2 = 2 us 36 | IRQ Release from RESET tiRR = 2 = 2 us MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY10 AS DS ADO-AD7 WRITE ADO-AD7 . 3 a + READ ee 4 a D NOTE: VHIGH = VIH or VoH VLow = VIL or VoL Figure 2.1. Read/Write Timing for Motorola Bus Cycle MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLAMOTOROLA ALE (ADDRESS LATCH ENABLE) x X VHIGH (AS PIN) __ VLOW @ > x_ _ > < G) > __ RD (READ OUTPUT ENABLE) y t (DS PIN) N. ___(2} > <___(3)_ @ *- WR (WRITE ENABLE} (RW PIN) _/f X > CS (CHIP SELECT) \ \ ~ ADO-AD7 { ADDRESS 4 (ADDRESS/DATA BUS) ~ VALID 4 Figure 2.2. Intel Bus Read Cycle < @7)| ALE (ADDRESS LATCH ENABLE) _,, ie" (AS PIN) J | VLOW < RD (READ OUTPUT ENABLE) (DS PIN) . @- <O> WR (WRITE ENABLE) \ 7 (RAW PIN) K ; @ @ CS (CHIP SELECT) \ \\\ \ Lf / / / / / @) @ < 8) G1) > < >> ()) ADO-AD? ADDRESS WRITE DATA }_- (ADDRESS/DATA BUS) VALID VALID _J Figure 2.3. Intel Bus Write Cycle MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 11so / \ VOW 4 < tIRDS RR @) @) x jw NOTE: VHIGH = VDD 2.0 V, VLow = 0.8 V for Vpp = 5.0 V+ 10% Figure 2.4. IRQ Release Delay Vpp PIN \ OV <__ tRLH __ RESET PIN | TN / a, > /<-. tRWL Figure 2.5. Power-Up Timing 12 MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLASECTION 3 PIN DESCRIPTIONS mot [] 1 @ 28{] Vop osci [] 2 27{] SQW mor [] 1 24[) Vop osce [] 3 26{] NC osci [] 2 23{] Saw ne [| 4 25{] NC osc [] 3 22{] NC apo [| 5 24]] RCLR Apo [} 4 21{] RCLR ADO ) ACER aot [] 6 231] VBaTT apt [| 5 201] Vearr AD D Vaart ane [} 7 22 [] IRQ av2 [] 6 19]] AD2 1 ia apa [} 8 21] RESET aps 7 ell AD3 RESET apa {I 9 20 {] 0s AD4 1] DS apa [] 8 17] Ds ADS []10 19[] Vsg AD5 Vsg ~ aos [] 9 16] Vss Ne TR aoe []11 18f] aos [10 15[) RW 1213 14 15 16 17 18 ap? [}12 17[] As apz {11 141] as S25 B8i8ee ne L113 16{] cS Vss f "2 13H os NC = No Connection VSS l 4 8 ! NC MCCS146818BP MCCS146818BFN MCCS156818BDW MCCS156818BP CASE 776 CASE 751F CASE 709 Pacc SOG PLASTIC DIP mor [] 4 241] Yop mor [| 4 241] Vpp 23{] SQW 23[] SQW apo [| 4 21[] RCLR Apo [] 4 apt [| 5 aot (5 ao2 [| 6 19] iRQ ao2 [| 6 19[] ind aps [| 7 18{] RESET aps (| 7 18 [] RESET apa [| 8 17{] ps apa [] 8 17[] Ds aps [] 9 aps [] 9 ape []10 151] RW ape [] 10 151] RAW ao7 {11 141] as ao (11 141] as vgg [12 13{] Vgg [12 13[] &S MCCS146818B1M MCCS146818BM MCCS156818B1M MCCS156818BM CASE 905 CASE 905 MODULE MODULE Figure 3.1. Pin Assignments MOTOROLA MCCS146818B e MCCS156818B REAL TIME CLOCK FAMILY 13PDIP* Pin # Pacc Pin # SOG Pin # Pin Name Description MOTOROLA/INTEL MOT This input pin is used to select different bus timing structures. When Vpp or a logic high is applied to this pin, the 18B responds to a Motorola microprocessor bus cycle. If a logic low or Vgg is applied to this pin, the Intel bus cycle is used. This pin should be hard-wired to Vpp or Vsg and should not change states during normal operation. See pin descriptions for R/W, DS, and AS for more information. This pin has an internal 20 kQ pulldown resistor. 2,3 3,4 2,3 OSCILLATOR/ CRYSTAL OSC1, OSC2 These input/output pins serve a single function in two different ways. First, the user may attach a 32.768 kHz quartz crystal with a load capacitance of 6-8 pF to these pins to supply the on-board oscillator with a frequency reference. Second, OSC1 may be used to supply the 188 an off-chip 32.768 kHz signal to run the internal counters. This signal may be supplied from an external oscillator or other source. Figure 3.2 shows the schematic for both these configurations. Figure 3.3 shows the crystal equivalent circuit. External trimming capacitors are required and the voltage requirements are 0 V < Vin < Vpp. The fixed input capacitor shown in Figure 3.2 may be replaced by a 5-15 pF tunable capacitor when higher accuracy is desired. Oscillator startup time is layout dependent. Not available on module version. Tuning measurements should NOT be taken from these pins. The SQW pin should be enabled and set up to output an 8.192 kHz signal via Registers A and B. Any frequency accuracy measurements should be made at the SQW pin. Measurements should be accurate to 3 decimal places. in the layout, traces MUST be kept as short as possible. No other traces should be routed under the oscillator. A ground ring around the oscillator circuit will improve noise rejection. 4-11 5-10, 12,14 5-12 ADDRESS/DATA ADO-AD7 These input/output pins are the media for which data and information is passed to and from the system microprocessor or other host. These pins are multiplexed and supply the 18B with both address and data. An address is applied to these pins, and then an address select is applied to the AS pin (see the AS pin description). After the address is applied the SRAM or clock location may be read from or written to depending on the other control signals applied to the 18B. During a read cycle the data is valid after the DS or RD signal is applied. The delay is defined by tDDR in the timing characteristics. The bus returns to a high impedance state after DS is removed. During a write cycle the data must be stable before the DS goes iow or WR signal goes high. This parameter is also supplied in the ac characteristics of this data sheet. The address must be valid just prior to the fall of AS. These pins have an active pulldown of approximately 100 kQ in standby mode. Module pin assignments are the same as for the PDIP unless otherwise noted in the Description column. 14 MCCS146818B * MCCS156818B REAL TIME CLOCK FAMILY MOTOROLAPDIP* Pin # PQacc Pin # SOG Pin # Pin Name Description 13 16 16 CHIP SELECT cs This input pin is used by the hosts address decoding scheme to select or enable this device. This signal must be stable over the entire cycle. If unused, this input should be grounded. If grounded, the application must always use AS and DS in pairs, as any AS latches a new address into the internal address latch. For instance, if the CS pin is grounded and an AS occurs, an address is latched into the internal address buffer and internal decoding takes place to select the proper SRAM or clock location. At this point, a DS should be applied to act upon the data in that SRAM or clock location. DS can not be continually pulsed to access the same or next address. When Vpp is below VBaTT x 1.25, the 18B internally inhibits access cycles by internally disabling the CS input. This action protects both the 18B clock data and SRAM data from a spurious write during a power cycle. This pin has an active pulldown of approximately 100 kQ. 14 17 17 ADDRESS STROBE AS This input pin is used to demultiplex the address/data bus. When an address is supplied to the 18B, this pin is pulsed, latching the address into internal latches. After this occurs, the data may then be transferred to or from the 18B via the address/data bus. This pin has an active pulldown of approximately 100 kQ. See Application Information for more information. 15 19 18 READ/WRITE RW The MOTEL circuit treats the R/W input pin in one of two ways. When a Motorola type processor is connected, R/W is a level sensitive input that indicates whether the current cycle is a read or write cycle. A read cycle is indicated with a high level on R/W while DS is high, a write cycle is a low on R/W during DS. The second interpretation of R/W is as negative write pulses, WR, froman Intel processor. The MOTEL circuit in this mode gives RW the same meaning as a write (W) pulse on many generic SRAMs. This pin has an active pulldown of approximately 100 k2Q2. 17 21 20 DATA STROBE DS This input pin has two interpretations via the MOT circuit. When emanating from a Motorola type processor, DS is a positive pulse during the latter portion of the bus cycle, and is variously called DS (data strobe), E (enable), and 62 (2 clock or phase 2 clock). During read cycles, DS signifies the time that the 18B is to drive the bidirectional bus. In write cycles, the trailing edge of DS causes the 18B to latch the written data. See Application Information, item 2, for more information. The second MOT interpretation of DS is that of RD emanating from the Intel processor. In this case, DS identifies the time period when the 18B drives the bus with read data. This interpretation of DS is also the same, and an output-enable signal on a typical memory. This pin has an active pulldown of approximately 100 kQ. *Module pin assignments are the same as for the PDIP unless otherwise noted in the Description column. MOTOROLA MCCS146818B e MCCS156818B REAL TIME CLOCK FAMILY 15PDIP* Pin # PQcc Pin # SOG Pin # Pin Name Description 18 22 21 This input pin does not affect the clock, calendar or SRAM functions of the 18B. On power up, the RESET pin should be held low for the specified item, tRLH, in order for the power supply to stabilize during the power cycle. When RESET is low the following occurs: a) Periodic interrupt enable (PIE) bit is cleared to zero. b) Alarm interrupt enable (AIE) bit is cleared to zero. c) Update ended interrupt flag (UF) bit is cleared to zero. d) Interrupt request status flag (IRQF) bit is cleared to zero. e) Periodic interrupt flag (PF) is cleared to zero. f) The device is not accessible. g) Alarm interrupt flag (AF) bit is cleared to zero. h) IRQ pin is in a high impedance state. i) Square wave output enable (SQWE) is cleared to zero. j) Update ended interrupt enable (UIE) is cleared to zero. This connection allows the 18B to go in and out of power fail without affecting any of the control registers. RESET function is not available when Vpp < (1.25 x VBatT). This pin has an active pulldown of approximately 100 kQ. 19 23 22 INTERRUPT REQUEST IRQ This output pin is an active-iow open-drain to ground output of the 18B that may be used as an interrupt input to a processor. This IRQ output remains low as long as the status bit (bits 7-4 of Register C) causing the interrupt is present and the corresponding interrupt enable bit (bits 64 of Register B) is set. To clear the IRQ pin, the processor program normally reads Register C. The RESET pin also clears pending interrupts. When no interrupt conditions are present, the IRQ level is in the high impedance state. Multiple interrupting devices may thus be connected to an IRQ bus with one pullup at the processor. IRQ is disabled during Stand-by Mode. 20 24 23 BACKUP POWER VBATT This input pin supplies the 18B with power while the system is in Stand-by Mode. This input is designed for a 3.0 volt lithium cell. This voltage needs to be held between 2.2 and 3 volts for proper operation. The nominal write protect trip point voltage at which access to the 18B is prohibited, is set by internal circuitry as 1.25 x VBATT- Amaximum load of 700 nA at 25C in the absence of Vpp should be used to size the battery or other source. See DC CHARACTERISTICS table. This device is optimized for a lithium cell. If a Ni-Cad is used the application must not allow the charging voltage at VBATT to exceed the VBATTx1.25criteria. Ifthe voltage atthe VBATT pinistoogreat, the device's internal power switching circuit disallows access to the device. Not available on module version. 21 25 24 SRAM CLEAR RCLR This input pin is used to set to logic high ($FF) all 114 bytes of general-purpose SRAM, but does not affect the RAM associated with the clock and calendar functions or registers. In order to clear the SRAM, RCLR must be forced to an input logic low (Vs) during battery backup mode, when Vpp is not applied. This can be done by placing ajumper from RCLR to Vss while the device is powered down. This pin has an internal 20 kQ pullup. Not available on 18BM version. This pin must be left open in normal operation. *Module pin assignments are the same as for the PDIP unless otherwise noted in the Description column. 16 MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLAPDIP* | PQCC | SOG Pin# | Pin# | Pin# Pin Name Description 23 27 27 SQUARE WAVE This output pin can output a signal from one of the 13 taps SQW provided by the 15 internally-divided stages. The frequency of the SQW may be altered by programming Register A, as shown in Table 4.2. The SQW signal may be turned on by setting the SQWE (square wave enable) bit in Register B to a 1, logic high. 24 28 28 POWER DC power, + 5 Vdc, is provided to the 18B via this pin. This pin VpD supplies power only during normal operation. During stand-by mode, power is supplied via the VBATT pin. 12,16 | 15,20 |14,19 | POWER These pins supply the 18B with system ground. One ground is Vss convenient to ground the back-up battery; however, this ground may also be used as a system ground along with the battery ground. Both pins should be grounded for optimum performance. Pin 16 not available on module version. 22 1,11, |4,13, | NO-CONNECT These pins are not connected to any internal device. Pin 22 not 13, 18, | 15, 25, | NC available on module version. 26 26 *Module pin assignments are the same as for the PDIP unless otherwise noted in the Description column. 32.768 kHz OPTIONAL Wop -1.0) 2 osci (OPEN) <a2] sce MCCS1X6818B Vpp 3.2a EXTERNAL SOURCE OSC1 32.768 kHz [J OSC2 T MCCS1X6818B The value of Cj; should be chosen according to the suppliers specifications. 3.2b CRYSTAL SOURCE NOTE: Figure not relevant to module versions. Figure 3.2. Oscillator Input Configurations ui C1 RS __ ff YY Y* WW fosc 32.768 kHz Rs (max) 50 kQ2 i__i.__4 e_ Co (max) 1.7 pF co Cy 0.003 pF || Q 40k a CXTAL 6-8 pF* 3 4 0 t 2 Cin 2-10 pF Fixed* *May vary due to board layout NOTE: Figure not relevant to module versions. Figure 3.3. Crystal Equivalent Circuit MOTOROLA MCCS146818B e MCCS156818B REAL TIME CLOCK FAMILY 174.1 4.2 18 SECTION 4 REGISTER DESCRIPTIONS INTRODUCTION The 18B has four control registers which are accessible to the processor. The four registers are also fully accessible during the update cycle. REGISTER A READ/WRITE ($0A) Bit 7 6 5 4 3 2 1 0 Function | UIP DV2 | DV1 DVO | RS3 | RS2 | RS1 RSO Bit 7 UIP Update in Progress The update in progress bit is a status flag that may be monitored by the user program. When UIP is a 1, ifthe update cycle is notin progress it willsoon begin. When UIP is a 0, the update cycle is not in progress and will not be for at least 244 ys. The time, calendar, and alarm information in SRAM is fully available to the program when the UIP bit is 0. The UIP is a read-only bit, and is not affected by RESET. Writing the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit. This bit is read only. Bits 6, 5, 4 DV2, DV1, DVO Divider These three bits are used to turn the oscillator on and off and to reset the count-down chain. A pattern of 010 is the only combination of bits that will turn the oscillator on and allow the 18B to keep time. A pattern of 11 will enable the oscillator but holds the countdown chain in reset. The next update will occur at 500 ms after a pattern of 010 is written to DV2, DV1, DVO. 000 may be written to DV2DVO to turn off the oscillator to conserve power during shipping and storage. See Table 4.1 for more information. Table 4.1. Divider Configurations Dv2 DV1 DVO | Divider RESET Oscillator 0 0 0 No Off 0 0 1 No Off 0 1 0 No On 0 1 1 No Off 1 0 0 No Off 1 0 1 No Off 1 1 0 Yes On 1 1 1 Yes On MCCS146818B e MCCS156818B REAL TIME CLOCK FAMILY MOTOROLABits 3, 2, 1,0 RS3, RS2, RS1, RSO Rate Select The four rate selection bits select one of 13 taps of the 15-stage divider, or disable the divider output. The tap selected may be used to generate an output square wave (SQW) and/or a periodic interrupt. The user may do one of the following: 1) Enable the interrupt with the PIE bit 2) Enable the SQW output pin with the SQWE bit 3) 4) Enable neither Enable both at the same time at the same rate Table 4.2 lists the periodic interrupt rates and the square wave frequencies that may be chosen with the RS bits. These four bits are read/write bits that are not affected by RESET. Table 4.2. Periodic Interrupt and Square Wave Output Frequency Periodic Interrupt Rate SQW Output RS3 RS2 RS1 RSO TPI Frequency 0 0 0 0 None None 0 0 0 1 3.90625 ms 256 Hz 0 0 1 0 7.8125 ms 128 Hz 0 0 1 1 122.070 us 8.192 kHz 0 1 0 0 244.141 us 4.096 kHz 0 1 0 1 488.284 us 2.048 kHz fe) 1 1 0 976.562 1s 1.024 kHz 0 1 1 1 1.953125 ms 512 Hz 1 0 0 0 3.90625 ms 256 Hz 1 0 0 1 7.8125 ms 128 Hz 1 0 1 0 15.625 ms 64 Hz 1 0 1 1 31.25 ms 32 Hz 1 1 0 0 62.5 ms 16 Hz 1 1 0 1 125 ms 8 Hz 1 1 1 0 250 ms 4 Hz 1 1 1 1 500 ms 2 Hz MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 194.3 REGISTER B READ/WRITE ($0B) 20 Bit 7 6 5 4 3 2 1 0 Function | SET | PIE AIE UIE | SQWE | DM | 24/12 | DSE Bit 7 SET When the SET bitis 0, the update cycle functions normally by advancing the clock count once per second. When the SET bit is written to a 1, any update cycle is inhibited and the program may initialize the time and calendar bytes without an update occurring during initialization. SET is a read/write bit that is not modified by RESET or an internal function of the 18B. Bit 6 PIE Periodic Interrupt Enable This bit is a read/write bit that allows the Periodic Interrupt Flag (PF) bit in Register C to drive the IRQ pin low. The user writes a 1 to the PIE bit in order to receive periodic interrupts at the rate specified by the RS3, RS2, RS1, and RS0O bits in Register A. A 0 in PIE blocks IRQ from being initiated by a Periodic Interrupt, but the PF bit is still set at the periodic rate. PIE is not modified by any internal 18B functions, but is cleared to 0 by RESET. Bit 5 AIE Alarm Interrupt Enable This bit is a read/write bit that when set to a 1, permits the Alarm Flag (AF) bit in Register C to assert IRQ. An Alarm Interrupt occurs when the three time bytes equal the three alarm bytes (including a dont care alarm code by binary 11XXXXXX). When the AIE bitis a 0, the AF bit does not initiate an [RQ signal. The RESET pin clears AIE to 0. The internal functions do not affect the AIE bit. Bit 4 UIE Update-Ended Interrupt Enable This bit enables the Update-ended Flag (UF) bit in Register C to assert IRQ allowing an interrupt when an update is finished. The RESET pin does not affect the UIE. (The SET bit, Bit 7, going high resets this bit on the MCCS156818B only.) Bit 3 SQWE Square Wave Enable When this bit is set to a 1 by the user, a Square wave signal at the frequency specified in the rate selection bits (RS3RS0) in Register A appears on the SQW pin. When the SQWE bit is set to a 0, the SQW pinis held low. The state of SQWE is cleared by the RESET pin. This bit is reset to 0 when Vpp is cycled. Bit 2 DM Data Mode This bit indicates whether time and calendar updates are to use binary or BCD formats. The DM bit is written by the processor program and may be read by the user, but is not modified by any internal functions or RESET. A0 in DM signifies binary-coded-decimal (BCD) data, a1in DM signifies binary data. Bit 1 24/12 24/12 Control Bit This establishes the format of the hours bytes as either the 24-hour mode (24/12 = 1) or the 12-hour mode (24/12 = 0). This bit is affected only by the software; RESET does not change this bit. MCCS146818B e MCCS156818B REAL TIME CLOCK FAMILY MOTOROLA4.4 Bit 0 DSE Daylight Savings Enable This bit is a read/write bit that allows the program to enable two special updates (DSE = 1). On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the last Sunday in October when the time first reaches 1:59:59 AM, it changes to 1:00:00 AM. These special updates do not occur when the DSE bit is a 0. DSE is not changed by any internal operations or RESET. The day of week byte must be set for the DSE function to operate properly. REGISTER C READ ONLY ($0C) Bit 7 6 5 4 3 2 1 0 Function | |RQF | PF AF UF 0 0 0 Bit 7 IRQF Interrupt Request Flag This bit is set to a 1 when one or more of the following are true: 1) PF =PIE=1 2) AF=AIE=1 3) UF =UIE=1 i.e., IRQF = (PF x PIE) + (AF x AIE) + ( UF x UIE) Any time the IRQF bit is a 1, the IRQ pin is driven low. All flag bits (bits 4-6 of Register C) are cleared after Register C is read or when RESET occurs. Bit 6 PF Periodic Interrupt Flag This bit is a read-only bit that is set to a 1 when a particular edge is detected on the selected tap of the divider chain. The RS3-RS0 bits establish the periodic rate. PF is set to a 1 independent of the state of the PIE bit. PF being a 1 initiates an IRQ signal and sets the IRQF bit only when PIE is also a 1. The PF bit is cleared by a RESET or a read of Register C. Bit 5 AF Alarm Flag A1 inthis bit indicates that the current time has matched the alarm time. A1 in AF causes the IRQ pin to go low and a 1 to appear in the IRQF only when the AIE bit is also set toa 1.A RESET or a read of Register C clears AF. Bit 4 UF Update-Ended Interrupt Flag This bit is set after each update cycle. When the UIE bit is a 1, the 1 in UF causes the IRQF bit to be a 1, asserting IRQ. UF is cleared by a Register C read or a RESET. Bits 3-0 Unused These bits are unused and are read as 0. They can not be written. MOTOROLA MCCS146818B e MCCS156818B REAL TIME CLOCK FAMILY 214.5 REGISTER D READ ONLY ($0D) Bit 7 6 5 4 3 2 1 0 Function | VRT 0 0 0 0 0 0 Bit 7 VRT Valid SRAM and Time This bit indicates the condition of the contents of the SRAM. A 0 appears in the VRT bit when VBATT < 2.2 V. This indicates invalid datain SRAM or questionable datain SRAM. The VRTisa read-only bit that is not modified by the RESET pin. The VRT bit can be reset only by reading Register D. For the module, this indicates a bad battery and the device may need replacement. Bits 6O Unused These bits are not used and should not be written to. 22 MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLASECTION 5 FUNCTIONAL DESCRIPTION 5.1 ADDRESS MAP Figure 5.1 shows the address map of the 18B. The memory consists of 114 general-purpose SRAM bytes; 10 SRAM bytes that contain the time, calendar, and alarm data; and 4 SRAM bytes that contain control and status information. All 128 bytes are directly readable and writeable by the processor program except for the following: 1) Registers C and D are read only, 2) bit 7 of Register A is read only, and 3) the high-order bit of the seconds byte is read only and is always 0. The contents of the four control and status registers (A, B, C, and D) are described in Register Descriptions, Section 4. 0 $0 0 SECONDS $00 BYTES 1 SECONDS ALARM $01 13 $0D 2 MINUTES $02 14 $0E 3 MINUTES ALARM $03 4 HOURS $04 5 HOURS ALARM $05 6 DAY OF WEEK $06 7 DAY OF MONTH $07 BYTES 8 MONTH $08 9 YEAR $09 10 REGISTER A $0A 11 REGISTER B $0B 12 REGISTER C $0C 127 s7F 3 REGISTER D $0D Figure 5.1. Address Map 5.2 TIME, CALENDAR, AND ALARM LOCATIONS The processor program obtains time and calendar information by reading the appropriate locations. The program may initialize the time, calendar, and alarm by writing to these SRAM locations. The contents of the 10 time, calendar, and alarm bytes may be either binary-coded-decimal (BCD) or binary. Before initializing the internal registers, the SET bit in Register B should be set to a 1 to prevent time/calendar updates from occurring. The program initializes the 10 locations in the selected format (binary or BCD), then indicates the format in the data mode (DM) bit of Register B. All 10 time, calendar, and alarm bytes must use the same data mode, binary or BCD. The SET bit may now be cleared to allow updates. Once initialized, the real-time clock makes all updates in the selected data mode. The data mode cannot be changed without reinitializing the 10 data bytes. MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 23Table 5.1 shows the binary and BCD formats of the 10 time, calendar, and alarm locations. The 24/12 bitin Register B establishes whether the hour locations represent 1-to-12 or 0-to-23 hours. The 24/12 bit cannot be changed without reinitializing the hour locations. When the 12-hour format is selected, the high-order bit of the hours byte represents PM when it is a 1. The three alarm bytes may be used in two ways. First, when the program inserts an alarm time in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. The second usage is to insert a dont care code in any hexadecimal byte from $CO to $FF. Thatis, the two most significant bits of each byte, when set to 1, create a dont care situation. An alarm interrupt each hour is created with a dont care code in the hours alarm locations. Similarly, an alarm is generated every minute with dont care codes in the hours and minutes alarm bytes. The dont care codes in all three alarm bytes create an interrupt every second. Table 5.1. Time, Calendar, and Alarm Data Modes Range Address Decimal Binary Data BCD Data Location Function Range Mode Mode $0 Seconds 0-59 $00-$3B $00-$59 $1 Second Alarm 0-59 $00-$3B $00-$59 $2 Minutes 0-59 $00-$3B $00-$59 $3 Minute Alarm 0-59 $00-$3B $00-$59 $4 Hours 12 Hour 1-12 $01-$0C AM $1-$12 AM $81-$8C PM $81-$92 PM 24 Hour 0-23 $00-$17 $00-$23 $5 Hour Alarm 12 Hour 1-12 $01-$0C AM $01-$12 AM $81-$8C PM $81-$92 PM 24 Hour 0-23 $00-$17 $00-$23 $6 Day of Week Sunday = 1 1-7 $01-$07 $01-$07 $7 Day of Month 1-31 $01-$1F $01-$31 $8 Month 1-12 $01-$0C $01-$12 $9 Year 0-99 $00-$63 $00-$99 5.3 STATIC CMOS SRAM 24 The 114 bytes of general-purpose SRAM are not dedicated within the 18B. They can be used by the processor program, and are fully available during the update cycle. While time and calendar information must use battery back-up, very frequently there is other nonvolatile data that must be retained when main power is removed. The 114 user SRAM bytes serve the need for low-power CMOS battery-backed storage, and extend the SRAM available to the program. MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLA5.4 5.5 POWER DOWN CONSIDERATIONS During and after the power source conversion, the Vin maximum specification must never be exceeded. Failure to meet the Vin maximum specification can cause a virtual SCR to appear, which may result in excessive current drain and destruction of the part. During the transition from system to battery power, the designer of a battery backed-up system must protect data integrity, minimize power consumption, and ensure hardware reliability. When VDDis applied to the 18B, and reaches a level of greater than VBATT pin potential x 1.25, the device becomes accessible. When Vpp falls below VBATT x 1.25, the chip select input is internally forced to an inactive level regardless of the value of CS at the input pin, and the 18B is write protected. When the 18B is in a write protected state, all inputs are ignored and ail outputs are in a high impedance state. For the module, while VDp is less than VBATT, the device is powered by the internal lithium cell. UPDATE CYCLE The 18B executes an update cycle once per second provided the DVODV2 divider bits are 010 and the SET bit (in Register B) is clear. When an update cycle occurs, the contents of an internal SRAM is updated by one second. A transfer of the user copy SRAM to the internal SRAM occurs prior to the update when a write to any of the timekeeping SRAM has been detected between update cycles. After the update cycle is finished, the new values will be written to the user copy of the timekeeping SRAM. An exception to the update cycle occurs when the SET bit in Register B is set to a 1. The SET bit in a 1 state permits the program to initialize the time and calendar bytes by inhibiting update transfers. If the SET bit is set to a 1, SRAM will be frozen, but the internal copy of SRAM will continue to keep time and will issue an alarm match if it occurs. Upon the release of the SET bit, update cycles would result with a transfer of data to the user copy SRAM. The primary function of the update cycle is to increment the seconds byte, check for overflow, increment the minutes byte when appropriate and so forth through the year of the century byte. The update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match occurs or if a dont care code (11XXXXXX) is present in all three positions. Three methods of accommodating non-availability during update are usable by the program. In discussing the three methods, it is assumed that at random points user programs are able to call a subroutine to obtain the time of day. The first method of avoiding the update cycle uses the update-ended interrupt. If enabled, an interrupt occurs after every update cycle which indicates that 999 ms are available to read valid time and date information. During this time a display could be updated or the information could be transferred to continually available SRAM. Before leaving the interrupt service routing, the IRQF bit in Register C should be cleared. The second method uses the UIP in Register A to determine if the update cycle is in progress or not. The UIP bit will pulse once per second. After the UIP bit goes high, the update cycle begins 244 us before the time/calendar data may be valid. The user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244 us. MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 25The third method uses a periodic interrupt to determine if an update cycle is in progress. The UIP bit in Register A is set high between the setting of the PF bit in Register C. Periodic interrupts that occur at a rate of greater than tBUC + tUC (see Figure 5.2) allow valid time and date information to be read at each occurrence of the periodic interrupt. The reads should be completed within (tPpL/2) + thUC to ensure that data is not read during the update cycle. To properly set up for daylight savings time operation, the user must set the time at least one second before the roll over will occur (i.e., 1:59:59 AM). UIP BIT IN REGISTER A ~ tyc tBuc > UF BIT N REGISTER C tpl > tp] + 2 >}<_ tpj +22. > PF BIT IN REGISTER C tp, = Periodic Interrupt Time Interval (500 ms, 125 ms, 62.5 ms, etc. per Table 2) tuc = Update Cycle Time (1984 us) tpuc = Delay Time Before Update Cycle (244 us) Figure 5.2. Update Ended and Periodic Relationships 5.6 DIVIDER STAGES The 18B has 13 binary-divider stages following the time base as shown in the block diagram. The output of the dividers is a 1 Hz signal to the update system logic. The dividers are controlled by three divider bits (DV2, DV1, DVO) in Register A. The only time base for this device is 32.768 kHz. The divider chain may be held at reset, which allows precision setting of the time. When the divider is changed from reset to an operation time base, the first update system is one second later. 5.7 SQUARE-WAVE OUTPUT SELECTION 26 Thirteen divider taps are made available to a 1-of-13 selector as shown in the block diagram. The first purpose of selecting a divider tap is to generate a square wave output signal at the SQW pin. The RSO-RS3 bits in Register A establish the square wave frequency as listed in Table 4.2. The SQW frequency selection shares the 1-of-13 selector with the periodic interrupts. MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLA5.8 Once the frequency is selected, the output of the SQW pin may be turned on and off under program control with the square wave output selection bit (SQWE bit) in Register B. The 18B then generates a symmetrical waveform at the time of execution. The square wave output pin has a number of potential uses. For example, it can serve as a frequency standard for internal use or as a frequency synthesizer, or could be used to generate one or more audio tones under program control. INTERRUPTS The RTC plus SRAM includes three separate fully automatic sources of interrupts to the processor. The alarm interrupt may be programmed to occur at rates from once-per-second to one-per-day. The periodic interrupt may be selected for rates from half-a-second to 122 us. The update-ended interrupt may be used to indicate to the program that an update cycle is completed. Each of these independent interrupt conditions is described in greater detail in other sections of this data sheet. The processor program selects which interrupts, if any, it wishes to receive. Three bits in Register B enable the three interrupts. Writing a 1 to an interrupt-enable bit allows the interrupt to be initiated when the event occurs. A 0 in the interrupt-enable bit prohibits the IRQ pin from being asserted due to the interrupt cause. If an interrupt flag is already set when the interrupt becomes enabled, the IRQ pin is immediately activated, though the interrupt causing the event may have occurred much earlier. Thus, there are cases where the programs should clear such earlier interrupts before first enabling new interrupts. When an interrupt event occurs, a flag bit is set to a 1 in Register C. Each of the three interrupt sources has separate flag bits in Register C, which are set independent of the state of the corresponding enable bits in Register B. The flag bit may be used with or without enabling the corresponding enable bits. In the software scanned or polling case, the program does not enable the interrupt. The interrupt flag bit becomes a status bit, which the software interrogates when it wishes. When the software detects that the flag is set, itis an indication to the software that the interrupt event occurred since the bit was last read. However, there is one precaution. The flag bits in Register C are cleared (record of the interrupt event is erased) when Register C is read. Double latching is included with Register C so the bits that are set are stable through the read cycle. All bits that are high when read by the program are cleared, and new interrupts (on any bits) are held after the read cycle. One, two, or three flag bits may be found to be set when Register C is used. The program should inspect all utilized flag bits every time register C is read to insure that no interrupts are lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is also set, the IRQ pin is asserted low. IRQ is asserted as long as one of the three interrupted sources has its flag and enables bits set. The IROQF bit in Register C is a 1 whenever the IRQ pin is being driven low. MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 275.9 28 The processor program can determine that the RTC initiated the interrupt by reading Register C. A1 in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the part. The act of reading Register C clears all the then active flag bits, plus the IRQF bit. When the program finds IROF set, it should look at each of the individual flag bits in the same byte which have the corresponding interrupt-mask bit set and service each interrupt which is set. Again, more than one interrupt-flag may be set. PERIODIC INTERRUPT SELECTION The periodic interrupt allows the IRQ pin to be triggered from once every 500 ms to once every 122 us. The periodic interrupt is separate from the alarm interrupt, which may be output from once per second to once per day. Table 4.2 shows that the periodic interrupt rate is selected with the same Register A bits that select the square wave frequency. Changing one also changes the other. But each function may be separately enabled so that a program could switch between the two features or use both. The SQW pin is enabled by the SQWE bit in Register B. Similarly the periodic interrupt is enabled by the PIE bit in Register B. Periodic interrupt is usable by practically all real time systems. It can be used to scan for all forms of inputs from contact closure to serial receive bits or bytes. It can be used in multiplexing displays or with software counters to measure inputs, create output intervals, or await the next needed software function. MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLA6.1 MOTOROLA SECTION 6 APPLICATION INFORMATION MCCS1X6818B APPLICATIONS Refer to Figure 6.1, Figure 6.2 and the following notes for application examples. 1. The MCCS146818B (18B) will drop directly into an MC146818A (18A) circuit with some modifications. The user may use the 18B if the following steps are taken: a) Cut trace or wire going to CKFS on the 18A; this is a battery connection on the 18B. The user needs to supply battery back-up power to this pin. A 3.0 V lithium cell is suggested. Cut the trace or wire to CKOUT on the 184A; this pin is used to clear the contents of the SRAM in stand-by mode on the 18B. It is not recommended to connect any signal to the NC on the 18B. Therefore, it is suggested that the user cut the wire or trace going to these pins and leave them open. The user will need to disconnect the battery from VDpp on the 18A. The battery connection for the 18B is on the VBATT pin. While Ni-Cads may be used (see VBATT in Pin Descriptions) the part is designed for a lithium cell. The 18B is aone-frequency device. The only crystal this chip accepts is the 32.768 kHz 6-8 pF type. If the user has the 1, 2, or 4 MHz crystal or oscillator in the 18A circuit, these will need to be replaced with the 32.768 kHz type. For this reason, the 18B cannot be used in applications that take advantage of the 18As 1, 2, or 4 MHz clock outputs. Vss is used for a system ground. The 18A used this as a stand-by input signal. This function is now done internally and this trace or wire will need to be replaced with a system ground or with a battery ground. The user may also wish to replace the 18A with an 18B1M, which will eliminate all the above except items b) and e). The RCLR pin on the 18B1M will need to be clipped off for proper operation. Or, the user may wish to use the 18BM which already has the RCLR pin clipped. The 18BM includes the 18B along with a crystal and a battery encapsulated into a module. The 18B1M is the same module with RCLR available. In some applications, the user may choose to tie CS directly to ground. This is acceptable; however, this will force the programmer to always apply AS and DS in pairs. This means that if CS is grounded, any ALE (IBM/Intel timing cycle) will cause a new address to be latched into the 18B. It is good practice to use the AS and DS signals in pairs at any time in any application. It is also good practice to use a true chip select derived from address decoding for CS. MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 29lf CS is grounded, the user must always use AS and DS in pairs since any AS will latch a new address into the internal address latch. For instance, If the CS pin is grounded andan AS occurs, an address is latched into the internal address buffer and internal decoding takes place to select the proper SRAM or clock location. At this point, a DS should be applied to act upon the data in said SRAM or clock location. 3. Cjnis dependent on C_ of the XTAL being selected. The recommended C_ of the crystal is 6-8 pF. 4. This device is optimized for a lithium cell. If a Ni-Cad is used the application must not allow the charging voltage at the VBATT pin to exceed the VBATT x 1.25 criteria. That is, if the voltage at the VBATT pin is too great, the devices internal power switching circuit will disallow access to the device. 5. For the MCCS156818B, care should be taken when using an external TTL clock reference. The upper rail must be limited to VBATT + 0.6 V. 1) MoT LY Vpp = ot OSC1 SQW | 32.768 kHz T Cin oS NC = 3 RCLR Osc2 IOW @ $70 [ OE 4 VBATT ADO __ AQ BOr / Al BIE) 5] apt IRQ 2 BREN / | RESET R (SEE NOTE 1) YS BIN & Ap2 MOA ON a DS PAS BSE 7 0.005 WF LITHIUM 3.0 V CELL /_ Od AG B6 rN / 1 AD3 16 T , VFN ft iss as 244 | AD4 Rows as = 9 & IOR @ $71 [OR @ $71 4 DIR y| A as [14 AO BO 10 ___ LTH fT Al Bt \ y AD6 as [13 1OW @ $71 / Re B2 = 11] ap7 | ______ iOwW @ $70 Yo ORIN SYSTEM V, AG B6 N\ ADDRESS /y a7 B7- EN DECODING DATA BUS 12 Vgg GROUND OF 80X86 OE | SEE APPLICATION 245 MCCS1X6818B OW @ $71 INFORMATION we 6.1 ITEM 2 IOR @ $71 J NOTES: 1. Motorola recommends that this resistor be used as a design consideration based on knowledge of the internal circuitry of the 9 18B. This resistor is not required for UL approval and may be omitted. 2. The IBM AT writes a 7-bit address to I/O port $70 and then reads the data from I/O port $71 or writes I/O address $71. This is a typical application for a non-multiplexed bus. 3. Cin is dependent on C,_ of XTAL being selected. Figure 6.1. IBM/INTEL Application Circuit Multiplexed Bus IBM PC/AT Intel 80X86 Multiplexed Bus Microprocessors 30 MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLA 8 ADDRESS/DATA MULTIPLEXED 8 v ADDRESS STROBE > OTHER DATA STROBE (E) >e pe PERIPHERALS AND MC68XX READ/WRITE (R/W) > MEMORY INTERRUPT REQUEST (IRQ) o~<g 8/5 ADDRESS a) ADDRESS DECODE | cs IRQ RW ODS AS ADO-AD7 RESET 18B RESET MOT saw Vpb Figure 6.2. 18B Interfaced with Motorola Compatible Multiplexed Bus 6.2 MODULE APPLICATIONS Refer to Figure 6.3 and the following notes for application examples. 1. MOTOROLA The MCCS146818B1M will drop directly into an 18A circuit with some modifications. The user may use the 18B1M if the following steps are taken; a) Cut trace or wire going to RCLR on 18B. This pin is used to clear the contents of the SRAM in stand-by mode. The user may also choose an 18BM which has the RCLR pin already clipped. b) The user will need to disconnect the battery and charging circuit from VDp. The battery is now internal and requires no charging. In some applications the user may choose to tie CS directly to ground. This is acceptable; however, this will force the programmer to always apply AS and DS in pairs. This means that if CS is grounded, any ALE (IBM/Intel timing cycle) will cause a new address to be latched into the 18B1M. It is good practice to use the AS and DS signals in pairs at any time in any application. It is also good practice to use a true chip select derived from address decoding for CS. MCCS146818B * MCCS156818B REAL TIME CLOCK FAMILY 31lf CS is grounded the user must always use AS and DS in pairs since any AS will latch a new address into the internal address latch. For instance, If the CS pin is grounded and an AS occurs, an address is latched into the internal address buffer and internal decoding takes place to select the proper SRAM or clock location. At this point, a DS should be applied to act upon the data in said SRAM or clock location. 3. Battery is sealed from outside contaminants, thus increasing battery reliability. The RTC chip pulls 500 to 700 nA at 25C. The battery installed has a 42 mAh capacity. 42 mAh/700 nA = 60,000 h (MCCS14681 8B) 42 mAh/500 nA = 84,000 h (MCCS15681 8B) Actual battery life is dependent on duty cycle (computer on time/computer off time), where a larger duty cycle indicates a longer battery life of the RTC. The above formulas are for approximation only. +5V CL vot \_Y Vpp = SQW RCLAY L2t IOW @ $70 OE AO BO /| B00 RG /-Ai BI 5! apt J 82 y 14 RESET A3 BS Y, 8) ap2 YO Y_ DS |17 0.005 uF A5 BS wus bl y| 4886 yy AD3 7 yar 87 8 = 244 AD4 a Z v RW [18 OR @ $71 lOR@$71 7 oR y AD as (14 0 BO 10 [ign s_9 80 29) ade [13 lOW @ $71 Yo Vaan AD7 | |_________. [OW @ $70 /, hope SYSTEM ADDRESS , x 68 DECODING DATABUS __| 12| Veg GROUND CI SEE OF 80X86 OE APPLICATION MCCS1X6818BM a _] 245 INFORMATION iOR @ $71 NOTE: RCLR not available on 18BM devices. Figure 6.3. IBM/INTEL Application Circuit Multiplexed Bus IBM PC/AT Intel 80X86 Multiplexed Bus Microprocessors MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLASECTION 7 PACKAGE DIMENSIONS 7.1 P SUFFIX, PLASTIC DIP (Case 709-02) MOTOROLA NOTES: 1, POSITIONAL TOLERANCE OF LEADS (0), SHALL BE WITHIN 0.25 mm (0.010} AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN 24 13 FORMED PARALLEL 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B 4. 709-01 OBSOLETE, NEW STANDARD 709-02. O 12 | a oe ed be - 4 ___ | af o Wy Ae F a, seanne la M soe MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 337.2 FN SUFFIX, PQCC (Case 776-02) 7 ree 8 LOMO Io ru q NOTE 1 q LEAD q A q n q] ACTUAL q qj q] qd {o) NOTE 1) 28 1 | Io t ote a 025 (0010) oy ae A VIEW D-D ap? K oS = Ai E wo) x) 0.10 (0.004) elele | Sesame mae i le DETAIL S DETAIL S 0.18 (0.007) @|T/ LOMO] nO@P@ 0.18 (0.007) @| T| NOP OQ|LO-u@ be > 7 > +] 0.18 (0.07 @| T/L OM@[NOr@ 0.18 (0.007 @|T/NrP|Ln a 28 (NOTE 1) rn > G1_> NOTES: 1. DUE TO SPACE LIMITATION, CASE 776-02 SHALL BE REPRESENTED BY A GENERAL {SMALLER) CASE OUTLINE DRAWING RATHER THAN SHOWING ALL 28 LEADS. 2. DATUMS -L-, -M-, -N-, AND -P- DETERMINED WHERE TOP OF LEAD SHOULDER EXIT PLASTIC BODY AT MOLD PARTING LINE. 3. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 4. DIMR AND U DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.25 (0.010) PER SIDE. 5. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 6. CONTROLLING DIMENSION: INCH. 7. 776-01 OBSOLETE, NEW STANDARD 776-02. 34 MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY MOTOROLA. 7.3 DW SUFFIX, SOG (Case 751F-03) oe NOTES cel . DIMENSIONS A AND B ARE DATUMS AND TIS ~Annn-n-nn-n-n7-n-n_n_ A DATUM SURFACE. AAA AA HAAARAASR HA . DIMENSIONING AND TOLERANCING PER ANSI 28 15 Y14.5M, 1982. . CONTROLLING DIMENSION: MILLIMETER. P | 4] 0.25 0.010) @ | DIMENSION A AND 8 DO NOT INCLUDE MOLD 14PL PROTRUSION. . MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 7 RX 45 Sr oe eee i ff uy pol es oOo o NW D zap. [#1025001 @]t]e [a O] 7.4 MODULE (Case 905-01) NOTES: 1, DIMENSIONING AND TOLERANCING PER ANS! Y14.5M, 1982. 2, CONTROLLING DIMENSION: INCH. 3. VARIOUS LEADS MISSING, DEPENDENT ON PART TYPE. <o> I }_ [efo.004 (0.10) aie icks TJ Sea . D 24 PL NOTE3 [4] 0.010 (0.25) [T]Z] MOTOROLA MCCS146818B MCCS156818B REAL TIME CLOCK FAMILY 35SECTION 8 ORDERING INFORMATION MCCS 1X6818B XX Device Prefix ee L Package (P = 24-Pin DIP Part Number FN = 28-Lead PQCC M = Module without RCLR (146818B or 156818B) 1M = Module with RGLR DW = SOG)- 7/6? Full Part Numbers MCCS146818BP MCCS156818BP MCCS146818BFN MCCS156818BM MCCS146818BM MCCS156818B1M MCCS146818B1M MCCS156818BDW Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. oszsi4 VR Le MOTOROLA Ee 7 MCCS146818B/D 0 al 1ATX26125-2 PRINTEDINUSA 7/92 IMPERIALLITHO 86565 12,000 MOS D-A YFAAAA