1K x 8 PROM
CY7C281A
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-04003 Rev. *C Revised August 16, 2006
Features
• CMOS for optimum speed/power
• High speed
— 25 ns (Commercial)
• Low power
— 495 mW (Commercial)
• EPROM technology 100% programma ble
• Slim 300-mil or standard 600-mil DIP or 28-pin LCC
•5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Direct replacement for bipolar PROMs
• Capable of withstanding >2001V static discharge
Functional Description
The CY7C281A is a high-performance 1024-word by 8-bit
CMOS PROMs. It is packaged in 300-mil and 600-mil-wide
packages respectively. The CY7C281A is also available in a
28-pin leadless chip carrier. The memory cells utilize proven
EPROM floating-gate technology and byte-wide intelligent
programming algorithms.
The CY7C281A is a plug-in re placements for bipolar devices
and offer the advantages of lower power, superior perfor-
mance, and programming yield. The EPROM cell requires
only 12.5V for the super voltage, and low current requirements
allow for gang programming. The EPROM cells allow each
memory location to be tested 100% because each location i s
written into, erased, and repeate dly exercised prior to encap-
sulation. Each PROM is also tested for AC performance to
guarantee that after customer programming, the product will
meet DC and AC specification limits.
Reading is accomplished b y placing an active LOW signal on
CS1 and CS2, and active HIGH signals on CS3 and CS4. The
contents of the memory location addressed by the address
lines (A0−A9) will become available on the output lines
(O0−O7).
LogicBlockDiagram Pin Configurations
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A8
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
O7
O6
O4
O5
O3
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O7
O6
O5
O4
O3
O2
O1
O0
CS1
15
COLUMN
DECODER
CS2
CS3
CS4
A9
CS1
CS2
CS3
CS4
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
V
CC
GND A6
A7
O3
O1
O018
O4
O5
NC
A0
A4
A3
NC
A8
A9
NC
NC
O7
O6
A2
A1
O2
CS1
CS2
CS3
CS4
DIP
LCC/PLCC
Top View
Top View
7C281A
7C281A
ROW
DECODER PROGRAMMABLE
ARRAY MULTIPLEXER
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CY7C281A
Document #: 38-04003 Rev. *C Page 2 of 8
Maximum Ratings[1]
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .....................................−65°C to +150 °C
Ambient Temperature with
Power Applied..................................................−55°C to +125°C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input V oltage.................................................−3.0V to +7.0V
DC Program Voltage (Pins 18, 20)............. ... ...............13.0V
Static Discharge Voltage............................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.....................................................>200 mA
Selection Guide 7C281A-25 7C281A-30 Unit
Maximum Access Time 25 30 ns
Maximum Operating
Current Commercial 100 100 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ±10%
Electrical Characteristics Over the Operating Range[2,3]
7C281A-25 7C281A-30
Parameter Description Test Conditions Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min., IOL = 16.0 mA 0.4 0.4 V
VIH Input HIGH Level Guaranteed Input Logical HIGH
Voltage for All Inputs 2.0 2.0 V
VIL Input LOW Le ve l Guaranteed Input Logical LOW
Voltage for All Inputs 0.8 0.8 V
IIX Input Current GND < VIN < VCC −10 +10 −10 +10 µA
IOZ Output Leakage Current GND < VOUT < VCC,
Output Disabled −10 +10 −10 +10 µA
IOS Output Short Circuit
Current[4] VCC = Max., VOUT = GND −20 −90 −20 −90 mA
ICC Power Supply Current VCC = Max.,
IOUT = 0 mA Commercial 100 100 mA
VPP Program Voltage 12 13 12 13 V
VIHP Program HIGH Voltage 3.0 3.0 V
VILP Program LOW Voltage 0.4 0.4 V
IPP Program Supply Current 50 50 mA
Capacitance[3]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacita nce 10 pF
Notes
1. The voltage on any input or I/ O pin cannot exceed the power pin during power-up.
2. See the last page of this specification for Group A subgroup testing information.
3. See “Introduction to CMOS PROMs” in this Data Book for general inf ormation on testing.
4. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seconds.
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CY7C281A
Document #: 38-04003 Rev. *C Page 3 of 8
AC Test Loads and Waveforms[3]
3.0V
5V
OUTPUT
R1 250Ω
R2
167Ω
30pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤5ns 5ns
5V
OUTPUT
5pF
INCLUDING
JIG AND
SCOPE
(a) NormalLoad (b) HighZ Load
OUTPUT 2.0V
Equivalent to: THÉ VENIN EQUIVALENT
100Ω
R1 250Ω
R2
167Ω
ALL INPUT PULSES
≤
Switching Characteristics Over the Operating Range[1,3]
7C281A-25 7C281A-30
Parameter Description Min. Max. Min. Max. Unit
tAA Address to Output Valid 25 30 ns
tHZCS Chip Select Inactive to High Z 15 20 ns
tACS Chip Select Active to Output Valid 15 20 ns
Switching Waveforms
tAA tHZCS tACS
A0−A9
ADDRESS
CS3,CS
4
CS1,CS
2
O0−O7
DATA
SELECTED DESELECTED SELECTED
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CY7C281A
Document #: 38-04003 Rev. *C Page 4 of 8
Programming Information
Programming support is available from Cypress as well as
from a number of third party software vendors. For detailed
programming information, including a listing of software
packages, please see the PROM Programming Information
located at the end of this section. Programming algorithms can
be obtained from any Cypress representative.
Figure 1. Programming Pinouts
Table 1. Mode Selection
Pin Function[5]
Read or Output Dis able A9–A0CS4CS3CS2CS1O7–O0
Mode Other A9–A0PGM VFY VPP CS1D7–D0
Read A9–A0VIH VIH VIL VIL O7–O0
Output Disable A9–A0X X VIH XHigh Z
Output Disable A9–A0X VIL X X High Z
Output Disable A9–A0VIL X X X High Z
Output Disable A9–A0X X X VIH High Z
Program A9–A0VILP VIHP VPP VILP D7–D0
Program Verify A9–A0VIHP VILP VPP VILP O7–O0
Program Inhibit A9–A0VIHP VIHP VPP VILP High Z
Intelligent Program A9–A0VILP VIHP VPP VILP D7–D0
Blank Check A9–A0VIHP VILP VPP VILP Zeros
Note
5. X = “don’t care” but not to exceed VCC ±5%.
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
24
23
22
21
13
14
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
D7
D6
D4
D5
D3
15
A9
CS1
VPP
VFY
PGM
28
4
5
6
7
8
9
10
321 27
1314151617
26
25
24
23
22
21
20
1112 19
A5
V
CC
GND A6
A7
D3
D1
D018
D4
D5
NC
A0
A4
A3
A8
A9
NC
NC
D7
D6
A2
A1
D2
CS1
VPP
VFY
PGM
7C281A NC
DIP PLCC
Top View Top View
7C281A
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CY7C281A
Document #: 38-04003 Rev. *C Page 5 of 8
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
1.2
1.0
0.8
0.6
4.0 4.5 5.0 5.5 6.0
NORMALIZED ACCESS TIME
SUPPLYVOLTAGE(V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE(°C) SUPPLYVOLTAGE(V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
0.6
1.2 1.0
0.9
0.8
NORMALIZED I
CC
NORMALIZED I
CC
TA=25°C
0.4
TA=25°C
f= f
MAX
CC
1.6
1.4
1.2
1.0
0.8
−55 125
NORMALIZED ACCESS TIME
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESSTIME
vs.TEMPERATURE
0.6
60
50
40
30
20
10
01.0 2.03.0
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
DELTA t (ns)
AA
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
4.0 0.0 1000
VCC =4.5V
TA=25°C
25 0
OUTPUT SOURCE CURRENT
vs. VOLTAGE
AA
150
175
125
75
50
25
0.0 1.0 2.0 3.0
OUTPUT SINK CURRENT (mA)
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
VCC =5.0V
TA=25°C
4.0
1.00
1.02
0.98
0.94
0.92
0.90
025 5075
100
0.88
0.96
ICC vs.CYCLE PERIOD
CYCLE PERIOD (ns)
NORMALIZED I
CC
VCC =5.5V
TA=25°C
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CY7C281A
Document #: 38-04003 Rev. *C Page 6 of 8
Ordering Information
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
25 CY7C281A-25JC J64 28-Le ad Plastic Leaded Chip Carrier Commercial
30 CY7C281A-30PC P13 24-Lead (300-Mil) Molded DIP Commercial
Package Diagrams
Figure 2. 28-Lead Pla stic Leaded Chip Carrier J64
51-85001-*A
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CY7C281A
Document #: 38-04003 Rev. *C Page 7 of 8
© Cypress Semi con duct or Cor po rati on , 20 06 . The information con t a in ed he re i n is subject to change wi t hou t n oti ce. C ypr ess S em ic on duct or Cor po rati on assu me s no resp onsi b i lity f or th e u s e
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significan t injury to the user. The inclusion of Cypre ss
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Figure 3. 24-Lead (300-Mil) PDIP P13
All product and company names mentioned in this document may be the trademarks of their respective holders.
Package Diagrams
51-85013-*B
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CY7C281A
Document #: 38-04003 Rev. *C Page 8 of 8
Document History Page
Document Title: CY7C281A 1K x 8 PROM
Document Number: 38-04003
REV. ECN NO. Issue Date Orig. of
Change Description of Change
** 113859 03/06/02 DSG Changed fro m Spec number: 38-00227 to 38-04003
*A 118902 10/09/02 GBI Updated ordering informa tio n
*B 122244 12/27/02 RBI Added power up requirements to Maximum ratings information
*C 499538 See ECN PCI Updated ord ering information
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