M368L5623MTN-LB3 - Samsung Semiconductor Division

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

DDR SDRAM Unbuffered Module

184pin Unbuffered Module based on 1Gb M-die

with 64/72-bit ECC/Non ECC

Revision 0.0

April 2004

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Revision History

Revision 0.0 (April, 2004)

- First relea se

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Ordering Information

Operating Frequencies

Part Number Density Organization Component Composition Height

M368L5623MTN-C(L)B3/A2/B0 2GB 128M x 64 128Mx8 (K4H1G0838M) * 16EA 1,250mil

M381L5623MTM-C(L)B3/A2/B0 2GB 128M x 72 128Mx8 (K4H1G0838M) * 18EA 1,250mil

B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5)

Speed @CL2 133MHz 133MHz 100MHz

Speed @CL2.5 166MHz 133MHz 133MHz

CL-tRCD-tRP 2.5-3-3 2-3-3 2.5-3-3

Feature

• Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)

• Differential clock inputs(CK and CK)

• DLL aligns DQ and DQS transition with CK transition

• Programmable Read latency 2, 2.5 (clock)

• Programmable Burst length (2, 4, 8)

• Programmable Burst type (sequential & interleave)

• Edge aligned data output, center aligned data input

• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)

• Serial presence detect with EEPROM

• PCB : Height 1,250 (mil) & double sided

• SSTL_2 Interface

184Pin Unbuffered DIMM based on 1Gb M-die (x8)

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Pin Configuration (Front side/back side)

Note :

1. * : These pins are not used in this module.

2. Pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module ( M381~ ), and are not used on x64 module.

3. Pins 111, 158 are NC for 1row modules & used for 2row modules[ M368(81)L5623MTN(M) ].

Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back

VREF

DQ0

VSS

DQ1

DQS0

DQ2

VDD

DQ3

VSS

DQ8

DQ9

DQS1

VDDQ

CK1

/CK1

VSS

DQ10

DQ11

CKE0

VDDQ

DQ16

DQ17

DQS2

VSS

DQ18

VDDQ

DQ19

DQ24

VSS

DQ25

DQS3

VDD

DQ26

DQ27

VSS

CB0

CB1

VDD

DQS8

CB2

VSS

CB3

BA1

DQ32

VDDQ

DQ33

DQS4

DQ34

VSS

BA0

DQ35

DQ40

VDDQ

/WE

DQ41

/CAS

VSS

DQS5

DQ42

DQ43

VDD

*/CS2

DQ48

DQ49

VSS

/CK2

CK2

VDDQ

DQS6

DQ50

DQ51

VSS

VDDID

DQ56

DQ57

VDD

DQS7

DQ58

DQ59

VSS

SDA

SCL

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

VSS

DQ4

DQ5

VDDQ

DM0

DQ6

DQ7

VSS

VDDQ

DQ12

DQ13

DM1

VDD

DQ14

DQ15

CKE1

VDDQ

*BA2

DQ20

A12

VSS

DQ21

A11

DM2

VDD

DQ22

DQ23

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

VSS

DQ28

DQ29

VDDQ

DM3

DQ30

VSS

DQ31

CB4

CB5

VDDQ

CK0

/CK0

VSS

DM8

A10

CB6

VDDQ

CB7

VSS

DQ36

DQ37

VDD

DM4

DQ38

DQ39

VSS

DQ44

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

173

174

175

176

177

178

179

180

181

182

183

184

/RAS

DQ45

VDDQ

/CS0

/CS1

DM5

VSS

DQ46

DQ47

*/CS3

VDDQ

DQ52

DQ53

A13

VDD

DM6

DQ54

DQ55

VDDQ

DQ60

DQ61

VSS

DM7

DQ62

DQ63

VDDQ

SA0

SA1

SA2

VDDSPD

KEY

Pin Description

Pin Name Function Pin Name Function

A0 ~ A13 Address input (Multiplexed) DM0 ~ 7, 8(for ECC) Data - in mask

BA0 ~ BA1 Bank Select Address VDD Power supply (2.5V)

DQ0 ~ DQ63 Data input/output VDDQ Power Supply for DQS(2.5V)

DQS0 ~ DQS8 Data Strobe input/output VSS Ground

CK0,CK0 ~ CK2, CK2 Clock input VREF Power supply for reference

CKE0, CKE1(for double banks) Clock enable input VDDSPD Serial EEPROM Power/Supply ( 2.3V to 3.6V )

CS0, CS1(for double banks) Chip select input SDA Serial data I/O

RAS Row address strobe SCL Serial clock

CAS Column address strobe SA0 ~ 2 Address in EEPROM

WE Write enable NC No connection

CB0 ~ CB7 (for x72 module) Check bit(Data-in/data-out)

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

2GB, 256M x 64 Non ECC Module (M368L5623MTN) (Populated as 2 bank of x8 DDR SDRAM Module)

Functional Block Diagram

CS0

DQS0

DM0

DM/ CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DM/ CS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DM/ CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DM/ CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS4

DM4

DM/ CS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DM/ CS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

DM/ CS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DM/ CS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM/ CS DQS

D10

DM/ CS DQS

D11

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM/ CS DQS

D12

DM/ CS DQS

D13

DM/ CS DQS

D14

DM/ CS DQS

D15

CS1

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

A0 - A13 A0-A13: DDR SDRAMs D0 - D15

RAS RAS : DDR SDRAMs D0 - D15

CAS CAS : DDR SDRAMs D0 - D15

WE WE : DDR SDRAMs D0 - D15

BA0 - BA1 BA0-BA1 : DDR SDRAMs D0 - D15

VSS D0 - D15

VDD/VDDQ D0 - D15

D0 - D15

VREF

VDDSPD SPD

D0 - D15

*Clock Net Wiring

* Clock Wiring

Clock

Input DDR SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

4 DDR SDRAMs

6 DDR SDRAMs

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

WP Card

Edge

D3/D0/D5

D11/D8/D13

Cap/D1/D6

Cap/D9/D14

D4/D2/D7

D12/D10/D15

R=120Ω

CK0/1/2

CKE 0/1 CKE : DDR SDRAMs D0 - D15

CK0/1/2

Notes :

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

2. DQ/DQS/DM/CKE/CS relationships must be

maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors: 3 Ohms +

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

2GB, 256M x 72 ECC Module (M381L5623MTM) (Populated as 2 ba nk of x8 DDR SD R A M Modul e )

Functional Block Diagram

CS0

DQS0

DM0

DM/ CS DQS

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQS1

DM1

DM/ CS DQS

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQS2

DM2

DM/ CS DQS

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQS3

DM3

DM/ CS DQS

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQS4

DM4

DM/ CS DQS

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQS5

DM5

DM/ CS DQS

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQS6

DM6

DM/ CS DQS

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQS7

DM7

DM/ CS DQS

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM/ CS DQS

D10

DM/ CS DQS

D11

DM/ CS DQS

D12

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

DM/ CS DQS

D13

DM/ CS DQS

D14

DM/ CS DQS

D15

DM/ CS DQS

D16

CS1

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

A0 - A13 A0-A13 : DDR SDRAMs D0 - D17

RAS RAS : DDR SDRAMs D0 - D17

CAS CAS : DDR SDRAMs D0 - D17

WE WE : DDR SDRAMs D0 - D17

BA0 - BA1 BA0-BA1 : DDR SDRAMs D0 - D17

VSS D0 - D17

VDD/VDDQ D0 - D17

D0 - D17

VREF

VDDSPD SPD

D0 - D17

*Clock Net Wiring

* Clock Wiring

Clock

Input DDR SDRAMs

*CK0/CK0

*CK1/CK1

*CK2/CK2

6 DDR SDRAMs

Serial PD

A1 A2

SA0 SA1 SA2

SCL SDA

WP Card

Edge

D3/D0/D5

D12/D9/D14

D8/D1/D6

D17/D10/D15

D4/D2/D7

D13/D11/D16

R=120Ω

CK0/1/2

CKE0/1 CKE : DDR SDRAMs D0 - D17

DQS8

DM8

DM/ CS DQS

I/O 7

I/O 6

I/O 1

I/O 0

I/O 5

I/O 4

I/O 3

I/O 2

DM/ CS DQS

D17

I/O 0

I/O 1

I/O 6

I/O 7

I/O 2

I/O 3

I/O 4

I/O 5

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

Notes :

1. DQ-to-I/O wiring is shown as recommended

but may be changed.

2. DQ/DQS/DM/CKE/C S relationships must be

maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms + 5%.

4. BAx, Ax, RAS, CAS, WE resistors:3 Ohms +

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Absolute Maximum Ratings

Parameter Symbol Value Unit

Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V

Voltage on VDD & VDDQ supply relative to VSS VDD, VDDQ -1.0 ~ 3.6 V

Storage temperature TSTG -55 ~ +150 °C

Power dissipation PD1.5 * # of component W

Short circuit current IOS 50 mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

Functional operation should be restricted to recommend operation condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operating Conditions Recommended operating conditions(Voltage referenced to V SS=0V, TA=0 to 70°C)

Parameter Symbol Min Max Unit Note

Supply voltage(for device with a nominal VDD of 2.5V) VDD 2.3 2.7

I/O Supply voltage VDDQ 2.3 2.7 V

I/O Reference voltage VREF 0.49*VDDQ 0.51*VDDQ V 1

I/O Termination voltage(system) VTT VREF-0.04 VREF+0.04 V2

Input logic high voltage VIH(DC) VREF+0.15 VDDQ+0.3 V

Input logic low voltage VIL(DC) -0.3 VREF-0.15 V

Input Voltage Level, CK and CK inputs VIN(DC) -0.3 VDDQ+0.3 V

Input Differential Voltage, CK and CK inputs VID(DC) 0.36 VDDQ+0.6 V 3

V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio) 0.71 1.4 - 4

Input leakage current II-2 2 uA

Output leakage current IOZ -5 5 uA

Output High Current(Normal strength driver) ;VOUT = VTT + 0.84V IOH -16.8 mA

Output High Current(Normal strength driver) ;VOUT = VTT - 0.84V IOL 16.8 mA

Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V IOH -9 mA

Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V IOL 9mA

1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.

Peak-to peak noise on VREF may not exceed +/-2% of the dc value.

2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to

VREF, and must track variations in the DC level of VREF

3. VID is the magnitude of the difference between the input level on CK and the input level on CK.

4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire

temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the

maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the

maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.

Note :

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes

IDD0 1,600 1,400 1,400 mA

IDD1 1,840 1,640 1,640 mA

IDD2P969696mA

IDD2F 560 480 480 mA

IDD2Q 480 400 400 mA

IDD3P 480 480 480 mA

IDD3N 960 880 880 mA

IDD4R 2,080 1,800 1,800 mA

IDD4W 2,560 2,280 2,280 mA

IDD5 2,880 2,720 2,720 mA

IDD6 Normal 128 128 128 mA

Low power mA Optional

IDD7A 3,920 3,400 3,400 mA

DDR SDRAM IDD spec table

M368L5623MTN [ (128M x 8) * 16, 2GB Non ECC Module ]

(VDD=2.7V, T = 10°C)

* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.

Symbol B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Unit Notes

IDD0 1,800 1,575 1,575 mA

IDD1 2,070 1,845 1,845 mA

IDD2P 108 108 108 mA

IDD2F 630 540 540 mA

IDD2Q 540 450 450 mA

IDD3P 540 540 540 mA

IDD3N 1,080 990 990 mA

IDD4R 2,340 2,025 2,025 mA

IDD4W 2,880 2,565 2,565 mA

IDD5 3,240 3,060 3,060 mA

IDD6 Normal 144 144 144 mA

Low power mA Optional

IDD7A 4,410 3,825 3,825 mA

M381L5623MTM [ (128M x 8) * 18, 2GB ECC Module ]

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK.

2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.

3. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in

simulation. the AC and DC input specifications are related to a Vref envelope that has been bandwidth limited 20MHz.

Output Load Circuit (SSTL_2)

Output Z0=50Ω

CLOAD=30pF

VREF

=0.5*VDDQ

RT=50Ω

Vtt=0.5*VDDQ

Input/Output Capacitance (VDD=2.5V, VDDQ=2.5V, TA= 25°C, f=1MHz)

Parameter Symbol M368L5623MTN M381L5623MTM Unit

Min Max Min Max

Input capacitance(A0 ~ A13, BA0 ~ BA1,RAS,CAS,WE )CIN165816987pF

Input capacitance(CKE0,CKE1) CIN2 42 50 44 53 pF

Input capacitance( CS0, CS1) CIN3 42 50 44 53 pF

Input capacitance( CLK0, CLK1,CLK2) CIN4 28 34 28 34 pF

Input capacitance(DM0~DM7, DM8(for ECC)) CIN5 10 12 10 12 pF

Data & DQS input/output capacitance(DQ0~DQ63) Cout1 10 12 10 12 pF

Data input/output capacitance (CB0~CB7) Cout2 - - 10 12 pF

AC Operating Conditions

Parameter/Condition Symbol Min Max Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V 3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL(AC) VREF - 0.31 V 3

Input Differential Voltage, CK and CK inputs VID(AC) 0.7 VDDQ+0.6 V 1

Input Crossing Point Voltage, CK and CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

AC Timing Parameters & Specifications

Parameter Symbol B3

(DDR333@CL=2.5)) A2

(DDR266@CL=2.0) B0

(DDR266@CL=2.5)) Unit Note

Min Max Min Max Min Max

Row cycle time tRC 60 65 65 ns

Refresh row cycle time tRFC 120 120 120 ns

Row active time tRAS 42 70K 45 120K 45 120K ns

RAS to CAS delay tRCD 18 20 20 ns

Row precharge time tRP 18 20 20 ns

Row active to Row active delay tRRD 12 15 15 ns

Write recovery time tWR 15 15 15 ns

Last data in to Read command tWTR 1 1 1 tCK

Col. address to Col. address delay tCCD 1 1 1 tCK

Clock cycle time CL=2.0 tCK 7.5 12 7.5 12 10 12 ns

CL=2.5 6 12 7.5 12 7.5 12 ns

Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock low level width tCL 0.45 0.55 0. 45 0.55 0.45 0.55 tCK

DQS-out access time from CK/CK tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 ns

Output data access time from CK/CK tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns

Data strobe ed ge to output data edge tDQSQ - 0.45 - 0.5 - 0.5 ns 12

Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS-in setup time tWPRES 0 0 0 ns 3

DQS-in hold time tWPRE 0.25 0.25 0.25 tCK

DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK rising-hold time tDSH 0.2 0.2 0.2 tCK

DQS-in high level width tDQSH 0.35 0.35 0.35 tCK

DQS-in low level width tDQSL 0.35 0.3 5 0.35 tCK

DQS-in cycle time t DSC 0.9 1.1 0.9 1.1 0.9 1.1 tCK

Address and Control Input setup time(fast) tIS 0.75 0.9 0.9 ns i,5.7~9

Address and Control Input hold ti me(fast) tIH 0.75 0.9 0.9 ns i,5.7~9

Address and Control Input setup time(slow) tIS 0.8 1.0 1.0 ns i, 6~9

Address and Control Input hold time(slow) tIH 0.8 1.0 1.0 ns i, 6~9

Data-out high impedance time from CK/CK tHZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 1

Data-out lo w impedance time from CK/CK tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 ns 1

Output Slew Rate Matching Ratio(rise to fall) tSLMR 0.67 1.5 0.67 1.5 0.67 1.5

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Parameter Symbol B3

(DDR333@CL=2.5)) A2

(DDR266@CL=2.0) B0

(DDR266@CL=2.5)) Unit Note

Min Max Min Max Min Max

Mode register set cycle time tMRD 12 15 15 ns

DQ & DM setup time to DQS tDS 0.45 0.5 0.5 ns j, k

DQ & DM hold time to DQS tDH 0.45 0.5 0.5 ns j, k

Control & A d dr ess input pul s e width tIPW 2.2 2.2 2.2 ns 8

DQ & DM input pulse width tDIPW 1.75 1.75 1.75 ns 8

Power down exit time tPDEX 6 7.5 7.5 ns

Exit self refresh to non-Read command tXSNR 75 75 75 ns

Exit self refresh to read command tXSRD 200 200 200 tCK

Refresh interval time tREFI 7.8 7.8 7.8 us 4

Output DQS valid window tQH tHP

-tQHS -tHP

-tQHS -ns11

Clock half period tHP tCLmin

or tCHmin -tCLmin

or tCHmin - ns 10, 11

Data hold s k ew factor tQHS 0.55 0.75 0.75 ns 11

DQS write postamble time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 2

Active to Read with Auto precharge

command tRAP 18 20 20

Autoprecharge write recovery +

Precharge time tDAL (tWR/tCK)

+(tRP/tCK) (tWR/tCK)

+(tRP/tCK) tCK 13

System Characteristics for DDR SDRAM

The following specification parameters are required in systems using DDR333 & DDR266 devices to ensure proper sys-

tem performance. these characteristics are for system simulation purposes and are guaranteed by design.

Table 1 : Input Slew Rate for DQ, DQS, and DM

Table 2 : Input Setup & Hold Time Derating for Slew Rate

Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate

AC CHARACTERISTICS DDR333 DDR266

PARAMETER SYMBOL MIN MAX MIN MAX Units Notes

DQ/DM/DQS input slew rate measured betw een

VIH(DC), VIL(DC) and VIL(DC), VIH(DC) DCSLEW TBD TBD TBD TBD V/ns a, m

Input Slew Rate tIS tIH Units Notes

0.5 V/ns 0 0 ps i

0.4 V/ns +5 0 0 ps i

0.3 V/ns +100 0 ps i

Input Slew Rate tDS tDH Units Notes

0.5 V/ns 0 0 ps k

0.4 V/ns +7 5 +75 ps k

0.3 V/ns +150 +150 ps k

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate

Table 5 : Output Slew Rate Characteristic (X4, X8 Devices only)

Table 6 : Output Slew Rate Characteristic (X16 Devices only)

Table 7 : Output Slew Rate Matching Ratio Characteristics

Delta Slew Rat e tDS tDH Units Notes

+/- 0.0 V/ n s 0 0 ps j

+/- 0.25 V/ns +50 +50 ps j

+/- 0.5 V/ns +100 +100 ps j

Slew Rate Characteristic Typical Range

(V/ns) Minimum

(V/ns) Maximum

(V/ns) Notes

Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g,h

Pulldown s le w 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g,h

Slew Rate Characteristic Typical Range

(V/ns) Minimum

(V/ns) Maximum

(V/ns) Notes

Pullup Slew Rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g,h

Pulldown s le w 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g,h

AC CHARACTERISTICS DDR333 DDR266

PARAMETER MIN MAX MIN MAX Notes

Output Slew Rate Matching Ratio (Pullup to Pulldown) TBD TBD TBD TBD e,m

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Component Notes

1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenc ed to a

specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).

2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys

tem performance (bus turnaround) will degrade accordingly.

3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A

valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ

ously in progress on the bus, DQS will be moving from High- Z to logic LOW . If a previous write was in progress, DQS could

be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.

4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.

5. For command/address input slew rate ≥ 1.0 V/ns

6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns

7. For CK & CK slew rate ≥ 1.0 V/ns

8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by

device design or tester correlation.

9. Slew Rate is measured between VOH(ac) and VOL(ac).

10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this

value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the

period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into

the clock traces.

11. tQH = tHP - tQHS, where:

tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The

pulse duration distortion of on-chip clock circuit s; and 2) The worst case push-out of DQS on one transition followed by the worst

case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-

channel to n-channel variation of the output drivers.

12. tDQSQ

Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given

cycle.

13. tDAL = (tWR/tCK) + (tRP/tCK)

For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and

tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)

tDAL = 5 clocks

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

System Notes :

a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.

Output Test point

VSSQ

50Ω

Figure 1 : Pullup slew rate test load

b. Pulldown slew rate is measured under the test conditions shown in Figure 2.

Output Test point

VDDQ

50Ω

Figure 2 : Pulldown slew rate test load

c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)

Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)

Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output

switching.

Example : For typical slew rate, DQ0 is switching

For minimum slew rate, all DQ bits are switching from either high to low, or low to high.

The remaining DQ bits remain the same as for previous state.

d. Evaluation conditions

Typical : 25 °C (T Ambient), VDDQ = 2.5V, typical process

Minimum : 70 °C (T Ambient), VDDQ = 2.3V, slow - slow process

Maximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast process

e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temper ature and

voltage range. For a given output, it represent s the maxi mum dif ference between pullup and pulldown drivers due to process variation.

f. Verified under typical conditions for qualification purposes.

g. TSOPII package devices only.

h. Only intended for operation up to 266 Mbps per pin.

i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns

as shown in Table 2. The Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or

VIH(DC) to VIL(DC), similarly for rising transitions.

j. A derating factor will be used to increase tDS an d tDH in the case where DQ, DM, and DQS slew rates dif fer, as shown in Tables 3 & 4.

Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the

slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.

The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}

For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delt a rise, fall rate is - 0.5ns/V . Using the table given, this

would result in the need for an increase in tDS and tDH of 100 ps.

k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser

on the lesser of the AC - AC slew rate and the DC- DC slew rate. The input slew rate is based on the lesser of the slew rates deter

mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.

m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotony.

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Command Truth Table

(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)

COMMAND CKEn-1 CKEn CS RAS CAS WE BA0,1 A10/AP A0 ~ A9

A11~ A13 Note

Refresh

Auto Refresh HHLL LH X 3

Self

Refresh

Entry L 3

Exit L H LHHH X3

HX XX 3

Bank Active & Row Addr. H X L L H H V Row Address

Read &

Column Address Auto Precharge Disable HXLHLHV

LColumn

Address 4

Auto Precharge Enable H 4

Write &

Column Address Auto Precharge Disable HXLHLLV

LColumn

Address 4

Auto Precharge Enable H 4, 6

Burst Stop H X L H H L X 7

Precharge Bank Selection HXLLHL

VL X

All Banks X H 5

Active Power Down Entry H L HX XX XLVVV

Exit L H X X X X

Precharge Power Down Mode Entry H L HX XX

LHHH

Exit L H HX XX

LVVV

DM H X X 8

No operation (NOP) : Not defined H X HX XX X9

LHHH 9

Note : 1. OP Code : Operand Code. A0 ~ A13 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)

2. EMRS/ MRS can be issued only at all banks precharge state.

A new command can be issued 2 clock cycles after EMRS or MRS.

3. Auto refresh functions are same as the CBR refresh of DRAM.

The automatic precharge without row precharge command is meant by "Auto".

Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.

If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.

If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.

If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.

If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.

5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.

6. During burst write with auto precharge, new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

7. Burst stop command is valid at every burst length.

8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (W rite DM latency is 0).

9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 128Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H1G0838M-T***

5.25 ± 0.006

5.077

Units : Inches (Millimeters)

0.050

0.0078 ± 0.006

(0.20 ± 0.15)

0.145 Max

0.050 ± 0.0039

(1.270 ± 0.10)

0.100

(2.30) 0.393

(10.00)

(1.270)

0.100

(2.50 )

Detail B

A B

(128.950)

(133.350 ± 0.15)

0.250

(6.350)

Detail A

0.157±0.0039

(4.00±0.1)

0.071

(1.80)

(3.67 Max)

0.039 ± 0.002

(1.000 ± 0.050)

(3.80)

2.175

(6.62)

(64.77) (49.53)

(17.80)

2.55 1.95

0.26

2.5 +0.1/-0.0

0.7

0.10 M CBA

0.1496

(3.00)

0.118

R (2.00)

0.0787

(4.00)

0.1575

1.25

± 0.006

(31.75 ±0.15)

(4.00)

(2X) 0.157

0.10 MCAM B

(3.00Min)

0.118Min

Physical Dimensions : 256Mx64 (M368L5623MTN)

Preliminary

2GB Unbuffered DIMM

Rev. 0.0 April 2004

DDR SDRAM

Tolerances : ± 0.005(.13) unless otherwise specified.

The used device is 128Mx8 DDR SDRAM, TSOPII.

DDR SDRAM Part No : K4H1G0838M-T***

5.25 ± 0.006

5.077

Units : Inches (Millimeters)

0.050

0.0078 ± 0.006

(0.20 ± 0.15)

0.145 Max

0.050 ± 0.0039

(1.270 ± 0.10)

0.100

(2.30) 0.393

(10.00)

(1.270)

0.100

(2.50 )

Detail B

A B

(128.950)

(133.350 ± 0.15)

0.250

(6.350)

Detail A

0.157±0.0039

(4.00±0.1)

0.071

(1.80)

(3.67 Max)

0.039 ± 0.002

(1.000 ± 0.050)

(3.80)

2.175

(6.62)

(64.77) (49.53)

(17.80)

2.55 1.95

0.26

2.5 +0.1/-0.0

0.7

0.10 M CBA

0.1496

(3.00)

0.118

R (2.00)

0.0787

(4.00)

0.1575

1.25

± 0.006

(31.75 ±0.15)

(4.00)

(2X) 0.157

0.10 MCAM B

(3.00Min)

0.118Min

Physical Dimensions : 256Mx72 (M381L5623MTM)