©2008 Fairchild Semiconductor Corporation 1www.fairchildsemi.com
FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
February 2008
FSB52006S
Smart Power Module (SPM)
Features
•60V, R
DS(ON).MAX=80mΩ @ 25°C 3-phase FRFET inverter
including high voltage integrated circuit (HVIC)
• 3 divided negative dc-link terminals for inver ter current sens-
ing applications
• HVIC for gate driving and undervoltage protection
• 3/5V CMOS/TTL compatible, active-high interface
• Optimized for low electromagnetic interference
• Isolation voltage rating of 1500Vrms for 1min.
• Surface mounted device package
• Moisture Sensitive Level 3
General Description
FSB52006S is a tiny smart power module (SPM) based on
FRFET technology as a compact inverter solution for small
power motor drive applications such as fan motors and water
suppliers. It is composed of 6 fast-recovery M OSFET (FRFET),
and 3 half-bridge HVICs for FRFET gate driving. FSB52006S
provides low electromagnetic interference (EMI) char acteristics
with optimized switching speed. Moreover, since it employs
FRFET as a power switch, it has much better ruggedness and
larger safe operation area (SOA) than that of an IGBT-based
power module or one-chip solution. The package is optimized
for the thermal performance and compactness for the use in the
built-in motor application and any other application where the
assembly space is concerned. FSB52006S is the most solution
for the compact inverter providing the energy efficiency,
compactness, and low electromagnetic interference.
Absolute Maximum Ratings
Symbol Parameter Conditions Rating Units
VPN DC Link Input Voltage,
Drain-source Voltage of each FRFET 60 V
ID25 Each FRFET Drain Current, Continuous TC = 25°C 2.6 A
ID100 Each FRFET Drain Current, Continuous TC = 100°C 1.3 A
IDP Each FRFET Drain Current, Peak TC = 25°C, PW < 100μs 5 A
PDMaximum Power Dissipation TC = 25°C, Each FRFET 11 W
VCC Control Supply Voltage Applied between VCC and COM 20 V
VBS High-side Bias Voltage Applied between VB(U)-VS(U), VB(V)-VS(V),
VB(W)-VS(W) 20 V
VIN Input Signal Voltage Applied between IN and COM -0.3 ~ VCC+0.3 V
TJOperating Junction Temperature -20 ~ 125 °C
TSTG Storage Temperature -50 ~ 150 °C
RθJC Junction to Case Therma l Resistance Each FRFET under inverter operating con-
dition (Note 1) 9.2 °C/W
VISO Isolation Voltage 60Hz, Sinusoidal, 1 minute, Connection
pins to heatsink 1500 Vrms
2www.fairchildsemi.com
FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
Pin Descriptions
Note:
Source termi na l o f e ach M OSFE T i s not connected to su pp l y gr o und o r bi a s vo ltage ground inside SPM. Exte rn al connections should be made as in dicated in Figure 2 and 5.
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
Pin Number Pin Name Pin Description
1COM IC Common Supply Ground
2 VB(U) Bias Voltage for U Phase High Side FRFET Driving
3 VCC(U) Bias Voltage for U Phase IC and Low Side FRFET Driving
4IN(UH) Signal Input for U Phase High-side
5IN(UL) Signal Inp ut for U Phase Low-side
6 VS(U) Bias Voltage Ground for U Phase High Side FRFET Driving
7 VB(V) Bias Voltage for V Phase High Side FRFET D riving
8 VCC(V) Bias Voltage for V Phase IC and Low Side FRFET Driving
9IN(VH) Signal Inp ut for V Phase High-side
10 IN(VL) Signal Input for V Phase Low-side
11 VS(V) Bias Voltage Ground for V Phase High Side FRFET Driving
12 VB(W) Bias Voltage for W Phase High Side FRFET Driving
13 VCC(W) Bias Voltage for W Phase IC and Low Side FRFET Driving
14 IN(WH) Signal Input for W Phase High-side
15 IN(WL) Signal Input for W Phase Low-side
16 VS(W) Bias Voltage Ground for W Phase High Side FRFET Driving
17 PPositive DC–Link Input
18 U, VS(U) Output for U Phase & Bias Voltage Ground for High Side FRFET Driving
19 NUNegative DC–Link Input for U Phase
20 NVNegative DC–Link Input for V Phase
21 V, VS(V) Output for V Phase & Bias Voltage Ground for High Side FRFET Driving
22 NWNegative DC–Link Input for W Phase
23 W, VS(W) Output for W Phase & Bias Voltage Ground for High Side FRFET Driving
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
(6) VS(U)
(7) VB(V)
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
(11) VS(V)
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
(16) VS(W)
(17) P
(18) U
(19) NU
(20) NV
(21) V
(22) NW
(23) W
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FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified)
Inverter Part (Each FRFET Unless Otherwise Specified)
Control Part (Each HVIC Unless Otherwise Specified)
Note:
1. For the measurement p oint of case temperatur e TC, please refer to Figure 3 in page 4.
2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM. VPN should be sufficiently less than this value considering the
effect of the stray inductance so that VDS should not exceed BVDSS in any case.
3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5.
4. The peak c ur rent and voltag e o f each FRFET during the sw itchi n g o per a ti on s hou l d b e incl u ded i n t he safe operating area ( SO A). Plea se se e Fig ure 5 for the RBSOA test cir-
cuit that is same as the switching test circuit.
Package Marking & Ordering Information
Symbol Parameter Conditions Min Typ Max Units
BVDSS Drain-Source Breakdown
Voltage VIN= 0V, ID = 250μA (Note 2) 60 - - V
ΔBVDSS/
ΔTJ
Breakdown Voltage Tem-
perature Coefficient ID = 250μA, Referenced to 25°C -0.06 - V
IDSS Zero Gate Voltage
Drain Current VIN= 0V, VDS = 60V - - 1 μA
RDS(on) Static Drain-Source
On-Resistance VCC = VBS = 15V, VIN = 5V, ID = 2.2A - - 0.08 Ω
VSD Drain-Source Diode
Forward Voltage VCC = VBS = 15V, VIN = 0V, ID = -2.2A - - 1.0 V
tON
Switching Times
VPN = 45V, VCC = VBS = 15V, ID = 2.2A
VIN = 0V ↔ 5V
Inductive load L=3mH
High- and low-side FRFET switching
(Note 3)
-620 -ns
tOFF -360 -ns
trr -70 -ns
EON -40 -μJ
EOFF - 5 - μJ
RBSOA Reverse-bias Safe Oper-
ating Area
VPN = 55V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS,
TJ = 150°C
High- and low-side FRFET switching (Note 4) Full Square
Symbol Parameter Conditions Min Typ Max Units
IQCC Quiescent VCC Current VCC=15V, VIN=0V Applied between VCC and C OM - - 160 μA
IQBS Quiescent VBS Current VBS=15V, VIN=0V Applied between VB(U)-VS(U),
VB(V)-VS(V), VB(W)-VS(W) - - 100 μA
UVCCD Low-side Undervoltage
Protection (Figure 6) VCC Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVCCR VCC Undervoltage Protection Reset Level 8.0 8.9 9.8 V
UVBSD High-side Undervoltage
Protection (Figure 7) VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVBSR VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V
VIH ON Threshold Voltage Logic High Level Applied between IN and COM 3.0 - - V
VIL OFF Threshold Voltage Logic Low Level - - 0.8 V
IIH Input Bias Current VIN = 5V Applied between IN and COM -10 20 μA
IIL VIN = 0V - - 2 μA
Device Marking Device Package Reel Size Packing Type Quantity
FSB52006S FSB52006S SPM23-BA 330mm Tape & reel 450
4www.fairchildsemi.com
FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
Recommended Operating Conditions
Note:
(1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 100-V rating
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is sho wn above .
(3) RC coupling(R5 and C5) at each inp ut (ind icate d as do tte d line s) ma y be use d to pr event imp roper inpu t sign al due to su rge n oise . Sign al in put of S PM is compatible with stan-
dard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2
and C3 should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters
Note:
Attach the thermocouple on top of the heatsink-side of SPM (between SPM and heatsink if applied) to get the correct temperature measurement.
Figure 3. Case Temperature Measurement
Symbol Parameter Conditions Value Units
Min. Typ. Max.
VPN Supply Voltage Applied between P and N -45 55 V
VCC Control Supply Voltage Applied between VCC and COM 13.5 15 16.5 V
VBS High-side Bias Voltage Applied between VB and VS13.5 15 16.5 V
VIN(ON) Input ON Threshold Voltage Applied between IN and COM 3.0 -VCC V
VIN(OFF) Input OFF Threshold Voltage 0 - 0.6 V
tdead Blanking Time for Preventing
Arm-short VCC=VBS=13.5 ~ 16.5V, TJ ≤ 125°C 1.0 - - μs
fPWM PWM Switching Frequency TJ ≤ 125°C -15 -kHz
TCCase Temperature TJ ≤ 125°C -20 -100 °C
COM
VCC
LIN
HIN
VB
HO
VS
LO
P
NR3
Inverter
Output
C3
R1D1
C1
R2
Micom
15-V Line
10μFOne-Leg Diagram of SPM
These values depend on PWM
control algorithm
* Example of bootstrap paramters:
C1 = C 2 = 1μF ceramic capacitor,
R1 = 56Ω, R2 = 20Ω
R5
C5
HIN LIN
VDC
0 0
0 1
1 0
1 1
Open Open
Output
Z
0
VDC
Forbidden
Z
Note
Both FRFET Off
Low-side FRFET On
High-side FRFET On
Shoot-through
Same a s (0, 0 )
C2
Case Tem perature(Tc)
Detecting Point
14.50mm
3.80mm
MOSFET Case Temperature(Tc)
Detecting Point
14.50mm
3.80mm
MOSFET
5www.fairchildsemi.com
FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
Figure 4. Switching Time Definition
Figure 5. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Figure 6. Undervoltage Prot ection (Low-side)
Figure 7. Undervoltage Protection (High-side)
tON trr
Irr
100% of ID120% of ID
(a) Turn -on
tOFF
(b) Tu rn -o ff
ID
VDS
VDS
ID
VIN VIN
10% of ID
COM
VCC
LIN
HIN
VB
HO
VS
LO
One-leg Diagram of SPM
ID
VCC RBS
REH
CBS
LV
DC
+
VDS
-
UVCCD
UVCCR
Input Signal
UV Protection
Status
Low-side Supply, VCC
MOSFET Current
RESET DETECTION RESET
UVBSD
UVBSR
Input Signal
UV Protection
Status
High-si de Supply, VBS
MOSFET Current
RESET DETECTION RESET
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FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
Figure 8. Example of Applicat ion Circuit
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
(6) VS(U)
(7) VB(V)
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
(11) VS(V)
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
(16) VS(W)
(17) P
(18) U
(19) NU
(20) NV
(21) V
(22) NW
(23) W
Micom
C1
R1
R2
15-V
Supply
M
C3VDC
R1
R1
C1
C1
C2
C2
C2
R3
R4
C4
R5
C5
For 3-phase current sensing and protection
7www.fairchildsemi.com
FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
Detailed Package Outline Drawings
12.00±0.20
29.00±0.20
0.60±0.10
Max 1.00
(1.80)
(1.30)
(2.275) 4x3.90=15.60±0.30
1.95
#1 #16
#17 #23
2x3.90=7.80±0.30
0.508
0.15±0.05
5°±3°
1.50±0.20
(2.50)
(1.30)
GAGE PLANE
Max 3.50
12.23±0.30 13.13±0.30
13.34±0.30
SEATING PLANE
(1.80)
3.10±0.20
(1.00)
17.00±0.20
0.50+0.10
-0.05
#1 #16
17.90
12.30
2.80
15*1.778=26.67
1.30
13.34±0.30
15.607.80
4.43 2.48
LAND PATTERN RECOMMENDATIONS
0.60±0.10
Max 1.00
(1.165) 15*1.778=26.67±0.30
8www.fairchildsemi.com
FSB52006S Rev. A
FSB52006S Smart Power Module (SPM)
Rev. I15
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an exhaustive list of all such trademarks.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF
THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE
UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF
FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE
PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
ACEx®
Across the board. Around the world.™
ActiveArray™
Bottomless™
Build it Now™
CoolFET™
CROSSVOLT™
CTL™
Current Transfer Logic™
DOME™
E2CMOS™
EcoSPARK®
EnSigna™
FACT Quiet Series™
FACT®
FAST®
FASTr™
FPS™
FRFET®
GlobalOptoisolator™
GTO™
HiSeC™
i-Lo™
ImpliedDisconnect™
IntelliMAX™
ISOPLANAR™
MICROCOUPLER™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR®
PACMAN™
POP™
Power220®
Power247®
PowerEdge™
PowerSaver™
PowerTrench®
Programmable Active Droop™
QFET®
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
ScalarPump™
SMART START™
SPM®
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TCM™
The Power Franchise®
™
TinyBoost™
TinyBuck™
TinyLogic®
TINYOPTO™
TinyPower™
TinyWire™
TruTranslation™
µSerDes™
UHC®
UniFET™
VCX™
Wire™
Datasheet Identification Product Status Definition
Advance Information Formative or In Design This datasheet contains the design specifications for product development.
Specifications may change in any manner without notice.
Preliminary First Production This datasheet contains preliminary data; supplementary data will be pub-
lished at a later date. Fairchild Semiconductor reserves the rig ht to make
changes at any time without notice to improve design.
No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
Obsolete N ot In Production This datasheet contains specifications on a product that has been discontin-
ued by Fairchild semiconductor. The datasheet is printed for reference infor-
mation only.
tm
