July 1997
NEC Electronics Inc.
A12634EU1V0DS00
CMOS-9
3.3-VOLT, 0.35-MICRON
CMOS GATE ARRAYS
Description
NEC's CMOS-9 gate array family provides designers
with the performance capabilities and features required
to develop devices for high-speed computer and
communications systems. NEC combines the highest
performance 0.35-micron drawn gate length (Leff=0.27
micron) 2- and 3-level metal CMOS technology with an
extensive family of interface macros to support very
high-speed system clocks. The high performance I/O
macros including GTL, HSTL, and pECL are under
development. PCI signaling standards are also
supported including 3.3V 66 MHz PCI.
This technology is enhanced by a set of advanced
features including phase-locked loops, clock tree
synthesis, and high-speed memory.
The CMOS-9 gate array family of 3.3-volt devices
consists of 20 masters, offered in densities of 190K raw
gates to 2 million raw gates. Usable gates range from
76K to 1.2 million used gates.
The gate array family is supported by NEC's OpenCAD®
design system; a mixture of popular third-party CAE
tools, and proprietary NEC tools. NEC proprietary tools
include the GALET floorplanner which helps reduce
design cycle time and improve design performance,
clock tree synthesis for clock skew minimization, and
table look-up delay calculator for accurate delay
calculation.
Figure 1. CMOS-9 Package Examples; BGA and QFP
Table 1. CMOS-9 Series Features and Benefits
CMOS-9 Series Features
• 0.35-micron (drawn), 2 and 3-level metal CMOS technology
• Eighteen base arrays with raw gates from 190K to 1.5M
• Narrow pad pitch for maximum gate to pad ratio
• Pad counts from 300 to 1060 pads
• GTL, GTL+, pECL, and all four classes of HSTL
• Full range of 5V-protected I/O buffers
• PCI buffers including 3.3V 66 MHz PCI buffer
• Phase-Locked Loop (DPLL) macros in development
• Low power dissipation: 0.9 µW/MHz/gate
• Extensive package offering: PQFP, TQFP, BGA, TAB
• Clock Tree Synthesis tool automates clock tree design
• Floorplanner supplies layout information for resynthesis
• Popular, third-party CAE tools supported
CMOS-9 Series Benefits
• Delivers dense cell structure and high speed
• Provides many base sizes to give best fit to design needs
• Minimizes device cost
• Supports high I/O integration and wide system bus widths
• Interfaces to high speed memory and processor buses
• Allows interface with 5V logic while protecting 3.3V ASIC
• Supports signaling methods defined in PCI Spec 2.1
• Eliminates clock insertion delay, reduces total clock skew
• Provides low power consumption at high system clock rates
• Delivers customer-specific package requirements
• Minimizes on-chip clock skew for high performance
• Reduces design time and improves device performance
• Enables a smooth flow from customer design to silicon
CMOS-9 Applications
The CMOS-9 family is ideal for use in enterprise
systems, engineering workstations, telecommunications
switching and transmission systems, where extensive
integration and high speeds are primary design goals.
CMOS-9 is well-suited for designs requiring very high
integration (300K-600K gates, 400-600 pins), high
system speeds (100-200 MHz), and high performance
interface standards (HSTL, GTL). CMOS-9 is also well-
suited for lower power applications where high
performance is required. CMOS-9 is offered now at
3.3V and will be released at 2.5V in the future.
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