NJU26902
-1-
Ver.2008-12-01
Digital Audio Delay
General Description
The NJU26902 is a digital audio delay. The NJU26902 provides delay-time
adjustment function and digital audio interface.
FEATURES
• 2-Channel Audio Delay (24 bits data width).
Delay Time 85msec at fs = 48kHz ( 128msec at fs = 32kHz , 43msec at fs = 96kHz)
• To make longer delay time, the NJU26902 can be connected serially.
• Non-audio-signal data can be delayed by the NJU26902.
Hardware Specification
• Digital Audio Interface : 1 Input port, 1 Output port
• Digital Audio Format : LJ / RJ / I
2S 24bit BCK : 64fs / 32fs,
Slave Mode
• Audio Bit Clock (BCK) Frequency : 13MHz Max ( approximate fs=200KHz)
• Package : SSOP20 ( Pb-Free )
• Power Supply : 2.5V ( +3.3V input tolerant )
Function Block Diagram
Fig. 1 Function Block Diagram
Package
NJU26902V
SDO
SDI
Control
Delay
RA M
SERIAL
A
UDI
O
B
CK
L/R outL/R in
NJU26902
SERIAL
AUDIO
RESETb COUNT[5:0] MODE[1:0] SDO_OD BYPASS F
S
LRI
LRI
B
CK
NJU26902
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Pin A ssignment
NJU26902
VDD
RESETb 1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SDI
LRI
COUNT[2]
COUNT[3]
BCKI
COUNT[4]
COUNT[5]
VSS
VSS
VDD
SDO
FS
BYPASS
SDO_OD
COUNT[1]
MODE[1]
COUNT[0]
MODE[0]
Fig. 2 Pin Assignment
Pin Description
Table 1 Pin Description
No. Symbol I/O Description
1 RESETb Ipu
Reset (Ac tive low )
2 SDI I
Audio Data Input
3 LRI I
LR Clock Input
4 COUNT[2] Ipu
Delay T ime Control 2
5 COUNT[3] Ipu
Delay T ime Control 3
6 BCKI I
Bit Clock Input
7 COUNT[4] Ipu
Delay T ime Control 4
8 COUNT[5] Ipu
Delay T ime Control 5
9 VSS -
GND
10 VSS -
GND
11 MODE[0] Ipd
Digital Audio Interface Format Select
12 COUNT[0] Ipu
Delay T ime Control 0
13 MODE[1] Ipu
Digital Audio Interface Format Select
14 COUNT[1] Ipu
Delay T ime Control 1
15 SDO_OD Ipd
SDO pin Open Drain Select
16 BYPASS Ipd
SDO pi n BYPASS Co ntrol
17 FS Ipu
BCK fs Select
18 SDO O
Audio Data Output (CMOS Output / Open Drain Output)
19 VDD -
Power Supply +2.5V
20 VDD -
Power Supply +2.5V
* I : Input
Ipu : Input (internal pull-up)
Ipd : Input (internal pull-down)
O : Output
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Ver .2008-12-01
A bsolute Maximum Ratings
Table2 Absolute Maximum Ratings (VSS=0V, T a=25°
°°
°C )
Parameter Symbol Rating Units
Power Supply V oltage VDD -0.3 to +3 .05 V
Input Pi n V o ltage VTMI -0.3 to +3.6 (VDD ≥ 2.25V)
-0.3 to +3 .05 (VDD < 2.25V) V
SDO Pin V oltage *
(CMOS Ou tput) VTMO -0.3 to +3 .05 V
SDO Pin V oltage *
(Open Drain Output) VTMOD -0.3 to +3.6 (VDD ≥ 2.25V)
-0.3 to +3 .05 (VDD < 2.25V) V
Power Dissipation PD 300 mW
Operating T emperature TOPR -40 to +85 °C
S torage Temperature TSTR -40 to +125 °C
* This specification is applied to VTMO at the SDO pin in case of SDO_OD= Low”.
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Electric Characteristics
Table 3 Electric Characteristics ( VDD=2.5V, VSS=0V , Ta=25°
°°
°C )
Parameter Symbol Test Condition Min. Typ. Max. Units
Operating VDD V o lta ge VDD 2.25 2.5 2.75 V
Operating Current IDD BCKI:13M Hz
SDO:CL=25pF - 1.0 - mA
Operating T emperature TOPR -40 25 85 °C
High Level Input V oltage VIH 2.0 - 3.3 V
Low Level In put V ol tage VIL - - 0.5 V
High Level Output V oltage
(SDO_OD =”Low”) VOH IOH= -2mA
IOH= -100µA VDD-0.4
VDD-0.1 -
- VDD
VDD V
Low Level Ou tput V o lta ge VOL IOL= 2mA
IOL= 100µA 0
0 -
- 0.4
0.1 V
Open D rain Outpu t Current
(SDO_OD=”High”) IOD V
IN= 3.3 V -15 - +15 µA
Input C urrent IIN V
IN= VSS to 3.3 V -15 - +15 µA
Input C urrent
(Internal Pull-up Pin) IIN(PU) V
IN= VSS to 3.3V -100 - +15 µA
Input C urrent
(Internal Pull-down Pin) IIN(PD) V
IN= VSS to 3.3V -15 - +200 µA
Input Capacitance CIN - 10 - pF
Input Ri se/Fall transition T ime tr / tf - - 100 ns
Equivalent Circuit
Input Pin Input Pin Output Pin
(SDI, LRI, BCKI) (Internal Pull-up (PU) : (SDO)
RESETb, MODE[1], FS,
COUNT[5], COUNT[4], COUNT[3],
COUNT[2], COUNT[1], COUNT[0],
Internal Pull-down (PD) :
MODE[0], SDO_OD,BYPASS)
Fig. 3 I/O Equivalent Circuit s
Input
terminal
VDD
VSS
Input
terminal
VDD
VSS
PU
PD
Output
terminal
VDD
VSS
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Ver .2008-12-01
LRI
BC
K
I
tDS tDH
tSIH tLS
I
tSIL tSLI
SDI
SD
O
tDOD
Serial A udio T iming
Table 4 Serial Audio Input Timing Parameters ( VDD=2.5V, V SS=0V, Ta=25°
°°
°C )
Parameter Symbol Test Condition Min Typ. Max Units
BCKI Frequency fBCK - - 13 MHz
BCKI Period
L Pulse Width
H Pulse Width
tSIL
tSIH
35
35 - - ns
BCKI to L RI T ime TSLI 15 - - ns
LRI to BC KI Ti me tLSI 15 - - ns
Data Setup T ime tDS 15 - - ns
Data Hold T ime tDH 15 - - ns
Data Output Delay tDOD SDO:CL=25pF
SDO_OD =”Low” - 15 ns
Fig. 4 Seri al A udio Input / Output Timing
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Serial A udio Interface
Fig. 5-1 I2S Data Format 64fs, 24bit Data
Fig. 5-2 Le f t-J usti fied Dat a Form at 6 4fs, 24bi t Da ta
Fig. 5-3 Right-J usti fie d Dat a Forma t 64fs , 24 bit Dat a
Fig. 5-4 I2S Data Format 32fs, 16bit Data
Fig. 5-5 Lef t-Ju sti fied Dat a Form at 3 2fs, 1 6bi t Da ta
Fig. 5-6 Right-J usti fie d Dat a Forma t 32fs , 16 bit Dat a
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Left Channe l Right Chann el
MSB MSB LSB LSB
32 Clock s 32 Clock s
LRI, LRO
BC KI, BCKO
SD I, SD O
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23
Left Channe l Right Chann el
MSB MSB LSB LSB
32 Clock s 32 Clocks
LRI, LRO
BCKI, BCKO
SDI, SDO
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Left Channe l R ight Chann el
MSB MSB LSB LSB
32 Clock s 32 Clock s
LRI, LRO
BCKI, BCKO
SD I, SDO 0 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Left Channel R ight Chann el
MSB MSB LSB LSB
16 C locks 16 Clock s
LRI, LRO
BC KI, BCKO
SD I, SDO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Left C hannel Right Chann el
MSB MSB LSB LSB
16 Clock s 16 Clock s
LRI, LRO
BCKI, BCK O
SD I, SD O
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Left C hanne l Right Channel
MSB MSB LSB LSB
16 Clock s 16 Clock s
LRI, LRO
BC KI, BCKO
SD I, SDO
NJU26902
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Ver .2008-12-01
Function Description
･SDI(#2) is the serial audio input pin. The input audio signal should be connected to this pin.
･LRI(#3) is the LR clock input pin. The LR clock frequency is the as same as of the input audio signal. In case of I2S
format, if LRI=”Low” SDI and SDO data are left channel data, if LRI=”High” SDI and SDO data are right channel
data.
･BCKI(#6) is the bit clock input pin. This BCKI clock frequency is 32 times (32fs) or 64 times (64fs) of the input
audio signal frequency. The bit precision is 16-bit at 32 fs mode, and 24-bit at 64fs mode.
･MODE [1:0](#13,#11) and FS(#17) pins are used to select serial audio format. Refer to Table 5 “Mode pin, FS pin
Setup” for details.
･SDO(#18) is the serial audio output pin. The delayed audio data come out through this pin.
･S DO is a s the 2. 5V C MOS output in c ase of SDO _OD(# 15)= " Low". SDO is as th e ope n dra in out put i n c ase of
SDO_OD= "H ig h", SDO can be pu lled u p to 3. 3V. In case of S DO_O D= "Low" & BYPA SS= "H igh" , t he bypass
mode is selected.
･T he next combi nation is reser ved. Do not us e this combin ation. S DO_OD= "High" & BYPASS= "H igh". Refer t o
Table 6 “SDO_OD pin, BYPASS pin Setup” for details.
･COUNT [5:0](#8, #7, #5, #4, #14, #12) pins are used to select delay time. When the setup is changed, SDO
outputs a "Low" level (mute) during the period selected by COUNT [5:0]. Refer to 4. Delay T ime for details.
･When RESETb is "L ow", th e NJU26902 is in itia li zed on the rising edge of BCKI. SDO out puts "Lo w" level (mute)
voltage during the period selected by COUNT [5:0].
･In case of not usin g RESETb , connect RE SETb to VDD .
･VDD is the power supply pin. Connect VDD to the 2.5V power supply. VSS is the GND pin. The decoupling
capacitor is necessary between VDD and VSS.
･The input pins can interface with 3.3V ICs. Refer to Table 3 “Electric Characteristics” for details.
･Af ter Power su ppl y or ser ial au dio f orm at chang ing , there is poss ibi lit y the NJ U26 902 g ener ates r andom data f or
the delay time during the period set by COUNT[5:1] pins. If necessary, the mute circuit should be added or reset
the NJU26902.
Table 5 Mode pin, FS pin S etup
FS
(17pin) MODE[1]
(13pin) MODE[0]
(11pin) Setup
0 0 0 RJ 16bit 32fs
0 0 1 LJ 16bit 32fs
0 1 0 I2S 16bit 32fs
1 0 0 RJ 24bit 64fs
1 0 1 LJ 24bit 64fs
1 1 0 I2S 24bit 64fs
Other Reserved *1
* : 0=Low , 1=High
*1 : Do not use.
Table 6 SDO_ OD pi n, B YPAS S pin Se tup
SDO_OD
(15pin) BYPAS S
(16pin) NJU26902 Function
0 0 Delay Operation, SDO=CMOS Output
0 1 Bypass Operation, SDO=CMOS Output
1 0 Delay Ope ration, SD O=Open Drai n Output
1 1 Reserved *1
* : 0=Low , 1=High
*1 : Do not use.
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Delay T ime
･The NJU26902 provides maximum 4097 samples delay and slave-mode audio interface. The delay time depends
on sampling frequency.
･The next formula shows how to calculate the delay time. Refer to Table 7 ”Delay Sample Number Setup
Example”.
Total delay sample number =
COUNT[0]*2048+COUNT[1]*1024+COUNT[2]*512+COUNT[3]*256+COUNT[4]*128+COUNT[5]*64+64+1
Table 7 Delay Sample Numb er Setu p Example
Pin
No. Symbol Count Setting
12 COUNT[0] 2048 0 0 0 1 1 1
14 COUNT[1] 1024 0 0 1 1 1 1
4 COUNT[2] 512 0 0 1 0 1 1
5 COUNT[3] 256 0 0 0 0 1 1
7 COUNT[4] 128 0 0 0 0 1 1
8 COUNT[5] 64 0 1
~
0
~
1
~
0 1
Total Delay Sample
Number 65
(min.) 129 ~ 1601 ~ 3201 ~ 4033 4097
(max.)
Table 8 Sampling Frequency, Delay Sample Number Setup and Delay Time
Delay Time (ms)
Fs 65
(min.) 129 ~ 1601 ~ 3201 ~ 4033 4097
(max.) Delay Sa mple
Number
192kHz 0.3ms 0.7ms 8.3ms 16.7ms 21.0ms 21.3ms
96kHz 0.7ms 1.3ms 16.7ms 33.3ms 42.0ms 42.7ms
88.2kHz 0.7ms 1.5ms 18.2ms 36.3ms 45.7ms 46.5ms
48kHz 1.4ms 2.7ms 33.4ms 66.7ms 84.0ms 85.4ms
44.1kHz 1.5ms 2.9ms 36.3ms 72.6ms 91.5ms 92.9ms
32kHz 2.0ms 4.0ms
~
50.0ms
~
100.0ms
~
126.0ms 128.0ms
NJU26902
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Ver .2008-12-01
Package Dimensions ( SSOP20, Pb-Free )
[CAU TION ]
The specifications on this databook are only
given for information , without any guarantee
as re gards eith er mist akes o r omiss ions . The
application circuits in this databook are
des cribe d only to show repr esent ative usage s
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
0.10
UNIT : mm
