SST39VF1681-70-4C-EKE - MICROCHIP

Microchip Technology Company

Data Sheet

www.microchip.com

16 Mbit (x8) Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Features

• Organized as 2M x8

• Single Voltage Read and Write Operations

– 2.7-3.6V

• Superior Reliability

– Endurance: 100,000 Cycles (Typical)

– Greater than 100 years Data Retention

• Low Power Consumption (typical values at 5 MHz)

– Active Current: 9 mA (typical)

– Standby Current: 3 µA (typical)

– Auto Low Power Mode: 3 µA (typical)

• Hardware Block-Protection/WP# Input Pin

– Top Block-Protection (top 64 KByte)

for SST39VF1682

– Bottom Block-Protection (bottom 64 KByte)

for SST39VF1681

• Sector-Erase Capability

– Uniform 4 KByte sectors

• Block-Erase Capability

– Uniform 64 KByte blocks

• Chip-Erase Capability

• Erase-Suspend/Erase-Resume Capabilities

• Hardware Reset Pin (RST#)

• Security-ID Feature

– SST: 128 bits; User: 128 bits

• Fast Read Access Time:

–70ns

• Latched Address and Data

• Fast Erase and Byte-Program:

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 40 ms (typical)

– Byte-Program Time: 7 µs (typical)

• Automatic Write Timing

– Internal VPP Generation

• End-of-Write Detection

– Toggle Bits

– Data# Polling

• CMOS I/O Compatibility

• JEDEC Standard

– Flash EEPROM Pinouts and Command sets

• Packages Available

– 48-ball TFBGA (6mm x 8mm)

– 48-lead TSOP (12mm x 20mm)

• All devices are RoHS compliant

The SST39VF1681 / SST39VF1682 are 2M x8 CMOS Multi-Purpose Flash Plus

(MPF+) manufactured with SST proprietary, high performance CMOS Super-

Flash® technology. The split-gate cell design and thick-oxide tunneling injector

attain better reliability and manufacturability compared with alternate approaches.

The SST39VF1681 / SST39VF1682 write (Program or Erase) with a 2.7-3.6V

power supply. These devices conforms to JEDEC standard pinouts for x8 memo-

ries.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Product Description

The SST39VF168x devices are 2M x8 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST’s

proprietary, high performance CMOS SuperFlash® technology. The split-gate cell design and thick-oxide

tunneling injector attain better reliability and manufacturability compared with alternate approaches. The

SST39VF168x write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC

standard pinouts for x8 memories.

Featuring high performance Byte-Program, the SST39VF168x devices provide a typical Byte-Program

time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program

operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protec-

tion schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices

are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater

than 100 years.

The SST39VF168x devices are suited for applications that require convenient and economical updat-

ing of program, configuration, or data memory. For all system applications, they significantly improve

performance and reliability, while lowering power consumption. They inherently use less energy during

Erase and Program than alternative flash technologies. The total energy consumed is a function of the

applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash

technology uses less current to program and has a shorter erase time, the total energy consumed dur-

ing any Erase or Program operation is less than alternative flash technologies. These devices also

improve flexibility while lowering the cost for program, data, and configuration storage applications.

The SuperFlash technology provides fixed Erase and Program times, independent of the number of

Erase/Program cycles that have occurred. Therefore the system software or hardware does not have

to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-

gram times increase with accumulated Erase/Program cycles.

To meet high density, surface mount requirements, the SST39VF168x are offered in both 48-ball TFBGA

and 48-lead TSOP packages. See Figures 2 and 3 for pin assignments.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Block Diagram

Figure 1: SST39VF1681 / SST39VF1682 Block Diagram

Pin Description

Figure 2: Pin Assignments for 48-lead TFBGA

Y-Decoder

I/O Buffers and Data Latches

1243 B1.0

Address Buffer Latches

X-Decoder

DQ7-DQ

Memory Address

OE#

CE#

WE#

SuperFlash

Memory

Control Logic

WP#

RESET#

1243 48-tfbga B3K P1.0

TOP VIEW (balls facing down)

A14

A10

WE#

A13

RST#

WP#

A18

A15

A11

A19

A16

A12

A20

A17

DQ7

DQ5

DQ2

DQ0

CE#

VDD

OE#

VSS

DQ6

DQ4

DQ3

DQ1

VSS

ABCDEFGH

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 3: Pin Assignments for 48-lead TSOP

Table 1: Pin Description

Symbol Pin Name Functions

AMS1-A0

1. AMS = Most significant address

AMS =A

20 for SST39VF1681/1682

Address Inputs To provide memory addresses.

During Sector-Erase AMS-A12 address lines will select the sector.

During Block-Erase AMS-A16 address lines will select the block.

DQ7-DQ0Data Input/output To output data during Read cycles and receive input data during Write cycles.

Data is internally latched during a Write cycle.

The outputs are in tri-state when OE# or CE# is high.

WP# Write Protect To protect the top/bottom boot block from Erase/Program operation when

grounded.

RST# Reset To reset and return the device to Read mode.

CE# Chip Enable To activate the device when CE# is low.

OE# Output Enable To gate the data output buffers.

WE# Write Enable To control the Write operations.

VDD Power Supply To provide power supply voltage: 2.7-3.6V

VSS Ground

NC No Connection Unconnected pins.

T1.1 25040

A17

VSS

DQ7

DQ6

DQ5

DQ4

VDD

DQ3

DQ2

DQ1

DQ0

OE#

VSS

CE#

1243 48-tsop P2.0

Standard Pinout

To p V i e w

Die Up

A16

A15

A14

A13

A12

A11

A10

A20

WE#

RST#

WP#

A19

A18

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Device Operation

Commands are used to initiate the memory operation functions of the device. Commands are written

to the device using standard microprocessor write sequences. A command is written by asserting WE#

low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever

occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first.

The SST39VF168x also have the Auto Low Power mode which puts the device in a near standby

mode after data has been accessed with a valid Read operation. This reduces the IDD active read cur-

rent from typically 9 mA to typically 3 µA. The Auto Low Power mode reduces the typical IDD active

read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode

with any address transition or control signal transition used to initiate another Read cycle, with no

access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with

CE# held steadily low, until the first address transition or CE# is driven high.

Read

The Read operation of the SST39VF168x is controlled by CE# and OE#, both have to be low for the system

to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected

and only standby power is consumed. OE# is the output control and is used to gate data from the output

pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle tim-

ing diagram for further details (Figure 4).

Byte-Program Operation

The SST39VF168x are programmed on a byte-by-byte basis. Before programming, the sector where

the byte exists must be fully erased. The Program operation is accomplished in three steps. The first

step is the three-byte load sequence for Software Data Protection. The second step is to load byte

address and byte data. During the Byte-Program operation, the addresses are latched on the falling

edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE#

or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after

the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initi-

ated, will be completed within 10 µs. See Figures 5 and 6 for WE# and CE# controlled Program opera-

tion timing diagrams and Figure 20 for flowcharts. During the Program operation, the only valid reads

are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform

additional tasks. Any commands issued during the internal Program operation are ignored. During the

command sequence, WP# should be statically held high or low.

Sector/Block-Erase Operation

The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or

block-by-block) basis. The SST39VF168x offer both Sector-Erase and Block-Erase mode. The sector

architecture is based on uniform sector size of 4 KByte. The Block-Erase mode is based on uniform

block size of 64 KByte. The Sector-Erase operation is initiated by executing a six-byte command

sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-

Erase operation is initiated by executing a six-byte command sequence with Block-Erase command

(30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling

edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth

WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase opera-

tion can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

timing waveforms and Figure 24 for the flowchart. Any commands issued during the Sector- or Block-

Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the protected

block will be ignored. During the command sequence, WP# should be statically held high or low.

Erase-Suspend/Erase-Resume Commands

The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing

data to be read from any memory location, or program data into any sector/block that is not suspended

for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-

Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the

Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not

suspended from an Erase operation. Reading at address location within erase-suspended sectors/

blocks will output DQ2toggling and DQ6at “1”. While in Erase-Suspend mode, a Byte-Program opera-

tion is allowed except for the sector or block selected for Erase-Suspend.

To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase

Resume command. The operation is executed by issuing one byte command sequence with Erase Resume com-

mand (30H) at any address in the last Byte sequence.

Chip-Erase Operation

The SST39VF168x provide a Chip-Erase operation, which allows the user to erase the entire memory array to

the “1” state. This is useful when the entire device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase command

(10H) at address AAAH in the last byte sequence. The Erase operation begins with the rising edge of the sixth

WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Poll-

ing. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 24 for the flowchart.

Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-

Erase will be ignored. During the command sequence, WP# should be statically held high or low.

Write Operation Status Detection

The SST39VF168x provide two software means to detect the completion of a Write (Program or

Erase) cycle, in order to optimize the system write cycle time. The software detection includes two sta-

tus bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after

the rising edge of WE#, which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data#

Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the sys-

tem may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7or DQ6.In

order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop

to read the accessed location an additional two (2) times. If both reads are valid, then the device has com-

pleted the Write cycle, otherwise the rejection is valid.

Data# Polling (DQ7)

When the SST39VF168x are in the internal Program operation, any attempt to read DQ7will produce the

complement of the true data. Once the Program operation is completed, DQ7will produce true data. Note that

even though DQ7may have valid data immediately following the completion of an internal Write operation, the

remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent succes-

sive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7will pro-

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

duce a ‘0’. Once the internal Erase operation is completed, DQ7will produce a ‘1’. The Data# Polling is valid

after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase,

the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 7 for Data# Polling tim-

ing diagram and Figure 21 for a flowchart.

Toggle Bits (DQ6 and DQ2)

During the internal Program or Erase operation, any consecutive attempts to read DQ6will produce

alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation

is completed, the DQ6bit will stop toggling. The device is then ready for the next operation. For Sector-

, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse.

DQ6will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-

gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6will toggle.

An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6to check

whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status

bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of

Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.

Note: DQ7and DQ2require a valid address when reading status information.

Data Protection

The SST39VF168x provide both hardware and software features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.

VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V.

Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-

vents inadvertent writes during power-up or power-down.

Table 2: Write Operation Status

Status DQ7DQ6DQ2

Normal Operation Standard Program DQ7# Toggle No Toggle

Standard Erase 0 Toggle Toggle

Erase-Suspend Mode Read from Erase Suspended Sector/Block 1 1 Toggle

Read from Non- Erase Suspended Sector/Block Data Data Data

Program DQ7# Toggle N/A

T2.0 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Hardware Block Protection

The SST39VF1682 supports top hardware block protection, which protects the top 64 KByte block of

the device. The SST39VF1681 supports bottom hardware block protection, which protects the bottom

64 KByte block of the device. The Boot Block address ranges are described in Table 3. Program and

Erase operations are prevented on the 64 KByte when WP# is low. If WP# is left floating, it is internally

held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase opera-

tions on that block.

Hardware Reset (RST#)

The RST# pin provides a hardware method of resetting the device to read array data. When the RST#

pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When

no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST#

is driven high before a valid Read can take place (see Figure 16).

The Erase or Program operation that has been interrupted needs to be re-initiated after the device

resumes normal operation mode to ensure data integrity.

Software Data Protection (SDP)

The SST39VF168x provide the JEDEC approved Software Data Protection scheme for all data altera-

tion operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-

byte sequence. The three-byte load sequence is used to initiate the Program operation, providing opti-

mal protection from inadvertent Write operations, e.g., during the system power-up or power-down.

Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the

Software Data Protection permanently enabled. See Table 6 for the specific software command codes.

During SDP command sequence, invalid commands will abort the device to Read mode within TRC.

Common Flash Memory Interface (CFI)

The SST39VF168x also contain the CFI information to describe the characteristics of the device. In order to

enter the CFI Query mode, the system must write three-byte sequence, same as product ID entry command

with 98H (CFI Query command) to address AAAH in the last byte sequence. Once the device enters the CFI

Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write

the CFI Exit command to return to Read mode from the CFI Query mode.

Table 3: Boot Block Address Ranges

Product Address Range

Bottom Boot Block

SST39VF1681 000000H-00FFFFH

Top Boot Block

SST39VF1682 1F0000H-1FFFFFH

T3.1 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Product Identification

The Product Identification mode identifies the devices as the SST39VF1681 and SST39VF1682, and manu-

facturer as SST. Users may use the software Product Identification operation to identify the part (i.e., using

the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software

operation, Figure 12 for the software ID Entry and Read timing diagram, and Figure 22 for the software ID

Entry command sequence flowchart.

Product Identification Mode Exit/CFI Mode Exit

In order to return to the standard Read mode, the Software Product Identification mode must be exited.

Exit is accomplished by issuing the software ID Exit command sequence, which returns the device to

the Read mode. This command may also be used to reset the device to the Read mode after any inad-

vertent transient condition that apparently causes the device to behave abnormally, e.g., not read cor-

rectly. Please note that the software ID Exit/CFI Exit command is ignored during an internal Program or

Erase operation. See Table 6 for software command codes, Figure 14 for timing waveform, and Figures

22 and 23 for flowcharts.

Security ID

The SST39VF168x devices offer a 256-bit Security ID space which is divided into two 128-bit seg-

ments. The first segment is programmed and locked at SST with a random 128-bit number. The user

segment is left un-programmed for the customer to program as desired.

To program the user segment of the Security ID, the user must use the Security ID Byte-Program com-

mand. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this

is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any

future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec

ID segment can be erased.

The Security ID space can be queried by executing a three-byte command sequence with Enter-Sec-

ID command (88H) at address AAAH in the last byte sequence. Execute the Exit-Sec-ID command to

exit this mode. Refer to Table 6 for more details.

Table 4: Product Identification

Address Data

Manufacturer’s ID 0000H BFH

Device ID

SST39VF1681 0001H C8H

SST39VF1682 0001H C9H

T4.1 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Operations

Table 5: Operation Modes Selection

Mode CE# OE# WE# DQ Address

Read VIL VIL VIH DOUT AIN

Program VIL VIH VIL DIN AIN

Erase VIL VIH VIL X1

1. X can be VIL or VIH, but no other value.

Sector or block address,

XXH for Chip-Erase

Standby VIH X X High Z X

Write Inhibit X VIL X High Z/ DOUT X

XXV

IH High Z/ DOUT X

Product Identification

Software Mode VIL VIL VIH See Table 6

T5.0 25040

Table 6: Software Command Sequence

Command

Sequence

1st Bus

Write Cycle

2nd Bus

Write Cycle

3rd Bus

Write Cycle

4th Bus

Write Cycle

5th Bus

Write Cycle

6th Bus

Write Cycle

Addr1

1. Address format A11-A0(Hex).

Addresses A20-A12 can be VIL or VIH, but no other value, for Command sequence for SST39VF1681/1682.

Data Addr1Data Addr1Data Addr1Data Addr1Data Addr1Data

Byte-Program AAAH AAH 555H 55H AAAH A0H BA2

2. BA = Program Byte Address

Data

Sector-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H SAX3

3. SAXfor Sector-Erase; uses AMS-A12 address lines

BAX, for Block-Erase; uses AMS-A16 address lines

AMS = Most significant address

AMS =A

20 for SST39VF1681/1682

50H

Block-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H BAX330H

Chip-Erase AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H AAAH 10H

Erase-Suspend

XXXXH

B0H

Erase-Resume

XXXXH

30H

Query Sec ID4AAAH AAH 555H 55H AAAH 88H

User Security ID

Byte-Program

AAAH AAH 555H 55H AAAH A5H BA5Data

User Security ID

Program Lock-Out

AAAH AAH 555H 55H AAAH 85H XXH500H

Software ID

Entry6,7 AAAH AAH 555H 55H AAAH 90H

CFI Query Entry AAAH AAH 555H 55H AAAH 98H

Software ID Exit8,9

/CFI Exit/Sec ID

Exit

AAAH AAH 555H 55H AAAH F0H

Software ID Exit8,9

/CFI Exit/Sec ID

Exit

XXH F0H

T6.1 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

4. With AMS-A5= 0; Sec ID is read with A4-A0,

SST ID is read with A4= 0 (Address range = 00000H to 0000FH),

User ID is read with A4= 1 (Address range = 00010H to 0001FH).

Lock Status is read with A7-A0= 0000FFH. Unlocked: DQ3= 1 / Locked: DQ3=0.

5. Valid Byte Addresses for Sec ID are from 000000H-00000FH and 000020H-00002FH.

6. The device does not remain in Software Product ID Mode if powered down.

7. With AMS-A1=0; SST Manufacturer ID = 00BFH, is read with A0=0,

SST39VF1681 Device ID = C8H, is read with A0=1,

SST39VF1682 Device ID = C9H, is read with A0=1,

AMS = Most significant address

AMS =A

20 for SST39VF1681/1682

8. Both Software ID Exit operations are equivalent

9. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1)

using the Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).

Table 7: CFI Query Identification String1

1. Refer to CFI publication 100 for more details.

Address Data Data

10H 51H Query Unique ASCII string “QRY”

11H 52H

12H 59H

13H 01H Primary OEM command set

14H 07H

15H 00H Address for Primary Extended Table

16H 00H

17H 00H Alternate OEM command set (00H = none exists)

18H 00H

19H 00H Address for Alternate OEM extended Table (00H = none exits)

1AH 00H

T7.1 25040

Table 8: System Interface Information

Address Data Data

1BH 27H VDD Min (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1CH 36H VDD Max (Program/Erase)

DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts

1DH 00H VPP min. (00H = no VPP pin)

1EH 00H VPP max. (00H = no VPP pin)

1FH 03H Typical time out for Byte-Program 2Nµs (23= 8 µs)

20H 00H Typical time out for min. size buffer program 2Nµs (00H = not supported)

21H 04H Typical time out for individual Sector/Block-Erase 2Nms (24=16ms)

22H 05H Typical time out for Chip-Erase 2Nms (25=32ms)

23H 01H Maximum time out for Byte-Program 2Ntimes typical (21x2

3=16µs)

24H 00H Maximum time out for buffer program 2Ntimes typical

25H 01H Maximum time out for individual Sector/Block-Erase 2Ntimes typical (21x2

4=32ms)

26H 01H Maximum time out for Chip-Erase 2Ntimes typical (21x2

5=64ms)

T8.1 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Table 9: Device Geometry Information

Address Data Data

27H 15H Device size = 2NBytes (15H = 21; 221 = 2 MByte)

28H 00H Flash Device Interface description; 00H = x8-only asynchronous interface

29H 00H

2AH 00H Maximum number of byte in multi-byte write = 2N(00H = not supported)

2BH 00H

2CH 02H Number of Erase Sector/Block sizes supported by device

2DH FFH Sector Information (y+1=Number of sectors; z x 256B = sector size)

2EH 01H y=511+1=512sectors (01FF = 511

2FH 10H

30H 00H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)

31H 1FH Block Information (y+1=Number of blocks; z x 256B = block size)

32H 00H y=31+1=32blocks(1F=31)

33H 00H

34H 01H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)

T9.1 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute

Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these conditions or conditions greater than those defined in the

operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating con-

ditions may affect device reliability.)

Temperature Under Bias ............................................. -55°C to +125°C

Storage Temperature ................................................ -65°C to +150°C

D. C. Voltage on Any Pin to Ground Potential ............................-0.5V to VDD+0.5V

Transient Voltage (<20 ns) on Any Pin to Ground Potential ..................-2.0V to VDD+2.0V

Voltage on A9Pin to Ground Potential .....................................-0.5V to 13.2V

Package Power Dissipation Capability (Ta = 25°C) .................................. 1.0W

Surface Mount Lead Soldering Temperature (3 Seconds) ............................ 240°C

Output Short Circuit Current1.................................................. 50mA

1. Outputs shorted for no more than one second. No more than one output shorted at a time.

Table 10:Operating Range

Range Ambient Temp VDD

Commercial 0°C to +70°C 2.7-3.6V

Industrial -40°C to +85°C 2.7-3.6V

T10.1 25040

Table 11:AC Conditions of Test1

1. See Figures 18 and 19

Input Rise/Fall Time Output Load

5ns CL=30pF

T11.1 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Table 12:DC Operating Characteristics VDD = 2.7-3.6V1

Symbol Parameter

Limits

Test ConditionsMin Max Units

IDD Power Supply Current Address input=VILT/VIHT2, at f=5 MHz,

VDD=VDD Max

Read318 mA CE#=VIL, OE#=WE#=VIH, all I/Os

open

Program and Erase 35 mA CE#=WE#=VIL, OE#=VIH

ISB Standby VDD Current 20 µA CE#=VIHC,V

DD=VDD Max

IALP Auto Low Power 20 µA CE#=VILC,V

DD=VDD Max

All inputs=VSS or VDD, WE#=VIHC

ILI Input Leakage Current 1 µA VIN=GND to VDD,V

DD=VDD Max

ILIW Input Leakage Current

on WP# pin and RST#

10 µA WP#=GND to VDD or RST#=GND to

VDD

ILO Output Leakage Current 10 µA VOUT=GND to VDD,V

DD=VDD Max

VIL Input Low Voltage 0.8 V VDD=VDD Min

VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max

VIH Input High Voltage 0.7VDD VV

DD=VDD Max

VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max

VOL Output Low Voltage 0.2 V IOL=100 µA, VDD=VDD Min

VOH Output High Voltage VDD-0.2 V IOH=-100 µA, VDD=VDD Min

T12.8 25040

1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C

(room temperature), and VDD = 3V. Not 100% tested.

2. See Figure 18

3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V.

Table 13:Recommended System Power-up Timings

Symbol Parameter Minimum Units

TPU-READ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

Power-up to Read Operation 100 µs

TPU-WRITE1Power-up to Program/Erase Operation 100 µs

T13.0 25040

Table 14:Capacitance (Ta = 25°C, f=1 MHz, other pins open)

Parameter Description Test Condition Maximum

CI/O1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

I/O Pin Capacitance VI/O =0V 12pF

CIN1Input Capacitance VIN =0V 6pF

T14.0 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

AC Characteristics

Table 15:Reliability Characteristics

Symbol Parameter Minimum Specification Units Test Method

NEND1,2 Endurance 10,000 Cycles JEDEC Standard A117

TDR1Data Retention 100 Years JEDEC Standard A103

ILTH1Latch Up 100 + IDD mA JEDEC Standard 78

T15.2 25040

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would

result in a higher minimum specification.

Table 16:Read Cycle Timing Parameters VDD = 2.7-3.6V

Symbol Parameter

SST39VF168x-70

UnitsMin Max

TRC Read Cycle Time 70 ns

TCE Chip Enable Access Time 70 ns

TAA Address Access Time 70 ns

TOE Output Enable Access Time 35 ns

TCLZ1

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

CE# Low to Active Output 0 ns

TOLZ1OE# Low to Active Output 0 ns

TCHZ1CE# High to High-Z Output 20 ns

TOHZ1OE# High to High-Z Output 20 ns

TOH1Output Hold from Address Change 0 ns

TRP1RST# Pulse Width 500 ns

TRHR1RST# High before Read 50 ns

TRY1,2

2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.

This parameter does not apply to Chip-Erase operations.

RST# Pin Low to Read Mode 20 µs

T16.1 25040

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Table 17:Program/Erase Cycle Timing Parameters

Symbol Parameter Min Max Units

TBP Byte-Program Time 10 µs

TAS Address Setup Time 0 ns

TAH Address Hold Time 30 ns

TCS WE# and CE# Setup Time 0 ns

TCH WE# and CE# Hold Time 0 ns

TOES OE# High Setup Time 0 ns

TOEH OE# High Hold Time 10 ns

TCP CE# Pulse Width 40 ns

TWP WE# Pulse Width 40 ns

TWPH1WE# Pulse Width High 30 ns

TCPH1CE# Pulse Width High 30 ns

TDS Data Setup Time 30 ns

TDH1Data Hold Time 0 ns

TIDA1Software ID Access and Exit Time 150 ns

TSE Sector-Erase 25 ms

TBE Block-Erase 25 ms

TSCE Chip-Erase 50 ms

T17.0 25040

1. This parameter is measured only for initial qualification and after a design or process change that could affect this

parameter.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 4: Read Cycle Timing Diagram

Figure 5: WE# Controlled Program Cycle Timing Diagram

1243 F02.0

ADDRESS AMS-0

DQ15-0

WE#

OE#

CE#

TCE

TRC TAA

TOE

TOLZ

VIH

HIGH-Z

TCLZ TOH TCHZ

HIGH-Z

DATA VALIDDATA VALID

TOHZ

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

1243 F03.2

ADDRESS AMS-0

DQ7-0

TDH

TWPH

TDS

TWP

TAH

TAS

TCH

TCS

CE#

SW0 SW1 SW2

AAA AAA555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

WE#

TBP

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 6: CE# Controlled Program Cycle Timing Diagram

Figure 7: Data# Polling Timing Diagram

1243 F04.2

ADDRESS AMS-0

DQ7-0

TDH

TCPH

TDS

TCP

TAH

TAS

TCH

TCS

WE#

SW0 SW1 SW2

AAA AAA555 ADDR

AA 55 A0 DATA

INTERNAL PROGRAM OPERATION STARTS

BYTE

(ADDR/DATA)

OE#

CE#

TBP

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

1243 F05.1

ADDRESS AMS-0

DQ7DATA DATA # DATA # DATA

WE#

OE#

CE#

TOEH

TOE

TCE

TOES

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 8: Toggle Bits Timing Diagram

Figure 9: WE# Controlled Chip-Erase Timing Diagram

1243 F06.1

ADDRESS AMS-0

DQ6and DQ2

WE#

OE#

CE#

TOE

TOEH

TCE

TOES

TWO READ CYCLES

WITH SAME OUTPUTS

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

1243 F07.1

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

AAA AAA AAA555 AAA

55 1055AA 80 AA

555

OE#

CE#

SIX-BYTE CODE FOR CHIP-ERASE

SCE

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 17.)

AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 10:WE# Controlled Block-Erase Timing Diagram

1243 F08.1

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

55 3055AA 80 AA

BAX

OE#

CE#

SIX-BYTE CODE FOR BLOCK-ERASE

TBE

TWP

AAA AAA555 AAA 555

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 17.)

BAX= Block Address

AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 11:WE# Controlled Sector-Erase Timing Diagram

1243 F9.1

ADDRESS AMS-0

DQ7-0

WE#

SW0 SW1 SW2 SW3 SW4 SW5

55 5055AA 80 AA

SAX

OE#

CE#

SIX-BYTE CODE FOR SECTOR-ERASE

TSE

TWP

AAA AAA555 AAA 555

Note: This device also supports CE# controlled Chip-Erase operation.

The WE# and CE# signals are interchangeable as long as minimum timings are meet. (See Table 17.)

SAX= Sector Address

AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 12:Software ID Entry and Read

Figure 13:CFI Query Entry and Read

1243 F10.1

ADDRESS AMS-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

AAA AAA555 0000 0001

OE#

CE#

THREE-BYTE SEQUENCE FOR

SOFTWARE ID ENTRY

TWP

TWPH TAA

BF Device ID55AA 90

Note: Device ID - See Table 4 on page 9

AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

1243 F11.2

ADDRESS AMS-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

555 AAAAAA

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

55AA 98

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 14:Software ID Exit/CFI Exit

Figure 15:Sec ID Entry

1243 F12.2

ADDRESS AMS-0

DQ7-0

TIDA

TWP

TWHP

WE#

SW0 SW1 SW2

AAA AAA555

THREE-BYTE SEQUENCE FOR

SOFTWARE ID EXIT AND RESET

OE#

CE#

AA 55 F0

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

1243 F13.1

ADDRESS AMS-0

TIDA

DQ7-0

WE#

SW0 SW1 SW2

AAA AAA555

OE#

CE#

THREE-BYTE SEQUENCE FOR

CFI QUERY ENTRY

TWP

TWPH TAA

55AA 88

Note: AMS = Most Significant Address

AMS =A

20 for SST39VF168x

WP# must be held in proper logic state (VIL or VIH) 1 µs prior to and 1 µs after the command sequence.

X can be VIL or VIH, but no other value.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 16:RST# Timing Diagram (When no internal operation is in progress)

Figure 17:RST# Timing Diagram (During Program or Erase operation)

1243 F14.0

RST#

CE#/OE#

TRP

TRHR

1243 F15.0

RST#

CE#/OE#

TRP

TRY

End-of-Write Detection

(Toggle-Bit)

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 18:AC Input/Output Reference Waveforms

Figure 19:A Test Load Example

1243 F16.0

REFERENCE POINTS OUTPUTINPUT

IHT

ILT

AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Mea-

surement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input

rise and fall times (10% 90%) are <5 ns.

Note: VIT -V

INPUT Test

VOT -V

OUTPUT Test

VIHT -V

INPUT HIGH Test

VILT -V

INPUT LOW Test

1243 F17.0

TO TESTER

TO DUT

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 20:Byte-Program Algorithm

1243 F18.0

Start

Load data: AAH

Address: AAAH

Load data: 55H

Address: 555H

Load data: A0H

Address: AAAH

Load Word

Address/Word

Data

Wait for end of

Program (TBP,

Data# Polling

bit, or Toggle bit

operation)

Program

Completed

X can be VIL or VIH, but no other value

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 21:Wait Options

1243 F19.0

Wait TBP,

TSCE, TSE

or TBE

Program/Erase

Initiated

Internal Timer Toggle Bit

Ye s

Program/Erase

Completed

Does DQ6

match

Read same

word

Data# Polling

Program/Erase

Completed

Program/Erase

Completed

Read word

Is DQ7=

true data

Read DQ7

Program/Erase

Initiated

Program/Erase

Initiated

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 22:Software ID/CFI Entry Command Flowcharts

1243 F20.0

Load data: AAH

Address: AAAH

Software Product ID Entry

Command Sequence

Load data: 55H

Address: 555H

Load data: 90H

Address: 5555H

Wait TIDA

Read Software ID

Load data: AAH

Address: AAAH

CFI Query Entry

Command Sequence

Load data: 55H

Address: 555H

Load data: 98H

Address: AAAH

Wait TIDA

Read CFI data

Load data: AAH

Address: AAAH

Sec ID Query Entry

Command Sequence

Load data: 55H

Address: 555H

Load data: 88H

Address: AAAH

Wait TIDA

Read Sec ID

X can be VIL or VIH, but no other value

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 23:Software ID/CFI Exit Command Flowcharts

1243 F21.0

Load data: AAH

Address: AAAH

Software ID Exit/CFI Exit/Sec ID Exit

Command Sequence

Load data: 55H

Address: 555H

Load data: F0H

Address: AAAH

Load data: F0H

Address: XXH

Return to normal

operation

Wait TIDA

Return to normal

operation

X can be VIL or VIH, but no other value

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 24:Erase Command Sequence

1243 F22.0

Load data: AAH

Address: AAAH

Chip-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 10H

Address: AAAH

Load data: AAH

Address: AAAH

Wait TSCE

Chip erased

to FFFFH

Load data: AAH

Address: AAAH

Sector-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 50H

Address: SAX

Load data: AAH

Address: AAAH

Wait TSE

Sector erased

to FFFFH

Load data: AAH

Address: AAAH

Block-Erase

Command Sequence

Load data: 55H

Address: 555H

Load data: 80H

Address: AAAH

Load data: 55H

Address: 555H

Load data: 30H

Address: BAX

Load data: AAH

Address: AAAH

Wait TBE

Block erased

to FFFFH

X can be VIL or VIH, but no other value

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Product Ordering Information

Valid Combinations for SST39VF1681

SST39VF1681-70-4C-EKE SST39VF1681-70-4C-B3KE

SST39VF1681-70-4I-EKE SST39VF1681-70-4I-B3KE

Valid Combinations for SST39VF1682

SST39VF1682-70-4C-EKE SST39VF1682-70-4C-B3KE

SST39VF1682-70-4I-EKE SST39VF1682-70-4I-B3KE

Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales

representative to confirm availability of valid combinations and to determine availability of new combinations.

SST 39 VF 1681 - 70 - 4C - B3KE

XX XX XXXX - XX - XX -XXXX

Environmental Attribute

E1= non-Pb

Package Modifier

K = 48 leads

Package Type

B3 = TFBGA (6mm x 8mm, 0.8mm pitch)

E = TSOP (type1, die up, 12mm x 20mm)

Temperature Range

C = Commercial = 0°C to +70°C

I = Industrial = -40°C to +85°C

Minimum Endurance

4 = 10,000 cycles

Read Access Speed

70=70ns

Hardware Block Protection

1 = Bottom Boot-Block

2 = Top Boot-Block

Device Density

168 = 16 Mbit

Voltage

V = 2.7-3.6V

Product Series

39 = Multi-Purpose Flash

1. Environmental suffix “E” denotes non-Pb solder.

SST non-Pb solder devices are “RoHS Compliant”.

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Packaging Diagrams

Figure 25:48-lead Thin Small Outline Package (TSOP) 12mm x 20mm

SST Package Code: EK

1.05

0.95

0.70

0.50

18.50

18.30

20.20

19.80

0.70

0.50

12.20

11.80

0.27

0.17

0.15

0.05

48-tsop-EK-8

Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,

although some dimensions may be more stringent.

2. All linear dimensions are in millimeters (max/min).

3. Coplanarity: 0.1 mm

4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.

1.20

max.

1mm

0°- 5°

DETAIL

Pin # 1 Identifier

0.50

BSC

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Figure 26:48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm

SST Package Code: B3K

A1 CORNER

HGFEDCBA

ABCDEFGH

BOTTOM VIEWTOP VIEW

SIDE VIEW

SEATING PLANE

0.35 0.05

1.10 0.10

0.12

6.00 0.10

0.45 0.05

(48X)

A1 CORNER

8.00 0.10

0.80

4.00

0.80

5.60

48-tfbga-B3K-6x8-450mic-5

Note: 1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent.

2. All linear dimensions are in millimeters.

3. Coplanarity: 0.12 mm

4. Ball opening size is 0.38 mm ( 0.05 mm)

1mm

16 Mbit Multi-Purpose Flash Plus

SST39VF1681 / SST39VF1682

Data Sheet

Microchip Technology Company

Table 18:Revision History

Number Description Date

00 •Initial release May 2003

01 •Change product number from 166x to 168x Sep 2003

02 •Added B3K package and associated MPNs (See page 31)

•Removed 90 ns Commercial temperature for the EK and EKE packages

Oct 2003

03 •2004 Data Book

•Updated B3K package diagram

Nov 2003

A•Updated document status to “Data Sheet.”

•Removed all 90ns information. Edited “Features” on page 1, “Product

Ordering Information” on page 31, and Table 16 on page 15.

•Updated TIDA information in Table 17 on page 16

•Applied new document format

•Released document under the letter revision system

•Updated spec number from S71243 to DS25040

May 2011

SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Tech-

nology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and

registered trademarks mentioned herein are the property of their respective owners.

Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current

package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging.

Memory sizes denote raw storage capacity; actual usable capacity may be less.

SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of

Sale.

For sales office(s) location and information, please see www.microchip.com.

Silicon Storage Technology, Inc.

A Microchip Technology Company

www.microchip.com

ISBN:978-1-61341-202-2