NCP1399 Series
www.onsemi.com
37
1. Application start, Brown−out off and restart,
OVP/OTP latch and then restart – Figure 61
Application is connected to the mains at point A thus the
HV input of the controller becomes biased. The HV startup
current source starts charged VCC capacitor until VCC
reaches VCC_ON threshold.
The VCC pin voltage reached VCC_ON threshold in point
B. The BO, FB, OVP/OTP and PFC MODE blocks are
enabled. The REM input is internally pulled down for
tREM_TIMER to assure that the secondary side will have enough
time to recover normal operation and pulls down the remote
optocoupler after the LLC stage restart. The VBULK/PFC
FB pin starts to receive divided bulk voltage as the external
HV switch is activated by PFC MODE output. The REM
timer is activated during each VCC_ON event except during
the off−mode operation. The VCC blank is also activated
during each VCC_ON event to ensure that the internal logic
ignores all fault inputs until the internal blocks are fully
biased and stabilized after a VCC_ON event. The IC DRVs
were not enabled after first VCC blank period in this case as
the voltage on VBULK/PFC FB is below VBO level. The IC
keeps all internal blocks biased and operates in the DSS
(Dynamic Self−Supply) mode as long as the fault conditions
is still present.
The BO_OK condition is received (voltage on
VBULK/PFC FB reach VBO level) at point C. The IC
activates the startup current source to refill VCC capacitor
in order to assure sufficient energy for a new startup. The
VCC capacitor voltage reaches VCC_ON level again and the
VCC blank period is started. The REM timer is activated
again on this VCC_ON event as well. The DRVs are enabled
and the application is started after VCC blank period lapses
because there is no faults condition at that time.
Line and also bulk voltage drops at point D so the BO_OK
signal become low (voltage on VBULK/PFC FB drops
below VBO level). The LLC DRVs are disabled as well as
OVP/OTP block bias. The PFC MODE output stay high to
keep the bulk voltage divider connected, so the BO block
still monitors the bulk voltage. The controller activates the
HV startup current source into DSS mode to keep enough
VCC voltage for operation of all blocks that are active while
the IC is waiting for BO_OK condition.
The line voltage and thus also bulk voltage increase at
point E so the Brown−out block provide the BO_OK signal
once the VBO level is reached. The startup current source is
activated after BO_OK signal is received to charge the VCC
capacitor for a new restart.
The VCC_ON level is reached in point F. The OVP/OTP
block is biased, REM timer and the VCC blank period is
started at the same time. The controller restores operation
via the regular startup sequence and soft−start after VCC
blank period lapses since there is no fault condition detected.
The application then operates normally until the
OVP/OTP input is pulled−up at point G. The controller then
enters latch−off mode in which all blocks are disabled except
for the feedback block. The VCC management controls the
HV startup in DSS mode in order to keep enough VCC level
to hold the latch−up state memorized while the application
remains plugged−in to the mains.
The power supply is removed from the mains at point H
and the VCC voltage drops down below VCC_RESET level
thus the low voltage controller is released from latch. A new
application start occurs when the user plugs the application
the mains again.
2. Application start, Brown−out off and restart, output
short fault with auto−recovery restart – Figure 62
Operating waveforms descriptions for this figure is
similar to one for Figure 61 from point A till point G – with
one difference. The skip mode operation (FB <
VFB_SKIP_IN) blocks the IC startup after first VCC_ON event
instead of BO_fault.
The LLC converter operation is stopped in point G
because the controller detects an overload condition (short
circuit event in this case as the Vout drops abruptly). The
controller disables all blocks except for the FB block and the
fault logic. The HV startup DSS operation is initiated in
order to keep enough VCC level for all internal blocks that
need to be biased. Internal auto−recovery timer counts down
the recovery delay period tA−REC_TIMER.
The auto−recovery restart delay period lapses at point H.
The HV startup current source is activated to recharge VCC
capacitor before a new restart.
The VCC_ON threshold is reached in point I and all the
internal blocks are biased. The VCC blank, REM timer and
OVP/OTP blank period are started at the same time. The
LLC converter operation is enabled, including a dedicated
startup and soft−start period. The output short circuit is
removed in between thus the Vout ramped−up and the FB
loop took over during the LLC converter soft−start period.
3. Startup, skip−mode operation, low line detection
and restart into skip−mode – Figure 63
The application is plugged into the mains at point A thus
the HV input of the controller becomes biased. The HV
startup current source starts charging the VCC capacitor
until VCC reaches the VCC_ON threshold.
The VCC pin voltage reaches the VCC_ON threshold at
point B. The BO, FB, OVP/OTP and PFC MODE blocks are
enabled. The REM input is pulled down for tREM_TIMER to
assure that the secondary side will have enough time to
recover to normal operation and pulls down the remote
optocoupler after the LLC stage restarts. The VBULK/PFC
FB pin begins to receive divided bulk voltage as the external
HV switch is activated by the PFC MODE output. The VCC
blank period is activated during each VCC_ON events. This
blank ensures that the internal logic ignores all fault inputs
until the internal blocks are fully biased and stabilized after
VCC_ON event. The IC DRVs are not enabled even after VCC
blank period ends because the OVP fault condition is
present. The OVP fault condition disappears after some time
so the HV startup current source is enabled to prepare
enough VCC for a new startup attempt. The new VCC blank,
OTP blank and REM timer periods are placed after the