MC14070BCL - Motorola / Freescale Semiconductor

MOTOROLA CMOS LOGIC DATA 1

MC14070B MC14077B

 

Quad Exclusive “OR” and “NOR” Gates

The MC14070B quad exclusive OR gate and the MC14077B quad

exclusive NOR gate are constructed with MOS P–channel and N–channel

enhancement mode devices in a single monolithic structure. These

complementary MOS logic gates find primary use where low power

dissipation and/or high noise immunity is desired.

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

•Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

•Double Diode Protection on All Inputs

•MC14070B — Replacement for CD4030B and CD4070B Types

•MC14077B — Replacement for CD4077B Type

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS* (Voltages Referenced to VSS)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VDD

ÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎÎ

– 0.5 to + 18.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Voltage (DC or Transient)

ÎÎÎÎÎÎ

– 0.5 to VDD + 0.5

ÎÎÎ

ÎÎÎÎ

Iin, Iout

ÎÎÎÎÎÎÎÎÎÎÎ

Input or Output Current (DC or Transient),

per Pin

ÎÎÎÎÎÎ

± 10

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation, per Package†

ÎÎÎÎÎÎ

500

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature (8–Second Soldering)

ÎÎÎÎÎÎ

260

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/

C From 65

C To 125

Ceramic “L” Packages: – 12 mW/

C From 100

C To 125

Figure 1. Power Dissipation Test Circuit and Waveform

VDD

Vin

IDD

20 ns 20 ns VDD

VSS

90%

50%

10%

Vin 1/f

50% DUTY CYCLE

*Inverted output on MC14077B only.

Figure 2. Switching Time Test Circuit and Waveforms

PIN ASSIGNMENT

105

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

VDD

20 ns

VSS

90%

OUTPUT

20 ns

VOH

VOL

VDD

tTHL tTLH

50%

10%

90%

50%

10%

tPLH

tPHL

INPUT

*Inverted output on MC14077B only.

PULSE

GENERATOR

#Connect unused input to VDD for MC14070B, to VSS for MC14077B.



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94





L SUFFIX

CERAMIC

CASE 632

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

MC14070B

QUAD Exclusive OR

Gate

MC14077B

QUAD Exclusive NOR

Gate

13 11

VDD = PIN 14

VSS = PIN 7

(BOTH DEVICES)

MOTOROLA CMOS LOGIC DATAMC14070B MC14077B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎÎ

– 55

ÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Typ #

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎ

Output Voltage

“0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎ

VOL

ÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎ

0.05

ÎÎÎ

—

ÎÎÎÎ

ÎÎÎ

0.05

ÎÎÎÎ

—

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

“1” Level

Vin = 0 or VDD

ÎÎÎ

VOH

ÎÎÎ

5.0

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

—

ÎÎÎ

4.95

9.95

14.95

ÎÎÎÎ

5.0

ÎÎÎ

—

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Voltage

“0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎ

VIL

ÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

—

ÎÎÎÎ

2.25

4.50

6.75

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

—

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎ

VIH

ÎÎÎ

5.0

ÎÎÎÎ

3.5

7.0

ÎÎÎ

—

ÎÎÎ

3.5

7.0

ÎÎÎÎ

2.75

5.50

8.25

ÎÎÎ

—

ÎÎÎÎ

3.5

7.0

ÎÎÎ

—

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

ÎÎÎ

IOH

ÎÎÎ

5.0

ÎÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

—

ÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎ

—

ÎÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎ

IOL

ÎÎÎ

5.0

ÎÎÎÎ

0.64

1.6

4.2

ÎÎÎ

—

ÎÎÎ

0.51

1.3

3.4

ÎÎÎÎ

0.88

2.25

8.8

ÎÎÎ

—

ÎÎÎÎ

0.36

0.9

2.4

ÎÎÎ

—

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎ

Iin

ÎÎÎ

ÎÎÎÎ

—

ÎÎÎ

± 0.1

ÎÎÎ

—

ÎÎÎÎ

±0.00001

ÎÎÎ

± 0.1

ÎÎÎÎ

—

ÎÎÎ

± 1.0

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎ

Cin

ÎÎÎ

—

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

5.0

ÎÎÎ

7.5

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎ

IDD

ÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎ

0.25

0.5

1.0

ÎÎÎ

—

ÎÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎ

0.25

0.5

1.0

ÎÎÎÎ

—

ÎÎÎ

7.5

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Total Supply Current**†

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎ

5.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.3 µA/kHz) f + IDD

IT = (0.6 µA/kHz) f + IDD

IT = (0.9 µA/kHz) f + IDD

ÎÎÎ

µAdc

ÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Times**

(CL = 50 pF)

tTLH, tTHL = (1.35 ns/pF) CL + 33 ns

tTLH, tTHL = (0.60 ns/pF) CL + 20 ns

tTLH, tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎ

tTLH,

tTHL

ÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

100

ÎÎÎ

200

100

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Times**

(CL = 50 pF)

tPLH, tPHL = (0.90 ns/pF) CL + 130ns

tPLH, tPHL = (0.36 ns/pF) CL + 57 ns

tPLH, tPHL = (0.26 ns/pF) CL + 37 ns

ÎÎÎ

tPLH,

tPHL

ÎÎÎ

5.0

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

—

ÎÎÎÎ

175

ÎÎÎ

350

150

110

ÎÎÎÎ

—

ÎÎÎ

—

ÎÎÎ

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

**The formulas given are for the typical characteristics only at 25

†To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However ,

precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance

circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must

be left open.

MOTOROLA CMOS LOGIC DATA 3

MC14070B MC14077B

OUTLINE DIMENSIONS

L SUFFIX

CERAMIC DIP PACKAGE

CASE 632–08

ISSUE Y

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.750 0.785 19.05 19.94

B0.245 0.280 6.23 7.11

C0.155 0.200 3.94 5.08

D0.015 0.020 0.39 0.50

F0.055 0.065 1.40 1.65

G0.100 BSC 2.54 BSC

J0.008 0.015 0.21 0.38

K0.125 0.170 3.18 4.31

L0.300 BSC 7.62 BSC

M0 15 0 15

N0.020 0.040 0.51 1.01

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIMENSION F MAY NARROW TO 0.76 (0.030)

WHERE THE LEAD ENTERS THE CERAMIC

BODY.

–A–

–B–

14 PLDGF N

14 PLJM

0.25 (0.010) T

–T–

SEATING

PLANE

1 7

14 9

P SUFFIX

PLASTIC DIP PACKAGE

CASE 646–06

ISSUE L

NOTES:

1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE

POSITION AT SEATING PLANE AT MAXIMUM

MATERIAL CONDITION.

2. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

3. DIMENSION B DOES NOT INCLUDE MOLD

FLASH.

4. ROUNDED CORNERS OPTIONAL.

1 7

14 8

H G D K

SEATING

PLANE

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L0.300 BSC 7.62 BSC

M0 10 0 10

N0.015 0.039 0.39 1.01

_ _ _ _

MOTOROLA CMOS LOGIC DATAMC14070B MC14077B

OUTLINE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751A–03

ISSUE F

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

–A–

–B–

P7 PL

14 8

71 M

0.25 (0.010) B M

0.25 (0.010) A S

–T–

RX 45

SEATING

PLANE

D14 PL K

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

_ _ _ _

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MC14070B/D

*MC14070B/D*

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