CA3130E - Harris Semiconductor

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.

April 1993

2-108

SEMICONDUCTOR

Description

CA3130A and CA3130 are integrated-circuit operational

ampliﬁers that combine the advantage of both CMOS and

bipolar transistors on a monolithic chip.

Gate-protected p-channel MOSFET (PMOS) transistors are

used in the input circuit to provide very-high-input imped-

ance, very-low-input current, and exceptional speed perfor-

mance. The use of PMOS ﬁeld-effect transistors in the input

stage results in common-mode input-voltage capability down

to 0.5 volt below the negative-supply terminal, an important

attribute in single-supply applications.

A complementary-symmetry MOS (CMOS) transistor-pair,

capable of swinging the output voltage to within 10 millivolts

of either supply-voltage terminal (at very high values of load

impedance), is employed as the output circuit.

The CA3130 Series circuits operate at supply voltages rang-

ing from 5 to 16 volts, or ±2.5 to ±8 volts when using split

supplies. They can be phase compensated with a single

external capacitor, and have terminals for adjustment of off-

set voltage for applications requiring offset-null capability.

Terminal provisions can also made to permit strobing of the

output stage.

The CA3130A offers superior input characteristics over

those of the CA3130.

Features

• MOSFET Input Stage Provides:

- Very High ZI = 1.5 TΩ (1.5 x 1012Ω) Typ.

- Very Low II = 5pA Typ. at 15V Operation

= 2pA Typ. at 5V Operation

• Ideal for Single-Supply Applications

• Common-Mode Input-Voltage Range Includes Nega-

tive Supply Rail; Input Terminals can be Swung 0.5V

Below Negative Supply Rail

• CMOS Output Stage Permits Signal Swing to Either

(or both) Supply Rails

Applications

• Ground-Referenced Single Supply Ampliﬁers

• Fast Sample-Hold Ampliﬁers

• Long-Duration Timers/Monostables

• High-Input-Impedance Comparators

(Ideal Interface with Digital CMOS)

• High-Input-Impedance Wideband Ampliﬁers

• Voltage Followers (e.g. Follower for Single-Supply D/A

Converter)

• Voltage Regulators (Permits Control of Output Voltage

Down to Zero Volts)

• Peak Detectors

• Single-Supply Full-Wave Precision Rectiﬁers

• Photo-Diode Sensor Ampliﬁers

Pinouts

CA3130, CA3130A

(PDIP, SOIC)

TOP VIEW

CA3130, CA3130A

(CAN)

TOP VIEW

OFFSET

INV.

NON-INV.

V-

STROBE

V+

OUTPUT

OFFSET

–

NULL

INPUT

NULL

TAB

OUTPUT

INV.

V- AND CASE

OFFSET

NON-INV.

V+

OFFSET

–

STROBE

PHASE

COMPENSATION

NULL

INPUT

NULL

Ordering Information

PART

NUMBER TEMP.

RANGE PACKAGE

CA3130AE -55oC to +125 oC 8 Lead PDIP

CA3130AM -55oC to +125 oC 8 Lead SOIC

CA3130AM96 -55oC to +125oC 8 Lead SOIC*

CA3130AT -55oC to +125oC 8 Pin CAN

CA3130BT -55oC to +125 oC 8 Pin CAN

CA3130E -55oC to +125 oC 8 Lead PDIP

CA3130M -55oC to +125oC 8 Lead SOIC

CA3130M96 -55oC to +125oC 8 Lead SOIC*

CA3130T -55oC to +125 oC 8 Pin CAN

* Denotes Tape and Reel

CA3130

BiMOS Operational Ampliﬁer

with MOSFET Input/CMOS Output

File Number 817.2

2-109

Speciﬁcations CA3130, CA3130A

Absolute Maximum Ratings Operating Conditions

DC Supply Voltage (Between V+ And V- Terminals). . . . . . . . . . 16V

Differential-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 8V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . (V+ +8 V) to (V- -0.5V)

Input-Terminal Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mA

Device Dissipation:

Without Heat Sink-

Up To 55oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .630 mW

Above 55oC. . . . . . . . . . . . . . . . . . Derate Linearly 6.67 mW/oC

With Heat Sink-

Up To 90οC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W

Above 90οC. . . . . . . . . . . . . . . . . Derate Linearly 16.7 mW/oC.

Output Short-Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indeﬁnite

Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC

Lead Temperature (Soldering 10 Sec.). . . . . . . . . . . . . . . . . +300oC

Operating Temperature Range (All Types) . . . . . . .-55oC to +125oC

Storage Temperature Range(All Types) . . . . . . . . . -65oC to +150oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

Electrical Speciﬁcations TA = +25oC, V+ = 15V, V- = 0V (Unless Otherwise Speciﬁed)

PARAMETERS SYMBOLS TEST

CONDITIONS

LIMITS

UNITS

CA3130A CA3130

MIN TYP MAX MIN TYP MAX

Input Offset Voltage |VIO|V± = ±7.5V - 2 5 - 8 15 mV

Input Offset Current |IIO|V± = ±7.5V - 0.5 20 - 0.5 30 pA

Input Current IIV± = ±7.5V - 5 30 - 5 50 pA

Large-Signal Voltage Gain AOL VO = 10 Vp-p

RL = 2kΩ50 320 - 50 320 - kV/V

94 110 - 94 110 - dB

Common-Mode

Rejection Ratio CMRR 80 90 - 70 90 - dB

Common-Mode Input

Voltage Range VICR 0 -0.5 to

12 10 0 -0.5 to

12 10 V

Power-Supply

Rejection Ratio ∆VIO/∆V±V± = ±7.5V - 32 150 - 32 320 µV/V

Maximum Output Voltage VOM+ At RL = 2kΩ12 13.3 - 12 13.3 - V

VOM- At RL = 2kΩ- 0.002 0.01 - 0.002 0.01 V

VOM+ At RL = 2kΩ14.99 15 - 14.99 15 - V

VOM- At RL = 2kΩ- 0 0.01 - 0 0.01 V

Maximum Output Current IOM+ (Source) at VO = 0V 12 22 45 12 22 45 mA

IOM- (Sink) at VO = 15V 12 20 45 12 20 45 mA

Supply Current I+ VO = 7.5V,

RL = ∞- 10 15 - 10 15 mA

I+ VO = 0V,

RL = ∞-23-23mA

Input Offset Voltage

Temperature Drift ∆VIO/∆T - 10 - - 10 - µV/oC

NOTE:

1. Short circuit may be applied to ground or to either supply.

2-110

Speciﬁcations CA3130, CA3130A

Electrical Speciﬁcations Typical Values Intended Only for Design Guidance, V+ = +7.5V, V- = -7.5V, TA = +25oC

(Unless Otherwise Speciﬁed)

PARAMETERS SYMBOL TEST CONDITIONS CA3130A,

CA3130 UNITS

Input Offset Voltage Adjustment Range 10kΩ Across Terms. 4 and 5 or

4 and 1 ±22 mV

Input Resistance RI1.5 TΩ

Input Capacitance CIf = 1MHz 4.3 pF

Equivalent Input Noise Voltage eNBW = 0.2MHz, RS = 1MΩ*23µV

Unity Gain Crossover Frequency fT

CC = 0 15 MHz

CC = 47pF 4 MHz

Slew Rate: SR

CC = 0 30 V/µsOpen Loop

Closed Loop CC = 56pF 10 V/µs

Transient Response: CC = 56pF,

CL = 25pF,

RL = 2kW

(Voltage Follower) 0.09 µsRise Time tR

Overshoot OS 10 %

Settling Time (To <0.1%, VIN = 4VP-P)t

S1.2 µs

* Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ.

Electrical Speciﬁcations Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = +25oC

(Unless Otherwise Speciﬁed)

PARAMETERS SYMBOL TEST CONDITIONS CA3130A CA3130 UNITS

Input Offset Voltage VIO 28mV

Input Offset Current IIO 0.1 0.1 pA

Input Current II22pA

Common-Mode Rejection Ratio CMRR 90 80 dB

Large-Signal Voltage Gain AOL VO = 4VP-P, RL = 5kW 100 100 kV/V

100 100 dB

Common-Mode Input Voltage Range VICR 0 to 2.8 0 to 2.8 V

Supply Current I+ VO = 5V, RL = ∞300 300 µA

VO = 2.5V, RL = ∞500 500 µA

Power Supply Rejection Ratio ∆VIO/∆V+ 200 200 µV/V

2-111

CA3130, CA3130A

FIGURE 1. SCHEMATIC DIAGRAM OF THE CA3130 SERIES

1 8 4

Q1 Q2

D5 D6 D7 D8

Q9 Q10

Q6 Q7

8.3V

INPUT STAGE

1kΩR4

1kΩ

NON-INV.

INPUT

INV.-INPUT

40kΩ

5kΩ

BIAS CIRCUIT CURRENT SOURCE FOR “CURRENT SOURCE

LOAD” FOR Q11

Q6 AND Q7 V+

OUTPUT

STAGE Q8

Q12

V-

Q11

SECOND

STAGE

OFFSET NULL COMPENSATION STROBING

NOTE: DIODES D5 THROUGH D8 PROVIDE GATE-OXIDE

PROTECTION FOR MOSFET INPUT STAGE

Circuit Description

Figure 2 is a block diagram of the CA3130 Series CMOS

Operational Ampliﬁers. The input terminals may be operated

down to 0.5 V below the negative supply rail, and the output

can be swung very close to either supply rail in many appli-

cations. Consequently, the CA3130 Series circuits are ideal

for single-supply operation. Three Class A ampliﬁer stages,

having the individual gain capability and current consump-

tion shown in Figure 2, provide the total gain of the CA3130.

A biasing circuit provides two potentials for common use in

the ﬁrst and second stages. Term. 8 can be used both for

phase compensation and to strobe the output stage into qui-

escence. When Term. 8 is tied to the negative supply rail

(Term. 4) by mechanical or electrical means, the output

potential at Term. 6 essentially rises to the positive supply-

rail potential at Term. 7. This condition of essentially zero

current drain in the output stage under the strobed “OFF”

condition can only be achieved when the ohmic load resis-

tance presented to the ampliﬁer is very high (e.g.,when the

ampliﬁer output is used to drive CMOS digital circuits in

Comparator applications).

Input Stages

The circuit of the CA3130 is shown in Figure 1. It consists of

a differential-input stage using PMOS ﬁeld-effect transistors

(Q6, Q7) working into a mirror-pair of bipolar transistors (Q9,

Q10) functioning as load resistors together with resistors R3

through R6. The mirror-pair transistors also function as a dif-

ferential-to-single-ended converter to provide base drive to

the second-stage bipolar transistor (Q11). Offset nulling,

when desired, can be effected by connecting a 100,000Ω

potentiometer across Terms. 1 and 5 and the potentiometer

slider arm to Term. 4. Cascade-connected PMOS transistors

Q2, Q4 are the constant-current source for the input stage.

The biasing circuit for the constant-current source is subse-

quently described. The small diodes D5 through D8 provide

gate-oxide protection against high-voltage transients, includ-

ing static electricity during handling for Q6 and Q7.

Second-Stage

Most of the voltage gain in the CA3130 is provided by the

second ampliﬁer stage, consisting of bipolar transistor Q11

and its cascade-connected load resistance provided by

2-112

CA3130, CA3130A

PMOS transistors Q3 and Q5. The source of bias potentials

for these PMOS transistors is subsequently described. Miller

Effect compensation (roll-of f) is accomplished by simply con-

necting a small capacitor between Terms. 1 and 8. A 47-

picofarad capacitor provides sufﬁcient compensation for sta-

ble unity-gain operation in most applications.

Bias-Source Circuit

At total supply voltages, somewhat above 8.3 volts, resistor

R2 and zener diode Z1 serve to establish a voltage of 8.3 volts

across the series-connected circuit, consisting of resistor R1,

diodes D1 through D4, and PMOS transistor Q1. A tap at the

junction of resistor R1 and diode D4 provides a gate-bias

potential of about 4.5 volts for PMOS transistors Q4 and Q5

with respect to Term. 7. A potential of about 2.2 volts is devel-

oped across diode-connected PMOS transistor Q1 with

respect to Term. 7 to provide gate bias for PMOS transistors

Q2 and Q3. It should be noted that Q1 is “mirror-connected”*

to both Q2 and Q3. Since transistors Q1, Q2, Q3 are

designed to be identical, the approximately 200-microampere

current in Q1 establishes a similar current in Q2 and Q3 as

constant current sources for both the ﬁrst and second ampli-

ﬁer stages, respectively.

At total supply voltages somewhat less than 8.3 volts, zener

diode Z1 becomes nonconductive and the potential, devel-

oped across series-connected R1, D1-D4, and Q1, varies

directly with variations in supply voltage. Consequently, the

gate bias for Q4, Q5 and Q2, Q3 varies in accordance with

supply-voltage variations. This variation results in deteriora-

tion of the power-supply-rejection ratio (PSRR) at total sup-

ply voltages below 8.3 volts. Operation at total supply

voltages below about 4.5 volts results in seriously degraded

performance.

Output Stage

The output stage consists of a drain-loaded inverting ampli-

ﬁer using CMOS transistors operating in the Class A mode.

When operating into very high resistance loads, the output

can be swung within millivolts of either supply rail. Because

the output stage is a drain-loaded ampliﬁer, its gain is

dependent upon the load impedance. The transfer charac-

teristics of the output stage for a load returned to the nega-

tive supply rail are shown in Figure 5. Typical op-amp loads

are readily driven by the output stage. Because large-signal

excursions are non-linear, requiring feedback for good wave-

form reproduction, transient delays may be encountered. As

a voltage follower, the ampliﬁer can achieve 0.01 percent

accuracy levels, including the negative supply rail.

* For general information on the characteristics of CMOS transistor-

pairs in linear-circuit applications, see File Number 619, data bulle-

tin on CA3600E “CMOS Transistor Array”.

FIGURE 2. BLOCK DIAGRAM OF THE CA3130 SERIES

FIGURE 3. OPEN-LOOP VOLTAGE GAIN AND PHASE SHIFT

vs FREQUENCY

815

BIAS CKT.

COMPENSATION

(WHEN REQUIRED)

AV≈ 5X AV≈AV≈

6000X 30X

INPUT

200µA 200µA

1.35mA 8mA*

0mA**

V+

OUTPUT

V-

STROBE

OFFSET

NULL

CA3130

TOTAL SUPPLY VOLTAGE (FOR INDICATED VOLTAGE GAINS) = 15V

*WITH INPUT TERMINALS BIASED SO THAT TERM. 6 POTENTIAL

IS +7.5V ABOVE TERM. 4.

**WITH OUTPUT TERMINAL DRIVEN TO EITHER SUPPLY RAIL.

SUPPLY VOLTAGE: V+ = 15V; V- = 0

TA = +25oC

φ OL

CAPACITANCE: LOAD (CL) = 9pF

COMPENSATION (CC) = 0

AOL

1 = LOAD RESISTANCE (RL) = ∞

2 = CL = 30pF, CC = 15pF, RL = 2kΩ

3 = CL = 30pF, CC = 47pF, RL = 2kΩ

4 = CL = 30pF, CC = 150pF, RL = 2kΩ

120

100

OPEN-LOOP VOLTAGE GAIN (dB)

-100

-200

-300

OPEN-LOOP PHASE (DEGREES)

102103104105106107108

FREQUENCY (Hz)

101

2-113

CA3130, CA3130A

FIGURE 4. OPEN-LOOP GAIN vs TEMPERATURE FIGURE 5. VOLTAGE TRANSFER CHARACTERISTICS OF

CMOS OUTPUT STAGE

FIGURE 6. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE FIGURE 7. QUIESCENT SUPPLY CURRENT vs SUPPLY

VOLTAGE

FIGURE 8. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR

(Q8) vs LOAD CURRENT FIGURE 9. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR

(Q12) vs LOAD CURRENT

LOAD RESISTANCE = 2kΩ

150

140

130

120

110

100

-100 -50 0 50 100

OPEN-LOOP VOLTAGE GAIN (dB)

TEMPERATURE (oC)

22.5

GATE VOLTAGE [TERMS 4 AND 8] (V)

OUTPUT VOLTAGE [TERMS 4 AND 6] (V)

17.5 2012.5 15107.52.5 50

2.5

7.5

12.5

17.5 SUPPLY VOLTAGE: V+ = 15, V- = 0V

TA = +25oC

LOAD RESISTANCE = 5kΩ

500Ω

1kΩ2kΩ

LOAD RESISTANCE = ∞

TA = +25oC

V- = 0 OUTPUT VOLTAGE BALANCED = V+/2

OUTPUT VOLTAGE HIGH = V+

OR LOW = V-

17.5

12.5

7.5

2.5

06 8 10 12 14 16 18

TOTAL SUPPLY VOLTAGE (V)

QUIESCENT SUPPLY CURRENT (mA)

OUTPUT VOLTAGE = V+/2

V- = 0

0246810121416

QUIESCENT SUPPLY CURRENT (mA)

TOTAL SUPPLY VOLTAGE (V)

TA = -55oC

+25oC

+125oC

NEGATIVE SUPPLY VOLTAGE = 0V

TA = +25oC

10 8

0.1 8

0.01 8

0.001

0.0012468

0.012468

0.1 2468

1.0 2468

10 2468

100

MAGNITUDE OF LOAD CURRENT (mA)

VOLTAGE DROP ACROSS PMOS OUTPUT

STAGE TRANSISTOR (V)

15V

10V

POSITIVE SUPPLY VOLTAGE = 5V

NEGATIVE SUPPLY VOLTAGE = 0V

TA = +25oC

10 8

0.1 8

0.01 8

0.001

0.0012468

0.012468

0.1 2468

2468

10 2468

100

MAGNITUDE OF LOAD CURRENT (mA)

VOLTAGE DROP ACROSS NMOS OUTPUT

STAGE TRANSISTOR (V)

15V

10V

POSITIVE SUPPLY VOLTAGE = 5V

2-114

CA3130, CA3130A

Input Current Variation with Common Mode Input

Voltage

As shown in the Table of Electrical Characteristics, the input

current for the CA3130 Series Op-Amps is typically 5pA at TA

= +25oC when terminals 2 and 3 are at a common-mode

potential of +7.5 volts with respect to negative supply Terminal

4. Figure 10 contains data showing the variation of input cur-

rent as a function of common-mode input voltage at TA =

+25oC. These data show that circuit designers can advanta-

geously exploit these characteristics to design circuits which

typically require an input current of less than 1pA, provided

the common-mode input voltage does not exceed 2 volts. As

previously noted, the input current is essentially the result of

the leakage current through the gate-protection diodes in the

input circuit and, therefore, a function of the applied voltage.

Although the ﬁnite resistance of the glass terminal-to-case

insulator of the TO-5 package also contributes an increment

of leakage current, there are useful compensating factors.

Because the gate-protection network functions as if it is con-

nected to Terminal 4 potential, and the TO-5 case of the

CA3130 is also internally tied to Terminal 4, input terminal 3 is

essentially “guarded” from spurious leakage currents.

FIGURE 10. INPUT CURRENT vs COMMON-MODE VOLTAGE

Offset Nulling

Offset-voltage nulling is usually accomplished with a

100,000-ohm potentiometer connected across Terms. 1 and

5 and with the potentiometer slider arm connected to

Term. 4. A ﬁne offset-null adjustment usually can be effected

with the slider arm positioned in the mid-point of the potenti-

ometer's total range.

Input-Current Variation with Temperature

The input current of the CA3130 Series circuits is typically

5pA at +25oC. The major portion of this input current is due

to leakage current through the gate-protective diodes in the

7.5

2.5

0-101234567

INPUT CURRENT (pA)

INPUT VOLTAGE (V)

TA = +25oC

VIN

CA3130

15 VOLTS

5 VOLTS

0 VOLTS

-10 VOLTS

V+

V-

input circuit. As with any semiconductor-junction device,

including op-amps with a junction-FET input stage, the leak-

age current approximately doubles for every +10oC increase

in temperature. Figure 11 provides data on the typical varia-

tion of input bias current as a function of temperature in the

CA3130.

FIGURE 11. INPUT CURRENT vs AMBIENT TEMPERATURE

In applications requiring the lowest practical input current

and incremental increases in current because of “warm-up”

effects, it is suggested that an appropriate heat sink be used

with the CA3130. In addition, when “sinking” or “sourcing”

signiﬁcant output current the chip temperature increases,

causing an increase in the input current. In such cases, heat-

sinking can also very markedly reduce and stabilize input

current variations.

Input-Offset-Voltage (VIO) Variation with DC Bias vs

Device Operating Life

It is well known that the characteristics of a MOSFET device

can change slightly when a dc gate-source bias potential is

applied to the device for extended time periods. The magni-

tude of the change is increased at high temperatures. Users

of the CA3130 should be alert to the possible impacts of this

effect if the application of the device involves extended oper-

ation at high temperatures with a signiﬁcant differential dc

bias voltage applied across Terms. 2 and 3. Figure 12 shows

typical data pertinent to shifts in offset voltage encountered

with CA3130 devices (TO-5 package) during life testing. At

lower temperatures (TO-5 and plastic), for example at

+85oC, this change in voltage is considerably less. In typical

linear applications where the differential voltage is small and

symmetrical, these incremental changes are of about the

same magnitude as those encountered in an operational

ampliﬁer employing a bipolar transistor input stage. The two-

volt dc differential voltage example represents conditions

when the ampliﬁer output stage is “toggled”, e.g., as in com-

parator applications.

V+ = 7.5V

V- = -7.5V

4000

10008

1008

108

1-80 -60 -40 -20 0 20 40 60 80 100 120 140

INPUT CURRENT (pA)

TEMPERATURE (oC)

2-115

CA3130, CA3130A

FIGURE 12. TYPICAL INCREMENTAL OFFSET-VOLTAGE

SHIFT vs OPERATING LIFE

(A) DUAL POWER-SUPPLY OPERATION

(B) SINGLE POWER-SUPPLY OPERATION

FIGURE 13. CA3130 OUTPUT STAGE IN DUAL AND SINGLE

POWER-SUPPLY OPERATION

TA = +125oC FOR TO-5 PACKAGES

0 500 1000 1500 2000 2500 3000 3500 4000

OFFSET-VOLTAGE SHIFT (mV)

TIME (HOURS)

DIFFERENTIAL DC VOLTAGE

(ACROSS TERMS 2 AND 3) = 0V

OUTPUT VOLTAGE = V+ / 2

DIFFERENTIAL DC VOLTAGE

(ACROSS TERMS 2 AND 3) = 2V

OUTPUT STAGE TOGGLED

POSITIVE

SUPPLY

NEGATIVE

SUPPLY

Q12

CA3130

POSITIVE

SUPPLY

Q12

CA3130

Power-Supply Considerations

Because the CA3130 is very useful in single-supply applica-

tions, it is pertinent to review some considerations relating to

power-supply current consumption under both single-and

dual-supply service. Figures 13A and 13B show the CA3130

connected for both dual-and single-supply operation.

Dual-supply Operation: When the output voltage at Term. 6

is zero-volts, the currents supplied by the two power supplies

are equal. When the gate terminals of Q8 and Q12 are

driven increasingly positive with respect to ground, current

ﬂow through Q12 (from the negative supply) to the load is

increased and current ﬂow through Q8 (from the positive

supply) decreases correspondingly. When the gate terminals

of Q8 and Q12 are driven increasingly negative with respect

to ground, current ﬂow through Q8 is increased and current

ﬂow through Q12 is decreased accordingly.

Single-supply Operation: Initially, let it be assumed that the

value of RL is very high (or disconnected), and that the input-

terminal bias (Terms. 2 and 3) is such that the output termi-

nal (No. 6) voltage is at V+/2, i.e., the voltage-drops across

Q8 and Q12 are of equal magnitude. Figure 6 shows typical

quiescent supply-current vs supply-voltage for the CA3130

operated under these conditions. Since the output stage is

operating as a Class A ampliﬁer, the supply-current will

remain constant under dynamic operating conditions as long

as the transistors are operated in the linear portion of their

voltage-transfer characteristics (see Figure 5). If either Q8 or

Q12 are swung out of their linear regions toward cut-off (a

non-linear region), there will be a corresponding reduction in

supply-current. In the extreme case, e.g., with Term. 8

swung down to ground potential (or tied to ground), NMOS

transistor Q12 is completely cut off and the supply-current to

series-connected transistors Q8, Q12 goes essentially to

zero. The two preceding stages in the CA3130, however,

continue to draw modest supply-current (see the lower curve

in Figure 6) even though the output stage is strobed off. Fig-

ure 13A shows a dual-supply arrangement for the output

stage that can also be strobed off, assuming RL = ∞ by pull-

ing the potential of Term. 8 down to that of Term. 4.

Let it now be assumed that a load-resistance of nominal

value (e.g., 2 kilohms) is connected between Term. 6 and

ground in the circuit of Figure 13B. Let it further be assumed

again that the input-terminal bias (Terms. 2 and 3) is such

that the output terminal (No. 6) voltage is at V+/2. Since

PMOS transistor Q8 must now supply quiescent current to

both RL and transistor Q12, it should be apparent that under

these conditions the supply-current must increase as an

inverse function of the RL magnitude. Figure 8 shows the

voltage-drop across PMOS transistor Q8 as a function of

load current at several supply voltages. Figure 5 shows the

voltage-transfer characteristics of the output stage for sev-

eral values of load resistance.

Wideband Noise

From the standpoint of low-noise performance consider-

ations, the use of the CA3130 is most advantageous in appli-

cations where in the source resistance of the input signal is

on the order of 1 megohm or more. In this case, the total

input-referred noise voltage is typically only 23µV when the

2-116

CA3130, CA3130A

test-circuit ampliﬁer of Figure 14 is operated at a total supply

voltage of 15 volts. This value of total input-referred noise

remains essentially constant, even though the value of

source resistance is raised by an order of magnitude. This

characteristic is due to the fact that reactance of the input

capacitance becomes a signiﬁcant factor in shunting the

source resistance. It should be noted, however, that for val-

ues of source resistance very much greater than 1 megohm,

the total noise voltage generated can be dominated by the

thermal noise contributions of both the feedback and source

resistors.

FIGURE 14. TEST-CIRCUIT AMPLIFIER (30-dB GAIN) USED

FOR WIDEBAND NOISE MEASUREMENTS

Typical Applications

Voltage Followers

Operational ampliﬁers with very high input resistances, like

the CA3130, are particularly suited to service as voltage fol-

lowers. Figure 15 shows the circuit of a classical voltage fol-

lower, together with pertinent waveforms using the CA3130

in a split-supply conﬁguration.

A voltage follower, operated from a single supply, is shown in

Figure 16, together with related waveforms. This follower cir-

cuit is linear over a wide dynamic range, as illustrated by the

reproduction of the output waveform in Figure 16A with

input-signal ramping. The waveforms in Figure 16B show

that the follower does not lose its input-to-output phase-

sense, even though the input is being swung 7.5 volts below

ground potential. This unique characteristic is an important

attribute in both operational ampliﬁer and comparator appli-

cations. Figure 16B also shows the manner in which the

CMOS output stage permits the output signal to swing down

to the negative supply-rail potential (i.e., ground in the case

shown). The digital-to-analog converter (DAC) circuit,

described in the following section, illustrates the practical

use of the CA3130 in a single-supply voltage-follower appli-

cation.

184

1MΩ

47pF -7.5V

0.01

µF

+7.5V

0.01µF

NOISE

VOLTAGE

OUTPUT

30.1kΩ

1kΩ

BW (-3dB) = 200kHz

TOTAL NOISE VOLTAGE (REFERRED

TO INPUT) = 23µV TYP.

Top Trace: Output

Bottom Trace: Input

(A) SMALL-SIGNAL RESPONSE (50mV/DIV. AND 200ns/DIV.)

Top Trace: Output Signal (2V/DIV. and 5µs/DIV.)

Center Trace: Difference Signal (5mV/DIV. and 5µs/DIV.)

Bottom Trace: Input Signal (2V/DIV. and 5µs/DIV.)

(B) INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SET-

TLING TIME (MEASUREMENT MADE WITH TEKTRONIX

7A13 DIFFERENTIAL AMPLIFIER)

FIGURE 15. SPLIT-SUPPLY VOLTAGE FOLLOWER WITH

ASSOCIATED WAVEFORMS

184

10kΩ

CC = 56pF

-7.5V 0.01µF

+7.5V

0.01µF

2kΩ

BW (-3dB) = 4MHz

SR = 10V/µs

25pF

0.1µF

2-117

CA3130, CA3130A

(A) OUTPUT-WAVEFORM WITH INPUT-SIGNAL RAMPING (2V/

DIV. AND 500µs/DIV.)

Top Trace: Output (5V/DIV. and 200µs/DIV.)

Bottom Trace: Input Signal (5V/DIV. and 200µs/DIV.)

(B) OUTPUT WAVEFORM WITH GROUND-REFERENCE SINE-

WAVE INPUT

FIGURE 16. SINGLE-SUPPLY VOLT AGE-FOLLOWER WITH

ASSOCIATED WAVEFORMS. (e.g., FOR USE IN SIN-

GLE-SUPPLY D/A CONVERTER; SEE FIGURE 9 IN

AN6080)

10kΩ

56pF OFFSET

+15V

0.01µF

2kΩ

0.1µF

ADJUST

100kΩ

9-Bit COS/MOS DAC

A typical circuit of a 9-bit Digital-to-Analog Converter (DAC)*

is shown in Figure 17 This system combines the concepts of

multiple-switch CMOS lC's, a low-cost ladder network of dis-

crete metal-oxide-ﬁlm resistors, a CA3130 op-amp con-

nected as a follower, and an inexpensive monolithic

regulator in a simple single power-supply arrangement. An

additional feature of the DAC is that it is readily interfaced

with CMOS input logic, e.g., 10-volt logic levels are used in

the circuit of Figure 17.

The circuit uses an R/2R voltage-ladder network, with the

output potential obtained directly by terminating the ladder

arms at either the positive or the negative power-supply ter-

minal. Each CD4007A contains three “inverters”, each

“inverter” functioning as a single-pole double-throw switch to

terminate an arm of the R/2R network at either the positive

or negative power-supply terminal. The resistor ladder is an

assembly of one percent tolerance metal-oxide ﬁlm resistors.

The ﬁve arms requiring the highest accuracy are assembled

with series and parallel combinations of 806,000-ohm resis-

tors from the same manufacturing lot.

A single 15-volt supply provides a positive bus for the

CA3130 follower ampliﬁer and feeds the CA3085 voltage

regulator. A “scale-adjust” function is provided by the regula-

tor output control, set to a nominal 10-volt level in this sys-

tem. The line-voltage regulation (approximately 0.2%)

permits a 9-bit accuracy to be maintained with variations of

several volts in the supply. The ﬂexibility afforded by the

COS/MOS building blocks simpliﬁes the design of DAC sys-

tems tailored to particular needs.

Single-Supply, Absolute-Value, Ideal Full-Wave Rectiﬁer

The absolute-value circuit using the CA3130 is shown in Figure

18. During positive excursions, the input signal is fed through

the feedback network directly to the output. Simultaneously, the

positive excursion of the input signal also drives the output ter-

minal (No. 6) of the inverting ampliﬁer in a negative-going

excursion such that the 1N914 diode effectively disconnects the

ampliﬁer from the signal path. During a negative-going excur-

sion of the input signal, the CA3130 functions as a normal

inverting ampliﬁer with a gain equal to -R2/R1. When the equal-

ity of the two equations shown in Figure 18 is satisﬁed, the full-

wave output is symmetrical.

Peak Detectors

Peak-detector circuits are easily implemented with the

CA3130, as illustrated in Figure 19 for both the peak-positive

and the peak-negative circuit. It should be noted that with

large-signal inputs, the bandwidth of the peak-negative cir-

cuit is much less than that of the peak-positive circuit. The

second stage of the CA3130 limits the bandwidth in this

case. Negative-going output-signal excursion requires a pos-

itive-going signal excursion at the collector of transistor Q11,

which is loaded by the intrinsic capacitance of the associ-

ated circuitry in this mode. On the other hand, during a neg-

ative-going signal excursion at the collector of Q11, the

transistor functions in an active “pull-down” mode so that the

intrinsic capacitance can be discharged more expeditiously.

2-118

CA3130, CA3130A

FIGURE 17. 18-9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130

20Vp-p Input: BW(-3dB) = 230kHz, DC Output (Avg.) = 3.2V

1Vp-p Input: BW(-3dB) = 130kHz, DC Output (Avg.) = 160mV

Top Trace: Output Signal (2V/div.)

Bottom Trace: Input Signal (10V/div.)

Time base on both traces: 0.2ms/div.

FIGURE 18. SINGLE-SUPPLY, ABSOLUTE-VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS

6 3 101036

512 12

1313 1 12

8 5

10V LOGIC INPUTS

+10.010

LSB

987 654 321

MSB

806K

PARALLELED

RESISTORS 10K

+15V

VOLTAGE

FOLLOWER

CA3130

OUTPUT

LOAD

100K

OFFSET

NULL

56pF

0.1µF

REGULATED

VOLTAGE

ADJ

22 1K

3 83K

0.001µF

CA3085

VOLTAGE

REGULATOR

+15V

2µF

25V

+10.010

CD4007A

“SWITCHES” CD4007A

“SWITCHES”

402K

1% 200K

1% 100K

1% 806K

806K

1% 750K

806K

1% 806K

(2) (4) (8)

806K

BIT

6 - 9

ALL RESISTANCES IN OHMS

REQUIRED

RATIO-MATCH

STANDARD

±0.1%

±0.2%

±0.4%

±0.8%

±1% ABS

815

2kΩ+15V

0.01

µF

IN914

5.1kΩ

PEAK

ADJUST

2kΩ

100kΩ

OFFSET

ADJUST

20pF

CA3130

4kΩ

Gain R2

R1XR3

R1R2R3

===

1X−

()=

For X 0.5: 2kΩ

4kΩ

4k Ω0.75

0.5

()6k Ω==

-0V

2-119

CA3130, CA3130A

(A) PEAK POSITIVE DETECTOR CIRCUIT (B) PEAK NEGATIVE DETECTOR CIRCUIT

FIGURE 19. PEAK-DETECTOR CIRCUITS

FIGURE 20. VOLTAGE REGULATOR CIRCUIT (0 TO 13V AT 40mA)

CA3130

+7.5V

0.01µF

+DC

OUTPUT

5µF

100

kΩ

IN914

0.01µF

-7.5V

2kΩ

10kΩ+

6VP-P INPUT;

BW(-3dB) = 1.3MHz

0.3 VP-P INPUT;

BW(-3dB) = 240kHz

CA3130

+7.5V

0.01µF

-DC

OUTPUT

5µF

100

kΩ

IN914

0.01µF

-7.5V

2kΩ

10kΩ+

6VP-P INPUT;

BW(-3dB) = 360kHz

0.3 VP-P INPUT;

BW(-3dB) = 320kHz

CA3086

CURRENT

LIMIT

ADJ

3Ω

1kΩ

Q5 13

Q1Q2Q3Q4

10 7 3

4269

11 8 1 5

390Ω1kΩ20kΩ

5µF

25V

56pF

ERROR

AMPLIFIER

CA3130

30kΩ

100kΩ

IC1

0.01

VOLTAGE

ADJUST

50kΩ

62kΩ

IC3

OUTPUT

0 TO 13V

40mA

0.01µF

+20V

INPUT

2.2kΩ

-25µF

IC2

CA3086 10 11 1, 2

Q4 Q1

8, 7 3, 5

Q3 Q2

REGULATION (NO LOAD TO FULL LOAD): < 0.01%

INPUT REGULATION: 0.02%/V

HUM AND NOISE OUTPUT: < 25µV UP TO 100kHz

2-120

CA3130, CA3130A

FIGURE 21. VOLTAGE REGULATOR CIRCUIT (0.1 TO 50V AT 1A)

4.3kΩ

1Ω

43kΩ100µF

ERROR

AMPLIFIER

IC1

VOLTAGE

ADJUST

100µF

+55V

INPUT

2.2kΩ

IC2

CA3086 10, 11

Q4 Q1

REGULATION (NO LOAD TO FULL LOAD): < 0.005%

INPUT REGULATION: 0.01%/V

HUM AND NOISE OUTPUT: < 250µV RMS UP TO 100kHz

CA3130

3.3kΩ

5µF

8, 7

1, 2

1kΩ

62kΩ

10kΩ

50kΩ

2N3055

2N2102 CURRENT

LIMIT

ADJUST

2N5294

2N2102

1000pF

10kΩ

8.2kΩ

OUTPUT:

0.1 TO 50V

AT 1A

2-121

CA3130, CA3130A

Error-Ampliﬁer in Regulated-Power Supplies

The CA3130 is an ideal choice for error-ampliﬁer service in

regulated power supplies since it can function as an error-

ampliﬁer when the regulated output voltage is required to

approach zero. Figure 20 shows the schematic diagram of a

40mA power supply capable of providing regulated output

voltage by continuous adjustment over the range from 0 to

13 volts. Q3 and Q4 in lC2 (a CA3086 transistor-array lC)

function as zeners to provide supply-voltage for the CA3130

comparator (IC1). Q1, Q2, and Q5 in IC2 are conﬁgured as a

low impedance, temperature-compensated source of adjust-

able reference voltage for the error ampliﬁer. Transistors Q1,

Q2, Q3, and Q4 in lC3 (another CA3086 transistor-array lC)

are connected in parallel as the series-pass element. Tran-

sistor Q5 in lC3 functions as a current-limiting device by

diverting base drive from the series-pass transistors, in

accordance with the adjustment of resistor R2.

Figure 21 contains the schematic diagram of a regulated

power-supply capable of providing regulated output voltage

by continuous adjustment over the range from 0.1 to 50 volts

and currents up to 1 ampere. The error ampliﬁer (lC1) and

circuitry associated with lC2 function as previously

described, although the output of lC1 is boosted by a dis-

crete transistor (Q4) to provide adequate base drive for the

Darlington-connected series-pass transistors Q1, Q2. Tran-

sistor Q3 functions in the previously described current-limit-

ing circuit.

Multivibrators

The exceptionally high input resistance presented by the

CA3130 is an attractive feature for multivibrator circuit

design because it permits the use of timing circuits with high

R/C ratios. The circuit diagram of a pulse generator (astable

multivibrator), with provisions for independent control of the

“on” and “off” periods, is shown in Figure 22. Resistors R1

and R2 are used to bias the CA3130 to the mid-point of the

supply-voltage and R3 is the feedback resistor. The pulse

repetition rate is selected by positioning S1 to the desired

position and the rate remains essentially constant when the

resistors which determine “on-period” and “off-period” are

adjusted.

Function Generator

Figure 23 contains a schematic diagram of a function gener-

ator using the CA3130 in the integrator and threshold detec-

tor functions. This circuit generates a triangular or square-

wave output that can be swept over a 1,000,000:1 range (0.1

Hz to 100 kHz) by means of a single control, R1. A voltage-

control input is also available for remote sweep-control.

The heart of the frequency-determining system is an opera-

tional-transconductance-ampliﬁer (OTA)*, lC1, operated as a

voltage-controlled current-source. The output, IO, is a current

applied directly to the integrating capacitor, C1, in the feed-

back loop of the integrator lC2, using a CA3130, to provide

the triangular-wave output. Potentiometer R2 is used to

adjust the circuit for slope symmetry of positive-going and

negative-going signal excursions.

Another CA3130, IC3, is used as a controlled switch to set

the excursion limits of the triangular output from the integra-

tor circuit. Capacitor C2 is a “peaking adjustment” to opti-

mize the high-frequency square-wave performance of the

circuit.

Potentiometer R3 is adjustable to perfect the “amplitude

symmetry” of the square-wave output signals. Output from

the threshold detector is fed back via resistor R4 to the input

of lC1 so as to toggle the current source from plus to minus

in generating the linear triangular wave.

Operation with Output-Stage Power-Booster

The current-sourcing and-sinking capability of the CA3130

output stage is easily supplemented to provide power-boost

capability. In the circuit of Figure 24, three CMOS transistor-

pairs in a single CA3600E* lC array are shown parallel con-

nected with the output stage in the CA3130. In the Class A

mode of CA3600E shown, a typical device consumes 20 mA

of supply current at 15V operation. This arrangement boosts

the current-handling capability of the CA3130 output stage

by about 2.5X.

The ampliﬁer circuit in Figure 24 employs feedback to estab-

lish a closed-loop gain of 48 dB. The typical large-signal

bandwidth (-3dB) is 50 kHz.

* See File Number 619 for technical information.

FIGURE 22. PULSE GENERATOR (ASTABLE MULTIVIBRATOR)

WITH PROVISIONS FOR INDEPENDENT CON-

TROL OF “ON” AND “OFF” PERIODS.

FREQUENCY RANGE:

POSITION OF SI

0.001µF

0.01µF

0.1µF

1µF

PULSE PERIOD

4µs to 1ms

40µs to 10ms

0.4µs to 100ms

4µs to 1s

100kΩ

ON-PERIOD

ADJUST

1MΩ

2kΩ2kΩ

OFF-PERIOD

ADJUST

1MΩ

+15V

0.01µF

OUTPUT

2kΩ

0.001µF

0.01µF

0.1µF

1µFSI CA3130

2-122

CA3130, CA3130A

FIGURE 23. FUNCTION GENERATOR (FREQUENCY CAN BE VARIED 1,000,000/1 WITH A SINGLE CONTROL).

FIGURE 24. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3130.

270kΩ

+7.5V

VOLTAGE-CONTROLLED

CURRENT SOURCE

IC1

3kΩ3kΩ

10MΩ

+7.5V

100kΩSLOPE

SYMMETRY

ADJUST

VOLTAGE

CONTROLLED

INPUT

-7.5V

10kΩ

-7.5V

FREQUENCY

ADJUST

(100kHz MAX)

-7.5V

+7.5V

IOIC1 +7.5V

100pF

INTEGRATOR

-7.5V

56pF

CA3130

CA3080A

-39kΩ

3 - 30pF

ADJUST

HIGH - FREQ. DETECTOR

THRESHOLD

150kΩ

IC3 +7.5V

CA3130

100kΩ

AMPLITUDE

SYMMETRY

ADJUST

* SEE FILE NUMBER 475 AND AN6668

FOR TECHNICAL INFORMATION

22kΩ

-7.5V

+15V

2kΩCA3130

41036

4 97

750kΩ

1µF

211

13 1

1µF

1MΩ0.01µF

510kΩ

500µF

n1 n2 n3

p2p1

CA3600E*

AV(CL) = 48 dB

LARGE SIGNAL

BW(-3 dB) = 50kHz

*SEE FILE NUMBER 619

NOTE:

TRANSISTORS p1, p2, p3 AND

n1, n2, n3 ARE PARALLEL

CONNECTED WITH Q8 AND Q12,

RESPECTIVELY, OF THE CA3130

RL = 100Ω

(PO = 150mW

AT THD = 10%)