Exar

Corporation 48720 Kato Road, Fremont CA, 94538

(510) 668-7000

FAX (510) 668-7017

www.exar.com

XR21V1410

APRIL 2012 REV. 1.3.0

GENERAL DESCRIPTION

The XR21V1410 (V1410) is an enhanced Universal

Asynchronous Receiver and Transmitter (UART) with

a USB interface. The USB interface is fully compliant

to Full Speed USB 2.0 specification that supports 12

rate generator, any baud rate can accurately be

generated using the internal 48MHz clock.

The large 128-byte TX FIFO and 384-byte RX FIFO

of the V1410 helps to optimize the overall data

throughput for various applications. The Automatic

Transceiver Direction control feature simplifies both

the hardware and software for half-duplex RS-485

applications. If required, the multidrop (9-bit) mode

with automatic half-duplex transceiver control feature

further simplifies typical multidrop RS-485

supported for the XR21V1410.

APPLICATIONS

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

IGURE

1. XR21V1410 B

LOCK

D

IAGRAM

IGURE

2. P

IN

ORDERING INFORMATION

REV. 1.3.0

PIN DESCRIPTIONS

Pin Description

# T

RX 10 I UART Channel A Receive Data or IR Receive Data. This pin has an

internal pull-up resistor. Internal pull-up resistor is not disabled during

suspend mode.

TX 9 O UART Channel A Transmit Data or IR Transmit Data.

mode.

has an internal pull-up resistor which is disabled during suspend mode.

If using this GPIO as an input, an external pull-up resistor is required to

minimize the device power consumption in the suspend mode.

GPIO2/DSR# 6 I/O General purpose I/O or UART Data-Set-Ready input (active low).

”Section 1.5.5, Automatic DTR/DSR Hardware Flow Control”

on page 9.

This pin has an internal pull-up resistor which is disabled during suspend

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

REV. 1.3.0

rupt to be generated

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

The I

C memory device (i.e. EEPROM) that can be read by

the V1410 for configuration.

The SDA and SCL are used to specify whether Remote Wakeup and/or Bus Powered configurations are to be

supported. These pins are sampled at power-up. The following table describes how Remote Wakeup and Bus

These values are uploaded from the EEPROM to the corresponding USB Standard Device Descriptor or

Standard Configuration Descriptor. For details of the USB Descriptors, refer to the USB 2.0 specifications.

1.3.1.1 Vendor ID

The Vendor ID value replaces the idVendor field in the USB Standard Device Descriptor.

1.3.1.2 Product ID

The Product ID value replaces the idProduct field in the USB Standard Device Descriptor.

1.3.1.3 Device Attributes

The Device Attributes value replaces the bmAttributes field in the USB Standard Configuration Descriptor. The

default setting in the V1410 device is 0xA0. The bit field definitions are:

Bit 7 is reserved - set to ’1’

ABLE

ONTENTS

REV. 1.3.0

The Device Maximum Power value replaces the bMaxPower field in the USB Standard Configuration

Descriptor. The value specified is in units of 2 mA. For example, the value 0x2F is decimal 47 or 94 mA. Note

1.4 UART Manager

The UART Manager enables/disables the UART including the TX and RX FIFOs. The UART Manager is

located in a separate register block from the UART registers.

1.5 UART

sections are described seperately in the following sections. At power-up, the V1410 will default to 9600 bps, 8

data bits, no parity bit, 1 stop bit, and no flow control. If a standard CDC driver accesses the V1410, defaults

will change. See ”Section 1.2, USB Device Driver” on page 5.

1.5.1 Transmitter

bit(s). The transmitter can be configured for 7 or 8 data bits with or without parity or 9 data bits without parity.

If 9 bit data is selected without wide mode, the 9th bit will always be ’0’.

1.5.1.1 Wide Mode Transmit

When both 9 bit data and wide mode are enabled, two bytes of data must be written. The first byte that is

loaded into the TX FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is

loaded into the TX FIFO is bit-8 of the 9-bit data. The data that is transmitted on the TX pin is as follows: start

bit, 9-bit data, stop bit. Use the WIDE_MODE register to enable wide mode.

1.5.2 Receiver

The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the

RSR via the RX pin is transferred into the RX FIFO along with any error tags such as Framing, Parity, Break

if enabled. If data is 9 bits, no parity is checked. The 9th bit of data is in bit position 0 along with the 3 error bits,

break, frame error and overrun error flags in bit positions 1, 2 & 3 respectively. In wide mode, the parity and

framing error and break flag are associated with the character that they accompany and the overrun error is

tied to the current contents of the entire RX FIFO.

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

Error flags are also available from the ERROR_STATUS register and the interrupt packet, however these flags

are historical flags indicating that an error has occurred since the previous read of the status register.

Therefore, no conclusion can be drawn as to which specific byte(s) may have contained an actual error in this

manner.

1.5.3 GPIO

There are 6 GPIOs. By default, the GPIOs are general purpose I/Os. However, there are few modes that can

When there is room in the RX FIFO, the RTS pin will be re-asserted. Automatic CTS flow control is used to

prevent data overrun to the remote RX FIFO. The CTS# input is monitored to suspend/restart the local

transmitter (see Figure 4):

REV. 1.3.0

Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control

described above except that it uses the DTR# and DSR# signals. For Auto hardware flow control,

FLOW_CONTROL[2:0] = ’001’. GPIO3 and GPIO2 become DTR# and DSR#, respectively, when

GPIO_MODE[2:0] = ’010’.

1.5.6 Automatic XON/XOFF Software Flow Control

When software flow control is enabled, the V1410 compares the receive data characters with the programmed

Xon or Xoff characters. If the received character matches the programmed Xoff character, the V1410 will halt

transmission as soon as the current character has completed transmission. Data transmission is resumed

address is used by a transmitting master to broadcast an address to all attached slave devices that is intended

for only one slave device. A multicast address is used to broadcast an address intended for more than one

recipient device. Each attached slave device should have a unique unicast address value stored in the

XON_CHAR register, while multiple slaves may have the same multicast adderss stored in the XOFF_CHAR

register. An address match occurs when an address byte (9th bit or parity bit is ’1’) is received that matches the

value stored in either the XON_CHAR or XOFF_CHAR register.

RTS

AND

CTS F

LOW

C

PERATION

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

For baud rates that are not listed in the table above, use the index value calcuated using the formula in

“Section 3.3.3, TX_CLOCK_MASK0, TX_CLOCK_MASK1 Register Description (Read/Write)” on page 15

D

IVISOR

AND

LOCK

M

ASK

V

ATES

REV. 1.3.0

9: TX

V

ALUES

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

any effect. In other words, there will not be an additional parity bit.

This register selects the number of stop bits to add to the transmitted character and how many stop bits to

check for in the received character.

3.3.6 FLOW_CONTROL Register Description (Read/Write)

These registers select the flow control mode. These registers should only be written to when the UART is

disabled. Writing to the FLOW_CONTROL register when the UART is enabled will result in undefined

behavior. Note that the FLOW_CONTROL register settings are used in conjunction with the GPIO_MODE

register.

ABLE

ATA

ABLE

ARITY

2 2 stop bits

REV. 1.3.0

FLOW_CONTROL[3]: Half-Duplex Mode

FLOW_CONTROL[7:4]: Reserved

These bits are reserved and should remain ’0’.

3.3.7 XON_CHAR, XOFF_CHAR Register Descriptions (Read/Write)

The XON_CHAR and XOFF_CHAR registers store the XON and XOFF characters, respectively, that are used

in the Automatic Software Flow control. If the V1410 is configured in multidrop mode, the XON_CHAR and

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

ERROR_STATUS[3]: Break error

Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not

This is the number of bit times to wait before changing the direction of the transceiver from transmit to receive

REV. 1.3.0

3.3.13 GPIO_DIRECTION Register Description (Read/Write)

This register controls the direction of the GPIO if it is not controlled by the GPIO_MODE register.

ABLE

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

Writing a ’1’ in this register drives the GPIO output low. Writing a ’0’ to a bit has no effect. Bits 7-6 are unused

This register reports the current state of the GPIO pin.

This register controls the bMaxPacketSize and enables the Wide mode functionality for the UART.

CDC_ACM USB command)

En

REV. 1.3.0

XR21V1410

1-CH FULL-SPEED USB UART

REV. 1.3.0

ABLE

16: I

NTERRUPT

ACKET

F

If the Exar vendor specific packet mapping is enabled then the data field also includes status for all of the

int_status

or

D6 = bOverRun

D5 = bParity

D4 = bFraming

D3 = bRingSignal (RI)

D2 = bBreak

D1 = bTxCarrier (DSR)

D0 = bRxCarrier (CD)

D15..D7 Reserved (0)

REV. 1.3.0