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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual PD179327 Subseries 8-Bit Single-Chip Microcontrollers PD179322 PD179322A PD179324 PD179324A PD179326 PD179327 PD78F9328 Document No. U16995EJ2V0UD00 (2nd edition) Date Published April 2006 NS CP(K) Printed in Japan 2004 [MEMO] 2 User's Manual U16995EJ2V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. User's Manual U16995EJ2V0UD 3 Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. * The information in this document is current as of March, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual U16995EJ2V0UD [MEMO] User's Manual U16995EJ2V0UD 5 INTRODUCTION Target Readers This manual is intended for users who wish to understand the functions of the PD179327 Subseries and to design and develop application systems and programs using these microcontrollers. Target products: * PD179327 Subseries: PD179322, 179322A, 179324, 179324A, 179326, 179327 The PD78F9328 is used as the flash memory version of the PD179327 Subseries. Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The PD179327 Subseries User's Manual is divided into two parts: this manual and instructions (common to the 78K/0S Series). 78K/0S Series PD179327 Subseries User's Manual User's Manual Instructions * Pin functions * CPU function * Internal block functions * Instruction set * Interrupt functions * Explanation of each instruction * Other on-chip peripheral functions * Electrical specifications How to Use This Manual It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. * To understand the functions in general: Read this manual in the order of the contents. The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. * How to interpret the register format: Where the bit number is enclosed in angle brackets (<>), the bit name is reserved for the assembler and is defined as an sfr variable by the #pragma sfr directive for the C compiler. * When you know a register name and want to confirm its details: Read APPENDIX B REGISTER INDEX. * To know the 78K/0S Series instruction function in detail: Read 78K/0S Series Instructions User's Manual (U11047E). * To know the PD179322, 179322A, 179324, 179324A, 179326, and 179327 electrical specification in details: Read CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327). * To know the PD78F9328 electrical specification in details: Read CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328). 6 User's Manual U16995EJ2V0UD Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numerical representation: Binary ... xxxx or xxxxB Decimal ... xxxx Hexadecimal ... xxxxH Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. PD179327 Subseries User's Manual This manual 78K/0S Series Instructions User's Manual U11047E Documents Related to Development Software Tools (User's Manuals) Document Name RA78K0S Assembler Package CC78K0S C Compiler SM78K Series Ver. 2.52 System Simulator ID78K0S-NS Ver. 2.52 Integrated Debugger Document No. Operation U16656E Language U14877E Structured Assembly Language U11623E Operation U16654E Language U14872E Operation U16768E External Part User Open Interface Specification U15802E Operation U16584E PM plus Ver.5.10 U16569E Document Related to Development Hardware Tools (User's Manuals) Document Name Document No. IE-78K0S-NS In-Circuit Emulator U13549E IE-78K0S-NS-A In-Circuit Emulator U15207E IE-789468-NS-EM1 Emulation Board To be prepared Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. User's Manual U16995EJ2V0UD 7 Documents Related to Flash Memory Writing Document Name PG-FP4 Flash Memory Programmer User's Manual Document No. U15260E Other Related Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html) Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing. 8 User's Manual U16995EJ2V0UD CONTENTS CHAPTER 1 GENERAL ..........................................................................................................................14 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features.........................................................................................................................................14 Applications ..................................................................................................................................14 Ordering Information....................................................................................................................15 Pin Configuration (Top View) ......................................................................................................16 179K Series Lineup ......................................................................................................................18 Block Diagram ..............................................................................................................................19 Overview of Functions.................................................................................................................20 CHAPTER 2 PIN FUNCTIONS...............................................................................................................22 2.1 List of Pin Functions ....................................................................................................................22 2.2 Description of Pin Functions ......................................................................................................24 2.2.1 P00 to P03 (Port 0) ........................................................................................................................... 24 2.2.2 P10, P11 (Port 1) .............................................................................................................................. 24 2.2.3 P20 to P22 (Port 2) ........................................................................................................................... 24 2.2.4 P40 to P43 (Port 4) ........................................................................................................................... 24 2.2.5 P60, P61 (Port 6) .............................................................................................................................. 25 2.2.6 P80 to P85 (Port 8) ........................................................................................................................... 25 2.2.7 S0 to S16, S23 .................................................................................................................................. 25 2.2.8 COM0 to COM3 ................................................................................................................................ 25 2.2.9 VLC0 ................................................................................................................................................... 25 2.2.10 RESET ............................................................................................................................................ 25 2.2.11 X1, X2 ............................................................................................................................................. 26 2.2.12 XT1, XT2......................................................................................................................................... 26 2.2.13 VDD .................................................................................................................................................. 26 2.2.14 VSS .................................................................................................................................................. 26 2.2.15 VPP (PD78F9328 only) .................................................................................................................. 26 2.2.16 IC0 (mask ROM version only) ......................................................................................................... 26 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ..........................27 CHAPTER 3 CPU ARCHITECTURE......................................................................................................29 3.1 Memory Space ..............................................................................................................................29 3.1.1 Internal program memory space ....................................................................................................... 34 3.1.2 Internal data memory (internal high-speed RAM) space ................................................................... 35 3.1.3 Special function register (SFR) area ................................................................................................. 35 3.1.4 Data memory addressing .................................................................................................................. 36 3.2 Processor Registers ....................................................................................................................41 3.2.1 Control registers................................................................................................................................ 41 3.2.2 General-purpose registers................................................................................................................. 44 3.2.3 Special function registers (SFRs)...................................................................................................... 45 3.3 Instruction Address Addressing.................................................................................................48 3.3.1 Relative addressing........................................................................................................................... 48 3.3.2 Immediate addressing ....................................................................................................................... 49 User's Manual U16995EJ2V0UD 9 3.3.3 Table indirect addressing .................................................................................................................. 50 3.3.4 Register addressing .......................................................................................................................... 50 3.4 Operand Address Addressing.....................................................................................................51 3.4.1 Direct addressing .............................................................................................................................. 51 3.4.2 Short direct addressing ..................................................................................................................... 52 3.4.3 Special function register (SFR) addressing ....................................................................................... 53 3.4.4 Register addressing .......................................................................................................................... 54 3.4.5 Register indirect addressing .............................................................................................................. 55 3.4.6 Based addressing.............................................................................................................................. 56 3.4.7 Stack addressing............................................................................................................................... 56 CHAPTER 4 PORT FUNCTIONS ...........................................................................................................57 4.1 Port Functions ..............................................................................................................................57 4.2 Port Configuration ........................................................................................................................58 4.2.1 Port 0................................................................................................................................................. 59 4.2.2 Port 1................................................................................................................................................. 60 4.2.3 Port 2................................................................................................................................................. 61 4.2.4 Port 4................................................................................................................................................. 64 4.2.5 Port 6................................................................................................................................................. 65 4.2.6 Port 8................................................................................................................................................. 67 4.3 Registers Controlling Port Function ..........................................................................................68 4.4 Port Function Operation ..............................................................................................................72 4.4.1 Writing to I/O port .............................................................................................................................. 72 4.4.2 Reading from I/O port........................................................................................................................ 72 4.4.3 Arithmetic operation of I/O port ......................................................................................................... 72 CHAPTER 5 CLOCK GENERATOR ......................................................................................................73 5.1 5.2 5.3 5.4 Clock Generator Functions .........................................................................................................73 Clock Generator Configuration ...................................................................................................73 Registers Controlling Clock Generator......................................................................................75 System Clock Oscillators ............................................................................................................77 5.4.1 Main system clock oscillator .............................................................................................................. 77 5.4.2 Subsystem clock oscillator ................................................................................................................ 78 5.4.3 Example of incorrect resonator connection ....................................................................................... 79 5.4.4 Divider circuit..................................................................................................................................... 80 5.4.5 When no subsystem clock is used .................................................................................................... 80 5.5 Clock Generator Operation..........................................................................................................81 5.6 Changing Setting of System Clock and CPU Clock..................................................................82 5.6.1 Time required for switching between system clock and CPU clock................................................... 82 5.6.2 Switching between system clock and CPU clock .............................................................................. 83 10 User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 .............................................................................................84 6.1 6.2 6.3 6.4 8-Bit Timers 30 and 40 Functions ...............................................................................................84 8-Bit Timers 30 and 40 Configuration ........................................................................................85 Registers Controlling 8-Bit Timers 30 and 40 ...........................................................................90 8-Bit Timers 30 and 40 Operation ...............................................................................................95 6.4.1 Operation as 8-bit timer counter........................................................................................................ 95 6.4.2 Operation as 16-bit timer counter.................................................................................................... 102 6.4.3 Operation as carrier generator ........................................................................................................ 106 6.4.4 Operation as PWM output (timer 40 only) ....................................................................................... 110 6.5 Notes on Using 8-Bit Timers 30 and 40....................................................................................112 CHAPTER 7 WATCH TIMER ...............................................................................................................113 7.1 7.2 7.3 7.4 Watch Timer Functions..............................................................................................................113 Watch Timer Configuration .......................................................................................................114 Register Controlling Watch Timer ............................................................................................115 Watch Timer Operation..............................................................................................................116 7.4.1 Operation as watch timer ................................................................................................................ 116 7.4.2 Operation as interval timer .............................................................................................................. 116 CHAPTER 8 WATCHDOG TIMER .......................................................................................................118 8.1 8.2 8.3 8.4 Watchdog Timer Functions .......................................................................................................118 Watchdog Timer Configuration.................................................................................................119 Registers Controlling Watchdog Timer ...................................................................................120 Watchdog Timer Operation .......................................................................................................122 8.4.1 Operation as watchdog timer .......................................................................................................... 122 8.4.2 Operation as interval timer .............................................................................................................. 123 CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) ............................................................124 9.1 9.2 9.3 9.4 Serial Interface 10 Functions ....................................................................................................124 Serial Interface 10 Configuration ..............................................................................................125 Registers Controlling Serial Interface 10.................................................................................127 Serial Interface 10 Operation.....................................................................................................129 9.4.1 Operation stop mode....................................................................................................................... 129 9.4.2 3-wire serial I/O mode ..................................................................................................................... 130 CHAPTER 10 LCD CONTROLLER/DRIVER.......................................................................................132 10.1 10.2 10.3 10.4 10.5 10.6 10.7 LCD Controller/Driver Functions ............................................................................................132 LCD Controller/Driver Configuration......................................................................................132 Registers Controlling LCD Controller/Driver.........................................................................134 Setting LCD Controller/Driver .................................................................................................138 LCD Display Data Memory.......................................................................................................139 Common and Segment Signals ..............................................................................................140 Display Modes ..........................................................................................................................143 10.7.1 Static display example................................................................................................................... 143 10.7.2 Four-time slot display example...................................................................................................... 146 User's Manual U16995EJ2V0UD 11 CHAPTER 11 POWER-ON-CLEAR CIRCUITS ...................................................................................149 11.1 11.2 11.3 11.4 Power-on-Clear Circuit Functions ..........................................................................................149 Power-on-Clear Circuit Configuration....................................................................................149 Register Controlling Power-on-Clear Circuit.........................................................................150 Power-on-Clear Circuit Operation ..........................................................................................150 CHAPTER 12 INTERRUPT FUNCTIONS ............................................................................................151 12.1 12.2 12.3 12.4 Interrupt Function Types .........................................................................................................151 Interrupt Sources and Configuration .....................................................................................151 Registers Controlling Interrupt Function...............................................................................154 Interrupt Servicing Operation..................................................................................................158 12.4.1 Non-maskable interrupt request acknowledgment operation......................................................... 158 12.4.2 Maskable interrupt request acknowledgment operation ................................................................ 160 12.4.3 Multiple interrupt servicing............................................................................................................. 161 12.4.4 Putting interrupt requests on hold.................................................................................................. 163 CHAPTER 13 STANDBY FUNCTION ..................................................................................................164 13.1 Standby Function and Configuration .....................................................................................164 13.2 Register Controlling Standby Function .................................................................................165 13.3 Standby Function Operation ...................................................................................................166 13.3.1 HALT mode ................................................................................................................................... 166 13.3.2 STOP mode .................................................................................................................................. 169 CHAPTER 14 RESET FUNCTION .......................................................................................................172 CHAPTER 15 PD78F9328...................................................................................................................176 15.1 Flash Memory Characteristics ................................................................................................177 15.1.1 Programming environment ............................................................................................................ 177 15.1.2 Communication mode ................................................................................................................... 178 15.1.3 On-board pin processing ............................................................................................................... 180 15.1.4 Connection on flash memory writing adapter ................................................................................ 183 CHAPTER 16 MASK OPTIONS ...........................................................................................................184 CHAPTER 17 INSTRUCTION SET ......................................................................................................185 17.1 Operation...................................................................................................................................185 17.1.1 Operand identifiers and description methods ................................................................................ 185 17.1.2 Description of "Operation" column................................................................................................. 186 17.1.3 Description of "Flag" column.......................................................................................................... 186 17.2 Operation List ...........................................................................................................................187 17.3 Instructions Listed by Addressing Type................................................................................192 12 User's Manual U16995EJ2V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) ............................................................................................................................................195 CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328)........................................................205 CHAPTER 20 PACKAGE DRAWING ..................................................................................................217 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS ..........................................................218 APPENDIX A DEVELOPMENT TOOLS ..............................................................................................220 A.1 A.2 A.3 A.4 A.5 A.6 A.7 Software Package ......................................................................................................................222 Language Processing Software ...............................................................................................222 Control Software ........................................................................................................................223 Flash Memory Writing Tools.....................................................................................................223 Debugging Tools (Hardware)....................................................................................................224 Debugging Tools (Software).....................................................................................................225 Cautions when designing target system.................................................................................226 APPENDIX B REGISTER INDEX.........................................................................................................227 B.1 Register Index (Alphabetic Order of Register Name) ............................................................227 B.2 Register Index (Alphabetic Order of Register Symbol) .........................................................229 APPENDIX C REVISION HISTORY ......................................................................................................231 <R> C.1 Major Revisions in This Edition ...............................................................................................231 C.2 Revision History of Preceding Editions ..................................................................................231 User's Manual U16995EJ2V0UD 13 CHAPTER 1 GENERAL 1.1 Features * ROM and RAM capacities Item Data Memory Program Memory (ROM) Internal High-Speed Part Number LCD Display RAM RAM PD179322 4 KB Mask ROM 256 bytes 24 x 4 bits PD179322A PD179324 8 KB PD179324A PD179326 16 KB PD179327 24 KB PD78F9328 Flash memory 512 bytes 32 KB * Minimum instruction execution time can be changed from high-speed (0.4 s: @ 5.0 MHz operation with main system clock) to ultra-low-speed (122 s: @ 32.768 kHz operation with subsystem clock) * I/O ports: 21 * Serial interface (3-wire serial I/O mode): 1 channel * Timer: 4 channels * 8-bit timer: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel * LCD controller/driver Segment signals: 24, common signals: 4 * Vectored interrupt sources Mask ROM versions: 8 * Flash memory version: 9 * * On-chip power-on clear circuit (mask option for mask ROM versions) * Power supply voltage Mask ROM versions: VDD = 1.8 to 3.6 VNote * Flash memory version: VDD = 1.8 to 5.5 VNote * * Operating ambient temperature: TA = -40 to +85C Note For mask ROM version when the use of the POC circuit is selected or for flash memory versions, the minimum value of the operation power supply voltage is the POC detection voltage (1.90.1 V). 1.2 Applications Remote controllers for air conditioners, AV equipments, and water flow (in toilets, baths, etc.), etc. 14 User's Manual U16995EJ2V0UD CHAPTER 1 GENERAL 1.3 Ordering Information Part Number PD179322GB-xxx-8ET PD179322AGB-xxx-8ET PD179324GB-xxx-8ET PD179324AGB-xxx-8ET PD179326GB-xxx-8ET PD179327GB-xxx-8ET PD179322GB-xxx-8ET-A PD179322AGB-xxx-8ET-A PD179324GB-xxx-8ET-A PD179324AGB-xxx-8ET-A PD179326GB-xxx-8ET-A PD179327GB-xxx-8ET-A PD78F9328GB-8ET PD78F9328GB-8ET-A Package Internal ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Mask ROM 52-pin plastic LQFP (10 x 10) Flash memory 52-pin plastic LQFP (10 x 10) Flash memory Remarks 1. xxx indicates ROM code suffix. 2. Products that have the part numbers suffixed by "-A" are lead-free products. User's Manual U16995EJ2V0UD 15 CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P81/S21 P60/TO40 2 38 P82/S20 P43/KR03 3 37 P83/S19 P42/KR02 4 36 P84/S18 P41/KR01 5 35 P85/S17 P40/KR00 6 34 S16 P03 7 33 S15 P02 8 32 S14 P01 9 31 S13 The parenthesized values apply to the PD78F9328. User's Manual U16995EJ2V0UD S8 S7 S6 S5 S4 27 13 14 15 16 17 18 19 20 21 22 23 24 25 26 S3 S10 P10 S2 28 S1 S11 12 S0 29 P11 COM3 S12 COM2 30 11 COM1 10 COM0 P00 INT/P61 Caution Connect the IC0 (Internally Connected) pin directly to VSS. 16 P80/S22 RESET Note SCK10, SO10, and SI10 are provided in the PD78F9328 only. Remark S23 VLC0 P22/SI10Note P21/SO10Note P20/SCK10Note IC0 (VPP) XT1 XT2 VSS VDD X2 X1 52-pin plastic LQFP (10 x 10) S9 CHAPTER 1 GENERAL COM0 to COM3: Common output S0 to S23: Segment output IC0: Internally connected SCK10: Serial clock input/output INT: Interrupt from peripherals SI10: Serial data input KR00 to KR03: Key return SO10: Serial data output P00 to P03: Port 0 TO40: Timer output P10, P11: Port 1 VDD: Power supply P20 to P22: Port 2 VLC0: Power supply for LCD P40 to P43: Port 4 VPP: Programming power supply P60, P61: Port 6 VSS: Ground P80 to P85: Port 8 X1, X2: Crystal (main system clock) RESET: Reset XT1, XT2: Crystal (subsystem clock) User's Manual U16995EJ2V0UD 17 CHAPTER 1 GENERAL 1.5 179K Series Lineup The products in the 179K Series are listed below. The names enclosed in boxes are subseries names. For pre-set remote controller 30-pin 179K Series On-chip the low-voltage detector, the data retention voltage detector, and key return circuit PD179088 For LCD remote controller 52-pin PD179327 On-chip the resistance division type LCD (24 x 4) The major differences between subseries are shown below. Function Subseries ROM Capacity (Bytes) I/O Timer 8-Bit 16-Bit Watch WDT VDD Remarks MIN.Value For pre-set remote controller PD179088 16 K-32 k 3 ch 1 ch 1 ch 1 ch 24 1.8 V - For LCD remote controller PD179327 4 K to 24 K 2 ch - 1 ch 1 ch 21 1.8 V - 18 User's Manual U16995EJ2V0UD CHAPTER 1 GENERAL 1.6 Block Diagram TO40/P60 8-bit timer 30 Cascaded 16-bit 8-bit timer timer 40 Watch timer 78K/0S CPU core ROM (flash memory) Port 0 P00 to P03 Port 1 P10, P11 Port 2 P20 to P22 Port 4 P40 to P43 Port 6 P60, P61 Port 8 P80 to P85 Watchdog timer SCK10Note1/P20 SO10Note1/P21 SI10Note1/P22 Serial interface 10Note1 RAM RAM space for LCD data S0 to S23 COM0 to COM3 System control LCD controller/driver VLC0 RESET X1 X2 XT1 XT2 INT/P61 Note2 Interrupt control Power-on clear VDD VSS KR00/P40 to KR03/P43 IC0 (VPP) Notes 1. The serial interface 10 is provided in the PD78F9328 only. 2. Only when use of the POC circuit is selected by a mask option in the case of mask ROM versions (PD179322, 179322A, 179324, 179324A, 179326, and 179327). Remarks 1. The internal ROM and RAM capacities vary depending on the product. 2. The parenthesized values apply to the PD78F9328. User's Manual U16995EJ2V0UD 19 CHAPTER 1 GENERAL 1.7 Overview of Functions PD179327 Subseries Part Number PD789327 Subseries Item Internal memory ROM PD179322 PD179324 PD179326 PD179322A PD179324A PD179327 Mask ROM 4 KB High-speed RAM 256 bytes LCD display RAM 24 x 4 bits PD78F9328 Flash memory 8 KB 16 KB 24 KB 32 KB 512 bytes Main system clock (oscillation frequency) Ceramic/crystal oscillation (1.0 to 5.0 MHz) Subsystem clock (oscillation frequency) Crystal oscillation (32.768 kHz) Minimum instruction execution time 0.4 s/1.6 s (@ 5.0 MHz operation with main system clock) 122 s (@ 32.768 kHz operation with subsystem clock) General-purpose registers Instruction set 8 bits x 8 registers * 16-bit operations * Bit manipulations (such as set, reset, and test) I/O ports Note 1 CMOS I/O: Timers Timer outputs 21 * 8-bit timer: 2 channels * Watch timer: 1 channel * Watchdog timer: 1 channel 1 - Serial interface 3-wire serial I/O mode: 1 channel LCD controller/driver Note 1 * Segment signal outputs: 24 * Common signal outputs: 4 * Mode: Static mode and 1/3 bias mode Vectored interrupt Maskable sources Non-maskable Reset Internal: 5 Internal: 6 external: 2 external: 2 Internal: 1 * Reset by RESET input * Internal reset by watchdog timer Note 2 * Reset by power-on-clear circuit Power supply voltage VDD = 1.8 to 3.6 V Note 3 VDD = 1.8 to 5.5 V Operating ambient temperature TA = -40 to +85C Package 52-pin plastic LQFP (10 x 10) Notes Note 3 1. Six among these pins are used to select either port function or LCD segment output via the port function 2. For mask ROM versions (PD179322, 179322A, 179324, 179324A, 179326, 179327), this is available register. only when the use of POC circuit is selected by mask option. 3. For mask ROM versions when the use of the POC circuit is selected or for flash memory versions, the minimum value of the operation power supply voltage is the POC detection voltage (1.9 0.1 V). 20 User's Manual U16995EJ2V0UD CHAPTER 1 GENERAL An outline of the timer is shown below. 8-Bit Timer 30 Operation mode Function Interval timer 8-Bit Timer 40 Watch Timer 1 channel Note 1 Watchdog Timer 1 channel 1 channel 1 channel External event counter - - - - Timer outputs - 1 output - - Square-wave outputs - 1 output - - Capture - - - - Interrupt sources 1 1 2 2 Note 2 Notes 1. The watch timer can perform both watch timer and interval timer functions at the same time. 2. The watchdog timer has the watchdog timer and interval timer functions. However, use the watchdog timer by selecting either the watchdog timer function or interval timer function. User's Manual U16995EJ2V0UD 21 CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions (1) Port pins Pin Name P00 to P03 I/O Function Input/ Port 0. output This is a 4-bit I/O port. After Reset Alternate Function Input - Input - Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified in port units using pull-up resistor option register 0 (PU0). P10, P11 Input/ Port 1. output This is a 2-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified in port units using pull-up resistor option register 0 (PU0). P20 P21 Input/ Port 2. output This is a 3-bit I/O port. Input SCK10 SO10 Input/output can be specified in 1-bit units. P22 SI10 On-chip pull-up resistors can be specified in 1-bit units using Note Note Note pull-up resistor option register 2 (PUB2). P40 to P43 Input/ Port 4. output This is a 4-bit I/O port. Input KR00 to KR03 Input TO40 Input/output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified in port units using pull-up resistor option register 0 (PU0), or key return mode register 00 (KRM00). P60 P61 P80 to P85 Input/ Port 6. output This is a 2-bit I/O port. Input/ Port 8. output This is a 6-bit I/O port. Input Input/output can be specified in 1-bit units. Note SCK10, SO10, and SI10 are provided in PD78F9328 only. 22 INT Input/output can be specified in 1-bit units. User's Manual U16995EJ2V0UD S22 to S17 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name INT I/O Input Function External interrupt input for which the valid edge (rising edge, After Reset Alternate Function Input P61 falling edge, or both rising and falling edges) can be specified. KR00 to KR03 Input Key return signal detection Input P40 to P43 TO40 Output 8-bit timer 40 output Input P60 Input/ Serial clock input/output of serial interface 10 Input P20 Input Serial data input of serial interface 10 Input P22 Output Serial data output of serial interface 10 Input P21 Output LCD controller/driver segment signal outputs Low-level SCK10 Note output SI10 Note SO10 Note S0 to S16 - output S17 to S22 Input P85 to P80 S23 Low-level - output COM0 to COM3 Output LCD controller/driver common signal outputs Low-level - output VLC0 X1 X2 - Input - XT1 Input XT2 - RESET Input LCD drive voltage - - Connecting crystal/ceramic resonator for main system clock - - oscillation - - Connecting crystal resonator for subsystem clock oscillation - - - - System reset input - Input VDD - Positive power supply - - VSS - Ground potential - - IC0 - Internally connected. Connect directly to VSS. - - VPP - Sets flash memory programming mode. Applies high voltage - - when a program is written or verified. Note SCK10, SO10, and SI10 are provided in PD78F9328 only. User's Manual U16995EJ2V0UD 23 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (Port 0) These pins constitute a 4-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 0 (PM0). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) in port units. 2.2.2 P10, P11 (Port 1) These pins constitute a 2-bit I/O port and can be set in the input or output port mode in 1-bit units by port mode register 1 (PM1). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) in port units. 2.2.3 P20 to P22 (Port 2) These pins constitute a 3-bit I/O port. In addition, these pins enable serial interface data I/O and clock I/O in PD78F9328 only. Port 2 can be specified in the following operation modes in 1-bit units. (1) Port mode In this mode, P20 to P22 function as a 3-bit I/O port. Port 2 can be set in the input or output port mode in 1bit units by port mode register 2 (PM2). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register B2 (PUB2) in 1-bit units. (2) Control mode In this mode, P20 to P22 function as the serial interface data I/O and clock I/O. (a) SI10 Note , SO10 Note These are the serial data I/O pins of the serial interface. (b) SCK10 Note This is the serial clock I/O pin of the serial interface. Note SCK10, SO10, and SI10 are provided in PD78F9328 only. Caution When using P20 to P22 as serial interface pins, the I/O mode and output latch must be set according to the functions to be used. For the details of the setting, refer to Table 9-2 Settings of Serial Interface 10 Operating Mode. 2.2.4 P40 to P43 (Port 4) These pins constitute a 4-bit I/O port. In addition, they also function as key return signal detection. Port 4 can be specified in the following operation mode in 1-bit units. (1) Port mode In this mode, port 4 functions as a 4-bit I/O port. Port 4 can be set in the input or output port mode in 1-bit units by port mode register 4 (PM4). When used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0) or key return mode register 00 (KRM00) in port units. 24 User's Manual U16995EJ2V0UD CHAPTER 2 PIN FUNCTIONS (2) Control mode In this mode, the pins function as key return signal detection (KR00 to KR03). 2.2.5 P60, P61 (Port 6) These pins constitute a 2-bit I/O port. In addition, they also function as timer output and external interrupt input. Port 6 can be specified in the following operation mode in 1-bit units. (1) Port mode In this mode, port 6 functions as a 2-bit I/O port. Port 6 can be set in the input or output port mode in 1-bit units by port mode register 6 (PM6). (2) Control mode In this mode, the pins function as timer output and external interrupt input. (a) TO40 This is the timer output pin to timer 40. (b) INT This is the external interrupt input pin for which valid edges (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.6 P80 to P85 (Port 8) These pins constitute a 6-bit I/O port. In addition, they also function as LCD controller/driver segment signal output. Port 8 can be specified in the following operation mode in 1-bit units by port function register 8 (PF8). (1) Port mode In this mode, port 8 functions as a 6-bit I/O port. Port 8 can be set in the input or output port mode in 1-bit units by port mode register 8 (PM8). (2) Control mode In this mode, the pins function as LCD controller/driver segment signal output (S17 to S22). 2.2.7 S0 to S16, S23 These pins are segment signal output pins for the LCD controller/driver. 2.2.8 COM0 to COM3 These pins are common signal output pins for the LCD controller/driver. 2.2.9 VLC0 This pin is the power supply voltage pin to drive the LCD. 2.2.10 RESET This pin inputs an active-low system reset signal. User's Manual U16995EJ2V0UD 25 CHAPTER 2 PIN FUNCTIONS 2.2.11 X1, X2 These pins are used to connect a crystal/ceramic resonator for main system clock oscillation. To supply an external clock, input the clock to X1 and input the inverted signal to X2. 2.2.12 XT1, XT2 These pins are used to connect a crystal resonator for subsystem clock oscillation. To supply an external clock, input the clock to XT1 and input the inverted signal to XT2. 2.2.13 VDD This is the positive power supply pin. 2.2.14 VSS This is the ground pin. 2.2.15 VPP (PD78F9328 only) A high voltage should be applied to this pin when the flash memory programming mode is set and when the program is written or verified. Perform either of the following. * Independently connect a 10 k pull-down resistor to VPP. * Use the jumper on the board to connect VPP to the dedicated flash programmer or VSS, in programming mode or normal operation mode, respectively. If the wiring between the VPP and VSS pins is long or external noise is superimposed on the VPP pin, the userprogram may not run correctly. 2.2.16 IC0 (mask ROM version only) The IC0 (Internally Connected) pin is used to set the PD179322, 179322A, 179324, 179324A, 179326, and 179327 in the test mode before shipment. In the normal operation mode, directly connect this pin to the VSS pin with as short a wiring length as possible. If a potential difference is generated between the IC0 pin and VSS pin due to a long wiring length, or an external noise superimposed on the IC0 pin, the user program may not run correctly. * Directly connect the IC0 pin to the VSS pin. VSS IC0 Keep short 26 User's Manual U16995EJ2V0UD CHAPTER 2 PIN FUNCTIONS 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, see Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name I/O Circuit Type 5-A P00 to P03 I/O I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P10, P11 P20/SCK10 P21/SO10 P22/SI10 Recommended Connection of Unused Pins Note1 8-A Note1 Note1 P40/KR00 to P43/KR03 P60/TO40 5 P61/INT 8 Input: Independently connect to VSS via a resistor. Output: Leave open. P80/S22 to P85/S17 17-N Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. S0 to S16, S23 17-D COM0 to COM3 18-B Output Leave open. Note2 - Connect to VDD XT1 Input Connect to VSS. XT2 - - VLC0 RESET 2 Input IC0 (mask ROM version) - - VPP (PD78F9328) . Leave open. - Connect directly to VSS. Independently connect VPP to a 10 k pull-down resistor or directly connect to VSS. Notes 1. SCK10, SO10, and SI10 are provided in PD78F9328 only. 2. The current flows from VLC0 to VSS via the LCD division resistors. Figure 2-1. I/O Circuit Type (1/2) Type 2 Type 5 VDD Data P-ch IN IN/OUT Output disable Schmitt-triggered input with hysteresis characteristics. N-ch VSS Input enable User's Manual U16995EJ2V0UD 27 CHAPTER 2 PIN FUNCTIONS Figure 2-1. I/O Circuit Type (2/2) Type 5-A Type 8 VDD Pull-up enable VDD P-ch Data VDD P-ch IN/OUT Data P-ch IN/OUT Output disable Output disable N-ch VSS N-ch VSS Input enable Type 8-A Type 17-D VDD VLC0 P-ch Pull-up enable P-ch VLC1 P-ch N-ch VDD Data P-ch SEG data P-ch OUT N-ch IN/OUT Output disable P-ch N-ch VLC2 N-ch N-ch VSS VSS Type 17-N Type 18-B VLC0 Data P-ch IN/OUT Output disable N-ch VDD VSS VLC0 Input enable VLC1 P-ch P-ch N-ch P-ch N-ch VLC0 P-ch VLC1 P-ch N-ch P-ch N-ch VLC2 N-ch SEG data N-ch VSS P-ch N-ch VLC2 N-ch VSS Remark VLC1: VLC0 x 2/3, VLC2: VLC0/3 28 OUT COM data P-ch N-ch User's Manual U16995EJ2V0UD P-ch CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space The PD179327 Subseries can access 64 KB of memory space. Figures 3-1 through 3-5 show the memory maps. Figure 3-1. Memory Map (PD179322 and 179322A) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH FA18H FA17H Data memory space Reserved LCD display RAM 24 x 4 bits FA00H F9FFH 0FFFH Reserved 1000H 0FFFH Program area Program memory space Internal ROM 4096 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0014H 0013H 0000H 0000H User's Manual U16995EJ2V0UD Vector table area 29 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (PD179324 and 179324A) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 256 x 8 bits FE00H FDFFH FA18H FA17H Data memory space Reserved LCD display RAM 24 x 4 bits FA00H F9FFH 2000H 1FFFH 1FFFH Reserved Program area Program memory space Internal ROM 8192 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0014H 0013H 0000H 30 0000H User's Manual U16995EJ2V0UD Vector table area CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (PD179326) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH FA18H FA17H Data memory space Reserved LCD display RAM 24 x 4 bits FA00H F9FFH 4000H 3FFFH 3FFFH Reserved Program area Program memory space Internal ROM 16384 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0014H 0013H 0000H 0000H User's Manual U16995EJ2V0UD Vector table area 31 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map (PD179327) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH Reserved FA18H FA17H Data memory space LCD display RAM 24 x 4 bits FA00H F9FFH 5FFFH Reserved 6000H 5FFFH Program area Program memory space Internal ROM 24576 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0014H 0013H 0000H 0000H 32 User's Manual U16995EJ2V0UD Vector table area CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map (PD78F9328) FFFFH Special function registers 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH Reserved FA18H FA17H Data memory space LCD display RAM 24 x 4 bits FA00H F9FFH 7FFFH Reserved 8000H 7FFFH Program area Program memory space Flash memory 32768 x 8 bits 0080H 007FH CALLT table area 0040H 003FH Program area 0014H 0013H 0000H 0000H User's Manual U16995EJ2V0UD Vector table area 33 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The PD179327 Subseries provide internal ROM (or flash memory) with the following capacity for each product. Table 3-1. Internal ROM Capacity Part Number Internal ROM Structure PD179322 and 179322A Capacity 4096 x 8 bits Mask ROM PD179324 and 179324A 8192 x 8 bits PD179326 16384 x 8 bits PD179327 24576 x 8 bits PD78F9328 32768 x 8 bits Flash memory The following areas are allocated to the internal program memory space. (1) Vector table area The 20-byte area of addresses 0000H to 0013H is reserved as a vector table area. This area stores program start addresses to be used when branching by the RESET input or an interrupt request generation. Of a 16bit program address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address. Table 3-2. Vector Table Vector Table Address Interrupt Request Vector Table Address Interrupt Request 0000H RESET input 000CH INTTM30 0004H INTWDT 000EH INTTM40 0010H INTKR00 0012H INTWTI 0006H INTP0 Note 0008H INTCSI10 000AH INTWT Note Note The PD78F9328 only (2) CALLT instruction table area The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of addresses 0040H to 007FH. 34 User's Manual U16995EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory (internal high-speed RAM) space The PD179327 Subseries products incorporate the following RAM. (1) Internal high-speed RAM Internal high-speed RAM is incorporated in the area between FE00H and FEFFH in the PD179322, 179322A, 179324 and 179324A, and in the area between FD00H and FEFFH in the PD179326, 179327, and 78F9328. Instructions cannot be written to this on-chip high-speed RAM as a program area for execution. The internal high-speed RAM is also used as a stack. (2) LCD display RAM LCD display RAM is allocated in the area between FA00H and FA17H. The LCD display RAM can also be used as ordinary RAM. 3.1.3 Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated in the area between FF00H and FFFFH (see Table 3-3). User's Manual U16995EJ2V0UD 35 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing The PD179327 Subseries are provided with a variety of addressing modes to make memory manipulation as efficient as possible. At the addresses corresponding to data memory area especially, specific addressing modes that correspond to the particular function an area, such as the special function registers are available. Figures 3-6 through 3-10 show the data memory addressing modes. Figure 3-6. Data Memory Addressing (PD179322 and 179322A) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH Direct addressing FE00H FDFFH Register indirect addressing Reserved FA18H FA17H Based addressing LCD display RAM 24 x 4 bits FA00H F9FFH Reserved 1000H 0FFFH Internal ROM 4096 x 8 bits 0000H 36 User's Manual U16995EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-7. Data Memory Addressing (PD179324 and 179324A) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 256 x 8 bits FE20H FE1FH Direct addressing FE00H FDFFH Register indirect addressing Reserved FA18H FA17H Based addressing LCD display RAM 24 x 4 bits FA00H F9FFH Reserved 2000H 1FFFH Internal ROM 8192 x 8 bits 0000H User's Manual U16995EJ2V0UD 37 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Data Memory Addressing (PD179326) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH Direct addressing FD00H FCFFH Register indirect addressing Reserved FA18H FA17H Based addressing LCD display RAM 24 x 4 bits FA00H F9FFH Reserved 4000H 3FFFH Internal ROM 16384 x 8 bits 0000H 38 User's Manual U16995EJ2V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Data Memory Addressing (PD179327) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH Direct addressing FD00H FCFFH Register indirect addressing Reserved FA18H FA17H Based addressing LCD display RAM 24 x 4 bits FA00H F9FFH Reserved 6000H 5FFFH Internal ROM 24576 x 8 bits 0000H User's Manual U16995EJ2V0UD 39 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data Memory Addressing (PD78F9328) FFFFH Special function registers (SFRs) 256 x 8 bits SFR addressing FF20H FF1FH FF00H FEFFH Short direct addressing Internal high-speed RAM 512 x 8 bits FE20H FE1FH Direct addressing FD00H FCFFH Register indirect addressing Reserved FA18H FA17H Based addressing LCD display RAM 24 x 4 bits FA00H F9FFH Reserved 8000H 7FFFH Flash memory 32768 x 8 bits 0000H 40 User's Manual U16995EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The PD179327 Subseries provide the following on-chip processor registers. 3.2.1 Control registers The control registers contain special functions to control the program sequence statuses and stack memory. The program counter, program status word, and stack pointer are control registers. (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data or register contents are set. RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter. Figure 3-11. Program Counter Configuration 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 (2) PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. The program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions. RESET input sets PSW to 02H. Figure 3-12. Program Status Word Configuration 7 PSW IE 0 Z 0 AC 0 User's Manual U16995EJ2V0UD 0 1 CY 41 CHAPTER 3 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledgement operations of the CPU. When 0, IE is set to the interrupt disable status (DI), and interrupt requests other than non-maskable interrupt are all disabled. When 1, IE is set to the interrupt enable status (EI). Interrupt request acknowledgement enable is controlled with an interrupt mask flag for various interrupt sources. IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (d) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction execution. 42 User's Manual U16995EJ2V0UD CHAPTER 3 CPU ARCHITECTURE (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-13. Stack Pointer Configuration 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-14 and 3-15. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before instruction execution. Figure 3-14. Data to Be Saved to Stack Memory PUSH rp instruction Interrupt CALL, CALLT instructions SP SP SP _ 2 SP SP _ 2 SP _ 3 SP _ 3 PC7 to PC0 SP _ 2 Lower register pairs SP _ 2 PC7 to PC0 SP _ 2 PC15 to PC8 SP _ 1 Higher register pairs SP _ 1 PC15 to PC8 SP _ 1 PSW SP SP SP Figure 3-15. Data to Be Restored from Stack Memory POP rp instruction SP RET instruction RETI instruction SP Lower register pairs SP PC7 to PC0 SP PC7 to PC0 SP + 1 Higher register pairs SP + 1 PC15 to PC8 SP + 1 PC15 to PC8 SP + 2 PSW SP + 2 SP SP + 2 SP User's Manual U16995EJ2V0UD SP + 3 43 CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX, BC, DE, and HL). General-purpose registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, or HL) or absolute names (R0 to R7 and RP0 to RP3). Figure 3-16. General-Purpose Register Configuration (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 44 0 7 User's Manual U16995EJ2V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. The special function registers are allocated in the 256-byte area of FF00H to FFFFH. Special function registers can be manipulated, like general-purpose registers, by operation, transfer, and bit manipulation instructions. The manipulatable bit units (1, 8, and 16) differ depending on the special function register type. The manipulatable bits can be specified as follows. * 1-bit manipulation Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. * 16-bit manipulation Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When addressing an address, describe an even address. Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows: * Symbol Indicates the addresses of the implemented special function registers. The symbols shown in this column are reserved for the assembler and are defined as an sfr variable by the #pragma sfr directive for the C compiler. Therefore, these symbols can be used as instruction operands if an assembler or integrated debugger is used. * R/W Indicates whether the special function register in question can be read or written. R/W: Read/write R: Read only W: Write only * Bit unit for manipulation Indicates the bit units (1, 8, 16) in which the special function register in question can be manipulated. * After reset Indicates the status of the special function register when the RESET signal is input. User's Manual U16995EJ2V0UD 45 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name Symbol R/W R/W Bit Unit for Manipulation 1 Bit 8 Bits 16 Bits - After Reset FF00H Port 0 P0 FF01H Port 1 P1 - FF02H Port 2 P2 - FF04H Port 4 P4 - FF06H Port 6 P6 - FF08H Port 8 P8 - FF20H Port mode register 0 PM0 - FF21H Port mode register 1 PM1 - FF22H Port mode register 2 PM2 - FF24H Port mode register 4 PM4 - FF26H Port mode register 6 PM6 - FF28H Port mode register 8 PM8 - 3FH FF32H Pull-up resistor option register B2 PUB2 - 00H FF42H Watchdog timer clock selection register TCL2 - - FF4AH Watch timer mode control register WTM - FF58H Port function register 8 PF8 - FF63H 8-bit compare register 30 CR30 W - - Undefined FF64H 8-bit timer counter 30 TM30 R - - 00H FF65H 8-bit timer mode control register 30 TMC30 R/W - FF66H 8-bit compare register 40 CR40 W - - FF67H 8-bit H width compare register 40 - - FF68H 8-bit timer counter 40 FF69H FF6AH CRH40 FFH Undefined TM40 R - - 8-bit timer mode control register 40 TMC40 R/W - Carrier generator output control register 40 TCA40 W - - R/W - - Undefined 00H Note1 CSIM10 Note1 FF72H Serial operation mode register 10 FF74H Transmission/reception shift register 10 FFB0H LCD display mode register 0 LCDM0 - FFB2H LCD clock control register 0 LCDC0 - POCF1 - Note1 FFDDH Power-on-clear register 1 Notes 1. 2. 46 00H SIO10 Note1 Provided in PD78F9328 only. Do not access this address for a mask ROM version. This value is 04H only after a power-on-clear reset. User's Manual U16995EJ2V0UD 00H Note2 00H CHAPTER 3 CPU ARCHITECTURE Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name Symbol R/W Bit Unit for Manipulation After Reset 1 Bit 8 Bits 16 Bits - 00H MK0 - FFH FFECH External interrupt mode register 0 INTM0 - 00H FFF0H Suboscillation mode register SCKM - FFF2H Subclock control register CSS - FFF5H Key return mode register 00 KRM00 - FFF7H Pull-up resistor option register 0 PU0 - FFF9H Watchdog timer mode register WDTM - OSTS - 04H PCC - 02H FFE0H Interrupt request flag register 0 FFE4H Interrupt mask flag register 0 IF0 FFFAH Oscillation stabilization time selection register FFFBH Processor clock control register User's Manual U16995EJ2V0UD R/W 47 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by the following addressing (for details of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E)). 3.3.1 Relative addressing [Function] The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start address of the following instruction is transferred to the program counter (PC) and branched. The displacement value is treated as signed two's complement data (-128 to +127) and bit 7 becomes a sign bit. This means that information is relatively branched to a location between -128 and +127, from the start address of the next instruction when relative addressing is used. This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed. [Illustration] 15 0 ... PC is the start address of PC the next instruction of a BR instruction. + 15 8 7 0 6 S jdisp8 15 0 PC When S = 0, indicates all bits 0. When S = 1, indicates all bits 1. 48 User's Manual U16995EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to any location in the memory space. [Illustration] In case of CALL !addr16 and BR !addr16 instructions 7 0 CALL or BR Low Addr. High Addr. 15 8 7 0 PC User's Manual U16995EJ2V0UD 49 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by the lower 5-bit immediate data of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. The instruction enables a branch to any location in the memory space by referring to the addresses stored in the memory table at 40H to 7FH. [Illustration] 7 Instruction code 6 0 5 1 1 ta4-0 0 15 Effective address 0 7 0 0 0 0 0 0 0 Memory (Table) 8 7 6 0 0 1 5 1 0 0 0 Low Addr. High Addr. Effective address + 1 8 15 7 0 PC 3.3.4 Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 X 8 7 PC 50 0 User's Manual U16995EJ2V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following various methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated with immediate data in an instruction word is directly addressed. [Operand format] Identifier addr16 Description Label or 16-bit immediate data [Description example] MOV A, !FE00H; When setting !addr16 to FE00H Instruction code 0 0 1 0 1 0 0 1 OP code 0 0 0 0 0 0 0 0 00H 1 1 1 1 1 1 1 0 FEH [Illustration] 7 0 OP code addr16 (Lower) addr16 (Higher) Memory User's Manual U16995EJ2V0UD 51 CHAPTER 3 CPU ARCHITECTURE 3.4.2 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space is the 256-byte space FE20H to FF1FH where the addressing is applied. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the whole SFR area. Ports that are frequently accessed in a program and the compare register of the timer counter are mapped in this area, and these SFRs can be manipulated with a small number of bytes and clocks. When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is set to 0. When it is at 00H to 1FH, bit 8 is set to 1. See [Illustration] below. [Operand format] Identifier Description saddr Label or FE20H to FF1FH immediate data saddrp Label or FE20H to FF1FH immediate data (even address only) [Description example] MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H Instruction code 1 1 1 1 0 1 0 1 OP code 1 0 0 1 0 0 0 0 90H (saddr-offset) 0 1 0 1 0 0 0 0 50H (Immediate data) [Illustration] 7 0 OP code saddr-offset Short direct memory 8 15 Effective address 1 1 1 1 1 1 1 When 8-bit immediate data is 20H to FFH, = 0. When 8-bit immediate data is 00H to 1FH, = 1. 52 User's Manual U16995EJ2V0UD 0 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Special function register (SFR) addressing [Function] The memory-mapped special function registers (SFRs) are addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can also be accessed with short direct addressing. [Operand format] Identifier Description sfr Special function register name [Description example] MOV PM0, A; When selecting PM0 for sfr Instruction code 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 [Illustration] 7 0 OP code sfr-offset SFR 8 7 15 Effective address 1 1 1 1 1 1 1 0 1 User's Manual U16995EJ2V0UD 53 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Register addressing [Function] In the register addressing mode, general-purpose registers are accessed as operands. The general-purpose register to be accessed is specified by a register specification code or functional name in the instruction code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL r and rp can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL). [Description example] MOV A, C; When selecting the C register for r Instruction code 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 Register specification code INCW DE; When selecting the DE register pair for rp Instruction code 1 0 0 0 1 0 0 0 Register specification code 54 User's Manual U16995EJ2V0UD CHAPTER 3 CPU ARCHITECTURE 3.4.5 Register indirect addressing [Function] In the register indirect addressing mode, memory is manipulated according to the contents of a register pair specified as an operand. The register pair to be accessed is specified by the register pair specification code in an instruction code. This addressing can be carried out for all the memory spaces. [Operand format] Identifier Description - [DE], [HL] [Description example] MOV A, [DE]; When selecting register pair [DE] Instruction code 0 0 1 0 1 0 1 1 [Illustration] 15 DE 8 7 D 0 E 7 Addressed memory contents are transferred. 7 0 Memory address specified with register pair DE. 0 A User's Manual U16995EJ2V0UD 55 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces. [Operand format] Identifier - Description [HL+byte] [Description example] MOV A, [HL+10H]; When setting byte to 10H Instruction code 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 0 3.4.7 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. Only the internal high-speed RAM area can be addressed using stack addressing. [Description example] In the case of PUSH DE Instruction code 56 1 0 1 0 User's Manual U16995EJ2V0UD 1 0 1 0 CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The PD179327 Subseries provide the ports shown in Figure 4-1, enabling various methods of control. Numerous other functions are provided that can be used in addition to the digital I/O port functions. For more information on these additional functions, see CHAPTER 2 PIN FUNCTIONS. Figure 4-1. Port Types P00 P40 Port 4 Port 6 Port 0 P43 P03 P60 P61 P10 P11 P80 P20 Port 1 Port 2 P22 Port 8 P85 User's Manual U16995EJ2V0UD 57 CHAPTER 4 PORT FUNCTIONS Table 4-1. Port Functions Port Name Port 0 Pin Name P00 to P03 Function This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0). Port 1 P10, P11 This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0). Port 2 P20 to P22 This is an I/O port for which input and output can be specified in 1-bit units. On-chip pull-up resistors can be specified using pull-up resistor option register B2 (PUB2). Port 4 P40 to P43 This is an I/O port for which input and output can be specified in 1-bit units. When used as an input port, on-chip pull-up resistors can be specified using pull-up resistor option register 0 (PU0), or key return mode register 00 (KRM00). Port 6 P60, P61 This is an I/O port for which input and output can be specified in 1-bit units. Port 8 P80 to P85 This is an I/O port for which input and output can be specified in 1-bit units. 4.2 Port Configuration The ports include the following hardware. Table 4-2. Configuration of Port Item Control registers Configuration Port mode registers (PMm: m = 0 to 2, 4, 6, 8) Pull-up resistor option registers (PU0, PUB2) Port function register 8 (PF8) Ports Total: 21 (CMOS I/O: 21) Pull-up resistors Total: 13 (software control: 13) 58 User's Manual U16995EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 0 Port 0 is a 4-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using the port mode register 0 (PM0). When the P00 to P03 pins are used as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (PU0). RESET input sets port 0 in the input mode. Figure 4-2 shows a block diagram of port 0. Figure 4-2. Block Diagram of P00 to P03 VDD WRPU0 PU00 P-ch Selector Internal bus RD WRPORT Output latch (P00 to P03) P00 to P03 WRPM PM00 to PM03 PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 0 read signal WR: Port 0 write signal User's Manual U16995EJ2V0UD 59 CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 1 Port 1 is a 2-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using port mode register 1 (PM1). When using the P10 and P11 pins as input port pins, on-chip pull-up resistors can be connected in 2-bit units by using pull-up resistor option register 0 (PU0). RESET input sets port 1 in the input mode. Figure 4-3 shows a block diagram of port 1. Figure 4-3. Block Diagram of P10 and P11 VDD WRPU0 PU01 P-ch Selector Internal bus RD WRPORT Output latch (P10, P11) P10, P11 WRPM PM10, PM11 60 PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 1 read signal WR: Port 1 write signal User's Manual U16995EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 2 Port 2 is a 3-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using port mode register 2 (PM2). On-chip pull-up resistors can be connected in 1-bit units by using pull-up resistor option register B2 (PUB2) regardless of whether the port is in the input or output mode. This port can also be used as serial interface data I/O in the PD78F9328. RESET input sets port 2 in the input mode. Figures 4-4 to 4-6 show block diagrams of port 2. Caution When using the pins of port 2 as the serial interface, the I/O or output latch must be set according to the function to be used. For how to set the latches, see Table 9-2 Settings of Serial Interface 10 Operating Mode. Figure 4-4. Block Diagram of P20 VDD WRPUB2 PUB20 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P20) P20/SCK10Note WRPM PM20 Alternate function PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal Note SCK10 is provided in the PD78F9328 only. User's Manual U16995EJ2V0UD 61 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P21 VDD WRPUB2 PUB21 P-ch Selector Internal bus RD WRPORT Output latch (P21) P21/SO10Note WRPM PM21 Alternate function PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal Note SO10 is provided in the PD78F9328 only. 62 User's Manual U16995EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P22 VDD WRPUB2 PUB22 P-ch Alternate function Selector Internal bus RD WRPORT Output latch (P22) P22/SI10Note WRPM PM22 PUB2: Pull-up resistor option register B2 PM: Port mode register RD: Port 2 read signal WR: Port 2 write signal Note SI10 is provided in the PD78F9328 only. User's Manual U16995EJ2V0UD 63 CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is a 4-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using port mode register 4 (PM4). When using the P40 to P43 pins as input port pins, on-chip pull-up resistors can be connected in 4-bit units by using pull-up resistor option register 0 (PU0). This port is also used as a key return. RESET input sets port 4 in the input mode. Figure 4-7 shows block diagram of port 4. Figure 4-7. Block Diagram of P40 to P43 VDD WRPU0 PU04 P-ch Selector RD WRKRM00 Internal bus KRM000 WRPORT Output latch (P40 to P43) P40/KR00 to P43/KR03 WRPM PM40 to PM43 Alternate function KRM00: Key return mode register 00 64 PU0: Pull-up resistor option register 0 PM: Port mode register RD: Port 4 read signal WR: Port 4 write signal User's Manual U16995EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 6 Port 6 is a 2-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using port mode register 6 (PM6). This port is also used as a timer output and external interrupt input. RESET input sets port 6 in the input mode. Figures 4-8 and 4-9 show block diagrams of port 6. Figure 4-8. Block Diagram of P60 Internal bus Selector RD WRPORT Output latch (P60) P60/TO40 WRPM PM60 Alternate function PM: Port mode register RD: Port 6 read signal WR: Port 6 write signal User's Manual U16995EJ2V0UD 65 CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P61 Alternate function Selector Internal bus RD WRPORT Output latch (P61) P61/INT WRPM PM61 66 PM: Port mode register RD: Port 6 read signal WR: Port 6 write signal User's Manual U16995EJ2V0UD CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 8 Port 8 is a 6-bit I/O port with an output latch. It can be specified in the input or output mode in 1-bit units by using port mode register 8 (PM8). This port is also used as a segment output, and can be switched to the port function or segment output function in 1-bit units by port function register 8 (PF8). RESET input sets port 8 in the input mode. Figure 4-10 shows a block diagram of port 8. Figure 4-10. Block Diagram of P80 to P85 RD Selector VDD WRPORT VLC0 Level shifter Internal bus Output latch (P80 to P85) P80/S22 to P85/S17 WRPM PM80 to PM85 WRPF PF80 to PF85 VLC0 Level shifter Alternate function PF: Port function register RD: Port 8 read signal WR: Port 8 write signal Caution When using port 8 as an output port, the high-level output voltage is VLC0, not VDD. When a high level is output from the output port, pay attention to the current capacity. User's Manual U16995EJ2V0UD 67 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function The ports are controlled by the following three types of registers. * Port mode registers (PM0 to PM2, PM4, PM6, PM8) * Pull-up resistor option registers (PU0, PUB2) * Port function register 8 (PF8) (1) Port mode registers (PM0 to PM2, PM4, PM6, PM8) PM0 to PM2, PM4, PM6 and PM8 are used to set port input/output in 1-bit units. The port mode registers are independently set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM0, PM1, PM2, PM4, and PM6 to FFH, and PM8 to 3FH. When port pins are used as alternate-function pins, set the port mode register and output latch according to Table 4-3. Caution As P61 has an alternate function as external interrupt input, when the port function output mode is specified and the output level is changed, the interrupt request flag is set. When the output mode is used, therefore, the interrupt mask flag (PMK0) should be preset to 1. Figure 4-11. Format of Port Mode Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W PM1 1 1 1 1 1 1 PM11 PM10 FF21H FFH R/W PM2 1 1 1 1 1 PM22 PM21 PM20 FF22H FFH R/W PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R/W PM8 0 0 PM85 PM84 PM83 PM82 PM81 PM80 FF28H 3FH R/W PMmn Pmn pin input/output mode selection (m = 0 to 2, 4, 6, 8 n = 0 to 5) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Cautions 1. Bits 4 to 7 of PM0, bits 2 to 7 of PM1, bits 3 to 7 of PM2, bits 4 to 7 of PM4, and bits 2 to 7 of PM6 must be set to 1. 2. Bits 6 and 7 of PM8 must be set to 0. 68 User's Manual U16995EJ2V0UD CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions Pin Name Alternate Function PMxx Pxx Input 1 x Output 0 1 Output 0 1 Input 1 x Name SCK10 P20 SO10 P21 I/O Note1 Note1 Note1 P22 SI10 P40 to P43 KR00 to KR03 Input 1 x P60 TO40 Output 0 0 P61 INT Input 1 x Output x x S22 to S17 P80 to P85 Note2 Notes 1. The PD78F9328 only 2. When using P80 to P85 pins as S22 to S17, set port function register 8 (PF8) to 3FH. Caution When port 2 is used as a serial interface pin, the I/O latch or output latch must be set according to its function. For the setting method, see Table 9-2 Settings of Serial Interface 10 Operating Mode. Remark (2) x: don't care PMxx: Pxx: Port mode register Port output latch Pull-up resistor option register 0 (PU0) PU0 sets whether an on-chip pull-up resistor on ports 0, 1, and 4 is used or not in port units. On the port specified to use an on-chip pull-up resistor by PU0, the pull-up resistor can be internally used only for the bits set in the input mode. No on-chip pull-up resistors can be used for the bits set in the output mode regardless of the setting of PU0. This also applies to cases when the pins are used for alternate functions. PU0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PU0 to 00H. Figure 4-12. Format of Pull-up Resistor Option Register 0 Symbol 7 6 5 <4> 3 2 <1> <0> Address After reset R/W PU0 0 0 0 PU04 0 0 PU01 PU00 FFF7H 00H R/W PU0m Pm on-chip pull-up resistor selection (m = 0, 1, 4) 0 On-chip pull-up resistor not used 1 On-chip pull-up resistor used Caution Bits 2, 3, and 5 to 7 must be set to 0. User's Manual U16995EJ2V0UD 69 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option register B2 (PUB2) PUB2 sets whether on-chip pull-up resistors on P20 to P22 are used or not in bit units. A pin for which use of an on-chip pull-up resistor is specified by PUB2 can be connected to the pull-up resistor regardless of whether the pin is in the input or output mode. The same applies when the alternate function of the pin is used. PUB2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PUB2 to 00H. Figure 4-13. Format of Pull-up Resistor Option Register B2 Symbol 7 6 5 4 3 <2> <1> <0> Address After reset R/W PUB2 0 0 0 0 0 PUB22 PUB21 PUB20 FF32H 00H R/W PUB2n P2n on-chip pull-up resistor selection (n = 0 to 2) 0 On-chip pull-up resistor not connected 1 On-chip pull-up resistor connected Cautions 1. Bits 3 to 7 must be set to 0. 2. Clear PUB2n to 0 when using P2n in the output mode or using it as an alternate function output pin. Otherwise, it always outputs a high level. (4) Port function register 8 (PF8) PF8 sets the port function of port 8 in 1-bit units. The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according to the setting of PF8. PF8 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PF8 to 00H. 70 User's Manual U16995EJ2V0UD CHAPTER 4 PORT FUNCTIONS Figure 4-14. Format of Port Function Register 8 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W PF8n P8n port function (n = 0 to 5) 0 Operates as a general-purpose port 1 Operates as an LCD segment signal output Cautions 1. Bits 6 and 7 must be set to 0. 2. When port 8 is used as a general-purpose port, observe the following restriction (because an ESD protection circuit for LCD pins (on the high-level side of port 8) is connected to VLC0). * When any one of pins P80/S22 to P85/S17 is used as a general-purpose input port pin, use the microcontroller at VDD = VLC0 or VDD < VLC0. There is no restriction when all of pins P80/S22 to P85/S17 are used as LCD segment pins or general-purpose output port pins. VLC0 P8n output signal P-ch VLC0 If a voltage higher than VLC0 is input to the P8n/Sm pin, the current flows from the pin to VLC0. As a result, the voltage of VLC0 becomes unstable. N-ch PM8n VSS Segment buffer P8n/Sm Sm output signal VDD P8n input signal VSS PF8n Remark Sm: VSS RD LCD segment output (m = 22 to 17) P8n: Bit n of Port 8 (n = 0 to 5) PF8n: Bit n of Port function register 8 (n = 0 to 5) RD: Port 8 read signal User's Manual U16995EJ2V0UD 71 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operation The operation of a port differs depending on whether the port is set in the input or output mode, as described below. 4.4.1 Writing to I/O port (1) In output mode A value can be written to the output latch of a port by using a transfer instruction. The contents of the output latch can be output from the pins of the port. Data once written to the output latch is retained until new data is written to the output latch. (2) In input mode A value can be written to the output latch by using a transfer instruction. However, the status of the port pin is not changed because the output buffer is OFF. Data once written to the output latch is retained until new data is written to the output latch. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 4.4.2 Reading from I/O port (1) In output mode The status of an output latch can be read by using a transfer instruction. The contents of the output latch are not changed. (2) In input mode The status of a pin can be read by using a transfer instruction. The contents of the output latch are not changed. 4.4.3 Arithmetic operation of I/O port (1) In output mode An arithmetic operation can be performed with the contents of the output latch. The result of the operation is written to the output latch. The contents of the output latch are output from the port pins. Data once written to the output latch is retained until new data is written to the output latch. (2) In input mode The contents of the output latch become undefined. However, the status of the pin is not changed because the output buffer is OFF. Caution A 1-bit memory manipulation instruction is executed to manipulate 1 bit of a port. However, this instruction accesses the port in 8-bit units. When this instruction is executed to manipulate a bit of an input/output port, therefore, the contents of the output latch of the pin that is set in the input mode and not subject to manipulation become undefined. 72 User's Manual U16995EJ2V0UD CHAPTER 5 CLOCK GENERATOR 5.1 Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are used. * Main system clock (ceramic/crystal) oscillator This circuit oscillates at 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction or setting the processor clock control register (PCC). * Subsystem clock oscillator This circuit oscillates at 32.768 kHz. Oscillation can be stopped by the suboscillation mode register (SCKM). 5.2 Clock Generator Configuration The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Configuration Processor clock control register (PCC) Suboscillation mode register (SCKM) Subclock control register (CSS) Oscillators Main system clock oscillator Subsystem clock oscillator User's Manual U16995EJ2V0UD 73 CHAPTER 5 CLOCK GENERATOR Figure 5-1. Block Diagram of Clock Generator Internal bus FRC SCC Suboscillation mode register (SCKM) XT1 XT2 Subsystem clock oscillator fXT Watch timer LCD controller/driver 1/2 X1 X2 Main system fX clock oscillator Clock to peripheral hardware Prescaler fX 22 Standby controller Selector fXT 2 STOP CLS CSS0 MCC PCC1 Processor clock control register (PCC) Subclock control register (CSS) Internal bus 74 User's Manual U16995EJ2V0UD Wait controller CPU clock (fCPU) CHAPTER 5 CLOCK GENERATOR 5.3 Registers Controlling Clock Generator The clock generator is controlled by the following three registers. * Processor clock control register (PCC) * Suboscillation mode register (SCKM) * Subclock control register (CSS) (1) Processor clock control register (PCC) PCC sets CPU clock selection and the division ratio. PCC is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PCC to 02H. Figure 5-2. Format of Processor Clock Control Register Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W PCC MCC 0 0 0 0 0 PCC1 0 FFFBH 02H R/W MCC Control of main system clock oscillator operation 0 Operation enabled 1 Operation disabled CSS0 PCC1 CPU clock (fCPU) selection Note Maximum instruction execution time: 2/fCPU fX = 5.0 MHz or fXT = 32.768 kHz operation 0 0 0.4 s fX 1.6 s 2 0 1 fX/2 1 x fXT/2 122 s Note The CPU clock is selected according to a combination of the PCC1 flag in the processor clock control register (PCC) and the CSS0 flag in the subclock control register (CSS) (Refer to 5.3 (3) Subclock control register (CSS)). Cautions 1. Bits 0 and 2 to 6 must be set to 0. 2. The MCC can be set only when the subsystem clock has been selected as the CPU clock. Setting MCC to 1 while the main system clock is operating is invalid. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. x: Don't care User's Manual U16995EJ2V0UD 75 CHAPTER 5 CLOCK GENERATOR (2) Suboscillation mode register (SCKM) SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock. SCKM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears SCKM to 00H. Figure 5-3. Format of Suboscillation Mode Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W SCKM 0 0 0 0 0 0 FRC SCC FFF0H 00H R/W FRC Feedback resistor selection 0 On-chip feedback resistor used 1 On-chip feedback resistor not used SCC Note Control of subsystem clock oscillator operation 0 Operation enabled 1 Operation disabled Note The feedback resistor is necessary to adjust the bias point of the oscillation waveform to close to the mid point of the supply voltage. Only when the subclock is not used, the power consumption in STOP mode can be further reduced by setting FRC = 1. Caution (3) Bits 2 to 7 must be set to 0. Subclock control register (CSS) CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies the CPU clock operation status. CSS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSS to 00H. Figure 5-4. Format of Subclock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset CSS 0 0 CLS CSS0 0 0 0 0 FFF2H 00H CLS CPU clock operation status 0 Operation based on the output of the divided main system clock 1 Operation based on the subsystem clock CSS0 Selection of the main system or subsystem clock oscillator 0 Divided output from the main system clock oscillator 1 Output from the subsystem clock oscillator Note Bit 5 is read only. Caution 76 Bits 0 to 3, 6, and 7 must be set to 0. User's Manual U16995EJ2V0UD R/W R/W Note CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillators 5.4.1 Main system clock oscillator The main system clock oscillator is oscillated by the crystal or ceramic resonator (5.0 MHz TYP.) connected across the X1 and X2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the X1 pin, and input the inverted signal to the X2 pin. Figure 5-5 shows the external circuit of the main system clock oscillator. Figure 5-5. External Circuit of Main System Clock Oscillator (a) Crystal or ceramic oscillation (b) External clock External clock VSS X1 X1 X2 X2 Crystal or ceramic resonator Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. User's Manual U16995EJ2V0UD 77 CHAPTER 5 CLOCK GENERATOR 5.4.2 Subsystem clock oscillator The subsystem clock oscillator is oscillated by the crystal resonator (32.768 kHz TYP.) connected across the XT1 and XT2 pins. An external clock can also be input to the circuit. In this case, input the clock signal to the XT1 pin, and input the inverted signal to the XT2 pin. Figure 5-6 shows the external circuit of the subsystem clock oscillator. Figure 5-6. External Circuit of Subsystem Clock Oscillator (a) Crystal oscillation (b) External clock External clock VSS XT1 32.768 kHz XT1 XT2 XT2 Crystal resonator Caution When using the main system or subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in Figures 5-5 and 5-6 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. When using the subsystem clock, particular care is required because the subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption. 78 User's Manual U16995EJ2V0UD CHAPTER 5 CLOCK GENERATOR 5.4.3 Example of incorrect resonator connection Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORTn (n = 0 to 2, 4, 6, 8) VSS X1 VSS X2 (c) Wiring near high fluctuating current X1 X2 (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn VSS X1 X2 VSS X1 X2 High current A B C High current Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 in series. User's Manual U16995EJ2V0UD 79 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signal is fetched (f) Parallel and near signal lines of main system clock and subsystem clock VSS VSS X1 X2 X1 XT2 XT1 X2 XT2 is wired parallel to X1. Remark When using the subsystem clock, read X1 and X2 as XT1 and XT2, respectively, and connect a resistor to the XT2 in series. Caution If the X1 wire is in parallel with the XT2 wire, crosstalk noise may occur between the X1 and XT2, resulting in a malfunction. To avoid this, do not lay the X1 and XT2 wires in parallel. 5.4.4 Divider circuit The divider circuit divides the output of the main system clock oscillator (fX) to generate various clocks. 5.4.5 When no subsystem clock is used If a subsystem clock is not necessary, for example, for low-power consumption operation or clock operation, handle the XT1 and XT2 pins as follows: XT1: Connect to VSS XT2: Leave open In this case, however, a small current leaks via the on-chip feedback resistor in the subsystem clock oscillator when the main system clock is stopped. To avoid this, set bit 1 (FRC) of the suboscillation mode register (SCKM) so that the on-chip feedback resistor will not be used. Also in this case, handle the XT1 and XT2 pins as stated above. 80 User's Manual U16995EJ2V0UD CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as the standby mode. * Main system clock * Subsystem clock * CPU clock fX fXT fCPU * Clock to peripheral hardware The operation and function of the clock generator is determined by the processor clock control register (PCC), suboscillation mode register (SCKM), and subclock control register (CSS), as follows. (a) The low-speed mode (1.6 s: at 5.0 MHz operation) of the main system clock is selected when the RESET signal is generated (PCC = 02H). While a low level is input to the RESET pin, oscillation of the main system clock is stopped. (b) Three types of minimum instruction execution time (0.4 s and 1.6 s: main system clock (at 5.0 MHz operation), 122 s: subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, and CSS settings. (c) Two standby modes, STOP and HALT, can be used with the main system clock selected. In a system where no subsystem clock is used, setting bit 1 (FRC) of the SCKM so that the on-chip feedback resistor cannot be used reduces current consumption in STOP mode. In a system where a subsystem clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation. (d) CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation is used (122 s: at 32.768 kHz operation). (e) With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating using bit 7 (MCC) of PCC. The HALT mode can be used, but the STOP mode cannot. (f) The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system clock, but the subsystem clock pulse is only supplied to the watch timer and LCD controller/driver. The watch timer and LCD controller/driver can therefore keep running even during standby. The other hardware stops when the main system clock stops because it runs based on the main system clock (except for external input clock operations). User's Manual U16995EJ2V0UD 81 CHAPTER 5 CLOCK GENERATOR 5.6 Changing Setting of System Clock and CPU Clock 5.6.1 Time required for switching between system clock and CPU clock The CPU clock can be selected by using bit 1 (PCC1) of the processor clock control register (PCC) and bit 4 (CSS0) of the subclock control register (CSS). The maximum time indicated in Table 5-2 is required until the CPU clock actually switches (i.e. switching does not occur immediately after the PCC register is rewritten). Until this time has elapsed, therefore, it is impossible to ascertain whether the clock before or after the switch is operating. Table 5-2. Maximum Time Required for Switching CPU Clock Set Value Before Switching CSS0 0 PCC1 Set Value After Switching CSS0 PCC1 CSS0 PCC1 CSS0 PCC1 0 0 0 1 1 x 0 4 clocks 2fX/fXT clocks (306 clocks) 1 2 clocks fX/2fXT clocks (76 clocks) 1 x 2 clocks 2 clocks Remarks 1. Two clocks are the minimum instruction execution time of the CPU clock before switching. 2. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. 3. x: don't care 82 User's Manual U16995EJ2V0UD CHAPTER 5 CLOCK GENERATOR 5.6.2 Switching between system clock and CPU clock The following figure illustrates how the CPU clock and system clock switch. Figure 5-8. Example of Switching Between System Clock and CPU Clock VDD RESET Input request signal PCC rewrite System clock CPU clock CSS rewrite fX fX Low-speed operation High-speed operation CSS rewrite fXT Subsystem clock operation Oscillation stabilization time wait (6.55 ms at 5.0 MHz operation) Internal reset operation fX High-speed operation Few clocks (For maximum values, refer to Table 5-2.) <1> The CPU is reset when the RESET pin is made low on power application. The effect of resetting is released when the RESET pin is later made high, and the main system clock starts oscillating. At this time, the oscillation stabilization time (215/fX) is automatically secured. After that, the CPU starts instruction execution at the slow speed of the main system clock (1.6 s at 5.0 MHz operation). <2> After the time required for the VDD voltage to rise to the level at which the CPU can operate at high speed has elapsed, bit 1 (PCC1) of the processor clock control register (PCC) is rewritten. <3> After a few clocks have elapsed, the CPU clock is switched to high-speed (0.4 s at 5.0 MHz operation), and the CPU starts the high-speed operation. <4> A drop of the VDD voltage is detected by an interrupt request signal. Bit 4 (CSS0) of the subclock control register (CSS) is rewritten so that the clock is switched to the subsystem clock (at this moment, the subsystem clock must be in the oscillation stabilized status). <5> After a few clocks have elapsed, the CPU clock is switched to the subsystem clock operation (122 s at 32.768 kHz operation). (At this time, bit 7 (MCC) of PCC can be set to 1 to stop the main system clock.) <6> When a recover of the VDD voltage is detected by an interrupt request signal, CSS0 is written so that the CPU clock is switched to the main system clock. (If the main system clock is stopped, set bit 7 (MCC) of PCC to 0 so that the main system clock starts oscillating. After the time required for the oscillation to stabilize has elapsed, rewrite CSS0.) <7> After a few clocks, the CPU clock is switched to high speed (0.4 s at 5.0 MHz operation), and the CPU returns to high-speed operation. Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. User's Manual U16995EJ2V0UD 83 CHAPTER 6 8-BIT TIMERS 30 AND 40 6.1 8-Bit Timers 30 and 40 Functions The 8-bit timer in the PD179327 Subseries has 2 channels (timer 30 and timer 40). The operation modes listed in the following table can be set via mode register settings. Table 6-1. Operation Modes Channel Timer 30 Timer 40 Available Available Mode 8-bit timer counter mode (Discrete mode) 16-bit timer counter mode Available (Cascade connection mode) Carrier generator mode Available PWM output mode Not available (1) 8-bit timer counter mode (discrete mode) The following functions can be used in this mode. * Interval timer with 8-bit resolution * Square-wave output with 8-bit resolution (timer 40 only) (2) 16-bit timer counter mode (cascade connection mode) Operation as a 16-bit timer is enabled during cascade connection mode. The following functions can be used in this mode. * Interval timer with 16-bit resolution * Square-wave output with 16-bit resolution (3) Carrier generator mode The carrier clock generated by timer 40 is output in cycles set by timer 30. (4) PWM output mode (timer 40 only) Pulses are output using any duty factor set by timer 40. 84 User's Manual U16995EJ2V0UD Available CHAPTER 6 8-BIT TIMERS 30 AND 40 6.2 8-Bit Timers 30 and 40 Configuration The 8-bit timers 30 and 40 include the following hardware. Table 6-2. Configuration of 8-Bit Timers 30 and 40 Item Configuration Timer counters 8 bits x 2 (TM30, TM40) Registers Compare registers: 8 bits x 3 (CR30, CR40, CRH40) Timer outputs 1 (TO40) Control registers 8-bit timer mode control register 30 (TMC30) 8-bit timer mode control register 40 (TMC40) Carrier generator output control register 40 (TCA40) Port mode register 6 (PM6) Port 6 (P6) User's Manual U16995EJ2V0UD 85 86 Figure 6-1. Block Diagram of Timer 30 Internal bus 8-bit timer mode control register 30 (TMC30) TCE30 TCL301 TCL300 TMD300 8-bit compare register 30 (CR30) Decoder Match (G) Carrier clock (from Figure 6-2 (C)) (C) Selector fX/26 fX/28 Timer 40 interrupt request signal (from Figure 6-2 (B)) (B) Selector User's Manual U16995EJ2V0UD Bit 7 of TM40 (from Figure 6-2 (A)) 8-bit timer counter 30 (TM30) To Figure 6-2 (G) Timer 30 match signal (in carrier generator mode) OVF Clear Internal reset signal (D) From Figure 6-2 (D) Count operation start signal (for cascade connection) Selector Cascade connection mode INTTM30 (E) From Figure 6-2 (E) Timer 40 match signal (in cascade connection mode) (F) To Figure 6-2 (F) Timer 30 match signal (in cascade connection mode) CHAPTER 6 8-BIT TIMERS 30 AND 40 Selector (A) Figure 6-2. Block Diagram of Timer 40 Internal bus Carrier generator output control register 40 (TCA40) 8-bit timer mode control register 40 (TMC40) 8-bit H width compare register 40 (CRH40) TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 8-bit compare register 40 (CR40) RMC40 NRZB40 NRZ40 Decoder From Figure 6-1 (G) Timer counter match signal from (G) timer 30 (in carrier generator mode) Selector To Figure 6-1 (C) (C) Carrier clock 8-bit timer counter 40 (TM40) 2 fX/22 3 fX/2 OVF Clear Selector Prescaler fX/2 fX/2 TO40/P60 Carrier generator mode PWM mode Reset fX/24 Cascade connection mode To Figure 6-1 (A) Bit 7 of TM40 (A) (in cascade connection mode) Internal reset signal INTTM40 (D) To Figure 6-1 (D) Count operation start signal to timer 30 (in cascade connection mode) (E) To Figure 6-1 (E) TM40 timer counter match signal (in cascade connection mode) (F) To Figure 6-1 (F) TM30 match signal (in cascade connection mode) 87 Note Refer to Figure 6-3 for details. To Figure 6-1 (B) Timer 40 interrupt request signal (B) count clock input signal to TM30 CHAPTER 6 8-BIT TIMERS 30 AND 40 User's Manual U16995EJ2V0UD fX Output controllerNote F/F Match CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-3. Block Diagram of Output Controller (Timer 40) TOE40 RMC40 NRZ40 Selector P60 output latch F/F PM60 TO40/P60 Carrier clock Carrier generator mode (1) 8-bit compare register 30 (CR30) This 8-bit register is used to continually compare the value set to CR30 with the count value in 8-bit timer counter 30 (TM30) and to generate an interrupt request (INTTM30) when a match occurs. CR30 is set with an 8-bit memory manipulation instruction. RESET input makes CR30 undefined. Caution CR30 cannot be used in PWM output mode. (2) 8-bit compare register 40 (CR40) This 8-bit register is used to continually compare the value set to CR40 with the count value in 8-bit timer counter 40 (TM40) and to generate an interrupt request (INTTM40) when a match occurs. When connected to TM30 via a cascade connection and used as a 16-bit timer, the interrupt request (INTTM40) occurs only when matches occur simultaneously between CR30 and TM30 and between CR40 and TM40 (INTTM30 does not occur). In carrier generator mode or PWM output mode, CR40 sets the timer output low-level width. CR40 is set with an 8-bit memory manipulation instruction. RESET input makes CR40 undefined. (3) 8-bit H width compare register 40 (CRH40) In carrier generator mode or PWM output mode, the high-level width of timer output is set by writing a value to CRH40. The set value of CRH40 is always compared with the TM40 count value, and when they match, an interrupt request (INTTM40) is generated. CRH40 is set with an 8-bit memory manipulation instruction. RESET input makes CRH40 undefined. 88 User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 (4) 8-bit timer counters 30 and 40 (TM30 and TM40) These are 8-bit registers that are used to count the count pulse. TM30 and TM40 are read with an 8-bit memory manipulation instruction. RESET input sets TM30 and TM40 to 00H. TM30 and TM40 are cleared to 00H under the following conditions. (a) Discrete mode (i) TM30 * After reset * When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0 * When a match occurs between TM30 and CR30 * When the TM30 count value overflows (ii) TM40 * After reset * When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0 * When a match occurs between TM40 and CR40 * When the TM40 count value overflows (b) Cascade connection mode (TM30 and TM40 are simultaneously cleared to 00H) * After reset * When the TCE40 flag is cleared to 0 * When matches occur simultaneously between TM30 and CR30 and between TM40 and CR40 * When the TM30 and TM40 count values overflow simultaneously (c) Carrier generator mode/PWM output mode (TM40 only) * After reset * When the TCE40 flag is cleared to 0 * When a match occurs between TM40 and CR40 * When a match occurs between TM40 and CRH40 * When the TM40 count value overflows User's Manual U16995EJ2V0UD 89 CHAPTER 6 8-BIT TIMERS 30 AND 40 6.3 Registers Controlling 8-Bit Timers 30 and 40 8-bit timer 30 and 40 are controlled by the following five registers. * 8-bit timer mode control register 30 (TMC30) * 8-bit timer mode control register 40 (TMC40) * Carrier generator output control register 40 (TCA40) * Port mode register 6 (PM6) * Port 6 (P6) 90 User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 (1) 8-bit timer mode control register 30 (TMC30) 8-bit timer mode control register 30 (TMC30) is used to control the timer 30 count clock setting and the operation mode setting. TMC30 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC30 to 00H. Figure 6-4. Format of 8-Bit Timer Mode Control Register 30 Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W TMC30 TCE30 0 0 TCL301 TCL300 0 TMD300 0 FF65H 00H R/W Note 1 TCE30 Control of TM30 count operation 0 Clear TM30 count value and stop operation 1 Start count operation TCL301 TCL300 Selection of timer 30 count clock 6 0 0 fX/2 (78.1 kHz) 0 1 fX/2 (19.5 kHz) 1 0 Timer 40 match signal 1 1 Carrier clock created for timer 40 TMD300 TMD401 TMD400 0 0 0 8-bit timer counter mode (discrete mode) 1 0 1 16-bit timer counter mode (cascade connection mode) 0 1 1 Carrier generator mode 0 1 0 8 Selection of operation mode for timer 30 and timer 40 Note 2 Timer 40: PWM output mode Timer 30: 8-bit timer counter mode Other than above Setting prohibited Notes 1. Since the count operation is controlled by TCE40 (bit 7 of TMC40) in cascade connection mode, any setting for TCE30 is ignored. 2. The operation mode selection is set to both the TMC30 register and TMC40 register. Cautions 1. In cascade connection mode, the timer 40 output signal is forcibly selected for the count clock. 2. Be sure to clear bits 0, 2, 5, and 6 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U16995EJ2V0UD 91 CHAPTER 6 8-BIT TIMERS 30 AND 40 (2) 8-bit timer mode control register 40 (TMC40) 8-bit timer mode control register 40 (TMC40) is used to control the timer 40 count clock setting and the operation mode setting. TMC40 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets TMC40 to 00H. Figure 6-5. Format of 8-Bit Timer Mode Control Register 40 Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W TMC40 TCE40 0 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 FF69H 00H R/W Note 1 TCE40 Control of TM40 count operation 0 Clear TM40 count value and stop operation (the count value is also cleared for TM30 during cascade connection mode) 1 Start count operation (the count operation is also started for TM30 during cascade connection mode) TCL402 TCL401 TCL400 0 0 0 fX (5 MHz) 0 0 1 fX/2 (1.25 MHz) 0 1 0 fX/2 (2.5 MHz) 0 1 1 fX/2 (1.25 MHz) 1 0 0 fX/2 (625 kHz) 1 0 1 fX/2 (313 kHz) Other than above Selection of timer 40 count clock 2 2 3 4 Setting prohibited TMD300 TMD401 TMD400 0 0 0 8-bit timer counter mode (discrete mode) 1 0 1 16-bit timer counter mode (cascade connection mode) 0 1 1 Carrier generator mode 0 1 0 Timer 40: PWM output mode Timer 30: 8-bit timer counter mode Other than above Selection of operation mode for timer 30 and timer 40 Note 2 Setting prohibited TOE40 Control of timer output 0 Output disabled (port mode) 1 Output enabled Notes 1. Since the count operation is controlled by TCE40 in cascade connection mode, any setting for TCE30 (bit 7 of TMC30) is ignored. 2. The operation mode selection is set to both the TMC30 register and TMC40 register. Caution Be sure to clear bit 6 to 0. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 92 User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 (3) Carrier generator output control register 40 (TCA40) This register is used to set the timer output data in carrier generator mode. TCA40 is set with an 8-bit memory manipulation instruction. RESET input sets TCA40 to 00H. Figure 6-6. Format of Carrier Generator Output Control Register 40 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W TCA40 0 0 0 0 0 RMC40 NRZB40 NRZ40 FF6AH 00H R/W RMC40 Control of remote control output 0 When NRZ40 = 1, carrier pulse is output to TO40/P60 pin 1 When NRZ40 = 1, high-level signal is output to TO40/P60 pin NRZB40 This is the bit that stores the next data to be output to NRZ40. Data is transferred to NRZ40 at the rising edge of the timer 30 match signal. Input the necessary value in NRZB40 in advance by program. NRZ40 No return zero data 0 Output low-level signal (carrier clock is stopped) 1 Output carrier pulse or high-level signal Cautions 1. Bits 3 to 7 must be set to 0. 2. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8bit memory manipulation instruction to set TCA40. 3. The NRZ40 flag can be written only when carrier generator output is stopped (TOE40 = 0). The data cannot be overwritten when TOE40 = 1. 4. When the carrier generator is stopped once and then started again, NRZB40 does not hold the previous data. Re-set data to NRZB40. manipulation instruction must not be used. At this time, a 1-bit memory Be sure to use an 8-bit memory manipulation instruction. 5. To enable operation in the carrier generator mode, set a value to the compare registers (CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in advance. Otherwise, the signal of the timer match circuit will become unstable and the NRZ40 flag will be undefined. User's Manual U16995EJ2V0UD 93 CHAPTER 6 8-BIT TIMERS 30 AND 40 (4) Port mode register 6 (PM6) This register is used to set the I/O mode of port 6 in 1-bit units. When using the P60/TO40 pin as a timer output, set the PM60 and P60 output latch to 0. PM6 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM6 to FFH. Figure 6-7. Format of Port Mode Register 6 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM6 1 1 1 1 1 1 PM61 PM60 FF26H FFH R/W PM6n I/O mode of P6n pin (n = 0, 1) 0 Output mode (output buffer is on) 1 Input mode (output buffer is off) Caution 94 Bits 2 to 7 must be set to 1. User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4 8-Bit Timers 30 and 40 Operation 6.4.1 Operation as 8-bit timer counter Timers 30 and 40 can be independently used as 8-bit timer counters. The following modes can be used for the 8-bit timer counters. * Interval timer with 8-bit resolution * Square-wave output with 8-bit resolution (timer 40 only) (1) Operation as interval timer with 8-bit resolution The interval timer with 8-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register n0 (CRn0). To operate 8-bit timer n0 as an interval timer, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter n0 (TMn0) (TCEn0 = 0). <2> Disable timer output of TOn0 (TOEn0 = 0). <3> Set a count value in CRn0. <4> Set the operation mode of timer n0 to 8-bit timer counter mode (see Figures 6-4 and 6-5). <5> Set the count clock for timer n0 (see Tables 6-3 and 6-4). <6> Enable the operation of TMn0 (TCEn0 = 1). When the count value of 8-bit timer counter n0 (TMn0) matches the value set in CRn0, TMn0 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTMn0) is generated. Tables 6-3 and 6-4 show the interval time, and Figures 6-8 to 6-12 show the timing of the interval timer operation. Caution Be sure to stop the timer operation before overwriting the count clock with different data. Remark n = 3, 4 User's Manual U16995EJ2V0UD 95 CHAPTER 6 8-BIT TIMERS 30 AND 40 Table 6-3. Interval Time of Timer 30 (at fX = 5.0 MHz Operation) TCL301 TCL300 Minimum Interval Time Maximum Interval Time Resolution 0 0 2 /fX (12.8 s) 2 /fX (3.28 ms) 0 1 2 /fX (51.2 s) 2 /fX (13.1 ms) 2 /fX (51.2 s) 1 0 Input cycle of timer 40 match Input cycle of timer 40 match Input cycle of timer 40 match signal signal x 2 signal Carrier clock cycle created Carrier clock cycle created Carrier clock cycle created with timer 40 with timer 40 x 2 with timer 40 1 Remark 6 8 1 14 2 /fX (12.8 s) 16 4 8 8 8 fX: Main system clock oscillation frequency Table 6-4. Interval Time of Timer 40 (at fX = 5.0 MHz Operation) TCL402 TCL401 TCL400 0 0 Minimum Interval Time Maximum Interval Time Resolution 0 1/fX (0.2 s) 2 /fX (51 s) 1/fX (0.2 s) 8 0 0 1 2 /fX (0.8 s) 2 /fX (205 s) 2 /fX (0.8 s) 0 1 0 2/fX (0.4 s) 2 /fX (102 s) 2/fX (0.4 s) 0 1 1 2 /fX (0.8 s) 2 /fX (205 s) 2 /fX (0.8 s) 1 0 0 2 /fX (1.6 s) 2 /fX (410 s) 2 /fX (1.6 s) 1 0 1 2 /fX (3.2 s) 2 /fX (819 s) 2 /fX (3.2 s) Remark 2 10 2 9 2 10 3 2 11 4 3 12 4 fX: Main system clock oscillation frequency Figure 6-8. Timing of Interval Timer Operation with 8-Bit Resolution (Basic Operation) t Count clock TMn0 00H 01H N 00H 01H 00H N Clear 01H N Clear 00H 01H 00H Clear N CRn0 TCEn0 Count start Count stop INTTMn0 Interrupt acknowledgment Interrupt acknowledgment Interval time Interval time TOn0 Remarks 1. Interval time = (N + 1) x t: N = 00H to FFH 2. n = 3, 4 96 User's Manual U16995EJ2V0UD Interrupt acknowledgment CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-9. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to 00H) Count clock 00H TMn0 00H CRn0 TCEn0 Count start INTTMn0 TOn0 Remark n = 3, 4 Figure 6-10. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Is Set to FFH) Count clock TMn0 00H 01H FFH 00H Clear 01H FFH 00H Clear 01H FFH 00H FFH 00H Clear FFH CRn0 TCEn0 Count start INTTMn0 TOn0 Remark n = 3, 4 User's Manual U16995EJ2V0UD 97 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-11. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N < M)) Count clock TMn0 00H N 01H 00H N M 00H Clear Clear N CRn0 M N 00H 01H Clear M TCEn0 Count start INTTMn0 Interrupt acknowledgment Interrupt acknowledgment TOn0 CRn0 overwritten Remark n = 3, 4 Figure 6-12. Timing of Interval Timer Operation with 8-Bit Resolution (When CRn0 Changes from N to M (N > M)) Count clock TMn0 N-1 00H N M N FFH Clear TCEn0 Clear N CRn0 M 00H Clear M H TMn0 overflows because M < N INTTMn0 TOn0 CRn0 overwritten Remark 98 n = 3, 4 User's Manual U16995EJ2V0UD 00H M 00H CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-13. Timing of Interval Timer Operation with 8-Bit Resolution (When Timer 40 Match Signal Is Selected for Timer 30 Count Clock) Timer 40 count clock TM40 00H N 01H M 00H Clear M 00H Clear M Clear N CR40 00H 00H Clear M TCE40 Count start INTTM40 Input clock to timer 30 (timer 40 match signal) 00H TM30 Y-1 01H Y 00H Y 00H Y CR30 TCE30 INTTM30 Count start TO40 TO30 Remark n = 3, 4 User's Manual U16995EJ2V0UD 99 CHAPTER 6 8-BIT TIMERS 30 AND 40 (2) Operation as square-wave output with 8-bit resolution (timer 40 only) Square waves of any frequency can be output at an interval specified by the value preset in 8-bit compare register 40 (CR40). To operate timer 40 for square-wave output, settings must be made in the following sequence. <1> Set P60 to output mode (PM60 = 0). <2> Set the output latch of P60 to 0. <3> Disable operation of timer counter 40 (TM40) (TCE40 = 0). <4> Set a count clock for timer 40 and enable output of TO40 (TOE40 = 1). <5> Set a count value in CR40. <6> Enable the operation of TM40 (TCE40 = 1). When the count value of TM40 matches the value set in CR40, the TO40 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TM40 is cleared to 00H and continues counting. At the same time, an interrupt request signal (INTTM40) is generated. The square-wave output is cleared to 0 by setting TCE40 to 0. Table 6-5 shows the square-wave output range, and Figure 6-14 shows the timing of square-wave output. Caution Be sure to stop the timer operation before overwriting the count clock with different data. Table 6-5. Square-Wave Output Range of Timer 40 (at fX = 5.0 MHz Operation) TCL402 TCL401 TCL400 0 0 0 1/fX (0.2 s) 2 /fX (51 s) 1/fX (0.2 s) Maximum Pulse Width 8 Resolution 0 0 1 2 /fX (0.8 s) 2 /fX (205 s) 2 /fX (0.8 s) 0 1 0 2/fX (0.4 s) 2 /fX (102 s) 2/fX (0.4 s) 2 10 9 2 0 1 1 2 /fX (0.8 s) 2 /fX (205 s) 2 /fX (0.8 s) 1 0 0 2 /fX (1.6 s) 2 /fX (410 s) 2 /fX (1.6 s) 1 0 1 2 /fX (3.2 s) 2 /fX (819 s) 2 /fX (3.2 s) Remark 100 Minimum Pulse Width 2 10 3 11 4 12 fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD 2 3 4 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-14. Timing of Square-Wave Output with 8-Bit Resolution t Count clock TM40 00H 01H N 00H 01H 00H N Clear 01H N Clear 00H 01H Clear N CR40 TCE40 Count start INTTM40 Interrupt acknowledgment Interrupt acknowledgment Interrupt acknowldgement TO40Note Square-wave output cycle Note The initial value of TO40 is low level when output is enabled (TOE40 = 1). Remark Square-wave output cycle = 2 (N + 1) x t: N = 00H to FFH User's Manual U16995EJ2V0UD 101 CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4.2 Operation as 16-bit timer counter Timers 30 and 40 can be used as 16-bit timer counters via a cascade connection. In this case, 8-bit timer counter 30 (TM30) is the higher 8 bits and 8-bit timer counter 40 (TM40) is the lower 8 bits. 8-bit timer 40 controls reset and clear. The following modes can be used for the 16-bit timer counter. * Interval timer with 16-bit resolution * Square-wave output with 16-bit resolution (1) Operation as interval timer with 16-bit resolution The interval timer with 16-bit resolution repeatedly generates an interrupt at a time interval specified by the count value preset in 8-bit compare register 30 (CR30) and 8-bit compare register 40 (CR40). To operate as an interval timer with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of 8-bit timer counter 30 (TM30) and 8-bit timer counter 40 (TM40) (TCE30 = 0, TCE40 = 0). <2> Disable timer output of TO40 (TOE40 = 0). <3> Set the count clock for timer 40 (see Table 6-4). <4> Set the operation mode of timer 30 and timer 40 to 16-bit timer counter mode (see Figures 6-4 and 65). <5> Set a count value in CR30 and CR40. <6> Enable the operation of TM30 and TM40 (TCE40 = 1Note). Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of TCE30 is invalid). When the count values of TM30 and TM40 match the values set in CR30 and CR40 respectively, both TM30 and TM40 are simultaneously cleared to 00H and counting continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated). Table 6-6 shows interval time, and Figure 6-15 shows the timing of the interval timer operation. Caution Be sure to stop the timer operation before overwriting the count clock with different data. Table 6-6. Interval Time with 16-Bit Resolution (at fX = 5.0 MHz Operation) TCL402 TCL401 0 0 TCL400 Minimum Interval Time 0 1/fX (0.2 s) Maximum Interval Time 1/fX (0.2 s) 18 2 /fX (0.8 s) 17 2/fX (0.4 s) 18 2 /fX (0.8 s) 19 2 /fX (1.6 s) 20 2 /fX (3.2 s) 2 /fX (13.1 ms) 0 0 1 2 /fX (0.8 s) 2 /fX (52.4 ms) 0 1 0 2/fX (0.4 s) 2 /fX (26.2 ms) 2 0 1 1 2 /fX (0.8 s) 2 /fX (52.4 ms) 1 0 0 2 /fX (1.6 s) 2 /fX (105 ms) 1 0 1 2 /fX (3.2 s) 2 /fX (210 ms) Remark 102 2 3 4 Resolution 16 fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD 2 2 3 4 Figure 6-15. Timing of Interval Timer Operation with 16-Bit Resolution t TM40 count clock TM40 count value 00H N 7FH 80H FFH 00H 7FH 80H N FFH 00H Not cleared because TM30 does not match CR40 N N N N 00H 7FH 80H FFH 00H N 00H Cleared because TM30 and TM40 match simultaneously N N N N N N User's Manual U16995EJ2V0UD Count start TM30 count clock TM30 00H CR30 X X-1 01H X X X-1 00H X 00H X INTTM40 TO40 Interrupt not generated because TM30 does not match Interrupt acknowledgment Interval time Remark Interval time = (256X + N + 1) x t: X = 00H to FFH, N = 00H to FFH Interrupt acknowledgment CHAPTER 6 8-BIT TIMERS 30 AND 40 TCE40 103 CHAPTER 6 8-BIT TIMERS 30 AND 40 (2) Operation as square-wave output with 16-bit resolution Square waves of any frequency can be output at an interval specified by the count value preset in CR30 and CR40. To operate as a square-wave output with 16-bit resolution, settings must be made in the following sequence. <1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0). <2> Disable output of TO40 (TOE40 = 0). <3> Set a count clock for timer 40. <4> Set P60 to output mode (PM60 = 0) and P60 output latch to 0 and enable TO40 output (TOE40 = 1). <5> Set count values in CR30 and CR40. <6> Enable the operation of TM40 (TCE40 = 1Note). Note Start and clear of the timer in the 16-bit timer counter mode are controlled by TCE40 (the value of TCE30 is invalid). When the count values of TM30 and TM40 simultaneously match the values set in CR30 and CR40 respectively, the TO40 pin output will be inverted. Through application of this mechanism, square waves of any frequency can be output. As soon as a match occurs, TM30 and TM40 are cleared to 00H and counting continues. At the same time, an interrupt request signal (INTTM40) is generated (INTTM30 is not generated). The square-wave output is cleared to 0 by setting TCE40 to 0. Table 6-7 shows the square wave-output range, and Figure 6-16 shows timing of square-wave output. Caution Be sure to stop the timer operation before overwriting the count clock with different data. Table 6-7. Square-Wave Output Range with 16-Bit Resolution (at fX = 5.0 MHz Operation) TCL402 TCL401 0 Minimum Pulse Width 0 1/fX (0.2 s) Maximum Pulse Width 1/fX (0.2 s) 18 2 /fX (0.8 s) 17 2/fX (0.4 s) 18 2 /fX (0.8 s) 19 2 /fX (1.6 s) 20 2 /fX (3.2 s) 2 /fX (13.1 ms) 0 1 2 /fX (0.8 s) 2 /fX (52.4 ms) 0 1 0 2/fX (0.4 s) 2 /fX (26.2 ms) 2 0 1 1 2 /fX (0.8 s) 2 /fX (52.4 ms) 1 0 0 2 /fX (1.6 s) 2 /fX (105 ms) 1 0 1 2 /fX (3.2 s) 2 /fX (210 ms) 2 3 4 Resolution 16 0 Remark 104 0 TCL400 fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD 2 2 3 4 Figure 6-16. Timing of Square-Wave Output with 16-Bit Resolution t TM40 count clock TM40 count clock 00H N 7FH 80H FFH 00H 7FH 80H N FFH 00H Not cleared because TM30 does not match CR40 N N N N 00H 7FH 80H FFH 00H N 00H Cleared because TM30 and TM40 match simultaneously N N N N N N User's Manual U16995EJ2V0UD Count start TM30 count clock TM30 CR30 X-1 01H 00H X X X X-1 00H X 00H X INTTM40 Note Interrupt not generated because TM30 does not match Interrupt acknowledgment TO40 Square-wave output cycle/2 Note The initial value of TO40 is low level when output is enabled (TOE40 = 1). Remark Square-wave output cycle = 2 (256X + N + 1) x t: X = 00H to FFH, N = 00H to FFH Interrupt acknowledgment CHAPTER 6 8-BIT TIMERS 30 AND 40 TCE40 105 CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4.3 Operation as carrier generator An arbitrary carrier clock generated by TM40 can be output in the cycle set in TM30. To operate timers 30 and 40 as carrier generators, settings must be made in the following sequence. <1> Disable operation of TM30 and TM40 (TCE30 = 0, TCE40 = 0). <2> Disable timer output of TO40 (TOE40 = 0). <3> Set count values in CR30, CR40, and CRH40. <4> Set the operation mode of timer 30 and timer 40 to carrier generator mode (see Figures 6-4 and 6-5). <5> Set the count clock for timer 30 and timer 40. <6> Set remote control output to carrier pulse (RMC40 (bit 2 of carrier generator output control register 40 (TCA40)) = 0). Input the required value to NRZB40 (bit 1 of TCA40) by program. Input a value to NRZ40 (bit 0 of TCA40) before it is reloaded from NRZB40. <7> Set P60 to output mode (PM60 = 0) and the P60 output latch to 0 and enable TO40 output by setting TOE40 to 1. <8> Enable the operation of TM30 and TM40 (TCE30 = 1, TCE40 = 1). <9> Save the NRZB40 value to a general-purpose register. <10> When INTTM30 rises, the NRZB40 value is transferred to NRZ40. After that, rewrite TCA40 using an 8-bit memory manipulation instruction. Input the value to be transferred next to NRZ40 to NRZB40, and input the value saved in step <9> to NRZ40. <11> Generate the desired carrier signal by repeating steps <9> and <10>. The operation of the carrier generator is as follows. <1> When the count the value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is generated and the output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40. <2> After that, when the count the value of TM40 matches the value set in CRH40, an interrupt request signal (INTTM40) is generated and the output of timer 40 is inverted again, which makes the compare register switch from CRH40 to CR40. <3> The carrier clock is generated by repeating <1> and <2> above. <4> When the count value of TM30 matches the value set in CR30, an interrupt request signal (INTTM30) is generated. The rising edge of INTTM30 is the data reload signal of NRZB40 and is transferred to NRZ40. <5> When NRZ40 is 1, a carrier clock is output from TO40 pin. Cautions 1. TCA40 cannot be set with a 1-bit memory manipulation instruction. Be sure to use an 8-bit memory manipulation instruction. 2. The NRZ40 flag can be rewritten only when the carrier generator output is stopped (TOE40 = 0). The data of the flag is not changed even if a write instruction is executed while TOE40 = 1. 3. When the carrier generator is stopped once and then started again, NRZB40 does not hold the previous data. Re-set data to NRZB40. At this time, a 1-bit memory manipulation instruction must not be used. Be sure to use an 8-bit memory manipulation instruction. 4. To enable operation in the carrier generator mode, set a value to the compare registers (CR30, CR40, and CRH40), and input the necessary value to the NRZB40 and NRZ40 flags in advance. Otherwise, the signal of the timer match circuit will become unstable and the NRZ40 flag will be undefined. 106 User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 Figures 6-17 to 6-19 show the operation timing of the carrier generator. Figure 6-17. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M > N)) TM40 count clock TM40 count value 00H 01H N 00H M N Clear CR40 N CRH40 M 00H N 00H Clear N M Clear 00H Clear TCE40 Count start INTTM40 Carrier clock TM30 count clock TM30 00H 01H X 00H 01H X 00H 01H X 00H X 00H 01H X CR30 TCE30 INTTM30 NRZB40 NRZ40 0 0 1 0 1 1 0 0 1 0 Carrier clock TO40 User's Manual U16995EJ2V0UD 107 CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-18. Timing of Carrier Generator Operation (When CR40 = N, CRH40 = M (M < N)) TM40 count clock TM40 count value N M 00H 00H M N CRH40 M M N Clear Clear CR40 00H M 00H Clear 00H Clear TCE40 Count start INTTM40 Carrier clock TM30 count clock TM30 01H 00H CR30 X 00H 01H X 00H 00H X 01H X 00H 01H X TCE30 INTTM30 NRZB40 NRZ40 0 0 1 0 1 1 0 0 1 0 Carrier clock TO40 Remark 108 This figure shows an example of when the NRZ40 value is changed while the carrier clock is high level. User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-19. Timing of Carrier Generator Operation (When CR40 = CRH40 = N) TM40 count clock TM40 count value N 00H 00H N Clear CR40 N CRH40 N N 00H Clear 00H N Clear 00H N Clear 00H N Clear TCE40 Count start INTTM40 Carrier clock TM30 count clock TM30 00H 01H X 00H 01H X 00H 01H X 00H X 00H 01H X CR30 TCE30 INTTM30 NRZB40 NRZ40 0 0 1 0 1 1 0 0 1 0 Carrier clock TO40 User's Manual U16995EJ2V0UD 109 CHAPTER 6 8-BIT TIMERS 30 AND 40 6.4.4 Operation as PWM output (timer 40 only) In the PWM output mode, a pulse of any duty ratio can be output by setting a low-level width using CR40 and a high-level width using CRH40. To operate timer 40 in PWM output mode, settings must be made in the following sequence. <1> Disable operation of TM40 (TCE40 = 0). <2> Disable timer output of TO40 (TOE40 = 0). <3> Set count values in CR40 and CRH40. <4> Set the operation mode of timer 40 to carrier generator mode (see Figure 6-5). <5> Set the count clock for timer 40. <6> Set P60 to output mode (PM60 = 0) and the P60 output latch to 0 and enable timer output of TO40 (TOE40 = 1). <7> Enable the operation of TM40 (TCE40 = 1). The operation in the PWM output mode is as follows. <1> When the count value of TM40 matches the value set in CR40, an interrupt request signal (INTTM40) is generated and the output of timer 40 is inverted, which makes the compare register switch from CR40 to CRH40. <2> A match between TM40 and CR40 clears the TM40 value to 00H and then counting starts again. <3> After that, when the count value of TM40 matches the value set in CRH40, an interrupt request signal (INTTM40) is generated and the output of timer 40 is inverted again, which makes the compare register switch from CRH40 to CR40. <4> A match between TM40 and CRH40 clears the TM40 value to 00H and then counting starts again. A pulse of any duty ratio is output by repeating <1> to <4> above. Figures 6-20 and 6-21 show the operation timing in the PWM output mode. 110 User's Manual U16995EJ2V0UD CHAPTER 6 8-BIT TIMERS 30 AND 40 Figure 6-20. PWM Output Mode Timing (Basic Operation) TM40 count clock TM40 count value 00H 01H N 00H M 01H Clear CR40 N CRH40 M 00H 00H N 01H Clear M 01H Clear 00H Clear TCE40 Count start INTTM40 TO40Note Note The initial value of TO40 is low level when output is enabled (TOE40 = 1). Figure 6-21. PWM Output Mode Timing (When CR40 and CRH40 Are Overwritten) TM40 count clock TM40 count value 00H 01H N 00H Y Clear CR40 N CRH40 M N 00H X Clear 00H M Clear 00H X Clear X Y M TCE40 Count start INTTM40 TO40Note Note The initial value of TO40 is low level when output is enabled (TOE40 = 1). User's Manual U16995EJ2V0UD 111 CHAPTER 6 8-BIT TIMERS 30 AND 40 6.5 Notes on Using 8-Bit Timers 30 and 40 (1) Error on starting timer An error of up to 1.5 clocks is included in the time between when the timer is started and a match signal is generated. This is because the counter may be incremented by detecting a rising edge at the timing at which the timer starts while the count clock is high level (see Figure 6-22). Figure 6-22. Case in Which Error of 1.5 Clocks (Max.) Occurs Delay A Selected clock Count pulse 8-bit timer counter n0 (TMn0) Clear signal TCEn0 Delay B Selected clock TCEn0 Clear signal Count pulse TMn0 count value 00H 01H 02H 03H Delay A Delay B If delay A > delay B when the timer starts while the selected clock is high level, an error of 1.5 clocks (max.) occurs. Remark 112 n = 3, 4 User's Manual U16995EJ2V0UD CHAPTER 7 WATCH TIMER 7.1 Watch Timer Functions The watch timer has the following functions. * Watch timer * Interval timer The watch and interval timers can be used at the same time. Figure 7-1 shows a block diagram of the watch timer. Figure 7-1. Block Diagram of Watch Timer fXT 5-bit counter 9-bit prescaler fW fW 24 fW 25 fW 26 fW 27 fW 28 fW 29 INTWT Clear Selector fX/2 Selector Clear 7 INTWTI WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus User's Manual U16995EJ2V0UD 113 CHAPTER 7 WATCH TIMER (1) Watch timer The 4.19 MHz main system clock or 32.768 kHz subsystem clock is used to generate an interrupt request (INTWT) at 0.5-second intervals. Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5second interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used instead. (2) Interval timer The interval timer is used to generate an interrupt request (INTWT) at specified intervals. Table 7-1. Interval Time of Interval Timer Interval At fX = 5.0 MHz Operation At fX = 4.19 MHz Operation At fXT = 32.768 kHz Operation 2 x 1/fW 409.6 s 488 s 488 s 2 x 1/fW 819.2 s 977 s 977 s 2 x 1/fW 1.64 ms 1.95 ms 1.95 ms 2 x 1/fW 3.28 ms 3.91 ms 3.91 ms 2 x 1/fW 6.55 ms 7.81 ms 7.81 ms 2 x 1/fW 13.1 ms 15.6 ms 15.6 ms 4 5 6 7 8 9 Remarks 1. fW: 2. fX: Watch timer clock frequency (fX/27 or fXT) Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 7.2 Watch Timer Configuration The watch timer includes the following hardware. Table 7-2. Configuration of Watch Timer Item Configuration Counter 5 bits x 1 Prescaler 9 bits x 1 Control register Watch timer mode control register (WTM) 114 User's Manual U16995EJ2V0UD CHAPTER 7 WATCH TIMER 7.3 Register Controlling Watch Timer The watch timer mode control register (WTM) is used to control the watch timer. * Watch timer mode control register (WTM) WTM selects a count clock for the watch timer and specifies whether to enable clocking of the timer. It also specifies the prescaler interval and how the 5-bit counter is controlled. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WTM to 00H. Figure 7-2. Format of Watch Timer Mode Control Register Symbol 7 6 5 4 3 2 <1> <0> Address After reset R/W WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0 FF4AH 00H R/W WTM7 Watch timer count clock (fW) selection 7 0 fX/2 (39.1 kHz) 1 fXT WTM6 (32.768 kHz) WTM5 WTM4 Prescaler interval selection 4 0 0 0 2 /fW 0 0 1 2 /fW 0 1 0 2 /fW 0 1 1 2 /fW 1 0 0 2 /fW 1 0 1 2 /fW Other than above 5 6 7 8 9 Setting prohibited WTM1 Control of 5-bit counter operation 0 Cleared after stop 1 Started WTM0 Watch timer operation 0 Operation stopped (both prescaler and timer cleared) 1 Operation enabled Caution Bits 2 and 3 must be set to 0. Remarks 1. fW: 2. fX: Watch timer clock frequency (fX/27 or fXT) Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. User's Manual U16995EJ2V0UD 115 CHAPTER 7 WATCH TIMER 7.4 Watch Timer Operation 7.4.1 Operation as watch timer The main system clock (4.19 MHz) or subsystem clock (32.768 kHz) is used as a watch timer which generates 0.5-second intervals. The watch timer is used to generate an interrupt request at specified intervals. By setting bits 0 and 1 (WTM0 and WTM1) of the watch timer mode control register (WTM) to 1, the watch timer starts counting. By setting them to 0, the 5-bit counter is cleared and the watch timer stops counting. When the interval timer also operates at the same time, only the watch timer can be started from 0 seconds by setting WTM1 to 0. However, an error of up to 29 x 1/fW seconds may occur for the first overflow of the watch timer (INTWT) after a 0-second start because the 9-bit prescaler is not cleared in this case. 7.4.2 Operation as interval timer The interval timer is used to repeatedly generate an interrupt request at the interval specified by a preset count value. The interval time can be selected by bits 4 to 6 (WTM4 to WTM6) of the watch timer mode control register (WTM). Table 7-3. Interval Time of Interval Timer Interval At fX = 5.0 MHz Operation At fX = 4.19 MHz Operation At fXT = 32.768 kHz Operation 2 x 1/fW 409.6 s 488 s 488 s 2 x 1/fW 819.2 s 977 s 977 s 2 x 1/fW 1.64 ms 1.95 ms 1.95 ms 2 x 1/fW 3.28 ms 3.91 ms 3.91 ms 2 x 1/fW 6.55 ms 7.81 ms 7.81 ms 2 x 1/fW 13.1 ms 15.6 ms 15.6 ms 4 5 6 7 8 9 Remarks 1. fW: 2. fX: Watch timer clock frequency (fX/27 or fXT) Main system clock oscillation frequency 3. fXT: Subsystem clock oscillation frequency 116 User's Manual U16995EJ2V0UD CHAPTER 7 WATCH TIMER Figure 7-3. Watch Timer/Interval Timer Operation Timing 5-bit counter 0H Overflow Start Overflow Count clock fW/29 Watch timer interrupt INTWT Watch timer interrupt time (0.5 s) Watch timer interrupt time (0.5 s) Interval timer interrupt INTWTI Interval timer (T) T Caution When operation of the watch timer and 5-bit counter has been enabled by setting the watch timer mode control register (WTM) (setting WTM0 (bit 0 of WTM) to 1), the time until the first interrupt request after this setting will not be exactly the same as the watch timer interrupt time (0.5 s). This is because the 5-bit counter starts counting one cycle after the output of the 9-bit prescaler. The INTWT signal will be generated at the set time from its second generation. Remarks 1. fW: Watch timer clock frequency 2. The parenthesized values apply to operation at fW = 32.768 kHz. User's Manual U16995EJ2V0UD 117 CHAPTER 8 WATCHDOG TIMER 8.1 Watchdog Timer Functions The watchdog timer has the following functions. * Watchdog timer * Interval timer Caution Select the watchdog timer mode or interval timer mode by using the watchdog timer mode register (WDTM). (1) Watchdog timer The watchdog timer is used to detect inadvertent program loop. When the inadvertent program loop is detected, a non-maskable interrupt or the RESET signal can be generated. Table 8-1. Inadvertent Program Loop Detection Time of Watchdog Timer Inadvertent Program Loop Detection Time 2 x 1/fX 410 s 2 x 1/fX 1.64 ms 2 x 1/fX 6.55 ms 2 x 1/fX 26.2 ms 11 13 15 17 Remark (2) At fX = 5.0 MHz Operation fX: Main system clock oscillation frequency Interval timer The interval timer generates an interrupt at any preset intervals. Table 8-2. Interval Time of Watchdog Timer Interval Time 410 s 2 x 1/fX 1.64 ms 2 x 1/fX 6.55 ms 2 x 1/fX 26.2 ms 13 15 17 Remark 118 At fX = 5.0 MHz Operation 2 x 1/fX 11 fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD CHAPTER 8 WATCHDOG TIMER 8.2 Watchdog Timer Configuration The watchdog timer includes the following hardware. Table 8-3. Configuration of Watchdog Timer Item Configuration Control registers Watchdog timer clock selection register (TCL2) Watchdog timer mode register (WDTM) Figure 8-1. Block Diagram of Watchdog Timer Internal bus fX 24 WDTMK Prescaler fX 26 fX 28 fX 210 Selector WDTIF 7-bit counter Controller INTWDT Maskable interrupt request RESET INTWDT Non-maskable interrupt request Clear 2 TCL22 TCL21 RUN WDTM4 WDTM3 Watchdog timer clock selection register (TCL2) Watchdog timer mode register (WDTM) Internal bus User's Manual U16995EJ2V0UD 119 CHAPTER 8 WATCHDOG TIMER 8.3 Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. * Watchdog timer clock selection register (TCL2) * Watchdog timer mode register (WDTM) (1) Watchdog timer clock selection register (TCL2) TCL2 sets the watchdog timer count clock. This register is set with an 8-bit memory manipulation instruction. RESET input clears TCL2 to 00H. Figure 8-2. Format of Watchdog Timer Clock Selection Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W TCL2 0 0 0 0 0 TCL22 TCL21 0 FF42H 00H R/W TCL22 TCL21 Watchdog timer count clock selection Inadvertent program loop detection or interval time 4 2 /fX (410 s) 6 2 /fX (1.64 ms) 8 2 /fX (6.55 ms) 10 2 /fX (26.2 ms) 0 0 fX/2 (313 kHz) 0 1 fX/2 (78.1 kHz) 1 0 fX/2 (19.5 kHz) 1 1 fX/2 (4.88 kHz) Caution 11 13 15 17 Bits 0, 3 to 7 must be set to 0. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 120 User's Manual U16995EJ2V0UD CHAPTER 8 WATCHDOG TIMER (2) Watchdog timer mode register (WDTM) WDTM sets an operation mode of the watchdog timer, and enables/disables counting of the watchdog timer. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears WDTM to 00H. Figure 8-3. Format of Watchdog Timer Mode Register Symbol <7> 6 5 4 3 2 1 0 Address After reset R/W WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W Note 1 RUN Selection of operation of watchdog timer 0 Stops counting 1 Clears counter and starts counting Note 2 WDTM4 WDTM3 Selection of operation mode of watchdog timer 0 0 Operation stopped 0 1 Interval timer mode (when overflow occurs, a maskable interrupt occur) 1 0 Watchdog timer mode 1 (when overflow occurs, a non-maskable interrupt occurs) 1 1 Watchdog timer mode 2 (when overflow occurs, reset operation starts) Note 3 Notes 1. Once RUN has been set (1), it cannot be cleared (0) by software. Therefore, when counting is started, it cannot be stopped by any means other than RESET input. 2. Once WDTM3 and WDTM4 have been set (1), they cannot be cleared (0) by software. 3. The watchdog timer starts operations as an interval timer when RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is up to 0.8% shorter than the time set by the watchdog timer clock selection register (TCL2). 2. In watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that the WDTIF (bit 0 of interrupt request flag register 0 (IF0)) is set to 0. While WDTIF is 1, a non-maskable interrupt is generated upon write completion if watchdog timer mode 1 or 2 is selected. User's Manual U16995EJ2V0UD 121 CHAPTER 8 WATCHDOG TIMER 8.4 Watchdog Timer Operation 8.4.1 Operation as watchdog timer The watchdog timer detects an inadvertent program loop when bit 4 (WDTM4) of the watchdog timer mode register (WDTM) is set to 1. The count clock (inadvertent program loop detection time interval) of the watchdog timer can be selected by bits 1 and 2 (TCL21 and TCL22) of the watchdog timer clock selection register (TCL2). By setting bit 7 (RUN) of WDTM to 1, the watchdog timer is started. Set RUN to 1 within the set inadvertent program loop detection time interval after the watchdog timer has been started. By setting RUN to 1, the watchdog timer can be cleared and start counting. If RUN is not set to 1, and the inadvertent program loop detection time is exceeded, the system is reset or a non-maskable interrupt is generated by the value of bit 3 (WDTM3) of WDTM. The watchdog timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the watchdog timer, and then execute the STOP instruction. Cautions 1. The actual inadvertent program loop detection time may be up to 0.8% shorter than the set time. 2. When the subsystem clock is selected as the CPU clock, the watchdog timer stops counting. In this case, therefore, the watchdog timer stops operation even though the main system clock is oscillating. Table 8-4. Inadvertent Program Loop Detection Time of Watchdog Timer TCL22 TCL21 0 0 2 x 1/fX 410 s 1 2 x 1/fX 1.64 ms 0 2 x 1/fX 6.55 ms 1 2 x 1/fX 26.2 ms 0 1 1 Remark 122 Inadvertent Program Loop Detection Time 11 13 15 17 At fX = 5.0 MHz Operation fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD CHAPTER 8 WATCHDOG TIMER 8.4.2 Operation as interval timer When bit 4 (WDTM4) and bit 3 (WDTM3) of the watchdog timer mode register (WDTM) are set to 0 and 1, respectively, the watchdog timer also operates as an interval timer that repeatedly generates an interrupt at time intervals specified by a preset count value. Select a count clock (or interval time) by setting bits 1 and 2 (TCL21 and TCL22) of the watchdog timer clock selection register (TCL2). The watchdog timer starts operation as an interval timer when the RUN bit (bit 7 of WDTM) is set to 1. In the interval timer mode, the interrupt mask flag (WDTMK) is valid, and a maskable interrupt (INTWDT) can be generated. The priority of INTWDT is set as the highest of all the maskable interrupts. The interval timer continues operation in the HALT mode, but stops in the STOP mode. Therefore, set RUN to 1 before entering the STOP mode to clear the interval timer, and then execute the STOP instruction. Cautions 1. Once bit 4 (WDTM4) of WDTM is set to 1 (when the watchdog timer mode is selected), the interval timer mode is not set, unless the RESET signal is input. 2. The interval time immediately after the setting by WDTM may be up to 0.8% shorter than the set time. Table 8-5. Interval Time of Watchdog Timer TCL22 Interval Time At fX = 5.0 MHz Operation 0 2 x 1/fX 410 s 0 1 2 x 1/fX 1.64 ms 1 0 2 x 1/fX 6.55 ms 1 2 x 1/fX 26.2 ms 0 1 Remark TCL21 11 13 15 17 fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD 123 CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) Caution Serial interface 10 is not available for mask ROM versions. Do not access the registers used for Serial interface 10 when using a mask ROM version. 9.1 Serial Interface 10 Functions Serial interface 10 has the following two modes. * Operation stop mode * 3-wire serial I/O mode (1) Operation stop mode This mode is used when serial transfer is not carried out. It enables a reduction in power consumption. (2) 3-wire serial I/O mode (MSB/LSB-first switchable) In this mode, 8-bit data transfer is carried out-first with three lines, one for the serial clock (SCK10) and two for serial data (SI10 and SO10). The 3-wire serial I/O mode supports simultaneous transmit and receive operations, reducing data transfer processing time. It is possible to switch the start bit of 8-bit data to be transmitted between the MSB and the LSB, thus allowing connection to devices with either start bit. The 3-wire serial I/O mode is effective for connecting display controllers and peripheral I/O such as the 75XL Series, 78K Series, and 17K Series, which have internal conventional clocked serial interfaces. 124 User's Manual U16995EJ2V0UD CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) 9.2 Serial Interface 10 Configuration Serial interface 10 includes the following hardware. Table 9-1. Configuration of Serial Interface 10 Item Register Control register Configuration Transmit/receive shift register 10 (SIO10) Serial operation mode register 10 (CSIM10) Port mode register 2 (PM2) Port 2 (P2) (1) Transmit/receive shift register 10 (SIO10) SIO10 is an 8-bit register used for parallel-to-serial conversion and to perform serial data transmission/reception in synchronization with serial clocks. This register is set with an 8-bit memory manipulation instruction. RESET input makes SIO10 undefined. User's Manual U16995EJ2V0UD 125 126 Figure 9-1. Block Diagram of Serial Interface 10 Internal bus Serial operation mode register 10 (CSIM10) CSIE10 TPS101 TPS100 DIR10 CSCK10 SI10/P22 PM21 output latch (P21) Serial clock counter Interrupt request generator output latch (P20) PM20 Clock controller F/F Selector SCK10/P20 Selector User's Manual U16995EJ2V0UD SO10/P21 fX/22 fX/23 TPS101 TPS100 INTCSI10 CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) Transmit/receive shift register 10 (SIO10) CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) 9.3 Registers Controlling Serial Interface 10 Serial interface 10 is controlled by the following three registers. * Serial operation mode register 10 (CSIM10) * Port mode register 2 (PM2) * Port 2 (P2) (1) Serial operation mode register 10 (CSIM10) CSIM10 is used to control serial interface 10 and set the serial clock and start bit. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM10 to 00H. Figure 9-2. Format of Serial Operation Mode Register 10 Symbol <7> CSIM10 CSIE10 6 5 4 3 2 1 0 Address After reset R/W 0 TPS101 TPS100 0 DIR10 CSCK10 0 FF72H 00H R/W CSIE10 Operation control in 3-wire serial I/O mode 0 Operation stopped 1 Operation enabled TPS101 TPS100 Count clock selection when internal clock is selected 2 0 0 fX/2 (1.25 MHz) 0 1 fX/2 (625 kHz) Other than above 3 Setting prohibited DIR10 Start bit specification 0 MSB 1 LSB CSCK10 SIO10 clock selection 0 Input clock to SCK10 pin from external 1 Internal clock selected by TPS100, TPS101 Cautions 1. Bits 0, 3, and 6 must be set to 0. 2. Switch operation mode after stopping the serial transmit/receive operation. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. User's Manual U16995EJ2V0UD 127 CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) (2) Port mode register 2 (PM2) This register is used to set the I/O mode of port 2 in 1-bit units. PM2 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets PM2 to FFH. Figure 9-3. Format of Port Mode Register 2 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM2 1 1 1 1 1 PM22 PM21 PM20 FF22H FFH R/W PM2n I/O mode of P2n pin (n = 0 to 2) 0 Output mode (output buffer is on) 1 Input mode (output buffer is off) Caution Bits 3 to 7 must be set to 1. Table 9-2. Settings of Serial Interface 10 Operating Mode (1) Operation stop mode CSIM10 PM22 CSIE10 DIR10 CSCK10 0 x x x Note 1 P22 x Note 1 PM21 x Note 1 P21 x Note 1 PM20 x Note 1 P20 x Note 1 Other than above (2) 1 Shift P22/SI10 P21/SO10 P20/SCK10 Clock Pin Function Pin Function Pin Function P22 P21 P20 -- -- Setting prohibited 3-wire serial I/O mode CSIM10 CSIE10 Start Bit DIR10 PM22 P22 PM21 P21 PM20 P20 CSCK10 0 0 Note 2 1 x Note 2 0 1 1 x Start Shift P22/SI10 P21/SO10 P20/SCK10 Bit Clock Pin Function Pin Function Pin Function SO10 SCK10 input MSB External SI10 Note 2 clock 1 0 1 Internal (CMOS output) SCK10 output clock 1 1 0 1 x LSB External SCK10 input clock 1 0 1 Internal clock Other than above Setting prohibited Notes 1. Can be used as port function. 2. If used only for transmission, can be used as P22 (CMOS I/O). Remark 128 x: don't care User's Manual U16995EJ2V0UD SCK10 output CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) 9.4 Serial Interface 10 Operation Serial interface 10 provides the following two types of modes. * Operation stop mode * 3-wire serial I/O mode 9.4.1 Operation stop mode In the operation stop mode, serial transfer is not executed, therefore enabling a reduction in the power consumption. The P20/SCK10, P21/SO10, and P22/SI10 pins can be used as normal I/O ports. (1) Register setting Operation stop mode is set by serial operation mode register 10 (CSIM10). (a) Serial operation mode register 10 (CSIM10) CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM10 to 00H. Symbol <7> CSIM10 CSIE10 6 5 4 3 2 1 0 Address After reset R/W 0 TPS101 TPS100 0 DIR10 CSCK10 0 FF72H 00H R/W CSIE10 Operation control in 3-wire serial I/O mode 0 Operation stopped 1 Operation enabled Caution Bits 0, 3, and 6 must be set to 0. User's Manual U16995EJ2V0UD 129 CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) 9.4.2 3-wire serial I/O mode The 3-wire serial I/O mode is useful for connection of peripheral I/O and display controllers, etc., which incorporate a conventional clocked serial interface, such as the 75XL Series, 78K Series, 17K Series. Communication is performed using three lines: a serial clock line (SCK10), serial output line (SO10), and serial input line (SI10). (1) Register setting 3-wire serial I/O mode settings are performed using serial operation mode register 10 (CSIM10). (a) Serial operation mode register 10 (CSIM10) CSIM10 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears CSIM10 to 00H. Symbol <7> CSIM10 CSIE10 6 5 4 3 2 1 0 Address After reset R/W 0 TPS101 TPS100 0 DIR10 CSCK10 0 FF72H 00H R/W CSIE10 Operation control in 3-wire serial I/O mode 0 Operation stopped 1 Operation enabled TPS101 TPS100 Count clock selection when internal clock is selected 2 0 0 fX/2 (1.25 MHz) 0 1 fX/2 (625 kHz) Other than above 3 Setting prohibited DIR10 Start bit specification 0 MSB 1 LSB CSCK10 SIO10 clock selection 0 Input clock to SCK10 pin from external 1 Internal clock selected by TPS100, TPS101 Cautions 1. Bits 0, 3, and 6 must be set to 0. 2. Switch operation mode after stopping the serial transmit/receive operation. Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. 130 User's Manual U16995EJ2V0UD CHAPTER 9 SERIAL INTERFACE 10 (PD78F9328 ONLY) (2) Communication operation In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit by bit in synchronization with the serial clock. Transmit shift register 10 (SIO10) shift operations are performed in synchronization with the fall of the serial clock (SCK10). Transmit data is then held in the SO10 latch and output from the SO10 pin. Also, receive data input to the SI10 pin is latched in the input bits of SIO10 on the rise of SCK10. At the end of an 8-bit transfer, the operation of SIO10 stops automatically, and the interrupt request signal (INTCSI10) is generated. Figure 9-4. 3-Wire Serial I/O Mode Timing SCK10 1 2 3 4 5 6 7 8 SI10 DI7 DI6 DI5 DI4 DI3 DI2 DI1 SO10 DO7 DO6 DO5 DO4 DO3 DO2 DO1 DI0 DO0 INTCSI10 Transfer starts at the falling edge of SCK10 Cautions End of transfer 1. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0), the data cannot be transmitted or received. 2. When data is written to SIO10 in the serial operation disabled status (CSIE10 = 0) and then serial operation is enabled (CSIE10 = 1), the data cannot be transmitted or received. 3. Once data has been written to SIO10 with the external serial clock selected (CSCK10 = 0), overwriting the data does not update the contents of SIO10. 4. When CSIM10 is operated during data transmission/reception, data cannot be transmitted or received normally. 5. When SIO10 is operated during data transmission/reception, the data cannot be transmitted or received normally. (3) Transfer start Serial transfer is started by setting transfer data to the transmit shift register 10 (SIO10) when the following two conditions are satisfied. * Bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) = 1 * Internal serial clock is stopped or SCK10 is a high level after 8-bit serial transfer. Termination of 8-bit transfer stops the serial transfer automatically and generates the interrupt request signal (INTCSI10). User's Manual U16995EJ2V0UD 131 CHAPTER 10 LCD CONTROLLER/DRIVER 10.1 LCD Controller/Driver Functions The functions of the LCD controller/driver of the PD179327 Subseries are as follows. (1) Automatic output of segment and common signals based on automatic display data memory read (2) Two different display modes: * Static * 1/4 duty (1/3 bias) (3) Four different frame frequencies, selectable in each display mode (4) Up to 24 segment signal outputs (S0 to S23) and four common signal outputs (COM0 to COM3) (5) Operation with a subsystem clock Table 10-1 lists the maximum number of pixels that can be displayed in each display mode. Table 10-1. Maximum Number of Pixels Bias Mode Number of Time Slices Common Signals Maximum Number of Pixels Used - Static 24 (24 segments x 1 common) Note 1 COM0 (COM1 to COM3) 1/3 4 96 (24 segments x 4 commons) Note 2 COM0 to COM3 Notes 1. 3-digit LCD panel, each digit having an 8-segment configuration. 2. 12-digit LCD panel, each digit having a 2-segment configuration. 10.2 LCD Controller/Driver Configuration The LCD controller/driver consists of the following hardware. Table 10-2. Configuration of LCD Controller/Driver Item Display outputs Control registers Configuration Segment signals: 24 Common signals: 4 LCD display mode register 0 (LCDM0) LCD clock control register 0 (LCDC0) Port function register 8 (PF8) 132 User's Manual U16995EJ2V0UD Figure 10-1. Block Diagram of LCD Controller/Driver Internal bus LCD clock control register 0 (LCDC0) LCD display mode register 0 (LCDM0) LCDON0 VAON0 LCDM02 LCDC03 LCDC02 LCDC01 LCDC00 FA00H 76543210 FA11H 76543210 FA16H 76543210 FA17H 76543210 3210 Selector 3210 Selector 3210 Selector 3210 Selector Port function register 8 (PF8) 2 2 Display data memory PF85 PF84 PF83 PF82 PF81 PF80 Selector fLCD fLCD 26 Prescaler fLCD 27 fLCD 28 fLCD 29 LCD clock LCDCL selector Timing controller LCDON0 LCDON0 Gate voltage amplifier LCD drive voltage controller Level shifter Level shifter Segment driver Segment driver VSS 1 VLC0 3 Level shifter Segment driver LCDON0 Level shifter Segment driver Common driver PF85 RLCD RLCD LCDON0 PF80 RLCD 2 VLC0 3 VLC0 COM0 COM1 COM2 COM3 S0 S17/P85 S22/P80 S23 CHAPTER 10 LCD CONTROLLER/DRIVER User's Manual U16995EJ2V0UD fX/25 fX/26 fX/27 fXT 133 CHAPTER 10 LCD CONTROLLER/DRIVER 10.3 Registers Controlling LCD Controller/Driver * LCD display mode register 0 (LCDM0) * LCD clock control register 0 (LCDC0) * Port function register 8 (PF8) (1) LCD display mode register 0 (LCDM0) LCDM0 specifies whether to enable display operation. It also specifies the operation mode and display mode. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDM0 to 00H. 134 User's Manual U16995EJ2V0UD CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-2. Format of LCD Display Mode Register 0 Symbol <7> LCDM0 LCDON0 <6> 5 4 3 2 1 0 Address After reset R/W VAON0 0 0 0 LCDM02 0 0 FFB0H 00H R/W LCDON0 LCD display enable/disable 0 Display off (all segment outputs are unselected for signal output) 1 Display on VAON0 LCD controller/driver operation mode 0 No gate voltage amplification (for VLC0 = 2.7 to 5.5 V display) 1 Gate voltage amplification enabled (for VLC0 = 1.8 to 5.5 V display) LCDM02 Display mode selection 0 Four-time slot, 1/3 bias mode 1 Static mode Note 1 Note 2 Notes 1. When LCD display is not performed, the power consumption can be lowered by clearing VAON0 to 0. 2. To set the STOP mode while the main system clock is selected as the LCD source clock, select the static mode (LCDM02 = 1). Cautions 1. Bits 0,1, 3 to 5 must be set to 0. 2. When operating VAON0, follow the procedure described below. A. To stop gate voltage amplification after switching display status from on to off: 1) Set to display off status by setting LCDON0 = 0. 2) Stop gate voltage amplification by setting VAON0= 0. B. To stop gate voltage amplification during display on status: Setting prohibited. Be sure to stop gate voltage amplification after setting display off. C. To set display on from gate voltage amplification stop status: 1) Start gate voltage amplification by setting VAON0 = 1, then wait for about 500 ms. 2) Set display on by setting LCDON0 = 1. D. To start voltage amplification during display on status: Setting prohibited. Be sure to setting display off, and follow the procedure in C. 3. When the main system clock is selected as the LCD source clock, If the STOP mode is selected, an abnormal display may occur. Before selecting the STOP mode, disable display and select the static mode (LCDON0 = 0 and LCDM02 = 1). If the subsystem clock is selected as the LCD source clock, a normal operation is performed in the STOP mode. 4. The LCD may momentarily light for 1 cycle immediately after the display has been turned on/off because the waveform has not become stabilized. User's Manual U16995EJ2V0UD 135 CHAPTER 10 LCD CONTROLLER/DRIVER (2) LCD clock control register 0 (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined by the LCD clock and the number of time divisions. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears LCDC0 to 00H. Figure 10-3. Format of LCD Clock Control Register 0 Symbol 7 6 5 4 3 2 1 <0> Address After reset R/W LCDC0 0 0 0 0 LCDC03 LCDC02 LCDC01 LCDC00 FFB2H 00H R/W LCDC03 LCDC02 0 0 fXT (32.768 kHz) 0 1 fX/2 (156.3 kHz) 1 0 fX/2 (78.1 kHz) 1 1 fX/2 (39.1 kHz) LCDC01 LCDC00 LCD source clock (fLCD) selection Note 5 6 7 LCD clock (LCDCL) selection 0 0 fLCD/2 6 0 1 fLCD/2 7 1 0 fLCD/2 8 1 1 fLCD/2 9 Note Specify an LCD source clock (fLCD) frequency of at least 32 kHz. Remarks 1. fX: Main system clock oscillation frequency 2. fXT: Subsystem clock oscillation frequency 3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz. Cautions 1. Bits 4 to 7 must be set to 0. 2. Be sure to turn off the display (LCDON = 0) and stop the voltage amplifier (VAON0 = 0) before changing the LCDC0 settings. For example, Table 10-3 lists the frame frequencies used when fXT (32.768 kHz) is supplied to the LCD source clock (fLCD). Table 10-3. Frame Frequencies (Hz) LCD Clock (LCDCL) 9 fXT/2 8 fXT/2 7 fXT/2 6 (64 Hz) (128 Hz) (256 Hz) (512 Hz) Static 64 128 256 512 4 16 32 64 128 Time Division 136 fXT/2 User's Manual U16995EJ2V0UD CHAPTER 10 LCD CONTROLLER/DRIVER (3) Port function register 8 (PF8) PF8 specifies whether S17/P85 to S22/P80 are used as LCD segment signal outputs or general-purpose ports in 1-bit units. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears PF8 to 00H. Figure 10-4. Format of Port Function Register 8 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W PF8n Port function of P8n (n = 0 to 5) 0 Operates as a general-purpose port 1 Operates as an LCD segment signal output Cautions 1. Bits 6 and 7 must be set to 0. 2. When port 8 is used as a general-purpose port, observe the following restriction (because an ESD protection circuit for LCD pins (on the high-level side of port 8) is connected to VLC0). * When any one of pins P80/S22 to P85/S17 is used as a general-purpose input port pin, use the microcontroller at VDD = VLC0 or VDD < VLC0. There is no restriction when all of pins P80/S22 to P85/S17 are used as LCD segment pins or general-purpose output port pins. VLC0 P8n output signal P-ch VLC0 If a voltage higher than VLC0 is input to the P8n/Sm pin, the current flows from the pin to VLC0. As a result, the voltage of VLC0 becomes unstable. N-ch PM8n VSS Segment buffer P8n/Sm Sm output signal VDD P8n input signal VSS PF8n VSS RD User's Manual U16995EJ2V0UD 137 CHAPTER 10 LCD CONTROLLER/DRIVER Remark Sm: LCD segment output (m = 22 to 17) P8n: Bit n of Port 8 (n = 0 to 5) PF8n: Bit n of Port function register 8 (n = 0 to 5) RD: Port 8 read signal 10.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <To enable gate voltage amplification> <1> Set the frame frequency using LCD clock control register 0 (LCDC0). <2> Set VAON0 (bit 6 of LCDM0) (VAON0 = 1). Wait for 500 ms or more after setting VAON0. <3> Start output corresponding to each display data memory by setting LCDON0 (bit 7 of LCDM0) (LCDON0 =1). <When gate voltage is not amplified> <1> Set the frame frequency using LCD clock control register 0 (LCDC0). <2> Start output corresponding to each display data memory by setting LCDON0 (bit 7 of LCDM0) (LCDON0 =1). 138 User's Manual U16995EJ2V0UD CHAPTER 10 LCD CONTROLLER/DRIVER 10.5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA00H to FA17H. Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller/driver. Figure 10-5 shows the relationship between the contents of the LCD display data memory and the segment/common outputs. That part of the display data memory which is not used for display can be used as ordinary RAM. Figure 10-5. Relationship Between LCD Display Data Memory Contents and Segment/Common Outputs Address b7 b6 b5 b4 b3 b2 b1 b0 FA17H S23 FA16H S22 FA15H S21 S20 FA02H S2 FA01H S1 FA00H S0 COM3 COM2 COM1 COM0 Caution No memory has been installed as the higher 4 bits of the LCD display data memory. Be sure to set 0 to them. User's Manual U16995EJ2V0UD 139 CHAPTER 10 LCD CONTROLLER/DRIVER 10.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). It turns off when the potential difference becomes lower than VLCD. Applying DC voltage to the common and segment signals for an LCD panel would deteriorate it. To avoid this problem, this LCD panel is driven with AC voltage. (1) Common signals Each common signal is selected sequentially according to a specified number of time slots at the timing listed in Table 10-4. Table 10-4. COM Signals COM Signal COM0 COM1 COM2 COM3 Number of Time Slots Static display mode Four-time slot mode (2) Segment signals The segment signals correspond to 24 bytes of LCD display data memory (FA00H to FA17H). Bits 0, 1, 2, and 3 of each byte are read in synchronization with COM0, COM1, COM2, and COM3, respectively. If the contents of each bit are 1, it is converted to the select voltage, and if 0, it is converted to the deselect voltage. The conversion results are output to the segment pins (S0 to S23). Check, with the information given above, what combination of the front-surface electrodes (corresponding to the segment signals) and the rear-surface electrodes (corresponding to the common signals) forms display patterns in the LCD display data memory, and write the bit data that corresponds to the desired display pattern on a one-to-one basis. LCD display data memory bits 1 to 3 are not used for LCD display in the static display. So these bits can be used for purposes other than display. LCD display data memory bits 4 to 7 are fixed to 0. (3) Output waveforms of common and segment signals The voltages listed in Table 10-5 are output as common and segment signals. When both common and segment signals are at the select voltage, a display on-voltage of VLCD is obtained. The other combinations of the signals correspond to the display off-voltage. 140 User's Manual U16995EJ2V0UD CHAPTER 10 LCD CONTROLLER/DRIVER Table 10-5. LCD Drive Voltage (a) Static display mode Segment Signal Select Signal Level Deselect Signal Level VSS0/VLC0 VLC0/VSS0 Common Signal VLC0/VSS0 -VLCD/+VLCD 0 V/0 V (b) 1/3 bias method Segment Signal Select Signal Level Deselect Signal Level VSS0/VLC0 VLC1/VLC2 Common Signal Select signal level VLC0/VSS0 -VLCD/+VLCD Deselect signal level VLC2/VLC1 - 1 3 VLCD/+ - 1 3 VLCD - 1 3 1 3 VLCD/+ VLCD/+ 1 3 1 3 VLCD VLCD Figure 10-6 shows the common signal waveforms, and Figure 10-7 shows the voltages and phases of the common and segment signals. Figure 10-6. Common Signal Waveforms (a) Static display mode VLC0 COM0 VLCD (Static display) VSS TF = T T: One LCD clock period TF: Frame frequency (b) 1/3 bias method VLC0 COMn VLC1 VLC2 VSS (Four-time slot mode) VLCD TF = 4 x T T: One LCD clock period TF: Frame frequency User's Manual U16995EJ2V0UD 141 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-7. Voltages and Phases of Common and Segment Signals (a) Static display mode Select Deselect VLC0 VLCD Common signal VSS VLC0 VLCD Segment signal VSS T T T: One LCD clock period (b) 1/3 bias method Select Deselect VLC0 VLC1 VLC2 Common signal VLCD VSS VLC0 VLC1 VLC2 Segment signal VSS T T T: One LCD clock period 142 User's Manual U16995EJ2V0UD VLCD CHAPTER 10 LCD CONTROLLER/DRIVER 10.7 Display Modes 10.7.1 Static display example Figure 10-9 shows how the three-digit LCD panel having the display pattern shown in Figure 10-8 is connected to the segment signals (S0 to S23) and the common signal (COM0) of the PD179327 Subseries chip. This example displays data "12.3" in the LCD panel. The contents of the display data memory (addresses FA00H to FA17H) correspond to this display. The following description focuses on numeral "2." ( ) displayed in the second digit. To display "2." in the LCD panel, it is necessary to apply the select or deselect voltage to the S8 to S15 pins according to Table 10-6 at the timing of the common signal COM0; see Figure 10-8 for the relationship between the segment signals and LCD segments. Table 10-6. Select and Deselect Voltages (COM0) Segment S8 S9 S10 S11 S12 S13 S14 S15 Select Deselect Select Select Deselect Select Select Select Common COM0 According to Table 10-6, it is determined that the bit-0 pattern of the display data memory locations (FA08H to FA0FH) must be 10110111. Figure 10-10 shows the LCD drive waveforms of S11 and S12, and COM0. When the select voltage is applied to S11 at the timing of COM0, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. COM1 to COM3 are supplied with the same waveform as for COM0. So, COM0 to COM3 may be connected together to increase the driving capacity. Figure 10-8. Static LCD Display Pattern and Electrode Connections S8n+3 S8n+4 S8n+2 S8n+5 S8n+6 COM0 S8n+1 S8n S8n+7 Remark n = 0 to 2 User's Manual U16995EJ2V0UD 143 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-9. Example of Connecting Static LCD Panel Timing Strobe COM 3 COM 2 COM 1 3 4 5 6 Data Memory Address 7 8 9 A B C D E F FA10H 1 2 3 4 5 6 7 Bit 1 Bit 0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 S 11 S 12 S 13 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 User's Manual U16995EJ2V0UD LCD panel 2 0 0 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Bit 3 Bit 2 COM 0 FA00H 144 Can be connected together CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-10. Static LCD Drive Waveform Examples TF VLC0 COM0 VSS VLC0 S11 VSS VLC0 S12 VSS +VLCD COM0 to S11 0 -VLCD +VLCD COM0 to S12 0 -VLCD User's Manual U16995EJ2V0UD 145 CHAPTER 10 LCD CONTROLLER/DRIVER 10.7.2 Four-time slot display example Figure 10-12 shows how the 12-digit LCD panel having the display pattern shown in Figure 10-11 is connected to the segment signals (S0 to S23) and the common signals (COM0 to COM3) of the PD179327 Subseries chip. This example displays data "123456.789012" in the LCD panel. The contents of the display data memory (addresses FA00H to FA17H) correspond to this display. The following description focuses on numeral "6." ( ) displayed in the seventh digit. To display "6." in the LCD panel, it is necessary to apply the select or deselect voltage to the S12 and S13 pins according to Table 10-7 at the timing of the common signals COM0 to COM3; see Figure 10-11 for the relationship between the segment signals and LCD segments. Table 10-7. Select and Deselect Voltages (COM0 to COM3) Segment S12 S13 COM0 Select Select COM1 Deselect Select COM2 Select Select COM3 Select Select Common According to Table 10-7, it is determined that the display data memory location (FA0CH) that corresponds to S12 must contain 1101. Figure 10-13 shows examples of LCD drive waveforms between the S12 signal and each common signal. When the select voltage is applied to S12 at the timing of COM0, an alternate rectangle waveform, +VLCD/-VLCD, is generated to turn on the corresponding LCD segment. Figure 10-11. Four-Time Slot LCD Display Pattern and Electrode Connections S2n ;; ;;;;;; ; COM0 COM2 S2n+1 Remark 146 COM1 n = 0 to 11 User's Manual U16995EJ2V0UD COM3 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-12. Example of Connecting Four-Time Slot LCD Panel Timing strobe COM 3 COM 2 COM 1 2 3 4 5 6 7 Data memory address 8 9 A B C D E F FA10H 1 2 3 4 5 6 7 Bit 1 Bit 2 Bit 0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S 10 S 11 S 12 S 13 LCD panel 1 0 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 FA00H 0 0 1 0 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 Bit 3 COM 0 S 14 S 15 S 16 S 17 S 18 S 19 S 20 S 21 S 22 S 23 User's Manual U16995EJ2V0UD 147 CHAPTER 10 LCD CONTROLLER/DRIVER Figure 10-13. Four-Time Slot LCD Drive Waveform Examples TF VLC0 VLC1 COM0 VLC2 VSS VLC0 VLC1 COM1 VLC2 VSS VLC0 VLC1 COM2 VLC2 VSS VLC0 VLC1 COM3 VLC2 VSS VLC0 VLC1 S12 VLC2 VSS +VLCD +1/3VLCD COM0-S12 0 -1/3VLCD -VLCD +VLCD +1/3VLCD 0 COM1-S12 -1/3VLCD -VLCD Remark The waveforms of COM2-S12 and COM3-S12 are not shown in the above chart. 148 User's Manual U16995EJ2V0UD CHAPTER 11 POWER-ON-CLEAR CIRCUITS PD179327 Subseries provides a power-on-clear (POC) circuit. In the flash memory version (PD78F9328), the POC circuit is always operating. However, it can only be used when selected by a mask option in mask ROM versions (PD179322, 179322A, 179324, 179324A, 179326, and 179327) (see CHAPTER 16 MASK OPTIONS). 11.1 Power-on-Clear Circuit Functions The power-on-clear circuits include the following function. (1) Power-on-clear (POC) circuit * Compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal reset signal if VDD < VPOC. * This circuit can operate even in STOP mode. 11.2 Power-on-Clear Circuit Configuration Figure 11-1 shows the block diagram of the power-on-clear circuits. Figure 11-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal - Detection voltage source (VPOC) POCOF1 Power-on-clear register 1 (POCF1) Internal bus User's Manual U16995EJ2V0UD 149 CHAPTER 11 POWER-ON-CLEAR CIRCUITS 11.3 Register Controlling Power-on-Clear Circuit The power-on-clear circuits are controlled by the following register. * Power-on-clear register 1 (POCF1) (1) Power-on-clear register 1 (POCF1) POCF1 controls POC circuit operation. This register is set with a 1-bit or 8-bit memory manipulation instruction. Figure 11-2. Format of Power-on-Clear Register 1 Symbol POCF1 7 6 0 5 0 0 4 3 0 0 POCOF1 <2> POCOF1 1 0 0 0 Address FFDDH After reset Note 00H R/W R/W POC output detection flag 0 Non-generation of reset signal by POC or in cleared state due to a write operation to POCF1 1 Generation of reset signal by POC Note This value is 04H only after a power-on-clear reset. 11.4 Power-on-Clear Circuit Operation The POC circuit compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal reset signal if VDD < VPOC. When a reset is generated via the power-on-clear circuit in bit 2 (POCOF1) on the power-on-clear register (POCF1) is set (1). This bit is then cleared (0) by an instruction written to POCF1. After a power-on-clear reset (i.e. after program execution has started from address 0000H), a power failure can be detected by detecting POCOF1. Caution Use of the POC circuit can be selected by a mask option in the case of the mask ROM version. With the PD78F9328, use of the POC circuit cannot be selected (always operating). Figure 11-3. Timing of Internal Reset Signal Generation of POC Circuit Power supply voltage (VDD) Detection voltage (VPOC) 1.8 V Time Internal reset signal 150 User's Manual U16995EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Non-maskable interrupt This interrupt is acknowledged unconditionally. It does not undergo interrupt priority control and is given top priority over all other interrupt requests. A standby release signal is generated. One interrupt source from the watchdog timer is incorporated as a non-maskable interrupt. (2) Maskable interrupt This interrupt undergoes mask control. If two or more interrupts with the same priority are simultaneously generated, each interrupt has a predetermined priority as shown in Table 12-1. A standby release signal is generated. 2 external and 5 (6 for the PD78F9328) internal interrupt sources are incorporated as maskable interrupts. 12.2 Interrupt Sources and Configuration A total of 8 (9 for the PD78F9328) non-maskable and maskable interrupts are incorporated as interrupt sources (see Table 12-1). User's Manual U16995EJ2V0UD 151 CHAPTER 12 INTERRUPT FUNCTIONS Table 12-1. Interrupt Source List Note 1 Interrupt Type Priority Interrupt Source Name Non-maskable - INTWDT Trigger Internal/ Vector Table Basic External Address Configuration Note 2 Type Watchdog timer overflow (with Internal 0004H (A) watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (with (B) interval timer mode selected) 1 2 INTP0 INTCSI10 Pin input edge detection End of serial interface 10 3-wire SIO transfer reception 3 INTWT 4 INTTM30 External Internal 0006H 0008H Note 3 (C) (B) Note 3 Watch timer interrupt 000AH Generation of 8-bit timer 30 000CH matching signal 5 INTTM40 Generation of 8-bit timer 40 000EH matching signal 6 INTKR00 7 INTWTI Key return signal detection External 0010H (C) Watch timer interval timer Internal 0012H (B) interrupt Notes 1. Priority is the priority order when more than one maskable interrupt request is generated at the same time. 0 is the highest priority and 7 is the lowest. 2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 12-1. 3. The PD78F9328 only Remark There are two interrupt sources for the watchdog timer (INTWDT): non-maskable and maskable interrupts (internal). Either one (but not both) should be selected for actual use. 152 User's Manual U16995EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal (C) External maskable interrupt Internal bus INTM0, KRM00 Interrupt request Edge detector MK IE IF Vector table address generator Standby release signal INTP0: External interrupt mode register 0 KRM00: Key return mode register 00 IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag User's Manual U16995EJ2V0UD 153 CHAPTER 12 INTERRUPT FUNCTIONS 12.3 Registers Controlling Interrupt Function The following five types of registers are used to control the interrupt functions. * Interrupt request flag register 0 (IF0) * Interrupt mask flag register 0 (MK0) * External interrupt mode register 0 (INTM0) * Program status word (PSW) * Key return mode register 00 (KRM00) Table 12-2 gives a listing of interrupt request flag and interrupt mask flag names corresponding to interrupt requests. Table 12-2. Flags Corresponding to Interrupt Request Signal Name Interrupt Request Signal Name Interrupt Request Flag INTWDT WDTIF INTP0 PIF0 INTCSI10 Note Interrupt Mask Flag WDTMK PMK0 CSIIF10 Note CSIMK10 INTWT WTIF WTMK INTTM30 TMIF30 TMMK30 INTTM40 TMIF40 TMMK40 INTKR00 KRIF00 KRMK00 INTWTI WTIIF WTIMK Note Note The PD78F9328 only (1) Interrupt request flag register 0 (IF0) An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal is input, or when an instruction is executed. IF0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears IF0 to 00H. Figure 12-2. Format of Interrupt Request Flag Register 0 Symbol IF0 <7> WTIIF <6> KRIF00 <5> TMIF40 <4> TMIF30 <3> WTIF xxIFx <2> CSIIF10 Note <1> <0> Address After reset R/W PIF0 WDTIF FFE0H 00H R/W Interrupt request flag 0 No interrupt request signal generated 1 An interrupt request signal is generated and an interrupt request made Note Provided in the PD78F9328 only. Be sure to clear 0 for a mask ROM version. Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer mode 1 or 2. 154 User's Manual U16995EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Cautions 2. Because P61 functions alternately as an external interrupt input, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) to 1 before using the port in output mode. 3. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is started. (2) Interrupt mask flag register 0 (MK0) Interrupt mask flags are used to enable and disable the corresponding maskable interrupts. MK0 is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MK0 to FFH. Figure 12-3. Format of Interrupt Mask Flag Register 0 Symbol MK0 <7> WTIMK <6> <5> <4> KRMK00 TMMK40 TMMK30 xxMK <3> <2> WTMK CSIMK10 Note <1> <0> Address After reset R/W PMK0 WDTMK FFE4H FFH R/W Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note Provided in the PD78F9328 only. Be sure to set 1 for a mask ROM version. Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read the WDTMK flag results in an undefined value being detected. 2. Because P61 functions alternately as an external interrupt input, when the output level changes after the output mode of the port function is specified, the interrupt request flag will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) to 1 before using the port in output mode. User's Manual U16995EJ2V0UD 155 CHAPTER 12 INTERRUPT FUNCTIONS (3) External interrupt mode register 0 (INTM0) INTM0 is used to specify the valid edge for INTP0. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears INTM0 to 00H. Figure 12-4. Format of External Interrupt Mode Register 0 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W INTM0 0 0 0 0 ES01 ES00 0 0 FFECH 00H R/W ES01 ES00 0 0 Falling edge 0 1 Rising edge 1 0 Setting prohibited 1 1 Both rising and falling edges INTP0 valid edge selection Cautions 1. Bits 0, 1, and 4 to 7 must be set to 0. 2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts. To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the interrupt mask flag (PMK0). (4) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for interrupt requests. The IE flag to set maskable interrupt enable/disable is mapped. Besides 8-bit unit read/write, this register can carry out operations with a bit manipulation instruction and dedicated instructions (EI, DI). When a vectored interrupt is acknowledged, the PSW is automatically saved into a stack, and the IE flag is reset to 0. RESET input sets PSW to 02H. Figure 12-5. Configuration of Program Status Word Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used when normal instruction is executed IE 156 Interrupt acknowledgement enabled/disabled 0 Disabled 1 Enabled User's Manual U16995EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS (5) Key return mode register 00 (KRM00) This register is used to specify whether the key return signal (falling edge of port 4) is to be detected. This register is set with a 1-bit or 8-bit memory manipulation instruction. RESET input clears KRM00 to 00H. Figure 12-6. Format of Key Return Mode Register 00 Symbol 7 6 5 4 3 2 1 0 Address After reset R/W KRM00 0 0 0 0 0 0 0 KRM00 FFF5H 00H R/W KRM00 Key return signal detection control 0 No detection 1 Detection (detecting falling edge of port 4) Cautions 1. Bits 1 to 7 must be set to 0. 2. Before setting KRM00, always set bit 6 of MK0 (KRMK00 = 1) to disable interrupts. After setting KRM00, clear KRMK00 after clearing bit 6 of IF1 (KRIF00 = 0) to enable interrupts. 3. On-chip pull-up resistors are automatically connected in input mode to the pins specified for key return signal detection (P40 to P43). Although these resistors are disconnected when the mode changes to output, key return signal detection continues unchanged. 4. The key return signal can be detected while all of P40 to P43 are high level. The key return signal cannot be detected while even one of P40 to P43 is low, even if any other key return pin goes low. Figure 12-7. Block Diagram of Falling Edge Detector Key return mode register 00 (KRM00) Note P41/KR01 P42/KR02 Selector P40/KR00 Falling edge detector INTKR00 P43/KR03 KRMK00 Standby release signal Note Selector that selects the pin used for falling edge input User's Manual U16995EJ2V0UD 157 CHAPTER 12 INTERRUPT FUNCTIONS 12.4 Interrupt Servicing Operation 12.4.1 Non-maskable interrupt request acknowledgment operation The non-maskable interrupt request is unconditionally acknowledged even when interrupts are disabled. It is not subject to interrupt priority control and takes precedence over all other interrupts. When the non-maskable interrupt request is acknowledged, PSW and PC are saved to the stack in that order, the IE flag is reset to 0, the contents of the vector table are loaded to the PC, and then program execution branches. Figure 12-8 shows the flow from non-maskable interrupt request generation to acknowledgement, Figure 12-9 shows the timing of non-maskable interrupt acknowledgement, and Figure 12-10 shows the acknowledgement operation when a number of non-maskable interrupts are generated. Caution During non-maskable interrupt service program execution, do not input another non-maskable interrupt request; if it is input, the service program will be interrupted and the new nonmaskable interrupt request will be acknowledged. 158 User's Manual U16995EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-8. Flow from Generation of Non-Maskable Interrupt Request to Acknowledgment Start WDTM4 = 1 (watchdog timer mode is selected) No Interval timer Yes No WDT overflows Yes WDTM3 = 0 No (non-maskable interrupt is selected) Reset processing Yes Interrupt request is generated Interrupt servicing starts WDTM: Watchdog timer mode register WDT: Watchdog timer Figure 12-9. Timing of Non-Maskable Interrupt Request Acknowledgment CPU processing Instruction Instruction Saving PSW and PC, and jump to interrupt servicing Interrupt servicing program WDTIF Figure 12-10. Non-Maskable Interrupt Request Acknowledgment Main routine First interrupt servicing NMI request (first) NMI request (second) Second interrupt servicing User's Manual U16995EJ2V0UD 159 CHAPTER 12 INTERRUPT FUNCTIONS 12.4.2 Maskable interrupt request acknowledgment operation A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt enabled status (when the IE flag is set to 1). The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in Table 12-3. Refer to Figures 12-12 and 12-13 for the timing of interrupt request acknowledgement. Table 12-3. Time from Generation of Maskable Interrupt Request to Servicing Note Minimum Time Maximum Time 9 clocks 19 clocks Note The wait time is maximum when an interrupt request is generated immediately before BT or BF instruction. Remark 1 clock: 1 fCPU (fCPU: CPU clock) When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting from the one assigned the highest priority by the priority specification flag. A pending interrupt is acknowledged when the status where it can be acknowledged is set. Figure 12-11 shows the algorithm of interrupt request acknowledgement. When a maskable interrupt request is acknowledged, the PSW and PC are saved to the stack in that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to the PC, and execution branches. To return from interrupt servicing, use the RETI instruction. Figure 12-11. Interrupt Request Acknowledgment Program Algorithm Start No xxIF = 1? Yes (Interrupt request generated) No xxMK = 0? Yes Interrupt request pending No IE = 1? Yes Interrupt request pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag IE: 160 Flag to control maskable interrupt request acknowledgement (1 = enable, 0 = disable) User's Manual U16995EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-12. Interrupt Request Acknowledgment Timing (Example: MOV A, r) 8 clocks Clock Saving PSW and PC, and jump to interrupt servicing MOV A, r CPU Interrupt servicing program Interrupt If the interrupt request has generated an interrupt request flag (xxIF) by the time the instruction clocks under execution, n clocks (n = 4 to 10), are n - 1, interrupt request acknowledgment processing will start following the completion of the instruction under execution. Figure 12-12 shows an example using the 8-bit data transfer instruction MOV A, r. Because this instruction is executed in 4 clocks, if an interrupt request is generated between the start of execution and the 3rd clock, interrupt request acknowledgment processing will take place following the completion of MOV A, r. Figure 12-13. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Generated in Final Clock Under Execution) 8 clocks Clock CPU NOP MOV A, r Saving PSW and PC, and jump to interrupt servicing Interrupt servicing program Interrupt If the interrupt request flag (xxIF) is generated in the final clock of the instruction, interrupt request acknowledgment processing will begin after execution of the next instruction is complete. Figure 12-13 shows an example whereby an interrupt request was generated in the 2nd clock of NOP (a 2-clock instruction). In this case, the interrupt request will be serviced after execution of MOV A, r, which follows NOP, is complete. Caution When interrupt request flag register 0 (IF0), or interrupt mask flag register 0 (MK0) is being accessed, interrupt requests will be held pending. 12.4.3 Multiple interrupt servicing Multiple interrupts, in which another interrupt request is acknowledged while an interrupt request being serviced, can be serviced using the priority order. If multiple interrupts are generated at the same time, they are serviced in the order according to the priority assigned to each interrupt request in advance (refer to Table 12-1). User's Manual U16995EJ2V0UD 161 CHAPTER 12 INTERRUPT FUNCTIONS Figure 12-14. Example of Multiple Interrupts Example 1. Acknowledging multiple interrupts INTxx servicing Main servicing EI IE = 0 INTxx EI INTyy servicing IE = 0 INTyy RETI RETI The interrupt request INTyy is acknowledged during the servicing of interrupt INTxx and multiple interrupts are performed. Before each interrupt request is acknowledged, the EI instruction is issued and the interrupt request is enabled. Example 2. Multiple interrupts are not performed because interrupts are disabled INTxx servicing Main servicing EI IE = 0 INTyy servicing INTyy is held pending INTyy RETI INTxx IE = 0 RETI Because interrupt requests are disabled (the EI instruction has not been issued) in the interrupt INTxx servicing, the interrupt request INTyy is not acknowledged and multiple interrupts are not performed. INTyy is held pending and is acknowledged after INTxx servicing is completed. IE = 0: Interrupt requests disabled 162 User's Manual U16995EJ2V0UD CHAPTER 12 INTERRUPT FUNCTIONS 12.4.4 Putting interrupt requests on hold If an interrupt request (such as a maskable, non-maskable, or external interrupt) is generated when a certain type of instruction is being executed, the interrupt request will not be acknowledged until the instruction is completed. Such instructions (interrupt request pending instructions) are as follows. * Instructions that manipulate interrupt request flag register 0 (IF0) * Instructions that manipulate interrupt mask flag register 0 (MK0) User's Manual U16995EJ2V0UD 163 CHAPTER 13 STANDBY FUNCTION 13.1 Standby Function and Configuration The standby function is to reduce the power consumption of the system and can be effected in the following two modes: (1) HALT mode This mode is set when the HALT instruction is executed. The HALT mode stops the operation clock of the CPU. The system clock oscillator continues oscillating. This mode does not reduce the operating current as much as the STOP mode, but is useful for resuming processing immediately when an interrupt request is generated, or for intermittent operations. (2) STOP mode This mode is set when the STOP instruction is executed. The STOP mode stops the main system clock oscillator and stops the entire system. The power consumption of the CPU can be substantially reduced in this mode. The data memory can be retained at the low voltage (VDD = 1.8 V). Therefore, this mode is useful for retaining the contents of the data memory at an extremely low operating current. The STOP mode can be released by an interrupt request, so that this mode can be used for intermittent operation. However, some time is required until the system clock oscillator stabilizes after the STOP mode has been released. If processing must be resumed immediately by using an interrupt request, therefore, use the HALT mode. In both modes, the previous contents of the registers, flags, and data memory before setting the standby mode are all retained. In addition, the statuses of the output latch of the I/O ports and output buffer are also retained. Caution To set the STOP mode, be sure to stop the operations of the peripheral hardware, and then execute the STOP instruction. 164 User's Manual U16995EJ2V0UD CHAPTER 13 STANDBY FUNCTION 13.2 Register Controlling Standby Function The wait time after the STOP mode is released upon interrupt request until oscillation stabilizes is controlled with the oscillation stabilization time selection register (OSTS). OSTS is set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets OSTS to 04H. Note that the time required for oscillation to stabilize after RESET input varies depending on the device (refer to Table 13-1), not depending on OSTS. Figure 13-1. Format of Oscillation Stabilization Time Selection Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W OSTS2 OSTS1 OSTS0 0 0 0 2 /fX (819 s) 0 1 0 2 /fX (6.55 ms) 1 0 0 2 /fX (26.2 ms) Other than above 12 15 17 Setting prohibited Caution The wait time after the STOP mode is released does not include the time from STOP mode release to clock oscillation start ("a" in the figure below), regardless of whether STOP mode is released by RESET input or by interrupt generation. STOP mode release X1 pin voltage waveform a Remarks 1. fX: Main system clock oscillation frequency 2. The parenthesized values apply to operation at fX = 5.0 MHz. Table 13-1. Oscillation Stabilization Time After RESET Input Part Number PD179322, 179322A, 179324, Oscillation Stabilization Time After RESET Input 15 17 2 /fX or 2 /fX (selectable using mask option) 179324A, 179326, 179327 PD78F9328 15 2 /fX User's Manual U16995EJ2V0UD 165 CHAPTER 13 STANDBY FUNCTION 13.3 Standby Function Operation 13.3.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. The operation status in the HALT mode is shown in the following table. Table 13-2. Operation Statuses in HALT Mode Item HALT Mode Operation Status During Main HALT Mode Operation Status During Subsystem System Clock Operation Clock Operation Subsystem Clock Subsystem Clock Main System Clock Main System Clock Operating Stopped Operating Stopped Main system clock Can be oscillated Oscillation stopped CPU Operation stopped Ports (output latches) Status before HALT mode setting retained 8-bit timer 30, 40 Operable Operation stopped Watch timer Operable Operable Watchdog timer Operable Power-on-clear circuit Operable Key return circuit Operable Serial interface 10 Operable Note 1 Operable Note 2 Operable Operation stopped Note 3 Note 4 Operable (provided in the PD78F9328 only) Note 5 LCD controller/driver Operable External interrupts Operable Operable Notes 1, 5 Operable Note 5 Note 3 Notes 1. Operation is enabled when the main system clock is selected 2. Operation is enabled when the subsystem clock is selected 3. Operation is enabled only for a maskable interrupt that is not masked 4. Operation is enabled only when an external clock is selected 5. The HALT instruction can be set after display instruction execution 166 User's Manual U16995EJ2V0UD Operable Notes 2, 5 CHAPTER 13 STANDBY FUNCTION (2) Releasing HALT mode The HALT mode can be released by the following three types of sources: (a) Releasing by unmasked interrupt request The HALT mode is released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed. If the interrupt is disabled, the instruction at the next address is executed. Figure 13-2. Releasing HALT Mode by Interrupt HALT instruction Wait Standby release signal Operation mode HALT mode Wait Operation mode Oscillation Clock Remarks 1. The broken line indicates the case where the interrupt request that has released the standby mode is acknowledged. 2. The wait time is as follows: (b) * When vectored interrupt processing is performed: 9 to 10 clocks * When vectored interrupt processing is not performed: 1 to 2 clocks Releasing by non-maskable interrupt request The HALT mode is released regardless of whether the interrupt is enabled or disabled, and vectored interrupt processing is performed. User's Manual U16995EJ2V0UD 167 CHAPTER 13 STANDBY FUNCTION (c) Releasing by RESET input When the HALT mode is released by the RESET signal, execution branches to the reset vector address in the same manner as the ordinary reset operation, and program execution is started. Figure 13-3. Releasing HALT Mode by RESET Input HALT instruction WaitNote RESET signal Operation mode Clock HALT mode Reset period Oscillation stabilization wait status Oscillation Oscillation stops Oscillation Operation mode Note 215/fX: 6.55 ms (@ fX = 5.0 MHz operation) Remark fX: Main system clock oscillation frequency Table 13-3. Operation After Releasing HALT Mode Releasing Source Maskable interrupt request Non-maskable interrupt request RESET input MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing 1 x Retains HALT mode - x Executes interrupt servicing --- - Reset processing x: don't care 168 User's Manual U16995EJ2V0UD CHAPTER 13 STANDBY FUNCTION 13.3.2 STOP mode (1) Setting and operation status of STOP mode The STOP mode is set by executing the STOP instruction. Caution Because the standby mode can be released by an interrupt request signal, the standby mode is released as soon as it is set if there is an interrupt source whose interrupt request flag is set and interrupt mask flag is reset. When the STOP mode is set, therefore, the HALT mode is set immediately after the STOP instruction has been executed, the wait time set by the oscillation stabilization time selection register (OSTS) elapses, and then an operation mode is set. The operation status in the STOP mode is shown in the following table. Table 13-4. Operation Statuses in STOP Mode Item STOP Mode Operation Status During Main System Clock Operation Subsystem Clock Operating Main system clock Oscillation stopped CPU Operation stopped Ports (output latches) Status before STOP mode setting retained 8-bit timer 30, 40 Operation stopped Watch timer Operable Watchdog timer Operation stopped Power-on-clear circuit Operable Key return circuit Operable Serial interface 10 Operable Note 1 Subsystem Clock Stopped Operation stopped Note 2 Note 3 (provided in the PD78F9328 only) LCD controller/driver Operable External interrupts Operable Note 1 Operation stopped Note 4 Note 2 Notes 1. Operation is enabled when the subsystem clock is selected. 2. Operation is enabled only for a maskable interrupt that is not masked. 3. Operation is enabled only when an external clock is selected. 4. Before selecting the STOP mode, disable display and select the static mode (refer to 10.3 (1) LCD display mode register 0 (LCDM0) ). User's Manual U16995EJ2V0UD 169 CHAPTER 13 STANDBY FUNCTION (2) Releasing STOP mode The STOP mode can be released by the following two types of sources: (a) Releasing by unmasked interrupt request The STOP mode can be released by an unmasked interrupt request. In this case, if the interrupt is enabled to be acknowledged, vectored interrupt processing is performed, after the oscillation stabilization time has elapsed. If the interrupt is disabled, the instruction at the next address is executed. Figure 13-4. Releasing STOP Mode by Interrupt Wait (set time by OSTS) STOP instruction Standby release signal Clock Remark Operation mode STOP mode Oscillation stabilization wait status Oscillation Oscillation stops Oscillation The broken line indicates the case where the interrupt request that has released the standby mode is acknowledged. 170 Operation mode User's Manual U16995EJ2V0UD CHAPTER 13 STANDBY FUNCTION (b) Releasing by RESET input When the STOP mode is released by the RESET signal, the reset operation is performed after the oscillation stabilization time has elapsed. Figure 13-5. Releasing STOP Mode by RESET Input STOP instruction WaitNote RESET signal Operation mode Clock Oscillation stabilization wait status Reset period STOP mode Oscillation stops Oscillation Operation mode Oscillation Note 215/fX: 6.55 ms (@ fX = 5.0 MHz operation) Remark fX: Main system clock oscillation frequency Table 13-5. Operation After Releasing STOP Mode Releasing Source Maskable interrupt request RESET input MKxx IE Operation 0 0 Executes next address instruction 0 1 Executes interrupt servicing 1 x Retains STOP mode - --- Reset processing x: don't care User's Manual U16995EJ2V0UD 171 CHAPTER 14 RESET FUNCTION The following three operations are available to generate reset signals. (1) External reset signal input via RESET pin (2) Internal reset by detection of watchdog timer inadvertent program loop time (3) Internal reset using power-on-clear circuit (POCNote) The external and internal reset signals are functionally equivalent. When RESET is input, program execution begins from the addresses written at addresses 0000H and 0001H. If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each item of the hardware to enter the states listed in Table 14-1. While a reset is being applied, or while the oscillation frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state. If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution is started after the oscillation stabilization time has elapsed. A reset sequence caused by a watchdog timer overflow is terminated automatically and program execution is started after the oscillation stabilization time has elapsed. Reset by power-on-clear (POCNote) is cleared if the supply voltage rises beyond a specific level, and the program execution is started after the oscillation stabilization time has elapsed. Note Enabled in mask ROM versions (PD179322, 179322A, 179324, 179324A, 179326, and 179327) only when POC circuit usage is selected by a mask option. Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. 2. When the STOP mode is cleared by reset, the STOP mode contents are held during reset input. However, the port pins become high impedance. 3. In the case of mask ROM versions, the oscillation stabilization time after RESET input or the release of STOP mode by POC can be selected from 215/fX or 217/fX by mask option (refer to CHAPTER 16 MASK OPTIONS). In the case of the PD78F9328, only 215/fX can be set because the mask option is not available. Figure 14-1. Block Diagram of Reset Function VDD Power-on-clear circuit RESET Count clock Watchdog timer Stop 172 Reset signal Reset controller User's Manual U16995EJ2V0UD Overflow Interrupt function CHAPTER 14 RESET FUNCTION Figure 14-2. Reset Timing by RESET Input X1 During normal operation Oscillation stabilization time wait Reset period (oscillation stops) Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin Figure 14-3. Reset Timing by Overflow in Watchdog Timer X1 Oscillation stabilization time wait Reset period (oscillation continues) During normal operation Normal operation (reset processing) Overflow in watchdog timer Internal reset signal Hi-Z Port pin Figure 14-4. Reset Timing by RESET Input in STOP Mode X1 STOP instruction execution During normal Stop status operation (oscillation stops) Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) RESET Internal reset signal Delay Delay Hi-Z Port pin User's Manual U16995EJ2V0UD 173 CHAPTER 14 RESET FUNCTION Figure 14-5. Reset Timing by Power-on Clear (a) At power application X1 Reset period (oscillation stops) VDD Oscillation stabilization time wait Normal operation (reset processing) Power-on-clear voltage (VPOC) Internal reset signal Hi-Z Port pin (b) In STOP mode X1 STOP instruction execution Stop status (oscillation stops) During normal operation Reset period (oscillation stops) Oscillation stabilization time wait Normal operation (reset processing) VDD Power-on-clear voltage (VPOC) Internal reset signal Hi-Z Port pin (c) In normal operation mode (including HALT mode) X1 Reset period (oscillation stops) During normal operation Oscillation stabilization time wait Normal operation (reset processing) VDD Power-on-clear voltage (VPOC) Internal reset signal Hi-Z Port pin 174 User's Manual U16995EJ2V0UD CHAPTER 14 RESET FUNCTION Table 14-1. Hardware Status After Reset Hardware Status After Reset Note 1 Program counter (PC) Contents of reset vector table (0000H, 0001H) set Stack pointer (SP) Undefined Program status word (PSW) 02H RAM Data memory Undefined General-purpose registers Undefined Note 2 Ports (P0 to P2, P4, P6, P8) (output latches) 00H Port mode registers (PM0 to PM2, PM4, PM6) FFH Port mode register 8 (PM8) 3FH Port function register 8 (PF8) 00H Pull-up resistor option registers (PU0, PUB2) 00H Processor clock control register (PCC) 02H Suboscillation mode register (SCKM) 00H Subclock control register (CSS) 00H Oscillation stabilization time selection register (OSTS) 04H 8-bit timer 30, 40 Timer counters (TM30, TM40) 00H Compare registers (CR30, CR40, CRH40) Undefined Mode control registers (TMC30, TMC40) 00H Carrier generator output control register (TCA40) 00H Watch timer Mode control register (WTM) 00H Watchdog timer Mode register (WDTM) 00H Clock selection register (TCL2) 00H Serial interface 10 ( Provided in the PD78F9328 only) LCD controller/driver Serial operation mode register 10 (CSIM10) Transmit/receive shift register 10 (SIO10) Note 3 Note 3 Note 2 00H Undefined Display mode register 0 (LCDM0) 00H Clock control register 0 (LCDC0) 00H Power-on-clear circuit Power-on-clear register 1 (POCF1) 00H Interrupts Request flag register 0 (IF0) 00H Mask flag register 0 (MK0) FFH External interrupt mode register 0 (INTM0) 00H Key return mode register 00 (KRM00) 00H Note 4 Notes 1. While a reset signal is being input, and during the oscillation stabilization time wait, only the contents of the PC will be undefined; the remainder of the hardware will be the same state as after reset. 2. In standby mode, RAM enters the hold state after reset. 3. Provided in the PD78F9328 only 4. The value is 04H only after a power-on-clear reset. User's Manual U16995EJ2V0UD 175 CHAPTER 15 PD78F9328 The PD78F9328 is available as the flash memory version of the PD179327 Subseries. The PD78F9328 is a version with the internal ROM of the PD179322, 179322A, 179324, 179324A, 179326, 179327 replaced with flash memory. The differences between the PD78F9328 and the mask ROM versions are shown in Table 15-1. Table 15-1. Differences Between PD78F9328 and Mask ROM Versions Part Number Flash Memory Mask ROM Version Version PD78F9328 Item Internal ROM memory 32 KB PD179322 PD179324 PD179322A PD179324A 4 KB 8 KB PD179326 16 KB PD179327 24 KB (flash memory) High-speed RAM 512 bytes 256 bytes 512 bytes LCD display RAM 24 x 4 bits IC0 pin Not provided Provided VPP pin Provided Not provided Serial interface 10 Provided Not provided Power-on clear (POC) Always operates Use is selected by mask option circuit Oscillation stabilization wait 15 15 17 Fixed to 2 /fX 2 /fX or 2 /fX selected by mask option Power supply voltage VDD = 1.8 to 5.5 V VDD = 1.8 to 3.6 V Electrical specifications Refer to CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, time after STOP mode is released by RESET or POC 179324A, 179326, AND 179327) and CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the commercial samples (not engineering samples) of the mask ROM version. 176 User's Manual U16995EJ2V0UD CHAPTER 15 PD78F9328 15.1 Flash Memory Characteristics Flash memory programming is performed by connecting a dedicated flash programmer (Flashpro IV (part no. FLPR4, PG-FP4)) to the target system with the flash memory mounted on the target system (on-board). A flash memory writing adapter (program adapter), which is a target board used exclusively for programming, is also provided. Remark FL-PR4, and the program adapter are the products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191). Programming using flash memory has the following advantages. * Software can be modified after the microcontroller is solder-mounted on the target system. * Distinguishing software facilities low-quantity, varied model production * Easy data adjustment when starting mass production 15.1.1 Programming environment The following shows the environment required for PD78F9328 flash memory programming. When Flashpro III/Flashpro IV is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS232C/USB (Rev.1.1). For details, refer the manuals for Flashpro IV. Figure 15-1. Environment for Writing Program to Flash Memory VPP VDD RS-232C VSS USB RESET Dedicated flash programmer 3-wire serial I/O PD78F9328 Host machine User's Manual U16995EJ2V0UD 177 CHAPTER 15 PD78F9328 15.1.2 Communication mode Use the communication mode shown in Table 15-2 to perform communication between the dedicated flash programmer and PD78F9328. Table 15-2. Communication Mode List Note 1 Communication Mode TYPE Setting COMM PORT CPU Clock SIO clock In Flashpro 3-wire serial I/O SIO ch-0 (3-wired, sync) 100 Hz to 1.25 Note2 MHz Pins used 1, 2, 4, 5 Number of VPP pulses Multiple rate On Target Board Note 2 1 to 5 MHz 1.0 Notes 2, 3 MHz SCK10/P20 0 SO10/P21 SI10/P22 Notes 1. Selection items for TYPE settings on the dedicated flash programmer (Flashpro IV (part no. FL-PR4, PG-FP4)). 2. The possible setting range differs depending on the voltage. For details, refer to CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328). Caution Be sure to select a communication mode depending on the number of VPP pulses shown in Table 15-2. Figure 15-2. Communication Mode Selection Format 10 V VPP VDD 1 2 n VSS VPP pulses VDD RESET VSS 178 User's Manual U16995EJ2V0UD CHAPTER 15 PD78F9328 Figure 15-3. Example of Connection with Dedicated Flash Programmer PD78F9328 Dedicated flash programmer VPP VPP VDD VDD /RESET RESET SCK SCK10 SO/TxD SI10 SI/RxD SO10 CLKNote X1 GND VSS Note Connect this pin when the system clock is supplied by dedicated flash programmer. If an oscillator is already connected to the X1 pin, do not connect to the CLK pin. Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. Before using the power supply connected to the VDD pin, supply voltage before starting programming. If Flashpro III/Flashpro IV is used as a dedicated flash programmer, the following signals are generated for the PD78F9328. For details, refer to the manual of Flashpro III/Flashpro IV. Table 15-3. Pin Connection List Signal Name VPP1 I/O Output Write voltage - VPP2 VDD Pin Function I/O - GND Pin Name VPP - x VDD voltage generation VDD Ground VSS CLK Output Clock output X1 RESET Output Reset signal RESET SI Input Reception signal SO10 SO Output Transmit signal SI10 SCK Output Transfer clock SCK10 HS - 3-Wire Serial I/O - - Note x Note VDD voltage must be supplied before programming is started. Remark : Pin must be connected. : If the signal is supplied on the target board, pin need not be connected. x: Pin need not be connected. User's Manual U16995EJ2V0UD 179 CHAPTER 15 PD78F9328 15.1.3 On-board pin processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and flash memory programming mode may be required in some cases. <VPP pin> In normal operation mode, input 0 V to the VPP pin. In flash memory programming mode, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin, so perform the following. (1) Connect a pull-down resistor (RVPP = 10 k) to the VPP pin. (2) Use the jumper on the board to switch the VPP pin input to either the writer or directly to GND. A VPP pin connection example is shown below. Figure 15-4. VPP Pin Connection Example PD78F9328 Connection pin of dedicated flash programmer VPP Pull-down resistor (RVPP) <Serial interface pin> The following shows the pins used by the serial interface. Serial Interface 3-wire serial I/O Pins Used SCK10, SO10, SI10 When connecting the dedicated flash programmer a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other devices may occur. Care must therefore be taken with such connections. 180 User's Manual U16995EJ2V0UD CHAPTER 15 PD78F9328 (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 15-5. Signal Conflict (Input Pin of Serial Interface) PD78F9328 Signal conflict Connection pin of dedicated flash programmer Input pin Other device Output pin In the flash memory programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict, therefore, isolate the signal of the other device. (2) Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the input signals to the other device are ignored. Figure 15-6. Abnormal Operation of Other Device PD78F9328 Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the PD78F9328 affects another device in the flash memory programming mode, isolate the signals of the other device. PD78F9328 Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the dedicated flash programmer affects another device in the flash memory programming mode, isolate the signals of the other device. User's Manual U16995EJ2V0UD 181 CHAPTER 15 PD78F9328 <RESET pin> If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the flash memory programming mode, a normal programming operation cannot be performed. Therefore, do not input reset signals from other than the dedicated flash programmer. Figure 15-7. Signal Conflict (RESET Pin) PD78F9328 Signal Conflict Connection pin of dedicated flash programmer RESET Output pin The signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the flash memory programming mode, so isolate the signal of the reset signal generator. <Port pins> When the PD78F9328 enters the flash memory programming mode, all the pins other than those that communicate in flash memory programming are in the same status as immediately after reset. If the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to VDD or VSS via a resistor. <Oscillator> When using the on-board clock, connect X1 and X2 as required in the normal operation mode. When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main oscillator on-board, and leave the X2 pin open. <Power supply> When using the power supply output of the flash programmer, connect the VDD and VSS pins to VDD and GND of the flash programmer, respectively. When using the on-board power supply, connect it as required in the normal operation mode. Because the flash programmer monitors the voltage, however, VDD of the flash programmer must be connected. 182 User's Manual U16995EJ2V0UD CHAPTER 15 PD78F9328 15.1.4 Connection on flash memory writing adapter The following shows an example of the recommended connection when using the flash memory writing adapter. Figure 15-8. Wiring Example of Flash Memory Writing Adapter Using 3-Wire Serial I/O Mode VDD (2.7 to 5.5 V) GND 1 52 51 50 49 48 47 46 45 44 43 42 41 40 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 27 13 14 15 16 17 18 19 20 21 21 23 24 25 26 GND VDD VDD2 SI/RxD SO/TxD SCK CLK /RESET VPP RESERVE/HS WRITER INTERFACE User's Manual U16995EJ2V0UD 183 CHAPTER 16 MASK OPTIONS The mask ROM versions (PD179322, 179322A, 179324, 179324A, 179326, and 179327) have the following mask option. * Oscillation stabilization wait time The oscillation stabilization wait time after the release of STOP mode by RESET or POC can be selected. <1> 215/fX <2> 217/fX Caution The oscillation stabilization wait time for the flash memory version (PD78F9328) is fixed to 215/fX. * Power-on-clear (POC) circuit Use/non use of the POC circuit can be selected. <1> POC circuit used <2> POC circuit not used Caution 184 The POC circuit of the flash memory version (PD78F9328) is always used (always operating). User's Manual U16995EJ2V0UD CHAPTER 17 INSTRUCTION SET This chapter lists the instruction set of the PD179327 Subseries. For the details of the operation and machine language (instruction code) of each instruction, refer to 78K/0S Series Instructions User's Manual (U11047E). 17.1 Operation 17.1.1 Operand identifiers and description methods Operands are described in "Operands" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for detail). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $, and [ ] are key words and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * $: Relative address specification * !: Absolute address specification * [ ]: Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $ and [ ] symbols. For operand register identifiers, r and rp, either functional names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for description. Table 17-1. Operand Identifiers and Description Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special-function register symbol saddr FE20H to FF1FH Immediate data or labels saddrp FE20H to FF1FH Immediate data or labels (even addresses only) addr16 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions) addr5 0040H to 007FH Immediate data or labels (even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label Remark See Table 3-3 Special Function Registers for symbols of special function registers. User's Manual U16995EJ2V0UD 185 CHAPTER 17 INSTRUCTION SET 17.1.2 Description of "Operation" column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Flag indicating non-maskable interrupt servicing in progress ( ): Memory contents indicated by address or register contents in parenthesis XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) V: Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 17.1.3 Description of "Flag" column (Blank): Unchanged 0: Cleared to 0 1: Set to 1 x: Set/cleared according to the result R: Previously saved value is restored 186 User's Manual U16995EJ2V0UD CHAPTER 17 INSTRUCTION SET 17.2 Operation List Mnemonic Operands Byte Clock Operation Flag Z AC CY MOV r, #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte 3 6 sfr byte A, r Note 1 2 4 Ar r, A Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL+byte] 2 6 A (HL + byte) [HL+byte], A 2 6 (HL + byte) A 1 4 AX 2 6 Ar A, saddr 2 6 A (saddr) A, sfr 2 6 A sfr A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL+byte] 2 8 A (HL + byte) sfr, #byte XCH A, X A, r Note 2 x x x x x x Notes 1. Except r = A. 2. Except r = A, X. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U16995EJ2V0UD 187 CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY MOVW rp, #word 3 6 rp word AX, saddrp 2 6 AX (saddrp) 2 8 (saddrp) AX AX, rp Note 1 4 AX rp rp, AX Note 1 4 rp AX XCHW AX, rp Note 1 8 AX rp ADD A, #byte 2 4 A, CY A + byte x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte x x x A, r 2 4 A, CY A + r x x x A, saddr 2 4 A, CY A + (saddr) x x x A, !addr16 3 8 A, CY A + (addr16) x x x A, [HL] 1 6 A, CY A + (HL) x x x A, [HL+byte] 2 6 A, CY A + (HL + byte) x x x A, #byte 2 4 A, CY A + byte + CY x x x saddr, #byte 3 6 (saddr), CY (saddr) + byte + CY x x x A, r 2 4 A, CY A + r + CY x x x A, saddr 2 4 A, CY A + (saddr) + CY x x x A, !addr16 3 8 A, CY A + (addr16) + CY x x x A, [HL] 1 6 A, CY A + (HL) + CY x x x A, [HL+byte] 2 6 A, CY A + (HL + byte) + CY x x x A, #byte 2 4 A, CY A - byte x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte x x x A, r 2 4 A, CY A - r x x x A, saddr 2 4 A, CY A - (saddr) x x x A, !addr16 3 8 A, CY A - (addr16) x x x A, [HL] 1 6 A, CY A - (HL) x x x A, [HL+byte] 2 6 A, CY A - (HL + byte) x x x saddrp, AX ADDC SUB Note Only when rp = BC, DE, or HL. Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 188 User's Manual U16995EJ2V0UD CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY SUBC AND OR XOR Remark A, #byte 2 4 A, CY A - byte - CY x x x saddr, #byte 3 6 (saddr), CY (saddr) - byte - CY x x x A, r 2 4 A, CY A - r - CY x x x A, saddr 2 4 A, CY A - (saddr) - CY x x x A, !addr16 3 8 A, CY A - (addr16) - CY x x x A, [HL] 1 6 A, CY A - (HL) - CY x x x A, [HL+byte] 2 6 A, CY A - (HL + byte) - CY x x x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL+byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A byte x saddr, #byte 3 6 (saddr) (saddr) byte x A, r 2 4 AAr x A, saddr 2 4 A A (saddr) x A, !addr16 3 8 A A (addr16) x A, [HL] 1 6 A A (HL) x A, [HL+byte] 2 6 A A (HL + byte) x A, #byte 2 4 A A V byte x saddr, #byte 3 6 (saddr) (saddr) V byte x A, r 2 4 AAVr x A, saddr 2 4 A A V (saddr) x A, !addr16 3 8 A A V (addr16) x A, [HL] 1 6 A A V (HL) x A, [HL+byte] 2 6 A A V (HL + byte) x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U16995EJ2V0UD 189 CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY A, #byte 2 4 A - byte x x x saddr, #byte 3 6 (saddr) - byte x x x A, r 2 4 A-r x x x A, saddr 2 4 A - (saddr) x x x A, !addr16 3 8 A - (addr16) x x x A, [HL] 1 6 A - (HL) x x x A, [HL+byte] 2 6 A - (HL + byte) x x x ADDW AX, #word 3 6 AX, CY AX + word x x x SUBW AX, #word 3 6 AX, CY AX - word x x x CMPW AX, #word 3 6 AX - word x x x INC r 2 4 rr+1 x x saddr 2 4 (saddr) (saddr) + 1 x x r 2 4 rr-1 x x saddr 2 4 (saddr) (saddr) - 1 x x INCW rp 1 4 rp rp + 1 DECW rp 1 4 rp rp - 1 ROR A, 1 1 2 (CY, A7 A0, Am-1 Am) x 1 x ROL A, 1 1 2 (CY, A0 A7, Am+1 Am) x 1 x RORC A, 1 1 2 (CY A0, A7 CY, Am-1 Am) x 1 x ROLC A, 1 1 2 (CY A7, A0 CY, Am+1 Am) x 1 x SET1 saddr.bit 3 6 (saddr.bit) 1 sfr.bit 3 6 sfr.bit 1 A.bit 2 4 A.bit 1 PSW.bit 3 6 PSW.bit 1 [HL].bit 2 10 (HL).bit 1 saddr.bit 3 6 (saddr.bit) 0 sfr.bit 3 6 sfr.bit 0 A.bit 2 4 A.bit 0 PSW.bit 3 6 PSW.bit 0 [HL].bit 2 10 (HL).bit 0 SET1 CY 1 2 CY 1 1 CLR1 CY 1 2 CY 0 0 NOT1 CY 1 2 CY CY x CMP DEC CLR1 Remark x x x x x One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). 190 x User's Manual U16995EJ2V0UD CHAPTER 17 INSTRUCTION SET Mnemonic Operands Byte Clock Operation Flag Z AC CY CALL !addr16 3 6 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 CALLT [addr5] 1 8 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 RET 1 6 RETI 1 8 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), R R R R R R PSW (SP + 2), SP SP + 3, NMIS 0 PSW 1 2 (SP - 1) PSW, SP SP - 1 rp 1 4 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 1 4 PSW (SP), SP SP + 1 rp 1 6 rpH (SP + 1), rpL (SP), SP SP + 2 SP, AX 2 8 SP AX AX, SP 2 6 AX SP !addr16 3 6 PC addr16 $addr16 2 6 PC PC + 2 + jdisp8 AX 1 6 PCH A, PCL X BC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 1 BNC $saddr16 2 6 PC PC + 2 + jdisp8 if CY = 0 BZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 1 BNZ $saddr16 2 6 PC PC + 2 + jdisp8 if Z = 0 BT saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 1 saddr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.bit, $addr16 4 10 PC PC + 4 + jdisp8 if sfr.bit = 0 A.bit, $addr16 3 8 PC PC + 3 + jdisp8 if A.bit = 0 PSW.bit, $addr16 4 10 PC PC + 4 + jdisp8 if PSW.bit = 0 B, $addr16 2 6 B B - 1, then PC PC + 2 + jdisp8 if B 0 C, $addr16 2 6 C C - 1, then PC PC + 2 + jdisp8 if C 0 saddr, $addr16 3 8 (saddr) (saddr) - 1, then PUSH POP MOVW BR BF DBNZ PC PC + 3 + jdisp8 if (saddr) 0 NOP 1 2 No Operation EI 3 6 IE 1 (Enable interrupt) DI 3 6 IE 0 (Disable interrupt) HALT 1 2 Set HALT mode STOP 1 2 Set STOP mode Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control register (PCC). User's Manual U16995EJ2V0UD 191 CHAPTER 17 INSTRUCTION SET 17.3 Instructions Listed by Addressing Type (1) 8-bit instructions MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH, POP, DBNZ 2nd Operand #byte A r sfr saddr !addr16 PSW [DE] [HL] [HL+byte] r 1 None 6 1st Operand A $addr1 Note ADD MOV ADDC XCHNote MOV MOV XCH XCH SUB ADD ADD SUBC ADDC AND MOV MOV MOV MOV ROR XCH XCH XCH ROL ADD ADD ADD RORC ADDC ADDC ADDC ADDC ROLC SUB SUB SUB SUB SUB OR SUBC SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP CMP CMP CMP CMP MOV MOV MOV INC DEC B, C sfr saddr DBNZ MOV MOV MOV MOV DBNZ ADD INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] MOV [HL] MOV [HL+byte] MOV Note Except r = A. 192 User's Manual U16995EJ2V0UD CHAPTER 17 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW 2nd Operand #word AX rp Note saddrp SP None 1st Operand AX ADDW MOVW SUBW XCHW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP saddrp MOVW SP MOVW Note Only when rp = BC, DE, or HL. (3) Bit manipulation instructions SET1, CLR1, NOT1, BT, BF 2nd Operand $addr16 None 1st Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 BT SET1 BF CLR1 SET1 CLR1 CY SET1 CLR1 NOT1 User's Manual U16995EJ2V0UD 193 CHAPTER 17 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ 2nd Operand AX !addr16 [addr5] $addr16 1st Operand Basic Instructions BR CALL BR CALLT BR BC BNC BZ BNZ Compound Instructions (5) DBNZ Other instructions RET, RETI, NOP, EI, DI, HALT, STOP 194 User's Manual U16995EJ2V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) Absolute Maximum Ratings (TA = 25C) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit VDD -0.3 to +6.5 V VLC0 -0.3 to +6.5 -0.3 to VDD + 0.3 VI Output voltage VO1 V Note P00 to P03, P10, P11, P20 to P22, Note -0.3 to VDD + 0.3 V V P40 to P43, P60, P61 VO2 COM0 to COM3, S0 to S16, Note -0.3 to VLC0 + 0.3 V P80/S22 to P85/S17, S23 Output current, high Output current, low IOH IOL Pin P60/TO40 -30 mA Per pin (except P60/TO40) -10 mA Total for all pins (except P60/TO40) -30 mA Per pin 30 mA Total for all pins 80 mA Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Note 6.5 V or less Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U16995EJ2V0UD 195 CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Resonator Ceramic Recommended Circuit X2 X1 resonator C2 Crystal X2 External clock X1 Conditions Oscillation frequency Note 1 (fX) MIN. 1.0 Oscillation After VDD has reached the Note 2 stabilization time oscillation voltage range MIN. C1 X1 resonator C2 Parameter Oscillation Note 1 frequency 1.0 Oscillation Note 2 stabilization time C1 X2 TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 30 ms X1 input frequency Note 1 (fX) 1.0 5.0 MHz X1 input high-/low- 85 500 ns level width (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator to stabilize oscillation within the oscillation wait time. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 196 User's Manual U16995EJ2V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) Recommended Oscillation Circuit Constants Ceramic oscillator (TA = -40 to +85C) (mask ROM version) Manufacturer Part Number Frequency (MHz) Murata Mfg. (standard Note CSBLA1M00J58-B0 CSBFB1M00J58-R1 Recommended Circuit Oscillation Voltage Constant (pF) Range (VDD) C1 C2 MIN. MAX. 1.0 100 100 1.9 3.6 2.0 - - Remark Rd = 1.5 k Note product) CSTCC2M00G56-R0 With internal capacitor CSTLS2M00G56-B0 4.0 CSTCR4M00G53-R0 CSTLS4M00G53-B0 1.8 3.6 1.9 3.6 1.8 3.6 1.9 3.6 1.8 3.6 4.194 CSTCR4M19G53-R0 CSTLS4M19G53-B0 4.915 CSTCR4M91G53-R0 CSTLS4M91G53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00G53-B0 Murata Mfg. (low-voltage CSTLS4M00G53093-B0 4.0 CSTLS4M19G53093-B0 4.194 CSTCR4M91G53093-R0 4.915 - - With internal capacitor drive type) CSTLS4M91G53093-B0 CSTCR5M00G53093-R0 5.0 CSTLS5M00G53093-B0 TDK FCR4.0MC5 4.0 FCR5.0MC5 - - 2.2 3.6 With internal capacitor 5.0 Note When using the CSBLA1M00J58-B0 or CSBFB1M00J58-R1 (1.0 MHz) of Murata Mfg. as the ceramic oscillator, a limiting resistor (Rd = 1.5 k) is necessary (refer to the figure below). The limiting resistor is not necessary when other recommended oscillators are used. X1 X2 CSBLA1M00J58-B0 CSBFB1M00J58-R1 C1 Caution Rd C2 The oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the PD179327 Subseries so that the internal operating conditions are within the specifications of the DC and AC characteristics. User's Manual U16995EJ2V0UD 197 CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) Remark For the resonator selection and oscillator constant of PD179322A and 179324A, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Resonator Crystal Recommended Circuit XT1 C3 External XT2 R resonator XT1 C4 XT2 clock Parameter Conditions Oscillation frequency Note 1 (fXT) MIN. TYP. MAX. Unit 32 32.768 35 kHz 10 s Oscillation Note 2 stabilization time XT1 input frequency Note 1 (fXT) 32 35 kHz XT1 input high-/low- 14.3 15.6 s level width (tXTH, tXTL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a resonator to stabilize oscillation during the oscillation wait time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 198 User's Manual U16995EJ2V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V) (1/2) Parameter Output current, low Output current, high Symbol IOL IOH Conditions MAX. Unit Per pin 10 mA Total for all pins 80 mA Per pin (except P60/TO40) -1 mA -24 mA -15 mA P60/TO40 VDD = 3.0 V, VOH = 2.0 V MIN. -7 Total for all pins (except P60/TO40) Input voltage, high VIH1 VIH2 Input voltage, low -15 P00 to P03, P10, P11, 2.7 VDD 3.6 V 0.7VDD VDD V P60, P80 to P85 1.8 VDD 3.6 V 0.9VDD VDD V RESET, P20 to P22, P40 to 2.7 VDD 3.6 V 0.8VDD VDD V P43, P61 1.8 VDD 3.6 V 0.9VDD VDD V VIH3 X1, X2 VDD - 0.1 VDD V VIH4 XT1, XT2 VDD - 0.1 VDD V VIL1 P00 to P03, P10, P11, 2.7 VDD 3.6 V 0 0.3VDD V P60, P80 to P85 1.8 VDD 3.6 V 0 0.1VDD V RESET, P20 to P22, P40 2.7 VDD 3.6 V 0 0.2VDD V to P43, P61 1.8 VDD 3.6 V 0 0.1VDD V VIL2 Output voltage, high TYP. VIL3 X1, X2 0 0.1 V VIL4 XT1, XT2 0 0.1 V VOH11 VOH12 P00 to P03, P10, P11, 1.8 VDD 3.6 V, P20 to P22, P40 to P43, IOH = -100 A P61 1.8 VDD 3.6 V, VDD - 0.5 V VDD - 0.7 V VDD - 0.5 V VDD - 0.7 V VLC0 - 0.5 V VLC0 - 0.7 V IOH = -500 A VOH21 1.8 VDD 3.6 V, P60/TO40 IOH = -400 A 1.8 VDD 3.6 V, VOH22 IOH = -2 mA VOH31 P80/S22 to P85/S17 1.8 VDD 3.6 V, IOH = -100 A 1.8 VDD 3.6 V, VOH32 IOH = -500 A Output voltage, low VOL11 VOL12 P00 to P03, P10, P11, 1.8 VDD 3.6 V, P20 to P22, P40 to P43, IOL = 400 A P60, P61 1.8 VDD 3.6 V, 0.5 V 0.7 V 0.5 V 0.7 V IOL = 2 mA VOL21 P80/S22 to P85/S17 1.8 VLC0 3.6 V, IOL = 400 A VOL22 1.8 VLC0 3.6 V, IOL = 2 mA Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U16995EJ2V0UD 199 CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V) (2/2) Parameter Input leakage current, Symbol ILIH1 Conditions VIN = VDD MIN. TYP. MAX. Unit 3 A X1, X2, XT1, XT2 20 A P00 to P03, P10, -3 A -20 A 100 200 k VDD = 3.3 V 0.6 1.2 mA VDD = 3.3 V 0.4 0.8 mA P00 to P03, P10, high P11, P20 to P22, P40 to P43, P60, P61, RESET, P80 to P85 ILIH2 Input leakage current, ILIL1 VIN = 0 V low P11, P20 to P22, P40 to P43, P60, P61, RESET, P80 to P85 X1, X2, XT1, XT2 ILIL2 Software pull-up R1 VIN = 0 V P00 to P03, P10, resistors 50 P11, P20 to P22, P40 to P43 Supply current Note 1 IDD1 5.0 MHz crystal oscillation Note 2 operating mode IDD2 5.0 MHz crystal oscillation HALT mode IDD3 32.768 kHz crystal Note 3 oscillation HALT mode VDD = 3.3 V 7 25 A IDD4 32.768 kHz crystal oscillation VDD = 3.3 V 1 10 A VDD = 3.3 V 0.05 5 A stopped STOP mode (POC circuit used) IDD5 32.768 kHz crystal oscillation stopped STOP mode (POC circuit not used) Notes 1. Current flowing through ports (including current flowing through on-chip pull-up resistors and from VLC0 to VSS) is not included. 2. Low-speed mode operation (when PCC is set to 02H) 3. When the main system clock operation is stopped. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 200 User's Manual U16995EJ2V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Parameter Symbol Cycle time TCY (Min. instruction execution time) Interrupt input tINTH, high-/low-level width tINTL Key return pin tKRIL Conditions MIN. TYP. MAX. Unit 2.7 VDD 3.6 V 0.4 8.0 s 1.8 VDD 3.6 V 1.6 8.0 s INT 10 s KR00 to KR03 10 s 10 s low-level width RESET low-level width tRSL TCY vs. VDD (Main System Clock) 60 20 Cycle time TCY [ s] 10 Guaranteed operation range 2.0 1.0 0.5 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD (V) User's Manual U16995EJ2V0UD 201 CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) AC Timing Measurement Points (Excluding X1, XT1 Input) 0.8VDD 0.8VDD Point of measurement 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) X1 input VIL3 (MAX.) 1/fXT tXTL tXTH VIH4 (MIN.) XT1 input VIL4 (MAX.) Interrupt Input Timing tINTL tINTH INT Key Return Input Timing tKRIL KR00 to KR03 RESET Input Timing tRSL RESET 202 User's Manual U16995EJ2V0UD CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) LCD Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V, VLC0 = 1.8 to 5.5 V) Parameter LCD drive voltage Symbol VLCD Conditions VAON0 Note 1 =1 VAON0 Note 1 =0 MIN. MAX. Unit 1.8 VLC0 V 2.7 VLC0 V 200 k LCD division resistor RLCD LCD output voltage VODC IO = 5 A 1/3 bias 0 0.2 V VODS IO = 1 A 1/3 bias 0 0.2 V differential Note 2 Note 2 100 (common) LCD output voltage differential 50 TYP. (segment) Notes 1. Bit 6 of LCD display mode register 0 (LCDM0). 2. The voltage differential is the difference between the output voltage and the ideal value of the segment and common signal outputs. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C, VDD = 1.8 to 3.6 V) Parameter Data retention supply voltage Low voltage detection (POC) Symbol Conditions MIN. VDDDR TYP. 1.8 Note 1 1.9 MAX. Unit 3.6 V 2.0 V 100 ms VPOC Response time: 2 ms 1.8 Supply voltage rise time tPth VDD : 0 V 1.8 V 0.01 Release signal set time tSREL STOP released by RESET Oscillation stabilization wait tWAIT Canceled by RESET pin or POC Note 3 s Canceled by interrupt request Note 4 s voltage time s 10 Note 2 Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. 2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid unstable operation at the start of oscillation. Program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed. 3. PD78F9328 is fixed to 215/fX. In mask ROM versions, 215/fX or 217/fX is selected by a mask option (refer to CHAPTER 16 MASK OPTIONS). 4. Selection of 212/fX, 215/fX, and 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS) (refer to 13.2 Register Controlling Standby Function). Remark fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD 203 CHAPTER 18 ELECTRICAL SPECIFICATIONS (PD179322, 179322A, 179324, 179324A, 179326, AND 179327) Data Retention Timing Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT 204 User's Manual U16995EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) Absolute Maximum Ratings (TA = 25C) Parameter Symbol Supply voltage Ratings Unit VDD -0.3 to +6.5 V VLC0 -0.3 to +6.5 V VPP Input voltage Conditions -0.3 to +10.5 Note 1 Note 2 -0.3 to VDD + 0.3 VI Output voltage VO1 Note 2 -0.3 to VDD + 0.3 P00 to P03, P10, P11, P20 to P22, V V V P40 to P43, P60, P61 VO2 Note 2 -0.3 to VLC0 + 0.3 COM0 to COM3, S0 to S16, V P80/S22 to P85/S17, S23 Output current, high IOH Output current, low IOL Operating ambient temperature TA Pin P60/TO40 -30 mA Per pin (except P60/TO40) -10 mA Total for all pins (except P60/TO40) -30 mA Per pin 30 mA Total for all pins 80 mA -40 to +85 C 10 to 40 C -40 to +125 C During normal operation During flash memory programming Storage temperature Tstg Flash memory version Notes 1. Make sure that the following conditions of the VPP voltage application timing are satisfied when the flash memory is written. * When supply voltage rises VPP must exceed VDD 10 s or more after VDD has reached the lower-limit value (1.8 V) of the operating voltage range (a in the figure below). * When supply voltage falls VDD must be lowered 10 s or more after VPP falls below the lower-limit value (1.8 V) of the range of VDD (b in the figure below). VDD 1.8 V 0V a b VPP 1.8 V 0V 2. 6.5 V or less Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U16995EJ2V0UD 205 CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) Main System Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Ceramic Recommended Circuit X2 X1 resonator C2 Crystal X2 External clock X1 Conditions Oscillation frequency Note 1 (fX) MIN. 1.0 Oscillation After VDD has reached the Note 2 stabilization time oscillation voltage range MIN. C1 X1 resonator C2 Parameter Oscillation Note 1 frequency 1.0 Oscillation 4.5 VDD 5.5 V Note 2 stabilization time 1.8 VDD 5.5 V C1 X2 TYP. MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms 30 ms X1 input frequency Note 1 (fX) 1.0 5.0 MHz X1 input high-/low- 85 500 ns level width (tXH, tXL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Use the resonator to stabilize oscillation within the oscillation wait time. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 206 User's Manual U16995EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) Recommended Oscillation Circuit Constants Ceramic oscillator (TA = -40 to +85C) (flash memory version) Manufacturer Part Number Frequency (MHz) Murata Mfg. (standard product) Note Recommended Circuit Oscillation Voltage Constant (pF) Range (VDD) C1 C2 MIN. MAX. CSBLA1M00J58-B0 1.0 100 100 2.1 5.5 CSTCC2M00G56-R0 2.0 - - 1.8 5.5 Rd = 3.3 k With internal capacitor 4.0 CSTCR4M00G53-R0 Remark CSTLS4M00G53-B0 4.194 CSTCR4M19G53-R0 CSTLS4M19G53-B0 4.915 CSTCR4M91G53-R0 CSTLS4M91G53-B0 CSTCR5M00G53-R0 5.0 CSTLS5M00G53-B0 TDK FCR4.0MC5 Kyocera 4.0 FCR5.0MC5 5.0 PBRC4.00HR 4.0 PBRC4.19HR 4.19 PBRC4.91HR 4.91 PBRC5.00HR 5.0 - - 2.2 5.5 With internal capacitor - - 1.8 5.5 With internal capacitor Note When using the CSBLA1M00J58-B0 of Murata Mfg. as the ceramic oscillator, a limiting resistor (Rd = 3.3 k) is necessary (refer to the figure below). The limiting resistor is not necessary when other recommended oscillators are used. X1 X2 CSBLA1M00J58-B0 C1 Caution Rd C2 The oscillator constant is a reference value based on evaluation under a specific environment by the resonator manufacturer. If optimization of oscillator characteristics is necessary in the actual application, apply to the resonator manufacturer for evaluation on the implementation circuit. The oscillation voltage and oscillation frequency indicate only oscillator characteristics. Use the PD78F9328 so that the internal operating conditions are within the specifications of the DC and AC characteristics. User's Manual U16995EJ2V0UD 207 CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Resonator Crystal Recommended Circuit XT1 C3 External XT2 R resonator XT1 C4 XT2 clock Parameter Conditions Oscillation frequency Note 1 (fXT) MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s 10 s Oscillation 4.5 VDD 5.5 V Note 2 stabilization time 1.8 VDD 5.5 V XT1 input frequency Note 1 (fXT) 32 35 kHz XT1 input high-/low- 14.3 15.6 s level width (tXTH, tXTL) Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a resonator to stabilize oscillation during the oscillation wait time. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. 208 User's Manual U16995EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/2) Parameter Output current, low Output current, high Symbol IOL IOH Conditions MAX. Unit Per pin 10 mA Total for all pins 80 mA Per pin (except P60/TO40) -1 mA -24 mA -15 mA P60/TO40 VDD = 3.0 V, VOH = 2.0 V MIN. -7 Total for all pins (except P60/TO40) Input voltage, high VIH1 VIH2 Input voltage, low -15 P00 to P03, P10, P11, 2.7 VDD 5.5 V 0.7VDD VDD V P60, P80 to P85 1.8 VDD 5.5 V 0.9VDD VDD V RESET, P20 to P22, P40 to 2.7 VDD 5.5 V 0.8VDD VDD V P43, P61 1.8 VDD 5.5 V 0.9VDD VDD V VIH3 X1, X2 VDD - 0.1 VDD V VIH4 XT1, XT2 VDD - 0.1 VDD V VIL1 P00 to P03, P10, P11, 2.7 VDD 5.5 V 0 0.3VDD V P60, P80 to P85 1.8 VDD 5.5 V 0 0.1VDD V RESET, P20 to P22, P40 2.7 VDD 5.5 V 0 0.2VDD V to P43, P61 1.8 VDD 5.5 V 0 0.1VDD V VIL2 Output voltage, high TYP. VIL3 X1, X2 0 0.1 V VIL4 XT1, XT2 0 0.1 V VOH11 VOH12 P00 to P03, P10, P11, 1.8 VDD 5.5 V, P20 to P22, P40 to P43, IOH = -100 A P61 1.8 VDD 5.5 V, VDD - 0.5 V VDD - 0.7 V VDD - 0.5 V VDD - 0.7 V VLC0 - 0.5 V VLC0 - 0.7 V IOH = -500 A VOH21 1.8 VDD 5.5 V, P60/TO40 IOH = -400 A 1.8 VDD 5.5 V, VOH22 IOH = -2 mA VOH31 P80/S22 to P85/S17 1.8 VDD 5.5 V, IOH = -100 A 1.8 VDD 5.5 V, VOH32 IOH = -500 A Output voltage, low VOL11 VOL12 P00 to P03, P10, P11, 1.8 VDD 5.5 V, P20 to P22, P40 to P43, IOL = 400 A P60, P61 1.8 VDD 5.5 V, 0.5 V 0.7 V 0.5 V 0.7 V IOL = 2 mA VOL21 P80/S22 to P85/S17 1.8 VLC0 5.5 V, IOL = 400 A VOL22 1.8 VLC0 5.5 V, IOL = 2 mA Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. User's Manual U16995EJ2V0UD 209 CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/2) Parameter Input leakage current, Symbol ILIH1 Conditions VIN = VDD MIN. TYP. MAX. Unit 3 A X1, X2, XT1, XT2 20 A P00 to P03, P10, -3 A -20 A 100 200 k 5.0 15.0 mA VDD = 3.3 V 2.0 5.0 mA VDD = 5.5 V 1.2 3.6 mA VDD = 3.3 V 0.5 1.5 mA VDD = 5.5 V 25 70 A VDD = 3.3 V 10 35 A VDD = 5.5 V 2 20 A VDD = 3.3 V 1 10 A P00 to P03, P10, high P11, P20 to P22, P40 to P43, P60, P61, RESET, P80 to P85 ILIH2 Input leakage current, ILIL1 VIN = 0 V low P11, P20 to P22, P40 to P43, P60, P61, RESET, P80 to P85 X1, X2, XT1, XT2 ILIL2 Software pull-up R1 VIN = 0 V P00 to P03, P10, resistors 50 P11, P20 to P22, P40 to P43 Supply current Note 1 IDD1 5.0 MHz crystal oscillation operating mode IDD2 5.0 MHz crystal oscillation HALT mode IDD3 IDD4 32.768 kHz crystal Note 4 oscillation HALT mode 32.768 kHz crystal oscillation stopped STOP mode Note 2 VDD = 5.5 V Note 3 Notes 1. Current flowing through ports (including current flowing through on-chip pull-up resistors and from VLC0 to VSS) is not included. 2. High-speed mode operation (when the processor clock control register (PCC) is set to 00H). 3. Low-speed mode operation (when PCC is set to 02H) 4. When the main system clock operation is stopped. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins. 210 User's Manual U16995EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Symbol Cycle time TCY (Min. instruction execution time) Interrupt input tINTH, high-/low-level width tINTL Key return pin tKRIL Conditions MIN. TYP. MAX. Unit 2.7 VDD 5.5 V 0.4 8.0 s 1.8 VDD 5.5 V 1.6 8.0 s INT 10 s KR00 to KR03 10 s 10 s low-level width RESET low-level width tRSL TCY vs. VDD (Main System Clock) 60 20 Cycle time TCY [ s] 10 Guaranteed operation range 2.0 1.0 0.5 0.4 0.1 1 2 3 4 5 6 Supply voltage VDD (V) User's Manual U16995EJ2V0UD 211 CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) (2) Serial Interface 10 (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output) Parameter SCK10 cycle time SCK10 high/low-level width Symbol tKCY1 tKH1, tKL1 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to tSIK1 tKSI1 tKSO1 Conditions MIN. TYP. MAX. Unit VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V tKCY1/2-50 ns VDD = 1.8 to 5.5 V tKCY1/2-150 ns VDD = 2.7 to 5.5 V 150 ns VDD = 1.8 to 5.5 V 500 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 800 ns R = 1 k, VDD = 2.7 to 5.5 V 0 250 ns VDD = 1.8 to 5.5 V 250 1000 ns MAX. Unit Note SO10 output C = 100 pF Note R and C are the load resistance and load capacitance of the SO10 output line. (a) 3-wire serial I/O mode (external clock input) Parameter SCK10 cycle time SCK10 high/low-level width Symbol tKCY2 tKH2, tKL2 SI10 setup time (to SCK10) SI10 hold time (from SCK10) Delay time from SCK10 to SO10 output tSIK2 tKSI2 tKSO2 Conditions MIN. VDD = 2.7 to 5.5 V 800 ns VDD = 1.8 to 5.5 V 3200 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 1600 ns VDD = 2.7 to 5.5 V 100 ns VDD = 1.8 to 5.5 V 150 ns VDD = 2.7 to 5.5 V 400 ns VDD = 1.8 to 5.5 V 600 ns R = 1 k, VDD = 2.7 to 5.5 V 0 300 ns VDD = 1.8 to 5.5 V 250 1000 ns Note C = 100 pF Note R and C are the load resistance and load capacitance of the SO10 output line. 212 TYP. User's Manual U16995EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) AC Timing Measurement Points (Excluding X1, XT1 Input) 0.8VDD 0.8VDD Point of measurement 0.2VDD 0.2VDD Clock Timing 1/fX tXL tXH VIH3 (MIN.) X1 input VIL3 (MAX.) 1/fXT tXTL tXTH VIH4 (MIN.) XT1 input VIL4 (MAX.) Interrupt Input Timing tINTL tINTH INT Key Return Input Timing tKRIL KR00 to KR03 RESET Input Timing tRSL RESET User's Manual U16995EJ2V0UD 213 CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) Serial Transfer Timing 3-wire serial I/O mode: tKCYn tKLn tKHn SCK10 tSIKn SI10 tKSIn Input data tKSOn SO10 Output data Remark n = 1, 2 214 User's Manual U16995EJ2V0UD CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) LCD Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V, VLC0 = 1.8 to 5.5 V) Parameter LCD drive voltage Symbol VLCD Conditions VAON0 Note 1 =1 VAON0 Note 1 =0 MIN. MAX. Unit 1.8 VLC0 V 2.7 VLC0 V 200 k LCD division resistor RLCD LCD output voltage VODC IO = 5 A 1/3 bias 0 0.2 V VODS IO = 1 A 1/3 bias 0 0.2 V differential Note 2 Note 2 100 (common) LCD output voltage differential 50 TYP. (segment) Notes 1. Bit 6 of LCD display mode register 0 (LCDM0). 2. The voltage differential is the difference between the output voltage and the ideal value of the segment and common signal outputs. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) Parameter Data retention supply voltage Low voltage detection (POC) Symbol Conditions MIN. VDDDR TYP. 1.8 Note 1 VPOC Response time: 2 ms 1.8 Supply voltage rise time tPth VDD : 0 V 1.8 V 0.01 Release signal set time tSREL STOP released by RESET 1.9 MAX. Unit 5.5 V 2.0 V 100 ms voltage Oscillation stabilization wait time tWAIT Canceled by RESET pin or POC s 10 15 2 /fX s Note 3 s Note 2 Canceled by interrupt request Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the time until operation stabilizes after the shift from the operation stopped state to the operating state. 2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid unstable operation at the start of oscillation. Program operation does not start until both the oscillation stabilization time and the time until oscillation starts have elapsed. 3. Selection of 212/fX, 215/fX, and 217/fX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS) (refer to 13.2 Register Controlling Standby Function). Remark fX: Main system clock oscillation frequency User's Manual U16995EJ2V0UD 215 CHAPTER 19 ELECTRICAL SPECIFICATIONS (PD78F9328) Data Retention Timing Internal reset operation HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT HALT mode STOP mode Operating mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (interrupt request) tWAIT Writing and Erasing Characteristics (TA = 10 to 40C, VDD = 1.8 to 5.5 V) Parameter Write operation frequency Symbol fX MIN. MAX. Unit VDD = 2.7 to 5.5 V 1.0 5 MHz VDD = 1.8 to 5.5 V 1.0 1.25 MHz IDDW When VPP supply voltage = VPP1 (at 5.0 MHz operation) 7 mA Note IPPW When VPP supply voltage = VPP1 13 mA IDDE When VPP supply voltage = VPP1 (at 5.0 MHz operation) 7 mA IPPE When VPP supply voltage = VPP1 100 mA 1 s Write current (VPP pin) Erase current (VDD pin) Note Note Erase current (VPP pin) Unit erase time ter Total erase time tera Number of overwrites 0.5 1 Erase and write is considered as 1 cycle VPP0 VPP1 Normal operation Flash memory programming Note Excludes current flowing through ports (including on-chip pull-up resistors) 216 TYP. Note Write current (VDD pin) VPP supply voltage Conditions User's Manual U16995EJ2V0UD 0 9.7 10.0 20 s 20 Times 0.2VDD V 10.3 V CHAPTER 20 PACKAGE DRAWING 52-PIN PLASTIC LQFP (10x10) A B detail of lead end 27 26 39 40 S P C T D R 52 1 L 14 13 U Q F J G I H M K M ITEM A B N S S MILLIMETERS 12.00.2 10.00.2 C 10.00.2 D 12.00.2 F 1.1 G 1.1 H I 0.320.06 0.13 J 0.65 (T.P.) K 1.00.2 L 0.5 M 0.17 +0.03 -0.05 N 0.10 P 1.4 Q 0.10.05 R 3 +4 -3 S 1.50.1 T U 0.25 0.60.15 S52GB-65-8ET-2 User's Manual U16995EJ2V0UD 217 CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS The PD179322, 179322A, 179324, 179324A, 179326, 179327, and 78F9328 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 21-1. Surface Mounting Type Soldering Conditions (1/2) (1) PD179322GB-xxx-8ET, 179322AGB-xxx-8ET Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Twice or less IR35-00-2 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: Twice or less VP15-00-2 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 350C max. Time: 3 seconds max. (per pin row) -- (2) PD179324GB-xxx -8ET, 179324AGB-xxx-8ET, 179326GB-xxx -8ET, 179327GB-xxx -8ET Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or Note higher), Count: Twice or less, Exposure limit: 3 days (after that, prebake at 125C for 10 hours) IR35-103-2 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or Note higher), Count: Twice or less, Exposure limit: 3 days (after that, prebake at 125C for 10 hours) VP15-103-2 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Note Exposure limit: 3 days (after that, prebake at 125C for 10 hours) WS60-103-1 Partial heating Pin temperature: 350C max. Time: 3 seconds max. (per pin row) -- Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution 218 Do not use different soldering methods together (except for partial heating). User's Manual U16995EJ2V0UD CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS Table 21-1. Surface Mounting Type Soldering Conditions (2/2) (3) PD78F9328GB-8ET Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235C, Time: 30 seconds max. (at 210C or Note higher), Count: Twice or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) IR35-107-2 VPS Package peak temperature: 215C, Time: 40 seconds max. (at 200C or Note higher), Count: Twice or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) VP15-107-2 Wave soldering Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature), Note Exposure limit: 7 days (after that, prebake at 125C for 10 hours) WS60-107-1 Partial heating Pin temperature: 350C max. Time: 3 seconds max. (per pin row) -- (4) PD179322GB-8ET-A, 179322AGB-8ET-A, 179324GB-8ET-A, 179324AGB-8ET-A, 179326GB-8ET-A, 179327GB-8ET-A, 78F9328GB-8ET-A Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 260C, Time: 60 seconds max. (at 220C or Note (after that, higher), Count: Three times or less, Exposure limit: 7 days IR60-207-3 prebake at 125C for 20 to 72 hours) Wave soldering For details, contact an NEC Electronics sales representative. - Partial heating Pin temperature: 350C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Remark Products that have the part numbers suffixed by "-A" are lead-free products. User's Manual U16995EJ2V0UD 219 APPENDIX A DEVELOPMENT TOOLS The following development tools are available for development of systems using the PD179327 Subseries. Figure A-1 shows development tools. * Support of PC98-NX series Unless specified otherwise, the products supported by IBM PC/ATTM compatibles can be used in the PC98-NX series. When using the PC98-NX Series, refer to the explanation of IBM PC/AT compatibles. * WindowsTM Unless specified otherwise, "Windows" indicates the following operating systems. * Windows 98 * Windows 2000 * Windows NTTM Ver.4.0 * Windows XP 220 User's Manual U16995EJ2V0UD APPENDIX A DEVELOPMENT TOOLS Figure A-1. Development Tools Software package * Software package Language processing software Software for debugging * Assembler package * C compiler package * Device file * C library source fileNote 1 * Integrated debugger * System simulator Control software * Project manager (Windows version only)Note 2 Host machine (PC or EWS) Interface adapter Power supply unit Flash memory writing tools In-circuit emulator Flash programmer Emulation board Flash memory writing adapter Flash memory Emulation probe Conversion socket or conversion adapter Target system Notes 1. The C library source file is not included in the software package. 2. The project manager is included in the assembler package. The project manager is used only for Windows. User's Manual U16995EJ2V0UD 221 APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0S Software package Various software tools for 78K/0S Series development are integrated into one package. The following tools are included. RA78K0S, CC78K0S, ID78K0S-NS, SM78K0S, various device files Part number: SxxxxSP78K0S xxxx in the part number differs depending on the operating system to be used. Remark SxxxxSP78K0S xxxx AB17 BB17 Host Machine PC-9800 series, IBM PC/AT compatibles OS Japanese Windows Supply Medium CD-ROM English Windows A.2 Language Processing Software RA78K0S Program that converts program written in mnemonic into object codes that can be executed Assembler package by microcontroller. In addition, automatic functions to generate symbol tables and optimize branch instructions are also provided. Used in combination with a device file (DF179327) (sold separately). <Caution when used in PC environment> The assembler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the assembler package). Part number: SxxxxRA78K0S CC78K0S Program that converts program written in C language into object codes that can be executed C compiler package by microcontroller. Used in combination with an assembler package (RA78K0S) and device file (DF179327) (both sold separately). <Caution when used in PC environment> The C compiler package is a DOS-based application but may be used in the Windows environment by using the Project Manager of Windows (included in the assembler package). Part number: SxxxxCC78K0S DF179327 Note1 File containing the information specific to the device. Device file Used in combination with the RA78K0S, CC78K0S, and SM78K0S (sold separately). Part number: SxxxxDF179327 CC78K0S-L Note2 C library source file Source file of functions for generating object library included in C compiler package. Necessary for changing object library included in C compiler package according to customer's specifications. Since this is a source file, its working environment does not depend on any particular operating system. Part number: SxxxxCC78K0S-L Notes 1. DF179327 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. 2. CC78K0S-L is not included in the software package (SP78K0S). 222 User's Manual U16995EJ2V0UD APPENDIX A DEVELOPMENT TOOLS Remark xxxx in the part number differs depending on the host machine and operating system to be used. SxxxxRA78K0S SxxxxCC78K0S xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT compatibles OS Japanese Windows Supply Medium 3.5" 2HD FD English Windows AB17 Japanese Windows BB17 English Windows 3P17 HP9000 series 700TM HP-UXTM (Rel.10.10) 3K17 SPARCstationTM SunOSTM (Rel.4.1.4), CD-ROM SolarisTM (Rel.2.5.1) SxxxxDF179327 SxxxxCC78K0S-L xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT compatibles OS Japanese Windows Supply Medium 3.5" 2HD FD English Windows 3P16 HP9000 series 700 HP-UX (Rel.10.10) DAT 3K13 SPARCstation SunOS (Rel.4.1.4), 3.5" 2HD FD Solaris (Rel.2.5.1) 3K15 1/4" CGMT A.3 Control Software Project manager Control software designed so that the user program can be efficiently developed in the Windows environment. A series of jobs for user program development including starting the editor, building, and starting the debugger, can be executed on the project manager. <Caution> The project manager is included in the assembler package (RA78K0S). It cannot be used in an environment other than Windows. A.4 Flash Memory Writing Tools Flashpro IV Dedicated flash programmer for microcontrollers incorporating flash memory (Part No. FL-PR4, PG-FP4) Flash programmer FA-52GB-8ET Adapter for writing to flash memory and connected to Flashpro III or Flashpro IV. Flash memory writing adapter FA-52GB-8ET: for 52-pin plastic LQFP (GB-8ET type) Remark The FL-PR4, and FA-52GB-8ET are products made by Naito Densei Machida Mfg. Co., Ltd. (TEL +8145-475-4191). User's Manual U16995EJ2V0UD 223 APPENDIX A DEVELOPMENT TOOLS A.5 Debugging Tools (Hardware) IE-78K0S-NS In-circuit emulator for debugging hardware and software of application system using 78K/0S In-circuit emulator Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter, emulation probe, and interface adapter for connecting the host machine. IE-78K0S-NS-A A coverage function has been added to the IE-78K0S-NS function and the debug function has In-circuit emulator been further enhanced, enhancing the tracer and timer functions. IE-70000-MC-PS-B Adapter for supplying power from AC 100 to 240 V outlet. AC adapter IE-70000-98-IF-C Adapter necessary when using PC-9800 series PC (except notebook type) as host machine Interface adapter (C bus supported) IE-70000-CD-IF-A PC card and interface cable necessary when using notebook PC as host machine (PCMCIA PC card interface socket supported) IE-70000-PC-IF-C Interface adapter necessary when using IBM PC/AT compatible as host machine (ISA bus Interface adapter supported) IE-70000-PCI-IF-A Adapter necessary when using personal computer incorporating PCI bus as host machine Interface adapter IE-789468-NS-EM1 Board for emulating peripheral hardware specific to device. Used in combination with in-circuit Emulation board emulator. NP-H52GB-TQ Probe for connecting in-circuit emulator and target system. Emulation probe Used in combination with TGB-052SBP. TGB-052SBP Conversion adapter to connect NP-H52GB-TQ and target system board on which 52-pin plastic Conversion LQFP (GB-8ET type) can be mounted adapter Remarks 1. The NP-H52GB-TQ is a product made by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-4754191). 2. The TGB-052SBP is a product made by TOKYO ELETECH CORPORATION. For further information, contact: Daimaru Kogyo, Ltd. Tokyo Electronics Department (TEL +81-3-3820-7112) Osaka Electronics Department (TEL +81-6-6244-6672) 224 User's Manual U16995EJ2V0UD APPENDIX A DEVELOPMENT TOOLS A.6 Debugging Tools (Software) ID78K0S-NS A debugger supporting in-circuit emulators for the 78K/0S Series: IE-78K0S-NS and IE- Integrated debugger 78K0S-NS-A. The ID78K0S-NS is Windows-based software. This program enhances the debugging functions for C language. Therefore, it can display the trace results corresponding to the source program by using the window integration function that links the source program, disassembled display, and memory display with the trace results. Use this program in combination with a device file (DF179327) (sold separately). Part number: SxxxxID78K0S-NS SM78K0S A system simulator for the 78K/0S Series. The SM78K0S is Windows-based software. System simulator C-source-level or assembler level debugging is possible while simulating the operation of the target system on the host machine. Using the SM78K0S enables logical and performance verification of an application independently of the hardware development. This enhances development efficiency and improves software quality. Use this program in combination with a device file (DF179327) (sold separately). Part number: SxxxxSM78K0S DF179327 Note File containing information specific to the device. Device file Use this file in combination with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S (sold separately). Part number: SxxxxDF179327 Note DF179327 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, and SM78K0S. Remark xxxx in the part number differs depending on the operating system to be used and the supply medium. SxxxxID78K0S-NS SxxxxSM78K0S xxxx AB13 BB13 Host Machine PC-9800 series, IBM PC/AT compatibles OS Japanese Windows Supply Medium 3.5" 2HD FD English Windows AB17 Japanese Windows BB17 English Windows User's Manual U16995EJ2V0UD CD-ROM 225 APPENDIX A DEVELOPMENT TOOLS A.7 Cautions when designing target system The following shows the conditions when connecting the emulation probe to the conversion adapter. Design the system considering shapes and other conditions of the components to be mounted on the target system and be sure to follow the configuration below. Figure A-2. Condition Diagram of Connection to Target System In-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A Target system Emulation board IE-789468-NS-EM1 When CN1 is connected: 370 mm CN1 CN2 Emulation probe NP-H52GB-TQ Conversion adapter: TGB-052SBP Connect to CN1 if PD179327 Subseries is used. Emulation probe NP-H52GB-TQ Emulation board IE-789468-NS-EM1 10 mm 43 mm 45 mm 11 mm 23 mm Conversion adapter: TGB-052SBP 14.45 mm 14.45 mm No.1 pin 53 mm Target system 226 User's Manual U16995EJ2V0UD 45 mm APPENDIX B REGISTER INDEX B.1 Register Index (Alphabetic Order of Register Name) [C] Carrier generator output control register 40 (TCA40) ............................................................................................. 93 [E] 8-bit compare register 30 (CR30) ........................................................................................................................... 88 8-bit compare register 40 (CR40) ........................................................................................................................... 88 8-bit H width compare register 40 (CRH40)............................................................................................................ 88 8-bit timer counter 30 (TM30) ................................................................................................................................. 89 8-bit timer counter 40 (TM40) ................................................................................................................................. 89 8-bit timer mode control register 30 (TMC30)......................................................................................................... 91 8-bit timer mode control register 40 (TMC40)......................................................................................................... 92 External interrupt mode register 0 (INTM0) .......................................................................................................... 156 [I] Interrupt mask flag register 0 (MK0) ..................................................................................................................... 155 Interrupt request flag register 0 (IF0).................................................................................................................... 154 [K] Key return mode register 00 (KRM00).................................................................................................................. 157 [L] LCD clock control register 0 (LCDC0) .................................................................................................................. 136 LCD display mode register 0 (LCDM0)................................................................................................................. 134 [O] Oscillation stabilization time selection register (OSTS) ........................................................................................ 165 [P] Port 0 (P0).............................................................................................................................................................. 59 Port 1 (P1).............................................................................................................................................................. 60 Port 2 (P2).............................................................................................................................................................. 61 Port 4 (P4).............................................................................................................................................................. 64 Port 6 (P6).............................................................................................................................................................. 65 Port 8 (P8).............................................................................................................................................................. 67 Port function register 8 (PF8) ......................................................................................................................... 70, 137 Port mode register 0 (PM0) .................................................................................................................................... 68 Port mode register 1 (PM1) .................................................................................................................................... 68 Port mode register 2 (PM2) ............................................................................................................................ 68, 128 Port mode register 4 (PM4) .................................................................................................................................... 68 Port mode register 6 (PM6) .............................................................................................................................. 68, 94 Port mode register 8 (PM8) .................................................................................................................................... 68 User's Manual U16995EJ2V0UD 227 APPENDIX B REGISTER INDEX Power-on-clear register 1 (POCF1) ......................................................................................................................150 Processor clock control register (PCC)...................................................................................................................75 Pull-up resistor option register 0 (PU0)...................................................................................................................69 Pull-up resistor option register B2 (PUB2) ..............................................................................................................70 [S] Serial operation mode register 10 (CSIM10) ........................................................................................................127 Subclock control register (CSS)..............................................................................................................................76 Suboscillation mode register (SCKM).....................................................................................................................76 [T] Transmit/receive shift register 10 (SIO10) ............................................................................................................125 [W] Watchdog timer clock selection register (TCL2) ...................................................................................................120 Watchdog timer mode register (WDTM) ...............................................................................................................121 Watch timer mode control register (WTM)............................................................................................................115 228 User's Manual U16995EJ2V0UD APPENDIX B REGISTER INDEX B.2 Register Index (Alphabetic Order of Register Symbol) [C] CR30: 8-bit compare register 30....................................................................................................................... 88 CR40: 8-bit compare register 40....................................................................................................................... 88 CRH40: 8-bit H width compare register 40.......................................................................................................... 88 CSIM10: Serial operation mode register 10........................................................................................................ 127 CSS: Subclock control register ....................................................................................................................... 76 [I] IF0: Interrupt request flag register 0 ........................................................................................................... 154 INTM0: External interrupt mode register 0 ....................................................................................................... 156 [K] KRM00: Key return mode register 00 ................................................................................................................ 157 [L] LCDC0: LCD clock control register 0 ................................................................................................................ 136 LCDM0: LCD display mode register 0 ............................................................................................................... 134 [M] MK0: Interrupt mask flag register 0............................................................................................................... 155 [O] OSTS: Oscillation stabilization time selection register..................................................................................... 165 [P] P0: Port 0..................................................................................................................................................... 59 P1: Port 1..................................................................................................................................................... 60 P2: Port 2..................................................................................................................................................... 61 P4: Port 4..................................................................................................................................................... 64 P6: Port 6..................................................................................................................................................... 65 P8: Port 8..................................................................................................................................................... 67 PCC: Processor clock control register............................................................................................................. 75 PF8: Port function register 8 .................................................................................................................. 70, 137 PM0: Port mode register 0 .............................................................................................................................. 68 PM1: Port mode register 1 .............................................................................................................................. 68 PM2: Port mode register 2 ...................................................................................................................... 68, 128 PM4: Port mode register 4 .............................................................................................................................. 68 PM6: Port mode register 6 ........................................................................................................................ 68, 94 PM8: Port mode register 8 .............................................................................................................................. 68 POCF1: Power-on-clear register 1 .................................................................................................................... 150 PU0: Pull-up resistor option register 0 ............................................................................................................ 69 PUB2: Pull-up resistor option register B2.......................................................................................................... 70 [S] SCKM: Suboscillation mode register.................................................................................................................. 76 SIO10: Transmit/receive shift register 10......................................................................................................... 125 User's Manual U16995EJ2V0UD 229 APPENDIX B REGISTER INDEX [T] TCA40: Carrier generator output control register 40...........................................................................................93 TCL2: Watchdog timer clock selection register ..............................................................................................120 TM30: 8-bit timer counter 30.............................................................................................................................89 TM40: 8-bit timer counter 40.............................................................................................................................89 TMC30: 8-bit timer mode control register 30 .......................................................................................................91 TMC40: 8-bit timer mode control register 40 .......................................................................................................92 [W] WDTM: Watchdog timer mode register.............................................................................................................121 WTM: Watch timer mode control register .......................................................................................................115 230 User's Manual U16995EJ2V0UD APPENDIX C REVISION HISTORY C.1 Major Revisions in This Edition Page <R> Description Throughout Addition of PD179322A and 179324A p. 231 Addition of C.2 Revision History of Preceding Editions C.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. Page Description p. 15 Addition of lead-free products to 1.3 Ordering Information p. 218 Addition of lead-free products to CHAPTER 21 RECOMMENDED SOLDERING CONDITIONS User's Manual U16995EJ2V0UD 231 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China TEL: 010-8235-1155 http://www.cn.necel.com/ Hanover Office Podbielski Strasse 166 B 30177 Hanover Tel: 0 511 33 40 2-0 NEC Electronics Shanghai Ltd. Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-5888-5400 http://www.cn.necel.com/ Munich Office Werner-Eckert-Strasse 9 81829 Munchen Tel: 0 89 92 10 03-0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel: 0 711 99 01 0-0 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Succursale Francaise 9, rue Paul Dautier, B.P. 52180 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 http://www.hk.necel.com/ Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 http://www.sg.necel.com/ Tyskland Filial Taby Centrum Entrance S (7th floor) 18322 Taby, Sweden Tel: 08 638 72 00 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Limburglaan 5 5616 HR Eindhoven The Netherlands Tel: 040 265 40 10 G05.12A