S912ZVML32F1WKH - NXP SEMICONDUCTORS

S12 MagniV

Microcontrollers

nxp.com

MC9S12ZVM-Family

Reference Manual and Datasheet

Rev. 2.11

28 OCT 2016

MC9S12ZVMRM

NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in NXP

data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including

“typicals,” must be validated for each customer application by customer’s technical experts. NXP does not convey any license under its patent rights nor the

rights of others. NXP Semiconductors products are not designed, intended, or authorized for use as components in systems intended for surgical implant

into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the NXP Semiconductors product

could create a situation where personal injury or death may occur. Should Buyer purchase or use NXP Semiconductors products for any such unintended

or unauthorized application, Buyer shall indemnify and hold NXP Semiconductors and its officers, employees, subsidiaries, affiliates, and distributors

harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or

death associated with such unintended or unauthorized use, even if such claim alleges that NXP Semiconductors was negligent regarding the design or

manufacture of the part.

The ZVMC256, ZVML31, ZVM32 and ZVM16 devices are targeted for safety releva nt systems and have

been developed using an ISO26262 compliant development system under the NXP SafeAssure program.

For details of device usage in safety relevant systems refer to the MC9S12ZVMB Safety Manual.

The document revision on the Internet is the most current. To verify this is the latest revision, refer to:

nxp.com.

This document contains information for all modules except the CPU. For CPU information please refer to

the CPU S12Z Reference Manual. This revision history table summarizes changes to this document. The

individual module sections contain revision history tables with more detailed information.

NOTE

This reference manual documents the S12ZVM-Family.

It contains a superset of features within the family.

Some module versions differ from one part to another within the family.

Section 1.2.1 MC9S12ZVM-Family Member Comparison provides support to access the

correct information for a particular part within the family.

MC9S12ZVM Family Reference Manual Rev . 2.11

NXP Semiconductors 3

Table 0-1. Revision History

Date Revision Description

22 MAY2014 1.4 Updated family derivative table for S12ZVML32, S12ZVM32 and S12ZVM16 devices

Added 64KB, 32KB and 16KB derivative information to flash module chapter

Added pin routing options for S12ZVM32 and S12ZVM16 devices

Added HV Phy information for the S12ZVM32 and S12ZVM16 derivatives

Updated Part ID assignment table and ordering information for S12ZVM32 and S12ZVM16

Corrected PLL VCO maximum frequency specification

Changed VLVLSA maximum from 7V to 6.9V

Added electrical parameter for HD division ratio through the phase multiplexer

Corrected preferred VRL reference from VRL_1 to VRL_0

Included NVM timing parameters for the S12ZVM32 and S12ZVM16 devices

Added GDU S12ZVM32 and S12ZVM16 specific differences and electrical specifications

Added references to fWSTAT

Added VDDX short circuit fall back current and temperature/input dependency specs.

22 SEP 2014 1.5 Removed incorrect references to PACLK in TIM chapter

Improved clarity of routing options in PIM chapter.

Updated S12ZVM- Family derivative table.

Added 48LQFP thermal package parameters

Extended LINPHY specification range minimum to 5V

Updated BKGD pin I/O specification

Specified ADC accuracy for a range of VDDA and VREF.

20 MAR 2015 2.0 Added ZVMC256 information

Added mask set 2N95G information

Added more detailed PTU minimum trigger spacing description

Updated CPMU, PIM and GDU chapters for ZVMC256

Improved CPMU specification clarity (see CPMU revision history)

Removed electrical parameter classification

Added reset startup timing parameter

Updated BATS parameters

Extended BKGD VIL condition from 3.15V to 3.13V

Extended GDU operating range from 26V to 26.6V

Temperature sensor output at 150C changed from 2.25V to 2.33V.

Added GDU VBS current parameter

Updated package thermal information for ZVM32 and ZVM16 parts

Added VBG temperature and voltage dependency parameters

Added device stop current at 105C.

22 APR 2015 2.1 Updated Stop and Wait current parameter values (ISUPS, ISUPW)

Corrected 80LQFP-EP pin name from VSS2 to VSS1

Updated ZVMC256 VDDS regulator parameters.

Changed PL0 ESD specification

Minor corrections to PIM, PMF, SRAM and ADC chapters (see module revision histories)

27 APR 2015 2.2 Updated Stop current parameter values (ISUPS)

Updated LINPHY parameter range limit to 5.5V

Added more information about VDDS1, VDDS2, SNPS1, SNPS2 to CPMU chapter.

Reintroduced EPRES bit for GDU V4

Added 80LQFP-EP mechanical package information

MC9S12ZVM Family Reference Manual Rev. 2.11

4NXP Semiconductors

20 NOV 2015 2.3 Added devices to Part ID list Table 1-6

Added explanation of GSUF dependency on xN14N mask set Ta ble 1 -19

Minor corrections to reset source and interrupt vector tables Table 1-15

Added device level POR information Figure 1-8

Minor correction to PIM chapter

Added constraints to EXTCON, SCS2 and SCS1 bits in CPMU chapter

Added PMF version difference table Table 15 -3

Corrected footnotes and parameter spelling in GDU register summary

Noted GDU sense amplifier dependence on GFDE bit

Documented that flash option (FOPT) register can be written in special mode

Added pulsed absolute maximum rating for HSx pins Ta b le A-2

Extended VDDS1 and VDDS2 maximum ratings Tab l e A- 2

Added thermal resistance parameter values for 80LQFP-EP package

Added VREG configuration to Run/Wait/Stop current measurement configurationTa b le A - 16

Removed de-saturation thresholds from electrical spec. tables

Added footnote for GDU tdelon/tdeloff electrical parameters

Added max. and min. values for GDU HD signal division through phase mux.

Removed incorrect limit from BATS electrical parameter table headers

Extended CANPHY maximum ratings to 175°C

Updated SRAM_ECC chapter to cover ZVMC256

Minor correction to PMF chapter

Updated typical Stop IDD and Pseudo Stop IDD values for ZVMC256 based on validation data

Added ZVMC256 parameter for Stop IDD with CANPHY and API enabled Table A-19

Renamed bit GSLEWMOD to TDEL (GDU V6). Removed GSLEWMOD bit (GDU V5)

Noted temperature sensor slope is subject to further characterization

14 DEC 2015 2.4 Added T1IC0RR to PIM MODRR2 register

Updated temperature sensor electrical specification, Table B-1

Added GDU current sense amp unity bandwidth parameter Tab l e E -1, Table E- 2

Added GDU current sense input resistance footnote Ta ble E-1, Tabl e E - 2

14 JAN 2016 2.5 Clarified non production mask sets Table 1-4, Ta b l e 1-6

Updated ordering information in Appendix L

Changed RESET pin input pulse passed parameter minimum specification value.Table A-13

Replaced Freescale with NXP in logo and page footers

Added maximum value for GDU parameter VBSx current whilst high side inactive Tab l e E -2

07 MAR 2016 2.6 Added 3N95G mask set information Table 1-19, Ta bl e 1 - 4 , Table 1-6

Added list of ISO26262 compliant devices

Moved GDU mask set dependent features to device overview section Table 1- 1 9

Added new 64LQFP-EP package diagrams Ta b le K.2

Added minimum value for GDU parameter VBSx current whilst high side inactive Table E-2

Updated VCSAoff parameter limits for GDU V5 and GDU V6 Ta b le E-1, Tabl e E - 2

Added ADCCMD1[7:6] device dependencies in register listing Section M.13, Section M.14

Simplified GDU device dependencies in register listing Section M.15

Corrected High Temperature Interrupt spec. (cannot wake up from STOP) Tab l e 1 -1 6

Added footnote to Table A-14

ZVMC256: added typical Run/Wait IDD values, updated 85°C Stop IDD Table A-18, Table A-19

Added bootstrap diode resistance parameter Ta bl e E -2

Updated GDU boost coil current limit specification Table E-2, Table E-1

Reverted to original current sense amp. offset values Table E - 2 , Ta bl e E -1

Added package to mask set mapping table Table K-1

08 MAR 2016 2.7 Changed maximum value of VBSTOFF Tab l e E - 2 , Ta b l e E- 1

Updated 48LQFP-EP Mechanical Information Diagram Section K.1

Table 0-1. Revision History

Date Revision Description

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NXP Semiconductors 5

19 APR 2016 2.8 Added PAD pin leakage specification at 125C Table A- 1 2

Updated tHGON, tHGOFF parameter values Table E - 1

Specified VRH drop when using VDDS1 or VDDS2 as VRH on ZVMC256 Section C.1.1.5

Added min. and max. desaturation comparator filter times to electrical spec. Table E- 1

Updated 64LQFP-EP thermal parameters Table A-9, Table A-10

06 JUN 2016 2.9 Fixed corrupted symbol fonts Table A - 3 , Table A - 5

Corrected wrong IFR reference Section 20.3.2.10

Clarified PAD8 leakage better Tab l e A -12

Added ISUPR and ISUPW maximum values at TJ = 175°C for ZVMC256 Table A-18

Added Pseudo STOP maximum current for ZVMC256 Table A-20

Removed bandgap temperature dependency footnote, Table B- 1

Changed ZVMC256 SNPS monitor threshold min/max values Tabl e B - 2

Changed VLS current limit threshold to 112mA Table E-1, Table E-2

Removed desaturation comparator filter times from GDU chapter.

Added desaturation comparator levels to Tab l e E -1, Table E- 2

Added low side desaturation comparator functional range as footnote Table E- 1 , Ta b l e E-2

29 JUN 2016 2.10 Updated GDU VBS filter Figure 18-20

Removed incorrect reference to temperature sensor influencing GDU outputs Section 1.13.3.4

Changed Stop IDD (ISUPS) specifications for ZVMC256 Table A- 1 9

28 OCT 2016 2.11 Added IOC0 signal mapping to 48LQFP package Figure 1-6

Fixed corrupted symbol fonts in PIM chapter

Added diode to VDDC pin Figure 1-18

Updated Stop mode current ISUPS maximum values Tabl e A - 19

Updated tdelon, tdeloff values Table E-1

Table 0-1. Revision History

Date Revision Description

MC9S12ZVM Family Reference Manual Rev. 2.11

6NXP Semiconductors

MC9S12ZVM Family Reference Manual Rev . 2.11

NXP Semiconductors 7

Chapter 1

Device Overview MC9S12ZVM-Family

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.2.1 MC9S12ZVM-Family Member Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.2.2 Module Version Differences Within The S12ZVM Family . . . . . . . . . . . . . . . . . . . . . . . 27

1.2.3 Functional Differences Between Masksets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.3 Chip-Level Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.4 Module Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.4.1 S12Z Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1.4.2 Embedded Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.4.3 Clocks, Reset & Power Management Unit (CPMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.4.4 Main External Oscillator (XOSCLCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.5 Timer (TIM0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.6 Timer (TIM1) (ZVMC256 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.7 Pulse width Modulator with Fault protection (PMF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.8 Programmable Trigger Unit (PTU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

1.4.9 LIN physical layer transceiver (ZVML devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.4.10 Serial Communication Interface Module (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.4.11 Multi-Scalable Controller Area Network (MSCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

1.4.12 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.4.13 Analog-to-Digital Converter Module (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.4.14 Supply Voltage Sensor (BATS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.4.15 On-Chip Voltage Regulator system (VREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

1.4.16 Gate Drive Unit (GDU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.4.17 Current Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.4.18 High Voltage Physical Interface (ZVM32, ZVM16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.4.19 CAN Physical Layer Module (ZVMC256 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

1.4.20 Pulse Width Modulation Module (PWM) (ZVMC256 only) . . . . . . . . . . . . . . . . . . . . . 36

1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

1.6 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

1.6.1 Flash Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

1.6.2 Part ID Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

1.7 Signal Description and Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

1.7.1 Pin Assignment Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

1.7.2 Detailed External Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

1.7.3 Power Supply And Voltage Regulator Related Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

1.7.4 Package and Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

1.8 Internal Signal Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

1.8.1 ADC Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

1.8.2 Motor Control Loop Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

1.8.3 Device Level PMF Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.8.4 BDC Clock Source Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.8.5 LINPHY Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

1.8.6 HVPHY Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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8NXP Semiconductors

1.8.7 FTMRZ Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.8.8 CPMU Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.9 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.9.1 Chip Configuration Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

1.9.2 Debugging Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

1.9.3 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

1.10 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.10.2 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

1.10.3 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

1.10.4 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

1.10.5 Reprogramming the Security Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

1.10.6 Complete Memory Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

1.11 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

1.11.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

1.11.2 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

1.11.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

1.12 Module device level dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1.12.1 CPMU COP and GDU Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

1.12.2 CPMU High Temperature Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

1.12.3 CPMU VDDC enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

1.12.4 Flash IFR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

1.13 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

1.13.1 ADC Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

1.13.2 SCI Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

1.13.3 Motor Control Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

1.13.4 BDCM Complementary Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

1.13.5 BLDC Six-Step Commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

1.13.6 PMSM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

1.13.7 Power Domain Overview (All devices except ZVMC256) . . . . . . . . . . . . . . . . . . . . . . . 96

1.13.8 Power Domain Overview (ZVMC256) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Chapter 2

Port Integration Module (S12ZVMPIMV3)

2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

2.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

2.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

2.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5

2.3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

2.3.2 PIM Registers 0x0200-0x020F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

2.3.3 PIM Generic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

2.3.4 PIM Generic Register Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

2.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

2.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

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2.4.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

2.4.3 Pin I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

2.4.4 Pin interrupts and Key-Wakeup (KWU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

2.4.5 Over-Current Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

2.4.6 High-Voltage Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

2.5 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

2.5.1 Port Data and Data Direction Register writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

2.5.2 Open Input Detection on HVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

2.5.3 Over-Current Protection on EVDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Chapter 3

Memory Mapping Control (S12ZMMCV1)

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

3.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

3.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

3.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

3.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

3.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

3.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

3.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

3.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

3.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

3.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

3.4.1 Global Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

3.4.2 Illegal Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

3.4.3 Uncorrectable ECC Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Chapter 4

Interrupt (S12ZINTV0)

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

4.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

4.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

4.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

4.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

4.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

4.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

4.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

4.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

4.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

4.4.1 S12Z Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

4.4.2 Interrupt Prioritization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178

4.4.3 Priority Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.4 Reset Exception Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

4.4.5 Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

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4.4.6 Interrupt Vector Table Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

4.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

4.5.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

4.5.2 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

4.5.3 Wake Up from Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

Chapter 5

Background Debug Controller (S12ZBDCV2)

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

5.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

5.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

5.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

5.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

5.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

5.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

5.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

5.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

5.4.1 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

5.4.2 Enabling BDC And Entering Active BDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

5.4.3 Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

5.4.4 BDC Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

5.4.5 BDC Access Of Internal Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210

5.4.6 BDC Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

5.4.7 Serial Interface Hardware Handshake (ACK Pulse) Protocol . . . . . . . . . . . . . . . . . . . . 216

5.4.8 Hardware Handshake Abort Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

5.4.9 Hardware Handshake Disabled (ACK Pulse Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . 219

5.4.10 Single Stepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

5.4.11 Serial Communication Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

5.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

5.5.1 Clock Frequency Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

Chapter 6

S12Z Debug (S12ZDBG) Module

6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

6.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

6.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

6.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

6.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

6.1.5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.2.1 External Event Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

6.2.2 Profiling Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

6.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

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6.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

6.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

6.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

6.4.1 DBG Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

6.4.2 Comparator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

6.4.3 Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

6.4.4 State Sequence Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

6.4.5 Trace Buffer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

6.4.6 Code Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

6.4.7 Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

6.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

6.5.1 Avoiding Unintended Breakpoint Re-triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

6.5.2 Debugging Through Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

6.5.3 Breakpoints from other S12Z sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

6.5.4 Code Profiling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

Chapter 7

ECC Generation Module (SRAM_ECCV1)

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

7.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

7.2 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

7.2.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

7.2.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

7.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

7.3.1 Non-aligned Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

7.3.2 Aligned 2 and 4 Byte Memory Write Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.3.3 Memory Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.3.4 Memory Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284

7.3.5 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

7.3.6 ECC Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

7.3.7 ECC Debug Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

Chapter 8

S12 Clock, Reset and Power Management Unit (V1 0 and V6)

8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288

8.1.1 Differences between S12CPMU_UHV_V10 and S12CPMU_UHV_V6 . . . . . . . . . . . 289

8.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

8.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292

8.1.4 S12CPMU_UHV_V10_V6 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

8.2 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

8.2.1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

8.2.2 EXTAL and XTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

8.2.3 VSUP — Regulator Power Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

8.2.4 VDDA, VSSA — Regulator Reference Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 297

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8.2.5 VDDX, VSSX— Pad Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

8.2.6 VDDC— CAN Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

8.2.7 VDDS1— Sensor Supply1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

8.2.8 VDDS2— Sensor Supply2 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

8.2.9 BCTL— Base Control Pin for external PNP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

8.2.10 BCTLC — Base Control Pin for external PNP for VDDC power domain . . . . . . . . . . . 299

8.2.11 BCTLS1 — Base Control Pin for external PNP for VDDS1 power domain . . . . . . . . . . 299

8.2.12 BCTLS2 — Base Control Pin for external PNP for VDDS2 power domain . . . . . . . . . . 300

8.2.13 SNPS1 — Sense Pin for VDDS1 power domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

8.2.14 SNPS2 — Sense Pin for VDDS2 power domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

8.2.15 VSS1,2 — Core Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300

8.2.16 VDD— Core Logic Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

8.2.17 VDDF— NVM Logic Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

8.2.18 API_EXTCLK — API external clock output pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

8.2.19 TEMPSENSE — Internal Temperature Sensor Output Voltage . . . . . . . . . . . . . . . . . . 301

8.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

8.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302

8.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

8.4.1 Phase Locked Loop with Internal Filter (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345

8.4.2 Startup from Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347

8.4.3 Stop Mode using PLLCLK as source of the Bus Clock . . . . . . . . . . . . . . . . . . . . . . . . 348

8.4.4 Full Stop Mode using Oscillator Clock as source of the Bus Clock . . . . . . . . . . . . . . . 348

8.4.5 External Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

8.4.6 System Clock Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

8.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

8.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352

8.5.2 Description of Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

8.5.3 Oscillator Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353

8.5.4 PLL Clock Monitor Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354

8.5.5 Computer Operating Properly Watchdog (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . 354

8.5.6 Power- On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

8.5.7 Low-Voltage Reset (LVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355

8.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

8.6.1 Description of Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356

8.7 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

8.7.1 General Initialization Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

8.7.2 Application information for COP and API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358

8.7.3 Application Information for PLL and Oscillator Startup . . . . . . . . . . . . . . . . . . . . . . . . 359

Chapter 9

Analog-to-Digital Converter (ADC12B_LBA)

9.1 Differences ADC12B_LBA V1 vs V2 vs V3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362

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9.3 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

9.3.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

9.3.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

9.4 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

9.4.1 Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

9.5 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

9.5.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

9.5.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

9.6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

9.6.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

9.6.2 Analog Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

9.6.3 Digital Sub-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407

9.7 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

9.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

9.8.1 ADC Conversion Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

9.8.2 ADC Sequence Abort Done Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420

9.8.3 ADC Error and Conversion Flow Control Issue Interrupt . . . . . . . . . . . . . . . . . . . . . . . 421

9.9 Use Cases and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422

9.9.1 List Usage — CSL single buffer mode and RVL single buffer mode . . . . . . . . . . . . . . 422

9.9.2 List Usage — CSL single buffer mode and RVL double buffer mode . . . . . . . . . . . . . 422

9.9.3 List Usage — CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 423

9.9.4 List Usage — CSL double buffer mode and RVL single buffer mode . . . . . . . . . . . . . 423

9.9.5 List Usage — CSL double buffer mode and RVL double buffer mode . . . . . . . . . . . . . 424

9.9.6 RVL swapping in RVL double buffer mode and related registers ADCIMDRI and

ADCEOLRI 424

9.9.7 Conversion flow control application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

9.9.8 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428

9.9.9 Triggered Conversion — Single CSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429

9.9.10 Fully Timing Controlled Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430

Chapter 10

Supply Voltage Sensor - (BATSV3)

10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

10.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

10.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

10.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

10.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

10.2.1 VSUP — Voltage Supply Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432

10.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

10.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

10.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

10.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

10.4.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437

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Chapter 11

Timer Module (TIM16B4CV3) Block Description

11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

11.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

11.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441

11.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

11.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

11.2.1 IOC3 - IOC0 — Input Capture and Output Compare Channel 3-0 . . . . . . . . . . . . . . . . 443

11.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

11.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

11.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

11.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

11.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456

11.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

11.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

11.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

11.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

11.6.1 Channel [3:0] Interrupt (C[3:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

11.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458

Chapter 12

Timer Module (TIM16B2CV3) Block Description

12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

12.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459

12.1.3 Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

12.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

12.2.1 IOC1 - IOC0 — Input Capture and Output Compare Channel 1-0 . . . . . . . . . . . . . . . . 461

12.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

12.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

12.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

12.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473

12.4.1 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

12.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

12.4.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475

12.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

12.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

12.6.1 Channel [1:0] Interrupt (C[1:0]F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

12.6.2 Timer Overflow Interrupt (TOF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Chapter 13

Scalable Controller Area Network (S12MSCANV3)

13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477

13.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

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13.1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478

13.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

13.1.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479

13.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

13.2.1 RXCAN — CAN Receiver Input Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

13.2.2 TXCAN — CAN Transmitter Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

13.2.3 CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480

13.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

13.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481

13.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483

13.3.3 Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502

13.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

13.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

13.4.2 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513

13.4.3 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516

13.4.4 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522

13.4.5 Low-Power Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524

13.4.6 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

13.4.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528

13.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

13.5.1 MSCAN initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

13.5.2 Bus-Off Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Chapter 14

Programmable Trigger Unit (PTUV3)

14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531

14.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532

14.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

14.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

14.2.1 PTUT0 — PTU Trigger 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

14.2.2 PTUT1 — PTU Trigger 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533

14.2.3 PTURE — PTUE Reload Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

14.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

14.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534

14.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536

14.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

14.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552

14.4.2 Memory based trigger event list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554

14.4.3 Reload mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

14.4.4 Async reload event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555

14.4.5 Interrupts and error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556

14.4.6 Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557

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16 NXP Semiconductors

Chapter 15

Pulse Width Modulator with Fault Protection (PMF15B6CV4)

15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560

15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

15.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561

15.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563

15.2 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

15.2.1 PWM0–PWM5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

15.2.2 FAULT0–FAULT5 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

15.2.3 IS0–IS2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

15.2.4 Global Load OK Signal — glb_ldok . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

15.2.5 Commutation Event Signal — async_event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564

15.2.6 Commutation Event Edge Select Signal — async_event_edge_sel[1:0] . . . . . . . . . . . 565

15.2.7 PWM Reload Event Signals — pmf_reloada,b,c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565

15.2.8 PWM Reload-Is-Asynchronous Signal — pmf_reload_is_async . . . . . . . . . . . . . . . . . 565

15.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

15.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566

15.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571

15.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

15.4.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599

15.4.2 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

15.4.3 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600

15.4.4 Independent or Complementary Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 604

15.4.5 Deadtime Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

15.4.6 Top/Bottom Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607

15.4.7 Asymmetric PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

15.4.8 Variable Edge Placement PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614

15.4.9 Double Switching PWM Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615

15.4.10Output Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

15.4.11Software Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

15.4.12PWM Generator Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620

15.4.13Fault Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625

15.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

15.6 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627

15.7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

15.8 Initialization and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

15.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628

15.8.2 BLDC 6-Step Commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

Chapter 16

Serial Communication Interface (S12SCIV6)

16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

16.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633

16.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634

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16.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

16.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635

16.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

16.2.1 TXD — Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

16.2.2 RXD — Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

16.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

16.3.1 Module Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636

16.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637

16.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650

16.4.1 Infrared Interface Submodule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

16.4.2 LIN Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651

16.4.3 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652

16.4.4 Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653

16.4.5 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654

16.4.6 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659

16.4.7 Single-Wire Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667

16.4.8 Loop Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

16.5 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

16.5.1 Reset Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668

16.5.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

16.5.3 Interrupt Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669

16.5.4 Recovery from Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

16.5.5 Recovery from Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672

Chapter 17

Serial Peripheral Interface (S12SPIV5)

17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

17.1.1 Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

17.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

17.1.3 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673

17.1.4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674

17.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

17.2.1 MOSI — Master Out/Slave In Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675

17.2.2 MISO — Master In/Slave Out Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

17.2.3 SS — Slave Select Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

17.2.4 SCK — Serial Clock Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

17.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

17.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676

17.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677

17.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685

17.4.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686

17.4.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

17.4.3 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688

17.4.4 SPI Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693

17.4.5 Special Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694

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17.4.6 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695

17.4.7 Low Power Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696

Chapter 18

Gate Drive Unit (GDU)

18.1 Differences GDUV4 vs GDUV5 vs GDUV6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699

18.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700

18.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701

18.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702

18.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.2.1 HD — High-Side Drain Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.2.2 VBS[2:0] — Bootstrap Capacitor Connection Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.2.3 HG[2:0] — High-Side Gate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.2.4 HS[2:0] — High-Side Source Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.2.5 VLS[2:0] — Voltage Supply for Low-Side Pre-Drivers . . . . . . . . . . . . . . . . . . . . . . . . 703

18.2.6 LG[2:0] — Low-Side Gate Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.2.7 LD[2:0] — Low-Side Gate Pins (only on GDUV6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

18.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

18.3.1 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705

18.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706

18.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

18.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

18.4.2 Low-Side FET Pre-Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

18.4.3 High-Side FET Pre-Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726

18.4.4 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729

18.4.5 Desaturation Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731

18.4.6 Phase Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733

18.4.7 Fault Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734

18.4.8 Current Sense Amplifier and Overcurrent Comparator . . . . . . . . . . . . . . . . . . . . . . . . . 738

18.4.9 GDU DC Link Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738

18.4.10Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739

18.4.11Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740

18.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

18.5.1 FET Pre-Driver Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741

18.5.2 GDU Intrinsic Dead Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742

18.5.3 Calculation of Bootstrap Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

18.5.4 On Chip GDU tdelon and tdeloff Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744

Chapter 19

LIN/HV Physical Layer (S12LINPHYV3)

19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747

19.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748

19.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748

19.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749

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19.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.2.1 LIN — LIN Bus Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.2.2 LGND — LIN Ground Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.2.3 VLINSUP — Positive Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.2.4 LPTxD — LIN Transmit Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.2.5 LPRxD — LIN Receive Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751

19.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753

19.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

19.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

19.4.2 Slew Rate and LIN Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760

19.4.3 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761

19.4.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764

19.5 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

19.5.1 Module Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767

19.5.2 Interrupt handling in Interrupt Service Routine (ISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 767

Chapter 20

Flash Module (S12ZFTMRZ)

20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769

20.1.1 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

20.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770

20.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771

20.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773

20.3 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

20.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774

20.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778

20.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

20.4.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

20.4.2 IFR Version ID Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

20.4.3 Flash Block Read Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798

20.4.4 Internal NVM resource . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799

20.4.5 Flash Command Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800

20.4.6 Allowed Simultaneous P-Flash and EEPROM Operations . . . . . . . . . . . . . . . . . . . . . . 804

20.4.7 Flash Command Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805

20.4.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821

20.4.9 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

20.4.10Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

20.5 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822

20.5.1 Unsecuring the MCU using Backdoor Key Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823

20.5.2 Unsecuring the MCU in Special Single Chip Mode using BDM . . . . . . . . . . . . . . . . . 823

20.5.3 Mode and Security Effects on Flash Command Availability . . . . . . . . . . . . . . . . . . . . . 823

20.6 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

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Chapter 21

CAN Physical Layer (S12CANPHYV3)

21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

21.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

21.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

21.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826

21.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827

21.2.1 CANH — CAN Bus High Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.2.2 CANL — CAN Bus Low Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.2.3 SPLIT — CAN Bus Termination Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.2.4 VDDC — Supply Pin for CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.2.5 VSSC — Ground Pin for CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.3 Internal Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.3.1 CPTXD — TXD Input to CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.3.2 CPRXD — RXD Output of CAN Physical Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828

21.4 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

21.4.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829

21.4.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830

21.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

21.5.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

21.5.2 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837

21.5.3 Configurable Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839

21.5.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840

21.6 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

21.6.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841

21.6.2 Wake-up Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

21.6.3 Bus Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842

21.6.4 CPTXD-Dominant Timeout Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843

Chapter 22

Pulse-Width Modulator (S12PWM8B8CV2)

22.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

22.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

22.1.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845

22.1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

22.2 External Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846

22.2.1 PWM7 - PWM0 — PWM Channel 7 - 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

22.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

22.3.1 Module Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

22.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847

22.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

22.4.1 PWM Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

22.4.2 PWM Channel Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865

22.5 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872

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22.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873

Appendix A

MCU Electrical Specifications

A.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875

A.2 General Purpose I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888

A.3 Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 890

A.4 ADC Calibration Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893

Appendix B

CPMU Electrical Specifications (VREG, OSC, IRC, PLL)

B.1 VREG Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895

B.2 Reset and Stop Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897

B.3 IRC and OSC Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898

B.4 Phase Locked Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898

Appendix C

ADC Electrical Specifications

C.1 ADC Operating Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 901

Appendix D

LIN/HV PHY Electrical Specifications

D.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 907

D.2 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 908

Appendix E

GDU Electrical Specifications

E.1 GDU specifications for devices featuring GDU V4 or V6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911

E.2 Preliminary GDU specifications for devices featuring GDU V5 . . . . . . . . . . . . . . . . . . . . . . . . . 914

Appendix F

NVM Electrical Parameters

F.1 NVM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 919

F.2 NVM Reliability Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926

F.3 NVM Factory Shipping Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 926

Appendix G

BATS Electrical Specifications

G.1 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927

G.2 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928

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Appendix H

S12CANPHY Electrical Specifications

H.1 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929

H.2 Static Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 929

H.3 Dynamic Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932

Appendix I

SPI Electrical Specifications

I.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 935

Appendix J

MSCAN Electrical Specifications

J.1 MSCAN Wake-up Pulse Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939

Appendix K

Package Information

K.1 48LQFP-EP Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 942

K.2 64LQFP-EP Mechanical Info (all mask sets except 1N95G, 2N95G) . . . . . . . . . . . . . . . . . . . . . 945

K.3 64LQFP-EP Mechanical Information (mask sets 1N95G, 2N95G) . . . . . . . . . . . . . . . . . . . . . . . 949

K.4 80LQFP-EP Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952

Appendix L

Ordering Information

Appendix M

Detailed Register Address Map

M.1 0x0000–0x0003 Part ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957

M.2 0x0010–0x001F S12ZINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 957

M.3 0x0070-0x00FF S12ZMMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959

M.4 0x0100-0x017F S12ZDBG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 959

M.5 0x0200-0x02FF PIM (See footnotes for part specific information) . . . . . . . . . . . . . . . . . . . . . . . 963

M.6 0x0380-0x039F FTMRZ128K512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 969

M.7 0x03C0-0x03CF SRAM_ECC_32D7P. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971

M.8 0x0400-0x042F TIM1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972

M.9 0x0480-0x04AF PWM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973

M.10 0x0500-x053F PMF15B6C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 975

M.11 0x0580-0x059F PTU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979

M.12 0x05C0-0x05FF TIM0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 981

M.13 0x0600-0x063F ADC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983

M.14 0x0640-0x067F ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985

M.15 0x06A0-0x06BF GDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 987

M.16 0x06C0-0x06DF CPMU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988

M.17 0x06F0-0x06F7 BATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

MC9S12ZVM Family Reference Manual Rev . 2.11

NXP Semiconductors 23

M.18 0x0700-0x0707 SCI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 990

M.19 0x0710-0x0717 SCI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991

M.20 0x0780-0x0787 SPI0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

M.21 0x0800–0x083F CAN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992

M.22 0x0980-0x0987 LINPHY0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994

M.23 0x0990-0x0997 CANPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 994

MC9S12ZVM Family Reference Manual Rev. 2.11

24 NXP Semiconductors

MC9S12ZVM Family Reference Manual Rev. 2.1 1

NXP Semiconductors 25

Chapter 1

Device Overview MC9S12ZVM-Family

Table 1-1. Revision History

1.1 Introduction

The MC9S12ZVM-Family is an automotive 16-bit microcontroller family using the NVM + UHV

technology that offers the capability to integrate 40 V analog components. This family reuses many

features from the existing S12/S12X portfolio. The particular dif ferentiating features of this family are the

enhanced S12Z core, the combination of dual-ADC synchronized with PWM generation and the

integration of “high-voltage” analog modules, including the voltage regulator (VREG), Gate Drive Unit

(GDU), and either Local Interconnect Network (LIN) physical layer or CAN Physical layer . These features

enable a fully integrated single chip solution to drive up to 6 external power MOSFETs for BLDC or

PMSM motor drive applications.

The MC9S12ZVM-Family includes error correction code (ECC) on RAM and flash memory, EEPROM

for diagnostic or data storage, a fast analog-to-digital converter (ADC) and a frequency modulated phase

locked loop (IPLL) that improves the EMC performance. The MC9S12ZVM-Family allows the

integration of several key system components into a single device, optimizing system architecture and

achieving significant space savings. The MC9S12ZVM-Family delivers all the advantages and

efficiencies of a 16-bit MCU while retaining the low cost, power consumption, EMC, and code-size

efficiency advantages currently enjoyed by users of existing S12(X) families. The MC9S12ZVM-Family

is available in different pin-out options, using 80-pin, 64-pin and 48-pin LQFP-EP packages to

accommodate LIN, CAN and external PWM based application interfaces. In addition to the I/O ports

available in each module, further I/O ports are available with interrupt capability allowing wake-up from

stop or wait modes.

The MC9S12ZVM-Family is a general-purpose family of devices suitable for a range of applications,

including:

• 3-phase sensorless BLDC motor control for

— Fuel pump

Version

Number Revision

Date Sections

Affected Description of Changes

1.8 04.Sep.2014 Section 1.2.1 • Added S12ZVML31 information to derivative table

2.0 10.Oct.2014 General • Added ZVMC256 information

2.01 06.Feb.2015 General • Added 2N95G maskset information.

• Added TIM1 for ZVMC256

2.02 25.Aug.2016 Figure 1-6,

Tab l e 1- 8

Section 1.13.3.6

• Clarified IOC0 device pin mapping dependencies

• Removed Temperature Sensor from list of Dynamic motor control fault inputs

Chapter 1 Device Overview MC9S12ZVM-Family

MC9S12ZVM Family Reference Manual Rev. 2.11

26 NXP Semiconductors

— Water pump

— Oil pump

— A/C compressor

— HVAC blower

— Engine cooling fan

— Electric vehicle battery cooling fan

• Brush DC motor control requiring driving in 2 directions, along with PWM control for

— Reversible wiper

— Trunk opener

1.2 Features

This section describes the key features of the MC9S12ZVM-Family. It documents the superset of features

within the family. Some module versions differ from one part to another within the family. Section 1.2.1

MC9S12ZVM-Family Member Comparison provides information to help access the correct information

for a particular part within the family.

1.2.1 MC9S12ZVM-Family Member Comparison

Table 1-2 provides a summary of feature set differences within the MC9S12ZVM-Family.

Table 1-2. S12ZVM Family Feature Set Differences

Feature ZVMC25

6ZVML12

8ZVMC12

8ZVML6

4ZVMC6

4ZVML3

2ZVML3

1ZVML3

1ZVM32 ZVM32 ZVM16 ZVM16

Flash 256 KB 128 KB 128 KB 64 KB 64 KB 32 KB 32 KB 32 KB 32 KB 32 KB 16 KB 16 KB

EEPROM 1 KB 512

Bytes

512

Bytes

512

Bytes

512

Bytes

512

Bytes

128

Bytes

128

Bytes

128

Bytes

128

Bytes

128

Bytes

128

Bytes

RAM 32 KB 8 KB 8 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 4 KB 2 KB 2 KB

Package 80 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 48 pin 64 pin 48 pin 64 pin 48 pin

LINPHY– 1 – 1–111––––

HVPHY– – – –––––1111

SCI 2 2 2 222222222

SPI 1 1 1 111101010

ADC

channels

8+8 4+5 4+5 4+5 4+5 4+5 4+5 1+3 4+5 1+3 4+5 1+3

PMF

channels

6 6 6 666666666

TIM

channels

4 TIM0 +

2 TIM1

4 4 444434343

Chapter 1 Device Overview MC9S12ZVM-Family

MC9S12ZVM Family Reference Manual Rev . 2.11

NXP Semiconductors 27

1.2.2 Module Version Differences Within The S12ZVM Family

Table 1-3 provides a summary of module version differences within the MC9S12ZVM-Family. The

differences between the module versi ons are summarized in the individual module chapters. Modules that

are not listed in this table have identical versions across all MC9S12ZVM-Family members.

PWM

channels

8 – – –––––––––

MSCAN 1 1 1 1 1 1 – – – – – –

CAN

VREG

1 – 1 –1–––––––

CANPHY1 – – –––––––––

External

FET gate

charge(n

Standard + 50% Standard

GDU

external

bootstrap

diode

Needed Needed Needed Needed Needed Needed Not

Needed

Not

Needed

Not

Neede

Not

Neede

Not

Neede

Not

Neede

Current

sense

op-amps

2 2 2 222212121

Auxiliary

tracker

VREGs

2 – – –––––––––

Table 1-3. S12ZVM Module Version Table

Feature ZVMC25

6ZVML12

8ZVMC12

8ZVML64 ZVMC64 ZVML32 ZVML31 ZVM32 ZVM16

PIM V3V2V2V2V2V2V2V2V2

CPMU_UH

V10V6V6V6V6V6V6V6V6

PMF V4V3V3V3V3V3V4V4V4

GDU V6 V4(1)

1. Mask set differences listed in Section 1.2.3

V4 (1) V4 (1) V4 (1) V4 (1) V5 V5 V5

DBG V4 V2 V2 V2 V2 V2 V3 (Lite) V3 (Lite) V3 (Lite)

ADC V3V1V1V1V1V1V1V1V1

Table 1-2. S12ZVM Family Feature Set Differences

Feature ZVMC25

6ZVML12

8ZVMC12

8ZVML6

4ZVMC6

4ZVML3

2ZVML3

1ZVML3

1ZVM32 ZVM32 ZVM16 ZVM16

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MC9S12ZVM Family Reference Manual Rev. 2.11

28 NXP Semiconductors

1.2.3 Functional Differences Between Masksets

The parts ZVML128, ZVMC128, ZVML64, ZVMC64 and ZVML32 have the following mask set options.

CAUTION

The maskset 2N95G uses the VSUP pin as the LINPHY supply . Thus the BST function must

not be used on this maskset because enabling it could cause a LINPHY supply volt age

offset with respect to other devices on the LIN bus.

Further GDU configuration mask set dependencies are specified in Table 1-19.

1.3 Chip-Level Features

On-chip modules available within the family include the following features:

• S12Z CPU core

• 256, 128, 64, 32 or 16KB on-chip flash with ECC

• 1K, 512 or 128 byte EEPROM with ECC

• 32, 8, 4 or 2 KB on-chip SRAM with ECC

• Phase locked loop (IPLL) frequency multiplier with internal filter

• 1 MHz internal RC oscillator with +/-1.3% accuracy over rated temperature range

• 4-20MHz amplitude controlled pierce oscillator

• Internal COP (watchdog) module

• 6-channel, 15-bit pulse width modulator with fault protection (PMF)

• Low side and high side FET pre-drivers for each phase

— Gate drive pre-regulator

— LDO (Low Dropout Voltage Regulator) (typically 11V)

— High side gate supply generated using bootstrap circuit with external diode and capacitor

— Sustaining charge pump with two external capacitors and diodes

— High side drain (HD) monitoring on internal ADC channel using HD/5 voltage

• Two parallel analog-to-digital converters (ADC) with 12-bit resolution and up to 16 channels

available on external pins

• Programmable Trigger Unit (PTU) for synchronization of PMF and ADC

• One serial peripheral interface (SPI) module

• One serial communication interface (SCI) module with interface to internal LIN physical layer

transceiver (with RX connected to a timer channel for frequency calibration purposes, if desired)

Table 1-4. N95G Option Table

Feature 0N95G(1)

1. 0N95G is not a production mask set

1N95G 2N95G 3N95G

LINPHY supply pin HD HD VSUP HD

BST pin function available Yes Yes No Yes

GDU low side driver state in HD over-voltage case on GOCA1 GOCA1 GOCA1

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NXP Semiconductors 29

• Up to one additional SCI (not connected to LIN physical layer)

• On-chip LIN physical layer transceiver fully compliant with the LIN 2.2 standard

(S12ZVML versions)

• One High Voltage physical interface. (ZVM32, ZVM16 versions only)

• 4-channel timer module (TIM0) with input capture/output compare

• 2-channel timer module (TIM1) with input capture/output compare (ZVMC256 version only)

• One 8-bit, 8-channel pulse width modulator (PWM) module. (ZVMC256 version only)

• MSCAN (1 Mbit/s, CAN 2.0 A, B software compatible) module

• On-chip voltage regulator (VREG) for regulation of input supply and all internal voltages

— Optional VREG ballast control output to supply an external CAN physical layer

• CAN Physical Layer, ISO 11898-2 and ISO 11898-5 compliant. (ZVMC256 version only)

• Two voltage regulator outputs to supply external loads. (ZVMC256 version only)

• Two current sense circuits for overcurrent detection or torque measurement

• Autonomous periodic interrupt (API)

• 20mA high-current output for use as Hall sensor supply

• Supply voltage sense with low battery warning

• Chip temperature sensor

• One High Voltage Input (ZVMC256 version only)

1.4 Module Features

The following sections provide more details of the integrated modules.

1.4.1 S12Z Central Processor Unit (CPU)

The S12Z CPU is a revolutionary high-speed core, with code size and execution efficiencies over the S12X

CPU. The S12Z CPU also provides a linear memory map eliminating the inconvenience and performance

impact of page swapping.

• Harvard Architecture - parallel data and code access

• 3 stage pipeline

• 32-Bit wide instruction and databus

• 32-Bit ALU

• 24-bit addressing, of 16MB linear address space

• Instructions and Addressing modes optimized for C-Programming & Compiler

— MAC unit 32bit += 32bit*32bit

— Hardware divider

— Single cycle multi-bit shifts (Barrel shifter)

— Special instructions for fixed point math

• Unimplemented opcode traps

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30 NXP Semiconductors

• Unprogrammed byte value (0xFF) defaults to SWI instruction

1.4.1.1 Background Debug Controller (BDC)

• Background debug controller (BDC) with single-wire interface

— Non-intrusive memory access commands

— Supports in-circuit programming of on-chip nonvolatile memory

1.4.1.2 Debugger (DBG)

ZVML31, ZVM32, ZVM16 feature subset listed in S12ZDBG chapter

• Enhanced DBG module including:

— Four comparators (A, B, C and D) each configurable to monitor PC addresses or addresses of

data accesses

— A and C compare full address bus and full 32-bit data bus with data bus mask register

— B and D compare full address bus only

— Three modes: simple address/data match, inside address range, or outside address range

— Tag-type or force-type hardware breakpoint requests

• State sequencer control

• 64 x 64-bit circular trace buffer to capture change-of-flow addresses or address and data of every

access

— Begin, End and Mid alignment of tracing to trigger

• Profiling mode for external visibility of internal program flow

1.4.2 Embedded Memory

1.4.2.1 Memory Access Integrity

• Illegal address detection

• ECC support on embedded NVM and system RAM

1.4.2.2 Flash

On-chip flash memory on the MC9S12ZVM-family on the features the following:

• Up to 256KB of program flash memory

— 32 data bits plus 7 syndrome ECC (error correction code) bits allow single bit fault correction

and double fault detection

— Erase sector size 512 bytes

— Automated program and erase algorithm

— User margin level setting for reads

— Protection scheme to prevent accidental program or erase

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NXP Semiconductors 31

1.4.2.3 EEPROM

• Up to 1K byte EEPROM

— 16 data bits plus 6 syndrome ECC (error correction code) bits allow single bit error correction

and double fault detection

— Erase sector size 4 bytes

— Automated program and erase algorithm

— User margin level setting for reads

1.4.2.4 SRAM

• Up to 32 KB of general-purpose RAM with ECC

— Single bit error correction and double bit error detection

1.4.3 Clocks, Reset & Power Management Unit (CPMU)

• Real time interrupt (RTI)

• Clock monitor, supervising the correct function of the oscillator (CM)

• Computer operating properly (COP) watchdog

— Configurable as window COP for enhanced failure detection

— Can be initialized out of reset using option bits located in flash memory

• System reset generation

• Autonomous periodic interrupt (API) (combination with cyclic, watchdog)

• Low Power Operation

— RUN mode is the main full performance operating mode with the entire device clocked.

— WAIT mode when the internal CPU clock is switched off, so the CPU does not execute

instructions.

— Pseudo STOP - system clocks are stopped but the oscillator the R TI, the COP, and API modules

can be enabled

— STOP - the oscillator is stopped in this mode, all clocks are switched off and all counters and

dividers remain frozen, with the exception of the COP and API which can optionally run from

ACLK.

1.4.3.1 Internal Phase-Locked Loop (IPLL)

• Phase-locked-loop clock frequency multiplier

— No external components required

— Reference divider and multiplier allow large variety of clock rates

— Automatic bandwidth control mode for low-jitter operation

— Automatic frequency lock detector

— Configurable option to spread spectrum for reduced EMC radiation (frequency modulation)

— Reference clock sources:

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32 NXP Semiconductors

– Internal 1 MHz RC oscillator (IRC)

– External 4-20 MHz crystal oscillator/resonator

1.4.3.2 Internal RC Oscillator (IRC)

• Trimmable internal 1MHz reference clock.

— Trimmed accuracy over -40C to 150C junction temperature range: 1.3%max.

1.4.4 Main External Oscillator (XOSCLCP)

• Amplitude controlled Pierce oscillator using 4 MHz to 20 MHz crystal

— Current gain control on amplitude output

— Signal with low harmonic distortion

— Low power

— Good noise immunity

— Eliminates need for external current limiting resistor

— Trans conductance sized for optimum start-up margin for typical crystals

— Oscillator pins shared with GPIO functionality

1.4.5 Timer (T IM0)

• 4 x 16-bit channels Timer module for input capture or output compare

• 16-bit free-running counter with 8-bit precision prescaler

1.4.6 Timer (TIM1) (ZVMC256 only)

• 2 x 16-bit channels Timer module for input capture or output compare

• 16-bit free-running counter with 8-bit precision prescaler

1.4.7 Pulse width Modu lator with Fault protection (PMF)

• 6 x 15-bit channel PWM resolution

• Each pair of channels can be combined to generate a PWM signal (with independent control of

edges of PWM signal)

• Dead time insertion available for each complementary pair

• Center-aligned or edge-aligned outputs

• Programmable clock select logic with a wide range of frequencies

• Programmable fault detection

1.4.8 Programmable Trigger Unit (PTU)

• Enables synchronization between PMF and ADC

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NXP Semiconductors 33

• 2 trigger input sources and software trigger source

• 2 trigger outputs

• One 16-bit delay register pre-trigger output

• Operation in One-Shot or Continuous modes

1.4.9 LIN physical layer transceiver (ZVML devices only)

• Compliant with LIN Physical Layer 2.2 specification.

• Compliant with the SAE J2602-2 LIN standard.

• Standby mode with glitch-filtered wake-up.

• Slew rate selection optimized for the baud rates: 10.4kBit/s, 20kBit/s and Fast Mode (up to

250kBit/s).

• Switchable 34k/330k pull-ups (in shutdown mode, 330k only)

• Current limitation for LIN Bus pin falling edge.

• Over-current protection.

• LIN TxD-dominant timeout feature monitoring the LPTxD signal.

• Automatic transmitter shutdown in case of an over-current or TxD-dominant timeout.

• Fulfills the OEM “Hardware Requirements for LIN (CAN and FlexRay) Interfaces in Automotive

Applications” v1.3.

1.4.10 Serial Communication Interface Module (SCI)

• Full-duplex or single-wire operation

• Standard mark/space non-return-to-zero (NRZ) format

• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths

• 16-bit baud rate selection

• Programmable character length

• Programmable polarity for transmitter and receiver

• Active edge receive wakeup

• Break detect and transmit collision detect supporting LIN

1.4.11 Multi-Scalable Controller Area Network (MSCAN)

• Implementation of the CAN protocol — Version 2.0A/B

• Five receive buffers with FIFO storage scheme

• Three transmit buffers with internal prioritization using a “local priority” concept

• Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four

16-bit filters, or either 8-bit filters

• Programmable wake-up functionality with integrated low-pass filter

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34 NXP Semiconductors

1.4.12 Serial Peripheral Interface Module (SPI)

• Configurable 8- or 16-bit data size

• Full-duplex or single-wire bidirectional

• Double-buffered transmit and receive

• Master or slave mode

• MSB-first or LSB-first shifting

• Serial clock phase and polarity options

1.4.13 Analog-to-Digital Converter Module (ADC)

• Dual ADC

— 12-bit resolution

— Up to 16 external channels & 8 internal channels

— 2.5us for single 12-bit resolution conversion

— Left or right aligned result data

— Continuous conversion mode

• Programmers model with list based command and result storage architecture

ADC directly writes results to RAM, preventing stall of further conversions

• Internal signals monitored with the ADC module

— VRH, VRL, (VRL+VRH)/2, Vsup monitor, Vbg, TempSense, GDU phase, GDU DC-link

• External pins can also be used as digital I/O

1.4.14 Supply Voltage Sensor (BATS)

• Monitoring of supply (VSUP) voltage

• Internal ADC interface from an internal resistive divider

• Generation of low or high voltage interrupts

1.4.15 On-Chip Voltage Regulator system (VREG)

• Voltage regulator

— Linear voltage regulator directly supplied by VSUP

— Low-voltage detect on VSUP

— Power-on reset (POR)

— Low-voltage reset (LVR) for VDDX domain

— External ballast device support to reduce internal power dissipation

— Capable of supplying both the MCU internally plus external components

— Over-temperature interrupt

• Internal voltage regulator

— Linear voltage regulator with bandgap reference

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MC9S12ZVM Family Reference Manual Rev . 2.11

NXP Semiconductors 35

— Low-voltage detect on VDDA

— Power-on reset (POR) circuit

— Low-voltage reset for VDD domain

• Package option for VREG ballast control output to supply external CANPHY

• Option for 2 further VREG ballast control outputs to supply external components (ZVMC256)

1.4.16 Gate Drive Unit (GDU)

• Low side and high side FET pre-drivers for each phase

• Gate drive pre-regulator LDO (Low Dropout Voltage Regulator)

• High side gate supply done via bootstrap circuit

• External bootstrap diode replaced by internal circuit (GDUV5 only)

• Sustaining charge pump with two external capacitors and diodes

• Optional boost converter configuration with voltage feedback

• FET-Predriver desaturation and error recognition

• Monitoring of FET High Side drain (HD) voltage

• Diagnostic failure management

• Low side drain pins for monitoring desaturation of switch reluctance motor drivers (ZVMC256)

1.4.17 Current Sense

• 2 channel, integrated op-amp functionality

1.4.18 High Voltage Physical Interface (ZVM32, ZVM16)

• Single pin high voltage interface signal operating in the VSUP voltage range

• Internal interface mapped to internal timer channel.

• Compliant with the ISO9141 (K-line) standard.

• Standby mode with glitch-filtered wake-up.

• Slew rate selection optimized for: 5.2 kHz, 10 kHz and Fast Mode (up to 125 kHz).

• Switchable 34 k/330 k pullup resistors (in shutdown mode, 330 konly

• Current limitation for pin falling edge.

• Overcurrent protection.

1.4.19 CAN Physical Layer Module (ZVMC256 only)

• High speed CAN interface for baud rates of up to 1 Mbit/s

• ISO 11898-2 and ISO 11898-5 compliant for 12 V battery systems

• SPLIT pin driver for bus recessive level stabilization

• Low power mode with remote CAN wake-up handled by MSCAN module

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36 NXP Semiconductors

• Configurable wake-up pulse filtering

• Over-current shutdown for CANH and CANL

• Voltage monitoring on CANH and CANL

• CPTXD-dominant timeout feature monitoring the CPTXD signal

• Fulfills the OEM “Hardware Requirements for (LIN,) CAN (and FlexRay) Interfaces in

Automotive Applications” v1.3

1.4.20 Pulse Width Modulation Module (PWM) (ZVMC256 only)

• Configurable as 8 channels x 8-bit or 4 channels x 16-bit

• Programmable period and duty cycle per channel

• Center-aligned or edge-aligned outputs

• Programmable clock select logic with a wide range of frequencies

Chapter 1 Device Overview MC9S12ZVM-Family

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NXP Semiconductors 37

1.5 Block Diagram

Figure 1-1. MC9S12ZVM-Family Block Diagram

2K, 4K, 8K, 32KB RAM with ECC

RESET

EXTAL

XTAL

1K, 512 bytes EEPROM with ECC

BKGD

VSUP

Real Time Interrupt

Clock Monitor

Background

TEST

Debug Controller

ADC0

Interrupt Module

SCI1

PS0

PS1

PTS / KWS

AN0_[7:0]

PAD[7:0]

12-bit

16-bit 4-Channel Timer

TIM0

Asynchronous Serial IF

15-bit 6 channel

Pulse Width Modulator

PMF

32K, 64K, 128K, 256KB Flash with ECC

S12ZCPU

COP Watchdog

PLL with Frequency

Modulation option

Debug Module

4 Comparators

Trace Buffer

Reset Generation

and Test Entry

RXD1

TXD1

Auton. Periodic Int. PT3

PT0

PT1

PT2

PTT

PP0

PP1

PP2

PTP / KWP

IOC0_3

IOC0_0

IOC0_1

IOC0_2

VSS1

Low Power Pierce

Oscillator

SCI0

Asynchronous Serial IF

RXD0

TXD0

MOSI0

SS0

SCK0

MISO0

SPI0

Synchronous Serial IF

PS2

PS3

PS4

PS5

Voltage Regulator

(Nominal 12V)

Block Diagram shows the maximum configuration

Not all pins or all peripherals are available on all devices and packages. Red highlighted features are ZVMC256 specific.

Rerouting options are not shown.

PE0

PTE

PE1

PTAD / KWAD

Analog-Digital Converter

Internal RC Oscillator

PWM1_0

LIN0

LINPHY0 (S12ZVML versions only)

LIN0

LGND

BATS

Voltage Supply Monitor

LGND

ADC1 AN1_[7:0]

12-bit

Analog-Digital Converter

PAD[15:8]

PWM1_1

PWM1_2

BDC

DBG

BCTL

CAN0

msCAN 2.0B

RXCAN0

TXCAN0

Current Sense Circuits

AMPP1

AMPM1

AMP1

VDDX1/VDDX2

VDD

VDDF

PTU

Programmable Trigger PTUT0

Unit PTUT1

PTURE

PWM1_3

PWM1_4

PWM1_5

VSS2

VRH

VRL

VRH

VRL

GDU

Gate Drive Unit

VBS[2:0]

HG[2:0]

HS[2:0]

VLS[2:0]

LG[2:0]

LS[2:0]

VCP

VLS_OUT

VBS[2:0]

HG[2:0]

HS[2:0]

VLS[2:0]

LG[2:0]

LS[2:0]

VCP

VLS_OUT

BST

VSSB

BST

VSSB

AMPP0

AMPM0

AMP0

VDDA/VSSA

5V Analog Supply

HV Physical Interface

CANH0

CANPHY0

CANH0

VSSC VSSC

CANL0

BCTLC

VDDC CAN VREG

PL0

PTL/KWL

High Voltage Input

HV0

PWM0

8-bit, 8-channel

Pulse Width Modulator

PWM0_[7,5,3,1]

Additional Voltage Regulator #1

BCTLS1

VDDS1

SNPS1

Additional Voltage Regulator #2

BCTLS2

VDDS2

SNPS2

LD[2:0]

SPLIT0

16-bit 2-Channel Timer

TIM1 IOC1_0

IOC1_1

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1.6 Device Memory Map

Table 1-5 shows the device register memory map. All modules that can be instantiated more than once on

S12 devices are listed with an index number, even if they are only instantiated once on this device family.

Table 1-5. Module Register Address Ranges

Address Module Size

(Bytes)

0x0000–0x0003 Part ID Register Section 1.6.2 4

0x0004–0x000F Reserved 12

0x0010–0x001F INT 16

0x0020–0x006F Reserved 80

0x0070–0x008F MMC 32

0x0090–0x00FF MMC Reserved 112

0x0100–0x017F DBG 128

0x0180–0x01FF Reserved 128

0x0200–0x033F PIM 320

0x0340–0x037F Reserved 64

0x0380–0x039F FTMRZ 32

0x03A0–0x03BF Reserved 32

0x03C0–0x03CF RAM ECC 16

0x03D0–0x03FF Reserved 48

0x0400–0x043F TIM1 (ZVMC256 only) 64

0x0440–0x047F Reserved 64

0x0480–0x04AF PWM0 (ZVMC256 only) 48

0x04B0–0x04FF Reserved(1) 80

0x0500–0x053F PMF 64

0x0540–0x057F Reserved 64

0x0580–0x059F PTU 32

0x05A0–0x05BF Reserved 32

0x05C0–0x05EF TIM0 48

0x05F0–0x05FF Reserved 16

0x0600–0x063F ADC0 64

0x0640–0x067F ADC1 64

0x0680–0x069F Reserved 32

(2)0x06A0–0x06BF GDU 32

0x06C0–0x06DF CPMU 32

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NOTE

Reserved register space shown above is not allocated to any module. This

effect. Read access to these locations returns zero.

1.6.1 Flash Module

This device family instantiates different flash modules, depending on derivative. The flash documentation

for the all devices is featured in the FTMRZ section.

0x06E0–0x06EF Reserved 16

0x06F0–0x06F7 BATS 8

0x06F8–0x06FF Reserved 8

0x0700–0x0707 SCI0 8

0x0708–0x070F Reserved 8

0x0710–0x0717 SCI1 8

0x0718–0x077F Reserved 104

0x0780–0x0787 SPI0 8

0x0788–0x07FF Reserved 120

0x0800–0x083F CAN0 64

0x0840–0x097F Reserved 320

0x0980–0x0987 LINPHY (S12ZVML derivatives) 8

0x0980–0x0987 HV Physical Interface

(S12ZVM32, S12ZVM16 derivatives)

0x0988–0x098F Reserved 8

0x0990–0x0997 CANPHY (ZVMC256 only) 8

0x0998–0x0FFF Reserved 1640

1. Reading from the first 16 locations in this reserved range returns undefined data

2. Address range = 0x0690-0x069F on Maskset N06E

Table 1-5. Module Register Address Ranges

Address Module Size

(Bytes)

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Figure 1-2. MC9S12ZVM-Family Global Memory Map. (See Table 1-3 for individual device details)

0x00_1000

0x00_0000

0x10_0000

0x1F_4000

0x80_0000

0xFF_FFFF

RAM

EEPROM

Unmapped

Program NVM

4 KB

max. 1 MByte - 4 KB

max. 1 MByte - 48 KB

max. 8 MB

6 MByte

High address aligned

Low address aligned

0x1F_8000

Unmapped

address range

0x1F_C000

Reserved (read only) 6 KB

NVM IFR 256 Byte

Reserved 512 Byte

0x20_0000

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1.6.2 Part ID Assignments

The part ID is located in four 8-bit registers at addresses 0x0000-0x0003. The read-only value is a unique

part ID for each revision of the chip. Table 1-6 shows the assigned part ID number and mask set number.

The shaded part ID numbers are not production mask sets.

1.7 Signal Description and Device Pinouts

This section describes signals that connect off-chip. It includes pin out diagrams a table of signal

properties, and detailed discussion of signals. Internal inter module signal mapping at device level is

described in 1.8 Internal Signal Mapping.

Table 1-6. Assigned Part ID Numbers

Device Mask Set Number Part ID Option

MC9S12ZVMC256 0N00R 0x00180000 CAN

MC9S12ZVMC256 1N00R 0x00180100 CAN

MC9S12ZVML12 N06E 0x00170000 LIN

MC9S12ZVMC12 N06E 0x00170001 CAN-VREG

MC9S12ZVML12 0N95G 0x00172000 LIN

MC9S12ZVMC12 0N95G 0x00172001 CAN-VREG

MC9S12ZVML12 1N95G 0x00172100 LIN

MC9S12ZVML64 1N95G 0x00172100 LIN

MC9S12ZVML32 1N95G 0x00172100 LIN

MC9S12ZVMC12 1N95G 0x00172101 CAN-VREG

MC9S12ZVMC64 1N95G 0x00172101 CAN-VREG

MC9S12ZVML12 2N95G 0x00172200 LIN

MC9S12ZVML64 2N95G 0x00172200 LIN

MC9S12ZVML32 2N95G 0x00172200 LIN

MC9S12ZVMC12 2N95G 0x00172201 CAN-VREG

MC9S12ZVMC64 2N95G 0x00172201 CAN-VREG

MC9S12ZVML12 3N95G 0x00172300 LIN

MC9S12ZVML64 3N95G 0x00172300 LIN

MC9S12ZVML32 3N95G 0x00172300 LIN

MC9S12ZVMC12 3N95G 0x00172301 CAN-VREG

MC9S12ZVMC64 3N95G 0x00172301 CAN-VREG

MC9S12ZVML31 0N14N 0x00150000 LIN

MC9S12ZVM32 0N14N 0x00150000 HV Physical Interface

MC9S12ZVM16 0N14N 0x00150000 HV Physical Interface

MC9S12ZVML31 1N14N 0x00150100 LIN

MC9S12ZVM32 1N14N 0x00150100 HV Physical Interface

MC9S12ZVM16 1N14N 0x00150100 HV Physical Interface

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1.7.1 Pin Assignment Overview

Table 1-7 provides a summary of which ports are available.

NOTE

To avoid current drawn from floating inputs, all non-bonded pins should be

configured as output or configured as input with a pull up or pull down

device enabled

1.7.2 Detailed External Signal Descriptions

This section describes the properties of signals available at device pins. Signal names associated with

modules that can be instantiated more than once on an S12 are indexed, even if the module is only

instantiated once on the MC9S12ZVM-Family. If a signal already includes a ch annel number , then the index

is inserted before the channel number. Thus ANx_y corresponds to AN instance x, channel number y.

1.7.2.1 RESET — External Reset Signal

The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to

a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has

an internal pull-up device.

1.7.2.2 TEST — Test Pin

This input only pin is reserved for factory test. This pin has an internal pull-down device.

NOTE

The TEST pin must be tied to ground in all applications.

Table 1-7. Port Availability by Option

Port 80 LQFP 64 LQFP 48LQFP

Port AD PAD[15:0] PAD[8:0] PAD[8],PAD[2:0]

Port E PE[1:0] PE[1:0] PE[1:0]

Port L PL[0] — —

Port P PP[1:0] PP[2:0] PP[0]

Port S PS[3:0] PS[5:0] PS[1:0]

Port T PT[3:0] PT[3:0] PT[0]

sum of ports292410

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1.7.2.3 MODC — Mode C Signal

The MODC signal is used as an MCU operating mode select during reset. The state of this signal is latched

to the MODC bit at the rising edge of RESET. The signal has an internal pull-up device.

1.7.2.4 PAD[15:0] / KWAD[15:0] — Port AD, Input Pins of ADC

These are general-purpose input or output signals. The signals can be configured on per signal basis as

interrupt inputs with wake-up capability (KWAD). These signals can have a pull-up or pull-down device

selected and enabled on per signal basis. During and out of reset the pull devices are disabled.

1.7.2.5 PE[1:0] — Port E I/O Signals

PE[1:0] are general-purpose input or output signals. The signals can have a pull-down device, enabled by

on a per pin basis. Out of reset the pull-down devices are enabled.

1.7.2.6 PL[0] — Port L Input Signal

PL[0] is a high voltage input port. The port can be configured as interrupt input with wake-up capability

(KWL[0]). The input voltage is also scaled and mapped to an internal ADC channel.

1.7.2.7 PP[2:0] / KWP[2:0] — Port P I/O Signals

PP[2:0] are general-purpose input or output signals. The signals can be configured on per signal basis as

interrupt inputs with wake-up capability (KWP[2:0]). They can have a pull-up or pull-down device

selected and enabled on per signal basis. During and out of reset the pull devices are disabled.

1.7.2.8 PS[5:0] / KWS[5:0] — Port S I/O Signals

PS[5:0] are general-purpose input or output signals. The signals can be configured on per signal basis as

interrupt inputs with wake-up capability (KWS[5:0]). They can have a pull-up or pull-down device

selected and enabled on per signal basis. During and out of reset the pull-up devices are enabled.

1.7.2.9 PT[3:0] — Port T I/O Signals

PT[3:0] are general-purpose input or output signals. They can have a pull-up or pull-down device selected

and enabled on per signal basis. During and out of reset the pull devices are disabled.

1.7.2.10 AN0_[7:0], AN1_[7:0]— ADC Input Signals

These are the analog inputs of the Analog-to-Digital Converters. These are mapped to PAD port pins. The

number of analog input channels connected to PAD port pins is package option dependent.

1.7.2.11 VRH0_[2:0], VRL0_[1:0] — ADC0 Reference Signals

VRH0_[2:0] and VRL0_[1:0] are the reference voltage signals for the analog-to-digital converter ADC0.

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1.7.2.12 VRH 1_[2:0], VRL1_[1:0] — ADC1 Reference Signals

VRH1_[2:0] and VRL1_[1:0] are the reference voltage signals for the analog-to-digital converter ADC1.

1.7.2.13 SPI0 Signals

1.7.2.13.1 SS0 Signal

This signal is associated with the slave select SS functionality of the serial peripheral interface SPI0.

1.7.2.13.2 SCK0 Signal

This signal is associated with the serial clock SCK functionality of the serial peripheral interface SPI0.

1.7.2.13.3 MISO0 Signal

This signal is associated with the MISO functionality of the serial peripheral interface SPI0. This signal

acts as master input during master mode or as slave output during slave mode.

1.7.2.13.4 MOSI0 Signal

This signal is associated with the MOSI functionality of the serial peripheral interface SPI0. This signal

acts as master output during master mode or as slave input during slave mode

1.7.2.14 SCI[1:0] Signals

1.7.2.14.1 RXD[1:0] Signals

These signals are associated with the receive functionality of the serial communication interfaces

(SCI[1:0]).

1.7.2.14.2 TXD[1:0] Signals

These signals are associated with the transmit functionality of the serial communication interfaces

(SCI[1:0]).

1.7.2.15 CAN0 Signals

1.7.2.15.1 RXCAN0 Signal

This signal is associated with the receive functionality of the scalable controller area network controller

(MSCAN0).

1.7.2.15.2 TXCAN0 Signal

This signal is associated with the transmit functionality of the scalable controller area network controller

(MSCAN0).

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1.7.2.16 Timer IOC0_[3:0] Signals

The signals IOC0_[3:0] are associated with the input capture or output compare functionality of the timer

(TIM0) module.

1.7.2.17 Timer IOC1_[1:0] Signals (ZVMC256 only)

The signals IOC1_[1:0] are associated with the input capture or output compare functionality of the timer

(TIM1) module.

1.7.2.18 PWM 1_[ 5:0] Sign als

The signals PWM1_[5:0] are associated with the PMF module digital channel outputs.

1.7.2.19 PWM 0_[7,5,3,1] Signals (ZVMC256 only)

The PWM0 signals are associated with the PWM0 module digital channel outputs.

1.7.2.20 PTU Signals

1.7.2.20.1 PTUT[1:0] Signals

These signals are the PTU trigger output signals. These signals are routed to pins for debugging purposes.

1.7.2.20.2 PTURE Signal

This signal is the PTU reload enable output signal. This signal is routed to a pin for debugging purposes.

1.7.2.21 Interrupt Signals — IRQ and XIRQ

IRQ is a maskable level or falling edge sensitive input. XIRQ is a non-maskable level-sensitive interrupt.

1.7.2.22 Oscillator and Clock Signals

1.7.2.22.1 Oscillator Pins — EXTAL and XTAL

EXTAL and XT AL are the crystal driver and external clock pins. On reset all the device clocks are derived

from the internal PLLCLK, independent of EXTAL and XTAL. XTAL is the oscillator output.

1.7.2.22.2 ECLK

This signal is associated with the output of the bus clock (ECLK).

NOTE

This feature is only intended for debug purposes at room temperature.

It must not be used for clocking external devices in an application.

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1.7.2.23 BDC and Debug Signals

1.7.2.23.1 BKGD — Background Debug signal

The BKGD signal is used as a pseudo-open-drain signal for the background debug communication. The

BKGD signal has an internal pull-up device.

1.7.2.23.2 PDO — Profiling Data Output

This is the profiling data output signal used when the DBG module profiling feature is enabled. This signal

is output only and provides a serial, encoded data stream that can be used by external development tools

to reconstruct the internal CPU code flow.

1.7.2.23.3 PDOCLK — Profiling Data Output Clock

This is the PDO clock signal used when the DBG module profiling feature is enabled. This signal is output

only. During code profiling this is the clock signal that can be used by external development tools to

sample the PDO signal.

1.7.2.23.4 DBGEEV — External Event Input

This signal is the DBG external event input. It is input only. W ithin the DBG module, it allows an external

event to force a state sequencer transition, or trace buffer entry, or to gate trace buffer entries. A falling

edge at the external event signal constitutes an event. Rising edges have no effect. The maximum

frequency of events is half the internal core bus frequency.

1.7.2.24 FAULT5 — External Fault Input

This is the PMF fault input signal, with configurable polarity, that can be used to disable PMF operation

when asserted. Asynchronous shutdown of the GDU outputs HG[2:0] and LG[2:0] is not supported. Select

QSMPm[1:0] > 0 in PMF.

1.7.2.25 LIN Physical Layer Sign als (Not Available On ZVMC256)

1.7.2.25.1 LIN0

On S12ZVML derivatives this pad is connected to the single-wire LIN data bus.

On the S12ZVM32 and S12ZVM16 derivatives this is a single pin bidirectional high voltage physical

interface. It operates in the VSUP voltage range. It can be connected to an external single-wire data bus.

1.7.2.25.2 LP0TXD

This is the LIN physical layer (or HV physical interface) transmitter input signal.

1.7.2.25.3 LP0RXD

This is the LIN physical layer (or HV physical interface) receiver output signal.

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1.7.2.25.4 LP0DR1

This is the LIN (or HV physical interface) LP0DR1 register bit, visible at the designated pin for debug

purposes.

1.7.2.25.5 LGND — LINPHY Ground Pin

On S12ZVM(L) parts LGND is the ground pin for the LIN physical layer LINPHY. This signal must be

connected to board ground, even if the LINPHY is not used.

On S12ZVM32 and S12ZVM16 parts this the ground pin for the HV physical interface. It must be

connected to board ground even when the HV physical interface is not used.

1.7.2.26 CAN Physical Layer Signals (ZVMC256 Only)

1.7.2.26.1 CANH0 — CAN Bus High Pin0

The CANH0 signal either connects directly to CAN bus high line or through an optional external common

mode choke.

1.7.2.26.2 CANL0 — CAN Bus Low Pin0

The CANL0 signal either connects directly to CAN bus low line or through an optional external common

mode choke.

1.7.2.26.3 SPLIT0 — CAN Bus Termination Pin0

The SPLIT0 pin can drive a 2.5 V bias for bus termination purpose (CAN bus middle point). Usage of this

pin is optional and depends on bus termination strategy for a given bus network.

1.7.2.26.4 CPTXD0

This is the CAN physical layer transmitter input signal.

1.7.2.26.5 CPRXD0

This is the CAN physical layer receiver output signal.

1.7.2.26.6 CPDR0

This is the CAN physical layer direct control output signal.

1.7.2.26.7 BCTLC

BCTLC provides the base current of an external bipolar that supplies an external CAN physical interface.

This signal is only available on S12ZVMC versions. If not used BCTLC should be left unconnected.

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1.7.2.26.8 VDDC (Only Available On S12ZVMC Versions)

VDDC is the CANPHY supply. This is the output voltage of the external bipolar, whose base current is

supplied by BCTLC. It is fed back to the MCU for regulation. On the ZVMC128 a diode is recommended

between VDDA and VDDC, whereby the anode is connected to VDDC.

1.7.2.26.9 VSSC (Only Available On ZVMC256)

VSSC is the CANPHY ground.

1.7.2.27 Gate Drive Unit (GDU) Signals

These are associated with driving the external FETs.

1.7.2.27.1 HD — FET Predriver High side Drain Input

This is the drain connection of the external high-side FET s. The voltage present at this input is scaled down

by an internal voltage divider, and can be routed to the internal ADC via an analog multiplexer.

1.7.2.27.2 VBS[2:0] - Bootstrap Capacitor Connections

These signals are the bootstrap capacitor connections for phases HS[2:0]. The capacitor connected

between HS[2:0] and these signals provides the gate voltage and current to drive the external FET.

1.7.2.27.3 HG[2:0] - High-Side Gate signals

The pins are the gate drives for the three high-side power FETs. The drivers provide a high current with

low impedance to turn on and off the high-side power FETs.

1.7.2.27.4 HS[2:0] - High-Side Source signals

The pins are the source connection for the high-side power FETs and the drain connection for the low-side

power FETs. The low voltage end of the bootstrap capacitor is also connected to this pin.

1.7.2.27.5 VLS[2:0] - Voltage Supply for Low -Side Drivers

The pins are the voltage supply pins for the three low-side FET pre-drivers. These pins should be

connected to the voltage regulator output pin VLS_OUT.

1.7.2.27.6 LG[2:0] - Low-Side Gate signals

The pins are the gate drives for the low-side power FETs. The drivers provide a high current with low

impedance to turn on and off the low-side power FETs.

1.7.2.27.7 LS[2:0] - Low-Side Source Signals

The pins are the low-side source connections for the low-side power FETs. The pins are the power ground

pins used to return the gate currents from the low-side power FETs.

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1.7.2.27.8 LD[2:0] - Low-Side Drain Signals (ZVMC256 Only)

The pins are the low-side drain connections for the low-side power FETs. The pins can be used to monitor

the low-side power FETs for desaturation conditions.

1.7.2.27.9 CP - Charge Pump Output Signal

This pin is the switching node of the charge pump circuit. The supply voltage for charge pump driver is

the output of the voltage regulator VLS_OUT. The output voltage of this pin switches typically between

0V and 11V. Must be left unconnected if not used.

1.7.2.27.10 VCP - Charge Pump Input For High-Side Driver Supply

This is the charge pump input for the FET high-side gate drive supply circuit. The pin must be left

unconnected if not used.

1.7.2.27.11 BST - Boost Signal

This pin provides the basic switching elements required to implement a boost converter for low battery

voltage conditions. This requires external diodes, capacitors and a coil. This pin must be left unconnected

if not used.

The boost function must not be used on devices of the maskset 2N95G, because these devices use the

VSUP pin as the LINPHY supply. Thus boosting the VSUP voltage can cause LIN supply voltage offsets

to other devices on the LIN bus.

1.7.2.27.12 VSSB - Boost Ground Signal

This pin is a separate ground pin for the on chip boost converter switching device.

1.7.2.27.13 VLS_OUT - 11V Voltage Regulator Output

This pin is the output of the integrated voltage regulator. The output voltage is typically VVLS=11V. The

input voltage to the voltage regulator is the VSUP pin.

1.7.2.27.14 AMPP[1:0] - Current Sense Amplifier Non-Inverting Input

These are the current sense amplifier non-inverting inputs.

1.7.2.27.15 AMPM[1:0] - Current Sense Amplifier Inverting Input

These are the current sense amplifier inverting inputs.

1.7.2.27.16 AMP[1:0] - Current Sense Amplifier Output

These are the current sense amplifier outputs.

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1.7.2.28 High Current Output — EVDD1

This is a high current, low voltage drop output intended for supplying external devices in a range of up to

20mA. Configuring the pin direction as output automatically enables the high current capability.

1.7.3 Power Supply And Voltage Regulator Related Pins

The power and ground pins are described below. Because fast signal transitions place high, short-duration

current demands on the power supply , use bypass capacitors with high-frequency characteristics and place

them as close to the MCU as possible.

NOTE

All ground pins must be connected together in the application.

1.7.3.1 VDDX1, VDDX2, VSSX1 — Digital I/O Power and Ground Pins

VDDX1, VDDX2 are voltage regulator outputs to supply the digital I/O drivers.

The VSSX1 pin is the ground pin for the digital I/O drivers.

Bypass requirements on VDDX2, VDDX1, VSSX1 depend on how heavily the MCU pins are loaded.

1.7.3.2 BCTL

BCTL is the ballast connection for the on chip voltage regulator . It provides the base current of an external

bipolar for the VDDX and VDDA supplies. If not used BCTL should be left unconnected.

1.7.3.3 VDDA, VSSA — Power Supply Pins For ADC

These are the power supply and ground pins for the analog-to-digital converter and the voltage regulator.

1.7.3.4 VDD, VSS2 — Core Power And Ground Pins

The VDD voltage supply of nominally 1.8V is generated by the internal voltage regulator. The return

current path is through the VSS1 pin on ZVMC256, or VSS2 pin on other devices.

1.7.3.5 VDDF, VSS1— NVM Power And Ground Pins

The VDDF voltage supply of nominally 2.8V is generated by the internal voltage regulator . The return path

is through the VSS1 pin. On ZVMC256, the return current path is through the VSS1 and VSSX pins.

1.7.3.6 VSUP — Voltage Supply Pin for Voltage Regulator

VSUP is the main supply pin typically coming from the car battery/alternator in the 12V supply voltage

range. This is the voltage supply input from which the voltage regulator generates the on chip voltage

supplies. It must be protected externally against a reverse battery connection.

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1.7.3.7 VDDS1 — 5V Supply Pin For External Devices (ZVMC256 Only)

This provides a regulated, short circuit protected, 5V supply for external devices. This is the output voltage

of the external bipolar, whose base current is supplied by BCTLS1. It is fed back to the MCU for

regulation.

1.7.3.8 BCTLS1 (ZVMC256 Only)

BCTLS1 provides the base current of an external bipolar that supplies VDDS1. If not used BCTLS1

should be left unconnected.

1.7.3.9 SNPS1 (ZVMC256 Only)

SNPS1 is the sense input associated with the VDDS1 regulator. The voltage regulator uses it to detect a

short circuit or over current condition.

1.7.3.10 VDDS2 — 5V Supply Pin For External Devices (ZVMC256 Only)

This provides a regulated, short circuit protected, 5V supply for external devices. This is the output voltage

of the external bipolar, whose base current is supplied by BCTLS2. It is fed back to the MCU for

regulation.

1.7.3.11 BCTLS2 (ZVMC256 Only)

BCTLS2 provides the base current of an external bipolar that supplies VDDS2. If not used BCTLS2

should be left unconnected.

1.7.3.12 SNPS2 (ZVMC256 Only)

SNPS2 is the sense input associated with the VDDS2 regulator. The voltage regulator uses it to detect a

short circuit or over current condition.

1.7.4 Package and Pinouts

The following package options are offered.

• 80LQFP-EP (exposed pad) with internal CANPHY and CAN VREG.

• 64LQFP-EP (exposed pad) with internal LINPHY or HV physical interface.

• 64LQFP-EP (exposed pad) with CAN VREG to support a low cost external CANPHY.

• 48LQFP-EP (exposed pad) with internal LINPHY or HV physical interface

The exposed pad must be connected to a grounded contact pad on the PCB.

The exposed pad has an electrical connection within the package to VSSFLAG (VSSX die connection).

The pin out details are shown in the following diagrams. Signals in brackets denote routing options.

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52 NXP Semiconductors

Figure 1-3. S12ZVMC256 80-pin LQFP pin out

VSUP

VLS_OUT

VSSB

BST

VCP

PL0

BCTL

SNPS1

BCTLS1

VDDS1

SNPS2

BCTLS2

VDDS2

LD0

LD1

LD2

PAD0

PAD1

HS1

HG1

VBS1

VLS1

LG1

LS1

LS2

LG2

VLS2

VBS2

HG2

HS2

HS0

HG0

VBS0

VLS0

LG0

LS0

SPLIT0

CANL0

PAD2

PAD3

PAD4

PAD5

PAD6

PAD7

PAD8

VDDA

VSSA

PAD9

PAD10

PAD11

PAD12

PAD13

PAD14

PAD15

BCTLC

VDDC

CANH0

VSSC

BKGD

VSSX1

VDDX1

PP0

PP1

VDD

VSS1

VDDF

PS0

PS1

PS2

PS3

TEST

PE0

PE1

RESET

PT3

PT2

PT1

PT0

S12ZVMC256

80-pin LQFP-EP

Top view

The exposed pad on the package bottom must be

connected to a grounded contact pad on the PCB.

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Figure 1-4. S12ZVM and S12ZVML option 64-pin LQFP pin out

HG1

VBS1

VLS1

LG1

LS1

LS2

LG2

VLS2

VBS2

HG2

HS2

HS0

HG0

VBS0

VLS0

LG0

VDDX2

TEST

VSS2

VDD

AN0_0 / AMP0 / KWAD0 / PAD0

AN0_1 / AMPM0 / KWAD1 / PAD1

AN0_2 / AMPP0 / KWAD2 / PAD2

AN0_3 / KWAD3 / PAD3

AN0_4 / KWAD4 / PAD4

AN1_0 / AMP1 / KWAD5 / PAD5

(SS0) / AN1_1 / AMPM1 / KWAD6 / PAD6

AN1_2 / AMPP1 / KWAD7 / PAD7

VRH / AN1_3 / KWAD8 / PAD8

VDDA

VSSA

LS0

LIN0

MODC / BKGD

PTUT0 / (IOC0_1) / (LP0RXD) / RXCAN0 / RXD1 / KWS0 / PS0

PTUT1 / (IOC0_2) / (LP0TXD) / TXCAN0 / TXD1 / KWS1 / PS1

MISO0 / (RXD1) / KWS2 / PS2

MOSI0 / (TXD1) / DBGEEV / KWS3 / PS3

PDOCLK / SCK0 / KWS4 / PS4

PDO / SS0 / KWS5 / PS5

BCTL

VCP

BST

VSSB

VLS_OUT

VSUP

LGND

VSSX1

VDDX1

PP0 / EVDD1 / KWP0 / (PWM0_0) / ECLK / FAULT5 / XIRQ

PP1 / KWP1 / (PWM0_1) / IRQ

PP2 / KWP2 / (PWM0_2)

VDDF

VSS1

PE0 / EXTAL

PE1 / XTAL

RESET

PT3 / IOC0_3 / (SS0)

PT2 / IOC0_2 / (PWM0_5) / (SCK0)

PT1 / IOC0_1 / (PWM0_4) / (MOSI0) / (TXD0) / LP0DR1 / PTURE

PT0 / IOC0_0 / (PWM0_3) / (MISO0) / (RXD0)

HS1

S12ZVML and S12ZVM

option

64-pin LQFP-EP

The exposed pad on the package bottom must be

connected to a grounded contact pad on the PCB.

On MC9S12ZVM options the LIN0 pin is mapped to

the HV physical interface function

IOC0_1 and IOC0_2 can be routed to Port S on the

ZVMC256, ZVML31, ZVM32 and ZVM16 devices but

not on other devices.

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54 NXP Semiconductors

Figure 1-5. S12ZVMC Option 64-pin LQFP pin out

S12ZVMC Option

64-pin LQFP-EP

HG1

VBS1

VLS1

LG1

LS1

LS2

LG2

VLS2

VBS2

HG2

HS2

HS0

HG0

VBS0

VLS0

LG0

BCTLC

MODC / BKGD

PTUT0 / RXCAN0 / RXD1 / KWS0 / PS0

PTUT1 / TXCAN0 / TXD1 / KWS1 / PS1

MISO0 / (RXD1) / KWS2 / PS2

MOSI0 / (TXD1) / DBGEEV / KWS3 / PS3

PDOCLK / SCK0 / KWS4 / PS4

PDO / SS0 / KWS5 / PS5

BCTL

VCP

BST

VSSB

VLS_OUT

VSUP

VDDC

VSSX1

VDDX1

PP0 / EVDD1 / KWP0 / (PWM0_0) / ECLK / FAULT5 / XIRQ

PP1 / KWP1 / (PWM0_1) / IRQ

PP2 / KWP2 / (PWM0_2)

VDDF

VSS1

PE0 / EXTAL

PE1 / XTAL

RESET

PT3 / IOC0_3 / (SS0)

PT2 / IOC0_2 / (PWM0_5) / (SCK0)

PT1 / IOC0_1 / (PWM0_4) / (MOSI0) / (TXD0) / PTURE

PT0 / IOC0_0 / (PWM0_3) / (MISO0) / (RXD0)

HS1

VDDX2

TEST

VSS2

VDD

AN0_0 / AMP0 / KWAD0 / PAD0

AN0_1 / AMPM0 / KWAD1 / PAD1

AN0_2 / AMPP0 / KWAD2 / PAD2

AN0_3 / KWAD3 / PAD3

AN0_4 / KWAD4 / PAD4

AN1_0 / AMP1 / KWAD5 / PAD5

(SS0) / AN1_1 / AMPM1 / KWAD6 / PAD6

AN1_2 / AMPP1 / KWAD7 / PAD7

VRH / AN1_3 / KWAD8 / PAD8

VDDA

VSSA

LS0

The exposed pad on the package bottom must be

connected to a grounded contact pad on the PCB.

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Figure 1-6. S12ZVM, S12ZVML Option 48-pin LQFP

VBS1

LG1

LS1

LS2

LG2

VLS2

VBS2

HG2

HS2

HS0

HG0

VBS0

VDDX2

TEST

VSS2

VDD

AN0_0 / AMP0 / KWAD0 / PAD0

AN0_1 / AMPM0 / KWAD1 / PAD1

AN0_2 / AMPP0 / KWAD2 / PAD2

VRH / AN1_3 / KWAD8 / PAD8

VDDA

VSSA

LS0

LG0

LIN0

MODC / BKGD

PTUT0 / (IOC0_1) / (LP0RXD) / RXD1 / KWS0 / PS0

PTUT1 / (IOC0_2) / (LP0TXD) / TXD1 / KWS1 / PS1

BCTL

VCP

BST

VSSB

VLS_OUT

VSUP

LGND

VSSX1

VDDX1

PP0 / EVDD1 / KWP0 / (PWM0_0) / ECLK / FAULT5 / XIRQ

VDDF

VSS1

PE0 / EXTAL

PE1 / XTAL

RESET

PT0 / IOC0_0 / (PWM0_3) / (RXD0)

HS1

HG1

S12ZVML and S12ZVM

Options

48-pin LQFP-EP

The exposed pad on the package bottom must be

connected to a grounded contact pad on the PCB.

The LIN0 pin is mapped to the HV physical interface

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56 NXP Semiconductors

1.7.4.1 Pin Summary And Signal Mapping

Table 1-8. Pin Summary For 64-Pin and 48-Pin Pa ckage Options (Sheet 1 of 4)

LQFP Option Function

(Priority and device dependencies specified in PIM

chapter) Power

Supply

Internal Pull

Resistor

MC 48 Pin 1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

1—1LIN0———————Up

(weak

)

—1—BCTLC————————

222BKGDMODC————V

DDX —Up

333PS0

(1) KWS0 RXD1 RXCAN0 LP0RXD PTUT0 /

IOC0_1

VDDX PERS/

PPSS

444PS1

(1) KWS1 TXD1 TXCAN0 LP0TXD PTUT1 /

IOC0_2

VDDX PERS/

PPSS

5 5 — PS2 KWS2 RXD1 MISO0 — — VDDX PERS/

PPSS

6 6 — PS3 KWS3 DBGEE

TXD1 MOSI0 — VDDX PERS/

PPSS

7 7 — PS4 KWS4 SCK0 PDOCLK — — VDDX PERS/

PPSS

8 8 — PS5 KWS5 SS0 PDO — — VDDX PERS/

PPSS

995BCTL————————

10106HD————————

11117VCP————————

12128BST————————

13 13 9 VSSB ————————

141410CP————————

15 15 11 VLS_OU

————————

161612VSUP—————V

SUP ——

171713VDDX2—————V

DDX ——

181814TEST——————RESET Down

19 19 15 VSS2 ————————

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202016VDD—————V

DD ——

21 21 17 PAD0 KWAD0 AN0_0 AMP0 — — VDDA PERADL

/PPSAD

Off

22 22 18 PAD1 KWAD1 AN0_1 AMPM0 — — VDDA PERADL

/PPSAD

Off

23 23 19 PAD2 KWAD2 AN0_2 AMPP0 — — VDDA PERADL

/PPSAD

Off

24 24 — PAD3 KWAD3 AN0_3 — — — VDDA PERADL

/PPSAD

Off

25 25 — PAD4 KWAD4 AN0_4 — — — VDDA PERADL

/PPSAD

Off

26 26 — PAD5 KWAD5 AN1_0 AMP1 — — VDDA PERADL

/PPSAD

Off

27 27 — PAD6 KWAD6 AN1_1 AMPM1 SS0 — VDDA PERADL

/PPSAD

Off

28 28 — PAD7 KWAD7 AN1_2 AMPP1 — — VDDA PERADL

/PPSAD

Off

29 29 20 PAD8 KWAD8 AN1_3 VRH0_0 VRH1_0 — VDDA PERAD

H/PPSA

Off

30 30 21 VDDA VRH0_1 VRH1_1 — — — VDDA ——

31 31 22 VSSA VRL0_

[1:0]

VRL1_

[1:0]

———V

DDA ——

323223LS0————————

333324LG0————————

3434—VLS0————————

35 35 25 VBS0 ————————

Table 1-8. Pin Summary For 64-Pin and 48-Pin Pa ckage Options (Sheet 2 of 4)

LQFP Option Function

(Priority and device dependencies specified in PIM

chapter) Power

Supply

Internal Pull

Resistor

MC 48 Pin 1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

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58 NXP Semiconductors

363626HG0————————

373727HS0————————

383828HS2————————

393929HG2————————

40 40 30 VBS2 ————————

414131VLS2————————

424232LG2————————

434333LS2————————

444434LS1————————

454535LG1————————

4646—VLS1————————

47 47 36 VBS1 ————————

484837HG1————————

494938HS1————————

50 50 39 PT0 IOC0_0 PWM1_3 MISO0 RXD0 — VDDX PERT/

PPST

Off

51 51 — PT1 IOC0_1 PWM1_4 MOSI0 TXD0 LP0DR1/

PTURE

VDDX PERT/

PPST

Off

52 52 — PT2 IOC0_2 PWM1_5 SCK0 — — VDDX PERT/

PPST

Off

53 53 — PT3 IOC0_3 SS0 — — — VDDX PERT/

PPST

Off

54 54 40 RESET —————V

DDX TEST pin Up

555541PE1XTAL————V

DDX PERE/

PPSE

Down

565642PE0EXTAL————V

DDX PERE/

PPSE

Down

57 57 43 VSS1 ————————

585844VDDF—————V

DDF ——

Table 1-8. Pin Summary For 64-Pin and 48-Pin Pa ckage Options (Sheet 3 of 4)

LQFP Option Function

(Priority and device dependencies specified in PIM

chapter) Power

Supply

Internal Pull

Resistor

MC 48 Pin 1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

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NXP Semiconductors 59

59 59 — PP2 KWP2 PWM1_2 — — — VDDX PERP/

PPSP

Off

60 60 — PP1 KWP1 PWM1_1 IRQ — — VDDX PERP/

PPSP

Off

61 61 45 PP0 /

EVDD1

KWP0 PWM1_0 ECLK FAULT5 XIRQ VDDX PERP/

PPSP

Off

626246VDDX1—————V

DDX ——

63 63 47 VSSX1 ————————

64—48LGND————————

—64—VDDC————————

1. IOC signal only available on ZVML31, ZVM32 and ZVM16 on this pin.

Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 1 of 5)

#Pin

Name

Function

(Priority and routing options defined in PIM chapter) Supply

Internal Pull

Resistor

1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. 6th

Func. 7th

Func. CTRL Reset

State

1VSUP—————— V

SUP ——

2 VLS_O

—————— V

SUP ——

3CP—————— ———

4VSSB—————— ———

5BST—————— ———

6VCP—————— ———

7HD—————— ———

8 PL0 HVI0 KWL0 IOC0_2 — — — — — —

9BCTL—————— ———

10SNPS1—————— ———

Table 1-8. Pin Summary For 64-Pin and 48-Pin Pa ckage Options (Sheet 4 of 4)

LQFP Option Function

(Priority and device dependencies specified in PIM

chapter) Power

Supply

Internal Pull

Resistor

MC 48 Pin 1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. CTRL Reset

State

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11 BCTLS

—————— ———

12VDDS1VRH0_1VRH1_1———— ———

13SNPS2—————— ———

14 BCTLS

—————— ———

15VDDS2VRH0_2VRH1_2———— ———

16LD0—————— ———

17LD1—————— ———

18LD2—————— ———

19 PAD0 KWAD0 AN0_0 AMP0 — — — VDDA PERAD

L/PPSA

Off

20 PAD1 KWAD1 AN0_1 AMPM0 — — — VDDA PERAD

L/PPSA

Off

21 PAD2 KWAD2 AN0_2 AMPP0 — — — VDDA PERAD

L/PPSA

Off

22PAD3KWAD3AN0_3———— V

DDA PERAD

L/PPSA

Off

23PAD4KWAD4AN0_4———— V

DDA PERAD

L/PPSA

Off

24 PAD5 KWAD5 AN1_0 AMP1 — — — VDDA PERAD

L/PPSA

Off

25 PAD6 KWAD6 AN1_1 SS0 AMPM1 — — VDDA PERAD

L/PPSA

Off

26 PAD7 KWAD7 AN1_2 AMPP1 — — — VDDA PERAD

L/PPSA

Off

27PAD8KWAD8AN1_3———— V

DDA PERAD

H/PPS

ADH

Off

Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 2 of 5)

#Pin

Name

Function

(Priority and routing options defined in PIM chapter) Supply

Internal Pull

Resistor

1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. 6th

Func. 7th

Func. CTRL Reset

State

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28VDDAVRH0_0VRH1_0———— V

DDA ——

29 VSSA VRL0_

[1:0]

VRL1_

[1:0]

—————V

DDA ——

30PAD9KWAD9AN1_4—————V

DDA PERAD

H/PPS

ADH

Off

31 PAD10 KWAD1

AN1_5—————V

DDA PERAD

H/PPS

ADH

Off

32 PAD11 KWAD1

AN1_6—————V

DDA PERAD

H/PPS

ADH

Off

33 PAD12 KWAD1

AN1_7—————V

DDA PERAD

H/PPS

ADH

Off

34 PAD13 KWAD1

AN0_5PTURE————V

DDA PERAD

H/PPS

ADH

Off

35 PAD14 KWAD1

AN0_6PDO————V

DDA PERAD

H/PPS

ADH

Off

36 PAD15 KWAD1

AN0_7 PDOCL

————V

DDA PERAD

H/PPS

ADH

Off

37BCTLC———————V

DDC ——

38VDDC———————V

DDC ——

39CANH0———————V

DDC ——

40VSSC———————V

DDC ——

41CANL0———————V

DDC ——

42SPLIT0———————V

DDC ——

43LS0——————————

44LG0——————————

45VLS0——————————

46 VBS0 ——————————

47HG0——————————

Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 3 of 5)

#Pin

Name

Function

(Priority and routing options defined in PIM chapter) Supply

Internal Pull

Resistor

1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. 6th

Func. 7th

Func. CTRL Reset

State

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48HS0——————————

49HS2——————————

50HG2——————————

51 VBS2 ——————————

52VLS2——————————

53LG2——————————

54LS2——————————

55LS1——————————

56LG1——————————

57VLS1——————————

58 VBS1 ——————————

59HG1——————————

60HS1——————————

61 PT0 IOC0_0 PWM1_

MISO0 RXD0 PWM0_

——V

DDX PERT/

PPST

Off

62 PT1 IOC0_1 PWM1_

MOSI0 TXD0 — — — VDDX PERT/

PPST

Off

63 PT2 IOC0_2 PWM1_

SCK0 PWM0_

———V

DDX PERT/

PPST

Off

64 PT3 IOC0_3 PWM1_

SS0 PWM0_

———V

DDX PERT/

PPST

Off

65 RESET ———————V

DDX TEST

66PE1XTAL——————V

DDX PERE/

PPSE

Down

67PE0EXTAL——————V

DDX PERE/

PPSE

Down

68TEST————————RESET Down

69 PS3 KWS3 TXD1 MOSI0 CPTXD

DBGEE

IOC1_1 — VDDX PERS/

PPSS

70 PS2 KWS2 RXD1 MISO0 CPRXD

IOC1_0 — — VDDX PERS/

PPSS

Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 4 of 5)

#Pin

Name

Function

(Priority and routing options defined in PIM chapter) Supply

Internal Pull

Resistor

1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. 6th

Func. 7th

Func. CTRL Reset

State

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NXP Semiconductors 63

1.8 Internal Signal Mapping

This section specifies the mapping of inter- module signals at device level.

1.8.1 ADC Connectivity

1.8.1.1 ADC Reference Voltages

The ZVMC256 includes ADC12B_LBA V3 which features VRH_2, VRH_1, VRH_0 and VRL_0. On

these devices for each ADC instance VRH_0 is mapped to VDDA, VRH_1 is mapped to VDDS1 and

VRH_2 is mapped to VDDS2. VRL_0 is mapped to VSSA. Both VDDS1 and VDDS2 must be enabled

by bits in the CPMUVREGCTL register before they can be used as references. When using VDDS1 or

VDDS2 as VRH reference, the reference is impacted by a voltage drop across the internal short circuit

protection switch. This is specified in Section C.1.1.5.

All other devices in the family include ADC12B_LBA V1, which features VRH_1, VRH_0, VRL_1 and

VRL_0. On these devices, for both ADC instances, VRL_0 and VRL_1 are mapped to VSSA, whereby

VRL_0 is the preferred reference for low noise. For both ADC instances VRH_1 is mapped to VDDA and

VRH_0 is mapped to PAD8.

71 PS1 KWS1 TXD1 SCK0 PTUT1 CPDR0 TXCAN

IOC0_2 VDDX PERS/

PPSS

72 PS0 KWS0 RXD1 SS0 PTUT0 RXCAN

IOC0_1 — VDDX PERS/

PPSS

73VDDF———————V

DDF ——

74 VSS1 ———————V

DD ——

75VDD———————V

DD ——

76 PP1 KWP1 PWM1_

PWM0_

IRQ———V

DDX PPRP/

PPSP

Off

77 PP0/

EVDD1

KWP0 PWM1_

ECLK FAULT5 XIRQ — — VDDX PPRP/

PPSP

Off

78VDDX1———————V

DDX ——

79 VSSX1 ———————V

DDX ——

80BKGDMODC——————V

DDX —Up

Table 1-9. Pin Summary For 80-Pin Package Option (ZVMC256 Only) (Sheet 5 of 5)

#Pin

Name

Function

(Priority and routing options defined in PIM chapter) Supply

Internal Pull

Resistor

1st

Func. 2nd

Func. 3rd

Func. 4th

Func. 5th

Func. 6th

Func. 7th

Func. CTRL Reset

State

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64 NXP Semiconductors

1.8.1.2 ADC Internal Channels

The ADC0 and ADC1 internal channel mapping is shown in Table 1-10 and Table 1-11 respectively.

The GDU current sense amplifier outputs are mapped to pins with ADC input functionality. Thus

configuring the ADC to convert these pin channels automatically converts the current sense outputs.

The ADC internal temperature sensors must be calibrated by the user. No electrical parameters are

specified for these sensors. The VREG temperature sensor electrical parameters are given in the

appendices.

1.8.2 Motor Control Loop Signals

The motor control loop signals are described in 1.13.3.1 Motor Control Loop Overview

Table 1-10. Usage of ADC0 Internal Channels

ADCCMD_1 CH_SEL[5:0] ADC Channel Usage

0 0 1 0 0 0 Internal_0 ADC0 temperature sensor

0 0 1 0 0 1 Internal_1 VREG temperature sensor or bandgap (VBG)(1)

1. Selectable in CPMU

0 0 1 0 1 0 Internal_2 GDU phase multiplexer voltage

0 0 1 0 1 1 Internal_3 GDU DC link voltage monitor

0 0 1 1 0 0 Internal_4 BATS VSUP sense voltage

0 0 1 1 0 1 Internal_5 HVI[0](2)

2. ZVMC256 only. On other devices this channel is reserved.

0 0 1 1 1 0 Internal_6 Reserved

0 0 1 1 1 1 Internal_7 Reserved

Table 1-11. Usage of ADC1 Internal Channels

ADCCMD_1 CH_SEL[5:0] ADC Channel Usage

0 0 1 0 0 0 Internal_0 ADC1 temperature sensor

0 0 1 0 0 1 Internal_1 VREG temperature sensor or bandgap (VBG)(1)

1. Selectable in CPMU

0 0 1 0 1 0 Internal_2 GDU phase multiplexer voltage

0 0 1 0 1 1 Internal_3 GDU DC link voltage monitor

0 0 1 1 0 0 Internal_4 Reserved

0 0 1 1 0 1 Internal_5 Reserved

0 0 1 1 1 0 Internal_6 Reserved

0 0 1 1 1 1 Internal_7 Reserved

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1.8.3 Device Level PMF Connectivity

1.8.4 BDC Clock Source Connectivity

The BDC clock, BDCCLK, is mapped to the IRCCLK generated in the CPMU module.

The BDC clock, BDCFCLK is mapped to the device bus clock, generated in the CPMU module.

1.8.5 LINPHY Connectivity

The VLINSUP supply is device dependent.

On ZVML128, ZVMC128, ZVML64, ZVMC64 and ZVML32 devices with the maskset number 2N95G

it is connected to VSUP

On all other devices it is connected to the device HD pin.

The LINPHY0 signals are mapped internally to SCI0. The receiver can be routed to TIM0 input capture

channel3. These routing options are described in detail in the PIM section.

1.8.6 HVPHY Connectivity

The HVPHY signals (S12ZVM32 and S12ZVM16 derivatives only) are mapped internally to SCI0. The

receiver can be routed to TIM0 input capture channel3.

Table 1-12. Mapping of PMF signals

PMF Connection Usage

Channel0 High-Side Gate and Source Pins HG[0], HS[0]

Channel1 Low-Side Gate and Source Pins LG[0], LS[0]

Channel2 High-Side Gate and Source Pins HG[1], HS[1]

Channel3 Low-Side Gate and Source Pins LG[1], LS[1]

Channel4 High-Side Gate and Source Pins HG[2], HS[2]

Channel5 Low-Side Gate and Source Pins LG[2], LS[2]

FAULT5 External FAULT5 pin

FAULT4 HD Over voltage or GDU over current

FAULT3 VLS under voltage

FAULT2 GDU Desaturation[2] or GDU over current

FAULT1 GDU Desaturation[1] or GDU over current

FAULT0 GDU Desaturation[0] or GDU over current

IS2 GDU Phase Status[2]

IS1 GDU Phase Status[1]

IS0 GDU Phase Status[0]

async_event_edge_sel[1:0] Tied to b11 (both edges active)

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1.8.7 FTMRZ Connectivity

The soc_erase_all_req input to the flash module is driven directly by a BDC erase flash request resulting

from the BDC ERASE_FLASH command.

The FTMRZ FCLKDIV register is forced to 0x05 by the BDC ERASE_FLASH command. This

configures the clock frequency correctly for the initial bus frequency on leaving reset. The bus frequency

must not be changed before launching the ERASE_FLASH command.

The device bus frequency, below which the flash wait states can be disabled, is specified in the device

operating conditions table in Table A-6.

1.8.8 CPMU Connectivity

The API clock generated in the CPMU is not mapped to a device pin in the MC9S12ZVM-Family.

1.9 Modes of Operation

The MCU can operate in different modes. These are described in 1.9.1 Chip Configuration Modes.

The MCU can operate in different power modes to facilitate power saving when full system performance

is not required. These are described in 1.9.3 Low Power Modes.

Some modules feature a software programmable option to freeze the module status whilst the background

debug module is active to facilitate debugging. This is referred to as freeze mode at module level.

1.9.1 Chip Configuration Modes

The different modes and the security state of the MCU affect the debug features (enabled or disabled).

The operating mode out of reset is determined by the state of the MODC signal during reset (Table 1-13).

The MODC bit in the MODE register shows the current operating mode and provides limited mode

switching during operation. The state of the MODC signal is latched into this bit on the rising edge of

RESET.

1.9.1.1 Normal Single-Chip Mode

This mode is intended for normal device operation. The opcode from the on-chip memory is being

executed after reset (requires the reset vector to be programmed correctly). The processor program is

executed from internal memory.

Table 1-13. Chip Modes

Chip Modes MODC

Normal single chip 1

Special single chip 0

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1.9.1.2 Special Single-Chip Mode

This mode is used for debugging operation, boot-strapping, or security related operations. The background

debug mode (BDM) is active on leaving reset in this mode

1.9.2 Debugging Modes

The background debug mode (BDM) can be activated by the BDC module or directly when resetting into

Special Single-Chip mode. Detailed information can be found in the BDC module section.

Writing to internal memory locations using the debugger, whilst code is running or at a breakpoint, can

change the flow of application code.

The MC9S12ZVM-Family supports BDC communication throughout the device Stop mode. During S top

mode, writes to control registers can alter the operation and lead to unexpected results. It is thus

recommended not to reconfigure the peripherals during STOP using the debugger.

On the S12ZVML and S12ZVMC versions, the DBG module supports breakpoint, tracing and profiling

features. At board level the profiling pins can use the same 6-pin connector typically used for the BDC

BKGD pin. The connector pin mapping shown in Figure 1-7 is supported by device evaluation boards and

leading development tool vendors.

Figure 1-7. Standard Debug Connector Pin Mapping

1.9.3 Low Power Modes

The device has two dynamic-power modes (run and wait) and two static low-power modes stop and pseudo

stop). For a detailed description refer to the CPMU section.

• Dynamic power mode: Run

— Run mode is the main full performance operating mode with the entire device clocked. The user

can configure the device operating speed through selection of the clock source and the phase

locked loop (PLL) frequency. To save power, unused peripherals must not be enabled.

• Dynamic power mode: Wait

— This mode is entered when the CPU executes the WAI instruction. In this mode the CPU does

not execute instructions. The internal CPU clock is switched of f. All peripherals can be active

in system wait mode. For further power consumption the peripherals can individually turn off

their local clocks. Asserting RESET, XIRQ, IRQ, or any other interrupt that is not masked,

either locally or globally by a CCR bit, ends system wait mode.

• Static power modes:

Static power (Stop) modes are entered following the CPU STOP instruction unless an NVM

command is active. When no NVM commands are active, the Stop request is acknowledged and

GND BKGD

RST

VDDX

PDO

PDOCLK

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the device enters either Stop or Pseudo Stop mode. Further to the general system aspects of Stop

mode discussed here, the motor control loop specific considerations are described in

Section 1.13.3.10.

— Pseudo-stop: In this mode the system clocks are stopped but the oscillator is still running and

the real time interrupt (RTI), watchdog (COP) and Autonomous Periodic Interrupt (API) may

be enabled. Other peripherals are turned off. This mode consumes more current than system

STOP mode but, as the oscillator continues to run, the full speed wake up time from this mode

is significantly shorter.

— Stop: In this mode the oscillator is stopped and clocks are switched off. The counters and

dividers remain frozen. The autonomous periodic interrupt (API) may remain active but has a

very low power consumption. The key pad, SCI and MSCAN transceiver modules can be

configured to wake the device, whereby current consumption is negligible.

If the BDC is enabled in Stop mode, the VREG remains in full performance mode and the

CPMU continues operation as in run mode. With BDC enabled and BDCCIS bit set, then all

clocks remain active to allow BDC access to internal peripherals. If the BDC is enabled and

BDCCIS is clear, then the BDCSI clock remains active, but bus and core clocks are disabled.

With the BDC enabled during Stop, the VREG full performance mode and clock activity lead

to higher current consumption than with BDC disabled. If the BDC is enabled in Stop mode,

then the BATS voltage monitoring remains enabled.

1.10 Security

The MCU security mechanism prevents unauthorized access to the flash me mory. It must be emphasized

that part of the security must lie with the application code. An extreme example would be application code

that dumps the contents of the internal memory. This would defeat the purpose of security. Also, if an

application has the capability of downloading code through a serial port and then executing that code (e.g.

an application containing bootloader code), then this capability could potentially be used to read the

EEPROM and Flash memory contents even when the microcontroller is in the secure state. In this

example, the security of the application could be enhanced by requiring a response authentication before

any code can be downloaded.

Device security details are also described in the flash block description.

1.10.1 Features

The security features of the S12Z chip family are:

• Prevent external access of the non-volatile memories (Flash, EEPROM) content

• Restrict execution of NVM commands

1.10.2 Securing the Microcontroller

The chip can be secured by programming the security bits located in the options/security byte in the Flash

memory array. These non-volatile bits keep the device secured through reset and power-down.

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This byte can be erased and programmed like any other Flash location. Two bits of this byte are used for

security (SEC[1:0]). The contents of this byte are copied into the Flash security register (FSEC) during a

reset sequence.

The meaning of the security bits SEC[1:0] is shown in Table 1-14. For security reasons, the state of device

security is controlled by two bits. To put the device in unsecured mode, these bits must be programmed to

SEC[1:0] = ‘10’. All other combinations put the device in a secured mode. The recommended value to put

the device in secured state is the inverse of the unsecured state, i.e. SEC[1:0] = ‘01’.

NOTE

Please refer to the Flash block description for more security byte details.

1.10.3 Operation of the Secured Microcontroller

By securing the device, unauthorized access to the EEPROM and Flash memory contents is prevented.

Secured operation has the following effects on the microcontroller:

1.10.3.1 Normal Single Chip M ode (NS)

• Background debug controller (BDC) operation is completely disabled.

• Execution of Flash and EEPROM commands is restricted (described in flash block description).

1.10.3.2 Special Single Chip Mode (SS)

• Background debug controller (BDC) commands are restricted

• Execution of Flash and EEPROM commands is restricted (described in flash block description).

In special single chip mode the device is in active BDM after reset. In special single chip mode on a secure

device, only the BDC mass erase and BDC control and status register commands are possible. BDC access

to memory mapped resources is disabled. The BDC can only be used to erase the EEPROM and Flash

memory without giving access to their contents.

1.10.4 Unsecuring the Microcontroller

Unsecuring the microcontroller can be done using three different methods:

1. Backdoor key access

2. Reprogramming the security bits

3. Complete memory erase

Table 1-14. Security Bits

SEC[1:0] Security State

00 1 (secured)

01 1 (secured)

10 0 (unsecured)

11 1 (secured)

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1.10.4.1 Unsecuring the MCU Using the Backdoor Key Access

In normal single chip mode, security can be temporarily disabled using the backdoor key access method.

This method requires that:

• The backdoor key has been programmed to a valid value

• The KEYEN[1:0] bits within the Flash options/security byte select ‘enabled’.

• The application program programmed into the microcontroller has the capability to write to the

backdoor key locations

The backdoor key values themselves would not normally be stored within the application data, which

means the application program would have to be designed to receive the backdoor key values from an

external source (e.g. through a serial port)

The backdoor key access method allows debugging of a secured microcontroller without having to erase

the Flash. This is particularly useful for failure analysis.

NOTE

No backdoor key word is allowed to have the value 0x0000 or 0xFFFF.

1.10.5 Reprogramming the Security Bits

Security can also be disabled by erasing and reprogramming the security bits within the flash

options/security byte to the unsecured value. Since the erase operation will erase the entire sector

(0xFF_FE00–0xFF_FFFF) the backdoor key and the interrupt vectors will also be erased; this method is

not recommended for normal single chip mode. The application software can only erase and program the

Flash options/security byte if the Flash sector containing the Flash options/security byte is not protected

(see Flash protection). Thus Flash protection is a useful means of preventing this method. The

microcontroller enters the unsecured state after the next reset following the programming of the security

bits to the unsecured value.

This method requires that:

• The application software previously programmed into the microcontroller has been designed to

have the capability to erase and program the Flash options/security byte.

• The Flash sector containing the Flash options/security byte is not protected.

1.10.6 Complete Memory Erase

The microcontroller can be unsecured by erasing the entire EEPROM and Flash memory contents. If

ERASE_FLASH is successfully completed, then the Flash unsecures the device and programs the security

byte automatically.

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1.11 Resets and Interrupts

1.11.1 Reset

Table 1-15. lists all reset sources and the vector locations. Resets are explained in detail in the Chapter 8,

“S12 Clock, Reset and Power Management Unit (V10 and V6)”.

Table 1-15. Reset Sources and Vector Locations

1.11.2 Interrupt Vectors

Table 1-16 lists all interrupt sources and vectors in the default order of priority. The interrupt module

description provides an interrupt vector base register (IVBR) to relocate the vectors.

Vector Address Reset Source CCR

Mask Local Enable

0xFFFFFC Power-On Reset (POR) None None

Low Voltage Reset (LVR) None None

External pin RESET None None

PLL clock monitor reset None None

Oscillator Clock monitor reset

None OSCE in CPMUOSC register

OMRE in CPMUOSC2 register

COP watchdog reset None CR[2:0] in CPMUCOP register

Table 1-16. Interrupt Vector Locations

Vector Address(1) Interrupt Source CCR

Mask Local Enable Wake up

from STOP Wake up

from WAIT

Vector base + 0x1F8 Unimplemented page1 op-code trap

(SPARE)

None None - -

Vector base + 0x1F4 Unimplemented page2 op-code trap

(TRAP)

None None - -

Vector base + 0x1F0 Software interrupt instruction (SWI) None None - -

Vector base + 0x1EC System call interrupt instruction

(SYS)

None None - -

Vector base + 0x1E8 Machine exception None None - -

Vector base + 0x1E4 Reserved

Vector base + 0x1E0 Reserved

Vector base + 0x1DC Spurious interrupt — None - -

Vector base + 0x1D8 XIRQ interrupt request X bit None Yes Yes

Vector base + 0x1D4 IRQ interrupt request I bit IRQCR(IRQEN) Yes Yes

Vector base + 0x1D0 RTI time-out interrupt I bit CPMUINT (RTIE) See CPMU

section

Yes

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Vector base + 0x1CC TIM0 timer channel 0 I bit TIM0TIE (C0I) No Yes

Vector base + 0x1C8 TIM0 timer channel 1 I bit TIM0TIE (C1I) No Yes

Vector base + 0x1C4 TIM0 timer channel 2 I bit TIM0TIE (C2I) No Yes

Vector base + 0x1C0 TIM0 timer channel 3 I bit TIM0TIE (C3I) No Yes

Vector base + 0x1BC

Vector base + 0x1B0

Reserved

Vector base + 0x1AC TIM0 timer overflow I bit TIM0TSCR2(TOI) No Yes

Vector base + 0x1A8

Vector base + 0x1A4

Reserved

Vector base + 0x1A0 SPI0 I bit SPI0CR1 (SPIE, SPTIE) No Yes

Vector base + 0x19C SCI0 I bit SCI0CR2

(TIE, TCIE, RIE, ILIE)

SCI0ACR1

(RXEDGIE, BERRIE, BKDIE)

RXEDIF

only

Yes

Vector base + 0x198 SCI1 I bit SCI1CR2

(TIE, TCIE, RIE, ILIE)

SCI1ACR1

(RXEDGIE, BERRIE, BKDIE)

RXEDIF

only

Yes

Vector base + 0x194 Reserved

Vector base + 0x190 Reserved

Vector base + 0x18C ADC0 Error I bit ADC0EIE (IA_EIE, CMD_EIE,

EOL_EIE, TRIG_EIE,

RSTAR_EIE, LDOK_EIE)

ADC0IE(CONIF_OIE)

No Yes

Vector base + 0x188 ADC0 conversion sequence abort I bit ADC0IE(SEQAD_IE) No Yes

Vector base + 0x184 ADC0 conversion complete I bit ADC0CONIE[15:0] No Yes

Vector base + 0x180 Oscillator status interrupt I bit CPMUINT (OSCIE) No Yes

Vector base + 0x17C PLL lock interrupt I bit CPMUINT (LOCKIE) No Yes

Vector base + 0x178

Vector base + 0x174

Reserved

Vector base + 0x170 RAM error I bit EECIE (SBEEIE) No Yes

Vector base + 0x16C

Vector base + 0x168

Reserved

Vector base + 0x164 FLASH error I bit FERCNFG (SFDIE) No Yes

Vector base + 0x160 FLASH command I bit FCNFG (CCIE) No Yes

Table 1-16. Interrupt Vector Locations

Vector Address(1) Interrupt Source CCR

Mask Local Enable Wake up

from STOP Wake up

from WAIT

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Vector base + 0x15C CAN0 wake-up I bit CAN0RIER (WUPIE) Yes Yes

Vector base + 0x158 CAN0 errors I bit CAN0RIER (CSCIE, OVRIE) No Yes

Vector base + 0x154 CAN0 receive I bit CAN0RIER (RXFIE) No Yes

Vector base + 0x150 CAN0 transmit I bit CAN0TIER (TXEIE[2:0]) No Yes

Vector base + 0x14C

Vector base + 0x148

Reserved

Vector base + 0x144 LINPHY over-current interrupt I bit LPIE (LPDTIE,LPOCIE) No Yes

Vector base + 0x140 BATS supply voltage monitor interrupt I bit BATIE (BVHIE,BVLIE) No Yes

Vector base + 0x13C GDU Desaturation Error I bit GDUIE (GDSEIE) No Yes

Vector base + 0x138 GDU Voltage Limit Detected I bit GDUIE (GOCIE, GHHDIE,

GLVLSIE)

No Yes

Vector base + 0x134

Vector base + 0x12C

Reserved

Vector base + 0x128 CAN Physical Layer

(ZVMC256 Only)

I bit CPIE

(CPVFIE, CPOCIE, CPDTIE)

No Yes

Vector base + 0x124 Port S interrupt I bit PIES[5:0] Yes Yes

Vector base + 0x120 Reserved

Vector base + 0x11C ADC1 Error I bit ADC1EIE (IA_EIE, CMD_EIE,

EOL_EIE, TRIG_EIE,

RSTAR_EIE, LDOK_EIE)

ADC1IE(CONIF_OIE)

No Yes

Vector base + 0x118 ADC1 conversion sequence abort I bit ADC1IE(SEQAD_IE) No Yes

Vector base + 0x114 ADC1 conversion complete I bit ADC1CONIE[15:0] No Yes

Vector base + 0x110 Reserved

Vector base + 0x10C Port P interrupt I bit PIEP[2:0] Yes Yes

Vector base + 0x108 EVDD1 over-current interrupt I bit PIEP(OCIE1) No Yes

Vector base + 0x104 Low-voltage interrupt (LVI) I bit CPMULVCTL (LVIE) No Yes

Vector base + 0x100 Autonomous periodical interrupt

(API) I bit CPMUAPICTRL (APIE) Yes Yes

Vector base + 0xFC High temperature interrupt I bit CPMUHTCTL(HTIE) No Yes

Vector base + 0xF8 VDDS integrity interrupt I bit CPMULVCTL(VDDSIE) No Yes

Vector base + 0xF4 Port AD interrupt I bit PIEADH(PIEADH0)

PIEADL(PIEADL[7:0])

Yes Yes

Vector base + 0xF0 PTU Reload Overrun I bit PTUIEH(PTUROIE) No Yes

Vector base + 0xEC PTU Trigger0 Error I bit PTUIEL(TG0AEIE,

TG0REIE,TG0TEIE)

No Yes

Table 1-16. Interrupt Vector Locations

Vector Address(1) Interrupt Source CCR

Mask Local Enable Wake up

from STOP Wake up

from WAIT

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1.11.3 Effects of Reset

When a reset occurs, MCU registers are initialized. Refer to the respective block sections for register reset

states. The initialization of I/O pins is specified in the PIM section.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers. If double

faults are detected in the reset phase, Flash module protection and security may be active on leaving reset.

This is explained in more detail in the Flash module description. If a reset occurs while any Flash command

Vector base + 0xE8 PTU Trigger1 Error I bit PTUIEL(TG1AEIE, TG1REIE,

TG1TEIE)

No Yes

Vector base + 0xE4 PTU Trigger0 Done I bit PTUIEL(TG0DIE) No Yes

Vector base + 0xE0 PTU Trigger1 Done I bit PTUIEL(TG1DIE) No Yes

Vector base + 0xDC

Vector base + 0xD4

Reserved

Vector base + 0xD0 PMF Reload A I bit PMFENCA(PWMRIEA) No Yes

Vector base + 0xCC PMF Reload B I bit PMFENCB(PWMRIEB) No Yes

Vector base + 0xC8 PMF Reload C I bit PMFENCC(PWMRIEC) No Yes

Vector base + 0xC4 PMF Fault I bit PMFFIE(FIE[5:0]) No Yes

Vector base + 0xC0 PMF Reload Overrun I bit PMFROIE(PMFROIEA,PMF

ROIEB,PMFROIEC)

No Yes

Vector base + 0xBC Port L interrupt

(ZVMC256 Only)

I bit PIEL(PIEL0) Yes Yes

Vector base + 0xB8

Vector base + 0xB0

Reserved

Vector base + 0xAC TIM1 timer channel 0

(ZVMC256 Only)

I bit TIM1TIE (C0I) No Yes

Vector base + 0xA8 TIM1 timer channel 1

(ZVMC256 Only)

I bit TIM1TIE (C1I) No Yes

Vector base + 0xA4

Vector base + 0x90

Reserved

Vector base + 0x8C TIM1 timer overflow

(ZVMC256 Only)

I bit TIM1TSCR2(TOI) No Yes

Vector base + 0x88

Vector base + 0x10

Reserved

1. 15 bits vector address based

Table 1-16. Interrupt Vector Locations

Vector Address(1) Interrupt Source CCR

Mask Local Enable Wake up

from STOP Wake up

from WAIT

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is in progress, that command will be immediately aborted. The state of the word being programmed or the

sector/block being erased is not guaranteed.

The system RAM arrays, including their ECC syndromes, are initialized following a power on reset. All

other RAM arrays are not initialized out of any type of reset. With the exception of a power-on-reset the

RAM content is unaltered by a reset occurrence.

The power on reset sequence including flash and SRAM initialization is shown in Figure 1-8

Figure 1-8. Device Power On Reset Sequence

1.12 Module device level dependencies

1.12.1 CPMU COP and GDU Configuration

The COP time-out rate bits CR[2:0] and the WCOP bit in the CPMUCOP register are loaded from the

Flash configuration field byte at global address 0xFF_FE0E during the flash initialization phase of the

Vsup

Vddx / Vddf / Vdd

POR

LVR

stem Reset

1.8V

2.8V

LVR monitors VDD,

VDDF and VDDA/VDDX

#1.6V

POR monitors

VDD

Fbus = Fvcorst/2

Fbus= 4Mhz min; 16Mhz max

768 Fvcorst cyc

[24 ; 96] μsec

RESET Pin

512 Fvcorst cyc

[16 ; 64] μsec

Fbus changing to 6.25Mhz

Bus Freq

Tlock= 406μsec max

Fbus = 6.25Mhz

Device

“state”

ET Flash initialization

396 to 510 bus cycles

[24 ; 128] μsec

Vector fetch, program execution

SRAM initialization – SRAM not accessible

For S12ZVM128 : 8kBytes / 32bits = 2048 bus cycles [128; 456] μsec

For S12ZVM256 : 32kBytes / 64bits = 4096 bus cycles [255; 1024] μsec

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reset sequence. The GSUF bit in the GDUF register is also loaded during the reset sequence. See Table 1-

17, Table 1-18 and Table 1-19.

The EPRES bit was only included in early mask sets but was not usable. The implementation of

GDUCTR1 register bits is also mask set dependent as shown in Table 1-19.

1.12.2 CPMU High Temperature Trimming

The value loaded from the flash into the CPMUHTTR register is a default value for the device family.

There is no device specific trimming carried out during production. The specified VHT value is a typical

value that is part dependent and should thus be calibrated.

Table 1-17. Initial COP Rate Configuration

NV[2:0] in

FOPT Register CR[2:0] in

CPMUCOP Register

000 111

001 110

010 101

011 100

100 011

101 010

110 001

111 000

Table 1-18. Initial WCOP Configuration

NV[3] in

FOPT Register WCOP in

CPMUCOP Register

Table 1-19. GDU Configuration

Mask Set GSUF (GDUF[7])

Initialization

EPRES

(GDUE[5])

Inclusion

GDUCTR1

Available bits

HD nominal over-

voltage time

constant

0N95G, 1N95G 1 Not usable None 300ns

2N95G 0 Not usable None 2.7us

3N95G FOPT:NV[6] Not included GDUCTR1[0] 2.7us

0N14N 1 Not included None 2.7us

1N14N FOPT:NV[7](1)

1. Note bit inversion

Not included None 2.7us

0N00R,1N00R FOPT:NV[7] (1) Not included GDUCTR1[7,6,0] 2.7us

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1.12.3 CPMU VDDC enable

On the ZVMC256 device, if the CANPHY is not used then the VDDC regulator can be disabled by

clearing EXTCON. An external VDDC capacitor is however still required for power up.

1.12.4 Flash IFR Mapping

1.13 Application Information

1.13.1 ADC Calibration

For applications that do not provide external ADC reference voltages, the VDDA/VSSA supplies can be

used as sources for VRH/VRL respectively. Since the VDDA must be connected to VDDX at board level

in the application, the accuracy of the VDDA reference is limited by the internal voltage regulator

accuracy. In order to compensate for VDDA reference voltage variation in this case, the reference voltage

is measured during production test using the internal reference voltage VBG, which has a narrow variation

over temperature and external voltage supply. VBG is mapped to an internal channel of each ADC module

(Table 1-10,Table 1-11). The resulting 12-bit right justified ADC conversion results of VBG are stored to

the flash IFR for reference, as listed in Table 1-20.

The measurement conditions of the reference conversion are listed in the device electrical parameters

appendix. By measuring the voltage VBG in the application environment and comparing the result to the

reference value in the IFR, it is possible to determine the current ADC reference voltage VRH :

The exact absolute value of an analog conversion can be determined as follows:

With:

ConvertedADInput: Result of the analog to digital conversion of the desired

ConvertedReference: Result of internal channel conversion

Table 1-20. Flash IFR Mapping

1514131211109876543210 IFR Byte Address

ADC0 reference conversion using VRH_1/VSSA 0x1F_C040 & 0x1F_C041

ADC0 reference conversion using VRH_0/VSSA 0x1F_C042 & 0x1F_C043

ADC1 reference conversion using VRH_1/VSSA 0x1F_C044 & 0x1F_C045

ADC1 reference conversion using VRH_0/VSSA 0x1F_C046 & 0x1F_C047

VRH StoredReference

ConvertedReference

-------------------------------------------------------5V=

Result ConvertedADInput StoredReference 5V

ConvertedReference 2n



------------------------------------------------------------------=

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StoredReference: Value in IFR location

n: ADC resolution (12 bit)

NOTE

The ADC reference voltage VRH must remain at a constant level throughout

the conversion process.

1.13.2 SCI Baud Rate Detection

The baud rate for SCI0 and SCI1 is achieved by using a timer channel to measure the data rate on the RXD

signal.

1. Establish the link:

— For SCI0: Set [T0IC3RR1:T0IC3RR0]=0b01 to disconnect IOC0_3 from TIM0 input capture

channel 3 and reroute the timer input to the RXD0 signal of SCI0.

— For SCI1: Set [T0IC3RR1:T0IC3RR0]=0b10 to disconnect IOC0_3 from TIM0 input capture

channel 3 and reroute the timer input to the RXD1 signal of SCI1.

2. Determine pulse width of incoming data: Configure TIM0 IC3 to measure time between incoming

signal edges.

1.13.3 Motor Control Application Overview

The following sections provide information for using the device in motor control applications. These

sections provide a description of motor control loop considerations that are not detailed in the individual

module sections, since they concern device level inter module operation specific for motor control. More

detailed information is available in application notes. The applications described are as follows:

1. BDCM - wiper pumps fans

2. BLDCM - pumps, fans and blowers

– based on Hall sensors

– sensorless based on back-EMF zero crossing comparators

– sensorless based on back-EMF ADC measurements

3. PMSM - high-end wiper, pumps, fans and blowers

– simple sinewave commutation with position sensor Hall effect, sine-cos

– FOC with sine-cos position sensor

– sensorless 3-phase sinewave control

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1.13.3.1 Motor Control Loop Overview

The mapping of motor control events at device level as depicted in Figure 1-9 is listed in Table 1-21,

whereby the columns list the names used in the module level descriptions

Figure 1-9. Internal Control Loop Configuration

The control loop consists of the PMF, GDU, ADC and PTU modules. The control loop operates using

either static, dynamic or asynchronous timing. In the following text the event names given in bold type

correspond to those shown in Figure 1-9. The PTU and ADC operate using lists stored in memory. These

lists define trigger points for the PTU, commands for the ADC and results from the ADC. If the PTU is

enabled the reload and async_reload events are immediately passed through to the ADC and GDU

modules.

PMF

PTU ADC0

SENSOR

TIM0

ADC1

commutation_event

dc_bus_current

OC0

GDU

zero crossing

back-EMF P1

PHMUX

comparators

GPHS

dc_bus_voltage

reload

async reload

trigger_1

reload

async reload

trigger_0

glb_ldok

reload

async reload

glb_ldok

reload

reloada async_reload

If PTU enabled

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Each control loop cycle is started by a PMF reload event. The PMF reload event restarts the PTU time

base. If the PTU is enabled, the reload is immediately passed through to the ADC and GDU modules.

The PMF generates the reload event at the required PWM reload frequency. The PMF reload event causes

the PTU time base to restart, to acquire the first trigger times from the list and the ADCs to start loading

the ADC conversion command from the Command Sequence List (CSL).

NOTE

In the PTU there is time window after the reload event assertion before the

first trigger is permitted. This time can be up to 10 bus cycles.

Subsequent triggers also require a load time of 6 bus clock cycles (one

trigger generator enabled) or 10 bus clock cycles (both trigger generators

enabled). This defines the minimal spacing between triggers without

causing a PTU trigger generator timing error.

In the ADC there is 10 bus cycle maximum time window after the reload

event assertion to access the first ADC command from the list. In this

window the ADC conversion can not be started. If the measurement is

control loop related these delays are negligible due to much larger delays in

the PWM-GDU-feedback loop.

When the trigger time is encountered the corresponding PTU trigger generates the trigger_x event for the

associated ADC. For simultaneous sampling the PTU generates simultaneous trigger_x events for both

ADCs. At the trigger_x event the ADC starts the first conversion of the next conversion sequence in the

CSL (the first ADC command is already downloaded).

A commutation event is used by the PMF to generate an async_reload event. The async_reload is used by

the PTU to update lists and re-initialize the trigger lists. If the PTU is enabled the async_reload is

immediately passed through to the ADC.

Table 1-21. Control Loop Events

Device Level Event TIM0 PMF PTU ADC0 ADC1

commutation_event OC0(1)

1. TIM channel OC0 must be configured to toggle on both edges.

commutation_event — — —

reload — reloada(2)

2. PMF events reloadb and reloadc are not connected at device level

reload Restart Restart

async_reload — async_reload async_reload Seq_abort Seq_abort

trigger_0 — — trigger_0 Trigger —

trigger_1 — — trigger_1 — Trigger

glb_ldok — glb_ldok glb_ldok LoadOK LoadOK

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1.13.3.2 Control Loop Timing Considerations

Delays within the separate control loop elements require consideration to ensure correct synchronization.

Regarding the raw PWM0 signal as the starting point and stepping through the control loop stages, the

factors shown in Figure 1-10 contribute to delays within the control loop, starting with the deadtime

insertion, going through the external FETs and back into the internal ADC measurements of external

voltages and currents.

Figure 1-10. Control Loop Delay Overview

The PWM deadtime (TDEAD_X) is an integral number of bus clock cycles, configured by the PMF

deadtime registers.

The GDU propagation delays (tdelon, tdeloff) are specified in the electrical parameter Table E-1.

The FET turn on times (tHGON) are load dependent but are specified for particular loads in the electrical

parameter Table E-1.

The current sense amplifier delay is highly dependent on external components.

The ADC delay until a result is available is specified as the conversion period NCONV in Table C-1.

1.13.3.3 Static Timing Operation

The timing frame is static if it is the same in every control cycle (defined by reload frequency) and is

relative to start of the control cycle. The only settings modified from one control cycle to the next one are

the PWM duty cycle registers.

The main control cycle synchronization event is the PMF reload event. The PMF reload event can be

generated every n PWM periods.

This mode can optionally be extended by a timer channel trigger to PMF to change the PWM channel

operation (e.g. used for BLDCM commutation). In this case, the PMF configuration can propagate the

PWM with

PWM base

PWM cycle

deadtime

GDU

propagation

FET

turn on

Current sense

settling time

ADC delay

TDEAD_x

tdelon

tHGON

(tcslsst)

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trigger through the control loop or can prevent propagation so the static timing of the control cycle and

inter-block coherency are not affected by the trigger.

At the end of the conversion sequence the first ADC command from the new sequence is loaded and the

ADCx waits for the next trigger_x. The PTU continues to generate the trigger_x events for each trigger

time from the list until a new reload or async_reload occurs.

Before the upcoming reload event the CPU:

• reads the ADC results from the buffered Conversion Result List

• clears the conversion complete flag

• services the reload by setting new duty cycle values

• sets the PTULDOK bit (corresponding to glb_ldok) to signal the duty cycle coherence

The CPU actions are typically performed in an ISR triggered by the conversion complete flag.

1.13.3.4 Static Timing Fault Handling

The following Faults and/or errors can occur:

• Desaturation error, Overvoltage, Undervoltage, External fault

The application run-time error is handled by the GDU without CPU interaction. Firstly the FETs are

disabled and the PMF signals switched to an inactive state. To re-enable the operation first the GDU fault

and then PWM fault must be cleared, to automatically re-enable the FET driving at the next PWM

boundary.

• PTU reload overrun error

This is an application run-time error caused by the CPU not setting PTULDOK on time. Servicing this type

of error is application dependent and may range from a further reload attempt to a total shut down.

• PTU trigger generator reload error, PTU trigger generator error

Since all timing is static, this error should only occur during application debugging. This type of error

occurring in a static timing configuration indicates possible data corruption. This can be serviced by a

control loop shutdown.

• PTU memory access error, Memory access double bit ECC error

This type of error occurring in an application indicates data corruption. This can be serviced by a control

loop shutdown.

• ADC sequence overrun, ADC command overrun, ADC command error

Since all timing is static, this error should only occur during application debugging. This type of error

occurring in an application indicates possible data corruption. This can be serviced by a control loop

shutdown.

1.13.3.5 Dynamic Timing Operation

The timing frame is dynamic if the following are modified on a cycle by cycle basis:

• PMF - duty cycle value registers (PMF_VALx), modulo registers

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• PTU - Trigger Event List (PTU_TELx)

• ADC - Command Sequence List (ADCx_CSL)

The main philosophy is that all cycle-by-cycle settings for cycle n need to be done within cycle n-1. The

main control cycle synchronization event is the PMF reload event, which can be generated every n PWM

periods.

This mode can optionally be extended by a timer channel trigger PMF to change PWM channel operation

(e.g. used for BLDCM commutation).

The event flow is the same as for static timing.

Before the upcoming reload event the CPU:

• reads the ADC results from the buffered Conversion Result List

• clears the conversion complete flag

• services the reload by setting new duty cycle values and a new PMF modulo value

• updates the non-active PTU_TELx

• updates the non-active ADCx_CSL

• sets the PTULDOK bit (corresponding to glb_ldok) to signal the duty cycle coherence

The CPU actions are typically performed in an ISR triggered by the conversion complete flag.

1.13.3.6 Dynamic Timing Fault Handling

The following Faults and/or errors can occur:

• Desaturation error, Overvoltage, Undervoltage, External fault

The application run-time error is handled by the GDU without CPU interaction. Firstly the FETs are

disabled and the PMF signals switched to an inactive state. To re-enable the operation first the GDU fault

and then PWM fault must be cleared, to automatically re-enable the FET driving at the next PWM

boundary.

• PTU reload overrun error

This is an application run-time error caused by the CPU not setting PTULDOK on time. Servicing this type

of error is application dependent and may range from a further reload attempt to a total shut down.

• PTU trigger generator reload error, PTU trigger generator error

This indicates an application run-time error caused by a settings mismatch. Servicing this type of error is

application dependent. In some cases, the ADC values for the current control cycle can be ignored.

• PTU memory access error, Memory access double bit ECC error

This type of error occurring in an application indicates possible data corruption. This can be serviced by a

control loop shutdown.

• ADC sequence overrun, ADC command overrun, ADC command error

This indicates an application run-time error caused by a settings mismatch. Servicing this type of error is

application dependent. In some cases, the ADC values for the current control cycle can be ignored.

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1.13.3.7 Asynchronous Timing

This case is an extension of the dynamic timing case by an asynchronous event generated by the Timer.

Note the asynchronous term is referenced to the control cycle.

The timing frame is the same as in dynamic timing case plus it can be asynchronously restarted at any time

within the control cycle.

At the asynchronous commutation_event

•the PMF actions are:

1. counter re-start, re-initialization

2. PWM configuration re-initialization according to the selected PWM settings (center /edge-aligned

pattern, normal/inverted type etc.)

3. re-initialization of the dead time generators (in case the commutation takes place at a time when

one of the dead times is being generated)

4. re-initialization of the PWM outputs according to pre-set PWM channel output settings in double

buffered registers (mask, swap, output control)

5. re-initialization of the automatic fault clearing

6. generates async_reload event for the PTU

7. optionally updates the PWM duty cycle values based on LDOK state

•the PTU actions are:

1. abortion of the trigger_x event generation

2. re-initialization and re-start the PTU counter

3. update of the current list index TGxList based on the glb_ldok state

4. fetch first trigger time from updated TGxList

5. passes the async_reload event immediately to the ADC (if the PTU is enabled)

6. generates the reload event for the ADC

•the ADC actions are:

1. the conversion in progress is completed

2. the ADC conversion sequence is aborted and the SEQA flag is set to indicate that the final

conversion occurred during the abortion process (potentially coinciding with a commutation and

is thus less precise than under normal conditions)

3. update of the current lists index ADxLists

4. re-start of the conversion sequencing upon successful abortion - fetches the first ADC command

from the ADCx_CSL, re-sets the result pointer to the top of the list

Note: in case the lists index ADxLists is not updated at the sequence abortion the new restarted

A/D conversions will overwrite the previously converted results.

•the GDU actions are:

1. standard operation

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1.13.3.8 Control Loop Startup Guidelines

The sequence for control loop start up is to firstly configure the signal measurement (inputs/feedback).

Once the measurement is properly configured (correct value is measured at defined time) the output

actuation (control action) is configured. The following modules are involved in signal measurements.

• TIM (to identify asynchronous commutation) [BLDC applications only]

• PMF (to generate main synchronous events for PTU and ADC)

• PTU (to generate delay relative to synchronous events generated by PMF)

• ADC (to acquire analog signals under synchronous control)

• GDU (zero crossing comparators, Back-EMF muxing) [application dependent]

The TIM OC0 channel identifies the commutation event and restarts the PMF counter . In order to establish

this link TIM and PMF need to be configured and started. Then to sample accurately within one PMF cycle

the PTU needs to be used, so the next step is to configure the PTU to establish PMF to PTU link. The PTU

sends triggers to the ADC to perform a measurement of control signals. So the next step is to configure the

ADC. In some cases the GDU involvement is required and therefore configured.

The control action involves the PMF (to generate the duty cycle for GDU) and the GDU (to propagate the

signal to the MOSFET s). Since the PMF has already been configured for the measurements, only the GDU

need be configured to complete startup. Sometimes the GDU can be configured earlier but the GDU output

is always enabled last.

The recommended startup sequence is summarized as follows:

• Configure TIM and PMF to establish the link between TIM OC0 commutation event and PMF

• Configure PTU to establish the PMF to PTU link and ensure correct sampling within PMF cycle

• Configure the ADC

• Configure the GDU

1.13.3.9 Control Loop Shutdown Guidelines

1. Remove energy stored in the system after the power stage

kinetic energy - stop all rotating/moving mass

magnetic energy - gracefully drive currents to zero

2. Put GDU and PMF outputs to safe state

1.13.3.10 Control Loop Stop Mode Considerations

In Stop mode the PMF, PTU, ADC can not run because the bus clock is not running. Thus the GDU must

transition to a disabled state. Before entering S top mode the application must perform the following steps:

1. Remove energy stored in the system after the power stage

kinetic energy - stop all rotating/moving mass

magnetic energy - gracefully drive currents to zero

2. Put GDU and PMF outputs to safe state

3. Verify GDU and PMF safe states

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4. Verify fault flags and service if necessary

5. Execute the STOP instruction

The return from stop is expected in reverse order:

1. On returning from Stop mode the clocks are automatically enabled coherently

2. Initialize and check device proper functionality (charge pump etc.)

3. Check functionality of the external system

4. Initializes control loop operation, however with PMF and GDU outputs still in safe state

5. Read the ADC values to check the system

6. Start driving energy into the system

based on the measurements from the previous step, the PWM duty cycle values are calculated

7. PMF and GDU outputs are enabled (actively driven)

The device does not support putting the FETs in an active driving state during STOP as the GDU charge

pump clock is not running. This means the device cannot be put in stop mode if the FETS need to be in an

active driving state to protect the system from external energy supply (e.g. externally driven motor-

generator).

NOTE

It is imperative, that whatever the modules perform on entering/exiting Stop

mode, the pre-set complementary mode of operation and dead time insertion

must be guaranteed all the times.

1.13.3.11 Application Signal Visibility

In typical motor control applications, TIM OC0 is used internally to indicate commutation events. To

switch off OC0 visibility at port pin PT0:

• Disable output compare signal on pin PT0 in TIM: OCPD[OCPD0]=0b1.

1.13.3.12 Debug Signal Visibility

Depending on required visibility of internal signals on port pins enable the following registers:

• Set [PWMPRR]=0b1 in PIM if monitoring of internal PWM waveforms is needed. PWM0_[5:3]

are driven out on pins PT[2:0] and PWM0_[2:0] on pins PP[2:0].

• Enable output compare channel OC0 to output commutation event on pin PT0 in TIM:

OCPD[OCPD0]=0b0.

• Set PTUDEBUG[PTUREPE]=0b1 in PTU to output the reload event.

• Set PTUDEBUG[PTUTxPE]=0b1 with x=0,1 in PTU to output the trigger events.

1.13.4 BDCM Complementary Mode Operation

This section describes BDCM control using center aligned complementary mode with deadtime insertion.

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The DC Brushed motor power stage topology is a classical full bridge as shown in Figure 1-11. The DC

Brushed motor is driven by the DC voltage source. A rotational field is created by means of commutator

and brushes on the motor. These drives are still very popular because sophisticated calculations and

algorithms such as commutation, waveform generation, or space vector modulation are not required.

Figure 1-11. DC Brushed Motor External Configuration

Usually the control consists of an outer, speed control loop with inner current (torque) control loop. The

inner loop controls DC voltage applied onto the motor winding. The control loop is calculated regularly

within a given period. In most cases, this period matches the PWM reload period.

Driving the DC motor from a DC voltage source, the motor can work in all four quadrants. The

complementary mode of operation with deadtime insertion is needed for smooth reversal of the motor

PWM

+ 1/2 U

- 1/2 U

A B

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current (motor torque), hence smooth full four quadrant control. Usually the center-aligned PWM is

chosen to lower electromagnetic emissions.

Figure 1-12. BDCM Control Loop Configuration

The PWM frequency selection is always a compromise between audible noise, electromagnetic emissions,

current ripples and power switching losses.

The BDCM control loop goal is to provide a controlled DC voltage to the motor winding, whereby it is

controlled cycle-by-cycle using a speed, current or torque feedback loop.

The center aligned PWM waveforms generated by the PMF module are applied to the bridge as shown in

Figure 1-13 whereby the base waveform for PWM0_0 and PWM0_1 is depicted at the top and the

complementary PWM0_0 and PWM0_1 waveforms are shown with deadtime insertion depicted by the

gray phases before the switching edges.

PMF

PTU

ADC0

GDU

reload

glb_ldok

dc_bus_voltage

trigger_0

dc_bus_current0

sine/

sensor

cosine

ADC1

reload

trigger_1

reloada

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Figure 1-13. BDCM Complementary Mode Waveform

Assuming first quadrant operation, forward accelerating operation, the applied voltage at node A must

exceed the applied voltage at node B (Figure 1-11). Thus the PWM0_0 duty cycle must exceed the

PWM0_2 duty cycle.

The duty cycle of PWM0_0 defines the voltage at the first power stage branch.

The duty cycle of PWM0_2 defines the voltage at the second power stage branch.

Modulating the duty cycle every period using the function FPWM then the duty cycle is expressed as:

PWM0_0 duty-cycle = 0.5 + (0.5 * FPWM); For -1<=FPWM <= 1;

PWM0_2 duty-cycle = 0.5 - (0.5 * FPWM)

PWM0_0

PWM0_1

PWM0_2

PWM0_3

TPWM

PWM0_[1:0] base PWM0_[3:2] base

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1.13.5 BLDC Six-Step Commutation

1.13.5.1 Hall Sensor Triggered Commutation

Figure 1-14. BLDC Configuration With Hall Sensors

This BLDC application uses Hall sensor signals to create commutation triggers. The integrated sense

amplifier and an ADC module are used to measure DC bus current, for torque calculation. The DC bus

voltage measurement is used in the control algorithm to counter-modulate the PWM such that the variation

of the DC-bus voltage does not affect the motor current closed loop. The configuration is as follows:

1. Connect the three Hall sensor signals from the motor to input pins PT3-1.

2. Set [T0IC1RR=1] in the register MODRR2 to establish the link from Hall sensor input pins to TIM

input capture channel 1.

3. Setup TIM IC1 for speed measurement of XORed Hall sensor signals. Enable interrupt on both

edges.

4. Enable TIM OC0 and select toggle action on output compare event: TCTL2[OM0:OL0]=01.

5. Configure PMF for edge-aligned PWM mode with or without restart at commutation:

PMFENCx[RSTR T]. If using the restart option, then select generator A as reload signal source and

keep the following configurations at their default setting: multi timebase generators

(PMFCFG0[MTG]=b0), reload frequency (PMFFQCx[LDFQx]=b0), prescaler

(PMFFQCx[PRSCx]=b00).

6. Enable PMF commutation event input: PMFCFG1[ENCE]=1.

PMF

PTU

ADC0

GDU M

reload

glb_ldok

dc_bus_voltage

trigger_0 dc_bus_current

TIM0 PIM Hall

EVDD1

PT1

PT2

PT3

XOR

IC1 Sensor

commutation_event

reload

PTIT

async_reload

OC0

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7. Read port register PTIT[3:1] to determine starting sector.

8. Startup motor by applying PWM to the related motor phase.

9. In IC1 interrupt ISR calculate the delay to next commutation and store value to output compare

10. On next output compare event the buffered mask and swap information is transferred to the active

PMF registers to execute the commutation.

1.13.5.2 Sensorless Commutation

Figure 1-15. Sensorless BLDC Configuration

To calculate the commutation time in a sensorless motor system the back-EMF zero crossing event of the

currently non-fed phase within an electrical rotation cycle must be determined. For fast motor rotation, the

ADC is used to measure the back-EMF voltage and the DC bus voltage to determine the zero crossing time.

For slow motor rotation the GPHS register can be polled. In either case the zero crossing event is handled

PMF

PTU

ADC0

GDU

ADC1

reload

glb_ldok

reload

dc_bus_current1

dc_bus_voltage

trigger_0

trigger_1

dc_bus_current0

zero crossing

back-EMF P1

PHMUX

TIM0

commutation_event

comparators

GPHS

OC0

async_reload

reloada

async_reload

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by the CPU monitoring flags or responding to interrupts. The TIM then generates the commutation_event

under CPU control, based on the zero crossing time.

1. Enable TIM OC0 and select toggle action on output compare event: TCTL2[OM0:OL0]=0b01.

2. Enable PMF commutation event input: PMFCFG1[ENCE]=0b1.

3. Enable internal ADC channel for measuring the phase voltages from the muxed GDU outputs.

4. Align rotor to stator field. Initialize phase MUX using register GDUPHMUX.

5. Startup motor by applying PWM to an arbitrary motor phase.

6. Take samples of the phase voltages periodically based on PWM cycle to detect zero crossing.

7. Calculate the delay to next commutation and store value to output compare register. Update

registers with next values of mask and swap.

8. On next output compare event the buffered mask and swap information are transferred to the active

PMF register to execute the commutation.

1.13.6 PMSM Control

PMSM control drives all 3 phases simultaneously with sinusoidal waveforms. Both sensorless and Sine-

Cosine position sensor control loop operation are supported.

1.13.6.1 PMSM Sensorless Operation

In this configuration the PMSM stator winding currents are driven sinusoidally and the back EMF

waveform is also sinusoidal. Thus all 3 phases are active simultaneously. The rotor position and speed are

determined by the current and calculated voltages respectively. The back EMF voltage is calculated based

on the currents.

1. Configure PMF for complementary mode operation.

2. Configure PMF for center aligned or phase shifted operation.

3. Select correct PMF deadtime insertion based on external FET switches.

4. Enable GDU current sense opamps for measuring the phase currents from 2 external shunts.

5. Map the output pin of each current sense opamp to the ADC input.

6. Optionally use GDU phase comparators for zero crossing detection to correct deadtime distortion.

7. Fetch targeted motor speed parameter from external source (e.g. SCI)

8. Configure PMF period and duty cycle.

9. Startup motor by applying FOC startup algorithm.

10. Take samples of the phase currents periodically based on PWM cycle to determine motor speed.

11. Calculate FOC algorithm to determine back EMF and motor position.

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Figure 1-16. Sensorless PMSM Control Loop Configuration

1.13.6.2 PMSM Operation With Sine-Cosine Position Sensor

In this configuration the PMSM stator winding currents are driven sinusoidally and the back EMF

waveform is also sinusoidal. Thus all 3 phases are active simultaneously. The back EMF voltage is

calculated based on the currents. The rotor position and speed are determined by a sine/cosine sensor,

which generates sinusoidal sine/cosine signals, indicating the angle of the rotor in relation to sensor

windings. The sensor is supplied by the EVDD1 pin.

1. Configure PMF for complementary mode operation.

2. Configure PMF for center aligned or phase shifted operation.

3. Select correct PMF deadtime insertion based on external FET switches.

4. Enable GDU current sense opamps for measuring the phase currents from external shunts.

5. Map the output pin of each current sense opamp to the ADC input.

PMF

PTU

ADC0

GDU

ADC1

reload

glb_ldok

reload

dc_bus_current1

dc_bus_voltage

trigger_0

trigger_1

dc_bus_current0

zero crossing

IS0

IS1

IS2

phase comparison

reloada

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6. Map the sine/cosine input signals to ADC input channels.

7. Configure the EVDD1 pin as output.

8. Optionally use GDU phase comparators for zero crossing detection to correct dead time distortion.

9. Fetch targeted motor speed parameter from external source (e.g. SCI)

10. Configure PMF period and duty cycle.

11. Start motor by applying startup algorithm.

12. Sample the sine/cosine voltages periodically based on PWM cycle to determine motor position.

13. Use FOC algorithm to determine back EMF and motor speed.

Figure 1-17. PMSM Sine/Cosine Control Loop Configuration

PMF

PTU

ADC0

GDU

ADC1

reload

glb_ldok

reload

dc_bus_current1

dc_bus_voltage

trigger_0

trigger_1

dc_bus_current0

zero crossing

IS0

IS1

IS2

sine/cosine

sensor

phase comparison

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1.13.6.3 Dead time Distortion Correction

PMSM motor control applications driven by sinusoidal voltages by default require zero crossing

information of phase currents to determine the point in time to change sign of deadtime compensation

value to be added to duty cycles.

The GDU phase comparator signals are connected internally to the PMF ISx inputs. This allows the dead

time distortion correction to be applied directly based on the phase status.

1. Align rotor to stator field.

2. Await phase comparator status change.

3. Switch to alternate duty cycle register to compensate distortion.

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96 NXP Semiconductors

1.13.7 Power Domain Overview (All devices except ZVMC256)

The power domains are illustrated in Figure 1-18. More detailed information is included in the individual

module descriptions.

Figure 1-18. Power Domain Overview

The system supply voltage VRBATP is a reverse battery protected input voltage. It must be protected

against reverse battery connections and must not be connected directly to the battery voltage (VBAT).

The device supply voltage VSUP provides the input voltage for the internal regulator, VREG_AUTO,

which generates the voltages VDDX, VDD and VDDF. The VDDX domain supplies the device I/O pins,

VDDA supplies the ADC and internal bias current generators. The VDDA and VDDX pins must be

connected at board level, they are not connected directly internally. ESD protection diodes exist between

VDDX and VDDA, therefore forcing a common operating range. The VDD domain supplies the internal

device logic. The VDDF domain supplies sections of the internal Flash NVM circuitry.

GHHDF

CORE

RAM’s

PLL

IRC

OSC

FLASH

PADS

GDU

LDO

BOOST

LINPHY

VREG_AUTO

(5V)

1.8V 2.8V 5V

VDDA

VDDC

BCTLC

VDD

VDDF

VSSA

VSS

VLS_OUT

VLINSUP

GPIO

VSSX

VSSB BST

LVSUP (12V/18V)

BCTL

VDDX

LIN

LGND EXTXONEXTCON

GBOE

GFDE

PORF

LVRF

GLVLSF

CPS

INT

RES

BATS

INT

VRBATP

ADC

VRH_SEL

VRL_SEL

PAD8 VRH

VRL

VSSA

VDDA

ADC

GCPE

INTXON

VRBATP

VLS

(11V)

VCP

(OPT L)

(OPT C)

OPT L = LINPHY p ackage option

OPT C = CANPHY package option

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NXP Semiconductors 97

The device supports the use of an external PNP to supplement the VDDX supply, for reducing on chip

power dissipation. In this configuration, most of the current flowing from VRBATP to VDDX, flows

through the external PNP. This configuration, using the BCTL pin, can be enabled by register bits

EXTXON and INTXON.

The maximum current that can be sourced by the voltage regulator without the external PNP is specified

as IDDX, for different VSUP ranges, in the electrical parameter appendices. Depending on activity and

external loading, an application current may exceed this specification limit. In such cases the external PNP

configuration must be used.

A supply for an external CANPHY is offered via external device pins BCTLC and VDDC, whereby

BCTLC provides the base current of an external PNP and VDDC is the CANPHY supply (output voltage

of the external PNP). This is only available in the CANPHY package option. This configuration can be

enabled by the register bit EXTCON. An external diode is recommended between VDDC and VDDA.

The LINPHY pull-up resistor is internally connected to VLINSUP.

The ADC register bit VRH_SEL maps the ADC reference VRH to VDDA or to the device pin PAD8.

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98 NXP Semiconductors

1.13.8 Power Domain Overview (ZVMC256)

Figure 1-19. Power Domain Overview (ZVMC256)