QS5807/A GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER FEATURES: - - - - - - QS5807/A DESCRIPTION: 10 outputs Rail-to-rail output voltage swing Input hysteresis for better noise margin Guaranteed low skew: * 0.3ns output skew (same bank) * 0.6ns output skew (different bank) * 1ns part-to-part skew Std. and A speed grades Available in QSOP packages The QS5807 clock driver/buffer circuits can be used for clock buffering schemes where low skew is a key parameter. The QS5807 offers ten non-inverting outputs. Designed in IDT's proprietary QCMOS process, these devices provide low propagation delay buffering with on-chip skew of 0.3ns for same-transition signals. The QS5807 is characterized for operation at -40C to +85C. FUNCTIONAL BLOCK DIAGRAM O1 O2 O3 O4 O5 IN O6 O7 O8 O9 O 10 INDUSTRIAL TEMPERATURE RANGE JANUARY 2001 1 c 2001 Integrated Device Technology, Inc. DSC-5231/2 QS5807/A GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol VTERM(2) (1) Description Supply Voltage to Ground Max. - 0.5 to +7 Unit V IN 1 20 VCC DC Output Voltage VOUT - 0.5 to +7 V G ND 2 19 O 10 VTERM(3) DC Input Voltage VIN - 0.5 to +7 V O1 3 18 O9 VAC AC Input Voltage (pulse width 20ns) -3 V V CC 4 17 G ND IOUT DC Output Current VIN < 0 -20 mA DC Output Current Max. Sink Current/Pin 120 mA O2 5 G ND 16 O8 6 15 VCC O3 7 14 O7 V CC 8 13 G ND O4 9 12 O6 G ND 10 11 O5 SO 20-8 TSTG Storage Temperature - 65 to +150 C TJ Junction Temperature +150 C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc Terminals. 3. All terminals except Vcc. QSOP/ SOIC TOP VIEW CAPACITANCE Pins CIN (TA = +25OC, f = 1.0MHz, VIN = 0V) Typ. 3 Max. (1) 6 NOTE: 1. This parameter is guaranteed but not production tested. PIN DESCRIPTION 2 Pin Names IN I/O I Description Clock Input Ox O Clock Outputs Unit pF QS5807/A GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10%, VHC = VCC - 0.2V, VLC = 0.2V Symbol VIH Parameter Input HIGH Voltage Test Conditions Guaranteed Logic HIGH for All Inputs Min. 2 Typ.(1) -- Max. -- Unit V VIL Input LOW Voltage Guaranteed Logic LOW for All Inputs -- -- 0.8 V VIC Clamp Diode Voltage (3) Vcc = Min., IIN = -18mA -- -0.7 -1.2 V VOH Output HIGH Voltage Vcc = Min., VIN = VIH or VIL, IOH = -300A VHC Vcc -- Vcc = Min., VIN = VIH or VIL, IOH = -15mA 3.6 4.3 -- Vcc = Min., VIN = VIH or VIL, IOH = -24mA 2.4 3.8 -- VOL Output LOW Voltage IIN Input Leakage Current IOFF Input Power Off Leakage IOS Short Circuit Current VT Input Hysteresis (2,3) Vcc = Min., VIN = VIH or VIL, IOL = 300A -- GND VLC Vcc = Min., VIN = VIH or VIL, IOL = 64mA -- 0.3 0.55 Vcc = Max., VIN = VCC or GND -- -- 1 Vcc = 0V, VIN = VCC or GND V V A -- -- 1 A Vcc = Max., VOUT = GND -60 -- -- mA VTLH - VTHL for All Inputs -- 0.2 -- V NOTES: 1. Typical values are at VCC = 5.0V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. POWER SUPPLY CHARACTERISTICS Symbol ICC Parameter Quiescent Power Supply Current Test Conditions VCC = Max., VIN = GND or Vcc ICC Supply Current per Input HIGH ICCD Dynamic Power Supply Current per Output (1) VCC = Max., VIN = 3.4V Input toggling at 50% duty cycle VCC = Max., outputs Enabled IC Total Power Supply Current Examples (2) VCC = Max., Input at 50% duty cycle fI = 10MHz VCC = Max., Input at 50% duty cycle fI = 2.5MHz NOTES: 1. Guaranteed by design but not tested. CL = 0pF. 2. IC = ICC + (ICC)(DH)(NT) + ICCD (fO)(NO) where: DH = Input Duty Cycle NT = Number of TTL HIGH inputs at DH fO = Output Frequency NO = Number of outputs at fO 3 Typ. 0.005 Max. 0.5 Unit mA 0.5 2.5 mA 0.12 0.2 mA/MHz VIN = GND or Vcc 12 21 mA VIN = GND or 3V 12 2.2 VIN = GND or Vcc 3 6 VIN = GND or 3V 3.5 7 QS5807/A GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE TA = -40C to +85C, VCC = 5.0V 10% CLOAD = 50pF, RLOAD = 500 unless otherwise noted. QS5807 Parameter (1) Symbol QS5807A Min. Max. Min. Max. Unit tSK(01) Skew between all outputs, same transition -- 0.5 -- 0.35 ns tSK(P) Pulse Skew; skew between opposite transitions of the same output (tPHL - tPLH) 1 -- 1 ns tSK(T) tPLH tPHL Part-to-part skew (2) Propagation Delay (2) IN to Ox -- -- 1.5 -- 1.5 ns 1.5 5.6 1.5 5.3 ns -- 1.5 -- 1.5 ns -- 3 -- 3 ns tR tF Output Rise Time, 0.8V to 2V (3) Output Fall Time, 0.2Vcc to 0.8Vcc (3) NOTES: 1. Skew parameters are guaranteed across temperature range, but not tested. Skew parameters are measured at 0.5Vcc. 2. tSK(T) only applies to devices of the same transition, part type, temperature, power supply voltage, loading, package, and speed grade. 3. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delays do not imply limit skew. 4 QS5807/A GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS V CC V IN V O UT Pulse Generator DU T 50pF 50 500 Pulse generator for all puls es: f 1.0M Hz; t F 2.5ns; tR 2.5ns PULSE SKEW -- tSK(P) PROPAGATION DELAY 3V 3V 1.5V INPUT INPU T 1.5V 0V tP LH 0V t PH L tP H L t P LH VOH VOH OUTPUT 2.0V OUTPUT 0.5V C C 0.5V C C 0.8V VOL tR VOL tSK(p) = t PHL - t PLHL tF OUTPUT SKEW -- tSK(O1) PART-TO-PART SKEW -- tSK(T) 3V 3V 1.5V INPUT 1.5V INPU T 0V tP HL1 tP LH 1 0V t P HL1 tP LH 1 VOH VOH PART 1 O UTPUT 0.5V C C 0.5V C C OUTPUT 1 VOL VOL tSK (O 1) tSK(t) tSK(t) VOH t SK(O 1) VOH OUTPUT 2 PART 2 O UTPUT 0.5V C C 0.5V C C VOL tP LH 2 VOL tP LH 2 tP HL2 tP HL2 t SK(01) = t PLH2 - t PLH1 or t PHL 2 - t PHL1 t SK(p) = t PLH2 - t PLH1 or t PHL2 - t PHL1 5 QS5807/A GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type X Package Q Quarter-size Sm all Outline Package (SO20-8) 5807 5807A Guaranteed Low Skew CM OS Clock Driver/Buffer CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. 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