Real-Time Analog
Computational Unit (ACU)
AD538
Rev. E
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FEATURES
VO = VY(VZ/VX)m transfer function
Wide dynamic range (denominator) −1000:1
Simultaneous multiplication and division
Resistor-programmable powers and roots
No external trims required
Low input offsets <100 μV
Low error ±0.25% of reading (100:1 range)
Monolithic construction
Real-time analog multiplication, division and
exponentiation
High accuracy analog division with a wide input dynamic range
On board +2 V or +10 V scaling reference
Voltage and current (summing) input modes
Monolithic construction with lower cost and higher
reliability than hybrid and modular circuits
APPLICATIONS
One- or two-quadrant multiply/divide
Log ratio computation
Squaring/square rooting
Trigonometric function approximations
Linearization via curve fitting
Precision AGC
Power functions
FUNCTIONAL BLOCK DIAGRAM
VO
A
B
D
VX
VZ
VY
+10
V
+2V
C
I
IX
IZ
IY
00959-001
100Ω
100Ω
25kΩ
25kΩ
AD538
LOG
RATIO
25kΩ
OUTPUT
ANTILOG
INTERNAL
VOLTAG E
REFERENCE
LOG
Figure 1.
GENERAL DESCRIPTION
The AD538 is a monolithic real-time computational circuit
that provides precision analog multiplication, division, and
exponentiation. The combination of low input and output offset
voltages and excellent linearity results in accurate computation
over an unusually wide input dynamic range. Laser wafer
trimming makes multiplication and division with errors as low
as 0.25% of reading possible, while typical output offsets of
100 μV or less add to the overall off-the-shelf performance level.
Real-time analog signal processing is further enhanced by the
400 kHz bandwidth of the device.
The overall transfer function of the AD538 is VO = VY(VZ/VX)m.
Programming a particular function is via pin strapping. No
external components are required for one-quadrant (positive
input) multiplication and division. Two-quadrant (bipolar
numerator) division is possible with the use of external level
shifting and scaling resistors. The desired scale factor for both
multiplication and division can be set using the on-chip +2 V or
+10 V references, or controlled externally to provide simultaneous
multiplication and division. Exponentiation with an m value
from 0.2 to 5 can be implemented with the addition of one or
two external resistors.
Direct log ratio computation is possible by using only the log
ratio and output sections of the chip. Access to the multiple
summing junctions adds further to the flexibility of the AD538.
Finally, a wide power supply range of ±4.5 V to ±18 V allows
operation from standard ±5 V, ±12 V and ±15 V supplies.
The AD538 is available in two accuracy grades (A and B) over
the industrial (−25°C to +85°C) temperature range and one
grade (S) over the military (−55°C to +125°C) temperature
range. The device is packaged in an 18-lead TO-118 hermetic
side-brazed ceramic DIP. A-grade chips are also available.
AD538
Rev. E | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ........................................................................ 9
Re-Examination of Multiplier/Divider Accuracy .................... 9
Functional Description .............................................................. 10
Stability Precautions ................................................................... 10
Using The Voltage References .................................................. 10
One-Quadrant Multiplication/Division .................................. 11
Two-Quadrant Division ............................................................ 12
Log Ratio Operation .................................................................. 12
Analog Computation Of Powers And Roots .......................... 13
Square Root Operation .............................................................. 13
Applications Information .............................................................. 15
Transducer Linearization .......................................................... 15
ARC-Tangent Approximation .................................................. 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
6/11—Rev. D to Rev. E
Updated Format .................................................................. Universal
Added Table 3 .................................................................................... 6
Changes to Ordering Guide .......................................................... 11
5/10—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 11
Changes to Ordering Guide .......................................................... 11
AD538
Rev. E | Page 3 of 16
SPECIFICATIONS
VS = ±15 V, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Test Conditions/
Comments
AD538AD AD538BD AD538SD
Unit Min Typ Max Min Typ Max Min Typ Max
MULTIPLIER DIVIDER
PERFORMANCE
Nominal Transfer
Function
10 V ≥ VX, VY, VZ ≥ 0 VO = VY(VZ/VX)m VO = VY(VZ/VX)m VO = VY(VZ/VX)m
400 µA ≥ IX, IY, IZ ≥ 0 VO = 25 kΩ × IY(IZ/IX)m VO = 25 kΩ × IY(IZ/IX)m VO = 25 kΩ × IY(IZ/IX)m
Total Error Terms 100 mV ≤ VX ≤ 10 V ±0.5 ±1 ±0.25 ±0.5 ±0.5 ±1 % of Reading +
100:1 Input
Range1
100 mV ≤ VY ≤ 10 V
±200 ±500 ±100 ±250 ±200 ±500 µV
100 mV ≤ VZ ≤ 10 V
VZ ≤ 10 VX, m = 1.0
TA = TMIN to TMAX ±1 ±2 ±0.5 ±1 ±1.25 ±2.5 % of Reading +
±450 ±750 ±350 ±500 ±750 ±1000 µV
Wide Dynamic
Range2
100 mV ≤ VX ≤ 10 V
±1 ±2 ±0.5 ±1 ±1 ±2 % of Reading +
100 mV ≤ VY ≤ 10 V ±200 ±500 ±100 ±250 ±200 ±500 µV
100 mV ≤ VZ ≤ 10 V ±100 ±250 ±750 ±150 ±200 ±250 µV × (VY + VZ)/VX
VZ ≤ 10 VX, m = 1.0
TA = TMIN to TMAX ±1 ±3 ±1 ±2 ±2 ±4 % of Reading +
±450 ±750 ±350 ±500 ±750 ±1000 µV +
±450 ±750 ±350 ±500 ±750 ±1000 µV × (VY +
VZ)/VX
Exponent (m)
Range
TA = TMIN to TMAX 0.2 5 0.2 5 0.2 5
OUTPUT
CHARACTERISTICS
Offset Voltage VY = 0, VC =
−600 mV
±200 ±500 ±100 ±250 ±200 ±500 µV
TA = TMIN to TMAX ±450 ±750 ±350 ±500 ±750 ±1000 µV
Output Voltage
Swing
RL = 2 kΩ −11 +11 −11 +11 −11 +11 V
Output Current 5 10 5 10 5 10 mA
FREQUENCY
RESPONSE
Slew Rate 1.4 1.4 1.4 V/µs
Small Signal
Bandwidth
100 mV ≤ 10 VY, VZ,
VX ≤ 10 V
400 400 400 kHz
VOLTAGE REFERENCE
Accuracy VREF = 10 V or 2 V ±25 ±50 ±15 ±25 ±25 ±50 mV
Additional Error TA = TMIN or TMAX ±20 ±30 ±20 ±30 ±30 ±50 mV
Output Current VREF = 10 V to 2 V 1 2.5 1 2.5 1 2.5 mA
Power Supply
Rejection
+2 V = VREF ±4.5 V ≤ VS ≤ ±18 V 300 600 300 600 300 600 µV/V
+10 V = VREF ±13 V ≤ VS ≤ ±18 V 200 500 200 500 200 500 µV/V
POWER SUPPLY
Rated RL = 2 kΩ ±15 ±15 ±15 V
Operating Range3 ±4.5 ±18 ±4.5 ±18 ±4.5 ±18 V
PSRR ±4.5 V<, VS < ±18 V 0.5 0.1 0.5 0.1 0.5 0.1 %/V
VX = VY = VZ = 1 V
VO = 1 V
Quiescent Current 4.5 7 4.5 7 4.5 7 mA
AD538
Rev. E | Page 4 of 16
Parameter
Test Conditions/
Comments
AD538AD AD538BD AD538SD
Unit Min Typ Max Min Typ Max Min Typ Max
TEMPERATURE RANGE
Rated −25 +85 −25 +85 −55 +125 °C
Storage −65 +150 −65 +150 −65 +150 °C
1 Over the 100 mV to 10 V operating range total error is the sum of a percent of reading term and an output offset. With this input dynamic range the input offset
contribution to total error is negligible compared to the percent of reading error. Thus, it is specified indirectly as a part of the percent of reading error.
2 The most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by
the incremental gain (VY + VZ) VX.
3 When using supplies below ±13 V, the 10 V reference pin must be connected to the 2 V pin in order for the AD538 to operate correctly.
AD538
Rev. E | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation 250 mW
Output Short Circuit-to-Ground Indefinite
Input Voltages VX, VY, VZ (+VS − 1 V), −1 V
Input Currents IX, IY, IZ, IO 1 mA
Operating Temperature Range −25°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Storage 60 sec, +300°C
Thermal Resistance
θJC 35°C/W
θJA 120°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD538
Rev. E | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
00959-002
I
Z1
V
Z2
B
3
+10V
4
A
18
D
17
I
X
16
V
X
15
+2V
5
SIGNAL GND
14
+V
S6
PW R GND
13
–V
S7
C
12
V
O8
I
Y
11
I
9
V
Y
10
AD538
TOP VIEW
(No t t o Scal e)
Figure 2. Pin Configuration
Table 3.
Pin No. Mnemonic Description
1 IZ Current Input for the Z Multiplicand.
2 VZ Voltage Input for the Z Multiplicand.
3 B Output of the Log Ratio Differential Amplifier. This amplifier subtracts the log of the Z input from the log of the X
input, or performs the equivalent logarithmic equivalent of long division.
4 +10V +10 V Reference Voltage Output.
5 +2V +2 V Reference Voltage Output.
6 +VS Positive Supply Rail.
7 –VS Negative Rail.
8 VO Output Voltage.
9 I Current Input to the Output Amplifier.
10 VY Voltage Input to the Y Multiplicand.
11 IY Current Input to the Y Multiplicand.
12 C Current Input to the Base of the Antilog Log-to-Linear Converter.
13 PWR GND High level Power Return of the Chip.
14 SIGNAL GND Low Level Ground Return of the Device.
15 VX Voltage Input of the X Multiplicand.
16 IX Current Input of the X Input Multiplicand.
17 D Use for Log Ratio Function.
18 A Use for Log Ratio Function.
AD538
Rev. E | Page 7 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
51000
800
600
400
200
0
4
3
2
1
0
–55 –40 –20 020 40 60 80 100 125
TEMPERATURE (°C)
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET (µV)
00959-003
OFFSET
% OF READI NG
Figure 3. Multiplier Error vs. Temperature (100 mV < VX, VY, VZ ≤ 10 V)
51000
800
600
400
200
0
4
3
2
1
0
–55 –40 –20 020 40 60 80 100 125
TEMPERATURE (°C)
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET (µV)
00959-004
OFFSET
% OF READI NG
Figure 4. Divider Error vs. Temperature (100 mV < VX, VY, VZ ≤ 10 V)
1000
100
10
1
100 1k 10k 100k 1M
INP UT FRE QUENCY ( Hz )
V
O
(mV p-p)
00959-005
V
X
= 10V
V
Y
= 0V
V
Z
= 5V +5V SIN ωt VOLTS
Figure 5. VZ Feedthrough vs. Frequency
1M
100k
400k
10k
40k
0.01 0.1 110
DENOMINATOR VOLTAGE, V
X
– V d c
SMALL S IG NAL BANDWIDT H ( Hz )
00959-006
V
Y
= 10V d c
V
Z
= V
X
+0.05 V
X
SIN ωt
Figure 6. Small Signal Bandwidth vs. Denominator Voltage (One-Quadrant
Mult/Div)
5
6
1000
1200
800
600
400
200
0
4
3
2
1
0
–55 –40 –20 020 40 60 80 100 125
TEMPERATURE (°C)
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET (µV)
00959-007
% OF READI NG
OFFSET
Figure 7. Multiplier Error vs. Temperature (10 mV < VX, VY, VZ ≤ 100 mV)
51000
800
600
400
200
0
4
3
2
1
0
–55 –40 –20 020 40 60 80 100 125
TEMPERATURE (°C)
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET (µV)
00959-008
% OF READI NG
OFFSET
Figure 8. Divider Error vs. Temperature (10 mV < VX, VY, VZ ≤ 100 mV)
AD538
Rev. E | Page 8 of 16
100
150
10
1
0.1
100 1k 10k 100k 1M
INP UT FRE QUENCY ( Hz )
V
O
(mV p-p)
00959-009
V
X
= 10V
V
Y
= 5V +5V SIN ωt VOLTS
V
Z
= 0V
Figure 9. VY Feedthrough vs. Frequency
5
4
3
2
1
0
0.01 0.1 110
DC OUTPUT VOLTAGE (V)
VOLTAGE NOISE (e
n
– µV/ Hz)
00959-010
V
X
= 0.01V
V
X
= 10V
FOR THE FREQUENCY RANGE OF 10Hz
TO 100kHz T HE TO TAL rms OUT P UT
NOISE, e
o
, FOR A GI V E N BANDWIDTH
Bw, IS CALCUL ATED e
o
= e
n
Bw.
Figure 10. 1 kHz Output Noise Spectral Density vs. DC Output Voltage
AD538
Rev. E | Page 9 of 16
THEORY OF OPERATION
RE-EXAMINATION OF MULTIPLIER/DIVIDER ACCURACY
Traditionally, the accuracy (actually the errors) of analog
multipliers and dividers has been specified in terms of percent
of full scale. Thus specified, a 1% multiplier error with a 10 V
full-scale output would mean a worst-case error of +100 mV at
any level within its designated output range. While this type of
error specification is easy to test evaluate, and interpret, it can
leave the user guessing as to how useful the multiplier actually
is at low output levels, those approaching the specified error
limit (in this case) 100 mV.
The error sources of the AD538 do not follow the percent of
full-scale approach to specification, thus it more optimally
fits the needs of the very wide dynamic range applications
for which it is best suited. Rather than as a percent of full
scale, the AD538’s error as a multiplier or divider for a 100:1
(100 mV to 10 V) input range is specified as the sum of two
error components: a percent of reading (ideal output) term
plus a fixed output offset. Following this format, the AD538AD,
operating as a multiplier or divider with inputs down to 100 mV,
has a maximum error of ±1% of reading ±500 μV. Some sample
total error calculations for both grades over the 100:1 input
range are illustrated in Table 4. This error specification format
is a familiar one to designers and users of digital voltmeters
where error is specified as a percent of reading ± a certain
number of digits on the meter readout.
For operation as a multiplier or divider over a wider dynamic
range (>100:1), the AD538 has a more detailed error specification
that is the sum of three components: a percent of reading term,
an output offset term, and an input offset term for the VY/VX log
ratio section. A sample application of this specification, taken
from Table 4, for the AD538AD with VY = 1 V, VZ = 100 mV
and VX = 10 mV would yield a maximum error of ±2.0% of
reading ±500 μV ± (1 V + 100 mV)/10 mV × 250 μV or ±2.0%
of reading ±500 μV ± 27.5 mV. This example illustrates that
with very low level inputs the AD538’s incremental gain (VY +
VZ)/VX has increased to make the input offset contribution to
error substantial.
Table 4. Sample Error Calculation Chart (Worst Case)
VY
Input
(V)
VZ
Input
(V)
VX
Input
(V)
Ideal
Output
(V)
Total O ffset Error
Term (mV)
% of Reading
Error Term
(mV)
Total Error
Summation
(mV)
Total Error
Summation as a
% of the Ideal
Output
100:1 INPUT
RANGE
Total Error =
±% rdg
±Output VOS
10 10 10 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD)
0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD)
10 0.1 0.1 10 0.5 (AD) 100 (AD) 100.5 (AD) 1.0 (AD)
0.25 (BD) 50 (BD) 50.25 (BD) 0.5 (BD)
1 1 1 1 0.5 (AD) 10 ) (AD 10.5 (AD) 1.05 (AD)
0.25 (BD) 5 (BD) 5.25 (BD) 0.5 (BD)
0.1 0.1 0.1 0.1 0.5 (AD) 1 (AD) 1.5 (AD) 1.5 (AD)
0.25 (BD) 0.5 (BD) 0.75 (BD) 0.75 (BD)
WIDE
DYNAMIC
RANGE
Total Error =
±% rdg ±
Output VOS ±
Input VOS ×
(VY + VZ)/VX
1 0.10 0.01 10 28 (AD) 200 (AD) 228 (AD) 2.28 (AD)
16.75 (BD) 100 (BD) 116.75 (BD) 1.17 (BD)
10 0.05 2 0.25 1.76 (AD) 5 (AD) 6.76 (AD) 2.7 (AD)
1 (BD) 2.5 (BD) 3.5 (BD) 1.4 (BD)
5 0.01 0.01 5 125.75 (AD) 100 (AD) 225.75 (AD) 4.52 (AD)
75.4 (BD) 50 (BD) 125.4 (BD) 2.51 (BD)
10 0.01 0.1 1 25.53 (AD) 20 (AD) 45.53 (AD) 4.55 (AD)
15.27 (BD) 10 (BD) 25.27 (BD) 2.53 (BD)
AD538
Rev. E | Page 10 of 16
FUNCTIONAL DESCRIPTION
As shown in Figure 1 and Figure 11, the VZ and VX inputs
connect directly to the input log ratio amplifiers of the AD538.
This subsection provides an output voltage proportional to the
natural log of input voltage, VZ, minus the natural log of input
voltage, VX. The output of the log ratio subsection at B can be
expressed by the transfer function
=
X
Z
B
V
V
q
kT
Vln
where:
k is 1.3806 × 10−23 J/K.
q is 1.60219 × 10−19 C.
T is in Kelvins.
The log ratio configuration may be used alone, if correctly
temperature compensated and scaled to the desired output
level (see the Applications Information section).
Under normal operation, the log-ratio output will be directly
connected to a second functional block at Input C, the antilog
subsection. This section performs the antilog according to the
transfer function:
=kT
q
VeVV C
Y
O
As with the log-ratio circuit included in the AD538, the user
may use the antilog subsection by itself. When both subsections
are combined, the output at B is tied to C, the transfer function
of the AD538 computational unit is:
VO = VY
e
C
B
V
V
kT
q
Q
kT
VV
X
Z
=
;
ln
which reduces to:
=
X
Z
Y
O
V
V
VV
Finally, by increasing the gain, or attenuating the output of the
log ratio subsection via resistor programming, it is possible to
raise the quantity VZ/VX to the mth power. Without external
programming, m is unity. Thus, the overall AD538 transfer
function equals:
m
X
Z
Y
O
V
V
VV
=
where 0.2 < m < 5.
When the AD538 is used as an analog divider, the VY input can
be used to multiply the ratio VZ/VX by a convenient scale factor.
The actual multiplication by the VY input signal is accomplished
by adding the log of the VY input signal to the signal at C, which
is already in the log domain.
STABILITY PRECAUTIONS
At higher frequencies, the multistaged signal path of the AD538
can result in large phase shifts (as illustrated in Figure 11). If a
condition of high incremental gain exists along that path (for
example, VO = VY × VZ/VX = 10 V × 10 mV/10 mV = 10 V so
that ΔVO/ΔVX = 1000), then small amounts of capacitive feedback
from VO to the current inputs IZ or IX can result in instability.
Appropriate care should be exercised in board layout to prevent
capacitive feedback mechanisms under these conditions.
00959-012
LOG
e
I
Y
V
Y
Ln Y
LOG
e
I
Z
V
Z
Ln Z
LOG
e
I
X
V
X
Ln X
ΣΣ
BUFFER
+++
–
Ln Z – Ln X
M(Ln Z – Ln X)
M(Ln Z – Ln X) +Ln Y
ANTILOG
e
0.2≤M≤5
V
O
= V
Y
V
Z
V
X
M
Figure 11. Model Circuit
USING THE VOLTAGE REFERENCES
A stable band gap voltage reference for scaling is included in the
AD538. It is laser-trimmed to provide a selectable voltage output of
+10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any voltages
between +2 V and +10.2 V buffered as shown in Figure 12. The
output impedance at Pin 5 is approximately 5 kΩ. Note that any
loading of this pin produces an error in the +10 V reference
voltage. External loads on the +2 V output should be greater
than 500 kΩ to maintain errors less than 1%.
25kΩ
25kΩ
100Ω
25kΩ
25kΩ
ANTILOG
LOG
OUTPUT
100Ω
50kΩ
+2V T O +10.2V
BUFFERED
11.5kΩ
AD538
I
Y
A
D
I
X
V
X
C
V
Y
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
I
Z
V
Z
V
O
I
+V
S
–V
S
B
REF OUT
+2V
00959-013
Figure 12. +2 V to +10.2 V Adjustable Reference
In situations not requiring both reference levels, the +2 V output
can be converted to a buffered output by tying Pin 4 and Pin 5
together. If both references are required simultaneously, the
+10 V output should be used directly and the +2 V output
should be externally buffered.
AD538
Rev. E | Page 11 of 16
ONE-QUADRANT MULTIPLICATION/DIVISION
Figure 13 shows how the AD538 may be easily configured
as a precision one-quadrant multiplier/divider. The transfer
function VO = VY (VZ/VX) allows three independent input
variables, a calculation not available with a conventional
multiplier. In addition, the 1000:1 (that is, 10 mV to 10 V)
input dynamic range of the AD538 greatly exceeds that of
analog multipliers computing one-quadrant multiplication
and division.
25kΩ
25kΩ
100Ω
25kΩ
25kΩ
ANTILOG
LOG
OUTPUT
100Ω
AD538
I
Y
A
D
I
X
V
X
C
IN4148
V
Y
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
I
Z
V
Z
V
Z
INPUT
V
O
I
+15V
–15V
B
+10V
+2V
00959-014
OUTPUT V
Y
INPUT
V
X
INPUT
V
O
= V
Y
V
Z
V
X
Figure 13. One-Quadrant Combination Multiplier/Divider
By simply connecting the input, VX (Pin 15) to the 10 V
reference (Pin 4), and tying the log-ratio output at B to the
antilog input at C, the AD538 can be configured as a one-
quadrant analog multiplier with 10 V scaling. If 2 V scaling
is desired, VX can be tied to the 2 V reference.
When the input VX is tied to the +10 V reference terminal, the
multiplier transfer function becomes:
=V
V
VV
Z
Y
O
10
As a multiplier, this circuit provides a typical bandwidth of 400 kHz
with values of VX, VY, or VZ varying over a 100:1 range (that is,
100 mV to 10 V). The maximum error with a 100 mV to 10 V
range for the two input variables will typically be +0.5% of
reading. Using the optional Z offset trim scheme, as shown in
Figure 14, this error can be reduced to +0.25% of reading.
By using the 10 V reference as the VY input, the circuit of
Figure 13 is configured as a one-quadrant divider with a fixed
scale factor. As with the one-quadrant multiplier, the inputs
accept only single (positive) polarity signals. The output of the
one-quadrant divider with a +10 V scale factor is:
=
X
Z
O
V
V
VV 10
The typical bandwidth of this circuit is 370 kHz with 1 V to
10 V denominator input levels. At lower amplitudes, the band-
width gradually decreases to approximately 200 kHz at the
2 mV input level.
AD538
Rev. E | Page 12 of 16
TWO-QUADRANT DIVISION
The two-quadrant linear divider circuit illustrated in Figure 14
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage
to it. The offsetting scheme changes the divider’s transfer
function from
=
X
Z
O
V
V
VV10
to
( )
+=
+=
+
=
X
Z
X
Z
X
X
Z
O
V
V
V
V
A
V
AVV
V
V10A10
1V10V10
where:
=kΩ25
kΩ35
A
As long as the magnitude of the denominator input is equal
to or greater than the magnitude of the numerator input, the
circuit accepts bipolar numerator voltages. However, under
the conditions of a 0 V numerator input, the output would
incorrectly equal +14 V. The offset can be removed by connecting
the 10 V reference through Resistors R1 and R2 to the output
section’s summing Node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The potentiometer,
R2, adjusts out or corrects this offset, leaving the desired
transfer function of 10 V (VZ/VX).
25kΩ
35kΩ
R2
10kΩ
R1
12.4kΩ
25kΩ
35kΩ
100Ω
25kΩ
25kΩ
ANTILOG
LOG
OUTPUT
ZERO
ADJUST
100Ω
AD538
IY
A
D
IX
VX
CIN4148
VY
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
IZ
VZ
VO
I
B
+10V
+2V
OUTPUT
VO = 10 FOR VX ≥ VZ
VZ
VX
10MΩ
VOS
3.9MΩ
1MΩ
ADJ
68kΩ
–1.2V
AD589
–VS
NUMERATOR
VZ
DENOMINATOR
VX
OPTIONAL
Z OFFSET TRIM
00959-015
+15V
–15V
Figure 14. Two-Quadrant Division with 10 V Scaling
LOG RATIO OPERATION
Figure 15 shows the AD538 configured for computing the log
of the ratio of two input voltages (or currents). The output
signal from B is connected to the summing junction of the
output amplifier via two series resistors. The 90.9 Ω metal film
resistor effectively degrades the temperature coefficient of the
±3500 ppm/°C resistor to produce a 1.09 kΩ +3300 ppm/°C
equivalent value. In this configuration, the VY input must
be tied to some voltage less than zero (−1.2 V in this case)
removing this input from the transfer function.
The 5 kΩ potentiometer controls the circuit’s scale factor
adjustment providing a +1 V per decade adjustment. The
output offset potentiometer should be set to provide a zero
output with VX = VZ = 1 V. T h e inp u t V Z adjustment should
be set for an output of 3 V with VZ = l mV and VX = 1 V.
25kΩ
1MΩ
AD589
68kΩ
5%
OPTIONAL
INPUT V
OS
ADJUSTMENT
10MΩ
–1.2V
–V
S
25kΩ
100Ω
90.9Ω
1%
1k
+3500
ppm/°C
25kΩ
25kΩ
ANTILOG
LOG
OUTPUT
100Ω
48.7Ω
AD538
I
Y
A
D
I
X
V
X
C
IN4148
V
Y
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
I
Z
V
Z
V
O
I
+15V
–15V
B
+10V
+2V
00959-016
OUTPUT
V
X
INPUT
V
Z
V
X
5kΩ
SCALE
FACTOR
ADJUST
OPTIONAL
OUTPUT V
OS
ADJUSTMENT
2kΩ
1%
+V
S
–V
S
10kΩ
10MΩ
V
O
= 1V LOG
10
Figure 15. Log Ratio Circuit
The log ratio circuit shown achieves ±0.5% accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of full-
scale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction
at the input of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (that is, 1 V × log10 (1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
AD538
Rev. E | Page 13 of 16
ANALOG COMPUTATION OF POWERS AND ROOTS
It is often necessary to raise the quotient of two input signals to
a power or take a root. This could be squaring, cubing, square
rooting or exponentiation to some noninteger power. Examples
include power series generation. With the AD538, only one or
two external resistors are required to set any desired power, over
the range of 0.2 to 5. Raising the basic quantity VZ/VX to a
power greater than one requires that the gain of the AD538’s log
ratio subtractor be increased, via an external resistor between
the A and D pins. Similarly, a voltage divider that attenuates the
log ratio output between Point B and Point C will program the
power to a value less than one.
00959-017
3 12 18 17
2
10 15
8
R
A
R
B
R
C
V
O
V
O
V
Z
V
Y
V
Z
V
Y
V
REF
V
X
V
REF
V
X
BCADPOWERS
m R
A
2 196Ω
3 97.6Ω
4 64.9Ω
5 48.7Ω
312
2
10 15
8
B C ROOTS
m R
B
R
C
1/2 100Ω 100Ω
1/3 100Ω 49.9Ω
1/4 150Ω 49.9Ω
1/5 162Ω 40.2Ω
R
A
=
R
B
= R
C
≤ 200Ω
196Ω
M – 1
V
Z
V
REF
V
Y
( )
m
V
Z
V
REF
V
Y
( )
m
= –1
R
B
R
C
1
M
Figure 16. Basic Configurations and Transfer Functions for the AD538
SQUARE ROOT OPERATION
The explicit square root circuit of Figure 17 illustrates a precise
method for performing a real-time square root computation.
For added flexibility and accuracy, this circuit has a scale factor
adjustment.
The actual square rooting operation is performed in this circuit
by raising the quantity VZ/VX to the one-half power via the
resistor divider network consisting of resistors RB and RC. For
maximum linearity, the two resistors should be 1% (or better)
ratio-matched metal film types.
1 V scaling is achieved by dividing-down the 2 V reference
and applying approximately 1 V to both the VY and VX inputs.
In this circuit, the VX input is intentionally set low, to about
0.95 V, so that the VY input can be adjusted high, permitting
a ±5% scale factor trim. Using this trim scheme, the output
voltage will be within ±3 mV ± 0.2% of the ideal value over a
10 V to 1 mV input range (80 dB). For a decreased input dynamic
range of 10 mV to 10 V (60 dB) the error is even less; here the
output will be within ±2 mV ± 0.2% of the ideal value. The
bandwidth of the AD538 square root circuit is approximately
280 kHz with a 1 V p-p sine wave with a +2 V dc offset.
This basic circuit may also be used to compute the cube, fourth
or fifth roots of an input waveform. All that is required for a
given root is that the correct ratio of resistors, RC and RB, be
selected such that their sum is between 150 Ω and 200 Ω.
The optional absolute value circuit shown preceding the AD538
allows the use of bipolar input voltages. Only one op amp is
required for the absolute value function because the IZ input of
the AD538 functions as a summing junction. If it is necessary to
preserve the sign of the input voltage, the polarity of the op amp
output may be sensed and used after the computation to switch
the sign bit of a DVM chip.
AD538
Rev. E | Page 14 of 16
00959-018
25kΩ
25kΩ
100Ω
25kΩ
25kΩ
ANTILOG
LOG
OUTPUT
100Ω
R
B
100Ω*
R
C
100Ω*
RATIO MATCH 1% METAL FILM
RESISTORS F OR BES T ACCURACY
*
AD538
I
Y
A
D
I
X
V
X
C
D1
IN4148
V
Y
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
I
Z
V
Z
V
O
I
+15V
–15V
B
+10V
+2V+2V
1kΩ
100Ω
SCALE FACTOR
TRIM
1kΩ
V
IN
20kΩ
20kΩ
10kΩ
5kΩ
OPTIONAL
ABSOLUTE VALUE SECTION
20kΩ
+V
S
V
OS
IN4148
AD OP-07
OR AD811
(V
OS
TAP
TO –V
S
)
IN4148
–V
S
27186
4
3
V
IN
1V
V
O
= 1V
V
O
Figure 17. Square Root Circuit
AD538
Rev. E | Page 15 of 16
APPLICATIONS INFORMATION
TRANSDUCER LINEARIZATION
Many electronic transducers used in scientific, commercial or
industrial equipment monitor the physical properties of a device
and/or its environment. Sensing (and perhaps compensating for)
changes in pressure, temperature, moisture or other physical
phenomenon can be an expensive undertaking, particularly
where high accuracy and very low nonlinearity are important.
In conventional analog systems accuracy may be easily increased
by offset and scale factor trims; however, nonlinearity is usually
the absolute limitation of the sensing device.
With the ability to easily program a complex analog function,
the AD538 can effectively compensate for the nonlinearities
of an inexpensive transducer. The AD538 can be connected
between the transducer preamplifier output and the next stage
of monitoring or transmitting circuitry. The recommended
procedure for linearizing a particular transducer is first to find
the closest function which best approximates the nonlinearity
of the device and then, to select the appropriate exponent
resistor value(s).
ARC-TANGENT APPROXIMATION
The circuit of Figure 18 is typical of those AD538 applications
where the quantity VZ/VX is raised to powers greater than one.
In an approximate arc-tangent function, the AD538 will accurately
compute the angle that is defined by X and Y displacements
represented by input voltages VX and VZ. With accuracy to
within one degree (for input voltages between 100 μV and
10 V), the AD538 arc-tangent circuit is more precise than
conventional analog circuits and is faster than most digital
techniques. The circuit shown is set up for the transfer
function:
( ) ( )
( )
21.1
−=
X
Z
REF
V
V
VVV
θθθ
where:
=
−
X
Z
Tan
1
θ
The (VθREF − Vθ) function is implemented in this circuit by
adding together the output, Vθ, and an externally applied
reference voltage, VθREF, via an external AD547 op amp. The
1 μF capacitor connected around the AD547’s 100 k Ω feedback
resistor frequency compensates the loop (formed by the amplifier
between Vθ and VY).
25kΩ
25kΩ
100Ω
25kΩ
25kΩ
ANTILOG
IN4148
LOG
OUTPUT
100Ω
AD538
I
Y
A
D
I
X
V
X
V
Z
1µF
1µF
V
X
C
V
Y
811
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
LOG
RATIO
INTERNAL
VOLTAGE
REFERENCE
SIGNAL
GND
PWR
GND
I
Z
V
Z
V
O
I
+V
S
–V
S
B
+10V
+2V
00959-019
V
θ
= [V
θREF
–V
θ
] × V
Z
V
X
1.21
θ = TAN
–1
Z
X
R
A
931Ω, 1%
V
θ
–15V
+15V
R1*
100kΩ
R2*
100kΩ
118kΩ
1µF
0.1µF
100kΩ
10kΩ
FULL-SCALE
ADJUST
+15V
–15V
7
4
3
6
2
AD547JH
RATI O MAT CH 1% M E TAL
FILM RESISTORS FOR BEST
ACCURACY
*
Figure 18. The Arc-Tangent Function
The VB/VA quantity is calculated in the same manner as in the
one-quadrant divider circuit, except that the resulting quotient
is raised to the 1.21 power. Resistor RA (nominally 931 Ω) sets
the power or m factor.
For the highest arc-tangent accuracy the R1 and R2 external
resistors should be ratio matched; however, the offset trim scheme
shown in other circuits is not required since nonlinearity effects
are the predominant source of error. Also note that instability
will occur as the output approaches 90° because, by definition,
the arc-tangent function is infinite and therefore, the gain of the
AD538 will be extremely high.
AD538
Rev. E | Page 16 of 16
OUTLINE DIMENSIONS
18
19
10
0.310 (7.87)
0.220 (5.59)
PIN 1
0.098 (2.49) MAX
0.005 (0.13) MIN
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18) 0.070 (1.78)
0.030 (0.76)
0.960 (24.38) MAX
0.100
(2.54)
BSC
0.150
(3.81)
MIN
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 19. 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-18)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model1Temperature Range Package Description Package Option
AD538ACHIPS −25°C to +85°C Chips
AD538AD −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18
AD538ADZ −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18
AD538BD −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18
AD538BDZ −25°C to +85°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18
AD538SD −55°C to +125°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18
AD538SD/883B −55°C to +125°C 18-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-18
1 Z = RoHS Compliant Part.
©2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00959-0-6/11(E)
