7025L35PFB - Integrated Device Technology

OCTOBER 2008

DSC 2683/10

1

IDT7025S/L

HIGH-SPEED

8K x 16 DUAL-PORT

STATIC RAM

Features

◆◆

◆True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

◆◆

◆High-speed access

– Military: 20/25/35/55/70ns (max.)

– Industrial: 55ns (max.)

– Commercial: 15/17/20/25/35/55ns (max.)

◆◆

◆Low-power operation

– IDT7025S

Active: 750mW (typ.)

Standby: 5mW (typ.)

– IDT7025L

Active: 750mW (typ.)

Standby: 1mW (typ.)

◆◆

◆Separate upper-byte and lower-byte control for multiplexed

bus compatibility

◆◆

◆IDT7025 easily expands data bus width to 32 bits or more

using the Master/Slave select when cascading more than

one device

◆◆

◆M/S = H for BUSY output flag on Master

M/S = L for BUSY input on Slave

◆◆

◆Interrupt Flag

◆◆

◆On-chip port arbitration logic

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆◆

◆Battery backup operation—2V data retention

◆◆

◆TTL-compatible, single 5V (±10%) power supply

◆◆

◆Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin

Quad Flatpack

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY outputs and INT outputs are non-tri-stated push-pull.

I/O

Control

Address

Decoder MEMORY

ARRAY

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

Address

Decoder

I/O

Control

R/W

L

BUSY

L

A

12L

A

0L

2683 drw 01

UB

L

LB

L

CE

L

OE

L

I/O

8L

-I/O

15L

I/O

0L

-I/O

7L

CE

L

OE

L

R/W

L

SEM

L

INT

L

M/S

R/W

R

BUSY

R

UB

R

LB

R

CE

R

OE

R

I/O

8R

-I/O

15R

I/O

0R

-I/O

7R

A

12R

A

0R

R/W

R

SEM

R

INT

R

CE

R

OE

R

(2)

(1,2) (1,2)

(2)

13 13

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

2

2683 drw 02

14

15

16

17

18

19

20

INDEX

21

22

23

24

11109876543218483

33 34 35 36 37 38 39 40 41 42 43 44 45

V

CC

GND

I/O

8L

A

7L

13

12

25

26

27

28

29

30

31

32 46 47 48 49 50 51 52 53

72

71

70

69

68

67

66

65

64

63

62

73

74

61

60

59

58

57

56

55

54

82 81 80 79 78 77 76 75

GND

BUSY

L

GND

IDT7025J or F

J84-1

(4)

F84-2

(4)

84-Pin PLCC/Flatpack

Top View

(5)

INT

L

M/S

INT

R

I/O

9L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

I/O

15L

I/O

0R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

6R

I/O

7R

I/O

8R

A

6L

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

BUSY

R

A

0R

A

2R

A

3R

A

4R

A

5R

A

6R

A

1R

I/O

7L

I/O

6L

I/O

5L

I/O

4L

I/O

3L

I/O

2L

V

CC

R/W

L

SEM

L

CE

L

UB

L

LB

L

A

11L

GND

I/O

1L

I/O

0L

A

10L

A

9L

A

8L

OE

L

I/O

9R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

GND

A

11R

A

10R

A

9R

A

8R

A

7R

OE

R

R/W

R

CE

R

UB

R

LB

R

A

12R

A

12L

SEM

R

11/06/01

Description

The IDT7025 is a high-speed 8K x 16 Dual-Port Static RAM. The

IDT7025 is designed to be used as a stand-alone 128K-bit Dual-Port RAM

or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit or more

word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach

in 32-bit or wider memory system applications results in full-speed, error-

free operation without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by Chip Enable (CE) permits the on-chip circuitry of each

port to enter a very low standby power mode.

Fabricated using IDT’s CMOS high-performance technology, these

devices typically operate on only 750mW of power. Low-power (L)

versions offer battery backup data retention capability with typical power

consumption of 500µW from a 2V battery.

The IDT7025 is packaged in a ceramic 84-pin PGA, an 84-pin

Flatpack, PLCC, and a 100-pin TQFP. Military grade product is manu-

factured in compliance with the latest revision of MIL-PRF-38535 QML,

making it ideally suited to military temperature applications demanding the

highest level of performance and reliability.

Pin Configurations(1,2,3)

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. J84-1 package body is approximately 1.15 in x 1.15 in x .17 in.

F84-2 package body is approximately 1.17 in x 1.17 in x .11 in.

PN100-1 package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

Index

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT7025PF

PN100-1

(4)

100-Pin TQFP

Top View

(5)

N/C

I/O

10L

I/O

11L

I/O

12L

I/O

13L

GND

I/O

14L

I/O

15L

V

CC

GND

I/O

0R

I/O

1R

I/O

2R

I/O

3R

V

CC

I/O

4R

I/O

5R

I/O

6R

N/C

2683 drw 03

N/C

A

5L

A

4L

A

3L

A

2L

A

1L

A

0L

INT

L

GND

M/S

BUSY

R

INT

R

A

0R

N/C

BUSY

L

A

1R

A

2R

A

3R

A

4R

I/O

9L

I/O

8L

I/O

7L

I/O

6L

I/O

5L

I/O

4L

I/O

3L

I/O

2L

GND

I/O

1L

I/O

0L

OE

L

V

CC

R/W

L

SEM

L

CE

L

UB

L

LB

L

A

11L

A

10L

A

9L

A

8L

A

7L

A

6L

I/O

7R

I/O

8R

I/O

9R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

GND

I/O

15R

OE

R

R/W

R

SEM

R

CE

R

UB

R

LB

R

GND

A

11R

A

10R

A

9R

A

8R

A

7R

A

6R

A

5R

A

12L

A

12R

.

11/06/01

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

3

Pin Configurations(1,2,3) (con't.)

NOTES:

1. All VCC pins must be connected to power supply.

2. All GND pins must be connected to ground supply.

3. Package body is approximately 1.12 in x 1.12 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part-marking.

2683 drw 04

I/O

7L

63 61 60 58 55 54 51 48 46 45

66

67

69

72

75

76

79

81

82

83

125

7

8

11

10

12

14 17 20

23

26

28 29

32 31

33 35

38

41

43

IDT7025G

G84-3

(4)

84-Pin PGA

Top View

(5)

ABCDEFGHJKL

42

59 56 49 50 40

25

27

30

36

34

37

39

84346915131618

22 24

19 21

68

71

70

77

80

UB

R

CE

R

GND

11

10

09

08

07

06

05

04

03

02

01

64

65

62

57 53 52

47 44

73

74

78

GND GND

R/W

R

OE

R

LB

R

GNDGND SEM

R

UB

L

CE

L

R/W

L

OE

L

GND

SEM

L

V

CC

LB

L

INT

R

BUSY

R

BUSY

L

M/S

INT

L

A

11L

I

ndex

I/O

5L

I/O

4L

I/O

2L

I/O

0L

I/O

10L

I/O

8L

I/O

6L

I/O

3L

I/O

1L

I/O

11L

I/O

9L

I/O

13L

I/O

12L

I/O

15L

I/O

14L

I/O

0R

A

9L

A

10L

A

8L

A

7L

A

5L

A

6L

A

4L

A

3L

A

2L

A

0L

A

1L

A

0R

A

2R

A

1R

A

5R

A

3R

A

6R

A

4R

A

9R

A

7R

A

8R

A

10R

A

11R

I/O

1R

I/O

2R

V

CC

I/O

3R

I/O

4R

I/O

5R

I/O

7R

I/O

6R

I/O

9R

I/O

8R

I/O

11R

I/O

10R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

V

CC

A

12R

A

12L

11/06/01

.

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

4

Pin Names

Left Port Right Port Names

CE

L

CE

R

Chip Enable

R/W

L

R/W

R

Re ad /W rite E nab le

OE

L

OE

R

Outp ut E nab le

A

0L

- A

12L

A

0R

- A

12R

Address

I/O

0L

- I/O

15L

I/O

0R

- I/O

15R

Data Inp ut/Output

SEM

L

SEM

R

Semaphore Enable

UB

L

UB

R

Upper Byte Select

LB

L

LB

R

Lower Byte Select

INT

L

INT

R

Inte rrupt Flag

BUSY

L

BUSY

R

Busy Flag

M/SMaster or Slave Select

V

CC

Power

GND Ground

2683 tbl 01

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

5

Truth T able I: Non-Contention Read/Write Control

NOTE:

1. A0L — A12L ≠ A0R — A12R.

Inputs

(1)

Outputs

Mode

CE R/WOE UB LB SEM I/O

8-15

I/O

0-7

H X X X X H High-Z High-Z Deselected

X X X H H H Hig h-Z High-Z Both By te s Dese le cted

LLXLHHDATA

IN

High-Z Write to Uppe r Byte Only

L L X H L H High-Z DATA

IN

Wr ite to Lo we r By te O nl y

LLXLLHDATA

IN

DATA

IN

Wr ite to B o th B y te s

LHLLHHDATA

OUT

High-Z Read Up p er Byte Only

LHLHLHHigh-ZDATA

OUT

Re ad Lo we r B yte Onl y

LHLLLHDATA

OUT

DATA

OUT

Read Both By tes

X X H X X X Hig h-Z High-Z Outputs Dis able d

2683 tbl 02

NOTES:

1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O15. These eight semaphores are addressed by A0 - A2.

Truth Table II: Semaphore Read/Write Control(1)

Inputs Outputs

Mode

CE R/WOE UB LB SEM I/O

8-15

I/O

0-7

HHLXXLDATA

OUT

DATA

OUT

Read Semaphore Flag Data Out

XHLHHLDATA

OUT

DATA

OUT

Read Semaphore Flag Data Out

H↑XXXLDATA

IN

DATA

IN

Write I/O

0

into Semaphore Flag

X↑XHHLDATA

IN

DATA

IN

Write I/O

0

into Semaphore Flag

LXXLXL

____ ____

Not Allo wed

LXXXLL

____ ____

Not Allo wed

2683 tbl 03

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

6

Recommended DC Operating

Conditions

Maximum Operating Temperature

and Supply Voltage(1)

Capacitance(1) (TA = +25°C, f = 1.0mhz)

Absolute Maximum Ratings(1)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20 mA for the period over VTERM > Vcc + 10%.

NOTES:

1. This is parameter TA. This is the "instant on" case temperature.

NOTES:

1. VIL > -1.5V for pulse width less than 10ns.

2. VTERM must not exceed Vcc + 10%.

NOTES:

1. This parameter is determined by device characterization but is not production

tested. For TQFP package only.

2 . 3dV references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

NOTE:

1. At Vcc < 2.0V input leakages are undefined.

Symbol Rating Commercial

& I ndustrial Military Unit

V

TERM

(2)

Te rminal Voltage

with Re s pe ct

to G N D

-0.5 to +7.0 -0.5 to +7.0 V

T

BIAS

Temperature

Under Bias -55 to +125 -65 to +135

o

C

T

STG

Storage

Temperature -65 to +150 -65 to +150

o

C

I

OUT

DC Outp ut

Current 50 50 mA

2683 t bl 04

Grade Am bient Temperature GND Vcc

Military -55

O

C to +125

O

C0V5.0V

+

10%

Commercial 0

O

C to +70

O

C0V5.0V

+

10%

Industrial -40

O

C to +85

O

C0V5.0V

+

10%

2683 tbl 05

Symbol Parameter Min. Typ. Max. Unit

V

CC

Sup p ly Voltag e 4.5 5.0 5. 5 V

GND Ground 0 0 0 V

V

IH

Input High Voltage 2.2

____

6.0

(2)

V

IL

Inp ut Low Vo ltage -0.5

(1)

____

0.8 V

2683 tbl 06

Symbol Parameter Conditions

(2)

Max. Unit

C

IN

Input Capacitance V

IN

= 3dV 9 pF

C

OUT

Outp ut Cap acitance V

OUT

= 3dV 10 pF

2683 tbl 07

Symbol Parameter Test Condi ti ons

7025S 7025L

UnitMin. Max. Min. Max.

|I

LI

| Inp ut Le akag e Curre nt

(1)

V

CC

= 5.5V, V

IN

= 0V to V

CC

___

10

___

5µA

|I

LO

| Outp ut Le ak age Curre nt V

OUT

= 0V to V

CC

___

10

___

5µA

V

OL

Output Low Vo ltage I

OL

= +4mA

___

0.4

___

0.4 V

V

OH

Output High Voltage I

OH

= -4mA 2.4

___

2.4

___

V

2683 tbl 08

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

7

NOTES:

1. 'X' in part number indicates power rating (S or L)

2. VCC = 5V, TA = +25°C, and are not production tested. Icc dc = 120mA (TYP)

3. At f = fMAX, address and I/O'S are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

DC Electrical Characteristics Over the 0perating

Temperature and Supply Voltage Range(1) (VCC = 5.0V ± 10%)

7025X15

Com'l Only 7025X17

Co m 'l O nly 7025X20

Com'l, Ind

& M i l i tary

7025X25

Com 'l &

Military

S ymbol Par ameter Test Conditi on Versi on T yp.(2) Max. Typ.(2) Max. Typ.(2 ) Max. Typ.(2) Max. Uni

t

I

CC

Dy namic Op erating

Current

(Both Ports Active)

CE = V

IL

, Outputs Disab led

SEM = V

IH

f = f

MAX

(3)

COM'L S

L170

170 310

260 170

170 310

260 160

160 290

240 155

155 265

220 mA

MIL &

IND S

L

____

160

160 370

320 155

155 340

280

I

SB1

Standby Current

(B o th P o rts - TTL

L e v e l In p u ts )

CE

L

= CE

R

= V

IH

SEM

R

= SEM

L

= V

IH

f = f

MAX

(3)

COM'L S

L20

20 60

50 20

20 60

50 20

20 60

50 16

16 60

50 mA

MIL &

IND S

L

____

20

20 90

70 16

16 80

65

I

SB2

Standby Current

(One P o rt - TTL

L e v e l In p u ts )

CE

"A"

= V

IL

and CE

"B"

= V

IH

(5)

Active Port Outputs Disabled,

f=f

MAX

(3)

SEM

R

= SEM

L

= V

IH

COM'L S

L105

105 190

160 105

105 190

160 95

95 180

150 90

90 170

140 mA

MIL &

IND S

L

____

95

95 240

210 90

90 215

180

I

SB3

Full Standb y Current

(B o th P o rts -

CMOS Le ve l Inp uts )

CE

L

and CE

R

> V

CC

- 0.2V,

V

IN

> V

CC

- 0 . 2V or

V

IN

< 0.2V, f = 0 (4)

SEM

R

= SEM

L

> V

CC

- 0. 2 V

COM'L S

L1.0

0.2 15

51.0

0.2 15

51.0

0.2 15

51.0

0.2 15

5mA

MIL &

IND S

L

____

1.0

0.2 30

10 1.0

0.2 30

10

I

SB4

Full Standb y Current

(One P o rt -

CMOS Le ve l Inp uts )

CE

"A"

< 0.2V and

CE

"B"

> V

CC

- 0.2V(5)

SEM

R

= SEM

L

> V

CC

- 0. 2 V

V

IN

> V

CC

- 0. 2V o r V

IN

< 0.2V

Active Port Outputs Disabled,

f = f

MAX

(3)

COM'L S

L100

100 170

140 100

100 170

140 90

90 155

130 85

85 145

120 mA

MIL &

IND S

L

____

90

90 225

200 85

85 200

170

2 683 tb l 09 a

7025X35

Com 'l &

Military

7025X55

Com 'l, I nd

& Mil itary

7025X70

Mi li tary Onl y

Symbol Parameter Test Condition Version Typ.

(2)

Max. Typ.

(2)

Max. Typ.

(2)

Max. Unit

I

CC

Dynamic Op erating

Current

(Bo th Po rts Active )

CE = V

IL

, Outp uts Disabled

SEM = V

IH

f = f

MAX

(3)

COM'L S

L150

150 250

210 150

150 250

210

____

mA

MIL &

IND S

L150

150 300

250 150

150 300

250 140

140 300

250

I

SB1

S tand b y Curre nt

(Bo th Po rts - TTL

Le ve l Inp uts )

CE

L

= CE

R

= V

IH

SEM

R

= SEM

L

= V

IH

f = f

MAX

(3)

COM'L S

L13

13 60

50 13

13 60

50

____

mA

MIL &

IND S

L13

13 80

65 13

13 80

65 10

10 80

65

I

SB2

S tand b y Curre nt

(One Port - TTL

Le ve l Inp uts )

CE

"A"

= V

IL

and CE

"B"

= V

IH

(5)

Active Port Outputs Disabled,

f=f

MAX

(3)

SEM

R

= SEM

L

= V

IH

COM'L S

L85

85 155

130 85

85 155

130

____

mA

MIL &

IND S

L85

85 190

160 85

85 190

160 80

80 190

160

I

SB3

Full Standby Current

(Both Ports -

CMOS Lev e l Inp uts)

CE

L

and CE

R

> V

CC

- 0. 2V,

V

IN

> V

CC

- 0. 2V o r

V

IN

< 0.2V, f = 0

(4)

SEM

R

= SEM

L

> V

CC

- 0. 2V

COM'L S

L1.0

0.2 15

51.0

0.2 15

5

____

mA

MIL &

IND S

L1.0

0.2 30

10 1.0

0.2 30

10 1.0

0.2 30

10

I

SB4

Full Standby Current

(One Port -

CMOS Lev e l Inp uts)

CE

"A"

< 0.2V and

CE

"B"

> V

CC

- 0. 2V

(5)

SEM

R

= SEM

L

> V

CC

- 0. 2V

V

IN

> V

CC

- 0. 2V o r V

IN

< 0.2V

Active Port Outputs Disabled,

f = f

MAX

(3)

COM'L S

L80

80 135

110 80

80 135

110

____

mA

MIL &

IND S

L80

80 175

150 80

80 175

150 75

75 175

150

2683 tbl 09b

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

8

Data Retention Waveform

Data Retention Characteristics Over All Temperature Ranges

(L Version Only)

NOTES:

1. TA = +25°C, VCC = 2V, and are not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed by device characterization, but is not production tested.

4. At Vcc < 2.0V input leakages are undefined.

AC Test Conditions

Figure 1. AC Output Test Load Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* including scope and jig.

Symbol Parameter Test Condition Min. Typ.

(1)

Max. Unit

V

DR

V

CC

fo r Data Re tentio n V

CC

= 2V 2.0

___ ___

V

I

CCDR

Data Rete ntio n Curre nt CE > V

HC

V

IN

> V

HC

or < V

LC

MIL. & IND.

___

100 4000 µA

COM'L.

___

100 1500

t

CDR

(3)

Chip De sele ct to Data Rete ntio n Time SEM > V

HC

0

___ ___

ns

t

R

(3)

Operation Recovery Time t

RC

(2)

___ ___

ns

2683 tbl 10

DATA RETENTION MODE

V

CC

CE

2683 drw 05

4.5V

t

CDR

t

R

V

IH

V

DR

V

IH

4.5V

V

DR

2V

≥

Input Pulse Levels

Inp ut Ris e /Fall Time s

Inp ut Timi ng Refe renc e L ev e ls

Outp ut Re fe re nc e Le ve ls

Outp ut Lo ad

GND to 3. 0V

5ns Max.

1.5V

Fi gures 1 and 2

2683 tbl 11

2683 drw 06

893Ω

30pF

347Ω

5V

DATA

OUT

BUSY

INT

893Ω

5pF*

347Ω

5V

DATA

OUT

.

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

9

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(4)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterazation, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access semephore, CE = VIH or UB & LB = VIH, and SEM = VIL.

4. 'X' in part number indicates power rating (S or L).

7025X15

Com 'l Onl y 7025X17

Com'l Only 7025X20

Com'l, Ind

& Mi li tary

7025X25

Com 'l &

Military

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.

READ CYCLE

tRC Re ad Cyc le Time 15

____

17

____

20

____

25

____

ns

tAA Address Access Time

____

15

____

17

____

20

____

25 ns

tACE Chip Enable Access Time

(3)

____

15

____

17

____

20

____

25 ns

tABE Byte Enable Access Time

(3)

____

15

____

17

____

20

____

25 ns

tAOE Output Enable Acc ess Time

(3)

____

10

____

10

____

12

____

13 ns

tOH O utp ut Hol d from Add res s Cha ng e 3

____

3

____

3

____

3

____

ns

tLZ O utput Lo w -Z Tim e

(1,2)

3

____

3

____

3

____

3

____

ns

tHZ Output High-Z Time

(1,2)

____

10

____

10

____

12

____

15 ns

tPU Ch ip E nab l e to P owe r Up Tim e

(1,2)

0

____

0

____

0

____

0

____

ns

tPD Ch ip Di s a bl e to P o w e r Do w n Tim e

(1,2)

____

15

____

17

____

20

____

25 ns

tSOP Semaphore Flag Update Pulse (OE or SEM)10

____

10

____

10

____

10

____

ns

tSAA Semaphore Ad dress Access

(3)

____

15

____

17

____

20

____

25 ns

2 6 83 tbl 12 a

7025X35

Com 'l &

Military

7025X55

Com'l, Ind

& Military

7025X70

Military Only

UnitSymbol Parameter Min.Max.Min.Max.Min.Max.

READ CYCLE

t

RC

Re ad Cyc le Time 35

____

55

____

70

____

ns

t

AA

Addre ss Access Time

____

35

____

55

____

70 ns

t

ACE

Chip Enable Access Time

(3)

____

35

____

55

____

70 ns

t

ABE

Byte Enable Access Time

(3)

____

35

____

55

____

70 ns

t

AOE

Output Enable Acc ess Time

(3)

____

20

____

30

____

35 ns

t

OH

Ou tp u t Ho ld fro m A d d res s Cha ng e 3

____

3

____

3

____

ns

t

LZ

Ou tp u t Low-Z Ti me

(1,2)

3

____

3

____

3

____

ns

t

HZ

Output Hig h-Z Time

(1,2)

____

15

____

25

____

30 ns

t

PU

Ch ip E n ab l e to P owe r Up Tim e

(1,2)

0

____

0

____

0

____

ns

t

PD

Ch ip Di s able to P o w e r Do w n Tim e

(1,2)

____

35

____

50

____

50 ns

t

SOP

Semaphore Flag Update Pulse (OE or SEM)15

____

15

____

15

____

ns

t

SAA

Semaphore Ad dress Access

(3)

____

35

____

55

____

70 ns

2683 t b l 12b

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

10

NOTES:

1. Timing depends on which signal is asserted last, OE, CE, LB, or UB.

2. Timing depends on which signal is de-asserted first, CE, OE, LB, or UB.

3. tBDD delay is required only in case where opposite port is completing a write operation to the same address location for simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tABE, tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Waveform of Read Cycles(5)

Timing of Power-Up Power-Down

t

RC

R/W

CE

ADDR

t

AA

OE

UB,LB

2683 drw 07

(4)

t

ACE

(4)

t

AOE

(4)

t

ABE

(4)

(1)

t

LZ

t

OH

(2)

t

HZ

(3,4)

t

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

CE

2683 drw 08

t

PU

I

CC

I

SB

t

PD

50% 50%

.

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

11

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. Either condition must be valid for the

entire tEW time.

4 . The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. 'X' in part number indicates power rating (S or L).

Symbol Parameter

7025X15

Com'l Only 7025X17

Com ' l On l y 7025X20

Com'l, Ind

& Military

7025X25

Com'l &

Military

UnitMin. Max. Min. Max. Min. Max. Min. Max.

WRI TE CYCLE

t

WC

Write Cycle Time 15

____

17

____

20

____

25

____

ns

t

EW

Chip Enable to End-of-Write

(3)

12

____

12

____

15

____

20

____

ns

t

AW

Address Valid to End-of-Write 12

____

12

____

15

____

20

____

ns

t

AS

Add re ss Set-up Time

(3)

0

____

0

____

0

____

0

____

ns

t

WP

Write Pulse Wid th 12

____

12

____

15

____

20

____

ns

t

WR

Write Recovery Time 0

____

0

____

0

____

0

____

ns

t

DW

Data Val id to E nd - o f-Wri te 10

____

10

____

15

____

15

____

ns

t

HZ

Outpu t Hig h -Z Tim e

(1,2)

____

10

____

10

____

12

____

15 ns

t

DH

Data Ho l d Ti m e

(4)

0

____

0

____

0

____

0

____

ns

t

WZ

Write Enable to Output in High-Z

(1,2)

____

10

____

10

____

12

____

15 ns

t

OW

Outp u t Ac ti v e from E nd -o f-Wr ite

(1,2,4)

0

____

0

____

0

____

0

____

ns

t

SWRD

SEM Flag Write to Read Time 5

____

5

____

5

____

5

____

ns

t

SPS

SEM Flag Contention Wind ow 5

____

5

____

5

____

5

____

ns

2683 tbl 13a

Symbol Parameter

7025X35

Com ' l &

Military

7025X55

Com'l, Ind

& Militar y

7025X70

Military Only

UnitMin. Max. Min. Max. Min. Max.

WRI T E CYC L E

t

WC

Wri te Cy c le Ti me 35

____

55

____

70

____

ns

t

EW

Chip Enable to End-of-Write

(3)

30

____

45

____

50

____

ns

t

AW

Address Valid to End-of-Write 30

____

45

____

50

____

ns

t

AS

Address Set-up Time

(3)

0

____

0

____

0

____

ns

t

WP

Wri te P uls e Wid th 25

____

40

____

50

____

ns

t

WR

Wri te Rec ove ry Ti me 0

____

0

____

0

____

ns

t

DW

Data Valid to End-of-Write 15

____

30

____

40

____

ns

t

HZ

Output Hig h-Z Time

(1,2)

____

15

____

25

____

30 ns

t

DH

Data Ho ld Time

(4)

0

____

0

____

0

____

ns

t

WZ

Wr ite E nab le to Outp ut in Hi gh-Z

(1,2)

____

15

____

25

____

30 ns

t

OW

Outp ut Acti ve fro m End-o f-Write

(1,2,4)

0

____

0

____

0

____

ns

t

SWRD

SEM Flag Write to Read Time 5

____

5

____

5

____

ns

t

SPS

SEM Flag Contention Window 5

____

5

____

5

____

ns

2683 t b l 1 3b

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

12

Timing Wa v eform of Write Cyc le No. 1, R/W Controlled Timing(1,5,8)

Timing Wa v eform of Write Cyc le No. 2, CE, UB, LB Controlled Timing(1,5)

NOTES:

1. R/W or CE or UB & LB = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a UB or LB = VIL and a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going to VIH to the end-of-write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the HIGH impedance state.

6. Timing depends on which enable signal is asserted last, CE, R/W, or byte control.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with Output Test Load

(Figure 2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIH, and SEM = VIL. tEW must be met

for either condition.

R/W

t

WC

t

HZ

t

AW

t

WR

t

AS

t

WP

DATA

OUT

(2)

t

WZ

t

DW

t

DH

t

OW

OE

ADDRESS

DATA

IN

(6)

(4) (4)

(7)

UB or LB

2683 drw 09

(9)

CE or SEM

(9)

(7)

(3)

2683 drw 10

t

WC

t

AS

t

WR

t

DW

t

DH

ADDRESS

DATA

IN

R/W

t

AW

t

EW

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

13

SEM

2683 drw 11

t

AW

t

EW

t

SOP

DATA

0

VALID ADDRESS

t

SAA

R/W

t

WR

t

OH

t

ACE

VALID ADDRESS

DATA

IN

VALID DATA

OUT

t

DW

t

WP

t

DH

t

AS

t

SWRD

t

AOE

t

SOP

Read Cycle

Write Cycle

A

0

-A

2

OE

VALID

(2)

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

NOTE:

1. CE = VIH or UB & LB = VIH for the duration of the above timing (both write and read cycle).

2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.

NOTES:

1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH.

2. All timing is the same for left and right port. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.

Timing Waveform of Semaphore Write Contention(1,3,4)

SEM

"A"

2683 drw 12

t

SPS

MATCH

R/W

"A"

MATCH

A

0"A"

-A

2"A"

SIDE "A"

(2)

SEM

"B"

R/W

"B"

A

0"B"

-A

2"B"

SIDE

(2)

"B"

.

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

14

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of 0ns, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on Port "B" during contention with Port "A".

5. To ensure that a write cycle is completed on Port "B" after contention with Port "A".

6. 'X' in part number indicates power rating (S or L).

AC Electrical Characteristics Over the

Operating Temperature Supply Voltage Range(6)

7025X15

Com'l Ony 7025X17

Com 'l Onl y 7025X20

Com'l, Ind

& M i l i tar y

7025X25

Co m 'l &

Military

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

BUSY TIMING (M/ S = V

IH

)

t

BAA

BUSY Access Time from Add ress Match

____

15

____

17

____

20

____

20 ns

t

BDA

BUSY Disable Time from Address Not Matched

____

15

____

17

____

20

____

20 ns

t

BAC

BUSY Access Time from Chip Enable LOW

____

15

____

17

____

20

____

20 ns

t

BDC

BUSY Di sab le Time fro m Chi p Enab le HIGH

____

15

____

17

____

17

____

17 ns

t

APS

Arbitration Prio rity Set-up Time

(2)

5

____

5

____

5

____

5

____

ns

t

BDD

BUSY Disable to Valid Data

(3)

____

18

____

18

____

30

____

30 ns

t

WH

Write Ho ld A fte r BUSY

(5)

12

____

13

____

15

____

17

____

ns

BUSY TIMING (M/ S = V

IL

)

t

WB

BUSY Inp ut to Write

(4)

0

____

0

____

0

____

0

____

ns

t

WH

Write Ho ld A fte r BUSY

(5)

12

____

13

____

15

____

17

____

ns

PORT -TO-PORT DE LAY TI MING

t

WDD

Wri te P ulse to Data Del ay

(1)

____

30

____

30

____

45

____

50 ns

t

DDD

W ri t e Da ta Va l i d to R ea d D a ta D e l a y

(1)

____

25

____

25

____

35

____

35 ns

2683 tb l 14a

7025X35

Com'l &

Military

7025X55

Com'l, Ind

& Military

7025X70

Mil i tary Only

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

BUSY TIMING (M/S = V

IH

)

t

BAA

BUSY Acce ss Time from Add re ss Matc h

____

20

____

45

____

45 ns

t

BDA

BUSY Disable Time from Addre ss No t Matc he d

____

20

____

40

____

40 ns

t

BAC

BUSY Acce ss Time from Chip Enab le LOW

____

20

____

40

____

40 ns

t

BDC

BUSY Disable Time from Chip Enab le HIGH

____

20

____

35

____

35 ns

t

APS

Arbitration Priority Se t-up Time

(2)

5

____

5

____

5

____

ns

t

BDD

BUSY Disable to Valid Data

(3)

____

35

____

40

____

45 ns

t

WH

Write Hold After BUSY

(5)

25

____

25

____

25

____

ns

BUSY TIMING (M/S = V

IL

)

t

WB

BUSY Inp ut to Wri te

(4)

0

____

0

____

0

____

ns

t

WH

Write Hold After BUSY

(5)

25

____

25

____

25

____

ns

PORT-TO-PORT DELAY TIMING

t

WDD

Write Pulse to Data Delay

(1)

____

60

____

80

____

95 ns

t

DDD

Write Data Valid to Re ad Data Delay

(1)

____

45

____

65

____

80 ns

2683 t b l 1 4b

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

15

Timing Wa vef orm of Write P ort-to-P ort R ead and BUSY(2,4,5) (M/S = VIH)

Timing Wa vef orm of Write with BUSY

NOTES:

1. tWH must be met for both BUSY input (slave) output master.

2. BUSY is asserted on port "B" Blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'Slave' Version.

2683 drw 1

3

t

DW

t

APS

ADDR

"A"

t

WC

DATA

OUT "B"

MATCH

t

WP

R/W

"A"

DATA

IN "A"

ADDR

"B"

t

DH

VALID

(1)

MATCH

BUSY

"B"

t

BDA

VALID

t

BDD

t

DDD

(3)

t

WDD

t

BAA

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (slave).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (SLAVE), then BUSY is an input. Therefore in this example BUSY"A" = VIH and BUSY"B" input is shown.

5 . All timing is the same for left and right ports. Port "A" may be either the left of right port. Port "B" is the opposite port from Port "A".

2683 drw 14

R/W

"A"

BUSY

"B"

t

WP

t

WB

R/W

"B"

t

WH

(1)

(2)

(3)

.

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

16

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(1)

Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)

NOTES:

1. 'X' in part number indicates power rating (S or L).

Waveform of BUSY Arbitration Cyc le Controlled by Address Match

Timing(1) (M/S = VIH)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

2683 drw 15

ADDR

"A"

and

"B"

ADDRESSES MATCH

CE

"A"

CE

"B"

BUSY

"B"

t

APS

t

BAC

t

BDC

(2)

2683 drw 16

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

t

APS

t

BAA

t

BDA

(2)

MATCHING ADDRESS "N"

7025X15

Com 'l Onl y 7025X17

Com 'l Onl y 7025X20

Com'l, Ind

& M i l i tar y

7025X25

Co m 'l &

Military

Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

t

AS

Address Set-up Time 0

____

0

____

0

____

0

____

ns

t

WR

Wri te Re c o v e ry Ti me 0

____

0

____

0

____

0

____

ns

t

INS

Inte rrup t Se t Ti me

____

15

____

15

____

20

____

20 ns

t

INR

Inte rrup t Res e t Time

____

15

____

15

____

20

____

20 ns

2683 tb l 15a

7025X35

Com ' l &

Military

7025X55

Com'l, Ind

& M i l i tar y

7025X70

Military Only

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

t

AS

Address Set-up Time 0

____

0

____

0

____

ns

t

WR

Wri te Re c o v e ry Ti me 0

____

0

____

0

____

ns

t

INS

Inte rrup t Se t Ti me

____

25

____

40

____

50 ns

t

INR

Inte rrup t Res e t Time

____

25

____

40

____

50 ns

2683 t b l 15b

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

17

Wa v eform of Interrupt Timing(1)

Truth Tables

T ruth T able I — Interrupt Flag(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt Flag Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTES:

1. Assumes BUSYL = BUSYR = VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTR and INTL must be initialized at power-up.

2683 drw 17

ADDR

"A"

INTERRUPT SET ADDRESS

CE

"A"

R/W

"A"

t

AS

t

WC

t

WR

(3) (4)

t

INS

(3)

INT

"B"

(2)

2683 drw 18

ADDR

"B"

INTERRUPT CLEAR ADDRESS

CE

"B"

OE

"B"

t

AS

t

RC

(3)

t

INR

(3)

INT

"B"

(2)

Left P ort Ri ght P ort

FunctionR/W

L

CE

L

OE

L

A

0L

-A

12L

INT

L

R/W

R

CE

R

OE

R

A

0R

-A

12R

INT

R

LLX1FFFXXXX X L

(2) S e t R ig h t INT

R

Flag

X X X X X X L L 1FFF H(3) Re s e t Rig ht INT

R

Flag

XXX X L

(3) L L X 1 FF E X S e t Left INT

L

Flag

XLL1FFE H

(2) XXXXXReset Left INT

L

Fl ag

2689 tb l 16

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

18

Functional Description

The IDT7025 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location

in memory. The IDT7025 has an automatic power down feature controlled

by CE. The CE controls on-chip power down circuitry that permits the

respective port to go into a standby mode when not selected (CE = VIH).

When a port is enabled, access to the entire memory array is permitted.

II

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 1FFE

(HEX), where a write is defined as the CER = R/WR = VIL per Truth Table

I. The left port clears the interrupt by an address location 1FFE access

when CEL = OEL = VIL, R/ WL is a "don't care". Likewise, the right port

interrupt flag (INTR) is asserted when the left port writes to memory location

1FFF (HEX) and to clear the interrupt flag (INTR), the right port must access

the memory location 1FFF, The message (16 bits) at 1FFE or 1FFF is

user-defined, since it is an addressable SRAM location. If the interrupt

function is not used, address locations 1FFE and 1FFF are not used as

mail boxes, but as part of the random access memory. Refer to Truth Table

I for the interrupt operation.

Truth Table III — Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7025.

2. There are eight semaphore flags written to via I/O0 and read from all I/0's. These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL, to access the semaphores. Refer to the Semaphore Read/Write Truth Table.

T ruth T able II — Address BUSY

Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. BUSY are inputs when configured as a slave. BUSYx outputs on the IDT7025

are push pull, not open drain outputs. On slaves the BUSY asserted internally inhibits write.

2 . "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

Inputs Outputs

Function

CE

L

CE

R

A

0L

-A

12L

A

0R

-A

12R

BUSY

L

(1)

BUSY

R

(1)

XXNO MATCH H H Normal

HX MATCH H H Normal

XH MATCH H H Normal

L L MATCH (2) (2) Write Inhib it

(3)

2683 tbl 17

Functions D

0

- D

15

Left D

0

- D

15

Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Rig ht P ort Write s "0" to S emap hore 0 1 No chang e. Right sid e has no write acc ess to se map hore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Po rt Writes "0" to Se map ho re 1 0 No chang e . Le ft p ort has no write ac ce ss to se map hore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

2683 tbl 18

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

19

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7025 RAMs.

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in slave

mode with the M/S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT 7025 RAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT7025 RAM array in width while using BUSY

logic, one master part is used to decide which side of the RAM array will

receive a BUSY indication, and to output that indication. Any number of

slaves to be addressed in the same address range as the master, use

the BUSY signal as a write inhibit signal. Thus on the IDT7025 RAM the

BUSY pin is an output if the part is used as a master (M/S pin = VIH), and

the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown

in Figure 3.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating BUSY on one side of the

array and another master indicating BUSY on one other side of the array.

This would inhibit the write operations from one port for part of a word and

inhibit the write operations from the other port for the other part of the word.

The BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enough for a BUSY flag to be output from the master before the actual write

pulse can be initiated with either the R/W signal or the byte enables. Failure

to observe this timing can result in a glitched internal write inhibit signal and

corrupted data in the slave.

Semaphores

The IDT7025 is an extremely fast Dual-Port 8K x 16 CMOS Static RAM

with an additional 8 address locations dedicated to binary semaphore flags.

These flags allow either processor on the left or right side of the Dual-Port

RAM to claim a privilege over the other processor for functions defined by

the system designer’s software. As an example, the semaphore can be

used by one processor to inhibit the other from accessing a portion of the

Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be read from,

or written to, at the same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphore location. Semaphores are protected against such ambiguous

situations and may be used by the system program to avoid any conflicts

in the non-semaphore portion of the Dual-Port RAM. These devices have

an automatic power-down feature controlled by CE, the Dual-Port RAM

enable, and SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into

standby mode when not selected. This is the condition which is shown in

Truth Table I where CE and SEM are both = VIH.

Systems which can best use the IDT7025 contain multiple processors

or controllers and are typically very high-speed systems which are

software controlled or software intensive. These systems can benefit from

a performance increase offered by the IDT7025's hardware sema-

phores, which provide a lockout mechanism without requiring complex

programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in varying

configurations. The IDT7025 does not use its semaphore flags to control

any resources through hardware, thus allowing the system designer total

flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred in

either processor. This can prove to be a major advantage in very high-

speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent

of the Dual-Port RAM. These latches can be used to pass a flag, or token,

from one port to the other to indicate that a shared resource is in use. The

semaphores provide a hardware assist for a use assignment method

called “Token Passing Allocation.” In this method, the state of a semaphore

latch is used as a token indicating that shared resource is in use. If the left

processor wants to use this resource, it requests the token by setting the

latch. This processor then verifies its success in setting the latch by reading

it. If it was successful, it proceeds to assume control over the shared

resource. If it was not successful in setting the latch, it determines that the

right side processor has set the latch first, has the token and is using the

shared resource. The left processor can then either repeatedly request

2683 drw 19

MASTER

Dual Port

RAM

BUSY

L

BUSY

R

CE

MASTER

Dual Port

RAM

BUSY

L

BUSY

R

CE

SLAVE

Dual Port

RAM

BUSY

L

BUSY

R

CE

SLAVE

Dual Port

RAM

BUSY

L

BUSY

R

CE

BUSY

L

BUSY

R

DECODER

.

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

20

that semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of the

token via the set and test sequence. Once the right side has relinquished

the token, the left side should succeed in gaining control.

The semaphore flags are active LOW. A token is requested by writing

a zero into a semaphore latch and is released when the same side writes

a one to that latch.

The eight semaphore flags reside within the IDT7025 in a separate

memory space from the Dual-Port RAM. This address space is accessed

by placing a LOW input on the SEM pin (which acts as a chip select for

the semaphore flags) and using the other control pins (Address, OE, and

R/W) as they would be used in accessing a standard Static RAM. Each

of the flags has a unique address which can be accessed by either side

through address pins A0 – A2. When accessing the semaphores, none of

the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a LOW level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Truth Table III). That

semaphore can now only be modified by the side showing the zero. When

a one is written into the same location from the same side, the flag will be

set to a one for both sides (unless a semaphore request from the other side

is pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits

so that a flag that is a one reads as a one in all data bits and a flag con-

taining a zero reads as all zeros. The read value is latched into one side’s

output register when that side's semaphore select (SEM) and output

enable (OE) signals go active. This serves to disallow the semaphore from

changing state in the middle of a read cycle due to a write cycle from the

other side. Because of this latch, a repeated read of a semaphore in a test

loop must cause either signal (SEM or OE) to go inactive or the output will

never change.

A sequence WRITE/READ must be used by the semaphore in order

to guarantee that no system level contention will occur. A processor

requests access to shared resources by attempting to write a zero into a

semaphore location. If the semaphore is already in use, the semaphore

request latch will contain a zero, yet the semaphore flag will appear as one,

a fact which the processor will verify by the subsequent read (see Truth

Table III). As an example, assume a processor writes a zero to the left port

at a free semaphore location. On a subsequent read, the processor will

verify that it has written successfully to that location and will assume control

over the resource in question. Meanwhile, if a processor on the right side

attempts to write a zero to the same semaphore flag it will fail, as will be

verified by the fact that a one will be read from that semaphore on the right

side during subsequent read. Had a sequence of READ/WRITE been

used instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed

by either repeated reads or by writing a one into the same location. The

reason for this is easily understood by looking at the simple logic diagram

of the semaphore flag in Figure 4. Two semaphore request latches feed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphore flag will force its side of the semaphore flag LOW and the other

side HIGH. This condition will continue until a one is written to the same

semaphore request latch. Should the other side’s semaphore request latch

have been written to a zero in the meantime, the semaphore flag will flip

over to the other side as soon as a one is written into the first side’s request

latch. The second side’s flag will now stay LOW until its semaphore request

latch is written to a one. From this it is easy to understand that, if a semaphore

is requested and the processor which requested it no longer needs the

resource, the entire system can hang up until a one is written into that

semaphore request latch.

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If

simultaneous requests are made, the logic guarantees that only one side

receives the token. If one side is earlier than the other in making the

request, the first side to make the request will receive the token. If both

requests arrive at the same time, the assignment will be arbitrarily made

to one port or the other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is secure.

As with any powerful programming technique, if semaphores are misused

or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled

via the initialization program at power-up. Since any semaphore request

flag which contains a zero must be reset to a one, all semaphores on both

sides should have a one written into them at initialization from both sides

to assure that they will be free when needed.

Using Semaphores—Some Examples

Perhaps the simplest application of semaphores is their application as

resource markers for the IDT7025’s Dual-Port RAM. Say the 8K x 16 RAM

was to be divided into two 4K x 16 blocks which were to be dedicated at

any one time to servicing either the left or right port. Semaphore 0 could

be used to indicate the side which would control the lower section of

memory, and Semaphore 1 could be defined as the indicator for the upper

section of memory.

To take a resource, in this example the lower 4K of Dual-Port RAM,

the processor on the left port could write and then read a zero in to

Semaphore 0. If this task were successfully completed (a zero was read

back rather than a one), the left processor would assume control

of the lower 4K. Meanwhile the right processor was attempting to gain

control of the resource after the left processor, it would read back a one

in response to the zero it had attempted to write into Semaphore 0. At this

point, the software could choose to try and gain control of the second 4K

section by writing, then reading a zero into Semaphore 1. If it succeeded

in gaining control, it would lock out the left side.

Once the left side was finished with its task, it would write a one to

Semaphore 0 and may then try to gain access to Semaphore 1. If

Semaphore 1 was still occupied by the right side, the left side could undo

its semaphore request and perform other tasks until it was able to write, then

read a zero into Semaphore 1. If the right processor performs a similar task

with Semaphore 0, this protocol would allow the two processors to swap

4K blocks of Dual-Port RAM with each other.

The blocks do not have to be any particular size and can even be

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

21

D

2683 drw 20

0DQ

WRITE D

0

D

Q

WRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT RPORT

SEMAPHORE

READ SEMAPHORE

READ

.

variable, depending upon the complexity of the software using the

semaphore flags. All eight semaphores could be used to divide the Dual-

Port RAM or other shared resources into eight parts. Semaphores can

even be assigned different meanings on different sides rather than being

given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

interfaces where the CPU must be locked out of a section of memory during

a transfer and the I/O device cannot tolerate any wait states. With the use

of semaphores, once the two devices has determined which memory area

was “off-limits” to the CPU, both the CPU and the I/O devices could access

their assigned portions of memory continuously without any wait states.

Semaphores are also useful in applications where no memory “WAIT”

state is available on one or both sides. Once a semaphore handshake has

Figure 4. IDT7025 Semaphore Logic

been performed, both processors can access their assigned RAM

segments at full speed.

Another application is in the area of complex data structures. In this

case, block arbitration is very important. For this application one processor

may be responsible for building and updating a data structure. The other

processor then reads and interprets that data structure. If the interpreting

processor reads an incomplete data structure, a major error condition may

exist. Therefore, some sort of arbitration must be used between the two

different processors. The building processor arbitrates for the block, locks

it and then is able to go in and update the data structure. When the update

is completed, the data structure block is released. This allows the

interpreting processor to come back and read the complete data structure,

thereby guaranteeing a consistent data structure.

6.42

IDT7025S/L

High-Speed 8K x 16 Dual-Port Static RAM Military, Industrial and Commercial Temperature Ranges

22

Ordering Information

NOTE:

1. Industrial range is available on selected PLCC packages in standard power.

For other speeds, packages and powers contact your sales office.

2683 drw 21

A

Power

999

Speed

A

Package

A

Process/

Temperature

Range

Blank

I

(1)

B

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Military (-55°C to +125°C)

Compliant to MIL-PRF-38535 QML

PF

G

J

F

100-pin TQFP (PN100-1)

84-pin PGA (G84-3)

84-pin PLCC (J84-1)

84-pin Flatpack (F84-2)

15

17

20

25

35

55

70

Commercial Only

Commercial, Industrial & Military

Commercial & Military

Commercial, Industrial & Military

Military Only

S

LStandard Power

Low Power

XXXXX

Device

Type

128K (8K x 16) Dual-Port RAM7025

Speed in nanoseconds

.

CORPORATE HEADQUARTERS for SALES: for Tech Support:

6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-284-2794

San Jose, CA 95138 fax: 408-284-2775 DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

1/13/99: Initiated datasheet document history

Converted to new format

Cosmetic and typographical corrections

Pages 2 and 3 Added additional notes to pin configurations

5/19/99: Page 11 Fixed typographical error

6/3/99: Changed drawing format

Page 1 Corrected DSC number

4/4/00: Replaced IDT logo

Page 7 Fixed typo in Data Retention chart

Changed ±500mV to 0mV in notes

5/22/00: Page 5 Increased storage temperature parameter

Clarified TA parameter

Page 6 DC Electrical parameters–changed wording from "open" to "disabled"

9/13/01: Page 2 & 3 Added date revision for pin configurations

Page 6 Added Industrial temp to the column heading for 20ns to DC Electrical Characteristics

Pages 8,10,13&15 Added Industrial temp to the column headings for 20ns to AC Electrical Characteristics

Pages 5,6,8,10,13&15 Removed Industrial temp footnote from all tables

Page 21 Added Industrial temp to 20ns in ordering information

10/21/08: Page 22 Removed "IDT" from orderable part number