v5.2 ProASICPLUS(R) (R) Flash Family FPGAs Features and Benefits High Performance Routing Hierarchy * * * * High Capacity Commercial and Industrial * * * I/O 75,000 to 1 Million System Gates 27 k to 198 kbits of Two-Port SRAM 66 to 712 User I/Os * * Military * * * * * * * 300, 000 to 1 million System Gates 72 k to 198 kbits of Two Port SRAM 158 to 712 User I/Os Reprogrammable Flash Technology * * * * * * 0.22 m 4 LM Flash-Based CMOS Process Live At Power-Up (LAPU) Level 0 Support Single-Chip Solution No Configuration Device Required Retains Programmed Design during Power-Down/Up Cycles Mil/Aero Devices Operate over Full Military Temperature Range Performance * * * 3.3 V, 32-Bit PCI, up to 50 MHz (33 MHz over military temperature) Two Integrated PLLs External System Performance up to 150 MHz Secure Programming * The Industry's Most Effective Security Key (FlashLock ) Schmitt-Trigger Option on Every Input 2.5 V/3.3 V Support with Individually-Selectable Voltage and Slew Rate Bidirectional Global I/Os Compliance with PCI Specification Revision 2.2 Boundary-Scan Test IEEE Std. 1149.1 (JTAG) Compliant Pin Compatible Packages across the ProASICPLUS Family Unique Clock Conditioning Circuitry * * * PLL with Flexible Phase, Multiply/Divide and Delay Capabilities Internal and/or External Dynamic PLL Configuration Two LVPECL Differential Pairs for Clock or Data Inputs Standard FPGA and ASIC Design Flow * * Flexibility with Choice of Industry-Standard Front-End Tools Efficient Design through Front-End Timing and Gate Optimization ISP Support * In-System Programming (ISP) via JTAG Port SRAMs and FIFOs * (R) Low Power * * * Ultra-Fast Local and Long-Line Network High-Speed Very Long-Line Network High-Performance, Low Skew, Splittable Global Network 100% Routability and Utilization * ACTgen Netlist Generation Ensures Optimal Usage of Embedded Memory Blocks 24 SRAM and FIFO Configurations with Synchronous and Asynchronous Operation up to 150 MHz (typical) Low Impedance Flash Switches Segmented Hierarchical Routing Structure Small, Efficient, Configurable (Combinatorial or Sequential) Logic Cells Table 1 * ProASICPLUS Product Profile Device APA075 APA150 APA3001 Maximum System Gates 75,000 150,000 300,000 Tiles (Registers) 3,072 6,144 8,192 Embedded RAM Bits (k=1,024 bits) 27 k 36k 72 k Embedded RAM Blocks (256x9) 12 16 32 LVPECL 2 2 2 PLL 2 2 2 Global Networks 4 4 4 Maximum Clocks 24 32 32 Maximum User I/Os 158 242 290 JTAG ISP Yes Yes Yes PCI Yes Yes Yes Package (by pin count) TQFP 100, 144 100 - PQFP 208 208 208 PBGA - 456 456 FBGA 144 144, 256 144, 256 CQFP2 208, 352 CCGA/LGA2 Notes: 1. Available as Commercial/Industrial and Military/MIL-STD-883B devices. 2. These packages are available only for Military/MIL-STD-883B devices. December 2005 (c) 2005 Actel Corporation APA450 450,000 12,288 108 k 48 2 2 4 48 344 Yes Yes APA6001 600,000 21,504 126 k 56 2 2 4 56 454 Yes Yes APA750 750,000 32,768 144 k 64 2 2 4 64 562 Yes Yes APA10001 1,000,000 56,320 198 k 88 2 2 4 88 712 Yes Yes - 208 456 144, 256, 484 - 208 456 256, 484, 676 208, 352 624 - 208 456 676, 896 - 208 456 896, 1152 208, 352 624 i ProASICPLUS Flash Family FPGAs Ordering Information APA1000 _ F G FG 1152 I Application (Ambient Temperature Range) Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C) PP = Pre-production ES = Engineering Silicon (Room Temperature Only) M = Military (-55C to 125C) B = MIL-STD-883 Class B Package Lead Count Lead-free packaging Blank = Standard Packaging G = RoHS Compliant (Green) Packaging Package Type TQ = Thin Quad Flat Pack (0.5mm pitch) PQ = Plastic Quad Flat Pack (0.5mm pitch) FG = Fine Pitch Ball Grid Array (1.0mm pitch) BG = Plastic Ball Grid Array (1.27mm pitch) CQ = Ceramic Quad Flat Pack (1.05mm pitch) CG = Ceramic Column Grid Array (1.27mm pitch) LG = Land Grid Array (1.27 mm pitch) Speed Grade Blank = Standard Speed F = 20% Slower than Standard Part Number APA075 APA150 APA300 APA450 APA600 APA750 APA1000 = = = = = = = 75,000 Equivalent System Gates 150,000 Equivalent System Gates 300,000 Equivalent System Gates 450,000 Equivalent System Gates 600,000 Equivalent System Gates 750,000 Equivalent System Gates 1,000,000 Equivalent System Gates Plastic Device Resources User I/Os2 Military Commercial/Industrial Device TQFP TQFP PQFP PBGA FBGA FBGA FBGA FBGA FBGA FBGA CQFP CQFP CCGA/LGA 100-Pin 144-Pin 208-Pin 456-Pin 144-Pin 256-Pin 484-Pin 676-Pin 896-Pin 1152-Pin 208-Pin 352-Pin 624-Pin APA075 66 APA150 66 107 158 100 158 242 100 186 3 APA300 158 290 100 186 3 APA450 158 344 100 186 3 344 3 APA600 158 356 186 3 370 3 APA750 158 356 APA1000 158 356 454 454 562 158 248 158 248 440 158 248 440 4 642 4 712 4 Notes: 1. Package Definitions: TQFP = Thin Quad Flat Pack, PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Pitch Ball Grid Array, CQFP = Ceramic Quad Flat Pack, CCGA = Ceramic Column Grid Array, LGA = Land Grid Array 2. Each pair of PECL I/Os is counted as one user I/O. 3. FG256 and FG484 are footprint-compatible packages. 4. FG896 and FG1152 are footprint-compatible packages. ii v5.2 ProASICPLUS Flash Family FPGAs General Guideline Maximum performance numbers in this datasheet are based on characterized data. Actel does not guarantee performance beyond the limits specified within the datasheet. Temperature Grade Offerings Package APA075 APA150 APA300 APA450 APA600 APA750 APA1000 TQ100 C, I C, I TQ144 C, I PQ208 C, I C, I C, I, M C, I C, I, M C, I C, I, M C, I C, I, M C, I C, I, M C, I C, I, M C, I C, I C, I C, I C, I Commercial/Industrial BG456 FG144 FG256 C, I FG484 FG676 C, I C, I C, I C, I C, I FG896 C, I C, I FG1152 C, I C, I Military CQ208 M, B M, B M, B CQ352 M, B M, B M, B M, B M, B CG624 Note: C = Commercial I = Industrial M = Military B = MIL-STD-883 Speed Grade and Temperature Matrix C -F Std. I M, B Note: C = Commercial I = Industrial M = Military B = MIL-STD-883 v5.2 iii ProASICPLUS Flash Family FPGAs Table of Contents General Description ProASICPLUS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Timing Control and Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Sample Implementations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Adjustable Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 Clock Skew Minimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 PLL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Design Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 ISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Calculating Typical Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-33 Tristate Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-42 Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predicted Global Routing Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-44 1-46 1-48 1-50 Global Routing Skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-50 Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Sample Macrocell Library Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-51 Embedded Memory Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-54 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-73 Recommended Design Practice for VPN/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-74 Package Pin Assignments 100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 208-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12 352-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 456-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 676-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 896-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-59 1152-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69 624-Pin CCGA/LGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 iv v5.2 ProASICPLUS Flash Family FPGAs General Description The ProASICPLUS family of devices, Actel's secondgeneration Flash FPGAs, offers enhanced performance over Actel's ProASIC family. It combines the advantages of ASICs with the benefits of programmable devices through nonvolatile Flash technology. This enables engineers to create high-density systems using existing ASIC or FPGA design flows and tools. In addition, the ProASICPLUS family offers a unique clock conditioning circuit based on two on-board phase-locked loops (PLLs). The family offers up to one million system gates, supported with up to 198 kbits of two-port SRAM and up to 712 user I/Os, all providing 50 MHz PCI performance. combination of fine granularity, flexible routing resources, and abundant Flash switches allow 100% utilization and over 95% routability for highly congested designs. Tiles and larger functions are interconnected through a four-level routing hierarchy. Embedded two-port SRAM blocks with built-in FIFO/RAM control logic can have user-defined depths and widths. Users can also select programming for synchronous or asynchronous operation, as well as parity generations or checking. Advantages to the designer extend beyond performance. Unlike SRAM-based FPGAs, four levels of routing hierarchy simplify routing, while the use of Flash technology allows all functionality to be live at powerup. No external boot PROM is required to support device programming. While on-board security mechanisms prevent access to the program information, reprogramming can be performed in-system to support future design iterations and field upgrades. The device's architecture mitigates the complexity of ASIC migration at higher user volume. This makes ProASICPLUS a costeffective solution for applications in the networking, communications, computing, and avionics markets. The unique clock conditioning circuitry in each device includes two clock conditioning blocks. Each block provides a PLL core, delay lines, phase shifts (0, 90, 180, 270), and clock multipliers/dividers, as well as the circuitry needed to provide bidirectional access to the PLL. The PLL block contains four programmable frequency dividers which allow the incoming clock signal to be divided by a wide range of factors from 1 to 64. The clock conditioning circuit also delays or advances the incoming reference clock up to 8 ns (in increments of 0.25 ns). The PLL can be configured internally or externally during operation without redesigning or reprogramming the part. In addition to the PLL, there are two LVPECL differential input pairs to accommodate high-speed clock and data inputs. The ProASICPLUS family achieves its nonvolatility and reprogrammability through an advanced Flash-based 0.22 m LVCMOS process with four layers of metal. Standard CMOS design techniques are used to implement logic and control functions, including the PLLs and LVPECL inputs. This results in predictable performance compatible with gate arrays. To support customer needs for more comprehensive, lower-cost, board-level testing, Actel's ProASICPLUS devices are fully compatible with IEEE Standard 1149.1 for test access port and boundary-scan test architecture. For more information concerning the Flash FPGA implementation, please refer to the "Boundary Scan (JTAG)" section on page 1-11. The ProASICPLUS architecture provides granularity comparable to gate arrays. The device core consists of a Sea-of-TilesTM. Each tile can be configured as a flip-flop, latch, or three-input/one-output logic function by programming the appropriate Flash switches. The ProASICPLUS devices are available in a variety of highperformance plastic packages. Those packages and the performance features discussed above are described in more detail in the following sections. v5.2 1-1 ProASICPLUS Flash Family FPGAs ProASICPLUS Architecture The proprietary ProASICPLUS architecture granularity comparable to gate arrays. the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. provides The ProASICPLUS device core consists of a Sea-of-Tiles (Figure 1-1). Each tile can be configured as a three-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by programming the appropriate Flash switch interconnections (Figure 1-2 and Figure 1-3 on page 1-3). Tiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to ProASICPLUS devices also contain embedded, two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Please see the "Embedded Memory Configurations" section on page 1-22 for more information. RAM Block 256x9 Two-Port SRAM or FIFO Block I/Os Logic Tile RAM Block 256x9 Two Port SRAM or FIFO Block Figure 1-1 * The ProASICPLUS Device Architecture Floating Gate Sensing Switch In Switching Word Switch Out Figure 1-2 * Flash Switch 1 -2 v5.2 ProASICPLUS Flash Family FPGAs Local Routing In 1 Efficient Long-Line Routing In 2 (CLK) In 3 (Reset) Figure 1-3 * Core Logic Tile Live at Power-Up Flash Switch PLUS Unlike SRAM FPGAs, ProASICPLUS uses a live-on-power-up ISP Flash switch as its programming element. The Actel Flash-based ProASIC devices support Level 0 of the live at power-up (LAPU) classification standard. This feature helps in system component initialization, executing critical tasks before the processor wakes up, setting up and configuring memory blocks, clock generation, and bus activity management. The LAPU feature of Flash-based ProASICPLUS devices greatly simplifies total system design and reduces total system cost, often eliminating the need for Complex Programmable Logic Device (CPLD) and clock generation PLLs that are used for this purpose in a system. In addition, glitches and brownouts in system power will not corrupt the ProASICPLUS device's Flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based ProASICPLUS devices simplify total system design, and reduce cost and design risk, while increasing system reliability and improving system initialization time. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 1-2 on page 1-2). Logic Tile The logic tile cell (Figure 1-3) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). Any three-input, one-output logic function (except a three-input XOR) can be configured as one tile. The tile can be configured as a latch with clear or set or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. v5.2 1-3 ProASICPLUS Flash Family FPGAs Routing Resources The routing structure of ProASICPLUS devices is designed to provide high performance through a flexible fourlevel hierarchy of routing resources: ultra-fast local resources, efficient long-line resources, high-speed, very long-line resources, and high performance global networks. can in turn access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight surrounding tiles (Figure 1-4). The high-performance global networks are low-skew, high fanout nets that are accessible from external pins or from internal logic (Figure 1-7 on page 1-7). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles. The efficient long-line resources provide routing for longer distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 1-5 on page 1-5). Each tile can drive signals onto the efficient long-line resources, which L Inputs L L L L Ultra-Fast Local Lines (connects a tile to the adjacent tile, I/O buffer, or memory block) Output L The high-speed, very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 1-6 on page 1-6). L L L Figure 1-4 * Ultra-Fast Local Resources 1 -4 v5.2 ProASICPLUS Flash Family FPGAs Spans 1 Tile Spans 2 Tiles Spans 4 Tiles Logic Tile L L L L L L L L L L L L L L L L L L L L L L L L Spans 1 Tile Spans 2 Tiles Spans 4 Tiles Logic Cell L L L L L L Figure 1-5 * Efficient Long-Line Resources v5.2 1-5 ProASICPLUS Flash Family FPGAs High Speed Very Long-Line Resouces PAD RING I/O RING I/O RING PAD RING SRAM SRAM PAD RING Figure 1-6 * High-Speed, Very Long-Line Resources Clock Resources Clock Trees ProASICPLUS The family offers powerful and flexible control of circuit timing through the use of analog circuitry. Each chip has two clock conditioning blocks containing a phase-locked loop (PLL) core, delay lines, phase shifter (0, 90, 180, 270), clock multiplier/ dividers, and all the circuitry needed for the selection and interconnection of inputs to the global network (thus providing bidirectional access to the PLL). This permits the PLL block to drive inputs and/or outputs via the two global lines on each side of the chip (four total lines). This circuitry is discussed in more detail in the "ProASICPLUS Clock Management System" section on page 1-13. 1 -6 v5.2 One of the main architectural benefits of ProASICPLUS is the set of power- and delay-friendly global networks. ProASICPLUS offers four global trees. Each of these trees is based on a network of spines and ribs that reach all the tiles in their regions (Figure 1-7 on page 1-7). This flexible clock tree architecture allows users to map up to 88 different internal/external clocks in an APA1000 device. Details on the clock spines and various numbers of the family are given in Table 1-1 on page 1-7. The flexible use of the ProASICPLUS clock spine allows the designer to cope with several design requirements. Users implementing clock-resource intensive applications can easily route external or gated internal clocks using global routing spines. Users can also drastically reduce delay penalties and save buffering resources by mapping critical high fanout nets to spines. For design hints on using these features, refer to Actel's Efficient Use of ProASIC Clock Trees application note. ProASICPLUS Flash Family FPGAs High-Performance Global Network I/O RING PAD RING PAD RING Top Spine Global Networks Global Pads Global Pads Global Spine I/O RING Global Ribs Bottom Spine Scope of Spine (Shaded area plus local RAMs and I/Os) PAD RING Note: This figure shows routing for only one global path. Figure 1-7 * High-Performance Global Network Table 1-1 * Clock Spines APA075 APA150 APA300 APA450 APA600 APA750 APA1000 Global Clock Networks (Trees) 4 4 4 4 4 4 4 Clock Spines/Tree 6 8 8 12 14 16 22 Total Spines 24 32 32 48 56 64 88 Top or Bottom Spine Height (Tiles) 16 24 32 32 48 64 80 Tiles in Each Top or Bottom Spine Total Tiles 512 768 1,024 1,024 1,536 2,048 2,560 3,072 6,144 8,192 12,288 21,504 32,768 56,320 v5.2 1-7 ProASICPLUS Flash Family FPGAs Array Coordinates During many place-and-route operations in Actel's Designer software tool, it is possible to set constraints that require array coordinates. cells and core cells. In addition, the I/O coordinate system changes depending on the die/package combination. Core cell coordinates start at the lower left corner (represented as (1,1)) or at (1,5) if memory blocks are present at the bottom. Memory coordinates use the same system and are indicated in Table 1-2. The memory coordinates for an APA1000 are illustrated in Figure 1-8. For more information on how to use constraints, see the Designer User's Guide or online help for ProASICPLUS software tools. Table 1-2 is provided as a reference. The array coordinates are measured from the lower left (0,0). They can be used in region constraints for specific groups of core cells, I/Os, and RAM blocks. Wild cards are also allowed. I/O and cell coordinates are used for placement constraints. Two coordinate systems are needed because there is not a one-to-one correspondence between I/O Table 1-2 * Array Coordinates Logic Tile Min. Device x Memory Rows Max. y x Bottom Top y y y All Min. Max. APA075 1 1 96 32 - (33,33) or (33, 35) 0,0 97, 37 APA150 1 1 128 48 - (49,49) or (49, 51) 0,0 129, 53 APA300 1 5 128 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 129, 73 APA450 1 5 192 68 (1,1) or (1,3) (69,69) or (69, 71) 0,0 193, 73 APA600 1 5 224 100 (1,1) or (1,3) (101,101) or (101, 103) 0,0 225, 105 APA750 1 5 256 132 (1,1) or (1,3) (133,133) or (133, 135) 0,0 257, 137 APA1000 1 5 352 164 (1,1) or (1,3) (165,165) or (165, 167) 0,0 353, 169 (1,169) Memory Blocks (353,169) (1,167) (352,167) (1,165) (352,165) (1,164) (352,164) Core (1,5) (352,5) (1,3) (352,3) (1,1) (352,1) (0,0) Memory Blocks Figure 1-8 * Core Cell Coordinates for the APA1000 1 -8 v5.2 (353,0) ProASICPLUS Flash Family FPGAs Input/Output Blocks Table 1-3 * ProASICPLUS I/O Power Supply Voltages VDDP To meet complex system demands, the ProASICPLUS family offers devices with a large number of user I/O pins, up to 712 on the APA1000. Table 1-3 shows the available supply voltage configurations (the PLL block uses an independent 2.5 V supply on the AVDD and AGND pins). All I/Os include ESD protection circuits. Each I/O has been tested to 2000 V to the human body model (per JESD22 (HBM)). 2.5 V 3.3 V Input Compatibility 2.5 V 3.3 V Output Drive 2.5 V 3.3 V 3.3V/2.5V Signal Control Six or seven standard I/O pads are grouped with a GND pad and either a VDD (core power) or VDDP (I/O power) pad. Two reference bias signals circle the chip. One protects the cascaded output drivers, while the other creates a virtual VDD supply for the I/O ring. Y Pull-up Control EN I/O pads are fully configurable to provide the maximum flexibility and speed. Each pad can be configured as an input, an output, a tristate driver, or a bidirectional buffer (Figure 1-9 and Table 1-4). A Pad 3.3 V/2.5 V Signal Control Drive Strength and Slew-Rate Control Figure 1-9 * I/O Block Schematic Representation Table 1-4 * I/O Features Function I/O pads configured as inputs I/O pads configured as outputs Description * Selectable 2.5 V or 3.3 V threshold levels * Optional pull-up resistor * Optionally configurable as Schmitt trigger input. The Schmitt trigger input option can be configured as an input only, not a bidirectional buffer. This input type may be slower than a standard input under certain conditions and has a typical hysteresis of 0.35 V. I/O macros with an "S" in the standard I/O library have added Schmitt capabilities. * 3.3 V PCI Compliant (except Schmitt trigger inputs) * Selectable 2.5 V or 3.3 V compliant output signals * 2.5 V - JEDEC JESD 8-5 * 3.3 V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3 V PCI compliant * Ability to drive LVTTL and LVCMOS levels * Selectable drive strengths * Selectable slew rates * I/O pads configured as bidirectional * buffers * Tristate Selectable 2.5 V or 3.3 V compliant output signals 2.5 V - JEDEC JESD 8-5 * 3.3 V - JEDEC JESD 8-A (LVTTL and LVCMOS) * 3.3 V PCI compliant * Optional pull-up resistor * Selectable drive strengths * Selectable slew rates * Tristate v5.2 1-9 ProASICPLUS Flash Family FPGAs Power-Up Sequencing low voltage differential amplifier) and a signal and its complement, PPECL (I/P) (PECLN) and NPECL (PECLREF). The LVPECL input pad cell differs from the standard I/O cell in that it is operated from VDD only. While ProASICPLUS devices are live at power-up, the order of VDD and VDDP power-up is important during system start-up. VDD should be powered up simultaneously with VDDP on ProASICPLUS devices. Failure to follow these guidelines may result in undesirable pin behavior during system start-up. For more information, refer to Actel's Power-Up Behavior of ProASICPLUS Devices application note. Since it is exclusively an input, it requires no output signal, output enable signal, or output configuration bits. As a special high-speed differential input, it also does not require pull ups. Recommended termination for LVPECL inputs is shown in Figure 1-10. The LVPECL pad cell compares voltages on the PPECL (I/P) pad (as illustrated in Figure 1-11) and the NPECL pad and sends the results to the global MUX (Figure 1-14 on page 1-14). This high-speed, low-skew output essentially controls the clock conditioning circuit. LVPECL Input Pads In addition to standard I/O pads and power pads, ProASICPLUS devices have a single LVPECL input pad on both the east and west sides of the device, along with AVDD and AGND pins to power the PLL block. The LVPECL pad cell consists of an input buffer (containing a LVPECLs are designed to meet LVPECL JEDEC receiver standard levels (Table 1-5). Z 0= 50 PPECL + R = 100 From LVPECL Driver Z 0= 50 Data _ NPECL Figure 1-10 * Recommended Termination for LVPECL Inputs Voltage 2.72 2.125 1.49 0.86 Figure 1-11 * LVPECL High and Low Threshold Values Table 1-5 * Symbol LVPECL Receiver Specifications Parameter Min. Max Units VIH Input High Voltage 1.49 2.72 V VIL Input Low Voltage 0.86 2.125 V VID Differential Input Voltage 0.3 VDD V 1 -1 0 v5.2 ProASICPLUS Flash Family FPGAs Boundary Scan (JTAG) operation when no input data is supplied to them. These pins are dedicated for boundary-scan test usage. Actel recommends that a nominal 20 k pull-up resistor is added to TDO and TCK pins. ProASICPLUS devices are compatible with IEEE Standard 1149.1, which defines a set of hardware architecture and mechanisms for cost-effective, board-level testing. The basic ProASICPLUS boundary-scan logic circuit is composed of the TAP (test access port), TAP controller, test data registers, and instruction register (Figure 1-12). This circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS) and the optional IDCODE instruction (Table 1-6). The TAP controller is a four-bit state machine (16 states) that operates as shown in Figure 1-13 on page 1-12. The '1's and `0's represent the values that must be present at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the instruction register or the data register is operating in that state. ProASICPLUS devices have to be programmed at least once for complete boundary-scan functionality to be available. If boundary-scan functionality is required prior to programming, refer to online technical support on the Actel website and search for ProASICPLUS BSDL. Each test section is accessed through the TAP, which has five associated pins: TCK (test clock input), TDI and TDO (test data input and output), TMS (test mode selector) and TRST (test reset input). TMS, TDI and TRST are equipped with pull-up resistors to ensure proper I/O I/O I/O I/O I/O TDI Test Data Registers Instruction Register TAP Controller Device Logic TDO I/O TRST I/O TMS I/O TCK I/O Bypass Register I/O I/O I/O I/O I/O Figure 1-12 * ProASICPLUS JTAG Boundary Scan Test Logic Circuit Table 1-6 * Boundary-Scan Opcodes Hex Opcode EXTEST 00 SAMPLE/PRELOAD 01 IDCODE 0F CLAMP 05 BYPASS FF v5.2 1-11 ProASICPLUS Flash Family FPGAs The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for five TCK cycles. The TRST pin may also be used to asynchronously place the TAP controller in the Test-Logic-Reset state. with four fields (lowest significant byte (LSB), ID number, part number and version). The boundary-scan register observes and controls the state of each I/O pin. Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a device into a boundaryscan register chain, which starts at the TDI pin and ends at the TDO pin. The parallel ports are connected to the internal core logic tile and the input, output, and control ports of an I/O buffer to capture and load data into the register to control or observe the logic state of each I/O. ProASICPLUS devices support three types of test data registers: bypass, device identification, and boundary scan. The bypass register is selected when no other register needs to be accessed in a device. This speeds up test data transfer to other devices in a test data path. The 32-bit device identification register is a shift register 1 Test-Logic Reset 0 0 Run-Test/ Idle 1 1 Select-DRScan 0 Capture-DR 1 Capture-IR 1 0 0 0 Shift-DR 0 0 1 1 Exit-IR 0 1 1 Exit2-DR 1 Update-DR 0 1 Figure 1-13 * TAP Controller State Diagram 1 -1 2 v5.2 0 Pause-IR Pause-DR 0 0 Shift-IR 1 Exit-DR 1 Select-IRScan 0 0 Exit2-IR 1 Update-IR 0 1 1 ProASICPLUS Flash Family FPGAs Timing Control and Characteristics two signals available to drive the global networks are as follows (Figure 1-15 on page 1-15, Table 1-7 on page 115, and Table 1-8 on page 1-16): Global A (secondary clock) ProASICPLUS Clock Management System * * ProASICPLUS devices provide designers with very flexible clock conditioning capabilities. Each member of the ProASICPLUS family contains two phase-locked loop (PLL) blocks which perform the following functions: * Clock Phase Adjustment via Programmable Delay (250 ps steps from -7 ns to +8 ns) * Clock Skew Minimization * Clock Frequency Synthesis * * Output from Global MUX A Conditioned version of PLL output (fOUT) - delayed or advanced Divided version of either of the above Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)1 Global B * * * * Each PLL has the following key features: Output from Global MUX B Delayed or advanced version of fOUT Divided version of either of the above Further delayed version of either of the above (0.25 ns, 0.50 ns, or 4.00 ns delay)2 * Input Frequency Range (fIN) = 1.5 to 180 MHz * Feedback Frequency Range (fVCO) = 1.5 to 180 MHz * Output Frequency Range (fOUT) = 6 to 180 MHz Functional Description * Output Phase Shift = 0 , 90 , 180 , and 270 * Output Duty Cycle = 50% * Low Output Jitter (max at 25C) Each PLL block contains four programmable dividers as shown in Figure 1-14 on page 1-14. These allow frequency scaling of the input clock signal as follows: - fVCO <10 MHz. Jitter 1% or better - 10 MHz < fVCO < 60 MHz. Jitter 2% or better - fVCO > 60 MHz. Jitter 1% or better * * Note: Jitter(ps) = Jitter(%)* period * For Example: Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps * * Maximum Acquisition = 80 s for fVCO > 40 MHz Time = 30 s for fVCO < 40 MHz * Low Power Consumption - 6.9 mW (max - analog supply) + 7.0W/MHz (max - digital supply) The n divider divides the input clock by integer factors from 1 to 32. The m divider in the feedback path allows multiplication of the input clock by integer factors ranging from 1 to 64. The two dividers together can implement any combination of multiplication and division resulting in a clock frequency between 24 and 180 MHz exiting the PLL core. This clock has a fixed 50% duty cycle. The output frequency of the PLL core is given by the formula EQ 1-1 (fREF is the reference clock frequency): fOUT = fREF * m/n EQ 1-1 Physical Implementation * Each side of the chip contains a clock conditioning circuit based on a 180 MHz PLL block (Figure 1-14 on page 114). Two global multiplexed lines extend along each side of the chip to provide bidirectional access to the PLL on that side (neither MUX can be connected to the opposite side's PLL). Each global line has optional LVPECL input pads (described below). The global lines may be driven by either the LVPECL global input pad or the outputs from the PLL block, or both. Each global line can be driven by a different output from the PLL. Unused global pins can be configured as regular I/Os or left unconnected. They default to an input with pull-up. The The third and fourth dividers (u and v) permit the signals applied to the global network to each be further divided by integer factors ranging from 1 to 4. The implementations shown in EQ2 and EQ3 enable the user to define a wide range of frequency multiplier and divisors. fGLB = m/(n*u) EQ 1-2 fGLA = m/(n*v) EQ 1-3 1. This mode is available through the delay feature of the Global MUX driver. v5.2 1-13 ProASICPLUS Flash Family FPGAs enable the user to define a wide range of frequency multipliers and divisors. The clock conditioning circuit can advance or delay the clock up to 8 ns (in increments of 0.25 ns) relative to the positive edge of the incoming reference clock. The system also allows for the selection of output frequency clock phases of 0, 90, 180, and 270. signals relative to other signals to assist in the control of input set-up times. Not all possible combinations of input and output modes can be used. The degrees of freedom available in the bidirectional global pad system and in the clock conditioning circuit have been restricted. This avoids unnecessary and unwieldy design kit and software work. Prior to the application of signals to the rib drivers, they pass through programmable delay units, one per global network. These units permit the delaying of global AVDD AGND VDD GND GLA Global MUX B OUT Input Pins to the PLL See Figure 1-15 + 1-14 on page - Clock Conditioning Circuitry (Top level view) External Feedback Signal GLB 27 4 Global MUX A OUT 8 Flash Configuration Bits Dynamic Configuration Bits Clock Conditioning Circuitry Detailed Block Diagram CLK Bypass Primary 1 P+ OBMUX[2:0] FIVDIV[4:0] P- /n PLL Core /m 270 180 90 0 FBDIV[5:0] Clock from Core (GLINT mode) 0 /u DLYB[1:0] Delay Line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns OBDIV[1:0] 1 1 Delay Line 0.25 ns to 4.00 ns, 16 steps, 0.25 ns increments XDLYSEL Deskew Delay 2.95 ns 2 3 FBDLY[3:0] FBSEL[1:0] 3 OADIV[1:0] 2 /v DLYA[1:0] Delay Line 0.0 ns, 0.25 ns, 0.50 ns and 4.00 ns 1 OAMUX[1:0] CLKA Bypass Secondary Clock from Core (GLINT mode) Notes: 1. FBDLY is a programmable delay line from 0 to 4 ns in 250 ps increments. 2. DLYA and DLYB are programmable delay lines, each with selectable values 0 ps, 250 ps, 500 ps, and 4 ns. 3. OBDIV will also divide the phase-shift since it takes place after the PLL Core. Figure 1-14 * PLL Block - Top-Level View and Detailed PLL Block Diagram 1 -1 4 GLB 2 0 EXTFB 7 6 5 4 v5.2 GLA ProASICPLUS Flash Family FPGAs Package Pins GL Physical I/O Buffers Global MUX Configuration Tile Std. Pad Cell Global MUX B OUT NPECL PECL Pad Cell PPECL External Feedback GLMX Std. Pad Cell GL Std. Pad Cell Global MUX A OUT Configuration Tile CORE Legend Physical Pin DATA Signals to the Global MUX DATA Signals to the Core Control Signals to the Global MUX DATA Signals to the PLL Block Note: When a signal from an I/O tile is connected to the core, it cannot be connected to the Global MUX at the same time. Figure 1-15 * Input Connectors to ProASICPLUS Clock Conditioning Circuitry Table 1-7 * Clock-Conditioning Circuitry MUX Settings MUX Datapath Comments FBSEL 1 Internal Feedback 2 Internal Feedback and Advance Clock Using FBDLY 3 External Feedback (EXTFB) -0.25 to -4 ns in 0.25 ns increments XDLYSEL 0 Feedback Unchanged 1 Deskew feedback by advancing clock by system delay OBMUX Fixed delay of -2.95 ns GLB 0 Primary bypass, no divider 1 Primary bypass, use divider 2 Delay Clock Using FBDLY 4 Phase Shift Clock by 0 5 Phase Shift Clock by +90 6 Phase Shift Clock by +180 7 Phase Shift Clock by +270 OAMUX +0.25 to +4 ns in 0.25 ns increments GLA 0 Secondary bypass, no divider 1 Secondary bypass, use divider 2 Delay Clock Using FBDLY 3 Phase Shift Clock by 0 +0.25 to +4 ns in 0.25 ns increments v5.2 1-15 ProASICPLUS Flash Family FPGAs Table 1-8 * Sample Implementations Clock-Conditioning Circuitry Delay-Line Settings Delay Line Delay Value (ns) Frequency Synthesis DLYB 0 0 1 +0.25 2 +0.50 3 +4.0 DLYA 0 0 1 +0.25 2 +0.50 3 +4.0 Lock Signal An active-high Lock signal (added via the ACTgen PLL development tool) indicates that the PLL has locked to the incoming clock signal. The PLL will acquire and maintain lock even when there is jitter on the incoming clock signal. The PLL will maintain lock with an input jitter up to 5% of the input period, with a maximum of 5 ns. Users can employ the Lock signal as a soft reset of the logic driven by GLB and/or GLA. Note if FIN is not within specified frequencies, then both the FOUT and lock signal are indeterminate. PLL Configuration Options The PLL can be configured during design (via Flashconfiguration bits set in the programming bitstream) or dynamically during device operation, thus eliminating the need to reprogram the device. The dynamic configuration bits are loaded into a serial-in/parallel-out shift register provided in the clock conditioning circuit. The shift register can be accessed either from user logic within the device or via the JTAG port. Another option is internal dynamic configuration via user-designed hardware. Refer to Actel's ProASICPLUS PLL Dynamic Reconfiguration Using JTAG application note for more information. For information on the clock conditioning circuit, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. 1 -1 6 v5.2 Figure 1-16 on page 1-17 illustrates an example where the PLL is used to multiply a 33 MHz external clock up to 133 MHz. Figure 1-17 on page 1-17 uses two dividers to synthesize a 50 MHz output clock from a 40 MHz input reference clock. The input frequency of 40 MHz is multiplied by five and divided by four, giving an output clock (GLB) frequency of 50 MHz. When dividers are used, a given ratio can be generated in multiple ways, allowing the user to stay within the operating frequency ranges of the PLL. For example, in this case the input divider could have been two and the output divider also two, giving us a division of the input frequency by four to go with the feedback loop division (effective multiplication) by five. Adjustable Clock Delay Figure 1-18 on page 1-18 illustrates the delay of the input clock by employing one of the adjustable delay lines. This is easily done in ProASICPLUS by bypassing the PLL core entirely and using the output delay line. Notice also that the output clock can be effectively advanced relative to the input clock by using the delay line in the feedback path. This is shown in Figure 1-19 on page 1-18. Clock Skew Minimization Figure 1-20 on page 1-19 indicates how feedback from the clock network can be used to create minimal skew between the distributed clock network and the input clock. The input clock is fed to the reference clock input of the PLL. The output clock (GLA) feeds a clock network. The feedback input to the PLL uses a clock input delayed by a routing network. The PLL then adjusts the phase of the input clock to match the delayed clock, thus providing nearly zero effective skew between the two clocks. Refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note for more information. ProASICPLUS Flash Family FPGAs Global MUX B OUT 33 MHz /1 /n 270 180 90 0 PLL Core /m /4 /u /1 D GLB 133 MHz D D External Feedback /v D GLA Global MUX A OUT Figure 1-16 * Using the PLL 33 MHz In, 133 MHz Out Global MUX B OUT 40 MHz /4 /n PLL Core /m /5 270 180 90 0 /u /1 GLB D 50 MHz D D External Feedback /v D GLA Global MUX A OUT Figure 1-17 * Using the PLL 40 MHz In, 50 MHz Out v5.2 1-17 ProASICPLUS Flash Family FPGAs Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u /1 GLB D 133 MHz D D External Feedback /v D GLA Global MUX A OUT Figure 1-18 * Using the PLL to Delay the Input Clock Global MUX B OUT 133 MHz /1 /n 270 180 90 0 PLL Core /m /1 /u /1 GLB D 133 MHz D D External Feedback /v Global MUX A OUT Figure 1-19 * Using the PLL to Advance the Input Clock 1 -1 8 v5.2 D GLA ProASICPLUS Flash Family FPGAs Off chip Global MUX B OUT On chip /1 /n 133 MHz PLL Core /m 270 180 90 0 /u D GL B /1 D External Feedback D 133 MHz /v Global MUX A OUT Reference clock Q SET D GL A D Q CLR Figure 1-20 * Using the PLL for Clock Deskewing v5.2 1-19 ProASICPLUS Flash Family FPGAs Logic Tile Timing Characteristics Timing Derating ProASICPLUS Timing characteristics for devices fall into three categories: family dependent, device dependent, and design dependent. The input and output buffer characteristics are common to all ProASICPLUS family members. Internal routing delays are device dependent. Design dependency means that actual delays are not determined until after placement and routing of the user's design are complete. Delay values may then be determined by using the Timer utility or by performing simulation with post-layout delays. Since ProASICPLUS devices are manufactured with a CMOS process, device performance will vary with temperature, voltage, and process. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and optimal process variations. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case process variations (within process specifications). The derating factors shown in Table 1-9 should be applied to all timing data contained within this datasheet. Critical Nets and Typical Nets All timing numbers listed in this datasheet represent sample timing characteristics of ProASICPLUS devices. Actual timing delay values are design-specific and can be derived from the Timer tool in Actel's Designer software after place-and-route. Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timing-critical paths. Critical nets are determined by net property assignment prior to place-and-route. Refer to the Actel Designer User's Guide or online help for details on using constraints. Table 1-9 * Temperature and Voltage Derating Factors (Normalized to Worst-Case Commercial, TJ = 70C, VDD = 2.3 V) -55C -40C 0C 25C 70C 85C 110C 125C 135C 150C 2.3 V 0.84 0.86 0.91 0.94 1.00 1.02 1.05 1.13 1.18 1.27 2.5 V 0.81 0.82 0.87 0.90 0.95 0.98 1.01 1.09 1.13 1.21 2.7 V 0.77 0.79 0.83 0.86 0.91 0.93 0.96 1.04 1.08 1.16 Notes: 1. The user can set the junction temperature in Designer software to be any integer value in the range of -55C to 175C. 2. The user can set the core voltage in Designer software to be any value between 1.4 V and 1.6 V. 1 -2 0 v5.2 ProASICPLUS Flash Family FPGAs PLL Electrical Specifications Parameter Value Notes Reference Frequency fIN (min.) 1.5 MHz Clock conditioning circuitry (min.) lowest input frequency Reference Frequency fIN (max.) 180 MHz Clock conditioning circuitry (max.) highest input frequency OSC Frequency fVCO (min.) 24 MHz Lowest output frequency voltage controlled oscillator OSC Frequency fVCO (max.) 180 MHz Highest output frequency voltage controlled oscillator Frequency Ranges Clock Conditioning Circuitry fOUT (min.) 6 MHz Lowest output frequency clock conditioning circuitry Clock Conditioning Circuitry fOUT (max.) 180 MHz Highest output frequency clock conditioning circuitry Long Term Jitter Peak-to-Peak Max.* Temperature 25C (or higher) Frequency MHz fVCO<10 10<fVCO<60 fVCO>60 1% 2% 1% Jitter(ps) = Jitter(%)*period For example: Jitter in picoseconds at 100 MHz = 0.01 * (1/100E6) = 100 ps 0C 1.5% 2.5% 1% -40C 2.5% 3.5% 1% -55C 2.5% 3.5% 1% Acquisition Time from Cold Start Acquisition Time (max.) 30 s fVCO 40 MHz Acquisition Time (max.) 80 s fVCO > 40 MHz Power Consumption Analog Supply Power (max.*) 6.9 mW per PLL Digital Supply Current (max.) 7 W/MHz Duty Cycle 50% 0.5% 5% input period (max. 5 ns) Input Jitter Tolerance Maximum jitter allowable on an input clock to acquire and maintain lock. Note: *High clock frequencies (>60 MHz) under typical setup conditions v5.2 1-21 ProASICPLUS Flash Family FPGAs (R) User Security Embedded Memory Configurations ProASICPLUS The embedded memory in the ProASICPLUS family provides great configuration flexibility (Table 1-11). Each ProASICPLUS block is designed and optimized as a twoport memory (one read, one write). This provides 198 kbits of two-port and/or single port memory in the APA1000 device. devices have FlashLock protection bits that, once programmed, block the entire programmed contents from being read externally. Please refer to Table 1-10 for details on the number of bits in the key for each device. If locked, the user can only reprogram the device employing the user-defined security key. This protects the device from being read back and duplicated. Since programmed data is stored in nonvolatile memory cells (actually very small capacitors) rather than in the wiring, physical deconstruction cannot be used to compromise data. This type of security breach is further discouraged by the placement of the memory cells beneath the four metal layers (whose removal cannot be accomplished without disturbing the charge in the capacitor). This is the highest security provided in the industry. For more information, refer to Actel's Design Security in Nonvolatile Flash and Antifuse FPGAs white paper. Each memory block can be configured as FIFO or SRAM, with independent selection of synchronous or asynchronous read and write ports (Table 1-12). Additional characteristics include programmable flags as well as parity checking and generation. Figure 1-21 on page 1-24 and Figure 1-22 on page 1-25 show the block diagrams of the basic SRAM and FIFO blocks. Table 1-13 on page 1-24 and Table 1-14 on page 1-25 describe memory block SRAM and FIFO interface signals, respectively. A single memory block is designed to operate at up to 150 MHz (standard speed grade typical conditions). Each block is comprised of 256 9-bit words (one read port, one write port). The memory blocks may be cascaded in width and/or depth to create the desired memory organization. (Figure 1-23 on page 1-26). This provides optimal bit widths of 9 (one block), 18, 36, and 72, and optimal depths of 256, 512, 768, and 1,024. Refer to Actel's ACTgen User's Guide for more information. Table 1-10 * Flashlock Key Size by Device Device Key Size APA075 79 bits APA150 79 bits APA300 79 bits APA450 119 bits APA600 167 bits APA750 191 bits APA1000 263 bits Figure 1-24 on page 1-26 gives an example of optimal memory usage. Ten blocks with 23,040 bits have been used to generate three arrays of various widths and depths. Figure 1-25 on page 1-26 shows how RAM blocks can be used in parallel to create extra read ports. In this example, using only 10 of the 88 available blocks of the APA1000 yields an effective 6,912 bits of multiple port RAM. The Actel ACTgen software facilitates building wider and deeper memory configurations for optimal memory usage. Embedded Memory Floorplan The embedded memory is located across the top and bottom of the device in 256x9 blocks (Figure 1-1 on page 1-2). Depending on the device, up to 88 blocks are available to support a variety of memory configurations. Each block can be programmed as an independent memory array or combined (using dedicated memory routing resources) to form larger, more complex memory configurations. A single memory configuration could include blocks from both the top and bottom memory locations. Table 1-11 * ProASICPLUS Memory Configurations by Device Maximum Width Maximum Depth Device Bottom Top D W D W APA075 APA150 APA300 APA450 APA600 APA750 APA1000 0 0 16 24 28 32 44 12 16 16 24 28 32 44 256 256 256 256 256 256 256 108 144 144 216 252 288 396 1,536 2,048 2,048 3,072 3,584 4,096 5,632 9 9 9 9 9 9 9 1 -2 2 v5.2 ProASICPLUS Flash Family FPGAs Table 1-12 * Basic Memory Configurations Type Write Access Read Access Parity Library Cell Name RAM Asynchronous Asynchronous Checked RAM256x9AA RAM Asynchronous Asynchronous Generated RAM256x9AAP RAM Asynchronous Synchronous Transparent Checked RAM256x9AST RAM Asynchronous Synchronous Transparent Generated RAM256x9ASTP RAM Asynchronous Synchronous Pipelined Checked RAM256x9ASR RAM Asynchronous Synchronous Pipelined Generated RAM256x9ASRP RAM Synchronous Asynchronous Checked RAM256x9SA RAM Synchronous Asynchronous Generated RAM256xSAP RAM Synchronous Synchronous Transparent Checked RAM256x9SST RAM Synchronous Synchronous Transparent Generated RAM256x9SSTP RAM Synchronous Synchronous Pipelined Checked RAM256x9SSR RAM Synchronous Synchronous Pipelined Generated RAM256x9SSRP FIFO Asynchronous Asynchronous Checked FIFO256x9AA FIFO Asynchronous Asynchronous Generated FIFO256x9AAP FIFO Asynchronous Synchronous Transparent Checked FIFO256x9AST FIFO Asynchronous Synchronous Transparent Generated FIFO256x9ASTP FIFO Asynchronous Synchronous Pipelined Checked FIFO256x9ASR FIFO Asynchronous Synchronous Pipelined Generated FIFO256x9ASRP FIFO Synchronous Asynchronous Checked FIFO256x9SA FIFO Synchronous Asynchronous Generated FIFO256x9SAP FIFO Synchronous Synchronous Transparent Checked FIFO256x9SST FIFO Synchronous Synchronous Transparent Generated FIFO256x9SSTP FIFO Synchronous Synchronous Pipelined Checked FIFO256x9SSR FIFO Synchronous Synchronous Pipelined Generated FIFO256x9SSRP v5.2 1-23 ProASICPLUS Flash Family FPGAs DI <0:8> WADDR <0:7> DO <0:8> RADDR <0:7> SRAM (256x9) WRB WBLKB RDB RBLKB RCLKS Sync Write and Sync Read Ports WCLKS WPE DI <0:8> WADDR <0:7> WRB WBLKB WPE RPE PARODD DI <0:8> WADDR <0:7> DO <0:8> RADDR <0:7> WPE DI <0:8> WADDR <0:7> WRB WBLKB RDB RBLKB Sync Write and Async Read Ports WCLKS Async Write and Async Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE PARODD SRAM (256x9) WRB WBLKB SRAM (256x9) RPE WPE PARODD SRAM (256x9) Async Write and Sync Read Ports DO <0:8> RADDR <0:7> RDB RBLKB RCLKS RPE PARODD Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-21 * Example SRAM Block Diagrams Table 1-13 * Memory Block SRAM Interface Signals SRAM Signal Description Bits In/Out WCLKS 1 In Write clock used on synchronization on write side RCLKS 1 In Read clock used on synchronization on read side RADDR<0:7> 8 In Read address RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) WADDR<0:7> 8 In Write address WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> can be used for parity In WRB 1 In Write pulse (active Low) DO<0:8> 9 Out Output data bits <0:8>, <8> can be used for parity Out RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) PARODD 1 In Selects Odd parity generation/detect when High, Even parity when Low Note: Not all signals shown are used in all modes. 1 -2 4 v5.2 ProASICPLUS Flash Family FPGAs DI<0:8> DI<0:8> LEVEL<0:7> LGDEP<0:2> FIFO (256x9) WRB WBLKB WPE RBLKB PARODD RDB RBLKB EQTH PARODD GEQTH WCLKS FIFO (256x9) WRB WBLKB RPE FULL EMPTY Sync Write and Sync Read Ports RDB DO <0:8> LEVEL<0:7> LGDEP<0:2> DO <0:8> Sync Write and Async Read Ports DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB DO <0:8> FIFO (256x9) Async Write and Sync Read Ports RBLKB PARODD GEQTH RESET RCLKS RDB EQTH WCLKS RESET DI <0:8> LEVEL <0:7> LGDEP<0:2> WRB WBLKB WPE RPE FULL EMPTY WPE RPE FULL EMPTY EQTH RDB RBLKB GEQTH RESET DO <0:8> FIFO (256x9) WPE Async Write and Async Read Ports EMPTY EQTH GEQTH PARODD RCLKS RPE FULL RESET Note: Each RAM block contains a multiplexer (called DMUX) for each output signal, increasing design efficiency. These DMUX cells do not consume any core logic tiles and connect directly to high-speed routing resources between the RAM blocks. They are used when RAM blocks are cascaded and are automatically inserted by the software tools. Figure 1-22 * Basic FIFO Block Diagrams Table 1-14 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out WCLKS 1 In Write clock used for synchronization on write side Description RCLKS 1 In Read clock used for synchronization on read side LEVEL <0:7> 8 In Direct configuration implements static flag logic RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) RESET 1 In Reset for FIFO pointers (active Low) WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> will be generated parity if PARGEN is true WRB 1 In Write pulse (active Low) FULL, EMPTY 2 Out FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH 2 Out EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 Out Output data bits <0:8>. <8> will be parity output if PARGEN is true. RPE 1 Out Read parity error (active High) WPE 1 Out LGDEP <0:2> 3 In Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 In Parity generation/detect - Even when Low, Odd when High Write parity error (active High) v5.2 1-25 ProASICPLUS Flash Family FPGAs 9 Word Width 9 9 9 9 9 Word Depth 256 256 9 9 256 9 256 256 256 256 256 256 88 blocks Figure 1-23 * APA1000 Memory Block Architecture Word Width 9 9 Word Depth 9 256 256 256 256 256 256 256 9 9 256 256 256 words x 18 bits, 1 read, 1 write 512 words x 18 bits, 1 read, 1 write 256 1,024 words x 9 bits, 1 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 23,040 Figure 1-24 * Example Showing Memory Arrays with Different Widths and Depths Word Width 9 Word Depth 99 9 9 9 Write Port 9 9 Write Port 9 256 256 256 256 256 256 Read Ports 256 256 256 256 256 words x 9 bits, 2 read, 1 write Read Ports 512 words x 9 bits, 4 read, 1 write Total Memory Blocks Used = 10 Total Memory Bits = 6,912 Figure 1-25 * Multi-Port Memory Usage 1 -2 6 v5.2 ProASICPLUS Flash Family FPGAs Design Environment The ProASICPLUS family of FPGAs is fully supported by both Actel's Libero(R) Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is an integrated design manager that seamlessly integrates design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Additionally, Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment (see Actel's website for more information about Libero IDE). Libero IDE includes Synplify(R) AE from Synplicity(R), ViewDraw(R) AE from Mentor Graphics(R), ModelSim(R) HDL Simulator from Mentor Graphics, WaveFormer LiteTM AE from SynaptiCAD(R), PALACETM AE Physical Synthesis from Magma, and Designer software from Actel. With the Designer software, a user can lock the design pins before layout while minimally impacting the results of place-and-route. Additionally, Actel's back-annotation flow is compatible with all the major simulators. Another tool included in the Designer software is the ACTgen macro builder, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. PALACE is an effective tool when designing with ProASICPLUS. PALACE AE Physical Synthesis from Magma takes an EDIF netlist and optimizes the performance of ProASICPLUS devices through a physical placement-driven process, ensuring that timing closure is easily achieved. ISP Actel's Designer software is compatible with the most popular FPGA design entry and verification tools from EDA vendors, such as Mentor Graphics, Synplicity, Synopsys, and Cadence Design Systems. The Designer software is available for both the Windows and UNIX operating systems. The user can generate *.bit or *.stp programming files from the Designer software and can use these files to program a device. ProASICPLUS devices can be programmed in-system. For more information on ISP of ProASICPLUS devices, refer to the In-System Programming ProASICPLUS Devices and Performing Internal In-System Programming Using Actel's ProASICPLUS Devices application notes. Prior to being programmed for the first time, the ProASICPLUS device I/Os are in a tristate condition with the pull-up resistor option enabled. Actel's Designer software is a place-and-route tool that provides a comprehensive suite of back-end support tools for FPGA development. The Designer software includes the following: * Timer - a world-class integrated static timing analyzer and constraints editor that support timing-driven place-and-route * NetlistViewer - a design netlist schematic viewer * ChipPlanner - a graphical floorplanner viewer and editor * SmartPower - allows the designer to quickly estimate the power consumption of a design * PinEditor - a graphical application for editing pin assignments and I/O attributes * I/O Attribute Editor - displays all assigned and unassigned I/O macros and their attributes in a spreadsheet format v5.2 1-27 ProASICPLUS Flash Family FPGAs Related Documents Application Notes Efficient Use of ProASIC Clock Trees http://www.actel.com/documents/A500K_Clocktree_AN.pdf I/O Features in ProASICPLUS Flash FPGAs http://www.actel.com/documents/APA_LVPECL_AN.pdf Power-Up Behavior of ProASICPLUS Devices http://www.actel.com/documents/APA_PowerUp.pdf ProASICPLUS PLL Dynamic Reconfiguration Using JTAG http://www.actel.com/documents/APA_PLLdynamic_AN.pdf Using ProASICPLUS Clock Conditioning Circuits http://www.actel.com/documents/APA_PLL_AN.pdf In-System Programming ProASICPLUS Devices http://www.actel.com/documents/APA_External_ISP_AN.pdf Performing Internal In-System Programming Using Actel's ProASICPLUS Devices http://www.actel.com/documents/APA_Microprocessor_AN.pdf ProASICPLUS RAM and FIFO Blocks http://www.actel.com/documents/APA_RAM_FIFO_AN.pdf White Paper Design Security in Nonvolatile Flash and Antifuse FPGAs http://www.actel.com/documents/DesignSecurity_WP.pdf User's Guide Designer User's Guide http://www.actel.com/documents/designer_UG.pdf ACTgen User's Guide http://www.actel.com/documents/genguide_UG.pdf ProASIC and ProASICPLUS Macro Library Guide http://www.actel.com/documents/pa_libguide_UG.pdf Additional Information The following link contains additional information on ProASICPLUS Devices. http://www.actel.com/products/proasicplus/info.aspx 1 -2 8 v5.2 ProASICPLUS Flash Family FPGAs Package Thermal Characteristics the maximum allowable temperature on the active surface of the IC and is 110 C. P is defined as: The ProASICPLUS family is available in several package types with a range of pin counts. Actel has selected packages based on high pin count, reliability factors, and superior thermal characteristics. T J - TA P = -----------------ja EQ 1-4 Thermal resistance defines the ability of a package to conduct heat away from the silicon, through the package to the surrounding air. Junction-to-ambient thermal resistance is measured in degrees Celsius/Watt and is represented as Theta ja (ja). The lower the thermal resistance, the more efficiently a package will dissipate heat. ja is a function of the rate (in linear feet per minute (lfpm)) of airflow in contact with the package. When the estimated power consumption exceeds the maximum allowed power, other means of cooling, such as increasing the airflow rate, must be used. The maximum power dissipation allowed for a Military temperature device is specified as a function of jc. The absolute maximum junction temperature is 150C. A package's maximum allowed power (P) is a function of maximum junction temperature (TJ), maximum ambient operating temperature (TA), and junction-to-ambient thermal resistance ja. Maximum junction temperature is The calculation of the absolute maximum power dissipation allowed for a Military temperature application is illustrated in the following example for a 456-pin PBGA package: Max. junction temp. (C) - Max. case temp. (C) 150C - 125C Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------ = -------------------------------------- = 8.333W 3.0C/W jc (C/W) EQ 1-5 Table 1-15 * Package Thermal Characteristics ja Pin Count jc Still Air 1.0 m/s 200 ft./min. 2.5 m/s 500 ft./min. Units 100 14.0 33.5 27.4 25.0 C/W 144 11.0 33.5 28.0 25.7 C/W 208 8.0 26.1 22.5 20.8 C/W PQFP with Heat spreader 208 3.8 16.2 13.3 11.9 C/W Plastic Ball Grid Array (PBGA) 456 3.0 15.6 12.5 11.6 C/W Fine Pitch Ball Grid Array (FBGA) 144 3.8 26.9 22.9 21.5 C/W Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.6 22.8 21.5 C/W Fine Pitch Ball Grid Array (FBGA)3 484 3.2 18.0 14.7 13.6 C/W (FBGA)4 484 3.2 20.5 17.0 15.9 C/W Fine Pitch Ball Grid Array (FBGA) 676 3.2 16.4 13.0 12.0 C/W Fine Pitch Ball Grid Array (FBGA) 896 2.4 13.6 10.4 9.4 C/W Fine Pitch Ball Grid Array (FBGA) 1152 1.8 12.0 8.9 7.9 C/W Ceramic Quad Flat Pack (CQFP) 208 2.0 22.0 19.8 18.0 C/W Ceramic Quad Flat Pack (CQFP) 352 2.0 17.9 16.1 14.7 C/W Ceramic Column Grid Array (CCGA/LGA) 624 6.5 8.9 8.5 8.0 C/W Plastic Packages Thin Quad Flat Pack (TQFP) Thin Quad Flat Pack (TQFP) 1 Plastic Quad Flat Pack (PQFP) 2 Fine Pitch Ball Grid Array Notes: 1. 2. 3. 4. Valid for the following devices irrespective of temperature grade: APA075, APA150, and APA300 Valid for the following devices irrespective of temperature grade: APA450, APA600, APA750, and APA1000 Depopulated Array Full array v5.2 1-29 ProASICPLUS Flash Family FPGAs Calculating Typical Power Dissipation ProASICPLUS device power is calculated with both a static and an active component. The active component is a function of both the number of tiles utilized and the system speed. Power dissipation can be calculated using the following formula: Total Power Consumption--Ptotal Ptotal = Pdc + Pac where: Pdc = 7 mW for the APA075 8 mW for the APA150 11 mW for the APA300 12 mW for the APA450 12 mW for the APA600 13 mW for the APA750 19 mW for the APA1000 Pdc includes the static components of PVDDP + PVDD + PAVDD Pac = Pclock + Pstorage + Plogic + Poutputs + Pinputs + Ppll + Pmemory Global Clock Contribution--Pclock Pclock, the clock component of power dissipation, is given by the piece-wise model: for R < 15000 the model is: (P1 + (P2*R) - (P7*R2)) * Fs (lightly-loaded clock trees) for R > 15000 the model is: (P10 + P11*R) * Fs (heavily-loaded clock trees) where: P1 = 100 W/MHz is the basic power consumption of the clock tree per MHz of the clock P2 = 1.3 W/MHz is the incremental power consumption of the clock tree per storage tile - also per MHz of the clock P7 = 0.00003 W/MHz is a correction factor for partially-loaded clock trees P10 = 6850 W/MHz is the basic power consumption of the clock tree per MHz of the clock P11 = 0.4 W/MHz is the incremental power consumption of the clock tree per storage tile - also per MHz of the clock R = the number of storage tiles clocked by this clock Fs = the clock frequency Storage-Tile Contribution--Pstorage Pstorage, the storage-tile (Register) component of AC power dissipation, is given by Pstorage = P5 * ms * Fs where: 1 -3 0 P5 = ms Fs = = 1.1 W/MHz is the average power consumption of a storage tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2. the number of storage tiles (Register) switching during each Fs cycle the clock frequency v5.2 ProASICPLUS Flash Family FPGAs Logic-Tile Contribution--Plogic Plogic, the logic-tile component of AC power dissipation, is given by Plogic = P3 * mc * Fs where: P3 = mc Fs = = 1.4 W/MHz is the average power consumption of a logic tile per MHz of its output toggling rate. The maximum output toggling rate is Fs/2. the number of logic tiles switching during each Fs cycle the clock frequency I/O Output Buffer Contribution--Poutputs Poutputs, the I/O component of AC power dissipation, is given by Poutputs = (P4 + (Cload * VDDP2)) * p * Fp where: P4 = Cload = p = Fp = 326 W/MHz is the intrinsic power consumption of an output pad normalized per MHz of the output frequency. This is the total I/O current VDDP. the output load the number of outputs the average output frequency I/O Input Buffer's Buffer Contribution--Pinputs The input's component of AC power dissipation is given by Pinputs = P8 * q * Fq where: P8 = 29 W/MHz is the intrinsic power consumption of an input pad normalized per MHz of the input frequency. q = the number of inputs Fq = the average input frequency PLL Contribution--Ppll Ppll = P9 * Npll where: P9 = 7.5 mW. This value has been estimated at maximum PLL clock frequency. NPll = number of PLLs used RAM Contribution--Pmemory Finally, Pmemory, the memory component of AC power consumption, is given by Pmemory = P6 * Nmemory * Fmemory * Ememory where: P6 Nmemory = = Fmemory Ememory = = 175 W/MHz is the average power consumption of a memory block per MHz of the clock the number of RAM/FIFO blocks (1 block = 256 words * 9 bits) the clock frequency of the memory the average number of active blocks divided by the total number of blocks (N) of the memory. * Typical values for Ememory would be 1/4 for a 1k x 8,9,16, 32 memory and 1/16 for a 4kx8, 9, 16, and 32 memory configuration * In addition, an application-dependent component to Ememory can be considered. For example, for a 1kx8 memory configuration using only 1 cycle out of 2, Ememory = 1/4*1/2 = 1/8 v5.2 1-31 ProASICPLUS Flash Family FPGAs The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles. This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as follows: Pclock Fs = 10 MHz R = 13,440 Pclock = (P1 + (P2*R) - (P7*R2)) * Fs = 121.5 mW => Pstorage ms => = 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz) Pstorage = P5 * ms * Fs = 147.8 mW Plogic mc => = 0 (no logic tiles in this shift register) Plogic = 0 mW Poutputs => Cload = 40 pF VDDP = 3.3 V p = 24 Fp = 5 MHz Poutputs = (P4 + (Cload * VDDP2)) * p * Fp = 91.4 mW Pinputs => q = 1 Fq = 10 MHz Pinputs = P8 * q * Fq = 0.3 mW Pmemory Nmemory => = 0 (no RAM/FIFO blocks in this shift register) Pmemory = 0 mW Pac => 361 mW Ptotal Pdc + Pac = 374 mW (typical) 1 -3 2 v5.2 ProASICPLUS Flash Family FPGAs Operating Conditions Standard and -F parts are the same unless otherwise noted. All -F parts are only available as commercial. Table 1-16 * Absolute Maximum Ratings* Parameter Condition Minimum Maximum Units Supply Voltage Core (VDD) -0.3 3.0 V Supply Voltage I/O Ring (VDDP) -0.3 4.0 V DC Input Voltage -0.3 VDDP + 0.3 V PCI DC Input Voltage -1.0 VDDP + 1.0 V PCI DC Input Clamp Current (absolute) VIN < -1 or VIN = VDDP + 1 V LVPECL Input Voltage GND 10 mA -0.3 VDDP + 0.5 V 0 0 V Note: *Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated outside the Recommended Operating Conditions. Table 1-17 * Programming, Storage, and Operating Limits Storage Temperature Operating Programming Cycles (min.) Program Retention (min.) Min. Max. TJ Max. Junction Temperature 500 20 years -55C 110C 110C Industrial 500 20 years -55C 110C 110C Military 100 - -65C 150C 150C MIL-STD-883 100 - -65C 150C 150C Product Grade Commercial Performance Retention Example - the ambient temperature of a system cycles between 100C (25% of the time) and 50C (75% of the time). No forced ventilation cooling system is in use. An APA600-PQ208M FPGA operates in the system, dissipating 1 W. The package thermal resistance (junction-to-ambient) in still air ja is 20C/W, indicating that the junction temperature of the FPGA will be 120C (25% of the time) and 70C (75% of the time). The entry in Table 1-18 on page 1-34, which most closely matches the application, is 25% at 125C with 75% at 110C. Performance retention in this example is at least 16.0 years. For devices operated and stored at 110C or less, the performance retention period is 20 years after programming. For devices operated and stored at temperatures greater than 110C, refer to Table 1-18 on page 1-34 to determine the performance retention period. Actel does not guarantee performance if the performance retention period is exceeded. Designers can determine the performance retention period from the following table. Evaluate the percentage of time spent at the highest temperature, then determine the next highest temperature to which the device will be exposed. In Table 1-18 on page 1-34, find the temperature profile that most closely matches the application. Note that exceeding the stated retention period may result in a performance degradation in the FPGA below the worst-case performance indicated in the Actel Timer. To ensure that performance does not degrade below the worst-case values in the Actel Timer, the FPGA must be reprogrammed within the performance retention period. In addition, note that performance retention is independent of whether or not the FPGA is operating. The retention period of a device in storage at a given temperature will be the same as the retention period of a device operating at that junction temperature. v5.2 1-33 ProASICPLUS Flash Family FPGAs Table 1-18 * Performance Retention Minimum Time at TJ 110C or below Minimum Time at TJ 125C or below Minimum Time at TJ 135C or below Minimum Time at TJ 150C or below 100% 20.0 90% 10% 18.2 75% 25% 16 90% 50% 10% 15.4 50% 13.3 90% 10% 75% 25% 90% 50% 75% 10 10% 9.1 50% 8 25% 8 90% 75% 50% 11.8 11.4 100% 10% 7.7 25% 7.3 50% 75% 6.7 25% 100% 90% 5.7 5 10% 4.5 50% 4.4 50% 4 75% 25% 4 50% 50% 3.3 100% 2.5 50% 50% 1 -3 4 Minimum Performance Retention (Years) v5.2 ProASICPLUS Flash Family FPGAs Table 1-19 * Recommended Maximum Operating Conditions Programming and PLL Supplies Commercial/Industrial/Military/MIL-STD-883 Parameter VPP Condition Maximum Units 15.8 16.5 V 0 16.5 V -13.8 -13.2 V -13.8 During Programming Normal Operation VPN Minimum 1 During Programming 2 0.5 V IPP During Programming 25 mA IPN During Programming 10 mA Normal Operation AVDD VDD VDD V AGND GND GND V Notes: 1. Please refer to the "VPP Programming Supply Pin" section on page 1-74 for more information. 2. Please refer to the "VPN Programming Supply Pin" section on page 1-74 for more information. Table 1-20 * Recommended Operating Conditions Limits Parameter Symbol Commercial Industrial Military/MIL-STD-883 DC Supply Voltage (2.5 V I/Os) VDD and VDDP 2.5 V 0.2 V 2.5 V 0.2 V 2.5 V 0.2 V DC Supply Voltage (3.3 V I/Os) VDDP VDD 3.3 V 0.3 V 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V 3.3 V 0.3 V 2.5 V 0.2 V Operating Ambient Temperature Range TA, TC 0C to 70C -40C to 85C -55C (TA) to 125C (TC) TJ 110C 110C 150C Maximum Operating Junction Temperature Note: For I/O long-term reliability, external pull-up resistors cannot be used to increase output voltage above VDDP. v5.2 1-35 ProASICPLUS Flash Family FPGAs Table 1-21 * DC Electrical Specifications (VDDP = 2.5 V 0.2V) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol Parameter VOH Output High Voltage High Drive (OB25LPH) Low Drive (OB25LPL) VOL Conditions Min. IOH = -6 mA IOH = -12 mA IOH = -24 mA 2.1 2.0 1.7 IOH = -3 mA IOH = -6 mA IOH = -8 mA 2.1 1.9 1.7 Typ. Max. Units V Output Low Voltage High Drive (OB25LPH) Low Drive (OB25LPL) IOL = 8 mA IOL = 15 mA IOL = 24 mA 0.2 0.4 0.7 IOL = 4 mA IOL = 8 mA IOL = 15 mA 0.2 0.4 0.7 V VIH6 Input High Voltage 1.7 VDDP + 0.3 V VIL7 Input Low Voltage -0.3 0.7 V 6 56 k 0.45 V RWEAKPULLUP Weak Pull-up Resistance (OTB25LPU) VIN 1.25 V HYST Input Hysteresis Schmitt See Table 1-4 on page 1-9 IIN Input Current with pull up (VIN = GND) -240 - 20 A without pull up (VIN = GND or VDD) -10 10 A IDDQ IDDQ IDDQ GND4 Quiescent Supply Current (standby) Commercial VIN = Quiescent Supply Current (standby) Industrial VIN = GND4 or VDD Quiescent Supply Current (standby) Military/MIL-STD-883 VIN = GND4 or VDD or VDD Tristate Output Leakage Current VOH = GND or VDD IOZ 0.3 0.35 Std. 5.0 15 mA -F3 5.0 25 mA 5.0 20 mA 5.0 25 mA Std. Std. Std. -10 10 A -F3, 5 -10 100 A Notes: 1. 2. 3. 4. 5. 6. 7. All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are available only as commercial. No pull-up resistor. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle. 1 -3 6 v5.2 ProASICPLUS Flash Family FPGAs Table 1-21 * DC Electrical Specifications (VDDP = 2.5 V 0.2V) (Continued) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol Parameter IOSH Output Short Circuit Current High High Drive (OB25LPH) VIN = VSS VIN = VSS Low Drive (OB25LPL) IOSL Min. Conditions Typ. Max. Units mA -120 -100 mA Output Short Circuit Current Low High Drive (OB25LPH) VIN = VDDP VIN = VDDP Low Drive (OB25LPL) 100 30 CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF Notes: 1. 2. 3. 4. 5. 6. 7. All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are available only as commercial. No pull-up resistor. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0V for a limited time of no larger than 10% of the duty cycle. v5.2 1-37 ProASICPLUS Flash Family FPGAs Table 1-22 * DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol Parameter VOH Output High Voltage 3.3 V I/O, High Drive (OB33P) 3.3 V I/O, Low Drive (OB33L) Output Low Voltage 3.3 V I/O, High Drive (OB33P) VOL Conditions Min. IOH = -14 mA IOH = -24 mA 0.9VDDP 2.4 IOH = -6 mA IOH = -12 mA 0.9VDDP 2.4 Typ. Max. V IOL = 15 mA IOL = 20 mA IOL = 28 mA 0.1VDDP 0.4 0.7 IOL = 7 mA IOL = 10 mA IOL = 15 mA 0.1VDDP 0.4 0.7 3.3 V I/O, Low Drive (OB33L) VIH6 VIL7 1.6 2 1.7 VDDP + 0.3 VDDP + 0.3 VDDP + 0.3 Input Low Voltage 3.3 V Schmitt Trigger Inputs 3.3 V LVTTL/LVCMOS 2.5 V Mode -0.3 -0.3 -0.3 0.8 0.8 0.7 V Resistance VIN 1.5 V 7 43 k Resistance VIN 1.5 V 7 43 k with pull up (VIN = GND) -300 -40 A without pull up (VIN = GND or VDD) -10 10 A RWEAKPULLUP Weak Pull-up (IOB25U) Input Current IDDQ IDDQ IDDQ GND4 Quiescent Supply Current (standby) Commercial VIN = Quiescent Supply Current (standby) Industrial VIN = GND4 or VDD Quiescent Supply Current (standby) Military VIN = GND4 or VDD 1 -3 8 V Std. 5.0 15 mA -F3 5.0 25 mA Std. 5.0 20 mA Std. 5.0 25 mA or VDD Notes: 1. 2. 3. 4. 5. 6. 7. V Input High Voltage 3.3 V Schmitt Trigger Inputs 3.3 V LVTTL/LVCMOS 2.5 V Mode Pull-up RWEAKPULLUP Weak (IOB33U) IIN Units All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are only available as commercial. No pull-up resistor required. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0 V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0 V for a limited time of no larger than 10% of the duty cycle. v5.2 ProASICPLUS Flash Family FPGAs Table 1-22 * DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V) (Continued) Commercial/Industrial/ Military/MIL-STD-8831, 2 Symbol Parameter IOZ Tristate Current IOSH Output Conditions Min. Leakage VOH = GND or VDD Output Short Circuit Current High 3.3 V High Drive (OB33P) VIN = GND 3.3 V Low Drive (OB33L) VIN = GND Typ. Max. Units Std. -10 10 A -F3, 5 -10 100 A -200 -100 Output Short Circuit Current Low 3.3 V High Drive VIN = VDD VIN = VDD 3.3 V Low Drive 200 100 CI/O I/O Pad Capacitance 10 pF CCLK Clock Input Pad Capacitance 10 pF IOSL Notes: 1. 2. 3. 4. 5. 6. 7. All process conditions. Commercial/Industrial: Junction Temperature: -40 to +110C. All process conditions. Military: Junction Temperature: -55 to +150C. All -F parts are only available as commercial. No pull-up resistor required. This will not exceed 2 mA total per device. During transitions, the input signal may overshoot to VDDP +1.0 V for a limited time of no larger than 10% of the duty cycle. During transitions, the input signal may undershoot to -1.0 V for a limited time of no larger than 10% of the duty cycle. v5.2 1-39 ProASICPLUS Flash Family FPGAs Table 1-23 * DC Specifications (3.3 V PCI Operation)1 Commercial/ Industrial2,3 Symbol Parameter VDD Condition Military/MIL-STD- 8832,3 Min. Max. Min. Max. Units Supply Voltage for Core 2.3 2.7 2.3 2.7 V VDDP Supply Voltage for I/O Ring 3.0 3.6 3.0 3.6 V VIH Input High Voltage 0.5VDDP VDDP + 0.5 V VIL Input Low Voltage -0.5 0.3VDDP V 0.5VDDP VDDP + 0.5 -0.5 4 IIPU Input Pull-up Voltage IIL Input Leakage Current5 0.3VDDP 0.7VDDP 0 < VIN < VDDP Std. 3, 6 -F VOH Output High Voltage IOUT = -500 A VOL Output Low Voltage IOUT = 1500 A CIN Input Pin Capacitance (except CLK) CCLK CLK Pin Capacitance 0.7VDDP -10 10 -10 100 0.9VDDP 5 -50 V 50 A A 0.9VDDP V 0.1VDDP 0.1VDDP V 10 10 pF 12 pF 12 5 Notes: 1. 2. 3. 4. For PCI operation, use OTB33PH, OB33PH, IOB33PH, IB33, or IB33S macro library cell only. All process conditions. Junction Temperature: -40 to +110C for Commercial and Industrial devices and -55 to +125C for Military. All -F parts are available as commercial only. This specification is guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Designers with applications sensitive to static power utilization should ensure that the input buffer is conducting minimum current at this input voltage. 5. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 6. The sum of the leakage currents for all inputs shall not exceed 2mA per device. 1 -4 0 v5.2 ProASICPLUS Flash Family FPGAs Table 1-24 * AC Specifications (3.3 V PCI Revision 2.2 Operation) Commercial/Industrial/Military/MIL-STD- 883 Symbol Parameter IOH(AC) IOL(AC) Switching Current High Condition Min. 0 < VOUT 0.3VDDP* 0.3VDDP VOUT < 0.9VDDP* 0.7VDDP < VOUT < VDDP* (Test Point) VOUT = 0.7VDDP* Switching Current Low VDDP > VOUT mA (-17.1 + (VDDP - VOUT)) mA See equation C - page 124 of the PCI Specification document rev. 2.2 -32VDDP 1 mA (26.7VOUT) mA See equation D - page 124 of the PCI Specification document rev. 2.2 (Test Point) VOUT = 0.18VDDP ICL Low Clamp Current -3 < VIN -1 ICH High Clamp Current VDDP + 4 > VIN VDDP + 1 slewF Output Fall Slew Rate mA 16VDDP 0.18VDDP > VOUT > 0* Output Rise Slew Rate Units -12VDDP 0.6VDDP* 0.6VDDP > VOUT > 0.1VDDP slewR Max. 38VDDP mA -25 + (VIN + 1)/0.015 mA 25 + (VIN - VDDP - 1)/0.015 mA 0.2VDDP to 0.6VDDP load* 1 4 V/ns 0.6VDDP to 0.2VDDP load* 1 4 V/ns Note: * Refer to the PCI Specification document rev. 2.2. Pad Loading Applicable to the Rising Edge PCI pin 1/2 in. max output buffer 10 pF 1k Pad Loading Applicable to the Falling Edge PCI pin output buffer 1k 10 pF v5.2 1-41 ProASICPLUS Flash Family FPGAs Tristate Buffer Delays EN A PAD OTBx A 50% 50% VOH PAD VOL EN EN 50% 50% tDLH 35pF tDHL 50% 50% VDDP 50% PAD VOL tENZL 50% 50% VOH PAD GND 10% 90% 50% tENZH Figure 1-26 * Tristate Buffer Delays Table 1-25 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type Description Max tDHL2 Max tENZH3 Max tENZL4 Std. -F Std. -F Std. -F Units OTB33PH 3.3 V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 2.2 2.6 -F Std. 2.0 2.4 ns OTB33PN 3.3 V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 2.4 2.9 2.1 2.5 ns OTB33PL 3.3 V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 2.7 3.3 2.8 3.4 ns OTB33LH 3.3 V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 2.8 3.4 3.0 3.6 ns OTB33LN 3.3 V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 3.2 3.8 4.1 4.9 ns OTB33LL 3.3 V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 3.3 3.9 5.5 6.6 ns Notes: 1. 2. 3. 4. 5. tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low All -F parts are only available as commercial. Table 1-26 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type OTB25LPHH Description 2.5 V, Low Power, High Output Current, High Slew Rate5 5 Max tDHL2 Max tENZH3 Max tENZL4 Std. -F Std. -F Std. -F Units 2.0 2.4 2.1 2.5 2.3 2.7 -F Std. 2.0 2.4 ns 2.4 2.9 3.0 3.6 2.7 3.2 2.1 2.5 ns OTB25LPHL 2.5 V, Low Power, High Output Current, Low Slew Rate5 2.9 3.5 3.2 3.8 3.1 3.8 2.7 3.2 ns OTB25LPLH 2.5 V, Low Power, Low Output Current, High Slew Rate5 2.7 3.3 4.6 5.5 3.0 3.6 2.6 3.1 ns 3.5 4.2 4.2 5.1 3.8 4.5 3.8 4.6 ns 4.0 4.8 5.3 6.4 4.2 5.1 5.1 6.1 ns OTB25LPHN 2.5 V, Low Power, High Output Current, Nominal Slew Rate Rate5 OTB25LPLN 2.5 V, Low Power, Low Output Current, Nominal Slew OTB25LPLL 2.5 V, Low Power, Low Output Current, Low Slew Rate5 Notes: 1. 2. 3. 4. 5. 6. 1 -4 2 tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low Low power I/O work with VDDP=2.5 V 10% only. VDDP=2.3 V for delays. All -F parts are only available as commercial. v5.2 ProASICPLUS Flash Family FPGAs Table 1-27 * Worst-Case Military Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Max tDLH1 Max tDHL2 Max tENZH3 Max tENZL4 Std. Std. Std. Std. Units Macro Type Description OTB33PH 3.3 V, PCI Output Current, High Slew Rate 2.2 2.4 2.3 2.1 ns OTB33PN 3.3 V, High Output Current, Nominal Slew Rate 2.4 3.2 2.7 2.3 ns OTB33PL 3.3 V, High Output Current, Low Slew Rate 2.7 3.5 2.9 3.0 ns OTB33LH 3.3 V, Low Output Current, High Slew Rate 2.7 4.3 3.0 3.1 ns OTB33LN 3.3 V, Low Output Current, Nominal Slew Rate 3.3 4.7 3.4 4.4 ns OTB33LL 3.3 V, Low Output Current, Low Slew Rate 3.2 6.0 3.5 5.9 ns Max tDLH1 Max tDHL2 Max tENZH3 Max tENZL4 Std. Std. Std. Std. Units 2.3 2.3 2.4 2.1 ns Notes: 1. 2. 3. 4. tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low Table 1-28 * Worst-Case Military Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Macro Type Description 5 OTB25LPHH 2.5 V, Low Power, High Output Current, High Slew Rate OTB25LPHN 2.5 V, Low Power, High Output Current, Nominal Slew Rate5 2.7 3.2 2.8 2.1 ns OTB25LPHL 2.5 V, Low Power, High Output Current, Low Slew Rate5 3.2 3.5 3.3 2.8 ns OTB25LPLH Rate5 3.0 5.0 3.2 2.8 ns 3.7 4.5 4.1 4.1 ns 4.4 5.8 4.4 5.4 ns OTB25LPLN OTB25LPLL 2.5 V, Low Power, Low Output Current, High Slew 2.5 V, Low Power, Low Output Current, Nominal Slew Rate 2.5 V, Low Power, Low Output Current, Low Slew Rate 5 5 Notes: 1. 2. 3. 4. 5. tDLH=Data-to-Pad High tDHL=Data-to-Pad Low tENZH=Enable-to-Pad, Z to High tENZL = Enable-to-Pad, Z to Low Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. v5.2 1-43 ProASICPLUS Flash Family FPGAs Output Buffer Delays A 50% 50% VOH 50% PAD 50% VOL tDHL tDLH PAD A 35pF OBx Figure 1-27 * Output Buffer Delays Table 1-29 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type Description Max tDHL2 Std. -F Std. -F Units OB33PH 3.3 V, PCI Output Current, High Slew Rate 2.0 2.4 2.2 2.6 ns OB33PN 3.3 V, High Output Current, Nominal Slew Rate 2.2 2.6 2.9 3.5 ns OB33PL 3.3 V, High Output Current, Low Slew Rate 2.5 3.0 3.2 3.9 ns OB33LH 3.3 V, Low Output Current, High Slew Rate 2.6 3.1 4.0 4.8 ns OB33LN 3.3 V, Low Output Current, Nominal Slew Rate 2.9 3.5 4.3 5.2 ns OB33LL 3.3 V, Low Output Current, Low Slew Rate 3.0 3.6 5.6 6.7 ns Notes: 1. tDLH = Data-to-Pad High 2. tDHL = Data-to-Pad Low 3. All -F parts are only available as commercial. Table 1-30 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, 35 pF load, TJ = 70C Max tDLH1 Macro Type Description Rate3 OB25LPHH 2.5 V, Low Power, High Output Current, High Slew OB25LPHN 2.5 V, Low Power, High Output Current, Nominal Slew Rate3 OB25LPHL OB25LPLH 2.5 V, Low Power, High Output Current, Low Slew Rate 2.5 V, Low Power, Low Output Current, High Slew 3 Rate3 3 Max tDHL2 Std. -F Std. -F Units 2.0 2.4 2.1 2.6 ns 2.4 2.9 3.0 3.6 ns 2.9 3.5 3.2 3.8 ns 2.7 3.3 4.6 5.5 ns OB25LPLN 2.5 V, Low Power, Low Output Current, Nominal Slew Rate 3.5 4.2 4.2 5.1 ns OB25LPLL 2.5 V, Low Power, Low Output Current, Low Slew Rate3 4.0 4.8 5.3 6.4 ns Notes: 1. 2. 3. 4. 1 -4 4 tDLH = Data-to-Pad High tDHL = Data-to-Pad Low Low-power I/Os work with VDDP=2.5 V 10% only. VDDP=2.3 V for delays. All -F parts are only available as commercial. v5.2 ProASICPLUS Flash Family FPGAs Table 1-31 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Max. tDLH1 Max. tDHL2 Std. Std. Units Macro Type Description OB33PH 3.3V, PCI Output Current, High Slew Rate 2.1 2.3 ns OB33PN 3.3V, High Output Current, Nominal Slew Rate 2.5 3.2 ns OB33PL 3.3V, High Output Current, Low Slew Rate 2.7 3.5 ns OB33LH 3.3V, Low Output Current, High Slew Rate 2.7 4.3 ns OB33LN 3.3V, Low Output Current, Nominal Slew Rate 3.3 4.7 ns OB33LL 3.3V, Low Output Current, Low Slew Rate 3.3 6.1 ns Max. tDLH1 Max. tDHL2 Std. Std. Units 2.3 2.4 ns 2.7 3.3 ns 3.2 3.5 ns 3.0 5.0 ns 3.9 4.6 ns 4.3 5.7 ns Notes: 1. tDLH = Data-to-Pad High 2. tDHL = Data-to-Pad Low Table 1-32 * Worst-Case Military Conditions VDDP = 2.3 V, VDD = 2.3V, 35 pF load, TJ = 125C for Military/MIL-STD-883 Macro Type OB25LPHH OB25LPHN Description 2.5V, Low Power, High Output Current, High Slew Rate 3 2.5V, Low Power, High Output Current, Nominal Slew Rate Rate3 OB25LPHL 2.5V, Low Power, High Output Current, Low Slew OB25LPLH 2.5V, Low Power, Low Output Current, High Slew Rate3 OB25LPLN OB25LPLL 2.5V, Low Power, Low Output Current, Nominal Slew Rate 2.5V, Low Power, Low Output Current, Low Slew 3 Rate3 3 Notes: 1. tDLH = Data-to-Pad High 2. tDHL = Data-to-Pad Low 3. Low power I/O work with VDDP=2.5V 10% only. VDDP=2.3V for delays. v5.2 1-45 ProASICPLUS Flash Family FPGAs Input Buffer Delays VDDP PAD Y PAD Y GND IBx 0V 50% 50% VDD 50% tINYH 50% tIN YL Figure 1-28 * Input Buffer Delays Table 1-33 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Macro Type Description Levels3, IB33 3.3 V, CMOS Input IB33S 3.3 V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger No Pull-up Resistor Max. tINYH1 Max. tINYL2 Std. -F Std. -F Units 0.4 0.5 0.6 0.7 ns 0.6 0.7 0.8 0.9 ns Notes: 1. 2. 3. 4. 5. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial. Table 1-34 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, TJ = 70C Macro Type IB25LP IB25LPS Description 2.5 V, CMOS Input Levels3, Low Power 3, 2.5 V, CMOS Input Levels Low Power, Schmitt Trigger Notes: 1. 2. 3. 4. 5. 1 -4 6 tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial. v5.2 Max. tINYH1 Max. tINYL2 Std. -F Std. -F Units 0.9 1.1 0.6 0.8 ns 0.7 0.9 0.9 1.1 ns ProASICPLUS Flash Family FPGAs Table 1-35 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Macro Type Description Levels3 IB33 3.3V, CMOS Input IB33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger , No Pull-up Resistor Max. tINYH1 Max. tINYL2 Std. Std. Units 0.5 0.6 ns 0.6 0.8 ns Max. tINYH1 Max. tINYL2 Std. Std. Units 0.9 0.7 ns 0.8 1.0 ns Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays. Table 1-36 * Worst-Case Military Conditions VDDP = 2.3V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Macro Type IB25LP IB25LPS Description 3, 2.5V, CMOS Input Levels Low Power 2.5V, CMOS Input Levels3, Low Power, Schmitt Trigger Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays. v5.2 1-47 ProASICPLUS Flash Family FPGAs Global Input Buffer Delays Table 1-37 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Max. tINYH1 Macro Type GL33 Description 4 3 Units -F Std. 1.0 1.2 1.1 1.3 ns Std. 3.3 V, CMOS Input Levels4, No Pull-up Resistor 3 Max. tINYL2 -F GL33S 3.3 V, CMOS Input Levels , No Pull-up Resistor, Schmitt Trigger 1.0 1.2 1.1 1.3 ns PECL PPECL Input Levels 1.0 1.2 1.1 1.3 ns Notes: 1. 2. 3. 4. 5. 6. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low Applies to Military ProASICPLUS devices. LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial. Table 1-38 * Worst-Case Commercial Conditions VDDP = 2.3 V, VDD = 2.3 V, TJ = 70C Max. tINYH1 Macro Type Description Std. 4, 3 Max. tINYL2 -F Std.3 -F Units GL25LP 2.5 V, CMOS Input Levels Low Power 1.1 1.2 1.0 1.3 ns GL25LPS 2.5 V, CMOS Input Levels4, Low Power, Schmitt Trigger 1.3 1.6 1.0 1.1 ns Notes: 1. 2. 3. 4. 5. 6. 1 -4 8 tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low Applies to Military ProASICPLUS devices. LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3 V for delays. All -F parts are only available as commercial. v5.2 ProASICPLUS Flash Family FPGAs Table 1-39 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Macro Type Description 3 Max. tINYH1 Max. tINYL2 Std. Std. GL33 3.3V, CMOS Input Levels , No Pull-up Resistor 1.1 1.1 GL33S 3.3V, CMOS Input Levels3, No Pull-up Resistor, Schmitt Trigger 1.1 1.1 PECL PPECL Input Levels 1.1 1.1 Max. tINYH1 Max. tINYL2 Std. Std. 1.0 1.1 1.4 1.0 Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays. Table 1-40 * Worst-Case Military Conditions VDDP = 2.3V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Macro Type GL25LP GL25LPS Description 2.5V, CMOS Input Levels3, Low Power 3, 2.5V, CMOS Input Levels Low Power, Schmitt Trigger Notes: 1. 2. 3. 4. tINYH = Input Pad-to-Y High tINYL = Input Pad-to-Y Low LVTTL delays are the same as CMOS delays. For LP Macros, VDDP=2.3V for delays. v5.2 1-49 ProASICPLUS Flash Family FPGAs Predicted Global Routing Delay Table 1-41 * Worst-Case Commercial Conditions1 VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Max. Std. -F2 Units Input Low to High 3 1.1 1.3 ns Input High to Low 3 1.0 1.2 ns Input Low to High 4 0.8 1.0 ns Input High to Low 4 0.8 1.0 ns Parameter tRCKH tRCKL tRCKH tRCKL Description Notes: 1. 2. 3. 4. The timing delay difference between tile locations is less than 15ps. All -F parts are only available as commercial. Highly loaded row 50%. Minimally loaded row. Table 1-42 * Worst-Case Military Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Parameter Description Max. Units tRCKH Input Low to High (high loaded row of 50%) 1.1 ns tRCKL Input High to Low (high loaded row of 50%) 1.0 ns tRCKH Input Low to High (minimally loaded row) 0.8 ns tRCKL Input High to Low (minimally loaded row) 0.8 ns Note: * The timing delay difference between tile locations is less than 15 ps. Global Routing Skew Table 1-43 * Worst-Case Commercial Conditions VDDP = 3.0 V, VDD = 2.3 V, TJ = 70C Max. Parameter Description Std. -F* Units tRCKSWH Maximum Skew Low to High 270 320 ps tRCKSHH Maximum Skew High to Low 270 320 ps Note: *All -F parts are only available as commercial. Table 1-44 * Worst-Case Commercial Conditions VDDP = 3.0V, VDD = 2.3V, TJ = 125C for Military/MIL-STD-883 Parameter Description Max. Units tRCKSWH Maximum Skew Low to High 270 ps tRCKSHH Maximum Skew High to Low 270 ps 1 -5 0 v5.2 ProASICPLUS Flash Family FPGAs Module Delays A B C A Y 50%50% 50% 50% B C 50%50% 50% Y 50% 50% tDBLH tDALH tDAHL 50% 50% tDCLH 50% tDCHL tDBHL Figure 1-29 * Module Delays Sample Macrocell Library Listing Table 1-45 * Worst-Case Military Conditions1 VDD = 2.3 V, TJ = 70 C, TJ = 70C, TJ = 125C for Military/MIL-STD-883 -F2 Std. Cell Name Description Max Min Max Min Units NAND2 2-Input NAND 0.5 0.6 ns AND2 2-Input AND 0.7 0.8 ns NOR3 3-Input NOR 0.8 1.0 ns MUX2L 2-1 MUX with Active Low Select 0.5 0.6 ns OA21 2-Input OR into a 2-Input AND 0.8 1.0 ns XOR2 2-Input Exclusive OR 0.6 0.8 ns LDL Active Low Latch (LH/HL) LH3 0.9 1.1 HL3 0.8 0.9 CLK-Q DFFL ns ns tsetup 0.7 0.8 ns thold 0.1 0.2 ns Negative Edge-Triggered D-type Flip-Flop (LH/HL) CLK-Q ns LH3 0.9 1.1 HL3 0.8 1.0 ns tsetup 0.6 0.7 ns thold 0.0 0.0 ns Notes: 1. Intrinsic delays have a variable component, coupled to the input slope of the signal. These numbers assume an input slope typical of local interconnect. 2. All -F parts are only available as commercial. 3. LH and HL refer to the Q transitions from Low to High and High to Low, respectively. v5.2 1-51 ProASICPLUS Flash Family FPGAs Table 1-46 * Recommended Operating Conditions Limits Parameter Symbol Commercial/Industrial Military/MIL-STD-883 Maximum Clock Frequency* fCLOCK 180 MHz 180 MHz Maximum RAM Frequency* fRAM 150 MHz 150 MHz Maximum Rise/Fall Time on Inputs* * Schmitt Trigger Mode (10% to 90%) tR/tF N/A 100 ns * Non-Schmitt Trigger Mode (10% to 90%) tR/tF 100 ns 10 ns 180 MHz 180 MHz 10 MHz 10 MHz Maximum LVPECL Frequency* Maximum TCK Frequency (JTAG) fTCK Note: *All -F parts will be 20% slower than standard commercial devices. Table 1-47 * Slew Rates Measured at C = 30pF, Nominal Power Supplies and 25C Type Trig. Level Rising Edge (ns) Slew Rate (V/ns) Falling Edge (ns) Slew Rate (V/ns) PCI Mode OB33PH 10%-90% 1.60 1.65 1.65 1.60 Yes OB33PN 10%-90% 1.57 1.68 3.32 0.80 No OB33PL 10%-90% 1.57 1.68 1.99 1.32 No OB33LH 10%-90% 3.80 0.70 4.84 0.55 No OB33LN 10%-90% 4.19 0.63 3.37 0.78 No OB33LL 10%-90% 5.49 0.48 2.98 0.89 No OB25LPHH 10%-90% 1.55 1.29 1.56 1.28 No OB25LPHN 10%-90% 1.70 1.18 2.08 0.96 No OB25LPHL 10%-90% 1.97 1.02 2.09 0.96 No OB25LPLH 10%-90% 3.57 0.56 3.93 0.51 No OB25LPLN 10%-90% 4.65 0.43 3.28 0.61 No OB25LPLL 10%-90% 5.52 0.36 3.44 0.58 No Notes: 1. Standard and -F parts. 2. All -F only available as commercial. 1 -5 2 v5.2 ProASICPLUS Flash Family FPGAs Table 1-48 * JTAG Switching Characteristics Description Symbol Min Max Unit Output delay from TCK falling to TDI, TMS tTCKTDI -4 4 ns TDO Setup time before TCK rising tTDOTCK 10 TDO Hold time after TCK rising tTCKTDO 0 TCK period tTCK RCK period tRCK 100 ns ns 2 100 1,000 ns 1,000 ns Notes: 1. For DC electrical specifications of the JTAG pins (TCK, TDI, TMS, TDO, TRST), refer to Table 1-21 on page 1-36 when VDDP = 2.5 V and Table 1-22 on page 1-38 when VDDP = 3.3 V. 2. If RCK is being used, there is no minimum on the TCK period. TCK tTCK TMS, TDI tTCKTDI TDO tTDOTCK tTCKTDO Figure 1-30 * JTAG Operation Timing v5.2 1-53 ProASICPLUS Flash Family FPGAs Embedded Memory Specifications This section discusses ProASICPLUS SRAM/FIFO embedded memory and its interface signals, including timing diagrams that show the relationships of signals as they pertain to single embedded memory blocks (Table 1-49). Table 1-12 on page 1-23 shows basic SRAM and FIFO configurations. Simultaneous read and write to the same location must be done with care. On such accesses the DI bus is output to the DO bus. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more information. Enclosed Timing Diagrams--SRAM Mode: * "Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)" section on page 1-55 * "Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined)" section on page 1-56 * "Asynchronous SRAM Write" section on page 1-57 * "Asynchronous SRAM Read, Address Controlled, RDB=0" section on page 1-58 * "Asynchronous SRAM Read, RDB Controlled" section on page 1-59 * "Synchronous SRAM Write" * Embedded Memory Specifications The difference between synchronous transparent and pipeline modes is the timing of all the output signals from the memory. In transparent mode, the outputs will change within the same clock cycle to reflect the data requested by the currently valid access to the memory. If clock cycles are short (high clock speed), the data requires most of the clock cycle to change to valid values (stable signals). Processing of this data in the same clock cycle is nearly impossible. Most designers add registers at all outputs of the memory to push the data processing into the next clock cycle. An entire clock cycle can then be used to process the data. To simplify use of this memory setup, suitable registers have been implemented as part of the memory primitive and are available to the user in the synchronous pipeline mode. In this mode, the output signals will change shortly after the second rising edge, following the initiation of the read access. Table 1-49 * Memory Block SRAM Interface Signals SRAM Signal Bits In/Out Description WCLKS 1 In Write clock used on synchronization on write side RCLKS 1 In Read clock used on synchronization on read side RADDR<0:7> 8 In Read address RBLKB 1 In True read block select (active Low) RDB 1 In True read pulse (active Low) WADDR<0:7> 8 In Write address WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> can be used for parity In WRB 1 In Negative true write pulse DO<0:8> 9 Out Output data bits <0:8>, <8> can be used for parity Out RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) PARODD 1 In Selects Odd parity generation/detect when high, Even when low Note: Not all signals shown are used in all modes. 1 -5 4 v5.2 ProASICPLUS Flash Family FPGAs Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) RCLKS Cycle Start RBD, RBLKB New Valid Address RADDR New Valid Data Out Old Data Out DO RPE tRACS tRDCS tRDCH tRACH tOCH tRPCH tCMH tCML tOCA tRPCA tCCYC Note: The plot shows the normal operation status. Figure 1-31 * Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-50 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 7.5 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 9.5 ns RPCH Old RPE valid from RCLKS 3.0 3.0 Notes ns ns Note: All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-55 ProASICPLUS Flash Family FPGAs Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLKS Cycle Start RDB, RBLKB New Valid Address RADDR DO New Valid Data Out Old Data Out RPE Old RPE Out New RPE Out tOCA tRACS tRACH tRPCH tRDCH tOCH tRDCS tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-32 * Synchronous SRAM Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-51 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = 0C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns OCA New DO access from RCLKS 2.0 ns OCH Old DO valid from RCLKS RACH RADDR hold from RCLKS 0.5 ns RACS RADDR setup to RCLKS 1.0 ns RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 4.0 ns RPCH Old RPE valid from RCLKS 0.75 1.0 Note: All -F speed grade devices are 20% slower than the standard numbers. 1 -5 6 v5.2 ns ns Notes ProASICPLUS Flash Family FPGAs Asynchronous SRAM Write WADDR WRB, WBLKB DI WPE tAWRS tAWRH tDWRH tWPDA tWPDH tDWRS tWRML tWRMH tWRCYC Note: The plot shows the normal operation status. Figure 1-33 * Asynchronous SRAM Write Table 1-52 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx Description Min. Max. Units Notes AWRH WADDR hold from WB 1.0 ns AWRS WADDR setup to WB 0.5 ns DWRH DI hold from WB 1.5 ns DWRS DI setup to WB 0.5 ns PARGEN is inactive. DWRS DI setup to WB 2.5 ns PARGEN is active. WPDA WPE access from DI 3.0 ns WPDH WPE hold from DI WPE is invalid, while PARGEN is active. WRCYC Cycle time 7.5 ns WRMH WB high phase 3.0 ns Inactive WRML WB low phase 3.0 ns Active 1.0 ns Note: All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-57 ProASICPLUS Flash Family FPGAs Asynchronous SRAM Read, Address Controlled, RDB=0 RADDR DO RPE tOAH tRPAH tOAA tRPAA tACYC Note: The plot shows the normal operation status. Figure 1-34 * Asynchronous SRAM Read, Address Controlled, RDB=0 Table 1-53 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883B Symbol txxx Description Min. Units ACYC Read cycle time 7.5 ns OAA New DO access from RADDR stable 7.5 ns OAH Old DO hold from RADDR stable RPAA New RPE access from RADDR stable RPAH Old RPE hold from RADDR stable 3.0 10.0 v5.2 ns ns 3.0 Note: All -F speed grade devices are 20% slower than the standard numbers. 1 -5 8 Max. ns Notes ProASICPLUS Flash Family FPGAs Asynchronous SRAM Read, RDB Controlled RB=(RDB+RBLKB) DO RPE tORDH tRPRDH tORDA tRPRDA tRDML tRDMH tRDCYC Note: The plot shows the normal operation status. Figure 1-35 * Asynchronous SRAM Read, RDB Controlled Table 1-54 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes ORDA New DO access from RB ORDH Old DO valid from RB RDCYC Read cycle time 7.5 ns RDMH RB high phase 3.0 ns Inactive setup to new cycle RDML RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 ns RPRDH Old RPE valid from RB 7.5 ns 3.0 3.0 ns ns Note: All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-59 ProASICPLUS Flash Family FPGAs Synchronous SRAM Write WCLKS Cycle Start WRB, WBLKB WADDR, DI WPE tWRCH, tWBCH tWRCS, tWBCS tDCS, tWDCS tWPCH tDCH, tWACH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-36 * Synchronous SRAM Write Table 1-55 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS 0.5 ns DCS DI setup to WCLKS 1.0 ns WACH WADDR hold from WCLKS 0.5 ns WDCS WADDR setup to WCLKS 1.0 ns WPCA New WPE access from WCLKS 3.0 ns WPE is invalid while WPCH Old WPE valid from WCLKS ns PARGEN is active WRCH, WBCH WRB & WBLKB hold from WCLKS WRCS, WBCS WRB & WBLKB setup to WCLKS 0.5 0.5 ns 1.0 ns Notes: 1. On simultaneous read and write accesses to the same location, DI is output to DO. 2. All -F speed grade devices are 20% slower than the standard numbers. 1 -6 0 v5.2 ProASICPLUS Flash Family FPGAs Synchronous Write and Read to the Same Location tCCYC tCMH tCML RCLKS DO New Data* Last Cycle Data WCLKS t WCLKRCLKH t WCLKRCLKS tOCH tOCA * New data is read if WCLKS occurs before setup time. The data stored is read if WCLKS occurs after hold time. Note: The plot shows the normal operation status. Figure 1-37 * Synchronous Write and Read to the Same Location Table 1-56 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WCLKRCLKS WCLKS to RCLKS setup time - 0.1 ns WCLKRCLKH WCLKS to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS 7.5 ns Notes OCA/OCH displayed for Access Timed Output Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. During synchronous write and synchronous read access to the same location, the new write data will be read out if the active write clock edge occurs before or at the same time as the active read clock edge. The negative setup time insures this behavior for WCLKS and RCLKS driven by the same design signal. 3. If WCLKS changes after the hold time, the data will be read. 4. A setup or hold time violation will result in unknown output data. 5. All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-61 ProASICPLUS Flash Family FPGAs Asynchronous Write and Synchronous Read to the Same Location t CMH t CML RCLKS New Data* DO Last Cycle Data WB = {WRB + WBLKB} DI t WRCKS t BRCLKH t OCH t OCA t DWRRCLKS t DWRH tCCYC * New data is read if WB occurs before setup time. The stored data is read if WB occurs after hold time. Note: The plot shows the normal operation status. Figure 1-38 * Asynchronous Write and Synchronous Read to the Same Location Table 1-57 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns WBRCLKS WB to RCLKS setup time -0.1 ns WBRCLKH WB to RCLKS hold time 7.0 ns OCH Old DO valid from RCLKS 3.0 ns OCA New DO valid from RCLKS DWRRCLKS DI to RCLKS setup time DWRH DI to WB hold time 7.5 ns 0 ns 1.5 Notes OCA/OCH displayed Access Timed Output for ns Notes: 1. This behavior is valid for Access Timed Output and Pipelined Mode Output. The table shows the timings of an Access Timed Output. 2. In asynchronous write and synchronous read access to the same location, the new write data will be read out if the active write signal edge occurs before or at the same time as the active read clock edge. If WB changes to low after hold time, the data will be read. 3. A setup or hold time violation will result in unknown output data. 4. All -F speed grade devices are 20% slower than the standard numbers. 1 -6 2 v5.2 ProASICPLUS Flash Family FPGAs Asynchronous Write and Read to the Same Location RB, RADDR DO NEW OLD NEWER WB = {WRB+WBLKB} tORDA tRAWRH tORDH tRAWRS tOWRA tOWRH Note: The plot shows the normal operation status. Figure 1-39 * Asynchronous Write and Read to the Same Location Table 1-58 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WB OWRH Old DO valid from WB RAWRS RB or RADDR from WB 5.0 ns RAWRH RB or RADDR from WB 5.0 ns 7.5 Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. Refer to the ProASICPLUS RAM and FIFO Blocks application note for more information. 2. Violation or RAWRS will disturb access to the OLD data. 3. Violation of RAWRH will disturb access to the NEWER data. 4. All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-63 ProASICPLUS Flash Family FPGAs Synchronous Write and Asynchronous Read to the Same Location RB, RADDR DO NEW OLD NEWER WCLKS t ORDA t RAWCLKH t ORDH t OWRA t OWRH t RAWCLKS Note: The plot shows the normal operation status. Figure 1-40 * Synchronous Write and Asynchronous Read to the Same Location Table 1-59 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units ORDA New DO access from RB ORDH Old DO valid from RB OWRA New DO access from WCLKS OWRH Old DO valid from WCLKS RAWCLKS RB or RADDR from WCLKS 5.0 ns RAWCLKH RB or RADDR from WCLKS 5.0 ns 7.5 Notes ns 3.0 3.0 ns ns 0.5 ns Notes: 1. During an asynchronous read cycle, each write operation (synchronous or asynchronous) to the same location will automatically trigger a read operation which updates the read data. 2. Violation of RAWCLKS will disturb access to OLD data. 3. Violation of RAWCLKH will disturb access to NEWER data. 4. All -F speed grade devices are 20% slower than the standard numbers. 1 -6 4 v5.2 ProASICPLUS Flash Family FPGAs Asynchronous FIFO Full and Empty Transitions The asynchronous FIFO accepts writes and reads while not full or not empty. When the FIFO is full, all writes are inhibited. Conversely, when the FIFO is empty, all reads are inhibited. A problem is created if the FIFO is written to during the transition from full to not full, or read during the transition from empty to not empty. The exact time at which the write or read operation changes from inhibited to accepted after the read (write) signal which causes the transition from full or empty to not full or not empty is indeterminate. For slow cycles, this indeterminate period starts 1 ns after the RB (WB) transition, which deactivates full or not empty and ends 3 ns after the RB (WB) transition. For fast cycles, the indeterminate period ends 3 ns (7.5 ns - RDL (WRL)) after the RB (WB) transition, whichever is later (Table 1-1 on page 1-7). The timing diagram for write is shown in Figure 1-38 on page 1-62. The timing diagram for read is shown in Figure 1-39 on page 1-63. For basic SRAM configurations, see Table 1-13 on page 1-24. When reset is asserted, the empty flag will be asserted, the counters will reset, the outputs go to zero, but the internal RAM is not erased. Enclosed Timing Diagrams - FIFO Mode: * "Asynchronous FIFO Read" section on page 1-67 * "Asynchronous FIFO Write" section on page 1-68 * "Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent)" section on page 1-69 * "Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined)" section on page 1-70 * "Synchronous FIFO Write" section on page 1-71 * "FIFO Reset" section on page 1-72 Table 1-60 * Memory Block FIFO Interface Signals FIFO Signal Bits In/Out Description WCLKS 1 In Write clock used for synchronization on write side RCLKS 1 In Read clock used for synchronization on read side LEVEL <0:7>* 8 In Direct configuration implements static flag logic RBLKB 1 In Read block select (active Low) RDB 1 In Read pulse (active Low) RESET 1 In Reset for FIFO pointers (active Low) WBLKB 1 In Write block select (active Low) DI<0:8> 9 In Input data bits <0:8>, <8> will be generated if PARGEN is true WRB 1 In Write pulse (active Low) FULL, EMPTY 2 Out FIFO flags. FULL prevents write and EMPTY prevents read EQTH, GEQTH* 2 Out EQTH is true when the FIFO holds the number of words specified by the LEVEL signal. GEQTH is true when the FIFO holds (LEVEL) words or more DO<0:8> 9 Out Output data bits <0:8> RPE 1 Out Read parity error (active High) WPE 1 Out Write parity error (active High) LGDEP <0:2> 3 In Configures DEPTH of the FIFO to 2 (LGDEP+1) PARODD 1 In Selects Odd parity generation/detect when high, Even when low Note: *LEVEL is always eight bits (0000.0000, 0000.0001). That means for values of DEPTH greater than 256, not all values will be possible, e.g. for DEPTH=512, the LEVEL can only have the values 2, 4, . . ., 512. The LEVEL signal circuit will generate signals that indicate whether the FIFO is exactly filled to the value of LEVEL (EQTH) or filled equal or higher (GEQTH) than the specified LEVEL. Since counting starts at 0, EQTH will become true when the FIFO holds (LEVEL+1) words for 512-bit FIFOs. v5.2 1-65 ProASICPLUS Flash Family FPGAs FULL RB Write cycle Write inhibited Write accepted 1 ns 3 ns WB Note: All -F speed grade devices are 20% slower than the standard numbers. Figure 1-41 * Write Timing Diagram EMPTY WB Read cycle Read inhibited Read accepted 1 ns 3 ns RB Note: All -F speed grade devices are 20% slower than the standard numbers. Figure 1-42 * Read Timing Diagram 1 -6 6 v5.2 ProASICPLUS Flash Family FPGAs Asynchronous FIFO Read tRPRDA tRDL Cycle Start tRDH RB = (RDB+RBLKB) (Empty inhibits read) RDATA RPE WB EMPTY FULL EQTH, GETH tRDWRS tERDH, tFRDH tORDH tERDA, tFRDA tRPRDH tTHRDH tTHRDA tORDA tRPRDA tRDL tRDH tRDCYC Note: The plot shows the normal operation status. Figure 1-43 * Asynchronous FIFO Read Table 1-61 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. ERDH, FRDH, Old EMPTY, FULL, EQTH, & GETH valid hold THRDH time from RB ERDA New EMPTY access from RB FRDA Max. Units Notes 0.5 ns Empty/full/thresh are invalid from the end of hold until the new access is complete 3.01 ns FULL access from RB 1 3.0 ns ORDA New DO access from RB 7.5 ns ORDH Old DO valid from RB RDCYC Read cycle time RDWRS WB , clearing EMPTY, setup to RB 3.0 RDH RB high phase RDL 3.0 7.5 ns ns 2 ns Enabling the read operation ns Inhibiting the read operation 3.0 ns Inactive RB low phase 3.0 ns Active RPRDA New RPE access from RB 9.5 ns RPRDH Old RPE valid from RB THRDA EQTH or GETH access from RB 1.0 4.0 4.5 ns ns Notes: 1. At fast cycles, ERDA and FRDA = MAX (7.5 ns - RDL), 3.0 ns. 2. At fast cycles, RDWRS (for enabling read) = MAX (7.5 ns - WRL), 3.0 ns. 3. All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-67 ProASICPLUS Flash Family FPGAs Asynchronous FIFO Write Cycle Start WB = (WRB+WBLKB) WDATA (Full inhibits write) WPE RB FULL EMPTY EQTH, GETH tWRRDS tDWRH tWPDH tWPDA tDWRS tEWRH, tFWRH tEWRA, tFWRA tTHWRH tTHWRA tWRL tWRH tWRCYC Note: The plot shows the normal operation status. Figure 1-44 * Asynchronous FIFO Write Table 1-62 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Description Symbol txxx Min. Max. Units Notes DWRH DI hold from WB 1.5 DWRS DI setup to WB 0.5 ns PARGEN is inactive DWRS DI setup to WB 2.5 ns PARGEN is active ns Empty/full/thresh are invalid from the end of hold until the new access is complete EWRH, FWRH, Old EMPTY, FULL, EQTH, & GETH valid hold THWRH time after WB ns 0.5 EWRA EMPTY access from WB 3.01 ns FWRA New FULL access from WB 3.01 ns THWRA EQTH or GETH access from WB 4.5 ns WPDA WPE access from DI 3.0 ns WPDH WPE hold from DI WRCYC Cycle time 7.5 WRRDS RB , clearing FULL, setup to WB 3.02 1.0 WPE is invalid while PARGEN is active ns ns ns 1.0 Enabling the write operation Inhibiting the write operation WRH WB high phase 3.0 ns Inactive WRL WB low phase 3.0 ns Active Notes: 1. 2. 3. 4. 1 -6 8 At fast cycles, EWRA, FWRA = MAX (7.5 ns - WRL), 3.0 ns. At fast cycles, WRRDS (for enabling write) = MAX (7.5 ns - RDL), 3.0 ns. All -F speed grade devices are 20% slower than the standard numbers. After FIFO reset, WRB needs an initial falling edge prior to any write actions. v5.2 ProASICPLUS Flash Family FPGAs Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) RCLK Cycle Start RDB RDATA Old Data Out New Valid Data Out (Empty Inhibits Read) RPE EMPTY FULL EQTH, GETH tRDCH tECBH, tFCBH tECBA, tFCBA tRDCS tTHCBH tOCH tRPCH tHCBA tOCA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-45 * Synchronous FIFO Read, Access Timed Output Strobe (Synchronous Transparent) Table 1-63 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Description Symbol txxx Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS 3.01 ns FCBA FULL access from RCLKS 3.01 ns ECBH, FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold THCBH time from RCLKS 1.0 ns OCA New DO access from RCLKS OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 9.5 ns RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 7.5 Notes Empty/full/thresh are invalid from the end of hold until the new access is complete ns 3.0 3.0 4.5 ns ns ns Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-69 ProASICPLUS Flash Family FPGAs Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) RCLK Cycle Start RDB RDATA Old Data Out RPE New Valid Data Out Old RPE Out New RPE Out EMPTY FULL EQTH, GETH tECBH, tFCBH tOCA tRDCH tECBA, tFCBA tTHCBH tRDCS tRPCH tOCH tHCBA tRPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-46 * Synchronous FIFO Read, Pipeline Mode Outputs (Synchronous Pipelined) Table 1-64 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns ECBA New EMPTY access from RCLKS 3.01 ns FCBA FULL access from RCLKS 1 ns ECBH, THCBH 3.0 FCBH, Old EMPTY, FULL, EQTH, & GETH valid hold time from RCLKS 1.0 ns OCA New DO access from RCLKS OCH Old DO valid from RCLKS RDCH RDB hold from RCLKS 0.5 ns RDCS RDB setup to RCLKS 1.0 ns RPCA New RPE access from RCLKS 4.0 ns RPCH Old RPE valid from RCLKS HCBA EQTH or GETH access from RCLKS 2.0 ns 0.75 1.0 4.5 Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMS), 3.0 ns. 2. All -F speed grade devices are 20% slower than the standard numbers. 1 -7 0 v5.2 ns ns ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete ProASICPLUS Flash Family FPGAs Synchronous FIFO Write WCLKS Cycle Start WRB, WBLKB (Full Inhibits Write) DI WPE FULL EMPTY EQTH, GETH tWRCH, tWBCH tECBH, tFCBH tECBA, tFCBA tWRCS, tWBCS tDCS tHCBH tHCBA tWPCH tDCH tWPCA tCMH tCML tCCYC Note: The plot shows the normal operation status. Figure 1-47 * Synchronous FIFO Write Table 1-65 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units CCYC Cycle time 7.5 ns CMH Clock high phase 3.0 ns CML Clock low phase 3.0 ns DCH DI hold from WCLKS 0.5 ns DCS DI setup to WCLKS 1.0 ns FCBA New FULL access from WCLKS 3.01 ns ECBA EMPTY access from WCLKS 3.01 ns ECBH, FCBH, HCBH Old EMPTY, FULL, EQTH, & GETH valid hold time from WCLKS HCBA EQTH or GETH access from WCLKS 4.5 ns WPCA New WPE access from WCLKS 3.0 ns WPCH Old WPE valid from WCLKS WRCH, WBCH WRB & WBLKB hold from WCLKS WRCS, WBCS WRB & WBLKB setup to WCLKS 1.0 0.5 ns Notes Empty/full/thresh are invalid from the end of hold until the new access is complete WPE is invalid, while PARGEN is active ns 0.5 ns 1.0 ns Notes: 1. At fast cycles, ECBA and FCBA = MAX (7.5 ns - CMH), 3.0 ns. 2. All -F speed grade devices are 20% slower than the standard numbers. v5.2 1-71 ProASICPLUS Flash Family FPGAs FIFO Reset RESETB Cycle Start WRB/RBD1 WCLKS, RCLKS1 Cycle Start FULL EMPTY EQTH, GETH tCBRSS tERSA, tFRSA tCBRSH tWBRSH tTHRSA tRSL tWBRSS Notes: 1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low. 2. The plot shows the normal operation status. Figure 1-48 * FIFO Reset Table 1-66 * TJ = 0C to 110C; VDD = 2.3 V to 2.7 V for Commercial/industrial TJ = -55C to 150C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883 Symbol txxx Description Min. Max. Units Notes CBRSH1 WCLKS or RCLKS hold from RESETB 1.5 ns Synchronous mode only CBRSS1 WCLKS or RCLKS setup to RESETB 1.5 ns Synchronous mode only ERSA New EMPTY access from RESETB 3.0 ns FRSA FULL access from RESETB 3.0 ns RSL RESETB low phase 7.5 ns EQTH or GETH access from RESETB 4.5 ns 1 WB hold from RESETB 1.5 ns Asynchronous mode only 1 WB setup to RESETB 1.5 ns Asynchronous mode only THRSA WBRSH WBRSS Notes: 1. During rest, the enables (WRB and RBD) must be high OR the clocks (WCLKS and RCKLS) must be low. 2. All -F speed grade devices are 20% slower than the standard numbers. 1 -7 2 v5.2 ProASICPLUS Flash Family FPGAs Pin Description TMS The TMS pin controls the use of boundary-scan circuitry. This pin has an internal pull-up resistor. User Pins I/O TCK User Input/Output TDI No Connect TDO Global Pin TRST Global Multiplexing Pin Special Function Pins RCK In applications where two different signals access the same global net at different times through the use of GLMXx and GLMXLx macros, this pin will be fixed as one of the source pins. NPECL User Negative Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as any normal I/O. If not used, the GLMXx pin will be configured as an input with pull-up. PPECL User Positive Input Provides high speed clock or data signals to the PLL block. If unused, leave the pin unconnected. AVDD PLL Power Supply Analog VDD should be VDD (core voltage) 2.5 V (nominal) and be decoupled from GND with suitable decoupling capacitors to reduce noise. For more information, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. If the clock conditioning circuitry is not used in a design, AVDD can either be left floating or tied to 2.5 V. Dedicated Pins Ground Common ground supply voltage. Logic Array Power Supply Pin 2.5 V supply voltage. VDDP Running Clock A free running clock is needed during programming if the programmer cannot guarantee that TCK will be uninterrupted. If not used, this pin has an internal pullup and can be left floating. When the external feedback option is selected for the PLL block, this pin is routed as the external feedback source to the clock conditioning circuit. VDD Test Reset Input Asynchronous, active-low input pin for resetting boundary-scan circuitry. This pin has an internal pull-up resistor. For more information, please refer to Power-up Behavior of ProASICPLUS Devices application note. Low skew input pin for clock or other global signals. This pin can be used in one of two special ways (refer to Actel's Using ProASICPLUS Clock Conditioning Circuits). GND Test Data Out Serial output for boundary scan. Actel recommends adding a nominal 20k pull-up resistor to this pin. Low skew input pin for clock or other global signals. This pin can be configured with an internal pull-up resistor. When it is not connected to the global network or the clock conditioning circuit, it can be configured and used as a normal I/O. GLMX Test Data In Serial input for boundary scan. A dedicated pull-up resistor is included to pull this pin high when not being driven. To maintain compatibility with other Actel ProASICPLUS products, it is recommended that this pin not be connected to the circuitry on the board. GL Test Clock Clock input pin for boundary scan (maximum 10 MHz). Actel recommends adding a nominal 20 k pull-up resistor to this pin. The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with standard LVTTL and LVCMOS specifications. Unused I/O pins are configured as inputs with pull-up resistors. NC Test Mode Select AGND I/O Pad Power Supply Pin PLL Power Ground The analog ground can be connected to the system ground. For more information, refer to Actel's Using ProASICPLUS Clock Conditioning Circuits application note. If the PLLs or clock conditioning circuitry are not used in a design, AGND should be tied to GND. 2.5 V or 3.3 V supply voltage. v5.2 1-73 ProASICPLUS Flash Family FPGAs VPP Programming Supply Pin This pin may be connected to any voltage between GND and 16.5 V during normal operation, or it can be left unconnected.2 For information on using this pin during programming, see the In-System Programming ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to VDDP. VPN Programming Supply Pin finite length conductors that distribute the power to the device. This can be accomplished by providing sufficient bypass capacitance between the VPP and VPN pins and GND (using the shortest paths possible). Without sufficient bypass capacitance to counteract the inductance, the VPP and VPN pins may incur a voltage spike beyond the voltage that the device can withstand. This issue applies to all programming configurations. Recommended Design Practice for VPN/VPP The solution prevents spikes from damaging the ProASICPLUS devices. Bypass capacitors are required for the VPP and VPN pads. Use a 0.01 F to 0.1 F ceramic capacitor with a 25 V or greater rating. To filter lowfrequency noise (decoupling), use a 4.7 F (low ESR, <1 <, tantalum, 25 V or greater rating) capacitor. The capacitors should be located as close to the device pins as possible (within 2.5 cm is desirable). The smaller, highfrequency capacitor should be placed closer to the device pins than the larger low-frequency capacitor. The same dual-capacitor circuit should be used on both the VPP and VPN pins (Figure 1-49). ProASICPLUS Devices - APA450, APA600, APA750, APA1000 ProASICPLUS Devices - APA075, APA150, APA300 Bypass capacitors are required from VPP to GND and VPN to GND for all ProASICPLUS devices during programming. During the erase cycle, ProASICPLUS devices may have current surges on the VPP and VPN power supplies. The only way to maintain the integrity of the power distribution to the ProASICPLUS device during these current surges is to counteract the inductance of the These devices do not require bypass capacitors on the VPP and VPN pins as long as the total combined distance of the programming cable and the trace length on the board is less than or equal to 30 inches. Note: For trace lengths greater than 30 inches, use the bypass capacitor recommendations in the previous section. This pin may be connected to any voltage between 0.5V and -13.8 V during normal operation, or it can be left unconnected.3 For information on using this pin during programming, see the In-System Programming ProASICPLUS Devices application note. Actel recommends floating the pin or connecting it to GND. 2.5cm + _ V PP 0.1F to 0.01F Actel PLUS ProASIC Device 4.7F + _ + V PN 0.1F to 0.01F 4.7F + Figure 1-49 * ProASICPLUS VPP and VPN Capacitor Requirements 2. There is a nominal 40 k pull-up resistor on VPP. 3. There is a nominal 40 k pull-down resistor on VPN. 1 -7 4 Programming Header or Supplies v5.2 ProASICPLUS Flash Family FPGAs Package Pin Assignments 100-Pin TQFP 1 100 100-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-1 ProASICPLUS Flash Family FPGAs 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Pin Number APA075 Function APA150 Function Pin Number APA075 Function APA150 Function Pin Number APA075 Function APA150 Function 1 GND GND 36 I/O I/O 71 I/O I/O 2 I/O I/O 37 VDD VDD 72 I/O I/O 3 I/O I/O 38 GND GND 73 I/O I/O 4 I/O I/O 39 VDDP VDDP 74 I/O I/O 5 I/O I/O 40 GND GND 75 GND GND 6 I/O I/O 41 I/O I/O 76 VDDP VDDP 7 I/O I/O 42 I/O I/O 77 I/O I/O 8 I/O I/O 43 I/O I/O 78 I/O I/O 9 GND GND 44 I/O I/O 79 I/O I/O 10 I/O / GLMX1 I/O / GLMX1 45 I/O I/O 80 I/O I/O 11 I/O / GL1 I/O / GL1 46 I/O I/O 81 I/O I/O 12 AGND AGND 47 TCK TCK 82 I/O I/O 13 NPECL1 NPECL1 48 TDI TDI 83 I/O I/O 14 AVDD AVDD 49 TMS TMS 84 I/O I/O 50 VDDP VDDP 85 I/O I/O 15 2 -2 PPECL1 / Input PPECL1 / Input 16 I/O / GL2 I/O / GL2 51 GND GND 86 GND GND 17 VDD VDD 52 VPP VPP 87 VDDP VDDP 18 I/O I/O 53 VPN VPN 88 GND GND 19 I/O I/O 54 TDO TDO 89 VDD VDD 20 I/O I/O 55 TRST TRST 90 I/O I/O 21 I/O I/O 56 RCK RCK 91 I/O I/O 22 I/O I/O 57 I/O I/O 92 I/O I/O 23 I/O I/O 58 I/O I/O 93 I/O I/O 24 I/O I/O 59 I/O I/O 94 I/O I/O 25 GND GND 60 I/O / GL3 I/O / GL3 95 I/O I/O 26 VDDP VDDP 61 96 I/O I/O 27 I/O I/O 62 AVDD AVDD 97 I/O I/O 28 I/O I/O 63 NPECL2 NPECL2 98 I/O I/O 29 I/O I/O 64 AGND AGND 99 I/O I/O 30 I/O I/O 65 I/O / GL4 I/O / GL4 100 VDDP VDDP 31 I/O I/O 66 I/O / GLMX2 I/O / GLMX2 32 I/O I/O 67 GND GND 33 I/O I/O 68 VDD VDD 34 I/O I/O 69 I/O I/O 35 I/O I/O 70 I/O I/O PPECL2 / Input PPECL2 / Input v5.2 ProASICPLUS Flash Family FPGAs 144-Pin TQFP 144 1 144-Pin TQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-3 ProASICPLUS Flash Family FPGAs 144-Pin TQFP 144-Pin TQFP 144-Pin TQFP 144-Pin TQFP Pin Number APA075 Function Pin Number APA075 Function Pin Number APA075 Function Pin Number APA075 Function 1 I/O 37 I/O 74 VPN 110 I/O 2 I/O 38 I/O 75 TDO 111 I/O 3 I/O 39 I/O 76 TRST 112 I/O 4 I/O 40 I/O 77 RCK 113 I/O 5 I/O 41 I/O 78 I/O 114 I/O 6 I/O 42 I/O 79 I/O 115 I/O 7 I/O 43 I/O 80 I/O 116 I/O 8 I/O 44 I/O 81 VDDP 117 VDDP 9 VDD 45 VDD 82 GND 118 GND 10 GND 46 GND 83 I/O 119 VDD 11 VDDP 47 VDDP 84 I/O 120 I/O 12 I/O 48 I/O 85 I/O 121 I/O 13 I/O 49 I/O 86 I/O 122 I/O 14 I/O 50 I/O 87 I/O 123 I/O 15 I/O / GLMX1 51 I/O 88 I/O / GL3 124 I/O 16 I/O / GL1 52 I/O 89 125 I/O 17 AGND 53 I/O PPECL2 / Input 126 I/O 90 AVDD 127 I/O 91 NPECL 128 I/O 92 AGND 129 I/O 93 I/O / GL4 130 I/O 94 I/O / GLMX2 131 I/O 95 I/O 132 I/O 96 I/O 133 I/O 97 I/O 134 98 VDDP VDDP 135 GND 99 GND 136 100 VDD VDD 137 I/O 101 I/O 138 I/O 102 I/O 139 I/O 103 I/O 140 I/O 104 I/O 141 I/O 105 I/O 142 I/O 106 I/O 143 I/O 107 I/O 144 I/O 108 I/O 109 I/O 18 19 20 2 -4 NPECL AVDD PPECL1 / Input 21 I/O / GL2 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 GND 28 VDDP 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 I/O I/O I/O I/O I/O I/O I/O I/O VDD GND VDDP I/O I/O I/O I/O TCK TDI TMS 72 NC 73 VPP v5.2 ProASICPLUS Flash Family FPGAs 208-Pin PQFP 1 208 208-Pin PQFP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-5 ProASICPLUS Flash Family FPGAs 208-Pin PQFP 2 -6 Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 1 GND GND GND GND GND GND GND 2 I/O I/O I/O I/O I/O I/O I/O 3 I/O I/O I/O I/O I/O I/O I/O 4 I/O I/O I/O I/O I/O I/O I/O 5 I/O I/O I/O I/O I/O I/O I/O 6 I/O I/O I/O I/O I/O I/O I/O 7 I/O I/O I/O I/O I/O I/O I/O 8 I/O I/O I/O I/O I/O I/O I/O 9 I/O I/O I/O I/O I/O I/O I/O 10 I/O I/O I/O I/O I/O I/O I/O 11 I/O I/O I/O I/O I/O I/O I/O 12 I/O I/O I/O I/O I/O I/O I/O 13 I/O I/O I/O I/O I/O I/O I/O 14 I/O I/O I/O I/O I/O I/O I/O 15 I/O I/O I/O I/O I/O I/O I/O 16 VDD VDD VDD VDD VDD VDD VDD 17 GND GND GND GND GND GND GND 18 I/O I/O I/O I/O I/O I/O I/O 19 I/O I/O I/O I/O I/O I/O I/O 20 I/O I/O I/O I/O I/O I/O I/O 21 I/O I/O I/O I/O I/O I/O I/O 22 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 23 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 24 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 25 AGND AGND AGND AGND AGND AGND AGND 26 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 27 AVDD AVDD AVDD AVDD AVDD AVDD AVDD 28 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input 29 GND GND GND GND GND GND GND 30 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 31 I/O I/O I/O I/O I/O I/O I/O 32 I/O I/O I/O I/O I/O I/O I/O 33 I/O I/O I/O I/O I/O I/O I/O 34 I/O I/O I/O I/O I/O I/O I/O 35 I/O I/O I/O I/O I/O I/O I/O v5.2 ProASICPLUS Flash Family FPGAs 208-Pin PQFP Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 36 VDD VDD VDD VDD VDD VDD VDD 37 I/O I/O I/O I/O I/O I/O I/O 38 I/O I/O I/O I/O I/O I/O I/O 39 I/O I/O I/O I/O I/O I/O I/O 40 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 41 GND GND GND GND GND GND GND 42 I/O I/O I/O I/O I/O I/O I/O 43 I/O I/O I/O I/O I/O I/O I/O 44 I/O I/O I/O I/O I/O I/O I/O 45 I/O I/O I/O I/O I/O I/O I/O 46 I/O I/O I/O I/O I/O I/O I/O 47 I/O I/O I/O I/O I/O I/O I/O 48 I/O I/O I/O I/O I/O I/O I/O 49 I/O I/O I/O I/O I/O I/O I/O 50 I/O I/O I/O I/O I/O I/O I/O 51 I/O I/O I/O I/O I/O I/O I/O 52 GND GND GND GND GND GND GND 53 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 54 I/O I/O I/O I/O I/O I/O I/O 55 I/O I/O I/O I/O I/O I/O I/O 56 I/O I/O I/O I/O I/O I/O I/O 57 I/O I/O I/O I/O I/O I/O I/O 58 I/O I/O I/O I/O I/O I/O I/O 59 I/O I/O I/O I/O I/O I/O I/O 60 I/O I/O I/O I/O I/O I/O I/O 61 I/O I/O I/O I/O I/O I/O I/O 62 I/O I/O I/O I/O I/O I/O I/O 63 I/O I/O I/O I/O I/O I/O I/O 64 I/O I/O I/O I/O I/O I/O I/O 65 GND GND GND GND GND GND GND 66 I/O I/O I/O I/O I/O I/O I/O 67 I/O I/O I/O I/O I/O I/O I/O 68 I/O I/O I/O I/O I/O I/O I/O 69 I/O I/O I/O I/O I/O I/O I/O 70 I/O I/O I/O I/O I/O I/O I/O v5.2 2-7 ProASICPLUS Flash Family FPGAs 208-Pin PQFP 2 -8 Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 71 VDD VDD VDD VDD VDD VDD VDD 72 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 73 I/O I/O I/O I/O I/O I/O I/O 74 I/O I/O I/O I/O I/O I/O I/O 75 I/O I/O I/O I/O I/O I/O I/O 76 I/O I/O I/O I/O I/O I/O I/O 77 I/O I/O I/O I/O I/O I/O I/O 78 I/O I/O I/O I/O I/O I/O I/O 79 I/O I/O I/O I/O I/O I/O I/O 80 I/O I/O I/O I/O I/O I/O I/O 81 GND GND GND GND GND GND GND 82 I/O I/O I/O I/O I/O I/O I/O 83 I/O I/O I/O I/O I/O I/O I/O 84 I/O I/O I/O I/O I/O I/O I/O 85 I/O I/O I/O I/O I/O I/O I/O 86 I/O I/O I/O I/O I/O I/O I/O 87 I/O I/O I/O I/O I/O I/O I/O 88 VDD VDD VDD VDD VDD VDD VDD 89 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 90 I/O I/O I/O I/O I/O I/O I/O 91 I/O I/O I/O I/O I/O I/O I/O 92 I/O I/O I/O I/O I/O I/O I/O 93 I/O I/O I/O I/O I/O I/O I/O 94 I/O I/O I/O I/O I/O I/O I/O 95 I/O I/O I/O I/O I/O I/O I/O 96 I/O I/O I/O I/O I/O I/O I/O 97 GND GND GND GND GND GND GND 98 I/O I/O I/O I/O I/O I/O I/O 99 I/O I/O I/O I/O I/O I/O I/O 100 I/O I/O I/O I/O I/O I/O I/O 101 TCK TCK TCK TCK TCK TCK TCK 102 TDI TDI TDI TDI TDI TDI TDI 103 TMS TMS TMS TMS TMS TMS TMS 104 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 105 GND GND GND GND GND GND GND v5.2 ProASICPLUS Flash Family FPGAs 208-Pin PQFP Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 106 VPP VPP VPP VPP VPP VPP VPP 107 VPN VPN VPN VPN VPN VPN VPN 108 TDO TDO TDO TDO TDO TDO TDO 109 TRST TRST TRST TRST TRST TRST TRST 110 RCK RCK RCK RCK RCK RCK RCK 111 I/O I/O I/O I/O I/O I/O I/O 112 I/O I/O I/O I/O I/O I/O I/O 113 I/O I/O I/O I/O I/O I/O I/O 114 I/O I/O I/O I/O I/O I/O I/O 115 I/O I/O I/O I/O I/O I/O I/O 116 I/O I/O I/O I/O I/O I/O I/O 117 I/O I/O I/O I/O I/O I/O I/O 118 I/O I/O I/O I/O I/O I/O I/O 119 I/O I/O I/O I/O I/O I/O I/O 120 I/O I/O I/O I/O I/O I/O I/O 121 I/O I/O I/O I/O I/O I/O I/O 122 GND GND GND GND GND GND GND 123 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 124 I/O I/O I/O I/O I/O I/O I/O 125 I/O I/O I/O I/O I/O I/O I/O 126 VDD VDD VDD VDD VDD VDD VDD 127 I/O I/O I/O I/O I/O I/O I/O 128 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 129 PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input 130 GND GND GND GND GND GND GND 131 AVDD AVDD AVDD AVDD AVDD AVDD AVDD 132 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 133 AGND AGND AGND AGND AGND AGND AGND 134 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 135 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 136 I/O I/O I/O I/O I/O I/O I/O 137 I/O I/O I/O I/O I/O I/O I/O 138 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 139 I/O I/O I/O I/O I/O I/O I/O 140 I/O I/O I/O I/O I/O I/O I/O v5.2 2-9 ProASICPLUS Flash Family FPGAs 208-Pin PQFP Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 141 GND GND GND GND GND GND GND 142 VDD VDD VDD VDD VDD VDD VDD 143 I/O I/O I/O I/O I/O I/O I/O 144 I/O I/O I/O I/O I/O I/O I/O 145 I/O I/O I/O I/O I/O I/O I/O 146 I/O I/O I/O I/O I/O I/O I/O 147 I/O I/O I/O I/O I/O I/O I/O 148 I/O I/O I/O I/O I/O I/O I/O 149 I/O I/O I/O I/O I/O I/O I/O 150 I/O I/O I/O I/O I/O I/O I/O 151 I/O I/O I/O I/O I/O I/O I/O 152 I/O I/O I/O I/O I/O I/O I/O 153 I/O I/O I/O I/O I/O I/O I/O 154 I/O I/O I/O I/O I/O I/O I/O 155 I/O I/O I/O I/O I/O I/O I/O 156 GND GND GND GND GND GND GND 157 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 158 I/O I/O I/O I/O I/O I/O I/O 159 I/O I/O I/O I/O I/O I/O I/O 160 I/O I/O I/O I/O I/O I/O I/O 161 I/O I/O I/O I/O I/O I/O I/O 162 GND GND GND GND GND GND GND 163 I/O I/O I/O I/O I/O I/O I/O 164 I/O I/O I/O I/O I/O I/O I/O 165 I/O I/O I/O I/O I/O I/O I/O 166 I/O I/O I/O I/O I/O I/O I/O 167 I/O I/O I/O I/O I/O I/O I/O 168 I/O I/O I/O I/O I/O I/O I/O 169 I/O I/O I/O I/O I/O I/O I/O 170 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 171 VDD VDD VDD VDD VDD VDD VDD 172 I/O I/O I/O I/O I/O I/O I/O 173 I/O I/O I/O I/O I/O I/O I/O 174 I/O I/O I/O I/O I/O I/O I/O 175 I/O I/O I/O I/O I/O I/O I/O 2 -1 0 v5.2 ProASICPLUS Flash Family FPGAs 208-Pin PQFP Pin Number APA075 Function APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function 176 I/O I/O I/O I/O I/O I/O I/O 177 I/O I/O I/O I/O I/O I/O I/O 178 GND GND GND GND GND GND GND 179 I/O I/O I/O I/O I/O I/O I/O 180 I/O I/O I/O I/O I/O I/O I/O 181 I/O I/O I/O I/O I/O I/O I/O 182 I/O I/O I/O I/O I/O I/O I/O 183 I/O I/O I/O I/O I/O I/O I/O 184 I/O I/O I/O I/O I/O I/O I/O 185 I/O I/O I/O I/O I/O I/O I/O 186 VDDP VDDP VDDP VDDP VDDP VDDP VDDP 187 VDD VDD VDD VDD VDD VDD VDD 188 I/O I/O I/O I/O I/O I/O I/O 189 I/O I/O I/O I/O I/O I/O I/O 190 I/O I/O I/O I/O I/O I/O I/O 191 I/O I/O I/O I/O I/O I/O I/O 192 I/O I/O I/O I/O I/O I/O I/O 193 I/O I/O I/O I/O I/O I/O I/O 194 I/O I/O I/O I/O I/O I/O I/O 195 GND GND GND GND GND GND GND 196 I/O I/O I/O I/O I/O I/O I/O 197 I/O I/O I/O I/O I/O I/O I/O 198 I/O I/O I/O I/O I/O I/O I/O 199 I/O I/O I/O I/O I/O I/O I/O 200 I/O I/O I/O I/O I/O I/O I/O 201 I/O I/O I/O I/O I/O I/O I/O 202 I/O I/O I/O I/O I/O I/O I/O 203 I/O I/O I/O I/O I/O I/O I/O 204 I/O I/O I/O I/O I/O I/O I/O 205 I/O I/O I/O I/O I/O I/O I/O 206 I/O I/O I/O I/O I/O I/O I/O 207 I/O I/O I/O I/O I/O I/O I/O 208 VDDP VDDP VDDP VDDP VDDP VDDP VDDP v5.2 2-11 ProASICPLUS Flash Family FPGAs 160 159 158 157 194 193 192 191 190 189 188 187 186 208 207 206 205 208-Pin CQFP No. 1 1 2 3 4 156 155 154 153 Ceramic Tie Bar 31 32 33 34 35 36 37 38 39 142 141 140 139 138 137 136 135 134 208-Pin CQFP 101 102 103 104 84 85 86 87 88 89 90 91 92 108 107 106 105 53 54 55 57 49 50 51 52 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 2 -1 2 v5.2 ProASICPLUS Flash Family FPGAs 208-Pin CQFP 208-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 1 GND GND GND 36 VDD VDD VDD 2 I/O I/O I/O 37 I/O I/O I/O 3 I/O I/O I/O 38 I/O I/O I/O 4 I/O I/O I/O 39 I/O I/O I/O 5 I/O I/O I/O 40 VDDP VDDP VDDP 6 I/O I/O I/O 41 GND GND GND 7 I/O I/O I/O 42 I/O I/O I/O 8 I/O I/O I/O 43 I/O I/O I/O 9 I/O I/O I/O 44 I/O I/O I/O 10 I/O I/O I/O 45 I/O I/O I/O 11 I/O I/O I/O 46 I/O I/O I/O 12 I/O I/O I/O 47 I/O I/O I/O 13 I/O I/O I/O 48 I/O I/O I/O 14 I/O I/O I/O 49 I/O I/O I/O 15 I/O I/O I/O 50 I/O I/O I/O 16 VDD VDD VDD 51 I/O I/O I/O 17 GND GND GND 52 GND GND GND 18 I/O I/O I/O 53 VDDP VDDP VDDP 19 I/O I/O I/O 54 I/O I/O I/O 20 I/O I/O I/O 55 I/O I/O I/O 21 I/O I/O I/O 56 I/O I/O I/O 22 VDDP VDDP VDDP 57 I/O I/O I/O 23 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 58 I/O I/O I/O 24 I/O / GL2 I/O / GL2 I/O / GL2 59 I/O I/O I/O 25 AGND AGND AGND 60 I/O I/O I/O 26 NPECL1 NPECL1 NPECL1 61 I/O I/O I/O 27 AVDD AVDD AVDD 62 I/O I/O I/O 63 I/O I/O I/O 28 PPECL1 / Input PPECL1 / Input PPECL1 / Input 29 GND GND GND 64 I/O I/O I/O 30 I/O / GL1 I/O / GL1 I/O / GL1 65 GND GND GND 31 I/O I/O I/O 66 I/O I/O I/O 32 I/O I/O I/O 67 I/O I/O I/O 33 I/O I/O I/O 68 I/O I/O I/O 34 I/O I/O I/O 69 I/O I/O I/O 35 I/O I/O I/O 70 I/O I/O I/O v5.2 2-13 ProASICPLUS Flash Family FPGAs 208-Pin CQFP 208-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 71 VDD VDD VDD 106 VPP VPP VPP 72 VDDP VDDP VDDP 107 VPN VPN VPN 73 I/O I/O I/O 108 TDO TDO TDO 74 I/O I/O I/O 109 TRST TRST TRST 75 I/O I/O I/O 110 RCK RCK RCK 76 I/O I/O I/O 111 I/O I/O I/O 77 I/O I/O I/O 112 I/O I/O I/O 78 I/O I/O I/O 113 I/O I/O I/O 79 I/O I/O I/O 114 I/O I/O I/O 80 I/O I/O I/O 115 I/O I/O I/O 81 GND GND GND 116 I/O I/O I/O 82 I/O I/O I/O 117 I/O I/O I/O 83 I/O I/O I/O 118 I/O I/O I/O 84 I/O I/O I/O 119 I/O I/O I/O 85 I/O I/O I/O 120 I/O I/O I/O 86 I/O I/O I/O 121 I/O I/O I/O 87 I/O I/O I/O 122 GND GND GND 88 VDD VDD VDD 123 VDDP VDDP VDDP 89 VDDP VDDP VDDP 124 I/O I/O I/O 90 I/O I/O I/O 125 I/O I/O I/O 91 I/O I/O I/O 126 VDD VDD VDD 92 I/O I/O I/O 127 I/O I/O I/O 93 I/O I/O I/O 128 I/O / GL3 I/O / GL3 I/O / GL3 94 I/O I/O I/O 129 95 I/O I/O I/O 130 GND GND GND 96 I/O I/O I/O 131 AVDD AVDD AVDD 97 GND GND GND 132 NPECL2 NPECL2 NPECL2 98 I/O I/O I/O 133 AGND AGND AGND 99 I/O I/O I/O 134 I/O / GL4 I/O / GL4 I/O / GL4 100 I/O I/O I/O 135 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 101 TCK TCK TCK 136 I/O I/O I/O 102 TDI TDI TDI 137 I/O I/O I/O 103 TMS TMS TMS 138 VDDP VDDP VDDP 104 VDDP VDDP VDDP 139 I/O I/O I/O 105 GND GND GND 140 I/O I/O I/O 2 -1 4 v5.2 PPECL2 / Input PPECL2 / Input PPECL2 / Input ProASICPLUS Flash Family FPGAs 208-Pin CQFP 208-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 141 GND GND GND 176 I/O I/O I/O 142 VDD VDD VDD 177 I/O I/O I/O 143 I/O I/O I/O 178 GND GND GND 144 I/O I/O I/O 179 I/O I/O I/O 145 I/O I/O I/O 180 I/O I/O I/O 146 I/O I/O I/O 181 I/O I/O I/O 147 I/O I/O I/O 182 I/O I/O I/O 148 I/O I/O I/O 183 I/O I/O I/O 149 I/O I/O I/O 184 I/O I/O I/O 150 I/O I/O I/O 185 I/O I/O I/O 151 I/O I/O I/O 186 VDDP VDDP VDDP 152 I/O I/O I/O 187 VDD VDD VDD 153 I/O I/O I/O 188 I/O I/O I/O 154 I/O I/O I/O 189 I/O I/O I/O 155 I/O I/O I/O 190 I/O I/O I/O 156 GND GND GND 191 I/O I/O I/O 157 VDDP VDDP VDDP 192 I/O I/O I/O 158 I/O I/O I/O 193 I/O I/O I/O 159 I/O I/O I/O 194 I/O I/O I/O 160 I/O I/O I/O 195 GND GND GND 161 I/O I/O I/O 196 I/O I/O I/O 162 GND GND GND 197 I/O I/O I/O 163 I/O I/O I/O 198 I/O I/O I/O 164 I/O I/O I/O 199 I/O I/O I/O 165 I/O I/O I/O 200 I/O I/O I/O 166 I/O I/O I/O 201 I/O I/O I/O 167 I/O I/O I/O 202 I/O I/O I/O 168 I/O I/O I/O 203 I/O I/O I/O 169 I/O I/O I/O 204 I/O I/O I/O 170 VDDP VDDP VDDP 205 I/O I/O I/O 171 VDD VDD VDD 206 I/O I/O I/O 172 I/O I/O I/O 207 I/O I/O I/O 173 I/O I/O I/O 208 VDDP VDDP VDDP 174 I/O I/O I/O 175 I/O I/O I/O v5.2 2-15 ProASICPLUS Flash Family FPGAs 268 267 266 265 339 338 337 336 335 334 333 332 331 352 351 350 349 352-Pin CQFP Pin 1 1 2 3 4 264 263 262 261 Ceramic Tie Bar 41 42 43 44 45 46 47 48 49 223 222 221 220 219 218 217 216 215 352-Pin CQFP 173 174 175 176 127 128 129 130 131 132 133 134 135 180 179 178 177 89 90 91 92 85 86 87 88 Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 2 -1 6 v5.2 ProASICPLUS Flash Family FPGAs 352-Pin CQFP 352-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 1 I/O I/O I/O 38 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 2 I/O I/O I/O 39 I/O / GL2 I/O / GL2 I/O / GL2 3 I/O I/O I/O 40 AGND AGND AGND 4 I/O I/O I/O 41 AVDD AVDD AVDD 5 I/O I/O I/O 42 NPECL1 NPECL1 NPECL1 6 I/O I/O I/O 43 7 VDD VDD VDD 44 I/O / GL1 I/O / GL1 I/O / GL1 8 GND GND GND 45 I/O I/O I/O 9 VDDP VDDP VDDP 46 I/O I/O I/O 10 I/O I/O I/O 47 VDD VDD VDD 11 I/O I/O I/O 48 GND GND GND 12 I/O I/O I/O 49 VDDP VDDP VDDP 13 I/O I/O I/O 50 I/O I/O I/O 14 I/O I/O I/O 51 I/O I/O I/O 15 I/O I/O I/O 52 I/O I/O I/O 16 I/O I/O I/O 53 I/O I/O I/O 17 I/O I/O I/O 54 I/O I/O I/O 18 VDD VDD VDD 55 I/O I/O I/O 19 GND GND GND 56 I/O I/O I/O 20 VDDP VDDP VDDP 57 I/O I/O I/O 21 I/O I/O I/O 58 VDD VDD VDD 22 I/O I/O I/O 59 GND GND GND 23 I/O I/O I/O 60 VDDP VDDP VDDP 24 I/O I/O I/O 61 I/O I/O I/O 25 I/O I/O I/O 62 I/O I/O I/O 26 I/O I/O I/O 63 I/O I/O I/O 27 I/O I/O I/O 64 I/O I/O I/O 28 I/O I/O I/O 65 I/O I/O I/O 29 VDD VDD VDD 66 I/O I/O I/O 30 GND GND GND 67 I/O I/O I/O 31 VDDP VDDP VDDP 68 I/O I/O I/O 32 I/O I/O I/O 69 VDD VDD VDD 33 I/O I/O I/O 70 GND GND GND 34 I/O I/O I/O 71 VDDP VDDP VDDP 35 I/O I/O I/O 72 I/O I/O I/O 36 I/O I/O I/O 73 I/O I/O I/O 37 I/O I/O I/O 74 I/O I/O I/O v5.2 PPECL1 / Input PPECL1 / Input PPECL1 / Input 2-17 ProASICPLUS Flash Family FPGAs 352-Pin CQFP 352-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 75 I/O I/O I/O 112 GND GND GND 76 I/O I/O I/O 113 VDD VDD VDD 77 I/O I/O I/O 114 I/O I/O I/O 78 I/O I/O I/O 115 I/O I/O I/O 79 I/O I/O I/O 116 I/O I/O I/O 80 VDD VDD VDD 117 I/O I/O I/O 81 GND GND GND 118 I/O I/O I/O 82 VDDP VDDP VDDP 119 I/O I/O I/O 83 I/O I/O I/O 120 I/O I/O I/O 84 I/O I/O I/O 121 I/O I/O I/O 85 I/O I/O I/O 122 VDDP VDDP VDDP 86 I/O I/O I/O 123 GND GND GND 87 I/O I/O I/O 124 VDD VDD VDD 88 I/O I/O I/O 125 I/O I/O I/O 89 VDDP VDDP VDDP 126 I/O I/O I/O 90 GND GND GND 127 I/O I/O I/O 91 VDD VDD VDD 128 I/O I/O I/O 92 I/O I/O I/O 129 I/O I/O I/O 93 I/O I/O I/O 130 I/O I/O I/O 94 I/O I/O I/O 131 I/O I/O I/O 95 I/O I/O I/O 132 I/O I/O I/O 96 I/O I/O I/O 133 VDDP VDDP VDDP 97 I/O I/O I/O 134 GND GND GND 98 I/O I/O I/O 135 VDD VDD VDD 99 I/O I/O I/O 136 I/O I/O I/O 100 VDDP VDDP VDDP 137 I/O I/O I/O 101 GND GND GND 138 I/O I/O I/O 102 VDD VDD VDD 139 I/O I/O I/O 103 I/O I/O I/O 140 I/O I/O I/O 104 I/O I/O I/O 141 I/O I/O I/O 105 I/O I/O I/O 142 I/O I/O I/O 106 I/O I/O I/O 143 I/O I/O I/O 107 I/O I/O I/O 144 VDDP VDDP VDDP 108 I/O I/O I/O 145 GND GND GND 109 I/O I/O I/O 146 VDD VDD VDD 110 I/O I/O I/O 147 I/O I/O I/O 111 VDDP VDDP VDDP 148 I/O I/O I/O 2 -1 8 v5.2 ProASICPLUS Flash Family FPGAs 352-Pin CQFP 352-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 149 I/O I/O I/O 186 I/O I/O I/O 150 I/O I/O I/O 187 I/O I/O I/O 151 I/O I/O I/O 188 I/O I/O I/O 152 I/O I/O I/O 189 I/O I/O I/O 153 I/O I/O I/O 190 I/O I/O I/O 154 I/O I/O I/O 191 I/O I/O I/O 155 VDDP VDDP VDDP 192 I/O I/O I/O 156 GND GND GND 193 I/O I/O I/O 157 VDD VDD VDD 194 VDDP VDDP VDDP 158 I/O I/O I/O 195 GND GND GND 159 I/O I/O I/O 196 VDD VDD VDD 160 I/O I/O I/O 197 I/O I/O I/O 161 I/O I/O I/O 198 I/O I/O I/O 162 I/O I/O I/O 199 I/O I/O I/O 163 I/O I/O I/O 200 I/O I/O I/O 164 I/O I/O I/O 201 I/O I/O I/O 165 I/O I/O I/O 202 I/O I/O I/O 166 VDDP VDDP VDDP 203 I/O I/O I/O 167 GND GND GND 204 I/O I/O I/O 168 VDD VDD VDD 205 VDDP VDDP VDDP 169 I/O I/O I/O 206 GND GND GND 170 I/O I/O I/O 207 VDD VDD VDD 171 I/O I/O I/O 208 I/O I/O I/O 172 I/O I/O I/O 209 I/O I/O I/O 173 TCK TCK TCK 210 I/O I/O I/O 174 TDI TDI TDI 211 I/O I/O I/O 175 TMS TMS TMS 212 I/O I/O I/O 176 I/O I/O I/O 213 I/O I/O I/O 177 VPP VPP VPP 214 I/O I/O I/O 178 VPN VPN VPN 215 I/O I/O I/O 179 TDO TDO TDO 216 VDDP VDDP VDDP 180 TRST TRST TRST 217 GND GND GND 181 RCK RCK RCK 218 VDD VDD VDD 182 I/O I/O I/O 219 I/O I/O I/O 183 VDDP VDDP VDDP 220 I/O I/O I/O 184 GND GND GND 221 I/O / GL3 I/O / GL3 I/O / GL3 185 VDD VDD VDD 222 v5.2 PPECL2 / Input PPECL2 / Input PPECL2 / Input 2-19 ProASICPLUS Flash Family FPGAs 352-Pin CQFP 352-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 223 NPECL2 NPECL2 NPECL2 260 I/O I/O I/O 224 AVDD AVDD AVDD 261 I/O I/O I/O 225 AGND AGND AGND 262 I/O I/O I/O 226 I/O / GL4 I/O / GL4 I/O / GL4 263 I/O I/O I/O 227 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 264 I/O I/O I/O 228 I/O I/O I/O 265 I/O I/O I/O 229 I/O I/O I/O 266 I/O I/O I/O 230 I/O I/O I/O 267 I/O I/O I/O 231 I/O I/O I/O 268 I/O I/O I/O 232 I/O I/O I/O 269 I/O I/O I/O 233 I/O I/O I/O 270 I/O I/O I/O 234 VDDP VDDP VDDP 271 I/O I/O I/O 235 GND GND GND 272 I/O I/O I/O 236 VDD VDD VDD 273 VDD VDD VDD 237 I/O I/O I/O 274 GND GND GND 238 I/O I/O I/O 275 VDDP VDDP VDDP 239 I/O I/O I/O 276 I/O I/O I/O 240 I/O I/O I/O 277 I/O I/O I/O 241 I/O I/O I/O 278 I/O I/O I/O 242 I/O I/O I/O 279 I/O I/O I/O 243 I/O I/O I/O 280 I/O I/O I/O 244 I/O I/O I/O 281 I/O I/O I/O 245 VDDP VDDP VDDP 282 I/O I/O I/O 246 GND GND GND 283 I/O I/O I/O 247 VDD VDD VDD 284 VDD VDD VDD 248 I/O I/O I/O 285 GND GND GND 249 I/O I/O I/O 286 VDDP VDDP VDDP 250 I/O I/O I/O 287 I/O I/O I/O 251 I/O I/O I/O 288 I/O I/O I/O 252 I/O I/O I/O 289 I/O I/O I/O 253 I/O I/O I/O 290 I/O I/O I/O 254 I/O I/O I/O 291 I/O I/O I/O 255 I/O I/O I/O 292 I/O I/O I/O 256 VDDP VDDP VDDP 293 I/O I/O I/O 257 GND GND GND 294 I/O I/O I/O 258 VDD VDD VDD 295 VDD VDD VDD 259 I/O I/O I/O 296 GND GND GND 2 -2 0 v5.2 ProASICPLUS Flash Family FPGAs 352-Pin CQFP 352-Pin CQFP Pin Number APA300 Function APA600 Function APA1000 Function Pin Number APA300 Function APA600 Function APA1000 Function 297 VDDP VDDP VDDP 334 I/O I/O I/O 298 I/O I/O I/O 335 I/O I/O I/O 299 I/O I/O I/O 336 I/O I/O I/O 300 I/O I/O I/O 337 I/O I/O I/O 301 I/O I/O I/O 338 I/O I/O I/O 302 I/O I/O I/O 339 VDD VDD VDD 303 I/O I/O I/O 340 GND GND GND 304 I/O I/O I/O 341 VDDP VDDP VDDP 305 I/O I/O I/O 342 I/O I/O I/O 306 VDD VDD VDD 343 I/O I/O I/O 307 GND GND GND 344 I/O I/O I/O 308 VDDP VDDP VDDP 345 I/O I/O I/O 309 I/O I/O I/O 346 I/O I/O I/O 310 I/O I/O I/O 347 I/O I/O I/O 311 I/O I/O I/O 348 I/O I/O I/O 312 I/O I/O I/O 349 I/O I/O I/O 313 I/O I/O I/O 350 VDD VDD VDD 314 I/O I/O I/O 351 GND GND GND 315 I/O I/O I/O 352 VDDP VDDP VDDP 316 I/O I/O I/O 317 VDD VDD VDD 318 GND GND GND 319 VDDP VDDP VDDP 320 I/O I/O I/O 321 I/O I/O I/O 322 I/O I/O I/O 323 I/O I/O I/O 324 I/O I/O I/O 325 I/O I/O I/O 326 I/O I/O I/O 327 I/O I/O I/O 328 VDD VDD VDD 329 GND GND GND 330 VDDP VDDP VDDP 331 I/O I/O I/O 332 I/O I/O I/O 333 I/O I/O I/O v5.2 2-21 ProASICPLUS Flash Family FPGAs 456-Pin PBGA A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 2 -2 2 v5.2 ProASICPLUS Flash Family FPGAs 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function A1 VDDP VDDP VDDP VDDP VDDP VDDP A2 VDDP VDDP VDDP VDDP VDDP VDDP A3 NC NC I/O I/O I/O I/O A4 NC NC I/O I/O I/O I/O A5 NC NC I/O I/O I/O I/O A6 NC NC I/O I/O I/O I/O A7 NC NC I/O I/O I/O I/O A8 I/O I/O I/O I/O I/O I/O A9 I/O I/O I/O I/O I/O I/O A10 I/O I/O I/O I/O I/O I/O A11 I/O I/O I/O I/O I/O I/O A12 I/O I/O I/O I/O I/O I/O A13 I/O I/O I/O I/O I/O I/O A14 I/O I/O I/O I/O I/O I/O A15 I/O I/O I/O I/O I/O I/O A16 I/O I/O I/O I/O I/O I/O A17 I/O I/O I/O I/O I/O I/O A18 I/O I/O I/O I/O I/O I/O A19 I/O I/O I/O I/O I/O I/O A20 NC NC I/O I/O I/O I/O A21 NC NC I/O I/O I/O I/O A22 NC NC I/O I/O I/O I/O A23 NC NC I/O I/O I/O I/O A24 NC NC I/O I/O I/O I/O A25 VDDP VDDP VDDP VDDP VDDP VDDP A26 VDDP VDDP VDDP VDDP VDDP VDDP B1 VDDP VDDP VDDP VDDP VDDP VDDP B2 VDDP VDDP VDDP VDDP VDDP VDDP B3 NC NC NC I/O I/O I/O B4 NC NC I/O I/O I/O I/O B5 NC NC I/O I/O I/O I/O B6 NC NC I/O I/O I/O I/O B7 NC NC I/O I/O I/O I/O B8 I/O I/O I/O I/O I/O I/O v5.2 2-23 ProASICPLUS Flash Family FPGAs 456-Pin PBGA 2 -2 4 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function B9 I/O I/O I/O I/O I/O I/O B10 I/O I/O I/O I/O I/O I/O B11 I/O I/O I/O I/O I/O I/O B12 I/O I/O I/O I/O I/O I/O B13 I/O I/O I/O I/O I/O I/O B14 I/O I/O I/O I/O I/O I/O B15 I/O I/O I/O I/O I/O I/O B16 I/O I/O I/O I/O I/O I/O B17 I/O I/O I/O I/O I/O I/O B18 I/O I/O I/O I/O I/O I/O B19 I/O I/O I/O I/O I/O I/O B20 NC NC I/O I/O I/O I/O B21 NC NC I/O I/O I/O I/O B22 NC NC I/O I/O I/O I/O B23 NC NC I/O I/O I/O I/O B24 NC NC I/O I/O I/O I/O B25 VDDP VDDP VDDP VDDP VDDP VDDP B26 VDDP VDDP VDDP VDDP VDDP VDDP C1 VDDP VDDP VDDP VDDP VDDP VDDP C2 NC I/O I/O I/O I/O I/O C3 VDDP VDDP VDDP VDDP VDDP VDDP C4 NC NC NC I/O I/O I/O C5 NC NC I/O I/O I/O I/O C6 NC NC I/O I/O I/O I/O C7 I/O I/O I/O I/O I/O I/O C8 I/O I/O I/O I/O I/O I/O C9 I/O I/O I/O I/O I/O I/O C10 I/O I/O I/O I/O I/O I/O C11 I/O I/O I/O I/O I/O I/O C12 I/O I/O I/O I/O I/O I/O C13 I/O I/O I/O I/O I/O I/O C14 I/O I/O I/O I/O I/O I/O C15 I/O I/O I/O I/O I/O I/O C16 I/O I/O I/O I/O I/O I/O v5.2 ProASICPLUS Flash Family FPGAs 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function C17 I/O I/O I/O I/O I/O I/O C18 I/O I/O I/O I/O I/O I/O C19 I/O I/O I/O I/O I/O I/O C20 I/O I/O I/O I/O I/O I/O C21 NC NC I/O I/O I/O I/O C22 NC NC I/O I/O I/O I/O C23 NC NC I/O I/O I/O I/O C24 VDDP VDDP VDDP VDDP VDDP VDDP C25 NC NC NC I/O I/O I/O C26 NC NC NC I/O I/O I/O D1 NC NC NC I/O I/O I/O D2 NC NC NC I/O I/O I/O D3 NC I/O I/O I/O I/O I/O D4 VDDP VDDP VDDP VDDP VDDP VDDP D5 NC NC I/O I/O I/O I/O D6 NC NC I/O I/O I/O I/O D7 I/O I/O I/O I/O I/O I/O D8 I/O I/O I/O I/O I/O I/O D9 I/O I/O I/O I/O I/O I/O D10 I/O I/O I/O I/O I/O I/O D11 I/O I/O I/O I/O I/O I/O D12 I/O I/O I/O I/O I/O I/O D13 I/O I/O I/O I/O I/O I/O D14 I/O I/O I/O I/O I/O I/O D15 I/O I/O I/O I/O I/O I/O D16 I/O I/O I/O I/O I/O I/O D17 I/O I/O I/O I/O I/O I/O D18 I/O I/O I/O I/O I/O I/O D19 I/O I/O I/O I/O I/O I/O D20 I/O I/O I/O I/O I/O I/O D21 I/O I/O I/O I/O I/O I/O D22 NC NC I/O I/O I/O I/O D23 VDDP VDDP VDDP VDDP VDDP VDDP D24 NC I/O I/O I/O I/O I/O v5.2 2-25 ProASICPLUS Flash Family FPGAs 456-Pin PBGA 2 -2 6 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function D25 NC NC NC I/O I/O I/O D26 NC NC NC I/O I/O I/O E1 NC I/O I/O I/O I/O I/O E2 NC I/O I/O I/O I/O I/O E3 NC I/O I/O I/O I/O I/O E4 NC I/O I/O I/O I/O I/O E5 VDD VDD VDD VDD VDD VDD E6 VDD VDD VDD VDD VDD VDD E7 VDD VDD VDD VDD VDD VDD E8 VDD VDD VDD VDD VDD VDD E9 I/O I/O I/O I/O I/O I/O E10 I/O I/O I/O I/O I/O I/O E11 I/O I/O I/O I/O I/O I/O E12 I/O I/O I/O I/O I/O I/O E13 I/O I/O I/O I/O I/O I/O E14 I/O I/O I/O I/O I/O I/O E15 I/O I/O I/O I/O I/O I/O E16 I/O I/O I/O I/O I/O I/O E17 I/O I/O I/O I/O I/O I/O E18 I/O I/O I/O I/O I/O I/O E19 I/O I/O I/O I/O I/O I/O E20 VDD VDD VDD VDD VDD VDD E21 VDD VDD VDD VDD VDD VDD E22 VDD VDD VDD VDD VDD VDD E23 NC I/O I/O I/O I/O I/O E24 NC I/O I/O I/O I/O I/O E25 NC I/O I/O I/O I/O I/O E26 NC I/O I/O I/O I/O I/O F1 NC I/O I/O I/O I/O I/O F2 NC I/O I/O I/O I/O I/O F3 NC I/O I/O I/O I/O I/O F4 NC I/O I/O I/O I/O I/O F5 VDD VDD VDD VDD VDD VDD F22 VDD VDD VDD VDD VDD VDD v5.2 ProASICPLUS Flash Family FPGAs 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function F23 NC I/O I/O I/O I/O I/O F24 NC I/O I/O I/O I/O I/O F25 NC I/O I/O I/O I/O I/O F26 NC I/O I/O I/O I/O I/O G1 I/O I/O I/O I/O I/O I/O G2 I/O I/O I/O I/O I/O I/O G3 NC I/O I/O I/O I/O I/O G4 NC I/O I/O I/O I/O I/O G5 VDD VDD VDD VDD VDD VDD G22 VDD VDD VDD VDD VDD VDD G23 NC I/O I/O I/O I/O I/O G24 NC I/O I/O I/O I/O I/O G25 NC I/O I/O I/O I/O I/O G26 I/O I/O I/O I/O I/O I/O H1 I/O I/O I/O I/O I/O I/O H2 I/O I/O I/O I/O I/O I/O H3 I/O I/O I/O I/O I/O I/O H4 I/O I/O I/O I/O I/O I/O H5 VDD VDD VDD VDD VDD VDD H22 VDD VDD VDD VDD VDD VDD H23 I/O I/O I/O I/O I/O I/O H24 I/O I/O I/O I/O I/O I/O H25 I/O I/O I/O I/O I/O I/O H26 I/O I/O I/O I/O I/O I/O J1 I/O I/O I/O I/O I/O I/O J2 I/O I/O I/O I/O I/O I/O J3 I/O I/O I/O I/O I/O I/O J4 I/O I/O I/O I/O I/O I/O J5 I/O I/O I/O I/O I/O I/O J22 I/O I/O I/O I/O I/O I/O J23 I/O I/O I/O I/O I/O I/O J24 I/O I/O I/O I/O I/O I/O J25 I/O I/O I/O I/O I/O I/O J26 I/O I/O I/O I/O I/O I/O v5.2 2-27 ProASICPLUS Flash Family FPGAs 456-Pin PBGA 2 -2 8 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function K1 I/O I/O I/O I/O I/O I/O K2 I/O I/O I/O I/O I/O I/O K3 I/O I/O I/O I/O I/O I/O K4 I/O I/O I/O I/O I/O I/O K5 I/O I/O I/O I/O I/O I/O K22 I/O I/O I/O I/O I/O I/O K23 I/O I/O I/O I/O I/O I/O K24 I/O I/O I/O I/O I/O I/O K25 I/O I/O I/O I/O I/O I/O K26 I/O I/O I/O I/O I/O I/O L1 I/O I/O I/O I/O I/O I/O L2 I/O I/O I/O I/O I/O I/O L3 I/O I/O I/O I/O I/O I/O L4 I/O I/O I/O I/O I/O I/O L5 I/O I/O I/O I/O I/O I/O L11 GND GND GND GND GND GND L12 GND GND GND GND GND GND L13 GND GND GND GND GND GND L14 GND GND GND GND GND GND L15 GND GND GND GND GND GND L16 GND GND GND GND GND GND L22 I/O I/O I/O I/O I/O I/O L23 I/O I/O I/O I/O I/O I/O L24 I/O I/O I/O I/O I/O I/O L25 I/O I/O I/O I/O I/O I/O L26 I/O I/O I/O I/O I/O I/O M1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 M2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 M3 I/O I/O I/O I/O I/O I/O M4 I/O I/O I/O I/O I/O I/O M5 I/O I/O I/O I/O I/O I/O M11 GND GND GND GND GND GND M12 GND GND GND GND GND GND M13 GND GND GND GND GND GND v5.2 ProASICPLUS Flash Family FPGAs 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function M14 GND GND GND GND GND GND M15 GND GND GND GND GND GND M16 GND GND GND GND GND GND M22 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 M23 I/O I/O I/O I/O I/O I/O M24 I/O I/O I/O I/O I/O I/O M25 I/O I/O I/O I/O I/O I/O M26 I/O I/O I/O I/O I/O I/O N1 I/O I/O I/O I/O I/O I/O N2 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 N3 AGND AGND AGND AGND AGND AGND N4 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input N5 AVDD AVDD AVDD AVDD AVDD AVDD N11 GND GND GND GND GND GND N12 GND GND GND GND GND GND N13 GND GND GND GND GND GND N14 GND GND GND GND GND GND N15 GND GND GND GND GND GND N16 GND GND GND GND GND GND N22 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 NPECL2 N23 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 N24 AVDD AVDD AVDD AVDD AVDD AVDD N25 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 N26 AGND AGND AGND AGND AGND AGND P1 I/O I/O I/O I/O I/O I/O P2 I/O I/O I/O I/O I/O I/O P3 I/O I/O I/O I/O I/O I/O P4 I/O I/O I/O I/O I/O I/O P5 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 NPECL1 P11 GND GND GND GND GND GND P12 GND GND GND GND GND GND P13 GND GND GND GND GND GND P14 GND GND GND GND GND GND P15 GND GND GND GND GND GND v5.2 2-29 ProASICPLUS Flash Family FPGAs 456-Pin PBGA 2 -3 0 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function P16 GND GND GND GND GND GND P22 I/O I/O I/O I/O I/O I/O P23 I/O I/O I/O I/O I/O I/O P24 I/O I/O I/O I/O I/O I/O P25 I/O I/O I/O I/O I/O I/O P26 PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input R1 I/O I/O I/O I/O I/O I/O R2 I/O I/O I/O I/O I/O I/O R3 I/O I/O I/O I/O I/O I/O R4 I/O I/O I/O I/O I/O I/O R5 I/O I/O I/O I/O I/O I/O R11 GND GND GND GND GND GND R12 GND GND GND GND GND GND R13 GND GND GND GND GND GND R14 GND GND GND GND GND GND R15 GND GND GND GND GND GND R16 GND GND GND GND GND GND R22 I/O I/O I/O I/O I/O I/O R23 I/O I/O I/O I/O I/O I/O R24 I/O I/O I/O I/O I/O I/O R25 I/O I/O I/O I/O I/O I/O R26 I/O I/O I/O I/O I/O I/O T1 I/O I/O I/O I/O I/O I/O T2 I/O I/O I/O I/O I/O I/O T3 I/O I/O I/O I/O I/O I/O T4 I/O I/O I/O I/O I/O I/O T5 I/O I/O I/O I/O I/O I/O T11 GND GND GND GND GND GND T12 GND GND GND GND GND GND T13 GND GND GND GND GND GND T14 GND GND GND GND GND GND T15 GND GND GND GND GND GND T16 GND GND GND GND GND GND T22 I/O I/O I/O I/O I/O I/O v5.2 ProASICPLUS Flash Family FPGAs 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function T23 I/O I/O I/O I/O I/O I/O T24 I/O I/O I/O I/O I/O I/O T25 I/O I/O I/O I/O I/O I/O T26 I/O I/O I/O I/O I/O I/O U1 I/O I/O I/O I/O I/O I/O U2 I/O I/O I/O I/O I/O I/O U3 I/O I/O I/O I/O I/O I/O U4 I/O I/O I/O I/O I/O I/O U5 I/O I/O I/O I/O I/O I/O U22 I/O I/O I/O I/O I/O I/O U23 I/O I/O I/O I/O I/O I/O U24 I/O I/O I/O I/O I/O I/O U25 I/O I/O I/O I/O I/O I/O U26 I/O I/O I/O I/O I/O I/O V1 I/O I/O I/O I/O I/O I/O V2 I/O I/O I/O I/O I/O I/O V3 I/O I/O I/O I/O I/O I/O V4 I/O I/O I/O I/O I/O I/O V5 I/O I/O I/O I/O I/O I/O V22 I/O I/O I/O I/O I/O I/O V23 I/O I/O I/O I/O I/O I/O V24 I/O I/O I/O I/O I/O I/O V25 I/O I/O I/O I/O I/O I/O V26 I/O I/O I/O I/O I/O I/O W1 I/O I/O I/O I/O I/O I/O W2 I/O I/O I/O I/O I/O I/O W3 I/O I/O I/O I/O I/O I/O W4 I/O I/O I/O I/O I/O I/O W5 VDD VDD VDD VDD VDD VDD W22 VDD VDD VDD VDD VDD VDD W23 I/O I/O I/O I/O I/O I/O W24 I/O I/O I/O I/O I/O I/O W25 I/O I/O I/O I/O I/O I/O W26 I/O I/O I/O I/O I/O I/O v5.2 2-31 ProASICPLUS Flash Family FPGAs 456-Pin PBGA 2 -3 2 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function Y1 I/O I/O I/O I/O I/O I/O Y2 I/O I/O I/O I/O I/O I/O Y3 I/O I/O I/O I/O I/O I/O Y4 NC I/O I/O I/O I/O I/O Y5 VDD VDD VDD VDD VDD VDD Y22 VDD VDD VDD VDD VDD VDD Y23 NC I/O I/O I/O I/O I/O Y24 NC I/O I/O I/O I/O I/O Y25 NC I/O I/O I/O I/O I/O Y26 NC I/O I/O I/O I/O I/O AA1 I/O I/O I/O I/O I/O I/O AA2 NC I/O I/O I/O I/O I/O AA3 NC I/O I/O I/O I/O I/O AA4 NC I/O I/O I/O I/O I/O AA5 VDD VDD VDD VDD VDD VDD AA22 VDD VDD VDD VDD VDD VDD AA23 NC I/O I/O I/O I/O I/O AA24 NC I/O I/O I/O I/O I/O AA25 NC I/O I/O I/O I/O I/O AA26 NC I/O I/O I/O I/O I/O AB1 NC I/O I/O I/O I/O I/O AB2 NC I/O I/O I/O I/O I/O AB3 NC I/O I/O I/O I/O I/O AB4 NC I/O I/O I/O I/O I/O AB5 VDD VDD VDD VDD VDD VDD AB6 VDD VDD VDD VDD VDD VDD AB7 VDD VDD VDD VDD VDD VDD AB8 I/O I/O I/O I/O I/O I/O AB9 I/O I/O I/O I/O I/O I/O AB10 I/O I/O I/O I/O I/O I/O AB11 I/O I/O I/O I/O I/O I/O AB12 I/O I/O I/O I/O I/O I/O AB13 I/O I/O I/O I/O I/O I/O AB14 I/O I/O I/O I/O I/O I/O v5.2 ProASICPLUS Flash Family FPGAs 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AB15 I/O I/O I/O I/O I/O I/O AB16 I/O I/O I/O I/O I/O I/O AB17 I/O I/O I/O I/O I/O I/O AB18 I/O I/O I/O I/O I/O I/O AB19 I/O I/O I/O I/O I/O I/O AB20 VDD VDD VDD VDD VDD VDD AB21 VDD VDD VDD VDD VDD VDD AB22 VDD VDD VDD VDD VDD VDD AB23 NC I/O I/O I/O I/O I/O AB24 NC I/O I/O I/O I/O I/O AB25 NC I/O I/O I/O I/O I/O AB26 NC NC NC I/O I/O I/O AC1 NC I/O I/O I/O I/O I/O AC2 NC I/O I/O I/O I/O I/O AC3 NC I/O I/O I/O I/O I/O AC4 VDDP VDDP VDDP VDDP VDDP VDDP AC5 NC NC I/O I/O I/O I/O AC6 I/O I/O I/O I/O I/O I/O AC7 I/O I/O I/O I/O I/O I/O AC8 I/O I/O I/O I/O I/O I/O AC9 I/O I/O I/O I/O I/O I/O AC10 I/O I/O I/O I/O I/O I/O AC11 I/O I/O I/O I/O I/O I/O AC12 I/O I/O I/O I/O I/O I/O AC13 I/O I/O I/O I/O I/O I/O AC14 I/O I/O I/O I/O I/O I/O AC15 I/O I/O I/O I/O I/O I/O AC16 I/O I/O I/O I/O I/O I/O AC17 I/O I/O I/O I/O I/O I/O AC18 I/O I/O I/O I/O I/O I/O AC19 I/O I/O I/O I/O I/O I/O AC20 I/O I/O I/O I/O I/O I/O AC21 TMS TMS TMS TMS TMS TMS AC22 TDO TDO TDO TDO TDO TDO v5.2 2-33 ProASICPLUS Flash Family FPGAs 456-Pin PBGA 2 -3 4 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AC23 VDDP VDDP VDDP VDDP VDDP VDDP AC24 RCK RCK RCK RCK RCK RCK AC25 NC NC I/O I/O I/O I/O AC26 NC I/O I/O I/O I/O I/O AD1 NC NC NC I/O I/O I/O AD2 NC I/O I/O I/O I/O I/O AD3 VDDP VDDP VDDP VDDP VDDP VDDP AD4 NC NC I/O I/O I/O I/O AD5 NC NC I/O I/O I/O I/O AD6 NC NC I/O I/O I/O I/O AD7 I/O I/O I/O I/O I/O I/O AD8 I/O I/O I/O I/O I/O I/O AD9 I/O I/O I/O I/O I/O I/O AD10 I/O I/O I/O I/O I/O I/O AD11 I/O I/O I/O I/O I/O I/O AD12 I/O I/O I/O I/O I/O I/O AD13 I/O I/O I/O I/O I/O I/O AD14 I/O I/O I/O I/O I/O I/O AD15 I/O I/O I/O I/O I/O I/O AD16 I/O I/O I/O I/O I/O I/O AD17 I/O I/O I/O I/O I/O I/O AD18 I/O I/O I/O I/O I/O I/O AD19 I/O I/O I/O I/O I/O I/O AD20 NC NC I/O I/O I/O I/O AD21 TCK TCK TCK TCK TCK TCK AD22 VPP VPP VPP VPP VPP VPP AD23 NC NC NC I/O I/O I/O AD24 VDDP VDDP VDDP VDDP VDDP VDDP AD25 NC NC I/O I/O I/O I/O AD26 NC NC I/O I/O I/O I/O AE1 VDDP VDDP VDDP VDDP VDDP VDDP AE2 VDDP VDDP VDDP VDDP VDDP VDDP AE3 NC NC I/O I/O I/O I/O AE4 NC NC I/O I/O I/O I/O v5.2 ProASICPLUS Flash Family FPGAs 456-Pin PBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AE5 NC NC I/O I/O I/O I/O AE6 NC NC I/O I/O I/O I/O AE7 NC NC I/O I/O I/O I/O AE8 I/O I/O I/O I/O I/O I/O AE9 I/O I/O I/O I/O I/O I/O AE10 I/O I/O I/O I/O I/O I/O AE11 I/O I/O I/O I/O I/O I/O AE12 I/O I/O I/O I/O I/O I/O AE13 I/O I/O I/O I/O I/O I/O AE14 I/O I/O I/O I/O I/O I/O AE15 I/O I/O I/O I/O I/O I/O AE16 I/O I/O I/O I/O I/O I/O AE17 I/O I/O I/O I/O I/O I/O AE18 I/O I/O I/O I/O I/O I/O AE19 I/O I/O I/O I/O I/O I/O AE20 NC NC I/O I/O I/O I/O AE21 NC NC I/O I/O I/O I/O AE22 NC NC I/O I/O I/O I/O AE23 VPN VPN VPN VPN VPN VPN AE24 TRST TRST TRST TRST TRST TRST AE25 VDDP VDDP VDDP VDDP VDDP VDDP AE26 VDDP VDDP VDDP VDDP VDDP VDDP AF1 VDDP VDDP VDDP VDDP VDDP VDDP AF2 VDDP VDDP VDDP VDDP VDDP VDDP AF3 NC NC I/O I/O I/O I/O AF4 NC NC I/O I/O I/O I/O AF5 NC NC I/O I/O I/O I/O AF6 NC NC I/O I/O I/O I/O AF7 NC NC I/O I/O I/O I/O AF8 NC NC NC I/O I/O I/O AF9 I/O I/O I/O I/O I/O I/O AF10 I/O I/O I/O I/O I/O I/O AF11 I/O I/O I/O I/O I/O I/O AF12 I/O I/O I/O I/O I/O I/O v5.2 2-35 ProASICPLUS Flash Family FPGAs 456-Pin PBGA 2 -3 6 Pin Number APA150 Function APA300 Function APA450 Function APA600 Function APA750 Function APA1000 Function AF13 I/O I/O I/O I/O I/O I/O AF14 I/O I/O I/O I/O I/O I/O AF15 I/O I/O I/O I/O I/O I/O AF16 I/O I/O I/O I/O I/O I/O AF17 I/O I/O I/O I/O I/O I/O AF18 NC NC I/O I/O I/O I/O AF19 NC NC I/O I/O I/O I/O AF20 NC NC I/O I/O I/O I/O AF21 NC NC I/O I/O I/O I/O AF22 NC NC I/O I/O I/O I/O AF23 TDI TDI TDI TDI TDI TDI AF24 NC NC I/O I/O I/O I/O AF25 VDDP VDDP VDDP VDDP VDDP VDDP AF26 VDDP VDDP VDDP VDDP VDDP VDDP v5.2 ProASICPLUS Flash Family FPGAs 144-Pin FBGA A1 Ball Pad Corner 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-37 ProASICPLUS Flash Family FPGAs 144-FBGA Pin 144-FBGA Pin Pin APA075 Number Function APA150 Function APA300 Function APA450 Function Pin APA075 Number Function APA150 Function APA300 Function APA450 Function A1 I/O I/O I/O I/O D2 I/O I/O I/O I/O A2 I/O I/O I/O I/O D3 I/O I/O I/O I/O A3 I/O I/O I/O I/O D4 I/O I/O I/O I/O A4 I/O I/O I/O I/O D5 I/O I/O I/O I/O A5 I/O I/O I/O I/O D6 I/O I/O I/O I/O A6 GND GND GND GND D7 I/O I/O I/O I/O A7 I/O I/O I/O I/O D8 I/O I/O I/O I/O A8 VDD VDD VDD VDD D9 I/O I/O I/O I/O A9 I/O I/O I/O I/O D10 I/O I/O I/O I/O A10 I/O I/O I/O I/O D11 I/O I/O I/O I/O A11 I/O I/O I/O I/O D12 A12 I/O I/O I/O I/O E1 VDD VDD VDD VDD B1 I/O I/O I/O I/O E2 I/O I/O I/O I/O B2 GND GND GND GND E3 I/O I/O I/O I/O B3 I/O I/O I/O I/O E4 VDDP VDDP VDDP VDDP B4 I/O I/O I/O I/O E5 I/O I/O I/O I/O B5 I/O I/O I/O I/O E6 VDDP VDDP VDDP VDDP B6 I/O I/O I/O I/O E7 VDDP VDDP VDDP VDDP B7 I/O I/O I/O I/O E8 AVDD AVDD AVDD AVDD B8 I/O I/O I/O I/O E9 VDDP VDDP VDDP VDDP B9 I/O I/O I/O I/O E10 VDD VDD VDD VDD B10 I/O I/O I/O I/O E11 NPECL2 NPECL2 NPECL2 NPECL2 B11 GND GND GND GND E12 AGND AGND AGND AGND B12 I/O I/O I/O I/O F1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 C1 I/O I/O I/O I/O F2 AGND AGND AGND AGND C2 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 F3 C3 I/O I/O I/O I/O F4 I/O I/O I/O I/O C4 VDD VDD VDD VDD F5 GND GND GND GND C5 I/O I/O I/O I/O F6 GND GND GND GND C6 I/O I/O I/O I/O F7 GND GND GND GND C7 I/O I/O I/O I/O F8 I/O I/O I/O I/O C8 I/O I/O I/O I/O F9 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 C9 I/O I/O I/O I/O F10 GND GND GND GND C10 I/O I/O I/O I/O F11 C11 I/O I/O I/O I/O PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input C12 I/O I/O I/O I/O F12 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 D1 I/O I/O I/O I/O 2 -3 8 v5.2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 ProASICPLUS Flash Family FPGAs 144-FBGA Pin Pin APA075 Number Function 144-FBGA Pin APA150 Function APA300 Function APA450 Function G1 PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input G2 GND GND GND GND G3 AVDD AVDD AVDD AVDD G4 NPECL1 NPECL1 NPECL1 NPECL1 G5 GND GND GND GND G6 GND GND GND GND G7 GND GND GND GND G8 I/O I/O I/O I/O G9 I/O I/O I/O I/O G10 I/O I/O I/O I/O G11 I/O I/O I/O I/O G12 I/O I/O I/O I/O H1 VDD VDD VDD VDD H2 I/O I/O I/O I/O H3 I/O I/O I/O I/O H4 I/O I/O I/O I/O H5 VDD VDD VDD VDD H6 I/O I/O I/O I/O H7 I/O I/O I/O I/O H8 I/O I/O I/O I/O H9 I/O I/O I/O I/O H10 VDDP VDDP VDDP VDDP H11 I/O I/O I/O I/O H12 VDD VDD VDD VDD J1 I/O I/O I/O I/O J2 I/O I/O I/O I/O J3 VDDP VDDP VDDP VDDP J4 I/O I/O I/O I/O J5 I/O I/O I/O I/O J6 I/O I/O I/O I/O J7 VDD VDD VDD VDD J8 TCK TCK TCK TCK J9 I/O I/O I/O I/O J10 TDO TDO TDO TDO J11 I/O I/O I/O I/O J12 I/O I/O I/O I/O Pin APA075 Number Function v5.2 APA150 Function APA300 Function APA450 Function K1 I/O I/O I/O I/O K2 I/O I/O I/O I/O K3 I/O I/O I/O I/O K4 I/O I/O I/O I/O K5 I/O I/O I/O I/O K6 I/O I/O I/O I/O K7 GND GND GND GND K8 I/O I/O I/O I/O K9 I/O I/O I/O I/O K10 GND GND GND GND K11 I/O I/O I/O I/O K12 I/O I/O I/O I/O L1 GND GND GND GND L2 I/O I/O I/O I/O L3 I/O I/O I/O I/O L4 I/O I/O I/O I/O L5 VDDP VDDP VDDP VDDP L6 I/O I/O I/O I/O L7 I/O I/O I/O I/O L8 I/O I/O I/O I/O L9 TMS TMS TMS TMS L10 RCK RCK RCK RCK L11 I/O I/O I/O I/O L12 TRST TRST TRST TRST M1 I/O I/O I/O I/O M2 I/O I/O I/O I/O M3 I/O I/O I/O I/O M4 I/O I/O I/O I/O M5 I/O I/O I/O I/O M6 I/O I/O I/O I/O M7 I/O I/O I/O I/O M8 I/O I/O I/O I/O M9 TDI TDI TDI TDI M10 VDDP VDDP VDDP VDDP M11 VPP VPP VPP VPP M12 VPN VPN VPN VPN 2-39 ProASICPLUS Flash Family FPGAs 256-Pin FBGA A1 Ball Pad Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 2 -4 0 v5.2 ProASICPLUS Flash Family FPGAs 256-Pin FBGA 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function Pin Number APA150 Function APA300 Function APA450 Function APA600 Function A1 GND GND GND GND C4 I/O I/O I/O I/O A2 I/O I/O I/O I/O C5 I/O I/O I/O I/O A3 I/O I/O I/O I/O C6 I/O I/O I/O I/O A4 I/O I/O I/O I/O C7 I/O I/O I/O I/O A5 I/O I/O I/O I/O C8 I/O I/O I/O I/O A6 I/O I/O I/O I/O C9 I/O I/O I/O I/O A7 I/O I/O I/O I/O C10 I/O I/O I/O I/O A8 I/O I/O I/O I/O C11 I/O I/O I/O I/O A9 I/O I/O I/O I/O C12 I/O I/O I/O I/O A10 I/O I/O I/O I/O C13 I/O I/O I/O I/O A11 I/O I/O I/O I/O C14 I/O I/O I/O I/O A12 I/O I/O I/O I/O C15 I/O I/O I/O I/O A13 I/O I/O I/O I/O C16 I/O I/O I/O I/O A14 I/O I/O I/O I/O D1 I/O I/O I/O I/O A15 I/O I/O I/O I/O D2 I/O I/O I/O I/O A16 GND GND GND GND D3 I/O I/O I/O I/O B1 I/O I/O I/O I/O D4 I/O I/O I/O I/O B2 I/O I/O I/O I/O D5 I/O I/O I/O I/O B3 I/O I/O I/O I/O D6 I/O I/O I/O I/O B4 I/O I/O I/O I/O D7 I/O I/O I/O I/O B5 I/O I/O I/O I/O D8 I/O I/O I/O I/O B6 I/O I/O I/O I/O D9 I/O I/O I/O I/O B7 I/O I/O I/O I/O D10 I/O I/O I/O I/O B8 I/O I/O I/O I/O D11 I/O I/O I/O I/O B9 I/O I/O I/O I/O D12 I/O I/O I/O I/O B10 I/O I/O I/O I/O D13 I/O I/O I/O I/O B11 I/O I/O I/O I/O D14 I/O I/O I/O I/O B12 I/O I/O I/O I/O D15 I/O I/O I/O I/O B13 I/O I/O I/O I/O D16 I/O I/O I/O I/O B14 I/O I/O I/O I/O E1 I/O I/O I/O I/O B15 I/O I/O I/O I/O E2 I/O I/O I/O I/O B16 I/O I/O I/O I/O E3 I/O I/O I/O I/O C1 I/O I/O I/O I/O E4 I/O I/O I/O I/O C2 I/O I/O I/O I/O E5 I/O I/O I/O I/O C3 I/O I/O I/O I/O E6 VDDP VDDP VDDP VDDP v5.2 2-41 ProASICPLUS Flash Family FPGAs 256-Pin FBGA 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function Pin Number APA150 Function APA300 Function APA450 Function APA600 Function E7 VDDP VDDP VDDP VDDP G10 GND GND GND GND E8 I/O I/O I/O I/O G11 VDD VDD VDD VDD E9 I/O I/O I/O I/O G12 VDDP VDDP VDDP VDDP E10 VDDP VDDP VDDP VDDP G13 I/O I/O I/O I/O E11 VDDP VDDP VDDP VDDP G14 I/O I/O I/O I/O E12 I/O I/O I/O I/O G15 I/O I/O I/O I/O E13 I/O I/O I/O I/O G16 I/O I/O I/O I/O E14 I/O I/O I/O I/O H1 I/O / GL1 I/O / GL1 I/O / GL1 I/O / GL1 E15 I/O I/O I/O I/O H2 NPECL1 NPECL1 NPECL1 NPECL1 E16 I/O I/O I/O I/O H3 F1 I/O I/O I/O I/O H4 AGND AGND AGND AGND F2 I/O I/O I/O I/O H5 I/O I/O I/O I/O F3 I/O I/O I/O I/O H6 VDD VDD VDD VDD F4 I/O I/O I/O I/O H7 GND GND GND GND F5 VDDP VDDP VDDP VDDP H8 GND GND GND GND F6 GND GND GND GND H9 GND GND GND GND F7 VDD VDD VDD VDD H10 GND GND GND GND F8 VDD VDD VDD VDD H11 VDD VDD VDD VDD F9 VDD VDD VDD VDD H12 I/O I/O I/O I/O F10 VDD VDD VDD VDD H13 F11 GND GND GND GND H14 NPECL2 NPECL2 NPECL2 NPECL2 F12 VDDP VDDP VDDP VDDP H15 AGND AGND AGND AGND F13 I/O I/O I/O I/O H16 I/O / GL4 I/O / GL4 I/O / GL4 I/O / GL4 F14 I/O I/O I/O I/O J1 I/O / GL2 I/O / GL2 I/O / GL2 I/O / GL2 F15 I/O I/O I/O I/O J2 F16 I/O I/O I/O I/O PPECL1 / Input PPECL1 / Input PPECL1 / Input PPECL1 / Input G1 I/O I/O I/O I/O J3 AVDD AVDD AVDD AVDD G2 I/O I/O I/O I/O J4 I/O I/O I/O I/O G3 I/O I/O I/O I/O J5 I/O I/O I/O I/O G4 I/O I/O I/O I/O J6 VDD VDD VDD VDD G5 VDDP VDDP VDDP VDDP J7 GND GND GND GND G6 VDD VDD VDD VDD J8 GND GND GND GND G7 GND GND GND GND J9 GND GND GND GND G8 GND GND GND GND J10 GND GND GND GND G9 GND GND GND GND J11 VDD VDD VDD VDD 2 -4 2 v5.2 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX1 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 I/O / GLMX2 ProASICPLUS Flash Family FPGAs 256-Pin FBGA 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function Pin Number APA150 Function APA300 Function APA450 Function APA600 Function J12 I/O I/O I/O I/O L14 I/O I/O I/O I/O J13 PPECL2 / Input PPECL2 / Input PPECL2 / Input PPECL2 / Input L15 I/O I/O I/O I/O L16 I/O I/O I/O I/O J14 I/O I/O I/O I/O M1 I/O I/O I/O I/O J15 AVDD AVDD AVDD AVDD M2 I/O I/O I/O I/O J16 I/O / GL3 I/O / GL3 I/O / GL3 I/O / GL3 M3 I/O I/O I/O I/O K1 I/O I/O I/O I/O M4 I/O I/O I/O I/O K2 I/O I/O I/O I/O M5 I/O I/O I/O I/O K3 I/O I/O I/O I/O M6 VDDP VDDP VDDP VDDP K4 I/O I/O I/O I/O M7 VDDP VDDP VDDP VDDP K5 VDDP VDDP VDDP VDDP M8 I/O I/O I/O I/O K6 VDD VDD VDD VDD M9 I/O I/O I/O I/O K7 GND GND GND GND M10 VDDP VDDP VDDP VDDP K8 GND GND GND GND M11 VDDP VDDP VDDP VDDP K9 GND GND GND GND M12 I/O I/O I/O I/O K10 GND GND GND GND M13 I/O I/O I/O I/O K11 VDD VDD VDD VDD M14 I/O I/O I/O I/O K12 VDDP VDDP VDDP VDDP M15 I/O I/O I/O I/O K13 I/O I/O I/O I/O M16 I/O I/O I/O I/O K14 I/O I/O I/O I/O N1 I/O I/O I/O I/O K15 I/O I/O I/O I/O N2 I/O I/O I/O I/O K16 I/O I/O I/O I/O N3 I/O I/O I/O I/O L1 I/O I/O I/O I/O N4 I/O I/O I/O I/O L2 I/O I/O I/O I/O N5 I/O I/O I/O I/O L3 I/O I/O I/O I/O N6 I/O I/O I/O I/O L4 I/O I/O I/O I/O N7 I/O I/O I/O I/O L5 VDDP VDDP VDDP VDDP N8 I/O I/O I/O I/O L6 GND GND GND GND N9 I/O I/O I/O I/O L7 VDD VDD VDD VDD N10 I/O I/O I/O I/O L8 VDD VDD VDD VDD N11 I/O I/O I/O I/O L9 VDD VDD VDD VDD N12 I/O I/O I/O I/O L10 VDD VDD VDD VDD N13 I/O I/O I/O I/O L11 GND GND GND GND N14 RCK RCK RCK RCK L12 VDDP VDDP VDDP VDDP N15 I/O I/O I/O I/O L13 I/O I/O I/O I/O N16 I/O I/O I/O I/O v5.2 2-43 ProASICPLUS Flash Family FPGAs 256-Pin FBGA 256-Pin FBGA Pin Number APA150 Function APA300 Function APA450 Function APA600 Function Pin Number APA150 Function APA300 Function APA450 Function APA600 Function P1 I/O I/O I/O I/O T4 I/O I/O I/O I/O P2 I/O I/O I/O I/O T5 I/O I/O I/O I/O P3 I/O I/O I/O I/O T6 I/O I/O I/O I/O P4 I/O I/O I/O I/O T7 I/O I/O I/O I/O P5 I/O I/O I/O I/O T8 I/O I/O I/O I/O P6 I/O I/O I/O I/O T9 I/O I/O I/O I/O P7 I/O I/O I/O I/O T10 I/O I/O I/O I/O P8 I/O I/O I/O I/O T11 I/O I/O I/O I/O P9 I/O I/O I/O I/O T12 I/O I/O I/O I/O P10 I/O I/O I/O I/O T13 I/O I/O I/O I/O P11 I/O I/O I/O I/O T14 I/O I/O I/O I/O P12 I/O I/O I/O I/O T15 TMS TMS TMS TMS P13 TCK TCK TCK TCK T16 GND GND GND GND P14 VPP VPP VPP VPP P15 TRST TRST TRST TRST P16 I/O I/O I/O I/O R1 I/O I/O I/O I/O R2 I/O I/O I/O I/O R3 I/O I/O I/O I/O R4 I/O I/O I/O I/O R5 I/O I/O I/O I/O R6 I/O I/O I/O I/O R7 I/O I/O I/O I/O R8 I/O I/O I/O I/O R9 I/O I/O I/O I/O R10 I/O I/O I/O I/O R11 I/O I/O I/O I/O R12 I/O I/O I/O I/O R13 I/O I/O I/O I/O R14 TDI TDI TDI TDI R15 VPN VPN VPN VPN R16 TDO TDO TDO TDO T1 GND GND GND GND T2 I/O I/O I/O I/O T3 I/O I/O I/O I/O 2 -4 4 v5.2 ProASICPLUS Flash Family FPGAs 484-Pin FBGA A1 Ball Pad Corner 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-45 ProASICPLUS Flash Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function A1 GND GND B15 I/O I/O D7 I/O I/O A2 GND GND B16 I/O I/O D8 I/O I/O A3 VDDP VDDP B17 I/O I/O D9 I/O I/O A4 I/O I/O B18 I/O I/O D10 I/O I/O A5 I/O I/O B19 I/O I/O D11 I/O I/O A6 I/O I/O B20 I/O I/O D12 I/O I/O A7 I/O I/O B21 VDDP VDDP D13 I/O I/O A8 I/O I/O B22 GND GND D14 I/O I/O A9 I/O I/O C1 VDDP VDDP D15 I/O I/O A10 I/O I/O C2 NC I/O D16 I/O I/O A11 I/O I/O C3 I/O I/O D17 I/O I/O A12 I/O I/O C4 I/O I/O D18 I/O I/O A13 I/O I/O C5 GND GND D19 GND GND A14 I/O I/O C6 I/O I/O D20 I/O I/O A15 I/O I/O C7 I/O I/O D21 I/O I/O A16 I/O I/O C8 VDD VDD D22 I/O I/O A17 I/O I/O C9 VDD VDD E1 I/O I/O A18 I/O I/O C10 I/O I/O E2 NC I/O A19 I/O I/O C11 I/O I/O E3 GND GND A20 VDDP VDDP C12 NC I/O E4 I/O I/O A21 GND GND C13 NC I/O E5 I/O I/O A22 GND GND C14 VDD VDD E6 I/O I/O B1 GND GND C15 VDD VDD E7 I/O I/O B2 VDDP VDDP C16 NC I/O E8 I/O I/O B3 I/O I/O C17 I/O I/O E9 I/O I/O B4 I/O I/O C18 GND GND E10 I/O I/O B5 I/O I/O C19 I/O I/O E11 I/O I/O B6 I/O I/O C20 I/O I/O E12 I/O I/O B7 I/O I/O C21 I/O I/O E13 I/O I/O B8 I/O I/O C22 VDDP VDDP E14 I/O I/O B9 I/O I/O D1 I/O I/O E15 I/O I/O B10 I/O I/O D2 I/O I/O E16 I/O I/O B11 I/O I/O D3 NC I/O E17 I/O I/O B12 I/O I/O D4 GND GND E18 I/O I/O B13 I/O I/O D5 I/O I/O E19 I/O I/O B14 I/O I/O D6 I/O I/O E20 GND GND 2 -4 6 v5.2 ProASICPLUS Flash Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function E21 I/O I/O G13 I/O I/O J5 I/O I/O E22 I/O I/O G14 I/O I/O J6 I/O I/O F1 I/O I/O G15 I/O I/O J7 I/O I/O F2 I/O I/O G16 I/O I/O J8 VDDP VDDP F3 I/O I/O G17 I/O I/O J9 GND GND F4 I/O I/O G18 I/O I/O J10 VDD VDD F5 I/O I/O G19 I/O I/O J11 VDD VDD F6 I/O I/O G20 I/O I/O J12 VDD VDD F7 I/O I/O G21 I/O I/O J13 VDD VDD F8 I/O I/O G22 I/O I/O J14 GND GND F9 I/O I/O H1 I/O I/O J15 VDDP VDDP F10 I/O I/O H2 I/O I/O J16 I/O I/O F11 I/O I/O H3 VDD VDD J17 I/O I/O F12 I/O I/O H4 I/O I/O J18 I/O I/O F13 I/O I/O H5 I/O I/O J19 I/O I/O F14 I/O I/O H6 I/O I/O J20 NC I/O F15 I/O I/O H7 I/O I/O J21 I/O I/O F16 I/O I/O H8 I/O I/O J22 I/O I/O F17 I/O I/O H9 VDDP VDDP K1 I/O I/O F18 I/O I/O H10 VDDP VDDP K2 I/O I/O F19 I/O I/O H11 I/O I/O K3 NC I/O F20 I/O I/O H12 I/O I/O K4 I/O I/O F21 I/O I/O H13 VDDP VDDP K5 I/O I/O F22 NC I/O H14 VDDP VDDP K6 I/O I/O G1 I/O I/O H15 I/O I/O K7 I/O I/O G2 I/O I/O H16 I/O I/O K8 VDDP VDDP G3 NC I/O H17 I/O I/O K9 VDD VDD G4 I/O I/O H18 I/O I/O K10 GND GND G5 I/O I/O H19 I/O I/O K11 GND GND G6 I/O I/O H20 VDD VDD K12 GND GND G7 I/O I/O H21 I/O I/O K13 GND GND G8 I/O I/O H22 I/O I/O K14 VDD VDD G9 I/O I/O J1 I/O I/O K15 VDDP VDDP G10 I/O I/O J2 I/O I/O K16 I/O I/O G11 I/O I/O J3 NC I/O K17 I/O I/O G12 I/O I/O J4 I/O I/O K18 I/O I/O v5.2 2-47 ProASICPLUS Flash Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function K19 I/O I/O M10 GND GND P1 I/O I/O K20 I/O I/O M11 GND GND P2 I/O I/O K21 I/O I/O M12 GND GND P3 I/O I/O K22 I/O I/O M13 GND GND P4 I/O I/O L1 NC I/O M14 VDD VDD P5 I/O I/O L2 I/O I/O M15 I/O I/O P6 I/O I/O L3 I/O I/O M16 I/O I/O I/O / GL1 I/O / GL1 PPECL2 / Input P7 L4 PPECL2 / Input P8 VDDP VDDP M17 I/O I/O P9 GND GND M18 AVDD AVDD P10 VDD VDD M19 I/O / GL3 I/O / GL3 P11 VDD VDD M20 I/O I/O P12 VDD VDD M21 I/O I/O P13 VDD VDD M22 I/O I/O P14 GND GND N1 I/O I/O P15 VDDP VDDP N2 I/O I/O P16 I/O I/O N3 NC I/O P17 I/O I/O N4 I/O I/O P18 I/O I/O N5 I/O I/O P19 I/O I/O N6 I/O I/O P20 NC I/O N7 I/O I/O P21 I/O I/O N8 VDDP VDDP P22 I/O I/O N9 VDD VDD R1 I/O I/O N10 GND GND R2 I/O I/O N11 GND GND R3 VDD VDD N12 GND GND R4 I/O I/O N13 GND GND R5 I/O I/O N14 VDD VDD R6 I/O I/O N15 VDDP VDDP R7 I/O I/O N16 I/O I/O R8 I/O I/O N17 I/O I/O R9 VDDP VDDP N18 I/O I/O R10 VDDP VDDP R11 I/O I/O R12 I/O I/O R13 VDDP VDDP R14 VDDP VDDP L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 2 -4 8 NPECL1 NPECL1 I/O / GLMX1 I/O / GLMX1 AGND I/O VDD GND GND GND GND VDD I/O AGND I/O VDD GND GND GND GND VDD I/O I/O / GLMX2 I/O / GLMX2 NPECL2 AGND I/O / GL4 I/O I/O I/O I/O I/O I/O I/O / GL2 NPECL2 AGND I/O / GL4 I/O I/O I/O I/O I/O I/O I/O / GL2 PPECL1 / Input PPECL1 / Input M6 AVDD AVDD N19 I/O I/O M7 I/O I/O N20 NC I/O M8 I/O I/O N21 I/O I/O M9 VDD VDD N22 I/O I/O v5.2 ProASICPLUS Flash Family FPGAs 484-Pin FBGA 484-Pin FBGA 484-Pin FBGA Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function R15 I/O I/O U7 I/O I/O V21 NC I/O R16 I/O I/O U8 I/O I/O V22 I/O I/O R17 I/O I/O U9 I/O I/O W1 NC I/O R18 I/O I/O U10 I/O I/O W2 I/O I/O R19 I/O I/O U11 I/O I/O W3 I/O I/O R20 VDD VDD U12 I/O I/O W4 GND GND R21 I/O I/O U13 I/O I/O W5 I/O I/O R22 I/O I/O U14 I/O I/O W6 I/O I/O T1 I/O I/O U15 I/O I/O W7 I/O I/O T2 I/O I/O U16 TCK TCK W8 I/O I/O T3 NC I/O U17 VPP VPP W9 I/O I/O T4 I/O I/O U18 TRST TRST W10 I/O I/O T5 I/O I/O U19 I/O I/O W11 I/O I/O T6 I/O I/O U20 NC I/O W12 I/O I/O T7 I/O I/O U21 I/O I/O W13 I/O I/O T8 I/O I/O U22 I/O I/O W14 I/O I/O T9 I/O I/O V1 I/O I/O W15 I/O I/O T10 I/O I/O V2 I/O I/O W16 I/O I/O T11 I/O I/O V3 GND GND W17 I/O I/O T12 I/O I/O V4 I/O I/O W18 TMS TMS T13 I/O I/O V5 I/O I/O W19 GND GND T14 I/O I/O V6 I/O I/O W20 NC I/O T15 I/O I/O V7 I/O I/O W21 NC I/O T16 I/O I/O V8 I/O I/O W22 I/O I/O T17 RCK RCK V9 I/O I/O Y1 VDDP VDDP T18 I/O I/O V10 I/O I/O Y2 I/O I/O T19 I/O I/O V11 I/O I/O Y3 I/O I/O T20 NC I/O V12 I/O I/O Y4 I/O I/O T21 I/O I/O V13 I/O I/O Y5 GND GND T22 I/O I/O V14 I/O I/O Y6 I/O I/O U1 I/O I/O V15 I/O I/O Y7 I/O I/O U2 I/O I/O V16 I/O I/O Y8 VDD VDD U3 I/O I/O V17 TDI TDI Y9 VDD VDD U4 I/O I/O V18 VPN VPN Y10 I/O I/O U5 I/O I/O V19 TDO TDO Y11 I/O I/O U6 I/O I/O V20 GND GND Y12 I/O I/O v5.2 2-49 ProASICPLUS Flash Family FPGAs 484-Pin FBGA 484-Pin FBGA Pin Number APA450 Function APA600 Function Pin Number APA450 Function APA600 Function Y13 I/O I/O AB5 I/O I/O Y14 VDD VDD AB6 I/O I/O Y15 VDD VDD AB7 I/O I/O Y16 I/O I/O AB8 I/O I/O Y17 I/O I/O AB9 I/O I/O Y18 GND GND AB10 I/O I/O Y19 I/O I/O AB11 I/O I/O Y20 I/O I/O AB12 I/O I/O Y21 NC I/O AB13 I/O I/O Y22 VDDP VDDP AB14 I/O I/O AA1 GND GND AB15 I/O I/O AA2 VDDP VDDP AB16 I/O I/O AA3 I/O I/O AB17 I/O I/O AA4 I/O I/O AB18 NC I/O AA5 I/O I/O AB19 I/O I/O AA6 I/O I/O AB20 VDDP VDDP AA7 I/O I/O AB21 GND GND AA8 I/O I/O AB22 GND GND AA9 I/O I/O AA10 I/O I/O AA11 I/O I/O AA12 I/O I/O AA13 I/O I/O AA14 I/O I/O AA15 I/O I/O AA16 I/O I/O AA17 I/O I/O AA18 NC I/O AA19 NC I/O AA20 I/O I/O AA21 VDDP VDDP AA22 GND GND AB1 GND GND AB2 GND GND AB3 VDDP VDDP AB4 I/O I/O 2 -5 0 v5.2 ProASICPLUS Flash Family FPGAs 676-Pin FBGA A1 Ball Pad Corner 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-51 ProASICPLUS Flash Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function A1 GND GND B10 I/O I/O C19 I/O I/O A2 GND GND B11 I/O I/O C20 I/O I/O A3 I/O I/O B12 I/O I/O C21 I/O I/O A4 I/O I/O B13 I/O I/O C22 I/O I/O A5 I/O I/O B14 I/O I/O C23 I/O I/O A6 I/O I/O B15 I/O I/O C24 I/O I/O A7 I/O I/O B16 I/O I/O C25 I/O I/O A8 I/O I/O B17 I/O I/O C26 I/O I/O A9 I/O I/O B18 I/O I/O D1 I/O I/O A10 I/O I/O B19 I/O I/O D2 I/O I/O A11 I/O I/O B20 I/O I/O D3 GND GND A12 I/O I/O B21 I/O I/O D4 I/O I/O A13 I/O I/O B22 I/O I/O D5 I/O I/O A14 I/O I/O B23 I/O I/O D6 I/O I/O A15 I/O I/O B24 I/O I/O D7 I/O I/O A16 I/O I/O B25 GND GND D8 I/O I/O A17 I/O I/O B26 GND GND D9 I/O I/O A18 I/O I/O C1 GND GND D10 I/O I/O A19 I/O I/O C2 GND GND D11 I/O I/O A20 I/O I/O C3 GND GND D12 I/O I/O A21 I/O I/O C4 GND GND D13 I/O I/O A22 I/O I/O C5 I/O I/O D14 I/O I/O A23 I/O I/O C6 I/O I/O D15 I/O I/O A24 I/O I/O C7 I/O I/O D16 I/O I/O A25 GND GND C8 I/O I/O D17 I/O I/O A26 GND GND C9 I/O I/O D18 I/O I/O B1 GND GND C10 I/O I/O D19 I/O I/O B2 GND GND C11 I/O I/O D20 I/O I/O B3 GND GND C12 I/O I/O D21 I/O I/O B4 GND GND C13 I/O I/O D22 I/O I/O B5 I/O I/O C14 I/O I/O D23 I/O I/O B6 I/O I/O C15 I/O I/O D24 I/O I/O B7 I/O I/O C16 I/O I/O D25 I/O I/O B8 I/O I/O C17 I/O I/O D26 I/O I/O B9 I/O I/O C18 I/O I/O E1 I/O I/O 2 -5 2 v5.2 ProASICPLUS Flash Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function E2 I/O I/O F11 I/O I/O G20 NC NC E3 I/O I/O F12 I/O I/O G21 I/O I/O E4 I/O I/O F13 I/O I/O G22 I/O I/O E5 I/O I/O F14 I/O I/O G23 I/O I/O E6 I/O I/O F15 I/O I/O G24 I/O I/O E7 I/O I/O F16 I/O I/O G25 I/O I/O E8 I/O I/O F17 I/O I/O G26 I/O I/O E9 I/O I/O F18 I/O I/O H1 I/O I/O E10 I/O I/O F19 I/O I/O H2 I/O I/O E11 I/O I/O F20 I/O I/O H3 I/O I/O E12 I/O I/O F21 I/O I/O H4 I/O I/O E13 I/O I/O F22 I/O I/O H5 I/O I/O E14 I/O I/O F23 I/O I/O H6 I/O I/O E15 I/O I/O F24 I/O I/O H7 VDDP VDDP E16 I/O I/O F25 I/O I/O H8 VDD VDD E17 I/O I/O F26 I/O I/O H9 VDDP VDDP E18 I/O I/O G1 I/O I/O H10 VDDP VDDP E19 I/O I/O G2 I/O I/O H11 VDDP VDDP E20 I/O I/O G3 I/O I/O H12 VDDP VDDP E21 I/O I/O G4 I/O I/O H13 VDDP VDDP E22 I/O I/O G5 I/O I/O H14 VDDP VDDP E23 I/O I/O G6 I/O I/O H15 VDDP VDDP E24 I/O I/O G7 I/O I/O H16 VDDP VDDP E25 I/O I/O G8 VDD VDD H17 VDDP VDDP E26 I/O I/O G9 NC NC H18 VDDP VDDP F1 I/O I/O G10 I/O I/O H19 VDD VDD F2 I/O I/O G11 NC NC H20 VDD VDD F3 I/O I/O G12 I/O I/O H21 I/O I/O F4 I/O I/O G13 NC NC H22 I/O I/O F5 GND GND G14 I/O I/O H23 I/O I/O F6 I/O I/O G15 NC NC H24 I/O I/O F7 NC NC G16 I/O I/O H25 I/O I/O F8 I/O I/O G17 NC NC H26 I/O I/O F9 I/O I/O G18 I/O I/O J1 I/O I/O F10 I/O I/O G19 VDDP VDDP J2 I/O I/O v5.2 2-53 ProASICPLUS Flash Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function J3 I/O I/O K12 GND GND L21 I/O I/O J4 I/O I/O K13 GND GND L22 I/O I/O J5 I/O I/O K14 GND GND L23 I/O I/O J6 I/O I/O K15 GND GND L24 I/O I/O J7 NC NC K16 GND GND L25 I/O I/O J8 VDDP VDDP K17 GND GND L26 I/O I/O J9 VDD VDD K18 VDD VDD M1 I/O I/O J10 VDD VDD K19 VDDP VDDP M2 I/O I/O J11 VDD VDD K20 I/O I/O M3 I/O I/O J12 VDD VDD K21 I/O I/O M4 I/O I/O J13 VDD VDD K22 I/O I/O M5 I/O I/O J14 VDD VDD K23 I/O I/O M6 I/O I/O J15 VDD VDD K24 I/O I/O M7 I/O I/O J16 VDD VDD K25 I/O I/O M8 VDDP VDDP J17 VDD VDD K26 I/O I/O M9 VDD VDD J18 VDD VDD L1 I/O I/O M10 GND GND J19 VDDP VDDP L2 I/O I/O M11 GND GND J20 NC NC L3 I/O I/O M12 GND GND J21 I/O I/O L4 I/O I/O M13 GND GND J22 I/O I/O L5 I/O I/O M14 GND GND J23 I/O I/O L6 I/O I/O M15 GND GND J24 I/O I/O L7 NC NC M16 GND GND J25 I/O I/O L8 VDDP VDDP M17 GND GND J26 I/O I/O L9 VDD VDD M18 VDD VDD K1 I/O I/O L10 GND GND M19 VDDP VDDP K2 I/O I/O L11 GND GND M20 I/O I/O K3 I/O I/O L12 GND GND M21 I/O I/O K4 I/O I/O L13 GND GND M22 I/O I/O K5 I/O I/O L14 GND GND M23 I/O I/O K6 I/O I/O L15 GND GND M24 I/O I/O K7 I/O I/O L16 GND GND M25 I/O I/O K8 VDDP VDDP L17 GND GND M26 I/O I/O K9 VDD VDD L18 VDD VDD N1 I/O / GL1 I/O / GL1 K10 GND GND L19 VDDP VDDP N2 AGND AGND K11 GND GND L20 NC NC N3 2 -5 4 v5.2 I/O / GLMX1 I/O / GLMX1 ProASICPLUS Flash Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function N4 I/O I/O P12 GND GND R20 NC NC N5 NPECL1 NPECL1 P13 GND GND R21 I/O I/O N6 I/O I/O P14 GND GND R22 I/O I/O N7 NC NC P15 GND GND R23 I/O I/O N8 VDDP VDDP P16 GND GND R24 I/O I/O N9 VDD VDD P17 GND GND R25 I/O I/O N10 GND GND P18 VDD VDD R26 I/O I/O N11 GND GND P19 VDDP VDDP T1 I/O I/O N12 GND GND P20 I/O I/O T2 I/O I/O N13 GND GND P21 I/O I/O T3 I/O I/O N14 GND GND P22 T4 I/O I/O N15 GND GND P23 I/O I/O T5 I/O I/O N16 GND GND P24 I/O I/O GND GND PPECL2 / Input T6 N17 PPECL2 / Input T7 I/O I/O P25 AVDD AVDD T8 VDDP VDDP P26 AGND AGND T9 VDD VDD R1 I/O I/O T10 GND GND R2 I/O I/O T11 GND GND R3 I/O I/O T12 GND GND R4 I/O I/O T13 GND GND R5 I/O I/O T14 GND GND R6 I/O I/O T15 GND GND R7 NC NC T16 GND GND R8 VDDP VDDP T17 GND GND R9 VDD VDD T18 VDD VDD R10 GND GND T19 VDDP VDDP R11 GND GND T20 I/O I/O R12 GND GND T21 I/O I/O R13 GND GND T22 I/O I/O T23 I/O I/O T24 I/O I/O T25 I/O I/O N18 N19 N20 N21 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 VDD VDDP NC I/O I/O / GL3 I/O NPECL2 I/O / GL4 I/O I/O / GL2 AVDD I/O I/O VDD VDDP NC I/O I/O / GL3 I/O NPECL2 I/O / GL4 I/O I/O / GL2 AVDD I/O I/O I/O / GLMX2 I/O / GLMX2 PPECL1 / Input PPECL1 / Input P6 I/O I/O R14 GND GND P7 I/O I/O R15 GND GND P8 VDDP VDDP R16 GND GND P9 VDD VDD R17 GND GND T26 I/O I/O P10 GND GND R18 VDD VDD U1 I/O I/O P11 GND GND R19 VDDP VDDP U2 I/O I/O v5.2 2-55 ProASICPLUS Flash Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function U3 I/O I/O V12 VDD VDD W21 I/O I/O U4 I/O I/O V13 VDD VDD W22 I/O I/O U5 I/O I/O V14 VDD VDD W23 I/O I/O U6 I/O I/O V15 VDD VDD W24 I/O I/O U7 NC NC V16 VDD VDD W25 I/O I/O U8 VDDP VDDP V17 VDD VDD W26 I/O I/O U9 VDD VDD V18 VDD VDD Y1 I/O I/O U10 GND GND V19 VDDP VDDP Y2 I/O I/O U11 GND GND V20 I/O I/O Y3 I/O I/O U12 GND GND V21 I/O I/O Y4 I/O I/O U13 GND GND V22 I/O I/O Y5 I/O I/O U14 GND GND V23 I/O I/O Y6 I/O I/O U15 GND GND V24 I/O I/O Y7 I/O I/O U16 GND GND V25 I/O I/O Y8 VDDP VDDP U17 GND GND V26 I/O I/O Y9 NC NC U18 VDD VDD W1 I/O I/O Y10 I/O I/O U19 VDDP VDDP W2 I/O I/O Y11 NC NC U20 NC NC W3 I/O I/O Y12 I/O I/O U21 I/O I/O W4 I/O I/O Y13 NC NC U22 I/O I/O W5 I/O I/O Y14 I/O I/O U23 I/O I/O W6 I/O I/O Y15 NC NC U24 I/O I/O W7 VDD VDD Y16 I/O I/O U25 I/O I/O W8 VDD VDD Y17 NC NC U26 I/O I/O W9 VDDP VDDP Y18 I/O I/O V1 I/O I/O W10 VDDP VDDP Y19 VDD VDD V2 I/O I/O W11 VDDP VDDP Y20 VPP VPP V3 I/O I/O W12 VDDP VDDP Y21 I/O I/O V4 I/O I/O W13 VDDP VDDP Y22 I/O I/O V5 I/O I/O W14 VDDP VDDP Y23 I/O I/O V6 I/O I/O W15 VDDP VDDP Y24 I/O I/O V7 I/O I/O W16 VDDP VDDP Y25 I/O I/O V8 VDDP VDDP W17 VDDP VDDP Y26 I/O I/O V9 VDD VDD W18 VDDP VDDP AA1 I/O I/O V10 VDD VDD W19 VDD VDD AA2 I/O I/O V11 VDD VDD W20 VDDP VDDP AA3 I/O I/O 2 -5 6 v5.2 ProASICPLUS Flash Family FPGAs 676-Pin FBGA 676-Pin FBGA 676-Pin FBGA Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function AA4 I/O I/O AB13 I/O I/O AC22 TMS TMS AA5 I/O I/O AB14 I/O I/O AC23 RCK RCK AA6 GND GND AB15 I/O I/O AC24 I/O I/O AA7 I/O I/O AB16 I/O I/O AC25 I/O I/O AA8 I/O I/O AB17 I/O I/O AC26 I/O I/O AA9 I/O I/O AB18 I/O I/O AD1 I/O I/O AA10 I/O I/O AB19 I/O I/O AD2 I/O I/O AA11 I/O I/O AB20 I/O I/O AD3 I/O I/O AA12 I/O I/O AB21 TCK TCK AD4 I/O I/O AA13 I/O I/O AB22 TRST TRST AD5 I/O I/O AA14 I/O I/O AB23 I/O I/O AD6 I/O I/O AA15 I/O I/O AB24 I/O I/O AD7 I/O I/O AA16 I/O I/O AB25 I/O I/O AD8 I/O I/O AA17 I/O I/O AB26 I/O I/O AD9 I/O I/O AA18 I/O I/O AC1 I/O I/O AD10 I/O I/O AA19 I/O I/O AC2 I/O I/O AD11 I/O I/O AA20 I/O I/O AC3 I/O I/O AD12 I/O I/O AA21 TDO TDO AC4 I/O I/O AD13 I/O I/O AA22 GND GND AC5 GND GND AD14 I/O I/O AA23 GND GND AC6 I/O I/O AD15 I/O I/O AA24 I/O I/O AC7 I/O I/O AD16 I/O I/O AA25 I/O I/O AC8 I/O I/O AD17 I/O I/O AA26 I/O I/O AC9 GND GND AD18 I/O I/O AB1 I/O I/O AC10 I/O I/O AD19 I/O I/O AB2 I/O I/O AC11 I/O I/O AD20 I/O I/O AB3 I/O I/O AC12 I/O I/O AD21 I/O I/O AB4 I/O I/O AC13 I/O I/O AD22 I/O I/O AB5 I/O I/O AC14 I/O I/O AD23 TDI TDI AB6 GND GND AC15 I/O I/O AD24 VPN VPN AB7 GND GND AC16 I/O I/O AD25 I/O I/O AB8 I/O I/O AC17 I/O I/O AD26 I/O I/O AB9 I/O I/O AC18 I/O I/O AE1 GND GND AB10 I/O I/O AC19 I/O I/O AE2 GND GND AB11 I/O I/O AC20 I/O I/O AE3 GND GND AB12 I/O I/O AC21 I/O I/O AE4 I/O I/O v5.2 2-57 ProASICPLUS Flash Family FPGAs 676-Pin FBGA 676-Pin FBGA Pin Number APA600 Function APA750 Function Pin Number APA600 Function APA750 Function AE5 I/O I/O AF14 I/O I/O AE6 I/O I/O AF15 I/O I/O AE7 I/O I/O AF16 I/O I/O AE8 I/O I/O AF17 I/O I/O AE9 I/O I/O AF18 I/O I/O AE10 I/O I/O AF19 I/O I/O AE11 I/O I/O AF20 I/O I/O AE12 I/O I/O AF21 I/O I/O AE13 I/O I/O AF22 I/O I/O AE14 I/O I/O AF23 I/O I/O AE15 I/O I/O AF24 I/O I/O AE16 I/O I/O AF25 GND GND AE17 I/O I/O AF26 GND GND AE18 I/O I/O AE19 I/O I/O AE20 I/O I/O AE21 I/O I/O AE22 I/O I/O AE23 I/O I/O AE24 I/O I/O AE25 GND GND AE26 GND GND AF1 GND GND AF2 GND GND AF3 GND GND AF4 GND GND AF5 I/O I/O AF6 I/O I/O AF7 I/O I/O AF8 I/O I/O AF9 I/O I/O AF10 I/O I/O AF11 I/O I/O AF12 I/O I/O AF13 I/O I/O 2 -5 8 v5.2 ProASICPLUS Flash Family FPGAs 896-Pin FBGA A1 Ball Pad Corner 3029 2827 2625 2423 22 2120191817 16 151413 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-59 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function A2 GND GND B7 I/O I/O C11 I/O I/O A3 GND GND B8 I/O I/O C12 I/O I/O A4 I/O I/O B9 I/O I/O C13 I/O I/O A5 GND GND B10 I/O I/O C14 I/O I/O A6 I/O I/O B11 I/O I/O C15 I/O I/O A7 GND GND B12 I/O I/O C16 I/O I/O A8 I/O I/O B13 I/O I/O C17 I/O I/O A9 I/O I/O B14 I/O I/O C18 I/O I/O A10 I/O I/O B15 I/O I/O C19 I/O I/O A11 I/O I/O B16 I/O I/O C20 I/O I/O A12 I/O I/O B17 I/O I/O C21 I/O I/O A13 I/O I/O B18 I/O I/O C22 I/O I/O A14 I/O I/O B19 I/O I/O C23 I/O I/O A15 I/O I/O B20 I/O I/O C24 I/O I/O A16 I/O I/O B21 I/O I/O C25 I/O I/O A17 I/O I/O B22 I/O I/O C26 VDDP VDDP A18 I/O I/O B23 I/O I/O C27 I/O I/O A19 I/O I/O B24 I/O I/O C28 VDD VDD A20 I/O I/O B25 VDD VDD C29 NC I/O A21 I/O I/O B26 I/O I/O C30 GND GND A22 I/O I/O B27 VDD VDD D1 I/O I/O A23 I/O I/O B28 I/O I/O D2 VDD VDD A24 GND GND B29 GND GND D3 I/O I/O A25 I/O I/O B30 GND GND D4 GND GND A26 GND GND C1 GND GND D5 I/O I/O A27 I/O I/O C2 I/O I/O D6 I/O I/O A28 GND GND C3 VDD VDD D7 I/O I/O A29 GND GND C4 I/O I/O D8 I/O I/O B1 GND GND C5 VDDP VDDP D9 I/O I/O B2 GND GND C6 I/O I/O D10 I/O I/O B3 I/O I/O C7 I/O I/O D11 I/O I/O B4 VDD VDD C8 I/O I/O D12 I/O I/O B5 I/O I/O C9 I/O I/O D13 I/O I/O B6 VDD VDD C10 I/O I/O D14 I/O I/O 2 -6 0 v5.2 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function D15 I/O I/O E19 I/O I/O F23 I/O I/O D16 I/O I/O E20 I/O I/O F24 I/O I/O D17 I/O I/O E21 I/O I/O F25 GND GND D18 I/O I/O E22 I/O I/O F26 I/O I/O D19 I/O I/O E23 I/O I/O F27 I/O I/O D20 I/O I/O E24 VDDP VDDP F28 I/O I/O D21 I/O I/O E25 I/O I/O F29 VDD VDD D22 I/O I/O E26 VDD VDD F30 I/O I/O D23 I/O I/O E27 I/O I/O G1 GND GND D24 I/O I/O E28 VDDP VDDP G2 I/O I/O D25 I/O I/O E29 I/O I/O G3 I/O I/O D26 I/O I/O E30 GND GND G4 I/O I/O D27 GND GND F1 I/O I/O G5 VDDP VDDP D28 I/O I/O F2 VDD VDD G6 I/O I/O D29 VDD VDD F3 I/O I/O G7 VDD VDD D30 I/O I/O F4 I/O I/O G8 I/O I/O E1 GND GND F5 I/O I/O G9 VDDP VDDP E2 I/O I/O F6 GND GND G10 I/O I/O E3 VDDP VDDP F7 I/O I/O G11 I/O I/O E4 I/O I/O F8 I/O I/O G12 I/O I/O E5 VDD VDD F9 I/O I/O G13 I/O I/O E6 I/O I/O F10 I/O I/O G14 I/O I/O E7 VDDP VDDP F11 I/O I/O G15 I/O I/O E8 I/O I/O F12 I/O I/O G16 I/O I/O E9 I/O I/O F13 I/O I/O G17 I/O I/O E10 I/O I/O F14 I/O I/O G18 I/O I/O E11 I/O I/O F15 I/O I/O G19 I/O I/O E12 I/O I/O F16 I/O I/O G20 I/O I/O E13 I/O I/O F17 I/O I/O G21 I/O I/O E14 I/O I/O F18 I/O I/O G22 VDDP VDDP E15 I/O I/O F19 I/O I/O G23 I/O I/O E16 I/O I/O F20 I/O I/O G24 VDD VDD E17 I/O I/O F21 I/O I/O G25 I/O I/O E18 I/O I/O F22 I/O I/O G26 VDDP VDDP v5.2 2-61 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function G27 I/O I/O J1 I/O I/O K5 I/O I/O G28 I/O I/O J2 I/O I/O K6 I/O I/O G29 I/O I/O J3 I/O I/O K7 I/O I/O G30 GND GND J4 I/O I/O K8 I/O I/O H1 I/O I/O J5 I/O I/O K9 NC I/O H2 I/O I/O J6 I/O I/O K10 VDD VDD H3 I/O I/O J7 VDDP VDDP K11 NC I/O H4 I/O I/O J8 I/O I/O K12 VDDP VDDP H5 I/O I/O J9 VDD VDD K13 VDDP VDDP H6 I/O I/O J10 NC I/O K14 VDDP VDDP H7 I/O I/O J11 NC I/O K15 VDDP VDDP H8 GND GND J12 NC I/O K16 VDDP VDDP H9 NC I/O J13 NC I/O K17 VDDP VDDP H10 NC I/O J14 NC I/O K18 VDDP VDDP H11 NC I/O J15 NC I/O K19 VDDP VDDP H12 NC I/O J16 NC I/O K20 NC I/O H13 NC I/O J17 NC I/O K21 VDD VDD H14 NC I/O J18 NC I/O K22 NC I/O H15 NC I/O J19 NC I/O K23 I/O I/O H16 NC I/O J20 NC I/O K24 I/O I/O H17 NC I/O J21 NC I/O K25 I/O I/O H18 NC I/O J22 VDD VDD K26 I/O I/O H19 NC I/O J23 I/O I/O K27 I/O I/O H20 NC I/O J24 VDDP VDDP K28 I/O I/O H21 NC I/O J25 I/O I/O K29 I/O I/O H22 NC I/O J26 I/O I/O K30 I/O I/O H23 GND GND J27 I/O I/O L1 I/O I/O H24 I/O I/O J28 I/O I/O L2 I/O I/O H25 I/O I/O J29 I/O I/O L3 I/O I/O H26 I/O I/O J30 I/O I/O L4 I/O I/O H27 I/O I/O K1 I/O I/O L5 I/O I/O H28 I/O I/O K2 I/O I/O L6 I/O I/O H29 I/O I/O K3 I/O I/O L7 I/O I/O H30 I/O I/O K4 I/O I/O L8 I/O I/O 2 -6 2 v5.2 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function L9 NC I/O M13 GND GND N17 GND GND L10 NC I/O M14 GND GND N18 GND GND L11 VDD VDD M15 GND GND N19 GND GND L12 VDD VDD M16 GND GND N20 VDD VDD L13 VDD VDD M17 GND GND N21 VDDP VDDP L14 VDD VDD M18 GND GND N22 NC I/O L15 VDD VDD M19 GND GND N23 I/O I/O L16 VDD VDD M20 VDD VDD N24 I/O I/O L17 VDD VDD M21 VDDP VDDP N25 I/O I/O L18 VDD VDD M22 NC I/O N26 I/O I/O L19 VDD VDD M23 I/O I/O N27 I/O I/O L20 VDD VDD M24 I/O I/O N28 I/O I/O L21 NC I/O M25 I/O I/O N29 I/O I/O L22 NC I/O M26 I/O I/O N30 I/O I/O L23 I/O I/O M27 I/O I/O P1 I/O I/O L24 I/O I/O M28 I/O I/O P2 I/O I/O L25 I/O I/O M29 I/O I/O P3 I/O I/O L26 I/O I/O M30 I/O I/O P4 I/O I/O L27 I/O I/O N1 I/O I/O P5 I/O I/O L28 I/O I/O N2 I/O I/O P6 I/O I/O L29 I/O I/O N3 I/O I/O P7 I/O I/O L30 I/O I/O N4 I/O I/O P8 I/O I/O M1 I/O I/O N5 I/O I/O P9 I/O I/O M2 I/O I/O N6 I/O I/O P10 VDDP VDDP M3 I/O I/O N7 I/O I/O P11 VDD VDD M4 I/O I/O N8 I/O I/O P12 GND GND M5 I/O I/O N9 NC I/O P13 GND GND M6 I/O I/O N10 VDDP VDDP P14 GND GND M7 I/O I/O N11 VDD VDD P15 GND GND M8 I/O I/O N12 GND GND P16 GND GND M9 NC I/O N13 GND GND P17 GND GND M10 VDDP VDDP N14 GND GND P18 GND GND M11 VDD VDD N15 GND GND P19 GND GND M12 GND GND N16 GND GND P20 VDD VDD v5.2 2-63 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function P21 VDDP VDDP R25 I/O I/O T29 AVDD AVDD P22 I/O I/O R26 I/O I/O T30 I/O I/O P23 I/O I/O R27 NPECL2 NPECL2 U1 I/O I/O P24 I/O I/O R28 AGND AGND U2 I/O I/O P25 I/O I/O R29 I/O / GLMX2 I/O / GLMX2 U3 I/O I/O P26 I/O I/O R30 I/O I/O U4 I/O I/O P27 I/O I/O T1 I/O I/O U5 I/O I/O P28 I/O I/O T2 AVDD AVDD U6 I/O I/O P29 I/O I/O T3 I/O / GL2 I/O / GL2 U7 I/O I/O P30 I/O I/O T4 U8 I/O I/O R1 I/O I/O T5 I/O I/O U9 NC I/O R2 I/O / GLMX1 I/O / GLMX1 T6 I/O I/O U10 VDDP VDDP R3 AGND AGND T7 I/O I/O U11 VDD VDD R4 NPECL1 NPECL1 T8 I/O I/O U12 GND GND R5 I/O / GL1 I/O / GL1 T9 I/O I/O U13 GND GND R6 I/O I/O T10 VDDP VDDP U14 GND GND R7 I/O I/O T11 VDD VDD U15 GND GND R8 I/O I/O T12 GND GND U16 GND GND R9 NC I/O T13 GND GND U17 GND GND R10 VDDP VDDP T14 GND GND U18 GND GND R11 VDD VDD T15 GND GND U19 GND GND R12 GND GND T16 GND GND U20 VDD VDD R13 GND GND T17 GND GND U21 VDDP VDDP R14 GND GND T18 GND GND U22 NC I/O R15 GND GND T19 GND GND U23 I/O I/O R16 GND GND T20 VDD VDD U24 I/O I/O R17 GND GND T21 VDDP VDDP U25 I/O I/O R18 GND GND T22 I/O I/O U26 I/O I/O R19 GND GND T23 I/O I/O U27 I/O I/O R20 VDD VDD T24 I/O I/O U28 I/O I/O R21 VDDP VDDP T25 I/O I/O U29 I/O I/O R22 I/O I/O T26 U30 I/O I/O R23 I/O I/O T27 I/O / GL4 I/O / GL4 V1 I/O I/O R24 I/O I/O T28 I/O / GL3 I/O / GL3 V2 I/O I/O 2 -6 4 PPECL1 / Input PPECL1 / Input PPECL2 / Input PPECL2 / Input v5.2 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function V3 I/O I/O W7 I/O I/O Y11 VDD VDD V4 I/O I/O W8 I/O I/O Y12 VDD VDD V5 I/O I/O W9 NC I/O Y13 VDD VDD V6 I/O I/O W10 VDDP VDDP Y14 VDD VDD V7 I/O I/O W11 VDD VDD Y15 VDD VDD V8 I/O I/O W12 GND GND Y16 VDD VDD V9 NC I/O W13 GND GND Y17 VDD VDD V10 VDDP VDDP W14 GND GND Y18 VDD VDD V11 VDD VDD W15 GND GND Y19 VDD VDD V12 GND GND W16 GND GND Y20 VDD VDD V13 GND GND W17 GND GND Y21 NC I/O V14 GND GND W18 GND GND Y22 NC I/O V15 GND GND W19 GND GND Y23 I/O I/O V16 GND GND W20 VDD VDD Y24 I/O I/O V17 GND GND W21 VDDP VDDP Y25 I/O I/O V18 GND GND W22 NC I/O Y26 I/O I/O V19 GND GND W23 I/O I/O Y27 I/O I/O V20 VDD VDD W24 I/O I/O Y28 I/O I/O V21 VDDP VDDP W25 I/O I/O Y29 I/O I/O V22 NC I/O W26 I/O I/O Y30 I/O I/O V23 I/O I/O W27 I/O I/O AA1 I/O I/O V24 I/O I/O W28 I/O I/O AA2 I/O I/O V25 I/O I/O W29 I/O I/O AA3 I/O I/O V26 I/O I/O W30 I/O I/O AA4 I/O I/O V27 I/O I/O Y1 I/O I/O AA5 I/O I/O V28 I/O I/O Y2 I/O I/O AA6 I/O I/O V29 I/O I/O Y3 I/O I/O AA7 I/O I/O V30 I/O I/O Y4 I/O I/O AA8 I/O I/O W1 I/O I/O Y5 I/O I/O AA9 NC I/O W2 I/O I/O Y6 I/O I/O AA10 VDD VDD W3 I/O I/O Y7 I/O I/O AA11 NC I/O W4 I/O I/O Y8 I/O I/O AA12 VDDP VDDP W5 I/O I/O Y9 NC I/O AA13 VDDP VDDP W6 I/O I/O Y10 NC I/O AA14 VDDP VDDP v5.2 2-65 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AA15 VDDP VDDP AB19 NC I/O AC23 GND GND AA16 VDDP VDDP AB20 NC I/O AC24 I/O I/O AA17 VDDP VDDP AB21 NC I/O AC25 I/O I/O AA18 VDDP VDDP AB22 VDD VDD AC26 I/O I/O AA19 VDDP VDDP AB23 I/O I/O AC27 I/O I/O AA20 NC I/O AB24 VDDP VDDP AC28 I/O I/O AA21 VDD VDD AB25 I/O I/O AC29 I/O I/O AA22 NC I/O AB26 I/O I/O AC30 I/O I/O AA23 I/O I/O AB27 I/O I/O AD1 GND GND AA24 I/O I/O AB28 I/O I/O AD2 I/O I/O AA25 I/O I/O AB29 I/O I/O AD3 I/O I/O AA26 I/O I/O AB30 I/O I/O AD4 I/O I/O AA27 I/O I/O AC1 I/O I/O AD5 VDDP VDDP AA28 I/O I/O AC2 I/O I/O AD6 I/O I/O AA29 I/O I/O AC3 I/O I/O AD7 VDD VDD AA30 I/O I/O AC4 I/O I/O AD8 I/O I/O AB1 I/O I/O AC5 I/O I/O AD9 VDDP VDDP AB2 I/O I/O AC6 I/O I/O AD10 I/O I/O AB3 I/O I/O AC7 I/O I/O AD11 I/O I/O AB4 I/O I/O AC8 GND GND AD12 I/O I/O AB5 I/O I/O AC9 NC I/O AD13 I/O I/O AB6 I/O I/O AC10 NC I/O AD14 I/O I/O AB7 VDDP VDDP AC11 NC I/O AD15 I/O I/O AB8 I/O I/O AC12 NC I/O AD16 I/O I/O AB9 VDD VDD AC13 NC I/O AD17 I/O I/O AB10 NC I/O AC14 NC I/O AD18 I/O I/O AB11 NC I/O AC15 NC I/O AD19 I/O I/O AB12 NC I/O AC16 NC I/O AD20 I/O I/O AB13 NC I/O AC17 NC I/O AD21 I/O I/O AB14 NC I/O AC18 NC I/O AD22 VDDP VDDP AB15 NC I/O AC19 NC I/O AD23 TCK TCK AB16 NC I/O AC20 NC I/O AD24 VDD VDD AB17 NC I/O AC21 NC I/O AD25 TRST TRST AB18 NC I/O AC22 NC I/O AD26 VDDP VDDP 2 -6 6 v5.2 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AD27 I/O I/O AF1 GND GND AG5 I/O I/O AD28 I/O I/O AF2 I/O I/O AG6 I/O I/O AD29 I/O I/O AF3 VDDP VDDP AG7 I/O I/O AD30 GND GND AF4 I/O I/O AG8 I/O I/O AE1 I/O I/O AF5 VDD VDD AG9 I/O I/O AE2 VDD VDD AF6 I/O I/O AG10 I/O I/O AE3 I/O I/O AF7 VDDP VDDP AG11 I/O I/O AE4 I/O I/O AF8 I/O I/O AG12 I/O I/O AE5 I/O I/O AF9 I/O I/O AG13 I/O I/O AE6 GND GND AF10 I/O I/O AG14 I/O I/O AE7 I/O I/O AF11 I/O I/O AG15 I/O I/O AE8 I/O I/O AF12 I/O I/O AG16 I/O I/O AE9 I/O I/O AF13 I/O I/O AG17 I/O I/O AE10 I/O I/O AF14 I/O I/O AG18 I/O I/O AE11 I/O I/O AF15 I/O I/O AG19 I/O I/O AE12 I/O I/O AF16 I/O I/O AG20 I/O I/O AE13 I/O I/O AF17 I/O I/O AG21 I/O I/O AE14 I/O I/O AF18 I/O I/O AG22 I/O I/O AE15 I/O I/O AF19 I/O I/O AG23 I/O I/O AE16 I/O I/O AF20 I/O I/O AG24 I/O I/O AE17 I/O I/O AF21 I/O I/O AG25 I/O I/O AE18 I/O I/O AF22 I/O I/O AG26 I/O I/O AE19 I/O I/O AF23 I/O I/O AG27 GND GND AE20 I/O I/O AF24 VDDP VDDP AG28 RCK RCK AE21 I/O I/O AF25 I/O I/O AG29 VDD VDD AE22 I/O I/O AF26 VDD VDD AG30 I/O I/O AE23 I/O I/O AF27 TDO TDO AH1 GND GND AE24 I/O I/O AF28 VDDP VDDP AH2 I/O I/O AE25 GND GND AF29 VPN VPN AH3 VDD VDD AE26 I/O I/O AF30 GND GND AH4 I/O I/O AE27 I/O I/O AG1 I/O I/O AH5 VDDP VDDP AE28 I/O I/O AG2 VDD VDD AH6 I/O I/O AE29 VDD VDD AG3 I/O I/O AH7 I/O I/O AE30 I/O I/O AG4 GND GND AH8 I/O I/O v5.2 2-67 ProASICPLUS Flash Family FPGAs 896-Pin FBGA 896-Pin FBGA 896-Pin FBGA Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function Pin Number APA750 Function APA1000 Function AH9 I/O I/O AJ13 I/O I/O AK18 I/O I/O AH10 I/O I/O AJ14 I/O I/O AK19 I/O I/O AH11 I/O I/O AJ15 I/O I/O AK20 I/O I/O AH12 I/O I/O AJ16 I/O I/O AK21 I/O I/O AH13 I/O I/O AJ17 I/O I/O AK22 I/O I/O AH14 I/O I/O AJ18 I/O I/O AK23 I/O I/O AH15 I/O I/O AJ19 I/O I/O AK24 GND GND AH16 I/O I/O AJ20 I/O I/O AK25 I/O I/O AH17 I/O I/O AJ21 I/O I/O AK26 GND GND AH18 I/O I/O AJ22 I/O I/O AK27 I/O I/O AH19 I/O I/O AJ23 I/O I/O AK28 GND GND AH20 I/O I/O AJ24 I/O I/O AK29 GND GND AH21 I/O I/O AJ25 VDD VDD AH22 I/O I/O AJ26 I/O I/O AH23 I/O I/O AJ27 VDD VDD AH24 I/O I/O AJ28 TMS TMS AH25 I/O I/O AJ29 GND GND AH26 VDDP VDDP AJ30 GND GND AH27 TDI TDI AK2 GND GND AH28 VDD VDD AK3 GND GND AH29 VPP VPP AK4 I/O I/O AH30 GND GND AK5 GND GND AJ1 GND GND AK6 I/O I/O AJ2 GND GND AK7 GND GND AJ3 I/O I/O AK8 I/O I/O AJ4 VDD VDD AK9 I/O I/O AJ5 I/O I/O AK10 I/O I/O AJ6 VDD VDD AK11 I/O I/O AJ7 I/O I/O AK12 I/O I/O AJ8 I/O I/O AK13 I/O I/O AJ9 I/O I/O AK14 I/O I/O AJ10 I/O I/O AK15 I/O I/O AJ11 I/O I/O AK16 I/O I/O AJ12 I/O I/O AK17 I/O I/O 2 -6 8 v5.2 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA A1 Ball Pad Corner 34 3332 3130 2928 2726 2524 232221 2019 18 171615 1413 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF AG AH AJ AK AL AM AN AP Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-69 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 2 -7 0 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function A2 NC B5 GND C7 GND A3 GND B6 NC C8 I/O A4 GND B7 I/O C9 GND A5 GND B8 NC C10 I/O A6 I/O B9 I/O C11 I/O A7 VDD B10 NC C12 I/O A8 VDD B11 I/O C13 I/O A9 VDD B12 GND C14 I/O A10 VDD B13 I/O C15 I/O A11 I/O B14 VDDP C16 I/O A12 GND B15 VDDP C17 I/O A13 I/O B16 I/O C18 I/O A14 VDDP B17 GND C19 I/O A15 VDDP B18 GND C20 I/O A16 I/O B19 I/O C21 I/O A17 GND B20 VDDP C22 I/O A18 GND B21 VDDP C23 I/O A19 I/O B22 I/O C24 I/O A20 VDDP B23 GND C25 I/O A21 VDDP B24 I/O C26 GND A22 I/O B25 NC C27 I/O A23 GND B26 I/O C28 GND A24 I/O B27 NC C29 I/O A25 VDD B28 I/O C30 GND A26 VDD B29 NC C31 GND A27 VDD B30 GND C32 NC A28 VDD B31 GND C33 GND A29 I/O B32 GND C34 GND A30 GND B33 NC D1 GND A31 GND B34 NC D2 GND A32 GND C1 GND D3 GND A33 NC C2 GND D4 GND B1 NC C3 NC D5 I/O B2 NC C4 GND D6 VDD B3 GND C5 GND D7 I/O B4 GND C6 I/O D8 VDD v5.2 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function D9 I/O E11 I/O F13 I/O D10 I/O E12 I/O F14 I/O D11 I/O E13 I/O F15 I/O D12 I/O E14 I/O F16 I/O D13 I/O E15 I/O F17 I/O D14 I/O E16 I/O F18 I/O D15 I/O E17 I/O F19 I/O D16 I/O E18 I/O F20 I/O D17 I/O E19 I/O F21 I/O D18 I/O E20 I/O F22 I/O D19 I/O E21 I/O F23 I/O D20 I/O E22 I/O F24 I/O D21 I/O E23 I/O F25 I/O D22 I/O E24 I/O F26 I/O D23 I/O E25 I/O F27 I/O D24 I/O E26 I/O F28 I/O D25 I/O E27 I/O F29 GND D26 I/O E28 VDDP F30 I/O D27 VDD E29 I/O F31 VDD D28 I/O E30 VDD F32 I/O D29 VDD E31 I/O F33 NC D30 I/O E32 GND F34 NC D31 GND E33 GND G1 VDD D32 GND E34 GND G2 I/O D33 GND F1 I/O G3 GND D34 GND F2 NC G4 I/O E1 GND F3 I/O G5 VDDP E2 GND F4 VDD G6 I/O E3 GND F5 I/O G7 VDD E4 I/O F6 GND G8 I/O E5 VDD F7 I/O G9 VDDP E6 I/O F8 I/O G10 I/O E7 VDDP F9 I/O G11 I/O E8 I/O F10 I/O G12 I/O E9 I/O F11 I/O G13 I/O E10 I/O F12 I/O G14 I/O v5.2 2-71 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 2 -7 2 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function G15 I/O H17 I/O J19 I/O G16 I/O H18 I/O J20 I/O G17 I/O H19 I/O J21 I/O G18 I/O H20 I/O J22 I/O G19 I/O H21 I/O J23 I/O G20 I/O H22 I/O J24 VDDP G21 I/O H23 I/O J25 I/O G22 I/O H24 I/O J26 VDD G23 I/O H25 I/O J27 I/O G24 I/O H26 I/O J28 VDDP G25 I/O H27 GND J29 I/O G26 VDDP H28 I/O J30 I/O G27 I/O H29 I/O J31 I/O G28 VDD H30 I/O J32 GND G29 I/O H31 VDD J33 I/O G30 VDDP H32 I/O J34 VDD G31 I/O H33 NC K1 VDD G32 GND H34 VDD K2 NC G33 I/O J1 VDD K3 I/O G34 VDD J2 I/O K4 I/O H1 VDD J3 GND K5 I/O H2 NC J4 I/O K6 I/O H3 I/O J5 I/O K7 I/O H4 VDD J6 I/O K8 I/O H5 I/O J7 VDDP K9 I/O H6 I/O J8 I/O K10 GND H7 I/O J9 VDD K11 I/O H8 GND J10 I/O K12 I/O H9 I/O J11 VDDP K13 I/O H10 I/O J12 I/O K14 I/O H11 I/O J13 I/O K15 I/O H12 I/O J14 I/O K16 I/O H13 I/O J15 I/O K17 I/O H14 I/O J16 I/O K18 I/O H15 I/O J17 I/O K19 I/O H16 I/O J18 I/O K20 I/O v5.2 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function K21 I/O L23 I/O M25 I/O K22 I/O L24 VDD M26 I/O K23 I/O L25 I/O M27 I/O K24 I/O L26 VDDP M28 I/O K25 GND L27 I/O M29 I/O K26 I/O L28 I/O M30 I/O K27 I/O L29 I/O M31 I/O K28 I/O L30 I/O M32 I/O K29 I/O L31 I/O M33 GND K30 I/O L32 I/O M34 GND K31 I/O L33 I/O N1 I/O K32 I/O L34 I/O N2 I/O K33 NC M1 GND N3 I/O K34 VDD M2 GND N4 I/O L1 I/O M3 I/O N5 I/O L2 I/O M4 I/O N6 I/O L3 I/O M5 I/O N7 I/O L4 I/O M6 I/O N8 I/O L5 I/O M7 I/O N9 I/O L6 I/O M8 I/O N10 I/O L7 I/O M9 I/O N11 I/O L8 I/O M10 I/O N12 I/O L9 VDDP M11 I/O N13 VDD L10 I/O M12 VDD N14 VDD L11 VDD M13 I/O N15 VDD L12 I/O M14 VDDP N16 VDD L13 I/O M15 VDDP N17 VDD L14 I/O M16 VDDP N18 VDD L15 I/O M17 VDDP N19 VDD L16 I/O M18 VDDP N20 VDD L17 I/O M19 VDDP N21 VDD L18 I/O M20 VDDP N22 VDD L19 I/O M21 VDDP N23 I/O L20 I/O M22 I/O N24 I/O L21 I/O M23 VDD N25 I/O L22 I/O M24 I/O N26 I/O v5.2 2-73 ProASICPLUS Flash Family FPGAs 2 -7 4 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function N27 I/O P29 I/O R31 I/O N28 I/O P30 I/O R32 I/O N29 I/O P31 I/O R33 VDDP N30 I/O P32 I/O R34 VDDP N31 I/O P33 VDDP T1 I/O N32 I/O P34 VDDP T2 I/O N33 I/O R1 VDDP T3 I/O N34 I/O R2 VDDP T4 I/O P1 VDDP R3 I/O T5 I/O P2 VDDP R4 I/O T6 I/O P3 I/O R5 I/O T7 I/O P4 I/O R6 I/O T8 I/O P5 I/O R7 I/O T9 I/O P6 I/O R8 I/O T10 I/O P7 I/O R9 I/O T11 I/O P8 I/O R10 I/O T12 VDDP P9 I/O R11 I/O T13 VDD P10 I/O R12 VDDP T14 GND P11 I/O R13 VDD T15 GND P12 VDDP R14 GND T16 GND P13 VDD R15 GND T17 GND P14 GND R16 GND T18 GND P15 GND R17 GND T19 GND P16 GND R18 GND T20 GND P17 GND R19 GND T21 GND P18 GND R20 GND T22 VDD P19 GND R21 GND T23 VDDP P20 GND R22 VDD T24 I/O P21 GND R23 VDDP T25 I/O P22 VDD R24 I/O T26 I/O P23 VDDP R25 I/O T27 I/O P24 I/O R26 I/O T28 I/O P25 I/O R27 I/O T29 I/O P26 I/O R28 I/O T30 I/O P27 I/O R29 I/O T31 I/O P28 I/O R30 I/O T32 I/O v5.2 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function T33 I/O V1 GND W3 I/O T34 I/O V2 GND W4 I/O U1 GND V3 I/O W5 I/O U2 GND V4 AVDD W6 I/O U3 I/O V5 I/O / GL2 W7 I/O U4 I/O / GLMX1 V6 PPECL1 / Input W8 I/O U5 AGND V7 I/O W9 I/O U6 NPECL1 V8 I/O W10 I/O U7 I/O / GL1 V9 I/O W11 I/O U8 I/O V10 I/O W12 VDDP U9 I/O V11 I/O W13 VDD U10 I/O V12 VDDP W14 GND U11 I/O V13 VDD W15 GND U12 VDDP V14 GND W16 GND U13 VDD V15 GND W17 GND U14 GND V16 GND W18 GND U15 GND V17 GND W19 GND U16 GND V18 GND W20 GND U17 GND V19 GND W21 GND U18 GND V20 GND W22 VDD U19 GND V21 GND W23 VDDP U20 GND V22 VDD W24 I/O U21 GND V23 VDDP W25 I/O U22 VDD V24 I/O W26 I/O U23 VDDP V25 I/O W27 I/O U24 I/O V26 I/O W28 I/O U25 I/O V27 I/O W29 I/O U26 I/O V28 PPECL2 / Input W30 I/O U27 I/O V29 I/O / GL4 W31 I/O U28 I/O V30 I/O / GL3 W32 I/O U29 NPECL2 V31 AVDD W33 I/O U30 AGND V32 I/O W34 I/O U31 I/O / GLMX2 V33 GND Y1 VDDP U32 I/O V34 GND Y2 VDDP U33 GND W1 I/O Y3 I/O U34 GND W2 I/O Y4 I/O v5.2 2-75 ProASICPLUS Flash Family FPGAs 2 -7 6 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function Y5 I/O AA7 I/O AB9 I/O Y6 I/O AA8 I/O AB10 I/O Y7 I/O AA9 I/O AB11 I/O Y8 I/O AA10 I/O AB12 I/O Y9 I/O AA11 I/O AB13 VDD Y10 I/O AA12 VDDP AB14 VDD Y11 I/O AA13 VDD AB15 VDD Y12 VDDP AA14 GND AB16 VDD Y13 VDD AA15 GND AB17 VDD Y14 GND AA16 GND AB18 VDD Y15 GND AA17 GND AB19 VDD Y16 GND AA18 GND AB20 VDD Y17 GND AA19 GND AB21 VDD Y18 GND AA20 GND AB22 VDD Y19 GND AA21 GND AB23 I/O Y20 GND AA22 VDD AB24 I/O Y21 GND AA23 VDDP AB25 I/O Y22 VDD AA24 I/O AB26 I/O Y23 VDDP AA25 I/O AB27 I/O Y24 I/O AA26 I/O AB28 I/O Y25 I/O AA27 I/O AB29 I/O Y26 I/O AA28 I/O AB30 I/O Y27 I/O AA29 I/O AB31 I/O Y28 I/O AA30 I/O AB32 I/O Y29 I/O AA31 I/O AB33 I/O Y30 I/O AA32 I/O AB34 I/O Y31 I/O AA33 VDDP AC1 GND Y32 I/O AA34 VDDP AC2 GND Y33 VDDP AB1 I/O AC3 I/O Y34 VDDP AB2 I/O AC4 I/O AA1 VDDP AB3 I/O AC5 I/O AA2 VDDP AB4 I/O AC6 I/O AA3 I/O AB5 I/O AC7 I/O AA4 I/O AB6 I/O AC8 I/O AA5 I/O AB7 I/O AC9 I/O AA6 I/O AB8 I/O AC10 I/O v5.2 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AC11 I/O AD13 I/O AE15 I/O AC12 VDD AD14 I/O AE16 I/O AC13 I/O AD15 I/O AE17 I/O AC14 VDDP AD16 I/O AE18 I/O AC15 VDDP AD17 I/O AE19 I/O AC16 VDDP AD18 I/O AE20 I/O AC17 VDDP AD19 I/O AE21 I/O AC18 VDDP AD20 I/O AE22 I/O AC19 VDDP AD21 I/O AE23 I/O AC20 VDDP AD22 I/O AE24 I/O AC21 VDDP AD23 I/O AE25 GND AC22 I/O AD24 VDD AE26 I/O AC23 VDD AD25 I/O AE27 I/O AC24 I/O AD26 VDDP AE28 I/O AC25 I/O AD27 I/O AE29 I/O AC26 I/O AD28 I/O AE30 I/O AC27 I/O AD29 I/O AE31 I/O AC28 I/O AD30 I/O AE32 I/O AC29 I/O AD31 I/O AE33 NC AC30 I/O AD32 I/O AE34 VDD AC31 I/O AD33 I/O AF1 VDD AC32 I/O AD34 I/O AF2 I/O AC33 GND AE1 VDD AF3 GND AC34 GND AE2 NC AF4 I/O AD1 I/O AE3 I/O AF5 I/O AD2 I/O AE4 I/O AF6 I/O AD3 I/O AE5 I/O AF7 VDDP AD4 I/O AE6 I/O AF8 I/O AD5 I/O AE7 I/O AF9 VDD AD6 I/O AE8 I/O AF10 I/O AD7 I/O AE9 I/O AF11 VDDP AD8 I/O AE10 GND AF12 I/O AD9 VDDP AE11 I/O AF13 I/O AD10 I/O AE12 I/O AF14 I/O AD11 VDD AE13 I/O AF15 I/O AD12 I/O AE14 I/O AF16 I/O v5.2 2-77 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 2 -7 8 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AF17 I/O AG19 I/O AH21 I/O AF18 I/O AG20 I/O AH22 I/O AF19 I/O AG21 I/O AH23 I/O AF20 I/O AG22 I/O AH24 I/O AF21 I/O AG23 I/O AH25 I/O AF22 I/O AG24 I/O AH26 VDDP AF23 I/O AG25 I/O AH27 I/O AF24 VDDP AG26 I/O AH28 VDD AF25 TCK AG27 GND AH29 TDO AF26 VDD AG28 I/O AH30 VDDP AF27 TRST AG29 I/O AH31 VPN AF28 VDDP AG30 I/O AH32 GND AF29 I/O AG31 VDD AH33 I/O AF30 I/O AG32 I/O AH34 VDD AF31 I/O AG33 NC AJ1 I/O AF32 GND AG34 VDD AJ2 NC AF33 I/O AH1 VDD AJ3 I/O AF34 VDD AH2 I/O AJ4 VDD AG1 VDD AH3 GND AJ5 I/O AG2 NC AH4 I/O AJ6 GND AG3 I/O AH5 VDDP AJ7 I/O AG4 VDD AH6 I/O AJ8 I/O AG5 I/O AH7 VDD AJ9 I/O AG6 I/O AH8 I/O AJ10 I/O AG7 I/O AH9 VDDP AJ11 I/O AG8 GND AH10 I/O AJ12 I/O AG9 I/O AH11 I/O AJ13 I/O AG10 I/O AH12 I/O AJ14 I/O AG11 I/O AH13 I/O AJ15 I/O AG12 I/O AH14 I/O AJ16 I/O AG13 I/O AH15 I/O AJ17 I/O AG14 I/O AH16 I/O AJ18 I/O AG15 I/O AH17 I/O AJ19 I/O AG16 I/O AH18 I/O AJ20 I/O AG17 I/O AH19 I/O AJ21 I/O AG18 I/O AH20 I/O AJ22 I/O v5.2 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 1152-Pin FBGA 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function Pin Number APA1000 Function AJ23 I/O AK25 I/O AL27 VDD AJ24 I/O AK26 I/O AL28 I/O AJ25 I/O AK27 I/O AL29 VDD AJ26 I/O AK28 VDDP AL30 TMS AJ27 I/O AK29 TDI AL31 GND AJ28 I/O AK30 VDD AL32 GND AJ29 GND AK31 VPP AL33 GND AJ30 RCK AK32 GND AL34 GND AJ31 VDD AK33 GND AM1 GND AJ32 I/O AK34 GND AM2 GND AJ33 NC AL1 GND AM3 NC AJ34 NC AL2 GND AM4 GND AK1 GND AL3 GND AM5 GND AK2 GND AL4 GND AM6 I/O AK3 GND AL5 I/O AM7 GND AK4 I/O AL6 VDD AM8 I/O AK5 VDD AL7 I/O AM9 GND AK6 I/O AL8 VDD AM10 I/O AK7 VDDP AL9 I/O AM11 I/O AK8 I/O AL10 I/O AM12 I/O AK9 I/O AL11 I/O AM13 I/O AK10 I/O AL12 I/O AM14 I/O AK11 I/O AL13 I/O AM15 I/O AK12 I/O AL14 I/O AM16 I/O AK13 I/O AL15 I/O AM17 I/O AK14 I/O AL16 I/O AM18 I/O AK15 I/O AL17 I/O AM19 I/O AK16 I/O AL18 I/O AM20 I/O AK17 I/O AL19 I/O AM21 I/O AK18 I/O AL20 I/O AM22 I/O AK19 I/O AL21 I/O AM23 I/O AK20 I/O AL22 I/O AM24 I/O AK21 I/O AL23 I/O AM25 I/O AK22 I/O AL24 I/O AM26 GND AK23 I/O AL25 I/O AM27 I/O AK24 I/O AL26 I/O AM28 GND v5.2 2-79 ProASICPLUS Flash Family FPGAs 1152-Pin FBGA 2 -8 0 1152-Pin FBGA Pin Number APA1000 Function Pin Number APA1000 Function AM29 I/O AN31 GND AM30 GND AN32 GND AM31 GND AN33 NC AM32 NC AN34 NC AM33 GND AP2 NC AM34 GND AP3 GND AN1 NC AP4 GND AN2 NC AP5 GND AN3 GND AP6 I/O AN4 GND AP7 VDD AN5 GND AP8 VDD AN6 NC AP9 VDD AN7 I/O AP10 VDD AN8 NC AP11 I/O AN9 I/O AP12 GND AN10 NC AP13 I/O AN11 I/O AP14 VDDP AN12 GND AP15 VDDP AN13 I/O AP16 I/O AN14 VDDP AP17 GND AN15 VDDP AP18 GND AN16 I/O AP19 I/O AN17 GND AP20 VDDP AN18 GND AP21 VDDP AN19 I/O AP22 I/O AN20 VDDP AP23 GND AN21 VDDP AP24 I/O AN22 I/O AP25 VDD AN23 GND AP26 VDD AN24 I/O AP27 VDD AN25 NC AP28 VDD AN26 I/O AP29 I/O AN27 NC AP30 GND AN28 I/O AP31 GND AN29 NC AP32 GND AN30 GND AP33 NC v5.2 ProASICPLUS Flash Family FPGAs 624-Pin CCGA/LGA Top View D A A2 A1 A1 Corner Index Area b E Side View D1 e AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A E1 e 1 2 3 4 5 6 7 8 9 101112131415 161718 19 20 2122 2324 25 Bottom View Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v5.2 2-81 ProASICPLUS Flash Family FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function A2 I/O I/O B12 I/O I/O C22 I/O I/O A3 I/O I/O B13 I/O I/O C23 GND GND A4 I/O I/O B14 I/O I/O C24 VDD VDD A5 I/O I/O B15 I/O I/O C25 I/O I/O A6 I/O I/O B16 I/O I/O D1 I/O I/O A7 I/O I/O B17 I/O I/O D2 I/O I/O A8 I/O I/O B18 I/O I/O D3 VDD VDD A9 I/O I/O B19 I/O I/O D4 GND GND A10 I/O I/O B20 I/O I/O D5 I/O I/O A11 I/O I/O B21 I/O I/O D6 I/O I/O A12 I/O I/O B22 I/O I/O D7 I/O I/O A13 I/O I/O B23 VDD VDD D8 I/O I/O A14 I/O I/O B24 GND GND D9 I/O I/O A15 I/O I/O B25 VDDP VDDP D10 I/O I/O A16 I/O I/O C1 I/O I/O D11 GND GND A17 I/O I/O C2 VDDP VDDP D12 I/O I/O A18 I/O I/O C3 GND GND D13 I/O I/O A19 I/O I/O C4 VDD VDD D14 I/O I/O A20 I/O I/O C5 I/O I/O D15 GND GND A21 I/O I/O C6 I/O I/O D16 I/O I/O A22 I/O I/O C7 GND GND D17 I/O I/O A23 I/O I/O C8 I/O I/O D18 I/O I/O A24 VDDP VDDP C9 I/O I/O D19 I/O I/O A25 GND GND C10 I/O I/O D20 I/O I/O B1 I/O I/O C11 I/O I/O D21 I/O I/O B2 GND GND C12 I/O I/O D22 I/O I/O B3 VDDP VDDP C13 I/O I/O D23 I/O I/O B4 I/O I/O C14 I/O I/O D24 I/O I/O B5 I/O I/O C15 I/O I/O D25 I/O I/O B6 I/O I/O C16 I/O I/O E1 I/O I/O B7 I/O I/O C17 I/O I/O E2 I/O I/O B8 I/O I/O C18 I/O I/O E3 I/O I/O B9 I/O I/O C19 GND GND E4 I/O I/O B10 I/O I/O C20 I/O I/O E5 I/O I/O B11 I/O I/O C21 I/O I/O E6 I/O I/O 2 -8 2 v5.2 ProASICPLUS Flash Family FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function E7 I/O I/O F17 I/O I/O H2 I/O I/O E8 I/O I/O F18 GND GND H3 GND GND E9 I/O I/O F19 I/O I/O H4 I/O I/O E10 I/O I/O F20 I/O I/O H5 I/O I/O E11 I/O I/O F21 I/O I/O H6 I/O I/O E12 I/O I/O F22 I/O I/O H7 I/O I/O E13 I/O I/O F23 I/O I/O H8 VDDP VDDP E14 I/O I/O F24 I/O I/O H9 VDDP VDDP E15 I/O I/O F25 I/O I/O H10 VDDP VDDP E16 I/O I/O G1 I/O I/O H11 VDDP VDDP E17 I/O I/O G2 I/O I/O H12 VDDP VDDP E18 I/O I/O G3 I/O I/O H13 VDDP VDDP E19 I/O I/O G4 I/O I/O H14 VDDP VDDP E20 I/O I/O G5 I/O I/O H15 VDDP VDDP E21 I/O I/O G6 I/O I/O H16 VDDP VDDP E22 I/O I/O G7 I/O I/O H17 VDDP VDDP E23 I/O I/O G8 I/O I/O H18 VDDP VDDP E24 I/O I/O G9 I/O I/O H19 I/O I/O E25 I/O I/O G10 I/O I/O H20 I/O I/O F1 I/O I/O G11 I/O I/O H21 I/O I/O F2 I/O I/O G12 I/O I/O H22 I/O I/O F3 I/O I/O G13 I/O I/O H23 GND GND F4 I/O I/O G14 I/O I/O H24 I/O I/O F5 I/O I/O G15 I/O I/O H25 I/O I/O F6 I/O I/O G16 I/O I/O J1 I/O I/O F7 I/O I/O G17 I/O I/O J2 I/O I/O F8 GND GND G18 I/O I/O J3 I/O I/O F9 I/O I/O G19 I/O I/O J4 I/O I/O F10 I/O I/O G20 I/O I/O J5 I/O I/O F11 I/O I/O G21 I/O I/O J6 GND GND F12 I/O I/O G22 I/O I/O J7 I/O I/O F13 I/O I/O G23 I/O I/O J8 VDDP VDDP F14 I/O I/O G24 I/O I/O J9 GND GND F15 I/O I/O G25 I/O I/O J10 GND GND F16 I/O I/O H1 I/O I/O J11 GND GND v5.2 2-83 ProASICPLUS Flash Family FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function J12 GND GND K22 I/O I/O M7 I/O / GLMX1 I/O / GLMX1 J13 GND GND K23 I/O I/O M8 VDDP VDDP J14 GND GND K24 I/O I/O M9 GND GND J15 GND GND K25 I/O I/O M10 VDD VDD J16 GND GND L1 I/O I/O M11 GND GND J17 GND GND L2 I/O I/O M12 GND GND J18 VDDP VDDP L3 I/O I/O M13 GND GND J19 I/O I/O L4 I/O I/O M14 GND GND J20 GND GND L5 I/O I/O M15 GND GND J21 I/O I/O L6 I/O I/O M16 VDD VDD J22 I/O I/O L7 I/O I/O M17 GND GND J23 I/O I/O L8 VDDP VDDP M18 VDDP VDDP J24 I/O I/O L9 GND GND M19 I/O / GLMX2 I/O / GLMX2 J25 I/O I/O L10 VDD VDD M20 I/O / GL4 I/O / GL4 K1 I/O I/O L11 GND GND M21 NPECL2 NPECL2 K2 I/O I/O L12 GND GND M22 AGND AGND K3 I/O I/O L13 GND GND M23 I/O I/O K4 I/O I/O L14 GND GND M24 I/O I/O K5 I/O I/O L15 GND GND M25 I/O I/O K6 I/O I/O L16 VDD VDD N1 I/O I/O K7 I/O I/O L17 GND GND N2 I/O I/O K8 VDDP VDDP L18 VDDP VDDP N3 I/O I/O K9 GND GND L19 I/O I/O N4 AVDD AVDD K10 VDD VDD L20 I/O I/O N5 K11 VDD VDD L21 I/O I/O PPECL1 / Input PPECL1 / Input K12 VDD VDD L22 I/O I/O N6 I/O / GL1 I/O / GL1 K13 VDD VDD L23 I/O I/O N7 I/O I/O K14 VDD VDD L24 I/O I/O N8 VDDP VDDP K15 VDD VDD L25 I/O I/O N9 GND GND K16 VDD VDD M1 I/O I/O N10 VDD VDD K17 GND GND M2 I/O I/O N11 GND GND K18 VDDP VDDP M3 I/O I/O N12 GND GND K19 I/O I/O M4 AGND AGND N13 GND GND K20 I/O I/O M5 NPECL1 NPECL1 N14 GND GND K21 I/O I/O M6 I/O / GL2 I/O / GL2 N15 GND GND 2 -8 4 v5.2 ProASICPLUS Flash Family FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function N16 VDD VDD P25 I/O I/O T10 VDD VDD N17 GND GND R1 I/O I/O T11 VDD VDD N18 VDDP VDDP R2 I/O I/O T12 VDD VDD N19 I/O I/O R3 I/O I/O T13 VDD VDD N20 I/O / GL3 I/O / GL3 R4 I/O I/O T14 VDD VDD N21 PPECL2 / Input PPECL2 / Input R5 I/O I/O T15 VDD VDD R6 I/O I/O T16 VDD VDD N22 AVDD AVDD R7 I/O I/O T17 GND GND N23 I/O I/O R8 VDDP VDDP T18 VDDP VDDP N24 I/O I/O R9 GND GND T19 I/O I/O N25 I/O I/O R10 VDD VDD T20 I/O I/O P1 I/O I/O R11 GND GND T21 I/O I/O P2 I/O I/O R12 GND GND T22 I/O I/O P3 I/O I/O R13 GND GND T23 I/O I/O P4 GND GND R14 GND GND T24 I/O I/O P5 I/O I/O R15 GND GND T25 I/O I/O P6 I/O I/O R16 VDD VDD U1 I/O I/O P7 I/O I/O R17 GND GND U2 I/O I/O P8 VDDP VDDP R18 VDDP VDDP U3 I/O I/O P9 GND GND R19 I/O I/O U4 I/O I/O P10 VDD VDD R20 I/O I/O U5 I/O I/O P11 GND GND R21 I/O I/O U6 GND GND P12 GND GND R22 I/O I/O U7 I/O I/O P13 GND GND R23 I/O I/O U8 VDDP VDDP P14 GND GND R24 I/O I/O U9 GND GND P15 GND GND R25 I/O I/O U10 GND GND P16 VDD VDD T1 I/O I/O U11 GND GND P17 GND GND T2 I/O I/O U12 GND GND P18 VDDP VDDP T3 I/O I/O U13 GND GND P19 I/O I/O T4 I/O I/O U14 GND GND P20 I/O I/O T5 I/O I/O U15 GND GND P21 I/O I/O T6 I/O I/O U16 GND GND P22 GND GND T7 I/O I/O U17 GND GND P23 I/O I/O T8 VDDP VDDP U18 VDDP VDDP P24 I/O I/O T9 GND GND U19 I/O I/O v5.2 2-85 ProASICPLUS Flash Family FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function U20 GND GND W5 I/O I/O Y15 I/O I/O U21 I/O I/O W6 I/O I/O Y16 I/O I/O U22 I/O I/O W7 I/O I/O Y17 GND GND U23 I/O I/O W8 I/O I/O Y18 I/O I/O U24 I/O I/O W9 I/O I/O Y19 TCK TCK U25 I/O I/O W10 I/O I/O Y20 VPP VPP V1 I/O I/O W11 I/O I/O Y21 VPN VPN V2 I/O I/O W12 I/O I/O Y22 I/O I/O V3 GND GND W13 I/O I/O Y23 I/O I/O V4 I/O I/O W14 I/O I/O Y24 I/O I/O V5 I/O I/O W15 I/O I/O Y25 I/O I/O V6 I/O I/O W16 I/O I/O AA1 I/O I/O V7 I/O I/O W17 I/O I/O AA2 I/O I/O V8 VDDP VDDP W18 I/O I/O AA3 I/O I/O V9 VDDP VDDP W19 TMS TMS AA4 I/O I/O V10 VDDP VDDP W20 TDO TDO AA5 I/O I/O V11 VDDP VDDP W21 I/O I/O AA6 I/O I/O V12 VDDP VDDP W22 I/O I/O AA7 I/O I/O V13 VDDP VDDP W23 I/O I/O AA8 I/O I/O V14 VDDP VDDP W24 I/O I/O AA9 I/O I/O V15 VDDP VDDP W25 I/O I/O AA10 I/O I/O V16 VDDP VDDP Y1 I/O I/O AA11 I/O I/O V17 VDDP VDDP Y2 I/O I/O AA12 I/O I/O V18 VDDP VDDP Y3 I/O I/O AA13 I/O I/O V19 RCK RCK Y4 I/O I/O AA14 I/O I/O V20 I/O I/O Y5 I/O I/O AA15 I/O I/O V21 I/O I/O Y6 I/O I/O AA16 I/O I/O V22 I/O I/O Y7 I/O I/O AA17 I/O I/O V23 GND GND Y8 GND GND AA18 I/O I/O V24 I/O I/O Y9 I/O I/O AA19 I/O I/O V25 I/O I/O Y10 I/O I/O AA20 TDI TDI W1 I/O I/O Y11 I/O I/O AA21 TRST TRST W2 I/O I/O Y12 I/O I/O AA22 I/O I/O W3 I/O I/O Y13 I/O I/O AA23 I/O I/O W4 I/O I/O Y14 I/O I/O AA24 I/O I/O 2 -8 6 v5.2 ProASICPLUS Flash Family FPGAs 624-Pin CCGA/LGA 624-Pin CCGA/LGA 624-Pin CCGA/LGA Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function Pin Number APA600 Function APA1000 Function AA25 I/O I/O AC10 I/O I/O AD20 I/O I/O AB1 I/O I/O AC11 I/O I/O AD21 I/O I/O AB2 I/O I/O AC12 I/O I/O AD22 I/O I/O AB3 I/O I/O AC13 I/O I/O AD23 VDD VDD AB4 I/O I/O AC14 I/O I/O AD24 GND GND AB5 I/O I/O AC15 I/O I/O AD25 VDDP VDDP AB6 I/O I/O AC16 I/O I/O AE1 GND GND AB7 I/O I/O AC17 I/O I/O AE2 VDDP VDDP AB8 I/O I/O AC18 I/O I/O AE3 I/O I/O AB9 I/O I/O AC19 GND GND AE4 I/O I/O AB10 I/O I/O AC20 I/O I/O AE5 I/O I/O AB11 GND GND AC21 I/O I/O AE6 I/O I/O AB12 I/O I/O AC22 I/O I/O AE7 I/O I/O AB13 I/O I/O AC23 I/O I/O AE8 I/O I/O AB14 I/O I/O AC24 VDD VDD AE9 I/O I/O AB15 GND GND AC25 I/O I/O AE10 I/O I/O AB16 I/O I/O AD1 VDDP VDDP AE11 I/O I/O AB17 I/O I/O AD2 GND GND AE12 I/O I/O AB18 I/O I/O AD3 VDD VDD AE13 I/O I/O AB19 I/O I/O AD4 I/O I/O AE14 I/O I/O AB20 I/O I/O AD5 I/O I/O AE15 I/O I/O AB21 I/O I/O AD6 I/O I/O AE16 I/O I/O AB22 I/O I/O AD7 I/O I/O AE17 I/O I/O AB23 I/O I/O AD8 I/O I/O AE18 I/O I/O AB24 I/O I/O AD9 I/O I/O AE19 I/O I/O AB25 I/O I/O AD10 I/O I/O AE20 I/O I/O AC1 I/O I/O AD11 I/O I/O AE21 I/O I/O AC2 VDD VDD AD12 I/O I/O AE22 I/O I/O AC3 GND GND AD13 I/O I/O AE23 I/O I/O AC4 I/O I/O AD14 I/O I/O AE24 VDDP VDDP AC5 I/O I/O AD15 I/O I/O AE25 GND GND AC6 I/O I/O AD16 I/O I/O AC7 GND GND AD17 I/O I/O AC8 I/O I/O AD18 I/O I/O AC9 I/O I/O AD19 I/O I/O v5.2 2-87 ProASICPLUS Flash Family FPGAs Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous version v5.1 v5.0 v4.1 Changes in current version (v5.2) Page MIL-STD-883 was added to the datasheet. N/A VCC and VCCI were changed to VDDP. N/A Table 1-9 was updated to include 135C. page 1-20 In the "208-Pin PQFP" table, the following pin numbers have been updated: Pin Number Function 24 I/O / GL2 30 I/O / GL1 page 2-6 In the "208-Pin CQFP" table, the following pin numbers have been updated: Pin Number Function 23 I/O / GLMX1 24 I/O / GL2 28 PPECL1 / Input 30 I/O / GL1 128 I/O / GL3 129 PPECL2 / Input 134 I/O / GL4 135 I/O / GLMX2 page 2-13 In the "624-Pin CCGA/LGA" table, the following pin numbers have been updated: Pin Number Function M6 I/O / GL2 M7 I/O / GLMX1 M19 I/O / GLMX2 M20 I/O / GL4 N5 PPECL1 / Input N6 I/O / GL1 N20 I/O / GL3 N21 PPECL2 / Input page 2-82 MIL-STD 883B data will be added into this datasheet after the MIL-STD 883B qualification is complete. Green packaging information in the "Ordering Information" section was updated. page ii The "Temperature Grade Offerings" table was updated for the CG624. page iii The "Ordering Information" section was updated. page ii The "Live at Power-Up" section is new. page 1-3 Note 2 in Figure 1-4 was updated. page 1-4 The 3.3 V column in Table 1-3 was updated. page 1-9 The "Input/Output Blocks" section was updated. page 1-9 The note was removed from Table 1-4. page 1-9 The "Power-Up Sequencing" section was updated. page 1-10 The first bullet in the "ProASICPLUS Clock Management System" section was updated. page 1-13 The first paragraph in the "Performance Retention" section was updated. page 1-33 v5.2 3-1 ProASICPLUS Flash Family FPGAs Previous version Changes in current version (v5.2) Page Mixed Voltage was removed from Table 1-19. page 1-35 Table 1-20 was updated. page 1-35 Mixed Mode Voltage was removed from Table 1-21 and the Military/MIL-STD-883B column was page 1-36 updated. All tables from page 1-42 to page 1-51 were updated. page 1-42 to page 1-51 Table 1-48 is new. page 1-53 Figure 1-30 is new. page 1-53 Note 1 in Table 1-50 was updated. page 1-55 The notes in Table 1-54 were updated. page 1-59 A note was added to Figure 1-48. page 1-72 A note was added to Table 1-66. Table 1-66 The "TRST Test Reset Input" section was updated in the "Pin Description" section. page 1-73 The "624-Pin CCGA/LGA" section was updated for the APA600 and APA1000. Please review all page 2-81 pin data. v4.0 Figure 1-20 was updated. page 1-19 Table 1-46 was updated. page 1-52 The "1152-Pin FBGA" figure was updated. page 2-69 Pin names were changed to more accurately reflect the multiple functions supported by each pin. v3.5 The ProASICPLUS and ProASICPLUS Military/Aerospace datasheets were combined. This document now supports Commercial, Industrial, and Military Temperature devices. Table 1 was updated. page i-i The "Ordering Information" section was updated. page i-ii "Plastic Device Resources" table was updated. page i-ii The Long Term Jitter Peak-to-Peak Max. in the "PLL Electrical Specifications" table was updated. page 1-21 The "Calculating Typical Power Dissipation" section was updated. v3.4 3 -2 page 1-30 "Performance Retention" section page 1-33 Table 1-18 page 1-34 Table 1-20 was updated. page 1-35 Table 1-21 was updated. page 1-36 Table 1-22 was updated. page 1-38 Table 1-46 was updated. page 1-52 The "Temperature Grade Offerings" table is new. page i-iii The "Speed Grade and Temperature Matrix" table is new. page i-iii The "ProASICPLUS Clock Management System" section was updated. page 1-13 The "Lock Signal" section was updated. page 1-16 The "PLL Electrical Specifications" table was updated. page 1-21 The "User Security" section was updated. page 1-22 The "Design Environment" section was updated. page 1-27 Table 1-15 was updated. page 1-29 The "Asynchronous FIFO Full and Empty Transitions" section was updated. page 1-65 The "AVDD PLL Power Supply" section in the "Pin Description" section was updated. page 1-73 v5.2 ProASICPLUS Flash Family FPGAs Previous version Changes in current version (v5.2) Page v3.3 The "144-Pin TQFP" table on page 2-4 was updated. The following pins changed: Pin 15 = GLMX1 Pin 16 = GL1 Pin 21 = GL2 Pin 88 = GL3 Pin93 = GL4 Pin 94 = GLMX2 page 2-4 v3.2 The "ProASICPLUS Clock Management System" section was updated. page 1-13 Figure 1-14 was updated. page 1-14 Table 1-7 is new. page 1-15 Figure 1-20 was updated. page 1-19 The "PLL Electrical Specifications" section was updated. page 1-21 Figure 1-26 was updated. page 1-42 In the "Calculating Typical Power Dissipation" section, P9 was changed to 7.5 mW. page 1-30 The "Programming, Storage, and Operating Limits" section was updated. page 1-33 The "Recommended Design Practice for VPN/VPP" section was updated. page 1-74 v3.1 The datasheet was updated to include references to guidelines concerning the use of certain ProASICPLUS I/O standards. v3.0 In Table 1-2 on page 1-8, the Memory Rows - Bottom coordinates were changed. page 1-8 Figure 1-8 was updated. page 1-8 The VIL Minimum in the Table 1-22 was changed from 0.3 to -0.3. page 1-38 In the "Output Buffer Delays" section, the OB25LPLL tDHL Standard changed to 5.3. page 1-44 In the "Sample Macrocell Library Listing" section, the AND2 Standard maximum changed to 0.7 page 1-51 and the -F maximum changed to 0.8. v2.0 The Table 1 was updated. page i-i The "Ordering Information" section was updated. page i-ii The "Plastic Device Resources" section was updated. page i-ii The "ProASICPLUS Architecture" section was updated. page 1-2 Table 1-2 was updated. page 1-8 Table 1-8 is new. page 1-16 Figure 1-11 is new. page 1-10 The Introduction section in the "ProASICPLUS Clock Management System" section was page 1-13 updated. The "Physical Implementation" section was updated. page 1-13 The "Functional Description" on page 1-13 was updated. page 1-13 Figure 1-14 on page 1-14 through Figure 1-20 on page 1-19 were updated. page 1-14 to page 1-19 The "PLL Electrical Specifications" on page 1-21 was updated. page 1-21 Figure 1-25 on page 1-26 was updated. page 1-26 The "Calculating Typical Power Dissipation" on page 1-30 was updated. page 1-30 The 'Nominal Supply Voltages' section was updated. page 1-34 The Table 1-22 was updated. page 1-38 The "Tristate Buffer Delays" on page 1-42 was updated. page 1-42 The "Output Buffer Delays" on page 1-44 was updated. page 1-44 The"Input Buffer Delays" on page 1-46 was updated. page 1-46 "Global Routing Skew" on page 1-50 was updated. page 1-50 The"Sample Macrocell Library Listing" on page 1-51 was updated. page 1-51 v5.2 3-3 ProASICPLUS Flash Family FPGAs Previous version v2.0 (continued) 3 -4 Changes in current version (v5.2) Page The "Pin Description" on page 1-73 was updated. page 1-73 The following pins have been changed in the "100-Pin TQFP" table: Pin Number Function Pin Number Function 10 I/O (GLMX1) 60 GL3 11 GL1 61 PPECL2 (I/P) 13 NPECL1 63 NPECL2 15 PPECL1(I/P) 65 GL4 16 GL2 66 I/O (GLMX2) page 2-1 "144-Pin TQFP" section is new. page 2-3 The following pins have been changed in the "208-Pin PQFP" table: Pin Number Function Pin Number Function 23 I/O (GLMX1) 128 GL3 24 GL1 129 PPECL2 (I/P) 26 NPECL1 132 NPECL2 28 PPECL1 (I/P) 134 GL4 30 GL2 135 I/O (GLMX2) page 2-5 The following pins have been changed in the "456-Pin PBGA" table: Pin Number Function Pin Number Function M1 GL1 N22 NPECL2 M2 GL2 N23 GL3 M22 GL4 N25 I/O (GLMX2) N2 I/O (GLMX1) P5 NPECL1 N4 PPECL1 (I/P) P26 PPECL2 (I/P) page 2-22 The following pins have been changed in the "144-Pin FBGA" table: Pin Number Function Pin Number Function C2 GL2 F9 GL4 D12 I/O (GLMX2 )F11 PPECL2 (I/P E11 NPECL2 F12 GL3 F1 GL1 G1 PPECL1 (I/P) F3 I/O (GLMX1) G4 NPECL1 page 2-37 The following pins have been changed in the "256-Pin FBGA" table: Pin Number Function Pin Number Function H1 GL1 H16 GL4 H2 NPECL1 J1 GL2 H3 I/O (GLMX1) J2 PPECL1 (I/P) H13 I/O (GLMX2) J13 PPECL2 (I/P) H14 NPECL2 J16 GL3 page 2-40 The following pins have been changed in the "484-Pin FBGA" table: Pin Number Function Pin Number Function L4 GL1 L19 GL4 L5 NPECL1 M4 GL2 L6 I/O (GLMX1) M5 PPECL1 (I/P) L16 I/O (GLMX2) M16 PPECL2 (I/P) L17 NPECL2 M19 GL3 page 2-45 The following pins have been changed in the "676-Pin FBGA" table: Pin Number Function Pin Number Function N1 GL1 N25 GL4 N3 I/O (GLMX1) P1 GL2 N5 NPECL1 P5 PPECL1 (I/P) N22 GL3 P22 I/O (GLMX2) N24 NPECL2 P24 PPECL2 (I/P) page 2-51 v5.2 ProASICPLUS Flash Family FPGAs Previous version Advanced v0.7 Changes in current version (v5.2) Page The following pins have been changed in the "896-Pin FBGA" table: Pin Number Function Pin Number Function R2 I/O (GLMX1) T3 GL2 R4 NPECL1 T4 PPECL1 (I/P) R5 GL1 T26 PPECL2 (I/P) R27 NPECL2 T27 GL4 R29 I/O (GLMX2) T28 GL3 page 2-59 The following pins have been changed in the "1152-Pin FBGA" table: Pin Number Function Pin Number Function U4 I/O (GLMX1) U29 NPECL2 U6 NPECL1 U31 I/O (GLMX2) U7 GL1 V28 PPECL2 (I/P) V5 GL2 V29 GL4 V6 PPECL1 (I/P) V30 GL3 page 2-69 The "ProASICPLUS Architecture" section was updated. page 1-2 The "Array Coordinates" section and Table 1-2 are new. page 1-8 The "Power-Up Sequencing" section is new. page 1-10 "I/O Features" section was updated. page 1-9 The "Timing Control and Characteristics" section was updated. "Physical Implementation" page 1-13 to page section, "Functional Description" section, "Lock Signal" section, and "PLL Configuration 1-16 Options" section are new. "PLL Block - Top-Level View and Detailed PLL Block Diagram" section was updated. page 1-14 Figure 1-15 was updated. page 1-15 "Sample Implementations" section, "Adjustable Clock Delay" section, and the "Clock Skew page 1-16 Minimization" section are new. (Advanced v0.6) Figure 1-16, Figure 1-17, Figure 1-18, Figure 1-19, and Figure 1-20 are new. page 1-17 to page 1-19 The "PLL Electrical Specifications" section is new. page 1-21 The "Design Environment" section was updated. page 1-27 Figure 1-26 was updated. page 1-42 The "Calculating Typical Power Dissipation" section was updated. page 1-30 The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated. page 1-36 The Table 1-22 was updated. page 1-38 The "DC Specifications (3.3 V PCI Operation)1" section was updated. page 1-40 The "Tristate Buffer Delays" section (the figure and table) have been updated. page 1-42 The "Output Buffer Delays" section (the figure and table) have been updated. page 1-44 The "Input Buffer Delays" section was updated. page 1-46 The "Global Input Buffer Delays" section was updated. page 1-48 The "Predicted Global Routing Delay" section was updated. page 1-50 The "Global Routing Skew" section was updated. page 1-50 The "Sample Macrocell Library Listing" section was updated. page 1-51 The "Pin Description" section was updated. GLMX is new. page 1-73 The "Recommended Design Practice for VPN/VPP" section was updated. page 1-74 Pin AK31 of FG1152 for the APA1000 changed to VPP. page 2-69 The "Features and Benefits" on page i-i were updated. page i-i The "ProASICPLUS Product Profile" on page i-i was updated. page i-i The "Ordering Information" on page i-ii was updated. page i-ii The "Plastic Device Resources" on page i-ii was updated. page i-ii The "ProASICPLUS Architecture" on page 1-2 was updated. page 1-2 v5.2 3-5 ProASICPLUS Flash Family FPGAs Previous version Changes in current version (v5.2) Advanced v0.6 Table 1-1 was updated. (continued) Figure 1-14 was updated. Page page 1-7 page 1-14 The "Design Environment" section was updated. page 1-27 The "Package Thermal Characteristics" section was updated. page 1-29 The "Calculating Typical Power Dissipation" section was updated. page 1-30 The "Absolute Maximum Ratings*" section was updated. page 1-33 The "Programming, Storage, and Operating Limits" section was updated. page 1-33 The 'Nominal Supply Voltages' section was updated. page 1-34 The "Recommended Operating Conditions" section was updated. page 1-35 The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated. page 1-36 The "DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V)" section was page 1-38 updated. The "Synchronous Write and Read to the Same Location" section was updated. page 1-61 The "Asynchronous Write and Synchronous Read to the Same Location" section was updated. page 1-62 Advanced v0.5 Advanced v0.4 Advanced v0.3 The "Asynchronous FIFO Read" section was updated. page 1-67 The "Pin Description" section has been updated. page 1-73 The "Recommended Design Practice for VPN/VPP" section is new. page 1-74 The "100-Pin TQFP" section is new. page 2-1 The "484-Pin FBGA" section is new. page 2-45 The description for the VPN pin has changed. page 1-74 The "Plastic Device Resources" section has been updated. page i-ii Figure 1-12 and Figure 1-13 have been updated. page 1-14 The "Tristate Buffer Delays" section has been updated. page 1-42 The "Output Buffer Delays" section has been updated. page 1-44 The "Input Buffer Delays" section has been updated. page 1-46 The "Global Input Buffer Delays" section has been updated. page 1-48 The "456-Pin PBGA" section has been updated. page 2-22 The "676-Pin FBGA" section has been updated. page 2-51 The "ProASICPLUS Product Profile" section has been changed. page i-i The "Plastic Device Resources" section has been updated. page i-ii The "ProASICPLUS I/O Power Supply Voltages" sectionhas been updated. page 1-9 WDATA has ben changed to DI, and RDATA has been changed to DO to make them consistent with the signal names found in the Macro Library Guide. Figure 1-21 and Figure 1-22 have been updated. page 1-24 and page 1-25 The "Design Environment" section and Figure 1-26 have been updated. page 1-27 and page 1-42 The table in the "Package Thermal Characteristics" section has been updated. page 1-29 The "Calculating Typical Power Dissipation" section is new. page 1-30 The "Programming, Storage, and Operating Limits" section is new. page 1-33 The 'Nominal Supply Voltages' section has been updated. page 1-34 The "DC Electrical Specifications (VDDP = 2.5 V 0.2V)" section was updated. page 1-36 The "DC Electrical Specifications (VDDP = 3.3 V 0.3 V and VDD = 2.5 V 0.2 V)" section was page 1-38 updated. 3 -6 The "Recommended Operating Conditions" section was updated. page 1-35 The "ProASICPLUS Clock Management System" section was updated. page 1-13 v5.2 ProASICPLUS Flash Family FPGAs Previous version Changes in current version (v5.2) Advanced v0.3 Figure 1-14 was updated. (continued) Figure 1-13 is new. Page page 1-14 page 1-12 Tables 5, 6, and 7 from Advanced v0.3 were removed. The "Memory Block SRAM Interface Signals" section was updated. page 1-24 The "Memory Block FIFO Interface Signals" section was updated. page 1-25 All pinout tables have been updated, and several packages are new: 208-Pin PQFP - APA150, APA300, APA450, APA600 456-Pin PBGA - APA150, APA300, APA450, APA600 144-Pin FBGA - APA150, APA300, APA450 256-Pin FBGA - APA150, APA300, APA450, APA600 676-Pin FBGA - APA600 Advanced v0.1 Figure 1-23 has been updated. page 1-26 Data Sheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definition of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. Export Administration Regulations (EAR) The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. v5.2 3-7 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. http://www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan www.jp.actel.com Actel Hong Kong www.actel.com.cn 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 5172161-18/12.05