Revision 5.04 Data Sheet DS2023
S4882 Data Sheet
10 Mbps - 4.25 Gbps Continuous Rate Transceiver
August 19, 2009
Features
• 12.5 mV Diff Input Sensitivity at 1x10-12 BER
• Single Reference Clock for 10 Mbps - 4.25 Gbps
RX/TX Continuous Rate Operation with 10 Hz
resolution.
• Single reference clock frequency for FEC and Non-
FEC applications.
• Frame / Boundary Detection and Byte Alignment
for SONET/SDH and 8B/10B encoded protocols
and Differential RX/TX Decoding/Encoding.
• Output Data De-Emphasis with Adjustable Swing
and Phase Continuous Output Clocking
• Programmable Parallel Data Path (4/8/10-bit or 4-
bit Redundant Data Mode) with Optional Parity &
Programmable Auto Squelch Functionality
• Post Amp Offset Adjust, Loss of Signal with Run
Length Detector, Signal Detect Input, Receive
Signal Strength Indicator and RX/TX Lock Detect
Output Circuits.
• Integrated PLL Loop Filter Components & I/O
Terminations for a Compact Applications
• Dual REFCLK Inputs for Flexible CDR/CSU
Reference Clocking and/or External Clean-Up
• Additional CDR & CSU Programmable Prescaler
Clock Outputs for Down/Upstream Timing
• Transmit FIFO Depth allows for Breathing of
Transmit PCLK & PICLK Clocks
• I2C & SPI Compatible Control Interfaces with
Global Alarm Interrupt, Status, & Control
• Clock Multiplier Unit (CMU) Capability
• Intelligent Power Down of Selected Features/
Functions for Power Restricted Applications.
• Recovery from Input Alarm Conditions.
• 1.2 V & 3.3 V Power Supply Requirements
• Complies with Bellcore/ITU-T Specs for Jitter
Tolerance/Transfer/Generation as well as the
Related GE/FC/CPRI/HDTV 1 Specifications.
• JTAG (IEEE 1149.1-2001 compliant) & Dual
Independent Pattern Generators/Checkers
• Less than 900 mW Typical Power Dissipation
• Standard and Green/RoHS Compliant Lead Free
Package Options
Applications
• Multi-Service Protocol Platforms
• Protocol Independent Switches & Routers
• Video Applications
• Metro DWDM Network (Client side and Line)
General Description
The S4882 transceiver device is a fully integrated
CMOS transceiver utilizing a single fixed rate reference
clock for continuous rate coverage of the 10 Mbps
through 4.25 Gbps band. I2C/SPI accessible
independent RX/TX data path rate control, with 10 Hz
resolution, also allows for asymmetrical continuous
rate operation. On-chip clock synthesis and clock
recovery PLL components are contained in the S4882.
The chip consists of a receive (RX) function that
includes a clock and data recovery (CDR) unit and a
DeMUX. The transmit (TX) function contains a MUX
and clock synthesis unit (CSU) elements.
Figure 1: Any-Rate Wavelength Services Application System Block Diagram
1. HDTV Pathological patterns are not supported.
Rubicon
DW/FEC/PM
Async Mapper
LO
CLIENT SIDE
Multi-Rate Client
Signal
NETWORK SIDE
Multi-Rate
Network Signal
O/E
E/O
E/O
O/E
LO
SONET/SDH OTU1
2.48 GHz 2.67 GHz
155.52 MHz 155.52 MHz
S4882
S4882
2 Data Sheet Revision 5.04
S4882 Data Sheet
Data Sheet Type
NOTICE: THIS IS A RELEASED SPECIFICATION
This document is a RELEASED specification for a device under development by AppliedMicro:
• Specifications in this document are not guaranteed to be the latest and are subject to change.
• This data sheet may be superseded by a future revision. Always confirm with AppliedMicro that you are using the latest version.
• Please consult and register for documentation updates from AppliedMicro’s external website via the AppliedMicro’s
MyProduct subscription updates page: https://www.appliedmicro.com/MyAMCC/jsp/secure/alertSubscriptions/
my_product_list.jsp.
Data Sheet Type Definition
CONCEPT Concept Specifications are made available for products ideas that are being marketed to obtain
customer feedback.
ADVANCE
Advance Specifications are made available for products that are in the engineering development
cycle. General samples are not yet available for these products and the specifications, including
pin lists and functional descriptions, may change at any time WITHOUT NOTICE.
PRELIMINARY
Preliminary Specifications are made available for products that have been released for general
sampling by AppliedMicro (known as Sample Release (SR)). The SR milestone indicates that
device samples and evaluation kits may made available upon request. Preliminary device char-
acterization and evaluation has also been completed by AppliedMicro. Known device errata’s will
be published and dispositioned upon SR. Device specifications may still change WITHOUT
NOTICE.
RELEASED
Released Specifications are made available for products that have passed AppliedMicro’s Pro-
duction and Qualification Testing. Although Released Specifications are expected to never
change, occasional clean-up changes may be made throughout the remaining product life cycle.
All future specification changes that negatively impact a customer are processed through
AppliedMicro’s Product Change Notification system.
Revision 5.04 Data Sheet 3
S4882 Data Sheet
Table of Contents
Table of Contents
APPLICATIONS ...................................................................................................................................................... 1
GENERAL DESCRIPTION ...................................................................................................................................... 1
DATA SHEET TYPE ................................................................................................................................................ 2
TABLE OF CONTENTS .......................................................................................................................................... 3
LIST OF FIGURES .................................................................................................................................................. 5
LIST OF TABLES .................................................................................................................................................... 6
S4882 OVERVIEW .................................................................................................................................................. 7
MODES OF OPERATION ..................................................................................................................................... 10
TRANSMITTER OPERATION ............................................................................................................................... 10
Parallel Input Data Bus (PIN[X:0]P/N) ............................................................................................................. 10
Clock Synthesizer ............................................................................................................................................ 10
Transmit Timing Generation ............................................................................................................................ 11
TX Lock Detect ................................................................................................................................................ 11
Parallel-to-Serial Converter ............................................................................................................................. 11
TX FIFO ........................................................................................................................................................... 12
TX Data Rate Programming ............................................................................................................................ 12
Transmit Serial Output ..................................................................................................................................... 12
RECEIVER OPERATION ...................................................................................................................................... 14
Post Amp and Offset Adjust ............................................................................................................................ 14
Equalization and Bandwidth Control ................................................................................................................ 14
Clock Recovery ............................................................................................................................................... 14
Receive Timing Generation ............................................................................................................................. 15
RX Lock Detect ................................................................................................................................................ 15
RX Loss of Signal (LOS) ................................................................................................................................. 15
Received Signal Strength Indicator (RSSI) ..................................................................................................... 16
Fixed Frequency Acquisition (FFA) Mode ....................................................................................................... 16
Example for RX, FFA Manual Programing Step .............................................................................................. 18
Harmonic Band (HB) Detector ......................................................................................................................... 19
8B/10B Byte Boundary Detection (only in 10-bit parallel data bus mode) ....................................................... 19
SONET/SDH Frame and Byte Boundary Detection (only in 8-bit and 4-bit parallel data bus modes) ............ 20
Serial-to-Parallel Converter ............................................................................................................................. 21
Parallel Output Data Bus (POUT[X:0]P/N) ...................................................................................................... 21
Programmable Auto Squelch ........................................................................................................................... 21
ADDITIONAL FEATURES & TEST MODES ......................................................................................................... 22
Serial Diagnostic Loopback Enable (SDLBK) .................................................................................................. 22
Serial Line Loopback Enable (SLLBK) ............................................................................................................ 22
Parallel Line Loopback Enable (PLLBK) ......................................................................................................... 22
Parallel Diagnostic Loopback Enable (PDLBK) ............................................................................................... 22
Serial Loop Timing Mode (SLPTIME) .............................................................................................................. 23
Built-In Self Test Mode (BIST) ......................................................................................................................... 23
JTAG Test Port ................................................................................................................................................ 23
General Purpose I/O (GPIO) ........................................................................................................................... 23
4 Data Sheet Revision 5.04
S4882 Data Sheet
Table of Contents
Device ID and Revision ................................................................................................................................... 24
Power On Initialization Sequence .................................................................................................................... 24
Low Power Operation ...................................................................................................................................... 24
Reset Descriptions .......................................................................................................................................... 24
REFCLK Configurations .................................................................................................................................. 24
I2C BUS® .............................................................................................................................................................. 26
Write Command Description ............................................................................................................................ 26
READ COMMAND DESCRIPTION: ...................................................................................................................... 27
Current Address Read ..................................................................................................................................... 27
SERIAL PERIPHERAL INTERFACE (SPI) ........................................................................................................... 28
SPI Pin Signals ................................................................................................................................................ 28
SPI Protocol ..................................................................................................................................................... 29
SONET/SDH JITTER CHARACTERISTICS ......................................................................................................... 30
SONET/SDH Performance .............................................................................................................................. 30
SONET Input Jitter Tolerance ......................................................................................................................... 30
SONET Jitter Transfer ..................................................................................................................................... 30
SONET Jitter Generation ................................................................................................................................. 30
SDH Input Jitter Tolerance .............................................................................................................................. 31
GIGABIT ETHERNET JITTER CHARACTERISTICS ........................................................................................... 32
GE Performance .............................................................................................................................................. 32
GE Input Jitter Tolerance ................................................................................................................................. 32
GE Jitter Generation ........................................................................................................................................ 32
FIBRE CHANNEL JITTER CHARACTERISTICS ................................................................................................. 33
FC Performance .............................................................................................................................................. 33
FC Input Jitter Tolerance ................................................................................................................................. 33
FC Jitter Generation ........................................................................................................................................ 33
HDTV JITTER CHARACTERISTICS ..................................................................................................................... 35
HDTV Performance ......................................................................................................................................... 35
HDTV Jitter Transfer ........................................................................................................................................ 35
HDTV Intrinsic Jitter ......................................................................................................................................... 35
GENERIC PROTOCOL JITTER PEAKING CHARACTERISTICS ....................................................................... 38
Generic Protocol Jitter Peaking ....................................................................................................................... 38
PIN ASSIGNMENTS AND DESCRIPTIONS ...................................................................................................... 39
SERIAL CONTROL INTERFACE REGISTER MAP SUMMARY .......................................................................... 53
S4882 PINOUT TOP VIEW .................................................................................................................................. 61
S4882 – 144 PBGA PACKAGE MECHANICAL DRAWINGS .............................................................................. 62
S4882 – 144 PBGA PACKAGE MARKING DRAWING ........................................................................................ 63
PERFORMANCE SPECIFICATIONS .................................................................................................................... 64
ELECTRICAL SPECIFICATIONS ......................................................................................................................... 68
RECOMMENDED TERMINATIONS ...................................................................................................................... 80
DOCUMENT REVISION HISTORY ....................................................................................................................... 85
ORDERING INFORMATION ................................................................................................................................. 86
Revision 5.04 Data Sheet 5
S4882 Data Sheet
List of Figures
List of Figures
Figure 1: Any-Rate Wavelength Services Application System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2: High Level Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3: Differential Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 4: SPI Write Protocol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 5: SPI Read Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 6: SONET Input Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 7: SONET Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 8: SDH Input Jitter Tolerance Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 9: Gigabit Ethernet System Node Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 10: Fibre Channel System Node Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11: HDTV Jitter Measurement Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12: HDTV Jitter Transfer Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 13: HDTV Input Jitter Tolerance Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 14: HDTV Timing Jitter Input Mask Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 15: HDTV Output Timing Jitter Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 16: HDTV Alignment Jitter Input Mask Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 17: HDTV Output Alignment Jitter Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 18: S4882 Pinout Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 19: S4882 – 1.0 mm Ball Pitch, 144 PBGA Package Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 20: S4882 – 144 PBGA Package Marking Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 21: S4882 REFCLK Phase Noise Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 22: I2C BUS® Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 23: SPI BUS Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 24: RX Data Path Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 25: TX Data Path Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 26: /RST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 27: Differential Voltage Measurement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 28: LVCMOS Input/Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 29: LVDS Output Buffers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 30: Differential CML Output to Differential CML Input DC Coupled Termination . . . . . . . . . . . . . . . . . . . . 80
Figure 31: Differential CML Output to Differential CML Input AC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 32: Differential LVDS Input DC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 33: Differential LVDS Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 34: Differential LVDS Driver to LVDS Input Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 35: Differential LVDS Output to LVDS Input AC Coupled Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 36: Differential CML Output to Differential LVPECL Input AC Termination (Not internal Biased) . . . . . . . . 82
Figure 37: 3.3 V Differential CML Oscillator to Reference Clock Input DC Coupled Termination . . . . . . . . . . . . . 83
Figure 38: 2.5 V Differential LVPECL Oscillator to Reference Clock Input AC Coupled Termination . . . . . . . . . . 83
Figure 39: LVCMOS Output to LVCMOS Input Termination. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 40: S4882 Interface Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6 Data Sheet Revision 5.04
S4882 Data Sheet
List of Tables
List of Tables
Table 1: Standards Compliance List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2: De-Emphasis Level Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3: Fixed Frequency Acquisition PLL Band Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 4: RX and TX External Reference Clock Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5: Rate Configuration Pin Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 6: SONET Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7: Gigabit Ethernet Input Jitter Tolerance Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 8: Gigabit Ethernet Output Jitter Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9: Fibre Channel Input Jitter Tolerance Specification at node
α
R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10: Fibre Channel Total Jitter Generation at node
α
T. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11: Generic Protocol Minimum Transition Density for Jitter Transfer Peaking . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12: S4882 Transmitter Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13: S4882 Receiver Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 14: S4882 Global Control Pin Assignments and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . 46
Table 16: S4882 Power and Ground Pin Assignments and Descriptions (1.0 mm Pitch Package) . . . . . . . . . . . . 52
Table 17: Serial Control Interface Register Map Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 18: 1.0 mm Pitch Package Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 19: Performance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 20: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 21: Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 22: 3.3 V LVCMOS Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 23: High-Speed CML Output Characteristics: TSD, TSCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 24: High-Speed CML Input Characteristics: RSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 25: LVDS Input/Output Characteristics POUT[X:0], POCLKx, RXMCK, POUTPARL, FPOUTL, PIN[X:0],
PCLKx, PICLKx, TXMCK, PINPARL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 26: REFCLK CML Input Characteristics: REFCLK0, REFCLK1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 27: I2C BUS® LVCMOS Input/Output & Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 28: SPI BUS Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 29: RX Data Path Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 30: TX Data Path Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 31: /RST Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Revision 5.04 Data Sheet 7
S4882 Data Sheet
S4882 Overview
S4882 Overview
The S4882 transceiver implements continuous rate
serialization/deserialization for a variety of protocols
and transmission standards. The block diagram in
Figure 2 shows the basic operation of the chip. This
chip can be used to implement the front end of a
variety of Clock/Data Recovery (CDR) and clock
synthesis Serializer/Deserializer (SerDes) applications.
The S4882 consists primarily of the serial receive
interface and the serial transmit interface. The chip
handles all of the functions of these two elements
including offset adjustment, serial-to-parallel and
parallel-to-serial conversion, clock generation, frame /
boundary detection & word alignment (only for SONET/
SDH and 10-bit 8B/10B based protocols), and system
timing via an internal Clock Synthesizer Unit (CSU).
Many optional features provide the ultimate in flexibility
for the S4882 device operation. The parallel interface
ports have programmable bus width capability (4/8/10
bits wide with the option of running in a 4-bit
Redundant Data Mode). Parity and bit/polarity swap
are also options on these interfaces. The device also
expands its alarm and control flexibility when used with
either of the supplied I2C or the SPI communication
interfaces. Through these communication ports the
user will have access to maskable interrupt alarms
(that are summed into a pin accessible summary
interrupt), as well as status registers, configuration and
control bits. Both communication ports may also be
used simultaneously for dedicated closed loop control
via the faster SPI port while utilizing the I2C bus for
initialization, configuration, and monitoring. The
communication ports also expand the fixed rate use of
the device so that any fixed rate (within 10 Hz) may be
programmed into the device.
The devices sequence of operations are as follows:
Receiver Operations:
1. Serial Data Input to Limiting Amp with Equalization
2. Clock and Data Recovery from Serial Input
3. Serial-to-Parallel Conversion
4. Optional Differential Decoding
5. Parallel Data Output with Optional SONET/SDH (4
or 8-bit interface) or 8B/10B (10-bit) Word Align-
ment and/or Parity.
Transmitter Operations:
1. Parallel Data Input (4/8/10-bit or 4-bit Redundant
Data Mode)
2. Optional Parity Calculation
3. Optional Differential Encoding
4. Parallel-to-Serial Conversion
5. Serial Data with Optional Clock Output
6. Optional Data De-Emphasis
The S4882 also provides many high performance
features. Eye performance may also improved with the
use of our Post Amp Offset Adjust. Copper
transmission links may also be extended via
AppliedMicro’s De-Emphasis technology.
8 Data Sheet Revision 5.04
S4882 Data Sheet
S4882 Overview
Table 1: Standards Compliance List1
Standard Rev Date
GR-253-CORE V 3.0 September 2000
GR-253-ILR- Sonet Jitter Specifications Issue 3A October 2000
ESD – JEDEC standard: JESD22-A114-D Rev D March 2006
T1.105.03 - Standards Committee Telecommunications 2002
ITU-T: G783 (Corrigendum 1:3/2001) January 2000
ITU-T G984.2 & G984.3 03/2003 & 05/2005
IEEE Draft P802.3ae D5.0 May 1, 2002
CPRI Specification V2.0 2004-10-01
ITU G.709/Y.1331 03/2003
T1X1 T11 1/8x 1/4x 1/2x 1x 2x Fibre Channel Compliant
ESCON / FICON
SMPTE-292 HD-SD 2
FDDI
Fibre Channel - Methodologies for Jitter Specification (FC-MJS) Rev 10
1.Standards compliance only relates to applicable sections pertaining to this product type.
2. HDTV, pathological pattern is not supported.
Revision 5.04 Data Sheet 9
S4882 Data Sheet
S4882 Overview
Figure 2: High Level Functional Block Diagram1
1. This diagram does not illustrate all control and functionality of the device. It is intended to provide a high level view of the data flow and clock organization.
REFCLK1P/N
REFCLK0P/N
PIN[0:X]U/L
PICLKU/L
POUT[0:X]U/L
POCLKU/L
pllbk
Bit
Swap
Parity
Check
TX
FIFO
GND
PRBS/PAT
GEN
Encode
Pol
Inv
PRBS
Check
OCML
DATA
OCML
CLK
CSU TXLOCKDET
reg
RX_LLDAT
sllbk
TXMCK
RX_LLCLK
slptime
TSD
TSCLK
PINPARU/L
txphinit, reg
TXPHERR
PCLK
PIN[0:X]U/L
PICLKU/L
PINPARU/L
Timing
Gen
X:1
RSDP/N
TSD
sdlbk
CRU
&
Timing
Gen
reg
reg
Decode
PRBS/PAT
GEN
GND
rx_pout_
mutedata or sd
control
RXLOCKDET
LOS
Pol
Inv
Align
Bit
Swap
PRBS
Check
Parity
Gen
PIN[0:X]U/L
PICLKU/L
PINPARU/L
pdlbk
POUT[0:X]U/L
POCLKU/L
POUTPARU/L
reg
FPOUT
RX CHANNEL
RXMCK
POUT[0:X]U/L
POCLKU/L
RX_LLDAT
RX_LLCLK
DIGITAL CORE
I2C & SPI Control
GPIO
JTAG
reg or other
lower case text
Config & Control
SD
Summary Interrupt
1:X
TX CHANNEL
De-Emphasis
reg
EQ
reg reg
reg
10 Data Sheet Revision 5.04
S4882 Data Sheet
Modes of Operation
Modes of Operation
1. Pin Controlled Mode: (SCI [0] = 0) I2C and SPI
programming disabled. Device setup and control
only to come from I/O pin control.
2. Serial Controlled Interface Mode: (SCI [0] = 1)
I2C and SPI programming is enabled. Register
values supersede I/O Pin settings for device setup
and control.
Pin Controlled mode enables use of the S4882 without
the need of a micro controller (or other device) to
program the I2C or SPI registers. The device registers
will have no affect in this mode of operation. It should
also be noted that some pin controlled features require
a reset before a state change can take affect.
Serial Controlled Interface (SCI) mode enables access
to a wider set of control options and alarms via register
access. In SCI mode, the register values supersede
any settings made by the corresponding I/O control
pins. When this mode is enabled, the register defaults
take control of the chip until the associated registers
are programmed. Care should be taken to ensure that
all important registers are programmed in the proper
amount of time to meet any required acquisition time/
fault recovery requirements. A reset is also required for
some features before a state change can take affect.
Transmitter Operation
The S4882 transmitter contains the serializing stage in
the processing of a 10 Mbps to 4.25 Gbps serial data
stream. It converts the parallel data stream into a bit
serial format. A high-frequency phase continuous bit
clock, TSCLKP/N, can be optionally generated. The
outgoing serial data signal may optionally be
differentially encoded as shown in Figure &/or
launched with De-Emphasis.
Parallel Input Data Bus (PIN[X:0]P/N)
The parallel data bus may be configured to operate in
4, 8, or 10-bit mode. It may also be operated in 4-bit
Redundant Data mode which allows the transmission
of data from an alternate 4-bit port for protection
switching applications. Parity pins are also available for
applications that desire the added data integrity
information. The functions are programmable in or out
of SCI mode. The board designer is also provided extra
routing flexibility when the device is operated in SCI
mode by providing polarity and order swap options for
this bus. The different states and modes of the
PIN[X:0]P/N bus and its associated clocks and parity
may be programmed via registers 0xE1-E4h, 0xF2h, &
0x53h.
Data may be clocked across the parallel data bus at
the word rate (data rate / bus width) or at half of this
value. To operate at half the value you will have to
enable Double Data Rate (DDR) mode. DDR mode
forces the S4882 to clock the data into the device on
both the rising and falling edges of the clock, thereby
doubling the data rate per clock cycle. This, as a result,
slows down the external clock requirements to half the
standard rate. When the data is clocked in at the
standard rate only the rising edge is used to clock in
the data.
Other restrictions apply to the parallel bus data width
including the S4882’s I/O speed limitation. A maximum
transfer rate of 800 Mbps is allowed across any single
LVDS I/O. Therefore, both the data rate and bus width
should be considered when designing your system.
Clock Synthesizer
The clock synthesizer, shown in the block diagram in
Figure 2, is a PLL that generates the serial output clock
phase synchronized with one of two input reference
clock (REFCLK0P/N or REFCLK1P/N) depending on the
setting of the xx_PLL_SELREF1 registers, 0x4Ch &
0xD3h, while in SCI mode where xx represents RX or
TX.
The REFCLK input must be generated from a crystal
oscillator which has a frequency accuracy that meets
the values specified in Table 19 in order for the TSD
and TSCLK frequency to have the same accuracy
required for operation in a SONET/SDH system. Lower
accuracy crystal oscillators may be used in
applications less demanding than SONET/SDH.
REFCLK may also be generated from an external
VCXO circuit for increased jitter performance.
Revision 5.04 Data Sheet 11
S4882 Data Sheet
Transmitter Operation
Figure 3: Differential Encoder/Decoder
Transmit Timing Generation
The timing generation function provides a word rate (or
half word rate when DDR mode is enabled) version of
the transmit serial clock to an attached ASIC. This
clock, known as the PCLKxP/N where x represents L or
U, is used by upstream circuits to create a frequency
locked clock for transmission of data across the
PIN[X:0]P/N bus interface. The S4882 receives this
new clock as the PICLKxP/N and decouples the phase
differential between the PCLKxP/N and the PICLKxP/N
with an internal FIFO. Using PCLKxP/N for upstream
circuits ensures a stable frequency and phase
relationship between the S4882 device and the
attached ASIC. The timing generation circuitry also
provides an internally generated load signal which
transfers the PIN[X:0]P/N data from the parallel input
register to the serial shift register. A programmable
divide by 2N utility clock, TXMCKP/N, is also generated
by the related Clock Synthesizer Unit (CSU). The
TXMCKP/N values and states may be programmed
while in SCI mode via registers 0xE0-E1h. TXMCKP/N
may also be powered down.
TX Lock Detect
The S4882 contains a transmit lock detect circuit which
monitors the status of the transmit CSU. The
TXLOCKDET I/O pin (or TX_LOCKDET status bit in
register 0xDAh while in SCI mode) indicates the lock
state of the CSU relative to the REFCLK frequency.
This indicator is typically used on startup to determine
that the CSU has locked on to the supplied REFCLK
input. The TXLOCKDET indicator will be valid when the
CSU PLL is within the ppm limits specified in Table 19.
The TX Lock Detect Loss of Lock alarms and /INT
mask are also available in registers 0x64h & 0x84h.
Parallel-to-Serial Converter
The parallel-to-serial converter, shown as X:1 in
Figure 2, is comprised of a small FIFO and a parallel-
to-serial register. The FIFO input latches the data from
the PIN[X:0]P/N bus on the rising edge of PICLKxP/N or
on both the rising and falling edges in DDR Mode. The
parallel-to-serial register is a loadable shift register that
takes its parallel input from the FIFO output.
An internally generated clock, which is phase aligned
to the transmit serial clock as described previously in
the timing generator description, activates the parallel
data transfer between registers. The serial data is
shifted out of the parallel-to-serial register at the
TSCLK rate.
D Q
data
in
data
out
Differential Encoder Differential Decoder
DQ
any number
of
inversions
data out == data in
12 Data Sheet Revision 5.04
S4882 Data Sheet
Transmitter Operation
TX FIFO
A 12 bit deep FIFO, shown as TX FIFO in Figure 2, is
added to decouple the internal (PCLKxP/N) and
external (PICLKxP/N) clocks. The internally generated
clock, PCLKxP/N, is used to clock out the data from the
FIFO. Once the FIFO is centered, any PCLKx-to-
PICLKx wander may cause the FIFO pointers to drift.
The FIFO pointers will automatically push apart when
they get within 1-2 positions from each other. This
event will cause a temporary loss of data and will
toggle the Phase Error (PHERR) I/O pin and will set the
associated TX_PIN_PHERR alarm. The FIFO pointers
may also be manually initialized with the Phase Init
(TX_PIN_PHINIT) bit while in SCI mode or by initiating
a Hard reset (/RST). When /RST is active, the TX PLL
goes unlocked. When the device relocks to data
(TXLOCKDET goes active) the TX FIFO’s pointers will
be reset to their maximum position apart as long as the
TX_PIN_AT_TX_LOCKDET register bit is enabled. The
decision to reset the phase error based on the TX PLL
locking (TX_PIN_AT_TX_LOCKDET), PHERR going
active (TX_PIN_PHINIT_AT_PHERR), or by manual
control (TX_PIN_PHINIT) is decided by the associated
programming to the register bits listed above and
located in register 0xE3h.
Note that PCLK is held in reset when /RST is active.
TX Data Rate Programming
The S4882 has 15 available data rates that are
controllable by the RATECFG I/O pins and the
associated register map controls when in SCI mode. It
also has the capability to program operation at any rate
across the continuous 10 Mbps to 4.25 Gbps operating
range. The programmable frequencies must be
separated by 10Hz spectral spacing to allow for proper
acquisition. Consult the Fixed Frequency Acquisition
(FFA) Mode section for details on programming a
specific TX data rate.
Regardless of the data rate programming method, the
S4882 requires the incoming REFCLK rate to acquire
data. This is programmed via the RX & TXREFSEL
inputs or the associated xx_PLL_REFCLK_FREQ
registers, 0x17h & 0xC4h, while in SCI mode where xx
represents RX or TX.
Transmit Serial Output
When in SCI mode, the transmit serial data output of
the S4882 may be wave shaped with AppliedMicro’s
De-Emphasis circuit as shown in Table 2. Signal swing
and slew rate may also be modified for transmission
across PCB backplanes and other media. The
outgoing wave form may also be differentially encoded
with the circuit shown in Figure , to account for multiple
transmission inversions or other Phase Shift Keying
requirements that may be encountered in related
applications.
A transmit serial clock output is also available for
interconnection to laser sources and test equipment
that requires a dedicated high frequency clock output.
While Frequency Hold and SLPTime are active, the
S4882’s transmit channel will provide the capability to
hold the TSCLKP/N output (and all other CSU related
TX clocks) at a desired frequency which allows multiple
outgoing clocks to be maintained in the absence of
data.
The different states and modes of the high speed
outputs (including TSCLKP/N) may be programmed via
registers 0xEB-EEh and 0xE4h when SCI mode is
enabled. Mute values and power down capabilities are
also available.
Revision 5.04 Data Sheet 13
S4882 Data Sheet
Transmitter Operation
Table 2: De-Emphasis Level Select1
TX_TSD_DEEMPH _LEVEL_SEL[3:0] De-Emphasis Level
0 0 0 0 Full Swing
0 0 0 1 (1 - 1*0.0383) * Full Swing
0 0 1 0 (1 - 2*0.0383) * Full Swing
0 0 1 1 (1 - 3*0.0383) * Full Swing
0 1 0 0 (1 - 4*0.0383) * Full Swing
0 1 0 1 (1 - 5*0.0383) * Full Swing
0 1 1 0 (1 - 6*0.0383) * Full Swing
0 1 1 1 (1 - 7*0.0383) * Full Swing
1 0 0 0 (1 - 8*0.0383) * Full Swing
1 0 0 1 (1 - 9*0.0383) * Full Swing
1 0 1 0 (1 - 10*0.0383) * Full Swing
1 0 1 1 (1 - 11*0.0383) * Full Swing
1 1 0 0 (1 - 12*0.0383) * Full Swing
1 1 0 1 (1 - 13*0.0383) * Full Swing
1 1 1 0 (1 - 14*0.0383) * Full Swing
1 1 1 1 (1 - 15*0.0383) * Full Swing
1. Swing settings are dependent on the programming of the TX_TSD_SWING bit in register 0xEC, b0.
De-Emphasis only applies to Full Swing, TX_TSD_SWING = 0.
For TX_TSD_SWING = 1, the De-Emphasis bit reduces the swing amplitude of the signal.
De-Emphasis Levels are approximate values.
14 Data Sheet Revision 5.04
S4882 Data Sheet
Receiver Operation
Receiver Operation
The S4882 receiver section provides the first stage of
digital processing of the received 10 Mbps to 4.25
Gbps bit-serial stream. It converts the bit-serial data
stream into a 4, 8, or 10-bit wide parallel data format. It
may also be operated in 4-bit Redundant Data mode
which allows the receipt of data on an alternate 4-bit
port for protection switching applications. Parity bits are
also available for applications that desire the added
data integrity information. Differential Decoding, as
shown in Figure , may also be enabled for multiple
transmission inversions or other Phase Shift Keying
requirements. The associated states and modes of the
RSDP/N/C inputs including EQ, Bandwidth, Offset
Adjust, and Bias control may be programmed via
registers 0x4C-4Dh.
Clock recovery is performed on the incoming NRZ data
stream. A reference clock is required for phase locked
loop start-up and proper operation under loss of signal
conditions. An integral prescaler and phase locked
loop circuit are used to multiply this reference to the
nominal bit rate.
The incoming serial data rate may be optionally
differentially decoded. The S4882 receiver section
provides Loss of Signal alarms, Signal Detect input,
and a Receive Signal Strength Indicator when in SCI
mode.
Post Amp and Offset Adjust
The S4882 contains an integrated Post Amp with
Offset Adjust. This feature allows the user to adjust the
input detection circuitry to optimize the received input
signal. Several other features are linked to the Post
Amp including the Loss of Signal circuitry and the
Received Signal Strength Indicator. These, however,
are discussed in a later section, RX Loss of Signal
(LOS) and Received Signal Strength Indicator (RSSI).
The programming values including power down for the
Post Amp Offset Adjust circuitry are in registers 0x31h,
0x33h, 0x4Dh, and 0x92h. Consult the S4882’s
Programmers Reference Manual for further details.
Equalization and Bandwidth Control
When in SCI mode, the user may enable the S4882’s
RX Equalization circuit. This circuit is intended to allow
the user to compensate for extended FR-4
interconnects to the front end of the device. The
programmable function, RX_PA_EQ_CNTL[1:0], in
register 0x4Ch, compensates for bandwidth
attenuation and distortion caused by the Printed Circuit
Board.
To remove the AC component of the input signal the
PA_BW_CNTL[1:0] bits in register 0x4Ch may be used
to set the appropriate input low pass filter level. This
filter may be used to obtain a flat common mode input
response and may be chosen low enough to
adequately remove most of the AC components for the
lowest S4882 data rate. The user, however, must
consider the related low pass filter time constants
which will alter the devices acquisition time when
enabled.
Clock Recovery
The clock recovery block, as shown in Figure 2,
generates a clock that is at the same frequency as the
incoming data bit rate at the RSDP/N input. The clock is
phase aligned by a PLL so that it samples the data in
the center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are
compared by a phase/frequency discriminator. Output
pulses from the discriminator indicate the required
direction of phase corrections. These pulses are then
smoothed by an integrated loop filter. The output of the
loop filter controls the frequency of the internal Voltage
Controlled Oscillator (VCO), which generates the
recovered clock. When in SCI mode, edge decisions
may be manually adjusted with AppliedMicro’s Post
Amp Offset Adjust, Equalization, Offset Adjust,
bandwidth, and bias control.
The part offers 15 pre-programmed rates with a
number of reference frequency options. If the incoming
data rate is known to be among these 15 rates, then
the appropriate incoming data rate should be selected
with RATECFG[3:0], and the reference frequency with
REFSEL[3:0] controls. For Fixed Frequency
Acquisition, all that is needed to recover data across
the devices entire 10 Mbps - 4.25 Gbps data range is a
single Reference Clock (REFCLK) source. The
REFSEL[3:0] input must be programed in conjunction
Revision 5.04 Data Sheet 15
S4882 Data Sheet
Receiver Operation
with the RATECFG[3:0] input to properly configure the
device for the desired input rate/REFCLK selection
combination. It should be noted that a 10Hz minimum
spacing is required to discriminate between incoming
signals and that the wait time between rate changes is
specified in Table Table 19.
The S4882 CDR also incorporates a run length
checker to verify that long strings of ones or zeros are
not contaminating threshold decisions within the part.
This capability is linked to an associated LOS interrupt
(RX_RLD_LOS_INTB). The associated thresholds and
alarms are only accessible while in SCI mode.
RATECFG and REFSEL are also available via register
settings when SCI mode is enabled.
Receive Timing Generation
The receive channel also provides timing generation
functions. It provides a word rate (or half word rate
when DDR mode is enabled) version of the recovered
receive serial clock to an attached ASIC. This clock,
known as the POCLKxP/N, where x is either L or U, is
used for transmission of data across the POUT[X:0]P/N
bus interface. The timing generation circuitry also
provides a programmable divide by 2N utility clock
known as RXMCKP/N. The RXMCKP/N values and
states may be programmed while in SCI mode via
register 0x05h. SLPTime is an alternate timing mode
explained in Additional Features & Test Modes section.
RX Lock Detect
The S4882 contains a receive lock detect circuit which
monitors the serial data input bit rate in reference to the
incoming REFCLK frequency. If the received serial
data rate fails the stated ppm relationship requirements
as defined in Table 19, the PLL will be forced to lock to
the REFCLK input. The REFCLK will then maintain the
correct frequency of the receive output clocks under
loss-of-lock or loss-of-signal conditions. When in SCI
mode the device may also be forced to lock on to the
REFCLK with the LCKREF bit in register 0x01h. The
RXLOCKDET I/O pin and the associated register
status bit in register 0xA5h, indicate the current lock-to-
data state of the PLL relative to the REFCLK
frequency. Once asserted, the RXLOCKDET output will
remain active (logic 1) indicating that the RX PLL is in
lock and will maintain this setting up to the ppm offset
limits stated in Table 19. Beyond the specified PLL
locked-to-data limits, the RXLOCKDET status will
produce a falling edge (high to low transition). For input
data rates beyond the stated ppm lock condition of the
REFCLK, the RXLOCKDET status indicator will be
indeterminate. When out of lock, the lock detect circuit
will poll the input data stream in an attempt to reacquire
lock-to-data. This description is only valid for known
fixed rate applications. The RX Lock Detect Loss of
Lock alarms and /INT mask are also available in
registers 0x64h & 0x84h.
RX Loss of Signal (LOS)
The S4882 has the capability to report a Loss Of Signal
condition based upon several different alarm
conditions. Choosing which alarm contributes to the
LOS output are controllable within the S4882’s register
map while in SCI mode. The following alarms can
contribute to the LOS alarm based on the setting of
their associated LOSMSK register bits (PA Receive
Level, RLD, TC, SD, & Ext LOS Input):
Post Amp (PA) Receive Level: While in SCI mode,
the S4882’s integrated Post Amp circuitry allows the
S4882 to receive low level signals and internally
translate them to values that may be handled by the
S4882’s clock and data recovery circuit. If the input
level goes below a user programmable “disable”
threshold, the S4882 will declare a Post Amp LOS
alarm. The associated status bit will contain the current
state (disabled or enabled). Programmable hysteresis
is available with a separate Post Amp “enable”
threshold for declaring that the Post Amp has returned
to receiving a valid value. The S4882 has the capability
to link these alarms to the LOS indicator via the
associated LOSMSK register bit. A separate function,
the Received Signal Strength Indicator allows the user
to evaluate the value of the received signal. Consult
the Received Signal Strength Indicator (RSSI) section.
The Post Amp alarms are available in registers 0x62h
and 0x82h. The programmable disable and enable
threshold values are available in registers 0x36h and
0x37h.
16 Data Sheet Revision 5.04
S4882 Data Sheet
Receiver Operation
Run Length Detector (RLD): While in SCI mode, the
S4882 has the capability to track the number of
consecutive 1’s or 0’s received by the S4882. When an
excessive number of consecutive 1’s or 0’s are
received, the link can become problematic (especially
within an AC coupled link) as the link’s bias value will
be offset which will limit its ability to properly receive
the following bits. All CDR’s are limited in the number
of consecutive 1’s or 0’s that can be received so when
their limit is reached, the CDR will lose lock. The S4882
provides RLD alarms as well as the capability to link
them to the LOS indicator. The alarms react as follows:
The S4882’s Run Length Detector keeps track of the
number of consecutive logic ones (or zeros) within the
received data stream. If the number of consecutive
logic ones (or zeros) exceeds N where:
N = (RX_RLD_TH_BASE) * 2(RX_RLD_TH_EXP)
the associated Run Length Detector alarm will be set.
The RLD alarms are available in registers 0x62h and
0x82h. The programmable base and exponent
threshold values for setting the threshold N are
available in register 0x4Ah. The RLD alarm may have
an affect on the global interrupt pin (/INT) depending on
the setting of the associated INTMSK register bit. The
associated mask bit (LOSMSK) for the LOS alarm is
available in register 0x25h.
Signal Detect (SD) Input: A SD input has been
provided to connect the S4882 to external optical
modules or LOS circuitry that provides an external
Signal Detect output. When connected, this input will
aid in the detection of lost data throughout the network.
Note - The following two registers at address 0x30
must be programmed as follows (RX_CP_INIT = 0, and
RX_AFA_EN_CP_INIT = 0) for proper SD operation.
While in SCI mode, the expected active polarity of the
SD input may be set via register 0x06h. The associated
mask bit (LOSMSK) for the LOS alarm is available in
register 0x25h
External LOS (Ext LOS) Input: While in SCI mode, the
S4882 has the capability to manually force an LOS
condition. This is available through the associated
register bits in register 0x25h. The associated mask bit
(LOSMSK) for the LOS alarm is available in register
0x25h as well as the Ext LOS enable.
Received Signal Strength Indicator
(RSSI)
The S4882 allows the user to evaluate the input level of
the incoming signal. This is done through the RSSI
feature. In SCI mode, the enable and associated
recorded value are available in registers 0x4Dh and
0x91h respectively.
Fixed Frequency Acquisition (FFA)
Mode
In order to lock and receive an incoming signal, the
S4882 device must be programmed to the frequency of
the incoming signal. There are three FFA programming
control modes to select data rate and reference clocks
frequencies. The three modes are described below:
Pin Control Mode
To minimize the programming task, the S4882 supplies
15 common rates to choose from using Pin Control
Mode. These rates may be set with the RATECFG[3:0]
I/O pins. See Table 5 for more details. These pre-
programmed pin settings eliminate the need for SCI
programming to select the 15 common data rates. The
reference clock(s) may be set via the xxREFSEL[1:0] I/
O pins as well. See Table 4 for reference clock
selections.
Rate Configuration Mode using SCI Programming 1
To simplify the SCI programming task, the S4882
supplies 15 common rates to choose from using the
xx_RATE_CFG register bits when SCI mode is
enabled, where xx is RX or TX. Registers 0x17h and
0xC4h respectively. These pre-programmed settings
eliminate manual programming the PLL divider values
directly, simplifying the task of programming the S4882.
It is important to note that the S4882 must always know
the rate of the applied reference clock(s) regardless of
the acquisition mode. The reference clock(s) may be
set via the xx_PLL_REFCLK_FREQ register bits, where
1.Note, for RATE_CONFIG mode while using the TX CSU this
additional programming sequence must be followed.
• TX_RATE_CFG[3:0] register 0xC4h must be set to 0000.
• Program the TX_PLL_BANDSEL[5:0] register 0xCAh with
the value of 11 1111. Then return the
TX_PLL_BANDSEL[5:0] register to it’s original value.
• The final step, program the TX_RATE_CFG[3:0] register to
the desired value for the new TX rate.
Revision 5.04 Data Sheet 17
S4882 Data Sheet
Receiver Operation
xx represents RX or TX, while in SCI mode. This
function is contained in registers 0x17h and 0xC4h for
RX and TX respectively.
Manual Configuration Mode using SCI
Programming
In SCI mode, when requiring an input frequency that is
not one of the pre-programmed settings, the S4882 is
required to have the associated registers bits
programmed:
RX_PLL_FREQRATIO, TX_PLL_DIV_RATIO, and
xx_PLL_BANDSEL, where xx represents RX or TX.
These registers bits are located in 0x12-15h, 0xC6-
C9h, 0x16h, and 0xCAh respectively. In addition to
programming these registers the xx_RATE_CFG[3:0]
register bits, where xx represents RX or TX, should be
programmed to 0000.
18 Data Sheet Revision 5.04
S4882 Data Sheet
Receiver Operation
Below are the six manual programming steps for both
RX & TX:
1. Identify the desired Input Frequency: FD
2. Identify the Frequency Band: BS and Exponent: M
from Table 3 where: FMIN < FD < FMAX
3. Calculate RXPLLRATIO:
FOSC = FD * 2(M+1)
RXPLLRATIO = FOSC / RX_REF_DIV
RXPLLRATIO = [RXPLLRATIO_i] + [RXPLLRATIO_F]
where: 18 < RXPLLRATIO_i < 105
and: 0 < RXPLLRATIO_F < 1
• Program Binary Form of RXPLLRATIO_i into
RX_PLL_FREQRATIO[30:24], 0x12h
• Program Binary Form of RXPLLRATIO_F into
RX_PLL_FREQRATIO[23:00], 0x13-15h
4. Calculate TXPLLRATIO:
TXPLLRATIO = FOSC / TX_REF_DIV
TXPLLRATIO = [TXPLLRATIO_i] + [TXPLLRATIO_F]
where: 18 < TXPLLRATIO_i < 105
and: 0 < TXPLLRATIO_F < 1
• Program Binary Form of TXPLLRATIO_i into
TX_PLL_DIV_RATIO[30:24], 0xC6h
• Program Binary Form of TXPLLRATIO_F into
TX_PLL_DIV_RATIO[23:00, 0xC7-C9h
5. RX Frequency Band Select (BS) Programming
• Program Binary Form of BS into RX_PLL_BANDSEL[5:0],
0x16h
6. TX Frequency Band Select (BS) Programming
• Prior to programming BS for the new TX rate, first program
the TX_PLL_BANDSEL[5:0] register with the value of 11
1111.
• Then Program the desired Binary Form of BS into
TX_PLL_BANDSEL[5:0], 0xCAh
The Fixed Frequency Acquisition mode has a status
register in 0xA5h. There is also an associated
Frequency Ratio Detector that allows the user to set
alarms based on the measured frequency value.
For all TX or RX REFCLK frequencies that produce a
fraction relative to the data rate, the Fraction N feature
must be enabled, otherwise the PLL will not lock.
Enabling the Fraction N feature may slightly increase
the device’s Jitter Generation.
The TX Fraction N feature can be enabled via register
0xC3 (TX_PLL_SD_FRAC_EN). The RX Fraction N
feature can be enabled via register 0x49
(RX_PLL_SD_FRAC_EN)
Revision 5.04 Data Sheet 19
S4882 Data Sheet
Receiver Operation
Example for RX, FFA Manual
Programing Step
For Example:
Desired Data Rate, FD = 400 MHz
Desired REFCLK: RX_REF_DIV = 198 MHz
So, from above table
Bandwidth Select, BS = 21
Exponent, M = 3
Fosc = FD * 2^(M+1)
= 6.4 GHz
RXPLLratio = Fosc / RX_REF_DIV
= 6.4GHz / 198 MHz
= 32.32
From the above result 32.32, 32 is the integer & 0.32 is
the fraction.
* Convert integer 32 to BIN (7 bits) = 0100000
* Convert fraction 0.32*2^24 to BIN (24 bits) = 0101
0010 1011 1111 0101 1010
* Convert Bs value from above table (21) into binary (6
bits) = 010101
* Program 0100000 (integer value) to the
RX_PLL_FREQRATIO [30:24]
* Program 0101 0010 1011 1111 0101 1010 (fraction
value) to the RX_PLL_FREQRATIO [23:00]
* Program 010101 (Bs value) into the
RX_PLL_BANDSEL [5:0]
Similarly, TX side can be programmed as above.
Table 3: Fixed Frequency Acquisition PLL Band Select
M
Fh1 Fh2 Fm1 Fm2 Fl1 Fl2
BSFMAX FMIN BSFMAX FMIN BSFMAX FMIN BSFMAX FMIN BSFMAX FMIN BSFMAX FMIN
005.16
GHz
4.00
GHz 14.40
GHz
3.62
GHz 24.50
GHz
3.30
GHz 33.80
GHz
3.00
GHz 43.20
GHz
2.50
GHz 52.80
GHz
2.20
GHz
162.58
GHz
2.00
GHz 72.20
GHz
1.81
GHz 82.25
GHz
1.65
GHz 91.90
GHz
1.50
GHz 10 1.60
GHz
1.25
GHz 11 1.4G
Hz
1.10
GHz
212
1.29
GHz
1.00
GHz 13 1.00
GHz
905
MHz 14 1125
MHz
825
MHz 15 950
MHz
750
MHz 16 800
MHz
625
MHz 17 700
MHz
550
MHz
318645
MHz
500
MHz 19 550
MHz
452.5
MHz 20 562.5
MHz
412.5
MHz 21 475
MHz
375
MHz 22 400
MHz
312.5
MHz 23 350
MHz
275
MHz
424
322.5
MHz
250
MHz 25 270
MHz
226.2
MHz 26 281.2
MHz
206.2
MHz 27 237.5
MHz
187.5
MHz 28 200
MHz
156.2
MHz 29 175
MHz
137.5
MHz
530
161.2
MHz
125
MHz 31 137.5
MHz
113.1
MHz 32 140.6
MHz
103.1
MHz 33 118.7
MHz
93.75
MHz 34 100
MHz
78.1
MHz 35 87.5
MHz
68.7
MHz
636
80.6
MHz
62.5
MHz 37 68.7
MHz
56.5
MHz 38 70.3
MHz
51.5
MHz 39 59.3
MHz
46.8
MHz 40 50
MHz
39.0
MHz 41 43.75
MHz
34.3
MHz
742
40.3
MHz
31.2
MHz 43 34.3
MHz
28.2
MHz 44 35.1
MHz
25.7
MHz 45 29.6
MHz
23.4
MHz 46 25
MHz
19.5
MHz 47 21.8
MHz
17.1
MHz
848
20.15
MHz
15.6
MHz 49 17.18
MHz
14.1
MHz 50 17.5
MHz
12.8
MHz 51 14.8
MHz
11.7
MHz 52 12.5
MHz
9.7
MHz 53 10.9
MHz
8.5
MHz
954
10.0
MHz
7.8
MHz 55 8.5
MHz
7.0
MHz 56 8.7
MHz
6.4
MHz 57 7.4
MHz
5.8
MHz 58 6.25
MHz
4.8
MHz 59 5.4
MHz
4.2
MHz
20 Data Sheet Revision 5.04
S4882 Data Sheet
Receiver Operation
External Loss of Lock (Ext LOL): While in SCI mode,
the S4882 has the capability to manually force an LOL
condition. This function is available through the
associated register bit in register 0x24h. The affect of
this register bit is controlled by the associated loss of
lock mask bit (LOLMSK) which is available in register
0x25h.
Harmonic Band (HB) Detector
While in SCI mode, the S4882 has the capability to
detect transitions to reduce the probability of false
locking on sub frequency harmonics. When the device
does not detect a 101 transition or 010 transition within
the programmed time, an alarm will be set. If a
transition is detected then the timer will reset and the
monitoring will start again. The timer length is based on
the number of parallel clock cycle, where N is the
number of cycles defined as:
N= 2(HB_DET_EPOCH_CNT_LENGTH)
The count length is programmed via register 0x4Bh
and the interrupt and status register with their
associated mask are available in registers 0x62h &
0x82h.
8B/10B Byte Boundary Detection (only
in 10-bit parallel data bus mode)
While in SCI mode, the RX_FRAME bit is active, and
the device is configured with a 10-bit wide parallel bus
width, the S4882 will search the incoming data for a
framing word (default framing word is a +/- disparity
comma (0011111 or 1100000) character that is a subset
of the +/- disparity K28.5 control character). Only one
framing word of either positive or negative disparity (by
default) is needed to align itself on the parallel outputs,
POUT[9:0]P/N. A framing word can only be detected
1325 bytes after the RX_FRAME bit has been
activated for a 4.25G signal. See Table Table 19 for
valid numbers for the other major data rates.
Once synchronization on both the bit and word
boundaries to the framing word is achieved, the
receiver will provide the framing word on its parallel
outputs (POUT[9:0]P/N) and the Frame Pulse signal will
toggle and stay high for the duration of the framing
word. When the S4882 is searching for a framing word,
the device will continue to process data uninterrupted
at its arbitrary data alignment. As the S4882 aligns to
the incoming framing word, there is a possibility that an
error will be transmitted down the link as the K28.5
character is inserted into the data path in its proper
alignment. A maximum of one errored byte will be
transmitted during a realignment of the POUT[9:0]P/N
bus.
If the RX_FRAME bit is active upon reset and the 10-bit
wide parallel bus is enabled, the S4882 device will
come out of reset with the framing word state machine
in the out-of-frame state. The bit to byte mapping of
RSDP/N to POUT[9:0]P/N will be indeterminate until the
Frame Pulse output pin (FPOUTP/N) indicates that a
valid framing word has been acquired. Once framing
has been acquired, the S4882 will maintain the same
bit to byte mapping until a new frame position has been
validated or the device has been reset. The Frame
Pulse output pin will toggle each time the chosen
alignment word is found, or a new alignment position
has been validated, as long as the 8B/10B Byte
Boundary Detection Monitor is active.
A Framing interrupt, RX_FRAME_LOF_INTB (or RX_
FRAME_OOF_INTB), will occur when going in and out
of SONET/SDH framing conditions. These RX_FRAME
interrupts (as well as the Out Of Alignment interrupt
which is used for 8B/10B patterns) serve as an alarm
notifications that the POUT[9:0]P/N bus has been
forced to realign. The RX_FRAME interrupt bits and
their associated interrupt mask contribute to the
summary interrupt (/INT) that is available from an
external I/O Pin while in SCI mode.
Further flexibility from these default conditions are
available to the 8B/10B Byte Boundary Detection
Monitor when SCI mode is enabled. Via register
settings, the user will be able to choose their framing
word from one of six alignment word decisions:
• + disparity K28.5 word
• - disparity K28.5 word
• + or - disparity K28.5 word
• + disparity comma character
• - disparity comma character
• (DEFAULT) + or - disparity comma character
The user will also be able to choose the number of
alignment words (0-3) required to validate the
realignment of the outgoing POUT[9:0]P/N word bus
(Default is 1). If 0 is selected, the 8B/10B Byte
Boundary Detection circuitry will maintain its current
alignment until the device is reset or the register value
is changed with framing enabled.
Revision 5.04 Data Sheet 21
S4882 Data Sheet
Receiver Operation
SONET/SDH Frame and Byte Boundary
Detection (only in 8-bit and 4-bit
parallel data bus modes)
The serialization of a SONET/SDH frame for STS-48/
STM-16 transport consists of the transmission of the
first 144 transport overhead bytes followed by the first
4176 Synchronous Payload Envelope (SPE) bytes.
This pattern of 144 overhead and 4176 SPE bytes is
repeated 9 times (one for each row) to construct the
entire 125us STS-48/STM-16 SONET/SDH frame.
While in SCI Mode, if the S4882 parallel bus width is
set to 8-bit or either 4-bit mode and the control pin the
RX_FRAME bit is set active, SONET/SDH framing will
be enabled and the S4882 will attempt to detect and
align to the incoming SONET/SDH frame and byte
boundaries by detecting the inclusion of the A1 and A2
bytes found in the first row of the transport overhead.
When SONET/SDH framing is enabled, the S4882
device will come out of reset with the SONET/SDH
framer state machine in the out-of-frame state. The bit
to byte mapping of RSDP/N to POUT[7:0 or 3:0] will be
indeterminate until the Frame Pulse output pin
(FPOUTP/N) indicates that a valid framing pattern has
been acquired. Once framing has been acquired, the
S4882 will maintain the same bit to byte mapping until
a new frame position has been acquired or the device
has been reset. The Frame Pulse will continue to
toggle every 125us when the device is in frame as long
as the SONET/SDH framer is active.
For a STS-48/STM-16 or STS-12/STM-4 input, the
S4882 framing algorithm searches for a 32-bit A1-A1-
A2-A2 framing pattern sequence of F6h-F6h-28h-28h.
For a STS-3/STM-1 input it will search for the 24-bit
A1-A1-A2 framing pattern sequence of F6h-F6h-28h.
When the S4882 finds 2 successive un-errored framing
sequences, separated in time by 125 µs, it will declare
itself in frame and will start initiating frame pulses
(FPOUTP/N) that are aligned with the outgoing
associated data. The output data bus, POUT[7:0 or
3:0], will align to the SONET bytes with the second A2
being the first valid aligned byte. In the case of a nibble
wide data bus (POUT[3:0]), the first nibble transmitted
will contain the first four most significant bits with the
second nibble of the byte containing the four least
significant bits. This follows the MSB/LSB serial
transmission order specified within GR-253.
The S4882 will remain in-frame until it receives 5
successive frames with at least a 1-bit error in the
received framing pattern. When this occurs the
RX_FRAME_OOFx alarm (only accessible in SCI
mode) will be set active and the framing algorithm will
reinitialize its search as long as the RX_FRAME bit is
active and the parallel data bus width is still
programmed to 8 or either 4-bit mode. The
RX_FRAME bit must be active for at least one
POCLKxP./N cycle to initiate the frame search
algorithm. After the frame search algorithm has been
initiated, the S4882 will continue its frame search until
the RX_FRAME bit goes inactive and the first Frame
Pulse (FPOUTP/N) has occurred. When the search
algorithm is enabled, the data is valid out of the
POUT[7:0 or 3:0] data bus until the device realigns to a
new frame at which time the data will become valid
again but with the new alignment. If the RX_FRAME bit
is left active, FPOUTP/N will continue to pulse every
125us as long as device remains in frame. During an
OOF/LOF condition the Frame Pulse will be absent
until the framer goes back in frame per the rules
described previously.
The S4882 framing algorithm also provides a Loss-Of-
Frame (RX_FRAME_LOF_STA&INT) indication when
in SCI mode. The S4882 provides two separate
definitions for declaring RX_FRAME_LOF and each
can be programmed to clear within 24 frames (3 ms) or
8 frames (1 ms). These definitions are chosen by
RX_FRAME_LOFDEF and the clearing method may
be selected by setting RX_FRAME_LOFCLRSEL. The
functions of the RX_FRAME_LOFDEF and
RX_FRAME_LOFCLRSEL register bits are
summarized in the following text.
When RX_FRAME_LOFDEF is inactive (low) the
following RX_FRAME_LOFx definition is used:
• If RX_FRAME_OOFx is active continuously for
24 consecutive frames (3 ms),
RX_FRAME_LOFx will be set active. Once
RX_FRAME_LOFx is set, it will remain active
until RX_FRAME_OOFx is set inactive continu-
ously for either 24 or 8 consecutive frames
depending on the state of
RX_FRAME_LOFCLRSEL (High=24 frames,
Low=8 frames).
When RX_FRAME_LOFDEF is active (high), the
following alternate RXLOF definition is used:
• An in-frame timer accumulates on each frame
where RX_FRAME_OOF is set inactive. It stops
accumulating and resets to 0 when
RX_FRAME_OOF goes active. An out-of-frame
timer accumulates on each frame where
22 Data Sheet Revision 5.04
S4882 Data Sheet
Receiver Operation
RX_FRAME_OOF is active. It stops accumulat-
ing when RX_FRAME_OOF is inactive. It resets
to 0 when the in-frame timer reaches 24 or 8
frames depending on the state of
RX_FRAME_LOFCLRSEL (High=24 frames,
Low=8 frames). RX_FRAME_LOF is set active
when the out-of-frame timer reaches 24 frames
(3 ms). Once set, it remains high until the in-
frame timer reaches 24 frames (3 ms, if
RX_FRAME_LOFCLRSEL is high) or 8 frames
(1 ms, if RX_FRAME_LOFCLRSEL is low).
RX_FRAME_OOF_INTB and RX_FRAME_LOF_INTB
Interrupt bits and their associated interrupt masks
contribute to the summary interrupt (/INT) that is
available from an external I/O Pin.
Serial-to-Parallel Converter
The serial-to-parallel converter, shown as 1:X in
Figure 2, consists of three variable width registers. The
first is a serial-in, parallel-out shift register, which
performs serial-to-parallel conversion clocked by the
clock recovery block. The second is an internal holding
register, which transfers data from the serial-to-parallel
register. On the falling edge of the free running
POCLKxP/N, the data in the holding register is
transferred to an output holding register which drives
POUT[X:0]P/N.
Parallel Output Data Bus (POUT[X:0]P/N)
The parallel output data bus may be configured to
operate in 4, 8, or 10-bit mode. It may also be operated
in a 4-bit Redundant Data mode which allows the
receipt of data on an alternate 4-bit port for protection
switching applications. A parity bit is also available for
applications that desire the added data integrity
information. The functions are programmable in or out
of SCI mode. The board designer is also provided extra
routing flexibility when the device is operated in SCI
mode by providing polarity and order swap options for
this bus.The different states and modes of the POUT
bus and its associated clocks and parity may be
programmed via registers 0x06-0Ah.
Data may be clocked across the parallel output data
bus at the word rate (data rate / bus width) or at half
this value by the POCLKP/N. To operate at half the
value you will have to enable Double Data Rate (DDR)
mode. DDR mode forces the S4882 to clock the data
out of the device on both the rising and falling edges of
the clock thereby doubling the data rate per clock
cycle. This intern slows down the external clock
requirements to half the standard rate. When the data
is clocked out at the standard rate only the rising edge
is used to clock in the data.
Other restrictions may apply to the parallel output data
width. The bus width and/or speed combination may be
restricted by the S4882’s I/O speed limitation. A
maximum transfer rate of 800 Mbps is allowed across
any single LVDS I/O. Therefore, both the data rate and
bus width should be considered when designing your
system.
The POUT bus width is also a consideration when
determining the type of framing mode that the
RX_FRAME bit will enable. When the 10-bit interface is
enabled, the RX_FRAME bit will only enable the 8B/
10B Byte Boundary Detection Monitor. In all other bus
width configurations the RX_FRAME bit will enable the
SONET/SDH framer. The POUT bus width is set by the
BUSMODE[1:0] I/O pins or the RX_POUT_BUSMODE
register bits.
Programmable Auto Squelch
In SCI mode, the S4882 has the capability to squelch
the POUT bus automatically when a LOS condition
occurs. This function for the POUT bus is configured
via register 0x0A, MUTE_LOSEN. When squelch is
active, the POUTP/N bus will produce an all zeros
pattern. This function can also be manually activated
with the MUTEDATA register bit in 0x0Ah. The
associated clocks may also be manually squelched but
their squelched value may be programmed to either a
high or low value. These functions are only controllable
when SCI mode is enabled.
Revision 5.04 Data Sheet 23
S4882 Data Sheet
Additional Features & Test
Modes
Additional Features & Test Modes
Serial Diagnostic Loopback Enable
(SDLBK)
When the Serial Diagnostic Loopback Enable (SDLBK)
input is active, a loopback from the transmitter to the
receiver at the serial data rate can be set up for
diagnostic purposes. The differential serial output data
from the transmitter is routed to the clock recovery unit
and serial-to-parallel block in place of the normal
Receive Serial Data (RSD) stream. The parallel data
from the PIN[X:0] bus is ultimately routed via this serial
path to the POUT[X:0] bus. The POCLKxP/N will be
derived from the TSDP/N serial output unless the Lock
to Reference register bit is set. In this case the
POCLKxP/N will be derived the RX reference source.
The TSDP/N and TSCLKP/N will continue to transmit the
received PIN[X:0]P/N data as long at these outputs are
not muted. The Signal Detect (SD) input is ignored
during this mode as the RSD input has no affect on
device.
This mode may be enabled via register 0x01h while in
SCI mode or via the MODECFG[2:0] I/O pins when SCI
mode is disabled.
Serial Line Loopback Enable (SLLBK)
When Serial Line Loopback Enable (SLLBK) is active,
a loopback from the receiver to the transmitter at the
serial data rate can be set up for facility loopback
testing. The recovered clock is used to retime the
incoming data before driving the TSDP/N outputs. The
clocking is the same as SLPTIME mode.
POUT[X:0]P/N and POCLKxP/N are still active when
SLLBK is enabled as long as they are not muted. When
not muted, they will continue to transmit the
deserialized RSD data with its associated recovered
clock.
This mode may only be enabled while in SCI mode via
register 0x01h.
Parallel Line Loopback Enable (PLLBK)
When Parallel Line Loopback Enable (PLLBK) is
active, a line loopback from the serial receiver to the
transmitter can be set up internally to the S4882 via the
internal parallel data bus. The CSU clock (driven
externally from the REFCLK inputs) is used to clock the
parallel data out of the TX FIFO and is used to conduct
the parallel to serial conversion, generating TSDP/N
and TSCLKP/N. The recovered clock from RSDP/N is
used during the Serial to Parallel conversion and is
used in place of PICLKxP/N to clock the parallel data
into the TX FIFO. This unique clocking scenario allows
independent clock operation between the transmitter
and receiver. Care should be taken to ensure that the
frequency relationship between the CSU and the
CDR’s recovered clock is maintained so that FIFO
over/under run error’s can be avoided.
POUT[X:0]P/N and POCLKxP/N are still active when
PLLBK is enabled as long as they are not muted. When
not muted, they will continue to transmit the
deserialized RSD data with its associated recovered
clock.
DDR clock is not used internally while in PLLBK mode.
For this reason keep TX_PIN_DDR inactive while in
PLLBK mode.
This mode may be enabled via register 0x01h while in
SCI mode or via the MODECFG[2:0] I/O pins when SCI
mode is disabled.
Parallel Diagnostic Loopback Enable
(PDLBK)
When Parallel Diagnostic Loopback Enable (PDLBK) is
active, a diagnostic loopback from the parallel
transmitter input to the parallel receiver output via the
internal parallel bus is set up internal to the S4882. The
received PICLKxP/N will be used in place of generated
POCLKxP/N internal to the S4882 to clock out the
parallel data through the POUT[X:0]P/N bus. The
transmitter parallel output clock, PCLKxP/N, can be
generated from either the TX CSU or from the
recovered high speed serial clock if Serial Loop Timing
(SLPTIME) is enabled.
The TSDP/N and TSCLKP/N will continue to transmit the
received PIN[X:0]P/N data as long at these outputs are
not muted.
24 Data Sheet Revision 5.04
S4882 Data Sheet
Additional Features & Test
Modes
This mode may only be enabled while in SCI mode via
register 0x01h but does note operate when DDR mode
is enabled.
Serial Loop Timing Mode (SLPTIME)
In Serial Loop Timing (SLPTIME) mode, the clock
synthesizer PLL of the S4882 is bypassed, and the
timing of the entire transmitter section is controlled by
the recovered receive serial clock. SLPTIME enables
this mode of operation which may be enabled in
conjunction with other operating modes such as
PDLBK.
This mode may be enabled via register 0x01h while in
SCI mode or via the MODECFG[2:0] I/O pins when SCI
mode is disabled.
Built-In Self Test Mode (BIST)
The S4882 has integrated BIST capabilities including a
32-bit user programmable pattern and standard PRBS
test patterns:
STANDARD PATTERN: RELATED POLYNOMIAL
27-1: X7 + X6 + 1
223-1: X23 + X18 + 1
231-1: X31 + X28 + 1
BIST generation and checking functions exist in both
the transmit and receive paths for added testing
flexibility. Consult Figure 2 for block locations.
The Built-In Self Test (BIST) feature allows for the
verification of the data path, CRU, CSU and other
blocks in the S4882. The S4882 may be placed in BIST
mode via the pre-programmed MODECFG settings
when SCI mode is disabled or via the register map
while in SCI mode. Note that the BIST Checkers are
not available when SCI mode is disabled. This is due to
the fact that you can not clear the Checker error flags if
you do not have register access. Once the S4882 is in
the BIST mode, the respective inputs (RX/TX) are
bypassed and the chosen data pattern is substituted.
The BIST system also includes two PRBS checkers
(RX and TX). If the associated BIST is enabled, the
checkers will be activated but will not start checking for
the valid data pattern until their associated LOCKDET
(RX or TX) is active. This will ensure that valid data is
being passed through the channel. Once their
respective RX or TX LOCKDET is active, the checker
will begin its initialization phase for 64 parallel clock
cycles for 8/10-bits and 128 parallel clock cycles for 4-
bits. During the initialization phase the checker reads
the data and defines the pattern to be used as selected
in register 0x0Bh & 0xXXh for RX and TX paths
respectively. After the checker is initialized, it will
compare the data output with the selected pattern. The
selected pattern may be user defined by the values
programmed into registers 0x0C-0Fh or 0xE6-E9h for
RX & TX respectively. If the data does not match the
calculated pattern, the xx_BIST_CHK_ERR_STA flag
will be set active. The respective error flag is cleared
with the xx_BIST_CHK_CLR bit. Once the checker is
notified that the register has been cleared, it will go
back to the initialization phase. The PCLKP/N and
POCLKP/N are generated in their respective BIST
modes. The BIST patterns, enables, and error/clear
registers are available from registers 0x0B-10h, 0xB2-
B3h for the RX channel and registers 0xE5-EAh, 0xF3-
F4h for the TX channel. The error counts can be
calculated from the following definition:
N = Number of Errors in M Number of Bits
M = 2(yy_BIST_CHK_CNT_LENGTH)
N = (yy_BIST_CHK_ERRCNT_BASE) * 2(yy_BIST_CHECK_ERRCNT_EXP)
where yy = RX or TX
JTAG Test Port
For ease of manufacturing, JTAG has been included in
the S4882 design. The functions and features are
described in the S4882 JTAG Application Note,
AN2072.
General Purpose I/O (GPIO)
The S4882 has four general purpose I/O bits that are
accessible when SCI mode is enabled. This device
function contains a general purpose enable register
which sets the GPIO’s as inputs or outputs. This
register location, 0x04h, is shared with the GPIO write
register which allows values to be transmitted out of
the configured outputs. The values that are read into
the S4882 are located in register 0xBBh. Both the write
and the read functions are useful for reading external
control signals or controlling external devices. They
may also be set by the S4882 software as functional or
alarm indicators, driving an LED buffer or a
programmable device’s input.
Revision 5.04 Data Sheet 25
S4882 Data Sheet
Additional Features & Test
Modes
Device ID and Revision
When in SCI mode, the S4882 provides the
programming software information regarding the
device part number and revision. This allows the
associated software engineers the flexibility to architect
their software around the exact revision of a particular
chip. If and when later revisions to the software are
required due to product changes, the programmer can
modify the software to independently determine which
code download to use based upon the revision of the
chip used in the system. Separate software revisions
for bill of material changes will no longer be needed.
Power On Initialization Sequence
• Power on
• Supply REFCLK
• Hard Reset
• Set REFSEL[3:0] I/O pins
• Set RATECFG[3:0] I/O pins
• Set MODECFG[2:0] I/O pins
• Program Register Values via I2C or SPI (SCI
Mode Only)
Note: Loss of REFCLK requires a Hard reset, /RST
Low Power Operation
When SCI mode is enabled, the S4882 allows the user
to power down different sections of the chip to
conserve power. The RX and TX sections of the S4882
may be powered down separately. This allows the
S4882 to be used in separate Mux and DeMux
applications. The REFCLK inputs may also be
powered down independently to reduce power when
only using one REFCLK input. The PA Offset Adjust,
TXMCKP/N, and the TSCLKP/N may also be powered
down to reduce power consumption. These power
down controls may be found in registers 0x00h, 0x03h,
0x4Dh, 0xE0h, and 0xEBh.
Reset Descriptions
The S4882 provides two different types of reset
functions; Hard reset & Soft reset. A hard reset
completely resets all of the device’s gates and the
register map. A soft reset clears logic for all modes and
for register locations in SCI mode, loads written values
into the associated register locations. Both of the hard
and soft reset functions are available from external I/O
pins. The soft reset, however, is also available from the
register map when SCI mode is enabled. The register
accessible soft reset bits also provide the user the
granularity to provide separate soft resets to the RX
and TX sections of the chip. Initial power-on and a loss
of REFCLK requires a hard reset (/RST).
It is important to note, as stated above, that resets are
required for some register and I/O changes to take
affect. These requirements and the associated control
are presented in the PIN ASSIGNMENTS AND
DESCRIPTIONS & SERIAL CONTROL INTERFACE
REGISTER MAP SUMMARY sections.
REFCLK Configurations
It is recommended that the same reference clock
source be used for both REFCLK0 and REFCLK1 or
that any possibility of a ppm offset between the two
inputs is eliminated to maintain the jitter generation
performance specified in the data sheet. Two different
frequencies (ex. 155.52 MHz and 622.08 MHz) may be
input without TSCLKOP/N jitter generation degradation
as long as they are maintained at their nominal rate
with no ppm offset
If two separate reference clock sources are used to
drive REFCLK0 and REFCLK1, any ppm offset
between the two sources may induce excess jitter on
the TSCLKOP/N output.
26 Data Sheet Revision 5.04
S4882 Data Sheet
Additional Features & Test
Modes
Table 4: RX and TX External Reference Clock Selections1 (Only one REFCLK needed)
RX Reference Frequency (MHz) RXREFSEL1 RXREFSEL0 TX Reference Frequency (MHz) TXREFSEL1 TXREFSEL0
100 MHz 0 0 100 MHz 0 0
125 MHz 0 1 125 MHz 0 1
155.52 MHz 1 0 155.52 MHz 1 0
622.08 MHz* 1 1 622.08 MHz* 1 1
1.Additional reference clock selections are available when SCI mode is enabled (SCI=1). Consult the S4882 Programmers Manual (PRM2005) for details.
*: For REFCLK1 only. REFCLK0 requires frequencies between 100 MHz to 200 MHz.
Table 5: Rate Configuration Pin Selections1
RATESEL SETTING RATE DESCRIPTION
RATECFG [3:0] = 0000 N/A N/A
RATECFG [3:0] = 0001 10 Mbps 10base-X Ethernet
RATECFG [3:0] = 0010 125 Mbps 100base-X Ethernet / Fast Ethernet
RATECFG [3:0] = 0011 155.52 Mbps SONET/SDH STS-3/STM-1 / OC-3
RATECFG [3:0] = 0100 200 Mbps ESCON / SBCON
RATECFG [3:0] = 0101 265.625 Mbps Fibre Channel (1/4 Rate)
RATECFG [3:0] = 0110 531.25 Mbps Fibre Channel (1/2 Rate)
RATECFG [3:0] = 0111 622.08 Mbps SONET/SDH STS-12/STM-4 / OC-12
RATECFG [3:0] = 1000 1.0625 Gbps Fibre Channel
RATECFG [3:0] = 1001 1.250 Gbps 1000base-X Ethernet / Gigabit Ethernet
RATECFG [3:0] = 1010 1.485 Gbps SMPTE 292M
RATECFG [3:0] = 1011 2.125 Gbps Fibre Channel (2X)
RATECFG [3:0] = 1100 2.488 Gbps SONET/SDH STS-48/STM-16 / OC-48
RATECFG [3:0] = 1101 2.666 Gbps ITU G.709 / OTU-1
RATECFG [3:0] = 1110 2 3.125 Gbps XAUI
RATECFG [3:0] = 1111 24.250 Gbps Fiber Channel (4X)
Note: Additional Rates from 10 Mbps to 4.25 Gbps with up to a 10Hz resolution may be programmed manually when in SCI mode is enabled (SCI=1).
1. S4882 is tested for all the rates mentioned in this datasheet. Of all the listed bit rates in Table 5, only the associated SONET/SDH,
Fibre Channel and Gigabit Ethernet protocols have been validated to their respective standards (as listed in Table 1). AppliedMicro has
characterized the remaining bit rates with a PRBS 231 pattern but has not validated their associated protocols against any known stan-
dard. It is the responsibility of the end user to evaluate and verify protocol/standards compliance for all other bit rates that are intended
for use.
2. Both 3.125 Gbps and 4.250 Gbps rates are not supported in Pin Configuration Mode. For these two data rates it is required to use
either Rate Configuration mode or Manual Configuration modes,
When selecting the Tx rate follow this procedure:
a. Set the RATECFG[3:0] pins to 0000.
b. Wait 300ns minimum to allow for the VCO change sequence to complete.
c. Set the RATECFG[3:0] pins to your desired value.
Revision 5.04 Data Sheet 27
S4882 Data Sheet
I2C BUS®
I2C BUS®
The S4882 uses a simple bi-directional two-wire bus
for register access and device programming. In an I2C
topology, the S4882 acts as a Slave device which is
denoted in the following sections as the Target. In this
configuration, the Master device always provides the
clock, the address (both of the device and register
location), and the command (read or write). The Target
device provides the acknowledge (with the exception of
data being received by the Master), the data (only in
response to a read command), and a clock stretch
(hold in the low position) when requiring a delay in the
response from a command. The S4882 does not
respond to General Call Commands and requires the
use of 7-bit addressing.
I2C Base Address: ADDR[6:0] = 1 1 0 1 ADDR[2:0]1
I2C Maximum Operating Rate: up to 400kHz
Write Command Description
Start Write Sequence: SDA transitions from high to low
while SCL is held high. This is initiated by the I2C
Master.
Device Address + R/W Write Sequence: The Target
device’s 7 bit I2C address is transmitted from the I2C
Master on the SDA line, MSB first. If the transmitted
I2C Target device address is not identical to the device
of interest, the device of interest may then ignore the
entire Write command (until Stop Sequence) as it is not
the Target device.
Continuing on in this sequence, the Read/Write bit will
follow the LSB of the Target device address with a
value of 0 for a Write Operation Request. After the
Write bit, the Target device must then reply on the next
clock cycle with an acknowledge (SDA pulled low for 1
bit time) if this sequence has been received and
understood. If this sequence was not understood or not
received, SDA will be left floating high which will cause
the Master to abort the command.
Register Address Write Sequence: The I2C Master
transmits the 8-bit register address of the Target device
to which the following data will be written to. The Target
device must then reply on the next clock cycle with an
acknowledge (SDA pulled low for 1 bit time) if this
sequence has been received and understood. If this
sequence was not understood or not received, SDA will
be left floating high which will cause the Master to abort
the command.
Data Field Write Sequence: The I2C Master transmits
the 8-bit register value to be written.to the Target
device. The Target device must then reply on the next
clock cycle with an acknowledge (SDA pulled low for 1
bit time) if this sequence has been received and
understood. If this sequence was not understood or not
received, SDA will be left floating high which will cause
the Master to abort the command.
Data Field Write Sequence Continued: The Target
device may continue to recover write commands
without the I2C Master having to resend the
commands:
• Start Write Sequence
• Device / Address & R/W Write Sequence,
• Register Address Write Sequence.
When the associated register bit is set in 0x03h, the
Target’s register address pointer will auto increment
with each received 8-bit word as long as an
acknowledge is sent by the Target as in previous
sequences. Once the address pointer reaches register
address 0xFFh, the next write will wrap around to
0x00h.
Stop Write Sequence: SDA transitions from low to high
while SCL is held high. This is initiated by the I2C
Master.
1. ADDR[2:0] are programmable I/O pins in SCI mode
28 Data Sheet Revision 5.04
S4882 Data Sheet
Read Command Description:
Read Command Description:
BYTE ADDRESS READ
Start Read Sequence: SDA transitions from high to low
while SCL is held high. This is initiated by the I2C
Master.
Device Address + R/W Read Sequence 1: The
Target device’s 7 bit I2C address is transmitted from
the I2C Master on the SDA line, MSB first. If the
transmitted I2C Target device address is not identical
to the device of interest, the device of interest may then
ignore the entire Read command (until Stop Sequence)
as it is not the Target device.
Continuing on in this sequence, the Read/Write bit will
follow the LSB of the Target device address with a
value of 0 for a Write Operation Request. This is
unique to the Read Command in that the Target device
register must first be setup for a write before you can
read the address. After the Write bit, the Target device
must then reply on the next clock cycle with an
acknowledge (SDA pulled low for 1 bit time) if this
sequence has been received and understood. If this
sequence was not understood or not received, SDA
should be left floating high which will cause the Master
to abort the command.
Register Address Read Sequence: The I2C Master
transmits the 8-bit register address of the Target device
to which the following data will be read. The Target
device will then reply on the next clock cycle with an
acknowledge (SDA pulled low for 1 bit time) if this
command has been received and understood. If the bit
was not understood or not received, SDA will be left
floating high which will cause the Master to abort the
command.
Restart Read Sequence: SDA transitions from high to
low while SCL is held high. This is initiated by the I2C
Master. This is a required restart for the Read
Command.
Device Address + R/W Read Sequence 2: The
Target device’s 7 bit I2C address is transmitted from
the I2C Master on the SDA line, MSB first. If the
transmitted I2C Target device address is not identical
to the device of interest, the device of interest may then
ignore the entire Read command (until Stop Sequence)
as it is not the Target device. for the associated SDA/
SCL timing as it applies to all sequences listed.
Continuing on in this sequence, the Read/Write bit will
follow the LSB of the Target device address with a
value of 1 for a Read Operation Request. After the
Read bit, the Target device must then reply on the next
clock cycle with an acknowledge (SDA pulled low for 1
bit time) if this sequence has been received and
understood. If this sequence was not understood or not
received, SDA should be left floating high which will
cause the Master to abort the command.
Data Field Read Sequence: The Target device
transmits the 8-bit register value to the I2C Master.
Clock Stretching (holding SCL low) may be used to
hold off the I2C Master clock from clocking out data
when the Target device is not ready. The I2C Master
must then reply on the next clock cycle with an
acknowledge (SDA pulled low for 1 bit time) if this
sequence has been received and understood. If this
sequence was not understood or not received, SDA will
be left floating high which will cause the Master to abort
the command.
Data Field Read Sequence Continued: The Target
device may continue to transmit read data without the
I2C Master having to resend the commands:
• Start Read Sequence
• Device / Address & R/W Read Sequence 1
• Register Address Read Sequence
• Restart Read Sequence
• Device Address + R/W Read Sequence 2.
When the associated register bit is set in 0x03h, the
Target’s register address pointer will auto increment
with each transmitted 8-bit word as long as an
acknowledge was received by the Target device from
the Master as in previous read sequences.
Stop Read Sequence: SDA transitions from low to high
while SCL is held high. This is initiated by the I2C
Master.
Current Address Read
The Current Address Read method only works from a
starting read address of 0x00h. This is due to the fact
that the register address is not defined in this
shortened read method.
Start Read Sequence: SDA transitions from high to low
while SCL is held high. This is initiated by the I2C
Master.
Revision 5.04 Data Sheet 29
S4882 Data Sheet
Serial Peripheral Interface
(SPI)
Device Address + R/W Read Sequence: The Target
device’s 7 bit I2C address is transmitted from the I2C
Master on the SDA line, MSB first. If the transmitted
I2C Target device address is not identical to the device
of interest, the device of interest may then ignore the
entire Read command (until Stop Sequence) as it is not
the Target device.
Continuing on in this sequence, the Read/Write bit will
follow the LSB of the Target device address with a
value of 1 for a Read Operation Request. After the
Read bit, the Target device must then reply on the next
clock cycle with an acknowledge (SDA pulled low for 1
bit time) if this sequence has been received and
understood. If this sequence was not understood or not
received, SDA should be left floating high which will
cause the Master to abort the command.
Data Field Read Sequence: The Target device
transmits the 8-bit register value to the I2C Master.
Clock Stretching (holding SCL low) may be used to
hold off the I2C Master clock from clocking out data
when the Target device is not ready. The I2C Master
must then reply on the next clock cycle with an
acknowledge (SDA pulled low for 1 bit time) if this
sequence has been received and understood. If this
sequence was not understood or not received, SDA will
be left floating high which will cause the Master to abort
the command.
Data Field Read Sequence Continued: The Target
device may continue to transmit read data without the
I2C Master having to resend the commands:
• Start Read Sequence
• Device / Address & R/W Read Sequence
When the associated register bit is set in 0x03h, the
Target’s register address pointer will auto increment
with each transmitted 8-bit word as long as an
acknowledge was received by the Target from the
Master as in previous read sequences.
Stop Read Sequence: SDA transitions from low to high
while SCL is held high. This is initiated by the I2C
Master.
Serial Peripheral Interface (SPI)
S4882 has the option to use a simple SPI bi-directional
serial bus for efficient inter-IC control. All register
controlled features and functions are programmed via
the SPI bus. A detailed register map description can
found in the S4882 Programmer’s Reference Manual
(PRM2005). The SPI bus is a simple communications
system with a Master which shifts data into the Slave
while the Slave simultaneously shifts data out. Serial
EEPROM manufacturers have developed a defacto
standard protocol for write and reads over SPI that are
supported by the S4882’s SPI interface. SPI uses two
pins to define the operating mode: CPOL (Clock
Polarity) and CPHA (Clock Phase). The S4882
supports two of these modes:
Mode 0,0: (CPOL = 0, CPHA = 0)
Mode 1,1: (CPOL = 1, CPHA = 1)
From a Slave point of view, both modes are identical
when using the standard protocol (data is sampled on
the rising edge of the clock and presented on the falling
edge of the clock). The SPI interface operates at a
SCK frequency up to 10 MHz.
SPI Pin Signals
SCK: SPI Clock. SCK is a S4882 input that
synchronizes the data transfer between the Master and
S4882 (Slave) device. As a Slave, the S4882 ignores
the SCK signal unless the Slave Select pin (/SS) is
active. In both supported modes for both the Master
and S4882 (Slave) SPI devices, data is shifted out on
the falling edge of SCK and is sampled on the rising
edge where data is stable.
MISO: Master In Slave Data Out.
MOSI: Master Out Slave Data In.
/SS: Slave Select. This pin is used to enable the SPI
Slave (S4882) for a transfer. If the /SS pin of the S4882
is inactive, the device ignores SCK clocks and keeps
the MISO output pin in the high-impedance state.
30 Data Sheet Revision 5.04
S4882 Data Sheet
Serial Peripheral Interface
(SPI)
SPI Protocol
Register reads and writes will follow a protocol similar
to SPI implementations for serial EEPROMs. Read and
write transfers are at least three bytes in length with the
first byte containing the 2-bit read or write opcode, the
second byte containing the register address, and the
third byte containing the write data or returned read
data.
Multi-byte reads and writes are accomplished by simply
continuing to write (or read) bytes while /SS remains
active and the associated bit is set in register 0x03h.
The Slave Select line (/SS) must go active before the
transfer begins and must go inactive after the transfer
ends. To maintain this protocol /SS cannot remain or
be tied active low. This requirement differs from
allowable /SS behavior when CPHA= 1 in the original
SPI specification.
The READ opcode is 00000011b and the WRITE
opcode is 00000010b. A detected invalid opcode will
result in no registers being written and the MISO output
will remain high Z.
Figure 4: SPI Write Protocol
Figure 5: SPI Read Protocol
0678 1516 23
10A7 A0
OPCODE REGISTER ADDRESS
D7 D0 D7 D0
/SS
SCK
MOSI
BYTEn BYTEn+1
MISO
SPI Write to the
S4882
HIGH Z
0 6 7 8 15 16 23
1 1 A7 A0
OPCODE REGISTER ADDRESS
D7 D0 D7 D0
/SS
SCK
MOSI
BYTEn BYTEn+1
MISO
SPI Read from the
S4882
HIGH Z
Revision 5.04 Data Sheet 31
S4882 Data Sheet
SONET/SDH Jitter
Characteristics
SONET/SDH Jitter Characteristics
SONET/SDH Performance
The S4882 PLL complies with the jitter specifications
proposed for SONET/SDH equipment as defined by
Table 1.
SONET Input Jitter Tolerance
Input jitter tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. SONET input jitter tolerance requirements are
shown in Table 6 and Figure 6. The measurement
condition is the input jitter amplitude that causes an
equivalent of 1 dB power penalty.
Figure 6: SONET Input Jitter Tolerance
Note: REFCLK for SONET/SDH/OTU1 Application. AppliedMi-
cro recommends a 155.52 MHz REFCLK for best perfor-
mance. See Figure 21
SONET Jitter Transfer
Jitter transfer function is defined as the ratio of jitter on
the output OC-N/STS-N signal to the jitter applied on
the input OC-N/STS-N signal versus jitter frequency.
Jitter transfer requirements are shown in Figure 7. The
measurement condition is that input sinusoidal jitter up
to the mask level in Figure 6 be applied for each of the
OC-N/STS-N rates.
Figure 7: SONET Jitter Transfer
SONET Jitter Generation
The jitter generation of the serial clock and serial data
outputs shall not exceed the value specified in Table 19
when a serial data input with no jitter is presented to
the serial data input. The REFCLK input must meet the
phase noise requirements shown in Figure 21.
Table 6: SONET Jitter Tolerance
Parameter Min Typ Units Conditions
Jitter
Tol era nce
STS-48
0.4 0.65 UI 1 MHz < f < 20 MHz
1.5 4 UI 6 kHz < f < 100 kHz
15 20 UI 10 Hz < f < 600 Hz
Jitter
Tol era nce
STS-12
0.4 0.65 UI 250 kHz < f < 5 MHz
1.5 4 UI 300 Hz < f < 25 kHz
15 20 UI 10 Hz < f < 30 Hz
f0 f1 f2 f3 ft
0.15
1.5
15
Sinusoidal
Input Jitter
Amplitude
(UI p-p)
Frequency
OC/STS
Level
f 0
(Hz)
f 1
(Hz)
f 2
(Hz)
f 3
(kHz)
f t
(kHz)
12 10 30 300 25 250
300 6.5 6530103
48 10 600 6000 100 1000
Jitter
Tolerance
STS-3
0.4 0.8 UI 65 kHz < f < 1.3 MHz
1.5 5 UI 300 Hz < f < 6.5 kHz
15 22 UI 10 Hz < f < 30 Hz
Table 6: SONET Jitter Tolerance
Parameter Min Typ Units Conditions
fc
P
Jitter
Transfer
Frequency
Acceptable
Range
slope = -20 dB/
decade
OC/STS
Level
fc
(kHz)
P
(dB)
12 500 0.1
130 0.13
48 2000 0.1
32 Data Sheet Revision 5.04
S4882 Data Sheet
SONET/SDH Jitter
Characteristics
SDH Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty.
According to the G.825 SDH Jitter Tolerance
specification, the regenerators must tolerate input jitter
defined by curve shown in Figure 8:
Figure 8: SDH Input Jitter Tolerance Specification
Frequency
f (Hz) Requirement (Peak-to-Peak)
2048 kbit/s Network 1544 kbit/s Network
10 < f < 70.9 1063.5 f-1 UI
70.9 < f < 500 15 UI
10 < f < 12.1 622 UI
12.1 < f < 500 7500 f-1 UI
500 < f< 5 k 7500 f-1 UI
5 k < f< 100 k 1.5 UI
100 k < f< 1 M 1.5 x 105 f-1 UI
1.0E+00
1.0E+01
1.0E+02
1.0E+01
1.0E+03
1.0E+05
1.0E–01
1.0E+00
1.0E+02
1.0E+04
Frequency (Hz)
1.0E+06
1.0E+07
Pk-Pk Phase Amplitude (UI)
1.0E+03
1.0E+08
NOTE – The dashed curve is the requirement for 1544
kbit/s networks for frequencies less than 500 Hz.
Revision 5.04 Data Sheet 33
S4882 Data Sheet
Gigabit Ethernet Jitter
Characteristics
Gigabit Ethernet Jitter
Characteristics
GE Performance
The S4882 complies with the jitter specifications pro-
posed for Gigabit Ethernet equipment as defined by
IEEE.
GE Input Jitter Tolerance
Input Jitter Tolerance is defined as the ability of the
circuit to correctly recover an incoming data stream
despite the presence of jitter. It is characterized by the
amount of jitter required to produce a specified bit error
rate. The reference point for jitter tolerance is always
the TP4 point. The tolerance depends upon the
frequency content of the jitter. The numbers shown in
Table 7 represent high frequency jitter (above 637 kHz)
and do not include low frequency jitter or wander.
GE Jitter Generation
The jitter of the serial data outputs shall not exceed the
value specified in Table 8 when a serial data stream
with no jitter is presented to the serial data inputs.
Figure 9: Gigabit Ethernet System Node Definition
Table 7: Gigabit Ethernet Input Jitter Tolerance
Specification
Compliance Point Total Jitter Deterministic Jitter
TP4 UI psec UI psec
0.749 599 0.462 370
Table 8: Gigabit Ethernet Output Jitter
Generation
Compliance Point Total Jitter Deterministic Jitter
TP1 UI psec UI psec
0.24 192 0.10 80
Patch
Cord
P
M
A
P
M
A
Signal_Detect
Optical Cable Plant
(Channel)
System Bulkheads
MDI MDI
Optical
PMD
Transmitter
Optical
PMD
Receiver
TP1
TP2 TP3
TP4
R+
R-
T+
T-
34 Data Sheet Revision 5.04
S4882 Data Sheet
Fibre Channel Jitter
Characteristics
Fibre Channel Jitter
Characteristics
FC Performance
The S4882 PLL complies with the jitter specifications
proposed for Fibre Channel.
FC Input Jitter Tolerance
Input Jitter Tolerance is defined as the peak to peak
amplitude of sinusoidal jitter applied on the input signal
that causes an equivalent 1 dB optical/electrical power
penalty. Fibre channel input jitter tolerance
requirements are shown in Table 9.
FC Jitter Generation
The jitter of the serial clock and serial data outputs
shall not exceed the value specified in Table 10 when a
serial data stream with no jitter is presented to the
serial data inputs.
Table 9: Fibre Channel Input Jitter Tolerance Specification at node
α
R
Parameter Description Min Max Units
1GFC
tFDJ Frequency Dependent Jitter Tolerance (637 kHz - 5 MHz) 0.10 UI p-p
tDJ Deterministic Jitter Tolerance (637 kHz - 531 MHz) 0.37 UI p-p
tRJ Random Jitter (637 kHz - 531 MHz) 0.21 UI p-p
tTJ Total Jitter 0.68 UI p-p
2GFC
tFDJ Frequency Dependent Jitter Tolerance (1274 kHz - 5 MHz) 0.10 UI p-p
tDJ Deterministic Jitter Tolerance (1274 kHz - 1062 MHz) 0.37 UI p-p
tRJ Random Jitter (1274 kHz - 1062 MHz) 0.20 UI p-p
tTJ Total Jitter 0.67 UI p-p
4GFC
tFDJ Frequency Dependent Jitter Tolerance (1274 kHz - 5 MHz) 0.10 UI p-p
tDJ Deterministic Jitter Tolerance (2.55 MHz - 2125 MHz) 0.38 UI p-p
tRJ Random Jitter (2.55 MHz - 2125 MHz) 0.19 UI p-p
tTJ Total Jitter 0.67 UI p-p
Revision 5.04 Data Sheet 35
S4882 Data Sheet
Fibre Channel Jitter
Characteristics
Figure 10: Fibre Channel System Node Definition
Table 10: Fibre Channel Total Jitter Generation at node
α
T
Parameter Description Min Max Units
DJ Deterministic Jitter 0.18 UI p-p
TJ Total Jitter 0.23 UI p-p
SYSTEM
STORAGE
DISK DRIVE
SERDES
αR =Component Receiver Node
SYSTEM
HOST ADAPTOR
SERDES
αT = Component Transmitter Node
BACKPLANE
PCB
REPEATERS
CABLES
CONNECTORS
36 Data Sheet Revision 5.04
S4882 Data Sheet
HDTV Jitter Characteristics
HDTV Jitter Characteristics
HDTV Performance
The S4882 complies with the jitter specifications
proposed for High Definition Serial Digital Interface
(HD-SDI) systems as defined by SMPTE. Jitter is
measured with reference to Figure 11 to Figure 17 as
shown below. The required Bit Error Rate (BER) for
spec compliance is 1E-14 (using 27-1 PRBS).
HDTV Jitter Transfer
The jitter transfer function is defined as the ratio on the
output signal (Point 3) to the jitter applied on the input
(Point 2) versus frequency. HDTV jitter transfer
requirements are shown in Figure 12. The
measurement condition, input sinusoidal jitter up to the
mask level in Figure 13, is applied.
HDTV Intrinsic Jitter
Intrinsic jitter has two components, alignment and
timing jitter, and is measured from point 2 to point 3 on
Figure 11. Alignment jitter is the variation in position of
a signal’s transitions relative to that of the clock that is
extracted from that signal. The bandwidth of the clock
extraction process determines the low frequency limit
for alignment jitter. Timing jitter is the variation in
position of a signal’s transitions occurring at a rate
greater than a specified frequency. Variations below
this specified frequency are termed “wander” and are
not considered. The remaining figures (Figure 14
through Figure 17) illustrate the HDTV Timing Jitter Input
Mask, Output Timing Jitter Specification, the Alignment
Jitter Input Mask, and the Output Alignment Jitter
Specification.
Jitter performance was characterized for HDTV with
the 27-1 PRBS pattern.
The proper INI file is required for HDTV operation.
Please consult the AppliedMicro support team.
Figure 11: HDTV Jitter Measurement Points
Figure 12: HDTV Jitter Transfer Specification
DeserializerRetimerSerializer
01234 5
10 kHz 1 MHz
0.2
_20 dB/decade
Jitter Frequency
Output Jitter
(dB)
Revision 5.04 Data Sheet 37
S4882 Data Sheet
HDTV Jitter Characteristics
Figure 13: HDTV Input Jitter Tolerance Mask
Figure 14: HDTV Timing Jitter Input Mask Specification
Figure 15: HDTV Output Timing Jitter Specification
20 kHz 100 kHz
0.2 UI
_20 dB/decade
Jitter Frequency
10 MHz
10 kHz
1 UI
Sinusoidal Input
Jitter Amplitude
(RMS)
10 Hz
0
_20 dB/decade
Jitter Frequency
+20 dB/decade
Timing Jitter Input (dB)
fCLK
10
10 Hz 10 MHz
1.0
Jitter Frequency
Outptu Timing Jitter
UI (P-P)
38 Data Sheet Revision 5.04
S4882 Data Sheet
HDTV Jitter Characteristics
Figure 16: HDTV Alignment Jitter Input Mask Specification
Figure 17: HDTV Output Alignment Jitter Specification
100 kHz fCLK
10
0
Alignment Jitter Input
(dB)
Jitter Frequency
100 kHz 10 MHz
0.2
Outptu Alignment Jitter UI
(P-P)
Jitter Frequency
Revision 5.04 Data Sheet 39
S4882 Data Sheet
Generic Protocol Jitter
Peaking Characteristics
Generic Protocol Jitter Peaking
Characteristics
Generic Protocol Jitter Peaking
Jitter peaking for a given transition density will be
specified for those data rates or protocols for which
jitter transfer has not been specified. Table 11 below
lists the data rates as well as the minimum transition
density (unchanging bit times) for which the jitter
transfer is 2 dB or less.
Table 11: Generic Protocol Minimum Transition Density for Jitter Transfer Peaking
Description Data Rate Band
Minimum Transition Density for
which Jitter Gain < 2 dB (Bit Time)
10base-X Ethernet 10 Mbps 0.5
100base-X Ethernet / Fast Ethernet 125 Mbps 0.5
SONET/SDH STS-3/STM-1 / OC-3 155.52 Mbps 0.5
ESCON / SBCON 200 Mbps 0.5
Fibre Channel (1/4 Rate) 265.625 Mbps 0.5
Fibre Channel (1/2 Rate) 531.25 Mbps 0.5
SONET/SDH STS-12/STM-4 / OC-12 622.08 Mbps 0.5
Fibre Channel 1.0625 Gbps 0.5
1000base-X Ethernet / Gigabit Ethernet 1.250 Gbps 0.5
SMPTE 292M 1.485 Gbps 0.5
Fibre Channel (2X) 2.125 Gbps 0.5
SONET/SDH STS-48/STM-16 / OC-48 2.488 Gbps 0.5
ITU G.709 / OTU-1 2.666 Gbps 0.5
XAUI 3.125 Gbps 0.5
Fiber Channel (4X) 4.250 Gbps 0.5
40 Data Sheet Revision 5.04
S4882 Data Sheet
Pin Assignments and
Descriptions
Pin Assignments and Descriptions
Table 12: S4882 Transmitter Pin Assignments and Descriptions
Pin Name Level I/O Pin # Description
TX Serial Interface
TSDP
TSDN
CML
CML
O
O
M8
L8
Transmit Serial Data Output. This signal is normally connected to a Trans-
mitter Optical Sub-Assembly (TOSA). The maximum serial data rate sup-
ported by this output is 4.25 Gbps. When in SCI mode, this output may be
optionally wave shaped with AppliedMicro’s De-Emphasis circuitry as well
as Differentially Encoded.
TSCLKP
TSCLKN
CML
CML
O
O
M7
L7
Transmit Serial Clock Output. This signal is normally connected to a Trans-
mitter Optical Sub-Assembly (TOSA). The maximum frequency supported
by this output is 4.25 GHz. This clock may be powered down with the
TX_TSCLK_PD register bit when SCI mode is enabled.
TX Parallel Interface and Clocking
PIN[9]P
PIN[9]N
PIN[8]P
PIN[8]N
PIN[7]P
PIN[7]N
PIN[6]P
PIN[6]N
PIN[5]P
PIN[5]N
PIN[4]P
PIN[4]N
PIN[3]P
PIN[3]N
PIN[2]P
PIN[2]N
PIN[1]P
PIN[1]N
PIN[0]P
PIN[0]N
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
G3
G4
H3
H4
G1
G2
H1
H2
J4
J5
J1
J2
K3
K4
K2
K1
L1
L2
L3
L4
TX Parallel Input Data Bus: Internally terminated and biased.
A data bus with programmable width (4/8/10-bits wide or 4-bit Redundant
Data mode which only uses PIN[7:4]P/N). The data is aligned to the associ-
ated clock, PICLKLP/N (or PICLKUP/N in 4-bit Redundant Data mode). The
Bus width & PICLKxP/N assignments are:
Normal Mode (Denoted by Functions with a L for Lower)
4-bit = PIN[3:0]P/N sampled by PICLKLP/N
8-bit = PIN[7:0]P/N sampled by PICLKLP/N
10-bit = PIN[9:0]P/N sampled by PICLKLP/N
Any unused PIN[X]P/N pairs are ignored and not processed by the S4882
4-bit Redundant Data Mode (Denoted by Functions with a U for Upper)
PIN[7:4]P/N = Data sampled by PICLKUP/N:
PIN[9]P/N = PINPARUP/N
Any unused PIN[X]P/N pairs are ignored and not processed by the S4882
In normal mode, the PIN[X:0]P/N bus will be sampled on the rising edge of
the associated PICLKxP/N. In Double Data Rate mode (DDR), the data is
sampled on both the rising and falling edges of the associated PICLKxP/N.
PIN[0]P/N is the most significant bit (corresponding to bit 1 of each PCM
word, the first bit transmitted). PIN[9]P/N is the least significant bit (corre-
sponding to bit 10 of each PCM word, the last bit transmitted).
When the TX_PIN_BITSWAP bit is active, the PINP/N labels 0 to 9 will be
reversed in order from what is stated in this table. Example: PIN[2]P will
become PIN[7]P. When the TX_PIN_POLINV bit is active the P & N posi-
tions of each pair will swap positions from what is stated in this table.
The maximum allowable data rate per PIN[X:0]P/N pair is 800 Mbps thus
making the maximum device data rate in all 4-bit modes as 3.2 Gbps
Revision 5.04 Data Sheet 41
S4882 Data Sheet
Pin Assignments and
Descriptions
PICLKLP
PICLKLN
LVDS
LVDS
I
I
E1
E2
TX Parallel Input Clock Lower: Internally terminated & biased.
This input clock is associated with all parallel data bus configurations except
the 4-bit Redundant Data mode as stated in the PIN[X:0]P/N section of the
pin assignments. If Redundant Data mode is being used these input pins
may be tied off.
This input is a nominally 50% duty cycle input clock, to which the PIN[X:0]P/
N parallel data bus is aligned. PICLKLP/N is used to transfer the data on the
PIN[X:0]P/N inputs. While under normal operating conditions, the rising edge
of PICLKLP/N samples the PINP/N data. In Double Data Rate mode, both the
rising and falling edges of PICLKLP/N sample the PINP/N data but the clock
rate is reduced by half to compensate accordingly. The maximum allowable
clock rate on this PICLKLP/N input is 800 MHz.
PICLKUP
PICLKUN
LVDS
LVDS
I
I
F2
F3
TX Parallel Input Clock Upper: Internally terminated & biased.
This input clock is only associated with PIN[7:4]P/N when 4-bit Redundant
Data mode is enabled. If Redundant Data mode is not enabled these input
pins may be tied off.
This input is a nominally 50% duty cycle input clock, to which the PIN[X:0]P/
N parallel data bus is aligned. PICLKUP/N is used to transfer the data on the
PIN[7:4]P/N inputs while in 4-bit Redundant Data mode. While under normal
operating conditions the rising edge of PICLKUP/N samples the PINP/N[3:0]
data. In Double Data Rate mode, both the rising and falling edges of
PICLKUP/N sample the PINP/N[3:0] data but the clock rate is reduced by half
to compensate accordingly. The maximum allowable clock rate on this
PICLKUP/N input is 800 MHz.
PCLKLP
PCLKLN
LVDS
LVDS
O
O
D9
C9
TX Parallel Clock Lower Output.
A reference clock generated by dividing the internal TX CSU bit clock appro-
priately to create a frequency locked source for the PICLKLP/N. This output
clock is associated with all parallel data bus configurations except 4-bit
Redundant Data mode, as stated in the PIN[X:0]P/N section of the pin
assignments. If Redundant Data mode is active these output pins may be
left floating as they will be at a zero voltage state.
Both PCLKLP/N and PICLKLP/N must remain frequency locked since they
are the respective read and write clocks for the S4882’s internal FIFO. The
internal FIFO will absorb any phase differential. PCLKLP/N may be alter-
nately sourced from the receive channel’s recovered clock if SLPTIME or
LLEB mode is enabled. Both PCLKLP/N and PCLKUP/N may be simulta-
neously powered down with the TX_PIN_MUTEPCLK register bit.
Table 12: S4882 Transmitter Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin # Description
42 Data Sheet Revision 5.04
S4882 Data Sheet
Pin Assignments and
Descriptions
PCLKUP
PCLKUN
LVDS
LVDS
O
O
B10
A10
TX Parallel Clock Upper Output.
A reference clock generated by dividing the internal TX CSU bit clock appro-
priately to create a frequency locked source for the PICLKUP/N. This output
clock is only associated with 4-bit Redundant Data mode. If Redundant Data
mode is not being used these output pins may be left floating as they will be
at a zero voltage state.
Both PCLKUP/N and PICLKUP/N must remain frequency locked since they
are the respective read and write clocks for the S4882’s internal FIFO. The
internal FIFO will absorb any phase differential. PCLKUP/N may be alter-
nately sourced from the receive channel’s recovered clock if SLPTIME or
LLEB mode is enabled. Both PCLKUP/N and PCLKLP/N may be simulta-
neously powered down with the TX_PIN_MUTEPCLK register bit.
PINPARLP
PINPARLN
LVDS
LVDS
I
I
M2
M3
TX Parallel Input Parity Lower
This input expects the generated parity signal for the associated PIN[X:0]P/N
data word. This input is associated with all parallel data bus configurations
except 4-bit Redundant Data mode. The equivalent pins for Redundant Data
mode are the PIN[9]P/N input pins as stated in the PIN[X:0]P/N section of the
pin assignments. If Redundant Data mode is being used these input pins
may be tied off.
Parity must be enabled via I2C or SPI access to the register set. Parity type
(even/odd) and alarms are also only available via register access.
TXMCKP
TXMCKN
LVDS
LVDS
O
O
A12
B12
CSU Monitor Clock Output. This is a utility clock that is a divided down ver-
sion of the TSCLKP/N. The divider value matches the width of the PIN[x:0]P/
N bus. This clock may be muted to varying values or powered down when
SCI mode is enabled via registers 0xE0-E1h.
Table 12: S4882 Transmitter Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin # Description
Revision 5.04 Data Sheet 43
S4882 Data Sheet
Pin Assignments and
Descriptions
Table 13: S4882 Receiver Pin Assignments and Descriptions
Pin Name Level I/O Pin # Description
RX Serial Interface
RSDP
RSDN
RSDC
CML
CML
CML
I
I
I
M5
L5
K5
Receive Serial Data Input. This signal is normally connected to a
Receiver Optical Sub-Assembly (ROSA). A clock is recovered from tran-
sitions on the RSDP/N inputs. The maximum serial data rate supported by
this input is 4.25 Gbps.
RSDC is a center tap capacitor connection. It creates a center ground
between two 50 Ohms input resistors. This pin is important for the input’s
sensitivity and symmetry. A capacitor of 1nF or larger should be con-
nected from this pin to ground
RX Parallel Interface and Clocking
POUT[9]P
POUT[9]N
POUT[8]P
POUT[8]N
POUT[7]P
POUT[7]N
POUT[6]P
POUT[6]N
POUT[5]P
POUT[5]N
POUT[4]P
POUT[4]N
POUT[3]P
POUT[3]N
POUT[2]P
POUT[2]N
POUT[1]P
POUT[1]N
POUT[0]P
POUT[0]N
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
B8
A8
E7
E8
C6
C7
A6
A7
B5
B6
A4
A5
C4
C5
A3
A2
B3
B4
C1
C2
RX Parallel Output Data Bus
A data bus with programmable width (4/8/10-bits wide or 4-bit Redundant
Data mode which only uses POUT[7:4]P/N). The data is aligned to the
associated POCLKLP/N (or POCLKUP/N in 4-bit Redundant Data mode).
The Bus width & POCLKxP/N assignments are:
Normal Mode (Denoted by Functions with a L for Lower)
4-bit = POUTP/N[3:0] sampled by POCLKLP/N
8-bit = POUTP/N[7:0] sampled by POCLKLP/N
10-bit = POUTP/N[9:0] sampled by POCLKLP/N
Any unused POUT[X]P/N pairs are in a powered down state.
4-bit Redundant Data Mode (Denoted by Functions with a U for Upper)
POUTP/N[7:4] = Output Data Sampled by POCLKUP/N
POUTP/N[8] = FPOUTUP/N
POUTP/N[9] = POUTPARUP/N
Any unused POUT[X]P/N pairs are in a powered down state.
In normal mode, the POUT[X:0]P/N bus will be sampled on the falling
edge of the associated POCLKxP/N. In Double Data Rate mode (DDR),
the data is sampled on both the rising and falling edges of the associated
POCLKxP/N. POUT[0]P/N is the most significant bit (corresponding to bit 1
of each PCM word, the first bit transmitted). POUT[9]P/N is the least sig-
nificant bit (corresponding to bit 10 of each PCM word, the last bit trans-
mitted).
When the RX_POUT_BITSWAP bit is active, the POUTP/N labels 0 to 9
will be reversed in order from what is stated in this table. Example:
POUT[2]P will become POUT[7]P. When the RX_POUT_POLINV bit is
active, the P & N positions of each pair will swap positions from what is
stated in this table.
The maximum allowable data rate per POUT[X:0]P/N pair is 800 Mbps
thus making the maximum device data rate in all 4-bit modes as
3.2 Gbps.
44 Data Sheet Revision 5.04
S4882 Data Sheet
Pin Assignments and
Descriptions
POCLKLP
POCLKLN
LVDS
LVDS
O
O
D8
C8
RX Parallel Output Clock Lower
This output clock is associated with all parallel data bus configurations
except 4-bit Redundant Data mode as stated in the POUT[X:0]P/N section
of the pin assignments. If Redundant Data mode is being used these out-
put pins may be left floating as they will be in a powered down state.
This output is a nominally 50% duty cycle output clock, to which the
POUT[X:0]P/N bus is aligned. POCLKLP/N is used to transfer the data on
the POUT[X:0]P/N outputs. While under normal operating conditions, the
falling edge of POCLKLP/N is aligned with the POUT[X:0]P/N parallel data
bus. In Double Data Rate mode, both the rising and falling edges of
POCLKLP/N are aligned with the POUT[X:0]P/N parallel data bus but the
clock rate is reduced by half to compensate accordingly. The maximum
allowable clock rate on this POCLKLP/N output is 800 MHz.
POCLKUP
POCLKUN
LVDS
LVDS
O
O
B9
A9
RX Parallel Output Clock Upper
This output clock is only associated with 4-bit Redundant Data mode. If
Redundant Data mode is being used these output pins may be left float-
ing as they will be in a powered down state.
This output is a nominally 50% duty cycle output clock, to which the
POUT[X:0]P/N parallel data bus is aligned. POCLKUP/N is used to trans-
fer the data on the POUT[7:4]P/N outputs while in 4-bit Redundant Data
mode. While under these operating conditions the falling edge of
POCLKUP/N is aligned with the POUT[7:4]P/N parallel data bus. In Dou-
ble Data Rate mode, both the rising and falling edges of POCLKUP/N are
aligned with the POUT[7:4]P/N parallel data bus but the clock rate is
reduced by half to compensate accordingly. The maximum allowable
clock rate on this POCLKUP/N output is 800 MHz.
POUTPARLP
POUTPARLN
LVDS
LVDS
O
O
B2
B1
RX Parallel Output Parity
This output pair contains the generated parity signal for the associated
POUT[X:0]P/N data word. This output is associated with all parallel data
bus configurations except 4-bit Redundant Data mode. The equivalent
pins for Redundant Data mode are the POUT[9]P/N output pins as stated
in the POUT[X:0]P/N section in the pin assignments. If Redundant Data
mode is being used, these output pins may be left floating as they will be
in a powered down state.
Parity must be enabled via I2C or SPI access to the register set. Parity
type (even/odd) and alarms are also only available via register access.
RXMCKP
RXMCKN
LVDS
LVDS
O
O
D1
D2
RX PLL Monitor Clock Output. This is a utility clock that is a divided down
version of the RX PLL VCO clock. The default divider value matches the
width of the POUT[X:0]P/N bus. This clock may be muted to varying val-
ues when SCI mode is enabled via register 0x05h.
Table 13: S4882 Receiver Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin # Description
Revision 5.04 Data Sheet 45
S4882 Data Sheet
Pin Assignments and
Descriptions
REFCLK
REFCLK0P
REFCLK0N
CML
CML
I
i
K12
L12
CML Reference Clock0. 100 MHz to 200 MHz frequency selectable as
controlled by the RXREFSEL settings. This reference clock seeds the RX
CDR in its default configuration. It will be used as the seed and frequency
hold source for the RX CDR unless the associated register map bits are
reprogrammed while in SCI mode. When reprogrammed it may also be
used to simultaneously (or separately) source the TX CSU’s REFCLK fre-
quency.
Consult the Table 4 for a list of the available REFCLK input frequencies.
Any of the listed REFCLK clock frequencies may be used to synthesize
one of the devices listed rates. Clock rate selection should be based on
desired performance (higher rate = better performance) and availability/
cost.
REFCLK0 has to be connected and driven all the time.
Note: It is recommended that the same reference clock source be used
for both REFCLK0 and REFCLK1 or that any possibility of a ppm offset
between the two inputs is eliminated to maintain jitter generation perfor-
mance specified in the data sheet. For example, REFCLK1 is fed from a
622.08MHz PLL and REFCLK0= REFCLK1/4= 622.08MHz PLL/4=
155.52MHz. Or, simply use a single 155.52MHz reference clock on
REFCLK0 for both Rx and Tx side.
REFCLK1P
REFCLK1N
CML
CML
I
I
M11
M10
CML Reference Clock1. 100 MHz to 667 MHz frequency selectable as
controlled by the TXREFSEL settings. This reference clock seeds the TX
CDR in its default configuration. It will be used as the seed and frequency
hold source for the TX CSU unless the associated register map bits are
reprogrammed while in SCI mode. When reprogrammed it may also be
used to simultaneously (or separately) source the RX CDR’s REFCLK fre-
quency.
Consult the Table 4 for a list of the available REFCLK input frequencies.
Any of the listed REFCLK clock frequencies may be used to synthesize
one of the devices listed rates. Clock rate selection should be based on
desired performance (higher rate = better performance) and availability/
cost.
Note: It is recommended that the same reference clock source be used
for both REFCLK0 and REFCLK1 or that any possibility of a ppm offset
between the two inputs is eliminated to maintain jitter generation perfor-
mance specified in the data sheet. For example, REFCLK1 is fed from a
622.08MHz PLL and REFCLK0= REFCLK1/4= 622.08MHz PLL/4=
155.52MHz. Or, simply use a single 155.52MHz reference clock on
REFCLK0 for both Rx and Tx side.
Table 13: S4882 Receiver Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin # Description
46 Data Sheet Revision 5.04
S4882 Data Sheet
Pin Assignments and
Descriptions
Table 14: S4882 Global Control Pin Assignments and Descriptions
Pin Name Level I/O Pin# Description
General Inputs
SCI LVCMOS
Pull Up
I H12 Serial Control Interface Enable. Active High.
When active the I2C and SPI ports are enabled and ready for access via a
micro processor or another standard controller device. When Inactive the
associated I2C and SPI I/O pins are used by other control functions as
shown in the S4882 Shared or Register Equivalent Pin Assignments and
Descriptions table below.
This pin requires a Hard Reset (/RST) for a change of state to take affect.
TCK
TDI
TDO
TMS
LVCMOS
LVCMOS
Pull Up
LVCMOS
LVCMOS
Pull Up
I
I
O
I
G6
G7
D11
G8
JTAG Port.
JTAG Clock (TCK)
Data Input (TDI)
Data Output (TDO)
Mode Select (TMS).
For normal device operation TMS should be pulled low. Maximum sup-
ported rate by this interface is 10 MHz.
SD LVCMOS
Pull Up
I K9 Signal Detect. Active High - Default.
Signal to be driven by the external ROSA to indicate that sufficient received
optical power has been received. When active, the ROSA is indicating that
proper optical power is being received and that the data should be processed
normally. When inactive, the ROSA will be indicating that there is a problem
with the received optical power and the S4882 will squelch the data on the
Serial Data Input (RSDP/N) pins per the RSD squelch settings, RXLOCK will
be forced low causing the PLL to lock to the reference. The desired polarity
of this input may be changed via the associated register bit when SCI is ac-
tive.
Note - The following two registers at address 0x30 must be programmed as
follows (RX_CP_INIT = 0, and RX_AFA_EN_CP_INIT = 0) for proper SD op-
eration.
/RST LVCMOS
Pull Up
I G12 Hard Reset. Active Low. Asynchronous reset input for the device. Initializes
all blocks including clock generation blocks. Tie high for normal operation.
ATEST LVCMOS I/O M9 ATest Enable: Used for Factory Test Only
TESTEN LVCMOS
Pull Down
I J12 Test Enable: Used for Factory Test Only
Revision 5.04 Data Sheet 47
S4882 Data Sheet
Pin Assignments and
Descriptions
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions
Pin Name Level I/O Pin Description
Reg
Equiv
Shared
Pin
General Control and Status
MODECFG[2]
MODECFG[1]
MODECFG[0]
LVCMOS
LVCMOS
LVCMOS
Pull Up
I
I/O
I
L11
K11
G11
Mode Configuration. These pins set the S4882’s
mode of operation: [2 1 0] Bit Order
000 = Normal Mode
001 = Parallel Line Loopback Mode (PLLBK)
010 = Serial Diagnostic Loopback Mode (SDLBK)
011 = SLPTIME Mode
100 = Normal Mode with TX_BIST_GEN &
RX_BIST_GEN enabled.
101 = Parallel Line Loopback Mode (PLLBK) with
RX_BIST_GEN enabled.
110 = Serial Diagnostic Loopback Mode (SDLBK)
with TX_BIST_GEN enabled
111 = RESERVED
These pins configure the mode of operation of the
S4882. Some configurations enable loopbacks and
BIST capability. When SCI is active, this function is
controlled by its associated register bits as shown
in the Register Equivalent column. The I/O will be
shared with I2C functions as stated in the Shared
Pin column.
These pins require a Soft (/SOFTRST) or a Hard
Reset (/RST) for a change of state to take affect.
PLLBK:
0x01h
bit 2
SDLBK:
0x01h
bit 5
SLPTime:
0x01h
bit 1
RXBIST
GEN
0x0Bh
bit 0
TXBIST
GEN
0xE5h
bit 0
SCL
SDA
/CE
48 Data Sheet Revision 5.04
S4882 Data Sheet
Pin Assignments and
Descriptions
RATECFG[3]
RATECFG[2]
RATECFG[1]
RATECFG[0]
LVCMOS
LVCMOS
Pull Down
LVCMOS
Pull Down
LVCMOS
Pull Down
I/O
I
I
I
C11
J10
H11
H6
Rate Configuration Input. Bit order = [3 2 1 0]
0000 = N/A
0001 = 10 Base-T Ethernet (10 Mbps)
0010 = 100 Base-T Ethernet (125 Mbps)
0011 = STS-3/STM-1 (155.52 Mbps)
0100 = ESCON/SBCON (200 Mbps)
0101 = FC 0.25x (265.625 Mbps)
0110 = FC 0.50x (531.25 Mbps)
0111 = STS-12/STM-4 (622.08 Mbps)
1000 = FC (1062.5 Mbps)
1001 = 1000 Base-T Ethernet (1250 Mbps)
1010 = SMPTE 292M (1485 Mbps)
1011 = FC 2x (2125 Mbps)
1100 = STS-48/STM-16 (2488.32 Mbps
1101 = ITU-T G.709 (2666.06 Mbps)
1110 = XAUI (3125 Mbps)
1111 = FC 4x (4250 Mbps)
These pins configure both the expected RX and TX
data rates. When SCI is active this function is con-
trolled by its associated register bit as shown in the
Register Equivalent column. This I/O will also be
controlled by another function listed in the Shared
Pin column. Alternate frequencies (denoted as
fixed frequencies) may also be programmed while
in SCI mode. These alternate frequencies may be
programmed within a 10Hz resolution.
These pins require a Soft (/SOFTRST) or a Hard
Reset (/RST) for a change of state to take affect.
For RX
0x17h
bits 7-4
For TX
0xC4h
bits 3-0
/INT
ADDR[2]
ADDR[1]
ADDR[0]
BUSMODE[1]
BUSMODE[0]
LVCMOS
Pull Up
LVCMOS
Pull Up
I
I
H9
H8
Parallel Bus Mode. Bit order = [1 0]
0 0 = 4-bit width (Lower)*
0 1 = 4-bit Redundant Data Mode (Upper)**
1 0 = 8-bit width (Lower)*
1 1 = 10-bit width (Lower)*
These pins configure the width of both the POUT
and PIN parallel data buses. When SCI is active,
this function is controlled by its associated register
bit as shown in the Register Equivalent column.
These pins require a Soft (/SOFTRST) or a Hard
Reset (/RST) for a change of state to take affect.
* Associated with Functions with a L for Lower
** Associated with Functions with a U for Upper
For RX
0x09h
bits 1-0
For TX
0xE2h
bits 1-0
N/A
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin Description
Reg
Equiv
Shared
Pin
Revision 5.04 Data Sheet 49
S4882 Data Sheet
Pin Assignments and
Descriptions
DDR LVCMOS
Pull Down
I J9 Double Data Rate Mode. Active High. When active
the parallel data (POUT and PIN) buses are
clocked in and out on both the rising and falling
edges of the associated clocks. This effectively
allows the external clocking to operate at half the
standard rate.
When SCI is active this function is controlled by its
associated register bit as shown in the Register
Equivalent column. This I/O will also be controlled
by another function listed in the Shared Pin column
while SCI is active.
This pin requires a Soft (/SOFTRST) or a Hard
Reset (/RST) for a change of state to take affect.
For RX
0x07h
bit 0
For TX
0xE2h
bit 2
N/A
SCK
MISO
MOSI
/SS
LVCMOS
Pull Up
LVCMOS
LVCMOS
Pull Up
LVCMOS
Pull Down
I
O
I
I
H10
D10
H7
G10
Serial Peripheral Interface (SPI) Bus
SPI Serial Clock (SCK): Clock that is driven by an
ext. Master device.
SPI Master In Slave Out (MISO): The S4882’s data
output line.
SPI Master Out Slave In (MOSI) is the S4882’s
data input.
SPI Slave Select (/SS) enables the S4882 for SPI
communication.
The S4882 is a slave device in a SPI
communications network. The timing requirements
for the SPI bus are illustrated in Figure Table 23
and Table Table 28. When SCI is inactive this
function is unavailable.
N/A NONE
NONE
NONE
N/A
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin Description
Reg
Equiv
Shared
Pin
50 Data Sheet Revision 5.04
S4882 Data Sheet
Pin Assignments and
Descriptions
SCL
SDA
/CE
ADDR[2]
ADDR[1]
ADDR[0]
LVCMOS
LVCMOS
LVCMOS
Pull Up
LVCMOS
Pull Down
LVCMOS
Pull Down
LVCMOS
Pull Down
I
I/O
I
I
I
I
L11
K11
G11
J10
H11
H6
Inter Integrated Circuit (I2C) Bus.
SCL: Clock driven by an I2C Master Device
SDA: Bi-directional data line
/CE: Chip Enable for S4882 device
ADDR[2:0]: Lower I2C address bits. Allows multiple
S4882’s to exist on the same bus.
Data is clocked in and out of the S4882 device
when the associated chip enable is active and the
requesting device calls the address associated the
appropriate S4882 device. I2C Timing associated
with the S4882 is referenced in Figure 4. Protocol
and Data/Clock timing follow the I2C standard for
100/400 kHz operation. When SCI is inactive this
function is unavailable.
N/A MODECF
G[2]
MODECF
G[1]
MODECF
G[0]
RATE-
CFG[2]
RATE-
CFG[1]
RATE-
CFG[0]
GPIO[3]
GPIO[2]
GPIO[1]
GPIO[0]
LVCMOS
LVCMOS
LVCMOS
LVCMOS
I/0
I/0
I/0
I/0
F10
F9
E12
F11
General Purpose I/O Bus.
Only operates when SCI is enabled (SCI=1). This
port allows values programmed into the register
map to be written out of these pins or allows values
to be read into the register map depending upon
the settings for each one of the GPIO pins
WRITE
0x04h
bits 3-0
READ
0xBBh
bits 3-0
RXREF-
SEL[1]
RXREF-
SEL[0]
TXREF-
SEL[1]
TXREF-
SEL[0]
/SOFTRST LVCMOS
Pull Up
I F12 Soft Reset. Active Low. Clears register values back
to their default state and/or enables newly written
register values when in SCI mode. Tie high for nor-
mal operation.
0x00h
bit 5
N/A
/INT LVCMOS O C11 Summary Interrupt. Active Low.
When active this signal notifies the alarm
monitoring system to begin interrupt servicing.
Interrupts and their associated Masks are only
available via the I2C or SPI buses. When SCI is
inactive, this function is unavailable.
N/A RATE-
CFG[3]
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin Description
Reg
Equiv
Shared
Pin
Revision 5.04 Data Sheet 51
S4882 Data Sheet
Pin Assignments and
Descriptions
RX Control and Status
RXREFSEL[1]
RXREFSEL[0]
LVCMOS
LVCMOS
I/O
I/O
F10
F9
RX REFCLK Frequency Config. Bit order = [1 0]
0 0 =100 MHz
0 1 = 125 MHz
1 0 = 155.52 MHz
1 1 = 622.08 MHz
This input programs the required incoming rate of
both to the transmit side of the S4882. The S4882’s
synthesizers will adjust the internal divide ratios
appropriately based on this setting, the programed
Rate Configuration, and the associated Bus Width.
When SCI is active, this function is controlled by its
associated register bit as shown in the Register
Equivalent column. Additional frequency choices
are available when in SCI mode.This I/O will also
be controlled by another function listed in the
Shared Pin column.
These pins require a Soft (/SOFTRST) or a Hard
Reset (/RST) for a change of state to take affect.
0x17h
bits 3-0
GPIO[3]
GPIO[2]
RXLOCKDET LVCMOS O D12 Receive PLL Lock Indicator. Active High.
When active, this output indicates that the RX PLL
is locked on to the serial data inputs. When inac-
tive, this output indicates that it has lost lock on the
incoming signal. It may then lock on to the local ref-
erence clock while attempting to reacquire the
incoming data signal.
0xA5h
bit 4
N/A
LOS LVCMOS O E11 Loss of Signal. Active High.
This is an output signal that is intended to drive an
external Receiver Optical Sub Assembly (ROSA) to
indicate that insufficient received optical signal has
been detected by the S4882. This is an asynchro-
nous output that may be configured to the users’
own specifications via the I2C or SPI buses while
SCI mode is enabled. See Table 17 for details.
0x82h
bits 2-0
N/A
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin Description
Reg
Equiv
Shared
Pin
52 Data Sheet Revision 5.04
S4882 Data Sheet
Pin Assignments and
Descriptions
FPOUTLP
FPOUTLN
LVDS
LVDS
O
O
B11
A11
Frame Pulse Output. Active High.
When the RX_FRAME bit or the associated
SONET/SDH or Comma Detect register bits are
active, an active level on the FPOUTP/N pins will
indicate that either a SONET/SDH framing byte or a
COMMA character is present on the POUTP/N par-
allel data bus, depending on the bus width. This
output is associated with all parallel data bus con-
figurations except 4-bit Redundant Data mode. The
equivalent pins for the FPOUTxP/N function during
Redundant Data mode are the POUT[8]P/N parallel
data bus pins denoted here as FPOUTUP/N and
also stated in the POUT[X:0]P/N section of the pin
assignments. The associated POCLKxP/N in
Redundant Data mode is POCLKUP/N. If Redun-
dant Data mode is being used the FPOUTLP/N out-
put pins may be left floating as they will be in a
powered down state.
The FPOUTLP/N (or FPOUTUP/N) signal will be ac-
tive for the associated active POCLKxP/N sampling
interval which contains the associated SONET/SDH
or Comma Detect framing word (i.e. 1 or 2 valid PO-
CLKs sampling periods for SONET/SDH 8-bit or 4-
bit modes respectively or 1 valid POCLK sampling
period for a Comma Detect).
0x83h
bits 2-0
N/A
TX Control and Status
TXREFSEL[1]
TXREFSEL[0]
LVCMOS
LVCMOS
I/O
I/O
E12
F11
TX REFCLK Frequency Config. Bit order = [1 0]
0 0 =100 MHz
0 1 = 125 MHz
1 0 = 155.52 MHz
1 1 = 622.08 MHz
This input programs the required incoming REF-
CLK rate to the transmit side of the S4882. The
S4882’s synthesizers will adjust the internal divide
ratios appropriately based on this setting, the pro-
gramed Rate Configuration, and the associated
Bus Width.
When SCI is active this function is controlled by its
associated register bit as shown in the Register
Equivalent column. Additional frequency choices
are available when in SCI mode. This I/O will also
be controlled by another function listed in the
Shared Pin column.
These pins require a Soft (/SOFTRST) or a Hard
Reset (/RST) for a change of state to take affect.
0xC4h
bits 7-4
GPIO[1]
GPIO[0]
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin Description
Reg
Equiv
Shared
Pin
Revision 5.04 Data Sheet 53
S4882 Data Sheet
Pin Assignments and
Descriptions
TXLOCKDET LVCMOS O E9 Transmit CSU Lock Indicator. Active High. When
active, this output indicates that the transmit CSU is
in lock and is generating the expected frequency.
0xDAh
bit 0
N/A
TXPHERR LVCMOS O F8 Transmit FIFO Phase Error Indicator. Active High.
When active, this output indicates that the TX FIFO
pointers are close to each other and may collide
causing a loss of data.
0xF2h
bit 0
N/A
Table 16: S4882 Power and Ground Pin Assignments and Descriptions (1.0 mm Pitch Package)
Pin Name Level I/O Pin # Description
AVDD12TX 1+1.2V J11 K7 K10 L9 Power for TX Analog Side
AVSSTX GND J7 K8 L10 M12 Ground for TX Analog Side
AVDD12RX 1, 2 +1.2V K6 L6 Power for RX Analog Side
AVSSRX GND M4 M6 Ground for RX Analog Side
VDD12 1+1.2V C3 D5 E4 E6 E10 F1 F7 G5 J3 1.2V Power for Digital Logic and
Low Speed I/O
VDD33 +3.3V C10 D3 D7 F4 G9 J6 3.3V Power for Low Speed I/O
VSS GND A1 B7 C12 D4 D6 E3 E5 F5 F6 H5 J8 M1 Ground for 1.2V & 3.3V Digital
Logic and Low Speed I/O
1. See Table 20 and 21 for Power Skew Conditions.
2. AVDD12RX voltage/transient isolation from system +1.2V power is recommended for clean 1GE performance. One
example to provide the necessary isolation is to uses a voltage regulator to provide isolated power to the S4882 +1.2V
power pins. Individual filtering between each of the three +1.2V power nets (AVDD12TX, AVDD12RX and VDD12) is
recommended as well.
Table 15: S4882 Shared or Register Equivalent Pin Assignments and Descriptions (Continued)
Pin Name Level I/O Pin Description
Reg
Equiv
Shared
Pin
54 Data Sheet Revision 5.04
S4882 Data Sheet
Serial Control Interface
Register Map Summary
Serial Control Interface Register Map Summary
Table 17 below contains the register map summary for the S4882. For detailed register descriptions, please
consult the S4882 - Programmer’s Reference Manual: PRM2005. When programming the S4882 device,
care should be take to preserve the default state of all RESERVED register bits.
Register Access Type Definitions
• RW = Read/Write Access
• RO = Read Only Access
• RC = Read Clear Access
• N/A = Access Type Not Applicable
The following are sub definitions for the register access type. These sub definitions are separated by a dash (“-”) from the primary register type listed above. The list
contains the associated reset requirements for changes to the stated register bit to take affect. The reset requirements may either be activated subsequently to each
register that is programmed or the reset may be activated after all of the required registers have been programmed so that the reset acts similarly to a gate enable
for all of the values to take affect at once.
• - G = Denotes that a register SOFT_RSTB or pin /SOFTRST is required for the newly written value to take affect
• - R/G = Denotes that a register RX_SOFT_RSTB, SOFT_RSTB, or a pin /SOFTRST is required for the newly written value to take affect
• - T/G = Denotes that a register TX_SOFT_RSTB, SOFT_RSTB, or a pin /SOFTRST is required for the newly written value to take affect
• blank = no reset required for the newly written value to take affect.
TFreeze_RegMap, 0x00h b0, allows the user to freeze the register map for multi-byte reads so that updates will not over write the multi-byte information.
Table 17: Serial Control Interface Register Map Summary12
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
General Control
0x00h TX_SOFT_
RSTB
RX_SOFT_
RSTB SOFT_RSTB Reserved Reserved TX_PD RX_PD FREEZE_
REGMAP
RW RW RW N/A N/A RW - T/G RW - R/G RW
0x01h Reserved SDLBK PDLBK LCKREF SLLBK PLLBK SLPTIME Reserved
N/A RW - G RW - G RW - G RW - G RW - G RW - G RW - G
0x02h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x03h
SPI_AUTOINC I2C_AUTOINC Reserved Reserved Reserved Reserved REFCLK_PD1 REFCLK_PD0
RW RW N/A N/A N/A N/A RW RW
0x04h GPIO_EN[3:0] GPIO[3:0]
RW RW
RX General Control Including BIST
0x05h RX_MUTEMCK RX_MUTEMCK_
VAL Reserved Reserved Reserved Reserved RX_MCK_FREQ[1:0]
RW RW N/A N/A N/A N/A RW - R/G
0x06h
Reserved Reserved Reserved Reserved Reserved RX_SDPOL
RX_POUT_
MUTEPOCLK_
VAL
RX_POUT_
MUTEPOCLK
N/A N/A N/A N/A N/ARWRWRW
0x07h Reserved Reserved Reserved Reserved RX_POUT_
PARITY_ODD
RX_POUT_
PARITY
RX_POUT_
DECODE RX_POUT_DDR
N/A N/A N/A N/A RW RW RW RW - R/G
Revision 5.04 Data Sheet 55
S4882 Data Sheet
Serial Control Interface
Register Map Summary
0x08h RX_FRAME_
LOFDEF
RX_FRAME_
LOFCLRSEL RX_FRAME_ K28.5ALIGN_ NUM[1:0] RX_FRAME_ K28.5VAL[2:0] RX_FRAME
RW RW RW RW RW
0x09h RX_POUT_SONET_RATE[7:6] Reserved Reserved Reserved Reserved RX_POUT_BUSMODE[1:0]
RW N/A N/A N/A N/A RW - R/G
0x0Ah Reserved Reserved Reserved Reserved RX_POUT_
BITSWAP
RX_POUT_
POLINV
RX_POUT_
MUTE_LOSEN
RX_POUT_
MUTEDATA
N/A N/A N/A N/ARWRWRWRW
0x0Bh Reserved Reserved Reserved Reserved RX_BIST_GEN_
ERRINSERT RX_BIST_PAT_SEL[1:0] RX_BIST_GEN
N/A N/A N/A N/A RW RW RW
0x0Ch
through
0x0Fh
RX_BIST_USRPAT[31:24] - MSB
RX_BIST_USRPAT[23:16]
RX_BIST_USRPAT[15:8
RX_BIST_USRPAT[7:0] - LSB
RW
0x10h Reserved RX_BIST_CHK_CNT_LENGTH[4:0] RX_BIST_CHK_
CLR RX_BIST_CHK
N/A RW RW RW
RX PLL Control
0x11h
through
0x15h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x16h Reserved Reserved RX_PLL_BANDSEL[5:0]
N/A N/A RW - R/G
0x17h RX_RATE_CFG[3:0] RX_PLL_REFCLK_FREQ[3:0]
RW - R/G RW - R/G
0x18h
through
0x20h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
RX LockDet, LOL, LOS, Control
0x21h Reserved Reserved Reserved Reserved Reserved RX_REF_LD_LOL_MARGIN[1:0] Reserved
N/A N/A N/A N/A N/A RW - R/G N/A
0x22h
through
0x23h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x24h RX_SD_
LOSMSK Reserved Reserved Reserved Reserved Reserved RX_EXT_LOL Reserved
RW N/A N/A N/A N/A N/A RW N/A
0x25h Reserved Reserved RX_RLD_LOS_
LOSMSK
RX_PA_LOS_
LOSMSK
RX_TC_LOS_
LOSMSK
RX_EXT_LOS_
LOSMSK RX_EXT_LOS RX_EXT_LOL_
LOLMSK
N/A N/ARWRWRWRWRWRW
0x26h
through
0x28h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
Table 17: Serial Control Interface Register Map Summary12 (Continued)
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
56 Data Sheet Revision 5.04
S4882 Data Sheet
Serial Control Interface
Register Map Summary
0x29h Reserved PLL_Filter_Setting_P[1:0] PLL_Filter_Setting_B[4:0]
N/A RW RW
0x2Ah Reserved Reserved Reserved Reserved Reserved PLL_Filter_Setting_I[2:0]
N/A N/A N/A N/A N/A RW
0x2Bh
through
0x2Eh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x2Fh Reserved Reserved RX_LOCKDET_
POL Reserved Reserved Reserved Reserved Reserved
N/A N/A RW N/A N/A N/A N/A N/A
0x30h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
RX PA (RSSI, LOS, TC, RLD, EQ) Control
0x31h Reserved Reserved Reserved Reserved Reserved RX_PA_
OFFSET Reserved Reserved
N/A N/A N/A N/A N/A RW N/A N/A
0x32h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x33h RX_PA_OFFSET_SVAL[7:0]
RW
0x34h
through
0x35h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x36h
-
RX_PA_LOS_DISTH[7:0]
RW
0x37h RX_PA_LOS_ENTH[7:0]
RW
0x38h
through
0x48h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x49h Reserved Reserved Reserved RX_PLL_SD_ ORDER_SEL RX_PLL_SD_
FRAC_EN
RX_PLL_SD_
DITH_ EN
RX_PLL_SD_
DITH_ SEL
N/A N/A N/A RW RWRWRW
0x4Ah RX_RLD_TH_EXP[3:0] RX_RLD_TH_BASE[3:0]
RW RW
0x4Bh Reserved Reserved Reserved RX_HB_DET_EPOCH_CNT_LENGTH[4:0]
N/A N/A N/A RW
0x4Ch Reserved Reserved Reserved RX_PA_EQ_CNTL[1:0] RX_PA_BW_CNTL[1:0] RX_PLL_
SELREF1
N/A N/A N/A RW RW RW - R/G
0x4Dh Reserved Reserved Reserved Reserved RX_PA_
OFFSET_PD RX_PA_RSSI RX_PA_OFFSET_RANGE[1:0]
N/A N/A N/A N/A RW RW RW
Table 17: Serial Control Interface Register Map Summary12 (Continued)
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Revision 5.04 Data Sheet 57
S4882 Data Sheet
Serial Control Interface
Register Map Summary
0x4Eh
through
0x52h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x53h Reserved Reserved Reserved Reserved Reserved Reserved Reserved LVDS_ACEN
N/A N/A N/A N/A N/A N/A N/A RW
0x54h
through
0x5Fh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
Summary Interrupt Masks
0x60h
through
0x61h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x62h RX_HB_ERR_
INTMSK
RX_RLD_LOS_
INTMSK Reserved RX_PA_LOS_
INTMSK Reserved Reserved Reserved Reserved
RW RW RW RW N/A N/A N/A N/A
0x63h Reserved RX_FRAME_
LOF_INTMSK
RX_FRAME_
OOA_INTMSK
RX_FRAME_
OOF_INTMSK Reserved Reserved Reserved Reserved
N/ARWRWRWN/A N/A N/A N/A
0x64h Reserved Reserved RX_REF_LOL_
INTMSK
TX_REF_LOL_
INTMSK Reserved Reserved Reserved Reserved
N/A N/A RW RW N/A N/A N/A N/A
0x65h
through
0x7Fh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
Interrupt and Status Bits
0x80h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0x81h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A RC RC N/A N/A RO RO
0x82h RX_HB_ERR_
INTB
RX_RLD_LOS_
INTB Reserved RX_PA_LOS_
INTB
RX_HB_ERR_
STA
RX_RLD_LOS_
STA Reserved RX_PA_LOS_
STA
RC RC RC RC RO RO RO RO
0x83h Reserved RX_FRAME_
LOF_INTB
RX_FRAME_
OOA_INTB
RX_FRAME_
OOF_INTB Reserved RX_FRAME_
LOF_STA
RX_FRAME_
OOA_STA
RX_FRAME_
OOF_STA
N/ARCRCRCN/ARORORO
0x84h Reserved Reserved RX_REF_LOL_
INTB
TX_REF_LOL_
INTB Reserved Reserved RX_REF_LOL_
STA
TX_REF_LOL_
STA
N/A N/A RW RC N/A N/A RO RO
0x85h
through
0x90h -
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
RX Additional Alarms and Values
0x91h RX_PA_RSSI_CVAL[7:0]
RC
Table 17: Serial Control Interface Register Map Summary12 (Continued)
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
58 Data Sheet Revision 5.04
S4882 Data Sheet
Serial Control Interface
Register Map Summary
0x92h RX_PA_OFFSET_CVAL[7:0]
RC
0x93h
through
0xA4h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0xA5h Reserved Reserved Reserved RX_LOCKDET_
STA Reserved RX_LRF_LOL_
STA
RX_FFA_LOL_
STA Reserved
N/A N/A N/ARORORORON/A
0xA6h
through
0xB1h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
RX BIST Values
0xB2h RX_BIST_CHK_ERRCNT_BASE[7:0]
RO
0xB3h RX_BIST_CHK_
ERR_STA Reserved Reserved Reserved RX_BIST_CHK_ERRCNT_EXP[3:0]
RO N/A N/A N/A RO
0xB4h
through
0xB8h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
Device ID
0xB9h DEVICE_ID[7:0]
RO
0xBAh DEVICE_REV[7:0]
RO
0xBBh SUM_INTB Reserved Reserved Reserved GPIO_RD[3:0]
RC N/A N/A N/A RO
0xBCh
through
0xBFh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
TX LockDet Control
0xC0h Reserved TX_LOCKDET_
POL Reserved Reserved Reserved Reserved Reserved Reserved
N/A RW N/A N/A N/A N/A N/A N/A
0xC1h
through
0xC2h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0xC3h TX_PLL_SD_DITH_ SEL Reserved TX_PLL_SD_ ORDER_SEL TX_PLL_SD_
FRAC_EN
TX_PLL_SD_
DITH_ EN Reserved
RW N/A RW RW RW N/A
Table 17: Serial Control Interface Register Map Summary12 (Continued)
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Revision 5.04 Data Sheet 59
S4882 Data Sheet
Serial Control Interface
Register Map Summary
TX PLL Control
0xC4h TX_PLL_REFCLK_FREQ[3:0] TX_RATE_CFG[3:0]
RW - T/G RW - T/G
0xC5h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0xC6h Reserved TX_PLL_DIV_RATIO[30:24] - MSB
LSBs in Next Registers (0xC7 - 0xC9h)
N/A RW - T/G
0xC7h
through
0xC9h
MSB in Previous Register (0xC6)
TX_PLL_DIV_RATIO[23:16]
TX_PLL_DIV_RATIO[15:8]
TX_PLL_DIV_RATIO[7:0] - LSB
RW - T/G
0xCAh Reserved Reserved TX_PLL_BANDSEL[5:0]
N/A N/A RW - T/G
0xCBh
through
0xD2h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0xD3h TX_PLL_
SELREF1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
RW - T/G N/A N/A N/A N/A N/A N/A N/A
0xD4h
through
0xD9h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
0xDAh Reserved Reserved Reserved Reserved Reserved Reserved Reserved TX_LOCKDET_
STA
N/A N/A N/A N/A N/A N/A N/A RO
0xDBh
through
0xDFh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
TX General Control
0xE0h
TXMCK_PD Reserved Reserved Reserved TXMCK_FREQ[1:0]
TX_
MUTETXMCK_
VAL
Reserved
RW N/A N/A N/A RW RW N/A
0xE1h
Reserved Reserved Reserved Reserved Reserved TX_PIN_
MUTEPCLK
TX_PIN_
MUTEPCLK_
VAL
TX_
MUTETXMCK
N/A N/A N/A N/A N/ARWRWRW
0xE2h Reserved Reserved Reserved Reserved Reserved TX_PIN_DDR TX_PIN_BUSMODE[1:0]
N/A N/A N/A N/A N/A RW - T/G RW - T/G
0xE3h
Reserved Reserved Reserved Reserved Reserved TX_PIN_PHINIT
TX_PIN_
PHINIT_AT_
PHERR
TX_PIN_
PHINIT_AT_TX_
LOCKDET
N/A N/A N/A N/A N/ARWRWRW
Table 17: Serial Control Interface Register Map Summary12 (Continued)
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
60 Data Sheet Revision 5.04
S4882 Data Sheet
Serial Control Interface
Register Map Summary
0xE4h Reserved TX_PIN_
MUTEDATA
TX_PIN_
PARITY_CLR
TX_PIN_
PARITY_ODD
TX_PIN_
PARITY
TX_PIN_
ENCODE
TX_PIN_
POLINV
TX_PIN_
BITSWAP
N/ARWRWRWRWRWRWRW
TX BIST Control
0xE5h Reserved Reserved Reserved Reserved TX_BIST_GEN_
ERRINSERT TX_BIST_PAT_SEL[1:0] TX_BIST_GEN
N/A N/A N/A N/A RW RW RW
0xE6h
through
0xE9h
TX_BIST_USRPAT[31:24] - MSB
TX_BIST_USRPAT[23:16]
TX_BIST_USRPAT[15:8]
TX_BIST_USRPAT[7:0] - LSB
RW
0xEAh Reserved TX_BIST_CHK_CNT_LENGTH[4:0] TX_BIST_CHK_
CLR TX_BIST_CHK
N/A RW RW RW
TX Output Control
0xEBh Reserved Reserved Reserved Reserved TX_TSCLK_PD TX_TSCLK_
MUTE
TX_TSCLK_
MUTE_VAL
TX_TSCLK_
SLEW
N/A N/A N/A N/ARWRWRWRW
0xECh Reserved Reserved Reserved Reserved Reserved Reserved Reserved TX_TSD_
SWING
N/A N/A N/A N/A N/A N/A N/A RW
0xEDh Reserved Reserved Reserved TX_TSD_SLEW TX_TSD_DEEMPH_LEVEL_SEL[3:0]
N/A N/A N/A RW RW
0xEEh TX_TSD_MUTE
_LOS_ SEL_VAL
TX_TSD_MUTE
_LOS_ SEL Reserved Reserved TX_TSD_
DEEMPH TX_TSD_STATE[2:0]
RW RW N/A N/A RW RW
0xEFh
through
0xF1h
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
Additional TX Alarms and Values
0xF2h
Reserved Reserved Reserved Reserved Reserved Reserved
TX_PIN_
PARITY_ERR_
STA
TX_PIN_
PHERR_STA
N/A N/A N/A N/A N/A N/A RO RO
Table 17: Serial Control Interface Register Map Summary12 (Continued)
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Revision 5.04 Data Sheet 61
S4882 Data Sheet
Serial Control Interface
Register Map Summary
TX BIST VALUES
0xF3h TX_BIST_CHK_ERRCNT_BASE[7:0]
RO
0xF4h TX_BIST_CHK_
ERR_STA Reserved Reserved Reserved TX_BIST_CHK_ERRCNT_EXP[3:0]
RO N/A N/A N/A RO
0xF5h
through
0xFFh
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
N/A N/A N/A N/A N/A N/A N/A N/A
1. The reserved bits are for factory use only. The reserved bit values should not be changed from the factory default. Changing the default bit value from the factory default will affect device performance. The
default value of the reserved bits may change depending on device operation.
2. All Bit Numbers are in binary. Address values are in hexadecimal. Default values are listed in binary and may be displayed as a combination of External I/O pins logic levels along with the bit values. The most
significant bit of a register is bit 7, the least significant bit is bit 0.
Table 17: Serial Control Interface Register Map Summary12 (Continued)
Addr
Default Value
after
Hard_RSTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
62 Data Sheet Revision 5.04
S4882 Data Sheet
S4882 Pinout Top View
S4882 Pinout Top View
Figure 18: S4882 Pinout Top View
12345678910 11 12
AVSS POUT2N POUT2P POUT4P POUT4N POUT6P POUT6N POUT9N POCLKUN PCLKUN FPOUTLN TXMCKP
BPOUT-
PARLN
POUT-
PARLP POUT1P POUT1N POUT5P POUT5N VSS POUT9P POCLKUP PCLKUP FPOUTLP TXMCKN
CPOUT0P POUT0N VDD12 POUT3P POUT3N POUT7P POUT7N POCLKLN PCLKLN VDD33 /INT__
RATECFG3 VSS
DRXMCKP RXMCKN VDD33 VSS VDD12 VSS VDD33 POCLKLP PCLKLP MISO TDO RXLOCK-
DET
EPICLKLP PICLKLN VSS VDD12 VSS VDD12 POUT8P POUT8N TXLOCK-
DET VDD12 LOS GPIO1__
TXREFSEL1
FVDD12 PICLKUP PICLKUN VDD33 VSS VSS VDD12 TXPHERR
GPIO2__
RXREFSEL
0
GPIO3_
RXREFSEL
1
GPIO0__
TXREFSEL0 /SOFTRST
GPIN7P PIN7N PIN9P PIN9N VDD12 TCK TDI TMS VDD33 /SS__ /CE__
MODECFG0 /RST
HPIN6P PIN6N PIN8P PIN8N VSS ADDR0__
RATECFG0 MOSI BUSMODE0 BUSMODE1 SCK ADDR1__
RATECFG1 SCI
JPIN4P PIN4N VDD12 PIN5P PIN5N VDD33 AVSSTX VSS DDR ADDR2__
RATECFG2 AVDD12TX TESTEN
KPIN2N PIN2P PIN3P PIN3N RSDC AVDD12RX AVDD12TX AVSSTX SD AVDD12TX SDA__
MODECFG1 REFCLK0P
LPIN1P PIN1N PIN0P PIN0N RSDN AVDD12RX TSCLKN TSDN AVDD12TX AVSSTX SCL__
MODECFG2 REFCLK0N
MVSS PINPARLP PINPARLN AVSSRX RSDP AVSSRX TSCLKP TSDP ATEST REFCLK1N REFCLK1P AVSSTX
Revision 5.04 Data Sheet 63
S4882 Data Sheet
S4882 – 144 PBGA Package
Mechanical Drawings
S4882 – 144 PBGA Package Mechanical Drawings
Figure 19: S4882 – 1.0 mm Ball Pitch, 144 PBGA Package Mechanical Drawing
PACKAGE MATERIAL NOTE:
Standard Package: 1.0 mm Ball Composition - 63/37 Sn/Pb
Green / RoHS Compliant Package: 1.0 mm Ball Composition - 96.5/3.0/0.5 Sn/Ag/Cu.
Table 18: 1.0 mm Pitch Package Thermal Management
Device θja θjb θjc
S4882 35.9°C/Watt w/o airflow 21.0°C/Watt 10.6°C/Watt
64 Data Sheet Revision 5.04
S4882 Data Sheet
S4882 – 144 PBGA Package
Marking Drawing
S4882 – 144 PBGA Package Marking Drawing
Figure 20: S4882 – 144 PBGA Package Marking Drawing
NOTES ( Unless Otherwise Specified ):
Dot Represents PIN 1 (A01) Designator
S4882 VVVVV
YYWW
JJJJJJJJ
CCCCCC
LEGEND (in row order - including symbols ):
ROW #1: AMCC Logo
AMCC Device Part Number , VVVVV : Listed options. See ordering Information .
Mask Protection Symbol
: Assembly Year Code
WW : Assembly Week Code
ZZZZZZ : AMCC 6 Digit Lot Code
ESD Symbol
CCCCCC : Assembly Location
M
1
1
e1 RoHS Lead Free Compliant Symbol (per JEDEC : JESD 97). When present, this signifies a lead free package.
ROW #2:
ROW #3:
ROW #4:
ROW #6:
ROW #7:
M
e1
YY
JJJJJJJJ: Sub Contractor Lot CodeROW #5:
ZZZZZZ
Revision 5.04 Data Sheet 65
S4882 Data Sheet
Performance Specifications
Performance Specifications
Table 19: Performance Specifications
Parameter Min Typ Max Units Conditions
CSU and CRU VCO Specifications
Output Clock Rate (TSCLKP/N) 10 4250 MHz
Frequency difference at which the RX or
TX PLL goes out of lock (Associated
REFCLK is compared to the divided
down VCO clock). The associated RX or
TX LOCKDET is set inactive when PLL
goes out of lock.
350 475 600 ppm
Previously In Lock.
Default values listed
from yy_REF_LD_LOL_MARGIN[1:0] = 0 0
in registers 0x21h & 0xC0h where yy is RX
or TX. Alternate values may be pro-
grammed while in SCI mode.
Frequency difference at which the RX or
TX PLL goes into lock (Associated REF-
CLK compared to the divided down VCO
clock). The associated RX or TX LOCK-
DET is set active 0.5ms after PLL goes
into lock.
220 300 330 ppm
Previously Out of Lock.
Default values listed
from yy_REF_LD_LOL_MARGIN[1:0] = 0 0
in registers 0x21h & 0xC0h where yy is RX
or TX. Alternate values may be pro-
grammed while in SCI mode.
Manual Acquisition (Set VCO range)
CDR Frequency & Phase Acquisition
Lock Time.
750 µsFast Acquisition (RX_FAST_LOCK)
feature is active.
Wait Time Between Back to Back Input
Data Rate Changes
800 ms Data Rate Change Applied as a Step Func-
tion Change in Frequency, not a Ramp.
LCID Consecutive Identical Digit 128 bits
SONET / SDH Jitter Specifications
STS-3/12: STM-1/4
Jitter Tolerance 0.4 UI Sinusoidal input jitter.
STS-48: STM-16
Jitter Tolerance 0.3 UI Sinusoidal input jitter.
STS-3/12/48: STM-1/4/16
Jitter Transfer Peaking 0.1 dB
STS-48/STM-16: Pole at 2 MHz
STS-12/STM-4: Pole at 500 kHz
STS-3/STM-1: Pole at 130 kHz
Jitter Generation (CSU)
SONET
TSCLKP/N
0.005 UI
(rms)
155.52 MHz
or
622.08 MHz
REFCLK
In Lock
Jitter added to the REFCLK
input jitter.
In this measured band-
width:
12 kHz -> 1.3 MHz (OC-3)
12 kHz -> 5 MHz (OC-12)
12 kHz -> 20 MHz (OC-48)
Note: If fraction frequency
REFCLK is used vs. the
data rate then the Jitter
Generation number will be
higher.
66 Data Sheet Revision 5.04
S4882 Data Sheet
Performance Specifications
Jitter Generation (CSU)
SONET
TSCLKP/N
0.050 UI
(p-p)
155.52 MHz
or
622.08 MHz
REFCLK
In Lock
Jitter added to the REFCLK
input jitter.
In this measured band-
width:
65 kHz -> 1.3 MHz (STM-1)
250 kHz -> 5 MHz (STM-4)
1 MHz -> 20 MHz (STM-16)
Note: If fraction frequency
REFCLK is used vs. the
data rate then the Jitter
Generation number will be
higher.
P-P value may vary with dif-
ferent equipment and
setup.
Jitter Generation (CDR)
TSCLKP/N
NOTE: SLPTime Mode Active
0.009 UI
(rms)
STS-48 / STM-16
SLPTIME Mode with CRU locked to RSDP/
N Except with Frequency Hold Measure-
ment.
PRBS 231-1 Pattern
SONET Pattern
PRBS 231-1 w/Freq Hold
In this measured bandwidth:
12 kHz -> 1.3 MHz (OC-3)
12 kHz -> 5 MHz (OC-12)
12 kHz -> 20 MHz (OC-48)
Fiber Channel (Total Jitter)
Fiber Channel (Deterministic Jitter)
TSCLKP/N
CSU
0.23
0.12
UI (p-p) 106.25 MHz
REFCLK
In Lock
Jitter added to the REFCLK
input jitter.
Fiber Channel (Total Jitter)
Fiber Channel (Deterministic Jitter)
TSCLKP/N
CDR (Loop Mode)
0.23
0.18
UI (p-p) 106.25 MHz
REFCLK
In Lock
Jitter added to the data
input jitter.
GE (Total Jitter)
GE (Deterministic Jitter)
TSCLKP/N
CSU and CDR
0.24
0.10
UI (p-p))125 MHz
REFCLK
In Lock
Jitter added to the REFCLK
input jitter.
Other Jitter Specifications
SMPTE 292
Jitter Tolerance
1.000 UI f<20 kHz
-20dB/
Dec slope: 20 kHz < f < 100 kHz
0.200 100 kHz < f
Table 19: Performance Specifications (Continued)
Parameter Min Typ Max Units Conditions
Revision 5.04 Data Sheet 67
S4882 Data Sheet
Performance Specifications
1GE
Jitter Tolerance
0.462 UI Deterministic Jitter
0.749 UI Total Jit ter
4GFC
Jitter Tolerance
0.410 UI Deterministic Jitter
0.710 UI Total Jit ter
0.100 UI Sinusoidal Input Jitter
2.529 to 5 MHz
SMPTE 292
Jitter Transfer 0.2 dB at 10 kHz. Pole 1MHz
High-Speed Input (RSD) Specifications
Input Sensitivity on RSD 12.5 1000 mV STS-48 / STM-16 (2.48832 Gbps)
OTU-1 (2.667 Gbps)
Measured SE while driven Diff with:
231-1 PRBS data pattern at 10-12 BER
25 1000 mV 4x Fibre Channel (4.25 Gbps)
Measured SE while driven Diff with:
231-1 PRBS data pattern at 10-12 BER
RX Post Amp Specifications
S11 Reflection Coefficient
-20
-9
-7
-5
dB
60 KHz to 10 MHz
100 KHz to 2.7 GHz
5 GHz
7 GHz
DC Offset Range -30 +30 mV Resolution: 0.5 mV
RX LOS Specifications
RX LOS Assert and Deassert Times 160 µs
LOS Differential Peak to Peak Voltage
5128 mV Measured Differentially. Assert
10 128 mV Measured Differentially. Deassert.
RX Framing Specifications
First Frame Symbol Acquisition 50 bytes 10 MHz Byte count measured from
RX_FRAME active until the
first recognized framing
symbol.
100 bytes 155.52 MHz
250 bytes 622.08 MHz
425 bytes 1.25 GHz
800 bytes 2.488 GHz
1325 bytes 4.25 GHz
Table 19: Performance Specifications (Continued)
Parameter Min Typ Max Units Conditions
68 Data Sheet Revision 5.04
S4882 Data Sheet
Performance Specifications
Figure 21: S4882 REFCLK Phase Noise Limits
Note: The chart above shows the phase noise limit for a selected Reference Clock (REFCLK) input, specific for TSCLKP/N. In order to meet the
SONET spec, the individual REFCLK spec needs to be below the indicated curves.
Reference Clock Requirements
Reference Clock
Frequency Tolerance
-100 +100 ppm Required ± 20 ppm for
TSCLK to meet SONET
output frequency specifica-
tion
Reference Clock
Input Duty Cycle
45 55 % of
UI
Reference Clock Rise & Fall Times 0.32 ns 622.08 MHz
REFCLK 20% to 80% of amplitude
1.5 ns 155.52 MHz
REFCLK 20% to 80% of amplitude
2ns 125 MHz
REFCLK 20% to 80% of amplitude
2.5 ns 100 MHz
REFCLK 20% to 80% of amplitude
Table 19: Performance Specifications (Continued)
Parameter Min Typ Max Units Conditions
-160
-140
-120
-100
-80
-60
100 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000
Frequency (Hz)
Phase Noise (dBc/Hz)
155.52 MHz
100 MHz
622.08 MHz
Revision 5.04 Data Sheet 69
S4882 Data Sheet
Electrical Specifications
Electrical Specifications
Electrostatic Discharge (ESD) Sensitivity Rating - Human Body Model (HBM):
The S4882 is rated to the following ESD voltages based upon JEDEC standard: JESD22-A114-B
1. CLASS 2 - All pins are rated at or above 2000 volts.
Adherence to standards for ESD protection should be taken during the handling of the devices to ensure that the devices are not damaged. The
standards to be used are defined in ANSI standard ANSI/ESD S20.20-1999, “Protection of Electrical and Electronic Parts, Assemblies and
Equipment.” Contact your local FAE or sales representative for applicable ESD application notes.
Table 20: Absolute Maximum Ratings
The following are the absolute maximum stress ratings for the S4882 device. Stresses beyond those listed may cause permanent damage to
the device. Absolute maximum ratings are stress ratings only, and operation of the device at the maximums stated, or any other conditions
beyond those indicated in the “Recommended Operating Conditions” of the document, are not inferred. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Parameter Min Typ Max Units Conditions
Storage Temperature -55 150 °C
Voltage on AVDD12RX, AVDD12TX, VDD12 with
Respect to GND
-0.2 1.5 V
1.2V Skew Time Duration; when Voltage Differen-
tial between AVDD12RX, AVDD12TX, or VDD12 is
>0.5V
10 ms Only Allowed at Initial Power-Up
and Complete Power-Down
Events.
Measured between the three
listed 1.2V supplies.
Voltage on VDD33 with Respect to GND -0.2 3.56 V
CML Input Voltage -0.5 VDD12
+0.2 VCML input voltage
LVCMOS Control Input Voltage -0.5 VDD33
+0.2 VLVCMOS control input voltage
LVDS Input Voltage -0.5 VDD33
+0.2 VLVDS input voltage
CML Output Current per Pin 8 mA CML output current per pin
CML Input Current per Pin 8 mA CML input current per pin
LVCMOS Output Current per Pin 2 mA LVCMOS output current per pin
LVCMOS Input Current per Pin 1 mA LVCMOS input current per pin
LVDS Output Current per Pin 4 mA LVDS output current per pin
LVDS Input Current per Pin 6.5 mA LVDS input current per pin
70 Data Sheet Revision 5.04
S4882 Data Sheet
Electrical Specifications
Table 21: Recommended Operating Conditions
The device will meet all electrical specifications at a junction temperature under bias of 125°C but part lifetime and
reliability may be reduced. It is recommended that prudent thermal management techniques are used to maximize
device lifetime.
Parameter Min Typ Max Units Conditions
Ambient Temperature Under Bias -40 85 °C
Junction Temperature Under Bias 125 °C
Voltage on VDD12, AVDD12TX and
AVDD12RX with Respect to GND
1.14 1.2 1.26 V
1.2V Skew Time Duration; when Voltage
Differential between AVDD12RX,
AVDD12TX, or VDD12 is >0.5V
50 us Only Allowed at Initial
Power-Up and Complete
Power-Down Events.
Measured between the
three listed 1.2V supplies.
Voltage on VDD33 with Respect to GND 3.135 3.3 3.465 V
Supply Current on AVDD12RX 1,
AVDD12TX
350 400 mA
Supply Current on VDD12 150 190 mA
Supply Current on VDD33 80 90 mA
Power Dissipation with:
Base LIne: All power downs disabled
(xxx_PD=0)
860 1055 mW
Power Dissipation with:
RX_PA_OFFSET_PD = 1 all others dis-
abled
860 1055 mW
Power Dissipation with:
TSCLK_PD = 1 all others disabled
860 1055 mW
Power Dissipation with
TXMCK_PD = 1 all others disabled
860 1055 mW
Power Dissipation with:
REFCLKx_PD = 1 all others disabled
860 1055 mW
Power Dissipation with:
RX_PD = 1 all others disabled
660 750 mW
Power Dissipation with:
TX_PD = 1 all others disabled
570 800 mW
Power Supply Noise Tolerance for
AVDD12RX, AVDD12TX
6 kHz – 2 MHz
40 mVp-p
Power Supply Noise Tolerance for VDD12
6 kHz – 2 MHz
50 mVp-p
Revision 5.04 Data Sheet 71
S4882 Data Sheet
Electrical Specifications
Note: Power consumptions are specified with the 20 pF load.
Noise on the power supply within the PLL bandwidth impacts the Jitter Generation performance.
Power Supply Noise Tolerance for VDD33
6 kHz – 2 MHz
50 mVp-p
1. The AVDDRX power pins require input power isolation for 1GE reliable operation. This isolation is best provided with a power supply regulator to
minimize noise from other devices.
Table 21: Recommended Operating Conditions
The device will meet all electrical specifications at a junction temperature under bias of 125°C but part lifetime and
reliability may be reduced. It is recommended that prudent thermal management techniques are used to maximize
device lifetime.
Parameter Min Typ Max Units Conditions
72 Data Sheet Revision 5.04
S4882 Data Sheet
Electrical Specifications
Table 22: 3.3 V LVCMOS Input/Output Characteristics1
Parameter Description Min Typ Max Units Conditions
VIH Input High Voltage 2.00 VDD33 V
VIL Input Low Voltage 0.0 0.8 V
VSESWING Input Single-Ended Swing VDD33
- 0.8 VDD33 V
IIH Input High Current - 20 70 µA VIN = 0.4V
IIL LVCMOS Input Low Current - 70 30 µAVIN = VDD33 - 0.4
CIN LVCMOS Input Capacitance 3.5 pF
VOH LVCMOS Output High Voltage 2.40 VDD33 V
VOL LVCMOS Output Low Voltage 00.40 V
tRISE tFALL LVCMOS Rise / Fall Times 40 ns 20 to 80%
FrequencyMAX LVCMOS Maximum Toggling
Rate 10 MHz
Rpull_up
Rpull_down
Pull up or Pull down
Input Resistor
14 41 kΩApplies to pull up or
pull down resistor as
listed in Table 15
and Table 16. Guar-
anteed by design.
1. I2C LVCMOS Values Located in Table 27
Table 23: High-Speed CML Output Characteristics: TSD, TSCLK
Parameter Description Min Typ Max Units Conditions
VOH
(Data/Clock)
CML Output High Voltage VDD12
- 0.70
VDD12 VFull Swing (default).
TX_TSD_SWING = 0
De-Emphasis = 0000
VOL
(Data/Clock)
CML Output Low Voltage VDD12
- 1.04
VDD12
- 0.66
VFull Swing (default).
TX_TSD_SWING = 0
De-Emphasis = 0000
VOUTDIFF
(Data)
CML Serial Output Differen-
tial Voltage Swing 800 1600 mV
Full Swing (default).
TX_TSD_SWING = 0
100 Ω line to line.
De-Emphasis = 0000
VOUTSINGLE
(Data)
CML Serial Output Single-
Ended Voltage Swing 400 800 mV
Full Swing (default).
TX_TSD_SWING = 0
100 Ω line to line.
De-Emphasis = 0000
Revision 5.04 Data Sheet 73
S4882 Data Sheet
Electrical Specifications
VOUTDIFF
(Clock)
CML Serial Output Differen-
tial Voltage Swing 640 1600 mV
Full Swing (default).
TX_TSD_SWING = 0
100 Ω line to line.
De-Emphasis = 0000
VOUTSINGLE
(Clock)
CML Serial Output Single-
Ended Voltage Swing 320 800 mV
Full Swing (default).
TX_TSD_SWING = 0
100 Ω line to line.
De-Emphasis = 0000
VOCM Output Common Mode Volt-
age 270 930 mV Full Swing (default).
De-Emphasis = 0000
VOH
(Data)
CML Output High Voltage VDD12
- 0.66
VDD12
- 0.26
VReduced Swing.
TX_TSD_SWING = 1
De-Emphasis = 1111
VOL
(Data)
CML Output Low Voltage VDD12
- 0.84
VDD12
- 0.54
VReduced Swing.
TX_TSD_SWING = 1
De-Emphasis = 1111
VOUTDIFF
(Data)
CML Serial Output Differen-
tial Voltage Swing 380 800 mV
Reduced Swing.
TX_TSD_SWING = 1
100 Ω line to line.
De-Emphasis = 1111
VOUTSINGLE
(Data)
CML Serial Output Single-
Ended Voltage Swing 190 400 mV
Reduced Swing.
TX_TSD_SWING = 1
100 Ω line to line.
De-Emphasis = 1111
VOCM Output Common Mode Volt-
age 390 860 mV Reduced Swing.
De-Emphasis = 1111
RDIFF Differential Output Resis-
tance 80 100 120 Ω
Table 23: High-Speed CML Output Characteristics: TSD, TSCLK (Continued)
Parameter Description Min Typ Max Units Conditions
74 Data Sheet Revision 5.04
S4882 Data Sheet
Electrical Specifications
Table 24: High-Speed CML Input Characteristics: RSD
Parameter Description Min Typ Max Units Conditions
VIH CML Input High Voltage VDD12
- 0.35
VDD12 V
VIL CML Input Low Voltage VDD12
- 1.0
VDD12
- 0.27
V
VINDIFF Differential Input Voltage
Swing 25 2000 mV 231-1 PRBS data pattern,
10-12 BER, SONET/OTU-1
VINSINGLE Single-Ended Input Voltage
Swing 12.5 1000 mV
231-1 PRBS data pattern,
10-12 BER, SONET/OTU-1
Driven differentially
VINBIAS Input Bias Range (AC Cou-
pled)
VDD12
- 0.6
VDD12
- 0.2 V
VICM Input Common Mode Volt-
age (DC coupled) 500 1125 mV
RDIFF Differential Input Resistance 80 100 120 Ω
Table 25: LVDS Input/Output Characteristics POUT[X:0], POCLKx, RXMCK, POUTPARL, FPOUTL,
PIN[X:0], PCLKx, PICLKx, TXMCK, PINPARL
Parameter Description Min Typ Max Units Conditions
VIH LVDS Input High Voltage 960 1575 mV
VIL LVDS Input Low Voltage 825 1420 mV
VIC Input Common Mode Voltage 875 1525 mV
VIS LVDS Serial Input Single-Ended
Voltage Swing
100 650 mV
VID LVDS Serial Input Differential
Voltage Swing
200 1300 mV
RDiff Differential Input Impedance 80 100 120 Ω
VOH LVDS Output High Voltage 1160 1525 mV
VOL LVDS Output Low Voltage 900 1200 mV
VOS LVDS Serial Output Single-
Ended Voltage Swing
250 450 mV Output swing is measured
at DC
VOD LVDS Serial Output Differential
Voltage Swing
500 900 mV Output swing is measured
at DC
ROI LVDS Output Impedance 40 140 Ω
Revision 5.04 Data Sheet 75
S4882 Data Sheet
Electrical Specifications
Table 26: REFCLK CML Input Characteristics: REFCLK0, REFCLK1
Parameter Description Min Typ Max Units Conditions
VIH CML Input High Voltage VDD12
- 0.42
VDD12 V
VIL CML Input Low Voltage VDD12
- 0.95
VDD12
- 0.27
V
VINDIFF Differential Input Voltage Swing 300 1800 mV
VINSINGLE Single-Ended Input Voltage
Swing 150 900 mV
VINBIAS Input Bias Range (AC Coupled) VDD12
- 0.5
VDD12
- 0.2 V
RDIFF Differential Input Resistance 80 100 120 Ω
76 Data Sheet Revision 5.04
S4882 Data Sheet
Electrical Specifications
Figure 22: I2C BUS® Timing Diagram
Table 27: I2C BUS® LVCMOS Input/Output & Timing Characteristics
Parameter Description Min Typ Max Units Conditions
I2C LVCMOS Input/Output Characteristics
VIH Input High Voltage VDD33 * 0.7 VDD33 + 0.5 V
VIL Input Low Voltage -0.3 VDD33 * 0.14 V
IIN Input Leakage Current 24 µA VIN =(0.1 * VDD33)
to (0.9 * VDD33)
VOH Output High Voltage VDD33 -0.5 V VDD33 + 0.3 V V
VOL Output Low Voltage 00.4 V IOL = 3 mA
I2C Timing Characteristics
tLOW Clock pulse width low 1.3 µsSerial Clock Operat-
ing Frequency:
400kHz Max
tHIGH Clock pulse width high 0.6 µs
tHD,STA START Hold Time 0.6 µs
tSU,STA START Set-up Time 0.6 µs
tHD,DAT Data In Hold Time 0µs
tSU,DAT Data In Set-up TIme 0.3 µs
tSU,STO STOP Set-up TIme 0.6 µs
tRInput Rise Time (400 kHz) 300 ns From (VIL,MAX-0.15)
to (VIH,MIN+0.15)
tFInput Fall Time (400 kHz) 300 ns From (VIH,MIN+0.15)
to (VIL,MAX-0.15)
SCL
tLOW
tHIGH tRtF
tF
tSU,DAT
tHD,DAT
SDA
START ReSTART STOP
tSU,STO
tHD,STA
tSU,STA
tR
Revision 5.04 Data Sheet 77
S4882 Data Sheet
Electrical Specifications
Figure 23: SPI BUS Timing Diagram
Table 28: SPI BUS Timing Characteristics
Symbol Parameter Min. Max. Units Test Conditions
fSCK Clock Frequency 10 MHz CL = 10 pF
Input and output DC voltage levels:
See 3.3 V LVCMOS spec
fSCK = 10 MHz Max
If 100 MHz REFCLK is used then tWH,
tWL and tV specification’s values will be
increased by 20%.
tWH SCK High Time 40 ns
tWL SCK Low Time 40 ns
tSU Data Setup Time 20 ns
tHData Hold Time 20 ns
tVOutput Valid from Clock Low 40 ns
tHO Output Hold Time 0ns
tDIS Output Disable Time 75 ns
tSSS /SS Setup Time 100 ns
tSSH /SS Hold TIme 100 ns
tSS /SS Width 100 ns
tRI & tFA Input rise and fall times 10 ns
/SS
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
HI-Z
VALID IN
tSU
tSSS
tWH tWL
tSSH
tRI
tFA tHO tDIS
HI-Z
tSS
tH
tV
SCK
MOSI
MISO
fSCK
78 Data Sheet Revision 5.04
S4882 Data Sheet
Electrical Specifications
Figure 24: RX Data Path Timing Diagram
Table 29: RX Data Path Timing Characteristics
POUT[X:0], POUTPARL, POCLKx, RXMCK, REFCLKx
Parameter Description Min Max Units
Setup POUT[X:0] & POUTPARL Setup time wrt. POCLKx rising
edge (or rising/falling edge in DDR Mode).
Maximum Frequency Rate
Timing will scale equivalently for other frequencies.
For any other frequencies use this calculation:
Setup = (Clock Period/2) - 125 ps
475 ps
Hold POUT[X:0] & POUTPARL Hold time wrt. POCLKx rising
edge (or rising/falling edge in DDR Mode).
Maximum Frequency Rate
Timing will scale equivalently for other frequencies.
For any other frequencies use this calculation:
Hold = (Clock Period/2) - 125 ps
475 ps
Delay POUT[X:0] delay wrt. POCLKx rising edge.
Maximum Frequency Rate, 3.2 Gbps, 4-bit
[1/(3.2 GHz/4-bit)] - 475 ps] = 775 ps
Timing will scale equivalently for other frequencies.
For any other frequencies use this calculation:
Delay max = (Clock Period/2) + 225 ps
Delay min = (Clock Period/2) - 125 ps
475 775 ps
Duty Cycle Duty Cycle of POCLKx, RXMCK 45 55 %
tRISE, tFALL LVDS Rise/Fall time (20 to 80%) 70 270 ps
Frequency LVDS Maximum Toggling Rate 400
800
MHz
Mbps
Bit Latency Number of clock cycles after RSD appears at POUT[X] 150 UI
Delay min
Data
POUT[X:0] , POUTPARL
Delay max
setup hold setup hold
Clock
POCLKx, RXMCK
80%
trise
20%
Clock
POCLKx,
Double Data Rate (DDR)
Note: There is no clock to clock timing relationship.
Revision 5.04 Data Sheet 79
S4882 Data Sheet
Electrical Specifications
Figure 25: TX Data Path Timing Diagram
Table 30: TX Data Path Timing Characteristics
PCLKx, TXMCK, PIN[X:0], PINPARL, PICLKx, TSD, TSCLK
Parameter Description Min Max Units
Setup PIN & PINPARL Setup time wrt. PICLKx rising edge (or
rising/falling edge in DDR Mode)
300 ps
Hold PIN & PINPARL Hold time wrt. PICLKx rising edge (or ris-
ing/falling edge in DDR Mode)
300 ps
Duty Cycle Required Duty Cycle for PICLKx 35 65 %
Duty Cycle Duty Cycle of PCLKx, TXMCK 45 55 %
tRISE, tFALL LVDS Rise/Fall time (20 to 80%) of PCLKx, TXMCK 100 250 ps
Setup TSD Setup time wrt. TSCLK rising edge (All rates)
TSD Setup time wrt. TSCLK rising edge (4.25 GHz)
80
70
ps
Hold TSD Hold time wrt. TSCLK rising edge (All rates)
TSD Hold time wrt. TSCLK rising edge (4.25 GHz)
80
70
ps
Duty Cycle Duty Cycle of TSCLK 45 55 %
tRISE, tFALL
Data (TSD)
Rise/Fall time (20 to 80%) of TSD, TSCLK with 100 Ohm
load line to line.
55 100 ps
tRISE, tFALL
Clock (TSCLK)
Rise/Fall time (20 to 80%) of TSD, TSCLK with 100 Ohm
load line to line.
30 60 ps
FIFO
Wander
The Maximum Allowable PCLKx-to-PICLKx wander after
the FIFO has centered
2PICLKx
Cycles
Bit Latency Number of clock cycles after PIN[x]P/N appears at
TSDP/N
200 UI
DATA
(PIN[X:0],
PINPARL, TSD*)
setup hold
50%
setup hold
* Double Data Rate specification is not applied for the TSD
CLOCK
(PICLKx, PCLKx)
Double Data Rate (DDR)
CLOCK
( PICLKx, PCLKx,
TXMCK, TSCLK)
50%
duty cycle
20%
80%
tfall
trise
80 Data Sheet Revision 5.04
S4882 Data Sheet
Electrical Specifications
Figure 26: /RST Timing Diagram
Note:
/RST active should extend over at least two xxREFCLK rising edges t>0.
Initial power-on and a loss of REFCLK requires a Hard reset (/RST)
Figure 27: Differential Voltage Measurement
Note: WRT = With Respect To
Table 31: /RST Timing Characteristics
Parameter Description Min Max Units Conditions
/RST Minimum Rest Value
= (1/100 MHz)*2 + 3 ns= 23 ns
23 ns Measured from the midpoint of the signal.
(100 MHz xxREFCLKP)
REFCLKxP
/RST
t
t > 0
V(+) wrt to GND
0 V
VSINGLE
V
Diff = 2 X VSINGLE
V(–) wrt to GND
V(+) wrt to V(-)
0 V
Revision 5.04 Data Sheet 81
S4882 Data Sheet
Electrical Specifications
Figure 28: LVCMOS Input/Output Buffers
Figure 29: LVDS Output Buffers
GND
VDD
I/P To Core
GND
VDD
O/P
A
Input Buffer Output Buffer
Output Buffer
100 Ω
Core
50 Ω
50 Ω
50 Ω50 Ω
+
+Core
V1
V2
Zo = 50 Ω
Zo = 50 Ω
82 Data Sheet Revision 5.04
S4882 Data Sheet
Recommended Terminations
Recommended Terminations
Figure 30: Differential CML Output to Differential CML Input DC Coupled Termination
Figure 31: Differential CML Output to Differential CML Input AC Termination
Note: When AC coupling the RSDP/N interface, a broadband capacitor is required. The value of the capacitor can be as low as 850 pF.
+1.2 V
S4882
RSDP/N
CML
CML
Ouput Driver
VDD12
VDD12 = + 1.2 V
Zo = 50 Ω
Zo = 50 Ω
50 Ω
50 Ω
+ 1.2 V,
2.5 V
Zo = 50 Ω
0.01 µF
0.01 µF
Zo = 50 Ω
50 Ω
50 Ω
VDD12 = + 1.2 V
VDD12
S4882
RSDP/N
CML
CML
Ouput Driver
Revision 5.04 Data Sheet 83
S4882 Data Sheet
Recommended Terminations
Figure 32: Differential LVDS Input DC Coupled Termination
Figure 33: Differential LVDS Input AC Coupled Termination
Figure 34: Differential LVDS Driver to LVDS Input Termination
Zo = 50 Ω
Zo = 50 Ω
LVDS
2.5 V or
3.3 V
VDD12
VDD33 = 3.3 V
S4882
PIN[0:X]
PICLK
LVDS
50 Ω
50 Ω
LVDS
Zo = 50 Ω
0.01 µF
0.01 µF
Zo = 50 Ω
1.8 V or 2.5 V
or 3.3 V
S4882
PIN[0:X]
PICLK
LVDS
50 Ω
50 Ω
VDD12
VDD33 = 3.3 V
Zo = 50 Ω
Zo = 50 Ω
S4882
POUT[0:X]
POCLKP/N
LVDS
SERDES
Framer
LVDS
+3.3 V
100 Ω
+ 1.8 V
+2.5 V
+3.3 V
84 Data Sheet Revision 5.04
S4882 Data Sheet
Recommended Terminations
Figure 35: Differential LVDS Output to LVDS Input AC Coupled Termination
Figure 36: Differential CML Output to Differential LVPECL Input AC Termination (Not internal Biased)
Note: When AC coupling the TSDP/N/TSCLKP/N interface, a broadband capacitor is required. The value of the capacitor can be as low as 850 pF.
SERDES
LVDS with Internal
Termination & Biasing
VDD
Zo = 50 Ω
0.01 µF
0.01 µF
Zo = 50 Ω
50 Ω
50 Ω
S4882
POUT[0:X]
POCLKP/N
LVDS
1.8 V or 2.5 V
or 3.3 V
+3.3 V
S4882
TSDP/N
TSCLKP/N
CML
Zo = 50 Ω
0.01 µF
0.01 µF
Zo = 50 Ω
LVPECL Input without
Internal Termination &
Biasing
82 Ω 130 Ω
82 Ω
VDD
VDD - 1.3 V 3.3 V
130 Ω
1.2 V
Revision 5.04 Data Sheet 85
S4882 Data Sheet
Recommended Terminations
Figure 37: 3.3 V Differential CML Oscillator to Reference Clock Input DC Coupled Termination
Figure 38: 2.5 V Differential LVPECL Oscillator to Reference Clock Input AC Coupled Termination
Zo = 50 Ω
Zo = 50 Ω
1.2 V
VDD12
VDD12 = + 1.2 V
50 Ω
50 Ω
S4882
CML
xxREFCLKP/N
OSCILLATOR
CML
S4882
CML
Zo = 50 Ω
0.01 µF
0.01 µF
Zo = 50 Ω
300 Ω
300 Ω
2.5 V VDD12 = + 1.2 V
VDD12
50 Ω
50 Ω
xxREFCLKP/N
OSCILLATOR
LVPECL
86 Data Sheet Revision 5.04
S4882 Data Sheet
Recommended Terminations
Figure 39: LVCMOS Output to LVCMOS Input Termination
Figure 40: S4882 Interface Termination
Zo = 50 Ω
S4882
LVCMOS
Output
3.3 V
LVCMOS
Input
VDD = 3.3 V
S4882
Transceiver
REFCLK
TX
RX
POCLK
POUT Data
Clock
PIN
PICLK
Data
Clock
Framer
Or
FPGA
SFP
RSDP/N
SD
TSDP/N
SFF
Optics
1X9 PCLK Clock
Revision 5.04 Data Sheet 87
S4882 Data Sheet
Document Revision History
Document Revision History
Revision Date Description
5.04 08/19/09 •Table 1, Added note for HDTV, pathological non-compliance.
• Page 16, Updated SD paragraph to include register note.
• Page 16 and 17, Updated paragraphs for Pin mode, Rate Config mode and Manual mode.
• Page 17, Update Bs programming sequence for the Tx.
• Page 22, Updated SLLBK paragraph to provide a note on DDR mode.
• Page 25, Updated Reset paragraph for Soft Reset action.
•Table 5, Added footnote to exclude 3G and 4G operation from Pin Mode.
•Table 5, Updated footnote to add Tx RATECFG sequence.
•Table 14, Updated to include a note for SD.
•Table 16, Footnote added with reference to the Power Skew
•Table 16, Footnote added for AVDD12RX power isolation
•Table 20, Updated table to change min 1.2V and min/max 3.3 volt absolute values.
•Table 20, Updated table to add Power Skew Condition
•Table 21, Updated table to add Power Skew Condition
•Table 21, Footnote added for AVDD12RX power isolation
5.03 06/24/09 • New layout format, no content change
5.02 04/06/09 • Pg 2, Data Sheet phase name replaced with Released and associated bullets updated for
clarity.
5.01 07/23/08 • Production Released
88 Data Sheet Revision 5.04
S4882 Data Sheet
Ordering Information
Ordering Information
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I2C BUS® is a registered trademark of Philips Electronics N.V. Corporation Netherlands
Device Code Product
S4882PBICB
S4882PRICB
S4882 – 10 Mbps - 4.25 Gbps Continuous Rate Transceiver
Standard Package, Industrial Temp
S4882 – 10 Mbps - 4.25 Gbps Continuous Rate Transceiver
Green / RoHS Compliant Package, Industrial Temp
TEMPERATURE RANGE
PACKAGE TYPE
DEVICE NAME
XX IS4882
I: Industrial
PB: 144 PBGA Standard Package
S4882: 10 Mbps - 4.25 Gbps Continuous Rate Transceiver
CB: Revision
REVISION / PACKAGE DETAILS
YY
PR: 144 PBGA Green/RoHS Compliant Package
