PIC18F2458/2553/4458/4553 PIC18F2458/2553/4458/4553 Rev. B6 Silicon Errata The PIC18F2458/2553/4458/4553 Rev. B6 parts you have received conform functionally to the Device Data Sheet (DS39887B), except for the anomalies described below. Any Data Sheet Clarification issues related to the PIC18F2458/2553/4458/4553 will be reported in a separate Data Sheet errata. Please check the Microchip web site for any existing issues. Note: The "PIC18F2458/2553/4458/4553 Data Sheet" is supplemented by the "PIC18F2455/2550/4455/4550 Data Sheet" (DS39632). PIC18F2458/2553/4458/4553 features and specifications that are shared with the PIC18F2455/2550/4455/ 4550 devices are documented in the "PIC18F2455/2550/4455/4550 Data Sheet". The following silicon errata apply only to PIC18F2458/2553/4458/4553 devices with these Device/Revision IDs: Part Number Device ID Revision ID PIC18F2458 0010 1010 011 0 0110 PIC18F2553 0010 1010 010 0 0110 PIC18F4458 0010 1010 001 0 0110 PIC18F4553 0010 1010 000 0 0110 1. Module: MSSP In SPI Slave mode with slave select enabled (SSPM<3:0> = 0100), the minimum time between the falling edge of the SS pin and first SCK edge is greater than specified in parameter 70 in Table 28-17 and Table 28-18 of the "PIC18F2455/2550/4455/4550 Data Sheet" (DS39632). The updated specification is shown in bold in Table 1. The minimum time between SS pin low and an SSPBUF write is also 3 TCY. If the falling edge of the SS pin occurs greater than 3 TCY, before the first SCK edge or loading SSPBUF, the peripheral will function correctly. Also, if SSPBUF is written prior to the SS pin going low, the peripheral will function correctly. Work around None. Date Codes that pertain to this issue: All engineering and production devices. The Device IDs (DEVID1 and DEVID2) are located at addresses 3FFFFEh:3FFFFFh in the device's configuration space. They are shown in binary in the format "DEVID2 DEVID1". All of the issues listed here will be addressed in future revisions of the PIC18F2458/2553/4458/4553 silicon. TABLE 1: Param No. 70 EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING) Symbol Characteristic TSSL2SCH, SS to SCK or SCK Input TSSL2SCL (c) 2008 Microchip Technology Inc. Min 3 TCY Max Units Conditions -- ns DS80336D-page 1 PIC18F2458/2553/4458/4553 2. Module: MSSP With MSSP in SPI Master mode, FOSC/64 or Timer2/2 clock rate and CKE = 0, a write collision may occur if SSPBUF is loaded immediately after the transfer is complete. A delay may be required after the MSSP Interrupt Flag bit, SSPIF, is set or the Buffer Full bit, BF, is set and before writing SSPBUF. If the delay is insufficiently short, a write collision may occur as indicated by the WCOL bit being set. Work around Add a software delay of one SCK period after detecting the completed transfer and prior to updating the SSPBUF contents. Verify the WCOL bit is clear after writing SSPBUF. If the WCOL is set, clear the bit in software and rewrite the SSPBUF register. 4. Module: Electrical Characteristics (BOR) Certain operating conditions can move the effective Brown-out Reset (BOR) threshold outside of the range specified in the electrical characteristics of the device data sheet (parameter D005). The BOR threshold has been observed to increase with high device operating frequencies, some table read operations and heavy loading on the USB voltage regulator. When all of these conditions are present, BOR has been observed with VDD 20 percent higher than the VBOR value specified for a given <BORV1:BORV0> setting. The BOR threshold may decrease under other conditions, such as during Sleep, where it may not occur until VDD is 120 mV below the specified minimums. Work around Date Codes that pertain to this issue: None. All engineering and production devices. Date Codes that pertain to this issue: 3. Module: ECCP (PWM Mode) When configured for half-bridge operation with dead band (CCPxCON<7:6> = 10), the PWM output may be corrupted for certain values of the PWM duty cycle. This can occur when these additional criteria are also met: * A non-zero dead-band delay is specified (PDC6:PDC0 > 0) * The duty cycle has a value of 0 through 3, or 4n + 3 (n 1) Work around None. Date Codes that pertain to this issue: All engineering and production devices. All engineering and production devices. 5. Module: MSSP (SPI Slave) If configured in SPI Slave mode, the MSSP may not successfully recognize data packets generated by an external master processor. This applies to all SPI Slave modes (CKE/CKP = 1 or 0), whether or not slave select is enabled (SSPM3:SSPM0 = 010x). Work around Insert a series resistor between the SPI master Serial Data Out (SDO) and the corresponding SPI slave Serial Data In (SDI) input line of the microcontroller. The required value for the resistor varies with the application system's characteristics and the process variations between the microcontrollers. Experimentation encouraged. and thorough testing are Date Codes that pertain to this issue: All engineering and production devices. DS80336D-page 2 (c) 2008 Microchip Technology Inc. PIC18F2458/2553/4458/4553 6. Module: MSSP Work around If the application firmware is expecting to receive valid data - in either SPI slave or Master mode - the firmware must read from the SSPBUF register before writing the next byte to transmit to SSPBUF. If the firmware does not read from SSPBUF, the BF bit (SSPSTAT<0>) can still be set from the previous transaction. If the BF bit is set, the incoming data byte is blocked from transferring from the SSPSR shift register to the SSPBUF register. If the firmware then reads from SSPBUF, the data read will not match the data most recently received on the SDI pin. If the firmware expects to receive valid data, always clear the BF bit by reading from SSPBUF prior to writing to SSPBUF, even when the current data in SSPBUF is not important. Sample workaround code, suitable for all silicon revisions, is given in Example 1 (Assembly language) and Example 2 (C language). Date Codes that pertain to this issue: All engineering and production devices. In the earlier silicon revision (B5), incoming data bytes received on the SDI pin are always transferred from SSPSR to SSPBUF, regardless of the state of the BF bit. EXAMPLE 1: SAMPLE ASSEMBLY CODE FOR TRANSFERRING SPI DATA WriteSPI: BCF PIR1, SSPIF MOVF SSPBUF, w MOVLW 0xA5 MOVWF SSPBUF ;Perform read, even if the data in SSPBUF is not important ;In this example, let's send "0xA5" to the other SPI device. WaitXmitComplete: BTFSS PIR1, SSPIF BRA WaitXmitComplete MOVF SSPBUF, w EXAMPLE 2: ;The data received should be valid. SAMPLE C CODE FOR TRANSFERRING SPI DATA unsigned char WriteSPI(unsigned char ByteToSend) { unsigned char TempVariable; PIR1bits.SSPIF = 0; TempVariable = SSPBUF; SSPBUF = ByteToSend; // Reads from SSPBUF, ensures BF bit is clear before // sending the next byte. while(!PIR1bits.SSPIF); return SSPBUF; // Wait until the transmission is complete. // The data received should be valid. } (c) 2008 Microchip Technology Inc. DS80336D-page 3 PIC18F2458/2553/4458/4553 REVISION HISTORY Rev A Document (8/2007) Initial release of this document. Silicon issues 1-2 (MSSP) and 3 (ECCP - PWM Mode). Rev B Document (3/2008) Added silicon issue 4 Electrical Characteristics (BOR). Rev C Document (4/2008) Added silicon issue 5 (MSSP - SPI Slave). Rev D Document (5/2008) Added silicon issue 6 (MSSP). DS80336D-page 4 (c) 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2008 Microchip Technology Inc. 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