PIC18F4553-I/PT - Microchip Technology

PIC18F2458/2553/4458/4553

The PIC18F2458/2553/4458/4553 Rev. B6 parts you

have received conform functionally to the Device Data

Sheet (DS39887B), except for the anomalies

described below. Any Data Sheet Clarification issues

related to the PIC18F2458/2553/4458/4553 will be

reported in a separate D ata Sheet errat a. Please chec k

the Microchip web site for any existing issues.

The following silicon errata apply only to

PIC18F2458/2553/4458/4553 devices with these

Device/Revision IDs:

All of the issues listed here will be addressed in future

revisions of the PIC18F2458/2553/4458/4553 silicon.

1. Module: MSSP

In SPI Slave mode with slave select enabled

(SSPM<3:0> = 0100), the minimum time between

the falling edge of the SS pin and first SCK edge

is greater than specified in parameter 70

in Table 28-17 and Table 28-18 of the

“PIC18F2455/2550/4455/4550 Data Sheet”

(DS39632). The updated specification is shown in

bold in Table 1.

The minimum time between SS pin low and an

SSPBUF write is also 3 TCY. If the falling edge of

the SS pin occurs greater than 3 TCY, before the

first SCK edge or loading SSPBUF, the peripheral

will function correctly. Also, if SSPBUF is written

prior to the SS pin going low, the peripheral will

function correctly.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

TABLE 1: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING)

Note: The “PIC18F2458/2553/4458/4553 Data

Sheet” is supplemented by the

“PIC18 F2 45 5/2 55 0/ 44 55 /45 50 D ata Shee t”

(DS39632). PIC18F2458/2553/4458/4553

features and specifications that are

shared with the PIC18F2455/2550/4455/

4550 devices are documented in

the “PIC18F2455/2550/4455/4550 Data

Sheet”.

Part Number Device ID Revision ID

PIC18F2458 0010 1010 011 0 0110

PIC18F2553 0010 1010 010 0 0110

PIC18F4458 0010 1010 001 0 0110

PIC18F4553 0010 1010 000 0 0110

The Devic e IDs (DEVID1 an d DEVID2 ) are located at

addresses 3FFFFEh:3FFFFFh in the device’s

configuration space. They are shown in binary in the

format “DEVID2 DEVID1”.

Param

No. Symbol Characteristic Min Max Units Conditions

70 TSSL2SCH,

TSSL2SCLSS ↓ to SCK ↓ or SCK ↑ Input 3TCY —ns

PIC18F2458/2553/4458/4553 Rev. B6 Silicon Errata

PIC18F2458/2553/4458/4553

2. Module: MSSP

With MSSP in SPI Master mode, FOSC/64 or

Timer2/2 clock rate and CKE = 0, a write collis ion

may occur if SSPBUF is loaded immediately after

the transfer is complete. A delay may be required

after the MSSP Interrupt Flag bit, SSPIF, is set or

the Buffer Full bit, BF, is set and before writing

SSPBUF. If the delay is insuf fi cie ntl y short, a write

collision may occur as indicated by the WCOL bit

being set .

Work around

Add a software delay of one SCK period after

detecting the completed transfer and prior to

updating the SSPBUF contents. Verify the WCOL

bit is clear after writing SSPBUF. If the WCOL is

set, clear the bit in software and rewrite the

SSPBUF register.

Date Codes that pertain to this issue:

All engineering and production devices.

3. Module: ECCP (PWM Mode)

When configured for half-bridge operation with

dead band (CCPxCON<7:6> = 10), the PWM

output may be corrupted for certain values of the

PWM duty cycle. This can occur when these

additional criteria are also met:

• A non-zero dead-band delay is specified

(PDC6:PDC0 > 0)

• The duty cycle has a value of 0 through 3, or

4n + 3 (n ≥ 1)

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

4. Module: Electrical Characteristics (BOR)

Certain operating conditions can move the effec-

tive Brown-out Reset (BOR) threshold outside of

the range specifie d in th e ele ctri ca l ch arac teri st ic s

of the device data sheet (parameter D005).

The BOR t hreshold has been observed to increase

with high device op erating frequencies, some t able

read operations and heavy loading on the USB

volt age regul ato r. When all o f these co nd itions a re

present, BOR has been observed with VDD

20 percent higher than the VBOR value specified

for a given <BORV1:BORV0> setting.

The BOR threshold may decrease under other

conditi ons, such as during Sleep , where it may not

occur until VDD is 120 mV below the specified

minimums.

Work around

None.

Date Codes that pertain to this issue:

All engineering and production devices.

5. Module: MSSP (SPI Slave)

If configured in SPI Slave mode, the MSSP may not

successfully recognize data packets generated by an

external master processor. This applies to all SPI

Slave modes (CKE/CKP = 1 or 0), whether or not

slave select is enabled (SSPM3:SSPM0 = 010x).

Work around

Insert a series resistor between the SPI master

Serial Data Out (SDO) and the corresponding SPI

slave Serial Data In (SDI) input line of the

microc ont roll er. The required val ue for the res ist or

varies wit h the applicatio n system’ s characteri stics

and the process variations between the

microcontrollers.

Experimentation and thorough testing are

encouraged.

Date Codes that pertain to this issue:

All engineering and production devices.

PIC18F2458/2553/4458/4553

6. Module: MSSP

If the application firmware is expecting to receive

valid data – in either SPI slave or Master mode –

the firmware must read from the SSPBUF regis ter

before writing the next byte to transmit to SSPBUF.

If the firmware does not read from SSPBUF, the

BF bit (SSP STAT<0>) can s till be se t fr om the p re-

vious transaction. If the BF bit is set, the incoming

data byte is blocked from transferring from the

SSPSR shif t register to the SSPBUF regis ter . If the

firmware then reads from SSPBUF, the data read

will not matc h the data mo st recen tly recei ved on

the SDI pin.

In the earlier silicon revision (B5), incoming data

bytes received on the SDI pin are always trans-

ferred from SSPSR to SSPBUF, regardless of the

state of the BF bit.

Work around

If the firmware expects to receive valid data,

always clear the BF bit by reading from SSPBUF

prior to writing to SSPBUF, even when the current

data in SSPBUF is not important. Sample work-

around code, suitable for all silicon revisions, is

given in Example 1 (Assembly language) and

Example 2 (C language).

Date Codes that pertain to this issue:

All engineering and production devices.

EXAMPLE 1: SAMPLE ASSEMBLY CODE FOR TR ANSFERRING SPI DAT A

EXAMPLE 2: SAMPLE C CODE FOR T R ANSFERRING SPI DAT A

WriteSPI:

BCF PIR1, SSPIF

MOVF SSPBUF, w ;Perform read, even if the data in SSPBUF is not important

MOVLW 0xA5 ;In this example, let’s send “0xA5” to the other SPI device.

MOVWF SSPBUF

WaitXmitComplete:

BTFSS PIR1, SSPIF

BRA WaitXmitComplete

MOVF SSPBUF, w ;The data received should be valid.

unsigned char WriteSPI(unsigned char ByteToSend)

{unsigned char TempVariable;

PIR1bits.SSPIF = 0;

TempVariable = SSPBUF; // Reads from SSPBUF, ensures BF bit is clear before

SSPBUF = ByteToSend; // sending the next byte.

while(!PIR1bits.SSPIF); // Wait until the transmission is complete.

return SSPBUF; // The data received should be valid.

}

PIC18F2458/2553/4458/4553

REVISION HISTORY

Rev A Document (8/2007)

Initial relea se of this do cument. Silicon i ssues 1-2 (MSSP)

and 3 (ECCP – PWM Mode).

Rev B Document (3/2008)

Added silicon issue 4 Electrical Characteristics (BOR).

Rev C Document (4/2008)

Added si licon iss ue 5 ( MSSP – SPI S lave) .

Rev D Document (5/2008)

Added sili con i ss ue 6 ( MSSP) .

Information contained in this publication regarding device

applications and t he lik e is provid ed only f or yo ur con ve nience

and may be supe rseded by u pdates. I t is y o u r r es ponsibility to

ensure that your application meets with your specifications.

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Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

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products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

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