ADP2323-EVALZ - Analog Devices

Dual 3 A, 20 V Synchronous Step-Down

Regulator with Integrated High-Side MOSFET

Data Sheet

ADP2323

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Input voltage: 4.5 V to 20 V

±1% output accuracy

Integrated 90 mΩ typical high-side MOSFET

Flexible output configuration

Dual output: 3 A/3 A

Parallel single output: 6 A

Programmable switching frequency: 250 kHz to 1.2 MHz

External synchronization input with programmable phase

shift, or internal clock output

Selectable PWM or PFM mode operation

Adjustable current limit for small inductor

External compensation and soft start

Startup into precharged output

Supported by ADIsimPower™ design tool

APPLICATIONS

Communications infrastructure

Networking and servers

Industrial and instrumentation

Healthcare and medical

Intermediate power rail conversion

DC-to-dc point of load applications

TYPICAL APPLICATION CIRCUIT

INTVCC

RTOP1

CC1

RC1 CSS1

CINT

CDRV

CIN1

CBST1

CBST2

VIN

VOUT1

COUT1

COUT2

VOUT2

RBOT1

RTOP2

RC2

CC2 CSS2

CIN2

RBOT2

ROSC

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

MODE

SCFG

TRK2

TRK1

VDRV

ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

09357-001

Figure 1.

GENERAL DESCRIPTION

The ADP2323 is a full featured, dual output, step-down dc-to-

dc regulator based on current-mode architecture. The ADP2323

integrates two high-side power MOSFETs and two low-side drivers

for the external N-channel MOSFETs. The two pulse-width mod-

ulation (PWM) channels can be configured to deliver dual 3 A

outputs or a parallel-to-single 6 A output. The regulator operates

from input voltages of 4.5 V to 20 V, and the output voltage can

be as low as 0.6 V.

The switching frequency can be programmed between 250 kHz

and 1.2 MHz, or synchronized to an external clock to minimize

interference in multirail applications. The dual PWM channels

run 180° out of phase, thereby reducing input current ripple as

well as reducing the size of the input capacitor.

The bidirectional synchronization pin can be programmed at

a 60°, 90°, or 120° phase shift, providing the possibility for a

stackable multiphase power solution.

The ADP2323 can be set to operate in pulse-frequency modulation

(PFM) mode at a light load for higher efficiency or in forced

PWM for noise sensitive applications. External compensation

and soft start provide design flexibility. Independent enable

inputs and power good outputs provide reliable power sequencing.

To enhance system reliability, the device also includes undervoltage

lockout (UVLO), overvoltage protection (OVP), overcurrent pro-

tection (OCP), and thermal shutdown (TSD).

The ADP2323 operates over the −40°C to +125°C junction

temperature range and is available in a 32-lead LFCSP_WQ

package.

100

00.5 1.0 1.5 2.0 2.5 3.0

EFFICIENCY (%)

OUTPUT CURRE NT (A)

VOUT = 5V

VOUT = 3. 3V

09357-002

Figure 2. Efficiency vs. Output Current at VIN = 12 V, fSW = 600 kHz

ADP2323 Data Sheet

Rev. A | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications ..................................................................................... 4

Absolute Maximum Ratings ............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution .................................................................................. 6

Pin Configuration and Function Descriptions ............................. 7

Typical Performance Characteristics ............................................. 9

Theory of Operation ...................................................................... 15

Control Scheme .......................................................................... 15

PWM Mode ................................................................................. 15

PFM Mode ................................................................................... 15

Precision Enable/Shutdown ...................................................... 15

Separate Input Voltages ............................................................. 15

Internal Regulator (INTVCC) .................................................. 15

Bootstrap Circuitry .................................................................... 16

Low-Side Driver .......................................................................... 16

Oscillator ..................................................................................... 16

Synchronization .......................................................................... 16

Soft Start ...................................................................................... 16

Peak Current-Limit and Short-Circuit Protection ................. 16

Voltage Tracking ......................................................................... 17

Parallel Operation....................................................................... 17

Power Good ................................................................................. 17

Overvoltage Protection .............................................................. 17

Undervoltage Lockout ............................................................... 18

Thermal Shutdown .................................................................... 18

Applications Information .............................................................. 19

ADIsimPower Design Tool ....................................................... 19

Input Capacitor Selection .......................................................... 19

Output Voltage Setting .............................................................. 19

Voltage Conversion Limitations ............................................... 19

Current-Limit Setting ................................................................ 19

Inductor Selection ...................................................................... 20

Output Capacitor Selection....................................................... 20

Low-Side Power Device Selection ............................................ 21

Programming UVLO Input ...................................................... 21

Compensation Components Design ....................................... 21

Design Example .............................................................................. 23

Output Voltage Setting .............................................................. 23

Current-Limit Setting ................................................................ 23

Frequency Setting ....................................................................... 23

Inductor Selection ...................................................................... 23

Output Capacitor Selection....................................................... 23

Low-Side MOSFET Selection ................................................... 24

Compensation Components ..................................................... 24

Soft Start Time Programming .................................................. 24

Input Capacitor Selection .......................................................... 24

External Components Recommendation .................................... 25

Typical Application Circuits ......................................................... 26

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

REVISION HISTORY

6/12—Rev. 0 to Rev. A

Change to Features Section ............................................................. 1

Added ADIsimPower Design Tool Section ................................. 19

7/11—Revision 0: Initial Version

Data Sheet ADP2323

Rev. A | Page 3 of 32

FUNCTIONAL BLOCK DIAGRAM

–

0.6V

SS1

FB1

COMP1

AMP1

CONTROL

LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

PROTECTION

BST1

SW1

MAX

HICCUP

MODE

NFET1

VDRV

DL1

0.7V

0.54V

OVP

PGOOD1

PVIN1

UVLO

EN1

CURRENT-

LIMIT

SELECTION

OSCILLATOR

PGND

SCFG

SYNC

CLK1

CLK2

SLOPE RAMP1

SLOPE RAMP2

5V REGULATOR

EN1_BUF

ADP2323

EN1_BUF

EN2_BUF INTVCC

PVIN1

GND

MODE MODE_BUF

SKIP MODE

THRESHOLD

MODE_BUF

SKIP

CMP1

SLOPE RAMP1

CLK1

–

ZERO CURRENT

CMP

VDRV

TRK1

–

1.2V

4µA1µA

OCP

CMP1

–

DRIVER

BOOST

REGULATOR

–

0.6V

SS2

FB2

COMP2

AMP2

CONTROL

LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

PROTECTION

BST2

SW2

MAX

HICCUP

MODE

NFET2

VDRV

DL2

0.7V

0.54V

OVP

PGOOD2

PVIN2

UVLO

EN2

CURRENT-

LIMIT

SELECTION

EN2_BUF

SKIP MODE

THRESHOLD

MODE_BUF

SKIP

CMP2

SLOPE RAMP2

CLK2

–

ZERO CURRENT

CMP

TRK2

–

1.2V

4µA1µA

OCP

CMP2

–

DRIVER

BOOST

REGULATOR

09357-042

CS1

CS2

Figure 3. Functional Block Diagram

ADP2323 Data Sheet

Rev. A | Page 4 of 32

SPECIFICATIONS

PVIN1 = PVIN2 = 12 V at TJ = −40°C to +125°C, unless otherwise noted.

Table 1.

Parameters Symbol Test Conditions/Comments Min Typ Max Units

POWER INPUT (PVINx PINS)

Power Input Voltage Range V

PVIN

4.5 20 V

Quiescent Current (PVIN1 + PVIN2) I

MODE = GND, no switching 3 5 mA

Shutdown Current (PVIN1 + PVIN2) I

SHDN

EN1 = EN2 = GND 50 100 µA

PVINx Undervoltage Lockout Threshold UVLO

PVINx Rising 4.3 4.5 V

PVINx Falling

3.5

3.8

FEEDBACK (FBx PINS)

FBx Regulation Voltage1 V

PVINx = 4.5 V to 20 V 0.594 0.6 0.606 V

FBx Bias Current I

0.01 0.1 µA

ERROR AMPLIFIER (COMPx PINS)

Transconductance g

230 300 370 µS

EA Source Current

ISOURCE

µA

EA Sink Current I

SINK

25 45 65 µA

INTERNAL REGULATOR (INTVCC PIN)

INTVCC Voltage 4.75 5 5.25 V

Dropout Voltage I

INTVCC

= 30 mA 400 mV

Regulator Current Limit 40 75 120 mA

SWITCH NODE (SWx PINS)

High-Side On Resistance

BST

to V

= 5 V 90 130 mΩ

SWx Peak Current Limit R

ILIM

= floating, V

BST

to V

= 5 V 4 4.8 5.8 A

ILIM

= 47 kΩ, V

BST

to V

= 5 V 2.3 3 3.7 A

ILIM

= 15 kΩ, V

BST

to V

= 5 V 0.8 1.5 2.2 A

SWx Minimum On Time3

tMIN_ON

130

SWx Minimum Off Time

MIN_OFF

150 ns

LOW-SIDE DRIVER (DLx PINS )

Rising Time

= 2.2 nF, see Figure 19 20 ns

Falling Time

= 2.2 nF, see Figure 22 10 ns

Sourcing Resistor 4 6 Ω

Sinking Resistor 2 4.5 Ω

OSCILLATOR (RT PIN)

PWM Switching Frequency f

OSC

= 100 kΩ 530 600 670 kHz

PWM Frequency Range 250 1200 kHz

SYNCHRONIZATION (SYNC PIN)

SYNC Input SYNC configured as input

Synchronization Range 300 1200 kHz

Minimum On Pulse Width

100

Minimum Off Pulse Width

100

High Threshold 1.3 V

Low Threshold 0.4 V

SYNC Output SYNC configured as output

Frequency on SYNC Pin f

CLKOUT

kHz

Positive Pulse Time 100 ns

SOFT START (SSx PINS)

SSx Pin Source Current I

2.5 3.5 4.5 µA

Data Sheet ADP2323

Rev. A | Page 5 of 32

Parameters Symbol Test Conditions/Comments Min Typ Max Units

TRACKING INPUT (TRKx PINS)

TRKx Input Voltage Range 0 600 mV

TRKx-to-FBx Offset Voltage TRKx = 0 mV to 500 mV −10 +10 mV

TRKx Input Bias Current 100 nA

POWER GOOD (PGOODx PINS)

Power Good Rising Threshold 87 90 93 %

Power Good Hysteresis 5 %

Power Good Deglitch Time From FBx to PGOODx 16 Clock cycle

PGOODx Leakage Current V

PGOOD

= 5 V 0.1 1 µA

PGOODx Output Low Voltage I

PGOOD

= 1 mA 50 100 mV

ENABLE (ENx PINS)

ENx Rising Threshold 1.2 1.28 V

ENx Falling Threshold 1.02 1.1 V

ENx Source Current EN voltage below falling threshold 5 µA

EN voltage above rising threshold 1 µA

MODE (MODE PIN)

Input High Voltage 1.3 V

Input Low Voltage 0.4 V

THERMAL

Thermal Shutdown Threshold 150 °C

Thermal Shutdown Hysteresis 15 °C

1 Tested in a feedback loop that adjusts VFB to achieve a specified voltage on the COMPx pin.

2 Pin-to-pin measurements.

3 Guaranteed by design.

ADP2323 Data Sheet

Rev. A | Page 6 of 32

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

PVIN1, PVIN2, EN1, EN2 −0.3 V to +22 V

SW1, SW2

−1 V to +22 V

BST1, BST2 V

+ 6 V

FB1, FB2, SS1, SS2,COMP1, COMP2,

PGOOD1, PGOOD2, TRK1, TRK2, SCFG,

SYNC, RT, MODE

−0.3 V to +6 V

INTVCC, VDRV, DL1, DL2 −0.3 V to +6 V

PGND to GND −0.3 V to +0.3 V

Temperature Range

Operating (Junction) −40°C to +125°C

Storage

−65°C to +150°C

Soldering Conditions JEDEC J-STD-020

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Boundary Condition

θJA is measured using natural convection on a JEDEC 4-layer

board, and the exposed pad is soldered to the printed circuit

board (PCB) with thermal vias.

Table 3. Thermal Resistance

Package Type θ

Unit

32-Lead LFCSP_WQ 32.7 °C/W

ESD CAUTION

Data Sheet ADP2323

Rev. A | Page 7 of 32

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1SW1

2BST1

3DL1

4PGND

5VDRV

6DL2

7BST2

8SW2

PGOOD1

NOTES

1. THE EXPOSED PAD SHOULD BE SOLDERED TO AN EXTERNAL GND PLANE.

SCFG

SYNC

GND

INTVCC

MODE

PGOOD2

FB2

COMP2

SS2

TRK2

EN2

PVIN2

SW2

FB1

COMP1

SS1

TRK1

EN1

PVIN1

SW1

TOP VIEW

(Not to Scale)

ADP2323

09357-003

Figure 4. Pin Configuration (Top View)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 PGOOD1 Power-Good Output (Open Drain) for Channel 1. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.

2 SCFG Synchronization Configuration Input. The SCFG pin configures the SYNC pin as an input or output. Connect

SCFG to INTVCC to configure SYNC as an output. Using a resistor to pull down to GND configures SYNC as an

input with various phase shift degrees.

3 SYNC Synchronization. This pin can be configured as an input or an output. When configured as an output, it

provides a clock at the switching frequency. When configured as an input, this pin accepts an external clock

to which the regulators are synchronized and the phase shift is configured by SCFG. Note that when SYNC is

configured as an input, the PFM mode is disabled and the device works only in continuous conduction mode

(CCM).

4 GND Analog Ground. Connect to the ground plane.

5 INTVCC Internal 5 V Regulator Output. The IC control circuits are powered from this voltage. Place a 1 F ceramic

capacitor between INTVCC and GND.

6 RT Connect a resistor between RT and GND to program the switching frequency between 250 kHz and 1.2 MHz.

7 MODE Mode Selection. When this pin is connected to INTVCC, the PFM mode is disabled and the regulator works

only in CCM. When this pin is connected to ground, the PFM mode is enabled. If the low-side device is a

diode, the MODE pin must be connected to ground.

8 PGOOD2 Power-Good Output (Open Drain) for Channel 2. A pull-up resistor of 10 kΩ to 100 kΩ is recommended.

9 FB2 Feedback Voltage Sense Input for Channel 2. Connect to a resistor divider from the Channel 2 output voltage,

VOUT2. Connect FB2 to INTVCC for parallel applications.

10 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from COMP2 to GND. Connect COMP1 and

COMP2 together for parallel applications.

11 SS2 Soft Start Control for Channel 2. Connect a capacitor from SS2 to GND to program the soft start time. For

parallel applications, SS2 remains open.

12 TRK2 Tracking Input for Channel 2. To track a master voltage, drive this pin from a voltage divider from the master

voltage. If the tracking function is not used, connect TRK2 to INTVCC.

13 EN2 Enable Pin for Channel 2. An external resistor divider can be used to set the turn-on threshold. When not

using the enable pin, connect EN2 to PVIN2.

14, 15 PVIN2 Power Input for Channel 2. Connect PVIN2 to the input power source, and connect a bypass capacitor

between PVIN2 and ground.

16, 17 SW2 Switch Node for Channel 2.

18 BST2 Supply Rail for the Gate Drive of Channel 2. Place a 0.1 µF capacitor between SW2 and BST2.

19 DL2 Low-Side Gate Driver Output for Channel 2. Connect a resistor between DL2 and PGND to program the

current-limit threshold of Channel 2.

20 VDRV Low-Side Driver Supply Input. Connect VDRV to INTVCC. Place a 1 µF ceramic capacitor between the VDRV

pin and PGND.

21 PGND Driver Power Ground. Connect to the source of the synchronous N-channel MOSFET.

22 DL1 Low-Side Gate Driver Output for Channel 1. Connect a resistor between this pin and PGND to program the

current-limit threshold of Channel 1.

ADP2323 Data Sheet

Rev. A | Page 8 of 32

Pin No. Mnemonic Description

23 BST1 Supply Rail for the Gate Drive of Channel 1. Place a 0.1 µF capacitor between SW1 and BST1.

24, 25 SW1 Switch Node for Channel 1.

26, 27 PVIN1 Power Input for Channel 1. This pin is the power input for Channel 1 and provides power for the internal

regulator. Connect to the input power source and connect a bypass capacitor between PVIN1 and ground.

28 EN1 Enable Pin for Channel 1. An external resistor divider can be used to set the turn-on threshold. When not

using the enable pin, connect the EN1 pin to PVIN1.

29 TRK1 Tracking Input for Channel 1. To track a master voltage, drive this pin from a voltage divider from the master

voltage. If the tracking function is not used, connect TRK1 to INTVCC.

30 SS1 Soft Start Control for Channel 1. To program the soft start time, connect a capacitor from SS1 to GND.

31 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to GND. Connect COMP1 and

COMP2 together for a parallel application.

32 FB1 Feedback Voltage Sense Input for Channel 1. Connect to a resistor divider from the Channel 1 output voltage,

OUT1

Exposed Pad Solder the exposed pad to an external GND plane.

Data Sheet ADP2323

Rev. A | Page 9 of 32

TYPICAL PERFORMANCE CHARACTERISTICS

Operating conditions: TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 4.7 µH, COUT = 2 × 47 µ F, f SW = 600 kHz, unless otherwise noted.

100

00.5 1.0 1.5 2.0 2.5 3.0

EFFICIENCY (%)

OUTPUT CURRE NT (A)

OUT

= 5.0V

OUT

= 3.3V

OUT

= 2.5V

OUT

= 1.8V

OUT

= 1.5V

OUT

= 1.2V

INDUCTOR: CDRH105RNP - 3R3N

MOSFET: FDS 8880

09357-005

Figure 5. Efficiency at VIN = 12 V, fSW = 600 kHz, FPWM

100

EFFICIENCY (%)

VOUT = 3. 3V, FPWM

VOUT = 3. 3V, PFM

VOUT = 5V, FPWM

VOUT = 5V, PFM

09357-006

INDUCTOR: CDRH105RNP - 3R3N

MOSFET: FDS 8880

0.01 0.1 110

OUTPUT CURRE NT (A)

Figure 6. Efficiency at VIN = 12 V, fSW = 600 kHz, PFM

46810 12 14 16 18 20

SHUTDOWN CURRENT (μA)

VIN (V)

09357-007

TJ = –40° C

TJ = +25°C

TJ = +125°C

Figure 7. Shutdown Current vs. VIN

00.5 1.0 1.5 2.0 2.5 3.0

OUTPUT CURRE NT (A)

INDUCTOR: CDRH105RNP - 6R8N

MOSFET: FDS 8880

VOUT = 5. 0V

VOUT = 3. 3V

VOUT = 2. 5V

VOUT = 1. 8V

VOUT = 1. 5V

VOUT = 1. 2V

09357-008

100

EFFICIENCY (%)

Figure 8. Efficiency at VIN = 12 V, fSW = 300 kHz, FPWM

100

0.01 0.1 110

EFFICIENCY (%)

OUTPUT CURRE NT (A)

VOUT = 3. 3V, FPWM

VOUT = 3. 3V, PFM

VOUT = 5V, FPWM

VOUT = 5V, PFM

09357-009

INDUCTOR: CDRH105RNP - 6R8N

MOSFET: FDS 8880

Figure 9. Efficiency at VIN = 12 V, fSW = 300 kHz, PFM

2.80

2.85

2.90

2.95

3.00

3.05

3.10

3.15

3.20

4 6 8 10 12 14

16 18 20

QUIESCE NT CURRENT (mA)

(V)

= –40° C

= +25°C

= +125°C

09357-010

Figure 10. Quiescent Current vs. VIN

ADP2323 Data Sheet

Rev. A | Page 10 of 32

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

–40 –20 020 40 60 80 100 120

UVL O THRE S HOL D ( V )

TEMPERAT URE ( °C)

RISING

FALLING

09357-011

Figure 11. UVLO Threshold vs. Temperature

0.90

0.92

0.94

0.96

0.98

1.00

1.02

1.04

1.06

1.08

1.10

–40 –20 020 40 60 80 100 120

EN SOURCE CURRENT (µA)

TEMPERAT URE ( °C)

09357-012

Figure 12. EN Source Current at VEN = 1.5 V

594

596

598

600

602

604

606

FE E DBACK V OLTAGE (mV)

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-013

Figure 13. FB Voltage vs. Temperature

1.00

1.05

1.10

1.15

1.20

1.25

1.30

ENABL E THRESHOL D ( V )

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

RISING

FALLING

09357-014

Figure 14. EN Threshold vs. Temperature

4.60

4.65

4.70

4.75

4.80

4.85

4.90

4.95

5.00

5.05

5.10

–40 –20 020 40 60 80 100 120

EN SOURCE CURRENT (µA)

TEMPERAT URE ( °C)

09357-015

Figure 15. EN Source Current at VEN = 1 V

250

260

270

280

290

300

310

320

330

340

350

TRANSCONDUCTANCE (µ S )

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-016

Figure 16. gm vs. Temperature

Data Sheet ADP2323

Rev. A | Page 11 of 32

540

560

580

600

620

640

660

FREQUENCY (kHz)

OSC

= 100kΩ

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-017

Figure 17. Frequency vs. Temperature

100

110

120

130

MOSFET RESISTOR (mΩ)

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-018

Figure 18. MOSFET RDSON vs. Temperature

09357-019

CH1 5.00V CH2 2.00V M20.0ns A CH1 1. 10V

T 31.20%

Figure 19. Low-Side Driver Rising Edge Waveform, CDL = 2.2 nF

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

46810 12 14 16 18 20

VOLTAGE (V)

VIN (V)

09357-020

Figure 20. INTVCC Voltage vs. VIN

2.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

SSx P IN SO URCE CURRE NT (µA)

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-021

Figure 21. SSx Pin Source Current vs. Temperature

09357-022

CH1 5.00V CH2 2.00V M20.0ns A CH1 1. 10V

T 60.20%

Figure 22. Low-Side Driver Falling Edge Waveform, CDL = 2.2 nF

ADP2323 Data Sheet

Rev. A | Page 12 of 32

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-023

4.0

4.2

4.4

4.6

4.8

5.0

5.2

5.4

5.6

5.8

PEAK CURRE NT LIMIT ( A)

Figure 23. Current-Limit Threshold vs. Temperature, RILIM = Floating

0.8

1.0

1.2

1.4

1.6

1.8

2.0

PEAK CURRE NT LIMIT ( A)

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-024

Figure 24. Current-Limit Threshold vs. Temperature, RILIM = 15 kΩ

09357-025

CH1 10.0mV

CH2 10.0V

CH4 500mA Ω

M2.00µs A CH2 9. 40V

T 50.20%

OUT

(AC)

Figure 25. Discontinuous Conduction Mode (DCM)

2.5

2.6

2.7

2.8

2.9

3.0

3.1

3.2

PEAK CURRE NT LIMIT ( A)

–40 –20 020 40 60 80 100 120

TEMPERAT URE ( °C)

09357-026

Figure 26. Current-Limit Threshold vs. Temperature, RILIM = 47 kΩ

09357-027

CH1 10.0mV

CH2 10.0V

CH4 2.00A Ω

M2.00µs A CH2 5. 80V

T 50.00%

OUT

(AC)

Figure 27. Continuous Conduction Mode (CCM)

09357-028

CH1 100mV

CH2 10.0V

CH4 1.00A Ω

M400µs A CH1 –12.0mV

T 60.40%

OUT

(AC)

Figure 28. Power Saving Mode

Data Sheet ADP2323

Rev. A | Page 13 of 32

09357-029

CH1 2.00V

CH3 10.0V CH2 5.00V

CH4 2.00A Ω

M1.00ms A CH2 1.80V

T 50.40%

OUT

PGOOD

OUT

Figure 29. Soft Start With Full Load

09357-030

CH1 100mV

CH4 1.00A Ω

M200µs A CH4 1.00A

T 70.20%

OUT

(AC)

OUT

Figure 30. Load Transient Response, 0.5 A to 2.5 A

09357-031

CH1 2.00V

CH2 10.0V

CH4 2.00A Ω

M10.0ms A CH1 960mV

T 20.60%

OUT

Figure 31. Output Short

09357-032

CH1 2.00V

CH3 10.0V CH2 5.00V

CH4 1.00A Ω

M1.00ms A CH2 1.80V

T 50.40%

OUT

PGOOD

Figure 32. Precharged Output

09357-033

CH1 20.0mV

CH3 5.00V

CH2 5.00V M1.00ms A CH1 –8.00mV

T 72.00%

OUT

(AC)

OUT

Figure 33. Line Transient Response, VIN from 8 V to 14 V, IOUT = 3 A

09357-034

CH1 2.00V

CH2 10.0V

CH4 2.00A Ω

M10.0ms A CH1 1.28V

T 60.40%

OUT

Figure 34. Output Short Recovery

ADP2323 Data Sheet

Rev. A | Page 14 of 32

09357-035

CH1 10.0V

CH3 5.00V CH2 10.0V M1.00µs A CH3 2.90V

T 50.20%

SYNC

SW2

SW1

Figure 35. External Synchronization with 60° Phase Shift

09357-036

CH1 10.0V

CH3 5.00V

CH2 10.0V M1.00µs A CH3 2.90V

T 50.20%

SYNC

SW2

SW1

Figure 36. External Synchronization with 120° Phase Shift

09357-037

CH3 1.00V

CH2 1.00V

M2.00ms A CH2 660mV

T 43.00%

MASTER

SLAVE

Figure 37. Coincident Tracking

09357-038

CH1 10.0V

CH3 5.00V CH2 10.0V M1.00µs A CH3 2.90V

T 50.20%

SYNC

SW2

SW1

Figure 38. External Synchronization with 90° Phase Shift

09357-039

CH1 10.0V

CH3 2.00A Ω CH4 2.00A Ω

CH2 10.0V M1.00µs A CH2 5. 80V

T 50.00%

SW2

SW1

Figure 39. Dual Phase, Single Output, VOUT = 3.3 V, IOUT = 6 A

09357-040

CH3 1.00V

CH2 1.00V

M2.00ms A CH2 660mV

T 43.00%

MASTER

SLAVE

Figure 40. Ratiometric Tracking

Data Sheet ADP2323

Rev. A | Page 15 of 32

THEORY OF OPERATION

The ADP2323 is a full featured, dual output, step-down dc-to-

dc regulator based on current-mode architecture. It integrates two

high-side power MOSFETs and two low-side drivers for

external MOSFETs. The ADP2323 targets high performance

applications that require high efficiency and design flexibility.

The ADP2323 can operate with an input voltage from 4.5 V to

20 V, and can regulate the output voltage down to 0.6 V.

Additional features for flexible design include programmable

switching frequency, programmable soft start, external compen-

sation, independent enable inputs, and power good outputs.

CONTROL SCHEME

The ADP2323 uses a fixed frequency, current-mode PWM

control architecture during medium to full loads, but shifts to a

power save mode (PFM) at light loads when the PFM mode is

enabled. The power save mode reduces switching losses and

boosts efficiency under light loads. When operating in the fixed

frequency PWM mode, the duty cycle of the integrated N-

channel MOSFET (referred to interchangeably as NFET or

MOSFET) is adjusted, which, in turn, regulates the output

voltage. When operating in power save mode, the switching

frequency is adjusted to regulate the output voltage.

PWM MODE

In PWM mode, the ADP2323 operates at a fixed frequency that

is set by an external resistor. At the start of each oscillator cycle, the

high-side NFET turns on, placing a positive voltage across the

inductor. The inductor current increases until the current sense

signal crosses the peak inductor current threshold that turns off

the high-side NFET and turns on the low-side NFET (diode). This

places a negative voltage across the inductor causing the

inductor current to reduce. The low-side NFET (diode) stays on

for the remainder of the cycle or until the inductor current reaches

zero.

PFM MODE

Pull the MODE pin to ground to enable the PFM mode. When

the COMPx voltage is below the PFM threshold voltage, the

device enters the PFM mode.

When the device enters the PFM mode, it monitors the FBx

voltage to regulate the output voltage. Because the high-side and

low-side NFETs are turned off, the output voltage drops due to

the load current discharging the output capacitor. When the FBx

voltage drops below 0.605 V, the device starts switching and the

output voltage increases as the output capacitor is charged by the

inductor current. When the FBx voltage exceeds 0.62 V, the device

turns off both the high-side and low-side NFETs until the FBx

voltage drops to 0.605 V. In the PFM mode, the output voltage

ripple is larger than the ripple in the PWM mode.

PRECISION ENABLE/SHUTDOWN

The ADP2323 has two independent enable pins (EN1 and EN2)

for each channel. The ENx pin has an internal pull-down

current source (5 µA) that provides default turn off when an

ENx pin is open.

When the voltage on the EN1 or EN2 pin exceeds 1.2 V

(typical), Channel 1 or Channel 2 is enabled and the internal

pull-down current source at the EN1 or EN2 pin is reduced to 1

µA, which allows the user to program the input voltage

undervoltage lockout (UVLO).

When the voltage on the EN1 or EN2 pin drops below 1.1 V

(typical), Channel 1 or Channel 2 turns off. When EN1 and

EN2 are both below 1.1 V, all of the internal circuits turn off

and the device enters the shutdown mode.

SEPARATE INPUT VOLTAGES

The ADP2323 supports two separate input voltages. This means

that the PVIN1 and PVIN2 voltages can be connected to two

different supply voltages. In these types of applications, the

PVIN1 voltage needs to be above the UVLO voltage before the

PVIN2 voltage begins to rise because the PVIN1voltage provides

the power supply for the internal regulator and control circuitry.

This feature makes it possible for a cascading supply operation as

shown in Figure 41, where PVIN2 is sourced from the Channel 1

output. In this configuration, the Channel 1 output voltage needs

to be high enough to maintain Channel 2 in regulation, and the

Channel 1 output voltage needs to be higher than the input

voltage UVLO threshold.

SW2

DL2

PVIN2

SW1

DL1

PGND

OUT1

PVIN1

ADP2323

OUT1

OUT2

09357-043

Figure 41. Cascading Supply Operation

INTERNAL REGULATOR (INTVCC)

The internal regulator provides a stable voltage supply for the

internal control circuits and bias voltage for the low-side gate

drivers. A 1 µF ceramic capacitor is recommended to be placed

between INTVCC and GND. The internal regulator also

includes a current-limit circuit for protection.

The internal regulator is active when either one of the channels is

enabled. The PVIN1 pin provides power for the internal

regulator that is used by both channels.

ADP2323 Data Sheet

Rev. A | Page 16 of 32

BOOTSTRAP CIRCUITRY

The ADP2323 integrates the boot regulators to provide the gate

drive voltage for the high-side NFETs. The regulators generate 5

V bootstrap voltages between the BSTx pin and the SWx pin.

It is recommended that an X7R or an X5R, 0.1 µF ceramic

capacitor be placed between the BSTx and the SWx pins.

LOW-SIDE DRIVER

The DLx pin provides the gate drive for the low-side N-channel

MOSFET. Internal circuitry monitors the gate driver signal to

ensure break-before-make switching to prevent cross

conduction.

The VDRV pin provides the power supply to the low-side

drivers. It is limited to a 5.5 V maximum input, and placing

a 1 µF ceramic capacitor close to this pin is recommended.

OSCILLATOR

A resistor from RT to GND programs the switching frequency

according to the following equation:

fSW [kHz] =

]kΩ[

000,60

OSC

A 200 kΩ resistor sets the frequency to 300 kHz, and a 100 kΩ

resistor sets the frequency to 600 kHz. Figure 42 shows the

typical relationship between fSW and ROSC.

200

300

400

600

800

500

700

900

1000

1100

1200

50 90 130 170 210

70 110 150 190 230 250

FREQUENCY (kHz)

OSC

(kΩ)

09357-044

Figure 42. fSW vs. ROSC

SYNCHRONIZATION

The SYNC pin can be configured as an input or an output by

setting the SCFG pin as shown in Table 5.

Table 5. SCFG Configuration

SCFG SYNC Phase Shift

High Output 0°

GND

Input

90°

180 kΩ to GND Input 120°

100 kΩ to GND Input 60°

When the SYNC pin is configured as an output, it generates a

clock with a frequency that is equal to the internal switching

frequency.

When the SYNC pin is configured as an input, the ADP2323

synchronizes to the external clock that is applied to the SYNC pin,

and the internal clock must be programmed lower than the

external clock. The phase shift can be programmed by the SCFG

pin.

When working in synchronization mode, the ADP2323 disables

the PFM mode and works only in the CCM mode.

SOFT START

The SSx pins are used to program the soft start time. Place a

capacitor between SSx and GND; an internal current charges

this capacitor to establish the soft start ramp. The soft start time

can be calculated using the following equation:

T×

=6.0

where:

CSS is the soft start capacitance.

ISS is the soft start pull-up current (3.5 µA).

If the output voltage is precharged prior to power up, the

ADP2323 prevents the low-side MOSFET from turning on until

the soft start voltage exceeds the voltage on the FBx pin.

During soft start, the ADP2323 uses frequency foldback to

prevent output current runaway. The switching frequency is

reduced according to the voltage present at the FBx pin, which

allows more time for the inductor to discharge. The correlation

between the switching frequency and the FBx pin voltage is listed

in Table 6.

Table 6. FBx Pin Voltage and Switching Frequency

FBx Pin Voltage Switching Frequency

≥ 0.4 V f

0.4 V > V

≥ 0.2 V 1/2 f

< 0.2 V 1/4 f

PEAK CURRENT-LIMIT AND SHORT-CIRCUIT

PROTECTION

The ADP2323 uses a peak current-limit protection circuit to

prevent current runaway. Place a resistor between DLx and

PGND to program the current-limit value listed in Table 7. The

programmable current-limit threshold feature allows for the use

of a small size inductor for low current applications.

Table 7. Peak Current-Limit Threshold Setting

RILIM

Peak Current-Limit Threshold

Floating 4.8 A

47 kΩ

3 A

15 kΩ 1.5 A

Data Sheet ADP2323

Rev. A | Page 17 of 32

The ADP2323 uses hiccup mode for overcurrent protection.

When the peak inductor current reaches the current-limit

threshold, the high-side MOSFET turns off and the low-side

driver turns on until the next cycle while the overcurrent

counter increments.

If the overcurrent counter reaches 10, or the FBx pin voltage falls

to 0.51 V after the soft start, the device enters hiccup mode. During

this mode, the high-side MOSFET and low-side driver are both

turned off. The device remains in this mode for seven soft start

times and then attempts to restart from soft start. If the current-

limit fault is cleared, the device resumes normal operation;

otherwise, it reenters hiccup mode.

In some cases, the input voltage (PVIN) ramp rate is too slow or

the output capacitor is too large to support the setting regulation

voltage during the soft start causing the device to enter the

hiccup mode. To avoid such cases, use a resistor divider at the

ENx pin to program the input voltage UVLO or use a longer

soft start time.

VOLTAGE TRACKING

The ADP2323 has a tracking input, TRKx, that allows the output

voltage to track an external (master) voltage. It allows power

sequencing applicable to FPGAs, DSPs, and ASICs, which may

require a power sequence between the core and the I/O voltages.

The internal error amplifier includes three positive inputs: the

internal reference voltage, the soft start voltage, and the tracking

input voltage. The error amplifier regulates the feedback voltage

to the lowest of the three voltages. To track a master voltage, tie the

TRKx pin to a resistor divider from the master voltage as shown

in Figure 43.

FBx

TRKx SWx

ADP2323

VMASTER

RTRK_TOP

RTRK_BOT

VSLAVE

RTOP

RBOT

09357-045

Figure 43. Voltage Tracking

A common application is coincident tracking, which is shown in

Figure 44. Coincident tracking limits the slave output voltage to

be the same as the master voltage until it reaches regulation. For

coincident tracking, set RTRK_TOP = RTOP and RTRK_BOT = RBOT.

TIME

VOLTAGE

VMASTER

VSLAVE

09357-046

Figure 44. Coincident Tracking

Ratiometric tracking is shown in Figure 45. The slave output is

limited to a fraction of the master voltage. In this application, the

slave and master voltages reach the final value at the same time.

TIME

VOLTAGE

MASTER

SLAVE

09357-047

Figure 45. Ratiometric Tracking

The ratio of the slave output voltage to the master voltage is a

function of the two dividers, as follows:

BOTTRK

TOPTRK

BOT

TOP

MASTER

SLAVE

The final TRKx pin voltage must be higher than 0.54 V. If the

TRK function is not used, connect the TRKx pin to INTVCC.

PARALLEL OPERATION

ADP2323 supports a two phase parallel operation to provide a

single output of 6 A. To configure the ADP2323 as a two phase

single output

1. Connect the FB2 pin to INTVCC, thereby disabling the

Channel 2 error amplifier.

2. Connect COMP1 to COMP2 and connect EN1 to EN2.

3. Use SS1 to set the soft start time and keep SS2 open.

During parallel operation, the voltages of PVIN1 and PVIN2

should be the same.

POWER GOOD

The power good (PGOODx) pin is an active high, open drain

output that indicates if the regulator output voltage is within

regulation. High indicates that the voltage at an FBx pin (and,

hence, the output voltage) is above 90% of the reference voltage.

Low indicates that the voltage at an FBx pin (and, hence, the

output voltage) is below 85% of the reference voltage. There is a

16-cycle deglitch time between FBx and PGOODx.

OVERVOLTAGE PROTECTION

The ADP2323 provides an overvoltage protection (OVP)

feature to protect the system against the output shorting to a

higher voltage supply or when a strong load transient occurs. If

the feedback voltage increases to 0.7 V, the internal high-side

MOSFET and low-side driver turn off until the voltage at the

FBx pin reduces to 0.63 V, at which time the ADP2323 resumes

normal operation.

ADP2323 Data Sheet

Rev. A | Page 18 of 32

UNDERVOLTAGE LOCKOUT

The undervoltage lockout (UVLO) threshold is 4.2 V with 0.5 V

hysteresis to prevent the device from power-on glitches. When

the PVIN1 or PVIN2 voltage rises above 4.2 V, Channel 1 or

Channel 2 is enabled and the soft start period initiates. When either

PVIN1 or PVIN2 drops below 3.7 V, it turns off Channel 1 or

Channel 2, respectively.

THERMAL SHUTDOWN

In the event that the ADP2323 junction temperature exceeds

150°C, the thermal shutdown circuit turns off the regulator. A

15°C hysteresis is included so that the ADP2323 does not

recover from thermal shutdown until the on-chip temperature

drops below 135°C. Upon recovery, soft start is initiated prior to

normal operation.

Data Sheet ADP2323

Rev. A | Page 19 of 32

APPLICATIONS INFORMATION

ADIsimPower DESIGN TOOL

The ADP2323 is supported by the ADIsimPower design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic and bill of materials,

and calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and parts count

while taking into consideration the operating conditions

and limitations of the IC and all real external components. For

more information about ADIsimPower design tools, refer to

www.analog.com/ADIsimPower. The tool set is available from

this website, and users can request an unpopulated board

through the tool.

INPUT CAPACITOR SELECTION

The input decoupling capacitor attenuates high frequency noise

on the input and acts as an energy reservoir. This capacitor

should be a ceramic capacitor in the range of 10 µF to 47 µF and

must be placed close to the PVINx pin. The loop composed of

this input capacitor, high-side NFET, and low-side NFET must

be kept as small as possible. The voltage rating of the input

capacitor must be greater than the maximum input voltage. The

rms current rating of the input capacitor should be larger than

the following equation:

( )

DDII

OUT

rmsC

IN −××= 1

OUTPUT VOLTAGE SETTING

The output voltage of the ADP2323 can be set by an external

resistive divider using the following equation:











+×=

BOT

TOP

OUT R

V16.0

To limit output voltage accuracy degradation due to FBx pin

bias current (0.1 µA maximum) to less than 0.5% (maximum),

ensure that RBOT is less than 30 kΩ.

Table 8 provides the recommended resistive divider for various

output voltage options.

Table 8. Resistive Divider for Various Output Voltages

VOUT (V)

RTOP, ±1% (kΩ)

RBOT, ±1% (kΩ)

1.0 10 15

1.2 10 10

1.5 15 10

1.8 20 10

2.5 47.5 15

3.3 10 2.21

5.0 22 3

VOLTAGE CONVERSION LIMITATIONS

The minimum output voltage for a given input voltage and

switching frequency is constrained by the minimum on time.

The minimum on time of the ADP2323 is typically 130 ns. The

minimum output voltage in CCM mode at a given input voltage

and frequency can be calculated by using the following equation:

VOUT_MIN = VIN × tMIN_ON × fSW − (RDSON1 − RDSON2) × IOUT_MIN ×

tMIN_ON × fSW − (RDSON2 + RL) × IOUT_MIN

where:

VOUT_MIN is the minimum output voltage.

tMIN_ON is the minimum on time.

IOUT_MIN is the minimum output current.

fSW is the switching frequency.

RDSON1 is the high-side MOSFET on resistance.

RDSON2 is the low-side MOSFET on resistance.

RL is the series resistance of output inductor.

The maximum output voltage for a given input voltage and

switching frequency is constrained by the minimum off time

and the maximum duty cycle. The minimum off time is typically

150 ns and the maximum duty is typically 90% in the ADP2323.

The maximum output voltage that is limited by the minimum off

time at a given input voltage and frequency can be calculated

using the following equation:

VOUT_MAX = VIN × (1 – tMIN_OFF × fSW) – (RDSON1 – RDSON2) ×

IOUT_MAX × (1 – tMIN_OFF × fSW) – (RDSON2 + RL) × IOUT_MAX

where:

VOUT_MAX is the maximum output voltage.

tMIN_OFF is the minimum off time.

IOUT_MAX is the maximum output current.

The maximum output voltage limited by the maximum duty

cycle at a given input voltage can be calculated by using the

following equation:

VOUT_MAX = DMAX × VIN

where DMAX is the maximum duty.

As the previous equations show, reducing the switching frequency

alleviates the minimum on time and minimum off time

limitation.

CURRENT-LIMIT SETTING

The ADP2323 has three selectable current-limit thresholds.

Make sure that the selected current-limit value is larger than the

peak current of the inductor, IPEAK.

ADP2323 Data Sheet

Rev. A | Page 20 of 32

INDUCTOR SELECTION

The inductor value is determined by the operating frequency,

input voltage, output voltage, and inductor ripple current. Using a

small inductor leads to a faster transient response but degrades

efficiency due to larger inductor ripple current, whereas a large

inductor value leads to smaller ripple current and better effi-

ciency but results in a slower transient response. Thus, there is a

trade-off between the transient response and efficiency. As a

guideline, the inductor ripple current, ΔIL, is typically set to 1/3

of the maximum load current. The inductor value can be

calculated using the following equation:

( )

IN OUT

L SW

VV D

LIf

−×

=∆×

where:

VIN is the input voltage.

VOUT is the output voltage.

ΔIL is the inductor ripple current.

fSW is the switching frequency.

D is the duty cycle.

OUT

The ADP2323 uses adaptive slope compensation in the current

loop to prevent subharmonic oscillations when the duty cycle is

larger than 50%. The internal slope compensation limits the

minimum inductor value.

For a duty cycle that is larger than 50%, the minimum inductor

value is determined by the following equation:

( )

OUT

×−

The inductor peak current is calculated using the following

equation:

OUT

PEAK

II ∆

The saturation current of the inductor must be larger than the

peak inductor current. For the ferrite core inductors with a

quick saturation characteristic, the saturation current rating of the

inductor should be higher than the current-limit threshold of the

switch to prevent the inductor from getting into saturation.

The rms current of the inductor can be calculated by the

following equation:

OUT

RMS

II ∆

Shielded ferrite core materials are recommended for low core

loss and low EMI.

Table 9. Recommended Inductors

Vendor Part No.

Value

[µH]

ISAT

[A]

IRMS

[A]

DCR

[mΩ]

Sumida CDRH105RNP-1R5N 1.5 10.5 8.3 5.8

CDRH105RNP-2R2N 2.2 9.25 7.5 7.2

CDRH105RNP-3R3N

3.3

7.8

6.5

10.4

CDRH105RNP-4R7N 4.7 6.4 6.1 12.3

CDRH105RNP-6R8N 6.8 5.4 5.4 18

Coilcraft MSS1048-152NL 1.5 10.5 10.8 5.8

MSS1048-222NL 2.2 8.4 9.78 7.2

MSS1048-332NL 3.3 7.38 7.22 10.4

MSS1048-472NL 4.7 6.46 6.9 12.3

MSS1048-682NL 6.8 5.94 6.01 18

Wurth

Elektronik

7447797180 1.8 13.3 7.3 16

7447797300

3.0

10.5

7.0

7447797470 4.7 8.0 5.8 27

7447797620 6.2 7.5 5.5 30

OUTPUT CAPACITOR SELECTION

The output capacitor selection affects both the output voltage

ripple and the loop dynamics of the regulator. For example,

during load step transient on the output, when the load is

suddenly increased, the output capacitor supplies the load until

the control loop has a chance to ramp up the inductor current,

which causes an undershoot of the output voltage.

Use the following equation to calculate the output capacitance that

is required to meet the voltage droop requirement:

( )

UVOUTOUT

STE

UVOUT

VVV

LIK

2∆×−×

×∆×

where:

ΔISTEP is the load step.

ΔVOUT_UV is the allowable undershoot on the output voltage.

KUV is a factor, typically setting KUV = 2.

Another case is when a load is suddenly removed from the

output and the energy stored in the inductor rushes into the

output capacitor, which causes the output to overshoot. The

output capacitance required to meet the overshoot requirement

can be calculated using the following equation:

_22

()

OV STEP

OUT OV OUT OUT OV OUT

KI L

CVV V

×∆ ×

=+∆ −

where:

ΔVOUT_OV is the allowable overshoot on the output voltage.

KOV is a factor, typically setting KOV = 2.

The output ripple is determined by the ESR of the output

capacitor and its capacitance value. Use the following equation to

select a capacitor that can meet the output ripple requirements:

RIPPLEOUT

8∆××

∆

RIPPLEOUT

ESR I

R∆

∆

Data Sheet ADP2323

Rev. A | Page 21 of 32

where:

ΔVOUT_RIPPLE is the allowable output voltage ripple.

RESR is the equivalent series resistance of the output capacitor.

Select the largest output capacitance given by COUT_UV, COUT_OV,

and COUT_RIPPLE to meet both load transient and output ripple

performance.

The selected output capacitor voltage rating must be greater

than the output voltage. The minimum rms current rating of

the output capacitor is determined by the following equation:

rmsC

OUT

∆

LOW-SIDE POWER DEVICE SELECTION

The ADP2323 has integrated low-side MOSFET drivers, which

can drive the low-side N-channel MOSFETs (NFETs). The

selection of the low-side N-channel MOSFET affects the dc-to-

dc regulator performance.

The selected MOSFET must meet the following requirements:

• Drain source voltage (VDS) must be higher than 1.2 × VIN.

• Drain current (ID) must be greater than the 1.2 × ILIMIT_MAX,

where ILIMIT_MAX is the selected maximum current-limit

threshold.

The ADP2323 low-side gate drive voltage is 5 V. Make sure that

the selected MOSFET can be fully turned on at 5 V.

Total gate charge (Qg at 5 V) must be less than 30 nC. Lower Qg

characteristics constitute higher efficiency.

When the high-side MOSFET is turned off, the low-side

MOSFET carries the inductor current. For low duty cycle

applications, the low-side MOSFET carries the current for most

of the period. To achieve higher efficiency, it is important to

select a low on-resistance MOSFET. The power conduction loss

for the low-side MOSFET can be calculated using the following

equation:

PFET_LOW = IOUT

2 × RDSON × (1 − D)

where RDSON is the on resistance of the low-side MOSFET.

Make sure that the MOSFET can handle the thermal dissipation

due to the power loss.

In some cases, efficiency is not critical for the system; therefore,

the diode can be selected as the low-side power device. The

average current of the diode can be calculated using the

following equation:

IDIODE (AVG) = (1 − D) × IOUT

The reverse breakdown voltage rating of the diode must be

greater than the input voltage with an appropriate margin to

allow for ringing, which may be present at the SWx node. A

Schottky diode is recommended because it has low forward

voltage drop and fast switching speed.

If a diode is used for the low-side device, the ADP2323 must

enable the PFM mode by connecting the MODE pin to ground.

Table 10. Recommended MOSFETs

Vendor Part No. V

DSON

Fairchild FDS8880 30 V 10.7 A 12 mΩ 12 nC

Fairchild FDMS7578 25 V 14 A 8 mΩ 8 nC

Fairchild FDS6898A 20 V 9.4 A 14 mΩ 16 nC

Vishay Si4804CDY 30 V 7.9 A 27 mΩ 7 nC

Vishay SiA430DJ 20 V 10.8 A 18.5 mΩ 5.3 nC

AOS AON7402 30 V 39 A 15 mΩ 7.1 nC

AOS AO4884L 40 V 10 A 16 mΩ 13.6 nC

PROGRAMMING UVLO INPUT

The precision enable input can be used to program the UVLO

threshold and hysteresis of the input voltage as shown in Figure 46.

ENx

1.2V

EN CMP

4µA1µA

PVINx

TOP_EN

BOT_EN

09357-048

Figure 46. Programming UVLO Input

Use the following equation to calculate RTOP_EN and RBOT_EN:

μA1V2.1μA5V1.1

V2.1V1.1 __

_×−×

×−×

=FALLINGINRISINGIN

ENTOP

V2.1μ5

V2.1

−Α×−

ENTOP

RISINGIN

ENTOP

ENBOT

where:

VIN_RISING is the VIN rising threshold.

VIN_FALLING is the VIN falling threshold.

COMPENSATION COMPONENTS DESIGN

For peak current-mode control, the power stage can be

simplified as a voltage controlled current source supplying

current to the output capacitor and load resistor. It is composed of

one domain pole and a zero contributed by the output capacitor

ESR. The control-to-output transfer function is shown in the

following equations:













×π×













×π×

××==

COMP

OUT

)(

OUT

ESR

f××π×

( )

OUT

ESR

pCRR

f×+×π×

where:

AVI = 5 A/V

R is the load resistance.

COUT is the output capacitance.

ADP2323 Data Sheet

Rev. A | Page 22 of 32

RESR is the equivalent series resistance of the output capacitor.

The ADP2323 uses a transconductance amplifier for the error

amplifier to compensate the system. Figure 47 shows the

simplified peak current-mode control small signal circuit.

ESR

–

OUT

TOP

BOT

–

OUT

COMP

OUT

09357-049

Figure 47. Simplified Peak Current-Mode Control Small Signal Circuit

The compensation components, RC and CC, contribute a zero,

and the optional CCP and RC contribute an optional pole.

The closed-loop transfer equation is as follows:

)(

)( sG

CCR

sCR

CPC

CPCC

CPC

TOPBOT

BOT











×

××

+×

××+

−

The following design guideline shows how to select the

compensation components, RC, CC, and CCP, for ceramic output

capacitor applications.

1. Determine the cross frequency (fC). Generally, the fC is

between fSW/12 and fSW/6.

2. RC can be calculated using the following equation:

OUTOUT

CAg

fCV

R××

×××π×

=V6.0

3. Place the compensation zero at the domain pole (fP).

CC can be determined by

( )

OUT

ESR

CRR

C×+

4. CCP is optional. It can be used to cancel the zero caused by

the ESR of the output capacitor.

OUT

ESR

CP R

C×

The ADP2323 has a 10 pF capacitor internally at the

COMPx pin; therefore, if CCP is smaller than 10 pF, no

external capacitor is needed.

Data Sheet ADP2323

Rev. A | Page 23 of 32

DESIGN EXAMPLE

This section explains design procedure and component selection as

shown in Figure 50; Table 11 provides a list of the required

settings.

Table 11. Dual Step-Down DC-to-DC Regulator Requirements

Parameter Specification

Channel 1

Input Voltage V

IN1

= 12.0 V ± 10%

Output Voltage V

OUT1

= 1.2 V

Output Current I

OUT1

= 3 A

Output Voltage Ripple ΔV

OUT1_RIPPLE

= 12 mV

Load Transient

±5%, 0.5 A to 3A, 1 A/µs

Channel 2

Input Voltage V

IN2

= 12.0 V ± 10%

Output Voltage V

OUT2

= 3.3 V

Output Current I

OUT2

= 3 A

Output Voltage Ripple ΔV

OUT2_RIPPLE

= 33 mV

Load Transient ±5%, 0.5 A to 3 A, 1 A/µs

Switching Frequency f

= 500 kHz

OUTPUT VOLTAGE SETTING

Choose a 10 kΩ top feedback resistor (RTOP); calculate the bottom

feedback resistor by using the following equation:













−

×= 6.0

6.0

OUT

TOPBOT V

To set the output voltage to 1.2 V, the resistor values are RTOP1 = 10

kΩ and RBOT1 = 10 kΩ. To set the output voltage to 3.3 V, t h e

resistors values are RTOP2 = 10 kΩ and RBOT2 = 2.21 kΩ.

CURRENT-LIMIT SETTING

For 3 A output current operation, the typical peak current limit

is 4.8 A. In this case, no RILIM is required.

FREQUENCY SETTING

To set the switching frequency to 500 kHz, use the following

equation to calculate the resistor value, ROSC:

( ) ( )

kHz

000,60

kΩ

OSC f

Therefore, ROSC =100 kΩ.

INDUCTOR SELECTION

The peak-to-peak inductor ripple current, ΔIL, is set to 30% of

the maximum output current. Use the following equation to

estimate the value of the inductor:

( )

OUT

DVV

L×∆

×−

For VOUT1 = 1.2 V, Inductor L1 = 2.4 µH, and for VOUT2 = 3.3 V,

Inductor L2 = 5.3 µH.

Select the standard inductor value of 2.2 µH and 4.7 µH for the

1.2 V and 3.3 V rails.

Calculate the peak-to-peak inductor ripple current as follows:

( )

OUT

DVV

I×

×−

=∆

For VOUT1 = 1.2 V, Δ I L1 = 0.98 A. For VOUT2 = 3.3 V, Δ I L2 = 1.02 A.

Find the peak inductor current by using the following equation:

OUT

PEAK

II ∆

For the 1.2 V rail, the peak inductor current is 3.49 A, and for

the 3.3 V rail, the peak inductor current is 3.51 A.

The rms current through the inductor can be estimated by

OUT

RMS

II ∆

The rms current of the inductor for both 1.2 V and 3.3 V is

approximately 3.01 A.

For the 1.2 V rail, select an inductor with a minimum rms

current rating of 3.01 A and a minimum saturation current

rating of 3.49 A. For the 3.3 V rail, select an inductor with a

minimum rms current rating of 3.01 A and a minimum

saturation current rating of 3.51 A.

Based on these requirements, for the 1.2 V rail, select a 2.2 µH

inductor, such as the Sumida CDRH105RNP-2R2N, with a

DCR = 7.2 mΩ; for the 3.3 V rail, select a 4.7 µH inductor, such

as the Sumida CDRH105RNP-4R7N, with a DCR = 12.3 mΩ.

OUTPUT CAPACITOR SELECTION

The output capacitor is required to meet the output voltage

ripple and load transient requirement. To meet the output

voltage ripple requirement, use the following equation to

calculate the ESR and capacitance:

RIPPLEOUT

RIPPLEOUT Vf

_8∆××

∆

RIPPLEOUT

ESR I

∆

For VOUT1 = 1.2 V, C OUT_RIPPLE1 = 20 µF and RESR1 = 12 mΩ. For

VOUT2 = 3.3 V, C OUT_RIPPLE2 = 7.7 µF and RESR2 = 32 mΩ.

To meet the ±5% overshoot and undershoot requirement, use

the following equation to calculate the capacitance:

( )

OUTOVOUTOUT

STEP

OVOUT VVV

LIK

C−∆+

×∆×

( )

UVOUTOUT

STEP

UVOUT VVV

LIK

_2∆×−×

×∆×

For estimation purposes, use KOV = KUV = 2. For VOUT1 = 1.2 V, use

COUT_OV1 = 191 µF and COUT_UV1 = 21 µF. For VOUT2 = 3.3 V, use

COUT_OV2 = 54 µF and COUT_UV2 = 20 µF.

ADP2323 Data Sheet

Rev. A | Page 24 of 32

For the 1.2 V rail, the output capacitor ESR needs to be smaller

than 12 mΩ, and the output capacitance needs to be larger than

191 µF. It is recommend that three pieces of 100 µF/X5R/6.3 V

ceramic capacitor be used, such as the GRM32ER60J107ME20

from Murata, with an ESR = 2 mΩ.

For the 3.3 V rail, the ESR of the output capacitor must be

smaller than 32 mΩ and the output capacitance must be larger

than 54 µ F. It is recommended that two pieces of 47 µF/X5R/6.3

V ceramic capacitor be used, such as the Murata

GRM32ER60J476ME20, with an ESR = 2 mΩ.

LOW-SIDE MOSFET SELECTION

A low RDSON N-channel MOSFET is selected for high efficiency

solutions. The MOSFET breakdown voltage needs to be greater

than 1.2 V × VIN, and the drain current needs to be greater than

1.2 V × ILIMIT.

It is recommended that a 30 V, N-channel MOSFET be used, such as

the FDS8880 from Fairchild. The RDSON of the FDS8880 at a 4.5 V

driver voltage is 12 mΩ, and the total gate charge is 12 nC.

COMPENSATION COMPONENTS

For better load transient and stability performance, set the cross

frequency, fC, to fSW/10. In this case, fSW is running at 500 kHz;

therefore, the fC is set to 50 kHz.

For the 1.2 V rail, the 100 µF ceramic output capacitor has

a derated value of 64 µF.

kΩ4.80

A/V5μs300V6.0

kHz50μF643V2.12 =

××

××××π×

( )

pF957

kΩ4.80

μF643Ω001.0Ω4.0 =

××+

pF4.2

kΩ4.80

μF64

3Ω001.0 =

××

CP1

Choose standard components, RC1 = 82 kΩ and CC1 = 1000 pF. No

CCP1 is needed.

Figure 48 shows the 1.2 V rail bode plot at 3 A. The cross

frequency is 49 kHz and the phase margin is 59°.

–60

–48

–36

–24

–12

MAGNIT UDE ( dB)

–180

–144

–108

–72

–36

108

144

180

PHASE ( Degrees)

09357-148

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 48. Bode Plot for 1.2 V Rail

For the 3.3 V rail, the 47µF ceramic output capacitor has a

derated value of 32 µF.

kΩ7.73

A/V5μs300V6.0

kHz50μF322V3.32 =

××

××××π×

( )

pF956

kΩ7.73

μF322Ω001.0Ω1.1 =

××+

pF1

kΩ7.73

μF322Ω001.0 =

××

CP2

Choose standard component values of RC2 = 75 kΩ and

CC2 = 1000 pF. No CCP2 is needed.

Figure 49 shows the 3.3 V rail bode plot at 3 A. The cross

frequency is 59 kHz and phase margin is 61°.

–60

–48

–36

–24

–12

MAGNIT UDE ( dB)

–180

–144

–108

–72

–36

108

144

180

PHASE ( Degrees)

09357-149

1k 10k 100k 1M

FREQUENCY (Hz)

Figure 49. Bode Plot for 3.3 V Rail

SOFT START TIME PROGRAMMING

The soft start feature allows the output voltage to ramp up in a

controlled manner, eliminating output voltage overshoot during

soft start and limiting inrush current. The soft start time is set

to 3 ms.

nF5.17

V6.0

ms3μA5.3

V6.0 =

SSSS

Choose a standard component value of CSS1 = CSS2 = 22 nF.

INPUT CAPACITOR SELECTION

A minimum 10 µF ceramic capacitor is required, placed near

the PVINx pin. In this application, one piece of 10 µF, X5R, 25

V ceramic capacitor is recommended.

Data Sheet ADP2323

Rev. A | Page 25 of 32

EXTERNAL COMPONENTS RECOMMENDATION

Table 12. Recommended External Components for Typical Applications with 3 A Output Current

(kHz) V

(V) V

OUT

(V) L (µH) C

OUT

(µF)1 R

TOP

(kΩ) R

BOT

(kΩ) R

(kΩ) C

(pF) C

(pF)

300 12 1 3.3 330 10 15 62 1500 33

12 1.2 4.7 330 10 10 82 1500 22

12 1.5 4.7 330 15 10 100 1500 22

12 1.8 4.7 2 × 100 20 10 47 1500 4.7

12 2.5 6.8 100 + 47 47.5 15 47 1500 4.7

12 3.3 10 100 + 47 10 2.21 62 1500 3.3

12 5 10 100 22 3 62 1500 2.2

3.3

330

1500

5 1.2 3.3 330 10 10 82 1500 22

5 1.5 3.3 330 15 10 100 1500 22

5 1.8 4.7 2 × 100 20 10 47 1500 4.7

5 2.5 4.7 100 + 47 47.5 15 47 1500 4.7

3.3

4.7

100

2.21

1500

3.3

600 12 1.5 2.2 2 × 100 15 10 82 820 2.2

12 1.8 3.3 100 + 47 20 10 75 820 3.3

12 2.5 3.3 2 × 47 47.5 15 62 820 2.2

12 3.3 4.7 2 × 47 10 2.21 82 820 2.2

12 5 4.7 47 22 3 62 820 2.2

5 1 1.5 2 × 100 10 15 56 820 2.2

5 1.2 1.5 2 × 100 10 10 62 820 2.2

5 1.5 2.2 100 + 47 15 10 62 820 2.2

1.8

2.2

2 × 47

820

2.2

5 2.5 2.2 2 × 47 47.5 15 62 820 2.2

5 3.3 2.2 2 × 47 10 2.21 82 820 2.2

1000 12 1.8 1.5 100 20 10 82 470 2.2

12 2.5 2.2 47 47.5 15 56 470 2.2

12 3.3 2.2 47 10 2.21 68 470 2.2

12 5 3.3 47 22 3 100 470 2.2

5 1 1 2 × 100 10 15 82 470 2.2

5 1.2 1 100 + 47 10 10 82 470 2.2

5 1.5 1 2 × 47 15 10 68 470 2.2

5 1.8 1 2 × 47 20 10 82 470 2.2

5 2.5 1 47 47.5 15 56 470 2.2

5 3.3 1 47 10 2.21 62 470 2.2

1 330 µF: 6.3 V, Sanyo 6TPD330M; 100 µF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 µF: 6.3 V, X5R, Murata GRM32ER60J476ME20.

ADP2323 Data Sheet

Rev. A | Page 26 of 32

TYPICAL APPLICATION CIRCUITS

INTVCC

TOP1

10kΩ C

1000pF

82kΩ C

SS1

22nF

INT

1µF

DRV

1µF

IN1

10µF, 25V

BST1

0.1µF

BST2

0.1µF

2.2µH

FDS8880

4.7µH

12V

OUT1

1.2V, 3A

OUT1

100µF

OUT4

47µF

OUT2

3.3V, 3A

BOT1

10kΩ

TOP2

10kΩ

75kΩ

1000pF

SS2

22nF C

IN2

10µF, 25V

BOT2

2.21kΩ

OSC

120kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

MODE

SCFG

TRK2

TRK1

VDRV ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

OUT2

100µF

OUT5

47µF

OUT3

100µF

09357-050

Figure 50. Using External MOSFET Application, VIN1 = VIN2 = 12 V, VOUT1 = 1.2 V, IOUT1 = 3 A, VOUT2 = 3.3 V, IOUT2 = 3 A, fSW = 500 kHz

INTVCC

TOP1

22kΩ C

1.2nF

75kΩ C

SS1

22nF

INT

1µF

DRV

1µF

IN1

10µF, 25V

BST1

0.1µF

BST2

0.1µF

8.2µH

B220A

8.2µH

12V

OUT1

5V, 2A

OUT1

22µF

OUT3

22µF

OUT2

3.3V, 1.5A

BOT1

3kΩ

TOP2

10kΩ

47kΩ

1.5nF

SS2

22nF C

IN2

10µF, 25V

BOT2

2.21kΩ

OSC

100kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

SCFG

TRK2

TRK1

VDRV ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

MODE

OUT2

22µF

ILIM2

47kΩ

OUT4

22µF

09357-051

Figure 51. Using External Diode Application, VIN1 = VIN2 = 12 V, VOUT1 = 5 V, IOUT1 = 2 A, VOUT2 = 3.3 V, IOUT2 = 1.5 A, fSW = 600 kHz

Data Sheet ADP2323

Rev. A | Page 27 of 32

TRK1

RTOP1

20kΩCC1

470pF

RC1

150kΩ

ROK1

100kΩ

ROSC

100kΩ

CSS1

22nF

CINT

1µF

CIN1

10µF, 25V

CBST1

0.1µF

CBST2

0.1µF

1µH

FDS8880

1µH

VIN

12V

VIN

12V

VOUT1

1.8V, 6A

COUT1

100µF

RBOT1

10kΩ

CIN2

10µF, 25V

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

PGOOD1

SCFG

SYNC

INTVCC ADP2323

MODE

PGOOD2

TRK2

GND

SW1

SW2

DL1

PGND

DL2

SW2

VDRV

PVIN1

COUT2

100µF

COUT3

100µF

ROK2

100kΩ

CDRV

1µF

09357-052

Figure 52. Parallel Single Output Application, VIN = 12 V, VOUT = 1.8 V, IOUT = 6 A, fSW = 600 kHz

INTVCC

TOP1

22kΩC

390pF

62kΩ

SS1

22nF

INT

1µF

DRV

1µF

IN1

10µF, 25V

BST1

0.1µF

BST2

0.1µF

3.3µH

1µH

12V

OUT1

5V, 2A

OUT2

100µF

OUT2

1.0V, 3A

BOT1

3kΩ

TOP2

10kΩ

82kΩ

390pF

SS2

22nF

IN2

10µF, 25V

BOT2

15kΩ

OSC

50kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

MODE

SCFG

TRK2

TRK1

VDRV

ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

OUT1

22µF

OUT3

100µF

FDS6898A

09357-053

Figure 53. Cascading Supply Application, VIN1 = 12 V, VOUT1 = 5 V, IOUT1 = 2 A, VOUT2 = 1 V, IOUT2 = 3 A, fSW = 1.2 MHz

ADP2323 Data Sheet

Rev. A | Page 28 of 32

INTVCC

TOP1

20kΩ C

820pF

75kΩ C

SS1

22nF

INT1

1µF

DRV1

1µF

IN1

10µF, 25V

BST1

0.1µF

BST2

0.1µF

3.3µH

FDS8880

4.7µH

12V

OUT1

1.8V, 3A

OUT1

100µF

OUT3

47µF

OUT2

3.3V, 3A

BOT1

10kΩ

TOP2

10kΩ

82kΩ

820pF

SS2

22nF C

IN2

10µF, 25V

BOT2

2.21kΩ

OSC1

100kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

MODE

SCFG

TRK2

TRK1

VDRV

ADP2323

GND

PGOOD2

PGOOD1

SW1

DL1

PGND

DL2

SW2

COUT2

47µF

COUT4

47µF

INTVCC

SYNC

RTOP3

20kΩ CC3

820pF

RC3

75kΩ CSS3

22nF

CINT2

1µF

CDRV2

1µF

CIN1

10µF, 25V

CBST3

0.1µF

CBST4

0.1µF

3.3µH

FDS8880

4.7µH

VIN

12V

VIN

12V

VOUT3

1.8V, 3A

COUT5

100µF

COUT7

47µF

VOUT4

3.3V, 3A

RBOT3

10kΩ

RTOP4

10kΩ

RC4

82kΩ

CC4

820pF

CSS4

22nF CIN4

10µF, 25V

RBOT4

2.21kΩ

ROSC2

120kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

MODE

SCFG

TRK2

TRK1

VDRV

ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

COUT6

47µF

COUT8

47µF

09357-054

Figure 54. Synchronization with 90° Phase Shift Between Each Channel

Data Sheet ADP2323

Rev. A | Page 29 of 32

INTVCC

RTOP1

15kΩ CC1

820pF

RC1

68kΩ CSS1

22nF

CINT

1µF

CDRV

1µF

CIN1

10µF, 25V

CBST1

0.1µF

CBST2

0.1µF

2.2µH

FDS8880

3.3µH

VIN

VOUT1

1.5V, 3A

COUT1

47µF

COUT4

47µF

VOUT2

2.5V, 3A

RBOT1

10kΩ

RTOP2

47.5kΩ

RC2

75kΩ

CC2

820pF

CSS2

22nF CIN2

10µF, 25V

RBOT2

15kΩ

ROSC

100kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

SCFG

TRK2

TRK1

VDRV

ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

MODE

COUT2

47µF

COUT5

47µF

COUT3

47µF

09357-055

Figure 55. Enable PFM Mode with MODE Pin Pulled to GND, VIN1 = VIN2 = 9 V, VOUT1 = 1.5 V, IOUT1 = 3 A, VOUT2 = 2.5 V, IOUT2 = 3 A, fSW = 600 kHz

INTVCC

RTOP1

10kΩ CC1

1500pF

RC1

100kΩ CSS1

22nF

CINT

1µF

CDRV

1µF

CIN1

10µF, 25V

CBST1

0.1µF

CBST2

0.1µF

8.2µH

FDS8880

5.6µH

VIN

12V

VIN

12V

VOUT1

3.3V, 3A

COUT1

100µF

COUT3

100µF

VOUT2

1.8V, 3A

RBOT1

2.21kΩ

REN_BOT

68kΩ

REN_TOP

330kΩ

RTOP2

20kΩ

RC2

51kΩ

CC2

1500pF

CSS2

22nF CIN2

10µF, 25V

RBOT2

10kΩ

ROSC

200kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

MODE

SCFG

TRK2

TRK1

VDRV

ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

RPGOOD1

100kΩ

COUT2

100µF

COUT4

100µF

09357-056

Figure 56. Programmable VIN_RISING = 8.7 V, VIN_FALLING = 6.7 V, 3.3 V Start Up Before 1.8 V,

VIN1 = VIN2 = 12 V, VOUT1 = 3.3 V, IOUT1 = 3 A, VOUT2 = 1.8 V, IOUT2 = 3 A, fSW = 300 kHz

ADP2323 Data Sheet

Rev. A | Page 30 of 32

INTVCC

RTOP1

47.5kΩ CC1

1000pF

RC1

68kΩ CSS1

22nF

CINT

1µF

CDRV

1µF

CIN1

10µF, 25V

CBST1

0.1µF

CBST2

0.1µF

4.7µH

FDS8880

2.2µH

VIN

12V

VIN

12V

VOUT1

2.5V, 3A

COUT1

47µF

COUT3

100µF

VOUT2

1.25V, 3A

RBOT1

15kΩ

RTRK_TOP

47.5kΩ

RTRK_BOT

15kΩ

RTOP2

13kΩ

RC2

58kΩ

CC2

1000pF

CSS2

10nF CIN2

10µF, 25V

RBOT2

12kΩ

ROSC

120kΩ

FB1

COMP1

SS1

EN1

PVIN1

BST1

FB2

COMP2

SS2

EN2

PVIN2

BST2

TRK2

MODE

SCFG

VDRV

ADP2323

GND

PGOOD2

PGOOD1

SYNC

SW1

DL1

PGND

DL2

SW2

TRK2

COUT2

47µF

COUT4

100µF

09357-057

Figure 57. Channel 2 Tracking with Channel 1

VIN1 = VIN2 = 12 V, VOUT1 = 2.5 V, IOUT1 = 3 A, VOUT2 = 1.25 V, IOUT2 = 3 A, fSW = 500 kHz

Data Sheet ADP2323

Rev. A | Page 31 of 32

OUTLINE DIMENSIONS

COM P LIANT T O JEDE C S TANDARDS M O-220- WHHD.

112408-A

0.50

BSC

BOTTOM VIEWTOP VI EW

PI N 1

INDICATOR

EXPOSED

PAD

PI N 1

INDICATOR

3.25

3.10 S Q

2.95

SEATING

PLANE

0.05 M AX

0.02 NOM

0.20 RE F

COPLANARITY

0.08

0.30

0.25

0.18

5.10

5.00 S Q

4.90

0.80

0.75

0.70

FOR PRO P E R CONNECTI ON O F

THE EXPOSED PAD, REFER TO

THE P IN CONFI GURAT IO N AND

FUNCTION DES CRIPTI ONS

SECTION OF THIS DATA SHEET.

0.50

0.40

0.30

0.25 M IN

Figure 58. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad

(CP-32-7)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Output Voltage Package Description Package Option

ADP2323ACPZ-R7 −40°C to +125°C Adjustable 32-Lead LFCSP_WQ CP-32-7

ADP2323-EVALZ Evaluation Board

1 Z = RoHS Compliant Part.

ADP2323 Data Sheet

Rev. A | Page 32 of 32

NOTES

registered trademarks are the property of their respective owners.

D09357-0-6/12(A)

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Analog Devices Inc.:

ADP2323ACPZ-R7 ADP2323-EVALZ