88AP303-A1-BGF2C624-TN22 - Marvell Semiconductor, Inc.

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Doc. No. MV-S105156-00, Rev. 2.0 Version -

April 6, 2009 Released

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Marvell® PXA3xx

(88AP3xx) Processor

Family

Electrical, Mechanical, and Thermal

Functional Specification

PXA30x Processor (88AP300, 88AP301, 88AP302, 88AP303)

PXA31x Processor (88AP310, 88AP311, 88AP312)

PXA32x Processor (88AP320, 88AP322)

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PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

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CONTENTS

1 Introduction..................................................................................................................................11

1.1 Product Summary ...........................................................................................................................................11

1.2 Document Purpose .........................................................................................................................................12

1.3 Number Representation..................................................................................................................................12

1.4 Naming Conventions.......................................................................................................................................12

1.5 Applicable Documents ....................................................................................................................................12

2 Functional Overview ...................................................................................................................15

3 Package Information ...................................................................................................................19

3.1 Introduction .....................................................................................................................................................19

3.2 Packaging Materials........................................................................................................................................19

3.3 PXA32x Processor Packaging Views..............................................................................................................19

3.3.1 PXA32x Processor 456-Ball VF-BGA Package................................................................................19

3.3.2 PXA320 Processor Detailed Package Dimensions ..........................................................................22

3.3.3 PXA322 Processor Pac kage-o n-Pac k age (PoP)... ..... ...... ..... ................. ...... ..... ...... ...... ..... ..............23

3.3.4 PXA322 Processor Detai le d 15mm2 POP Dimens ion s.... ................. ..... ...... ..... ...... ................. ..... ...28

3.4 PXA31x and PXA30x Processor Package Views............................................................................................28

3.4.1 PXA301 Processor and PXA311 Processor Multi-Chip Package (MCP)..........................................28

3.4.2 PXA301 Processor and PXA311 Processor Detailed MCP Package Dimensions...........................32

3.4.3 PXA302 and PXA312 Processor Package-on-Package (PoP).........................................................32

3.4.4 PXA302 Processor and PXA312 Processor Detailed 15mm2 POP Dimensions..............................36

3.4.5 PXA300 Processor and PXA310 Processor Discrete Package (VF-BGA).......................................36

3.5 PXA30x Processor Package Views ................................................................................................................40

3.5.1 PXA303 Processor 19m m2 Disc rete Pac kage (VF-BG A)...... ...... ................. ..... ...... ...... ..... ...... ........40

3.5.2 PXA303 Processor Detailed VF-BGA Package Dimensions............................................................ 43

3.6 PXA3xx Processor Family Markings...............................................................................................................44

3.6.1 PXA32x Processor Markings............................................................................................................45

4 Pin Listing and Signal Definitions .............................................................................................49

4.1 Ball Map View ................... ...... ..... ...... ................. ..... ...... ...... ..... ................. ...... ..... ...... .. ..................................49

4.1.1 PXA32x Processor Ball Maps...........................................................................................................49

4.1.2 PXA31x Processor Ball Maps...........................................................................................................56

4.1.3 PXA30x Processor Ball Maps...........................................................................................................60

4.1.4 PXA30x Processor and PXA302 Processor 15mm2 Multi-Chip Package (MCP) and Package on

Package (POP) Bottom Ball Map63

4.1.5 PXA303 Processor 19m m2 VF-BGA Ball.................................... ...... ..... ...... ..... ................. ...... ..... ...64

4.1.6 PXA312 and PXA302 Package on Package (POP) Top Ball Maps ................................................. 67

4.2 Pin Use Tables................................................................................................................................................68

4.2.1 PXA32x Processor Pin Use..............................................................................................................69

4.2.2 PXA31x Processor Pin Use..............................................................................................................87

4.2.3 PXA30x Processor Pin Use............................................................................................................104

4.2.4 Signal Type Definitions...................................................................................................................126

5 Maximum Ratings and Operation Conditions.........................................................................127

5.1 Absolute Maximum Ratings ..........................................................................................................................127

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Electrical, Mechanical, and Thermal Functional Specification

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5.2 Operati ng Cond itio ns .. ...... ...... ..... ...... ................. ..... ...... ...... ................ ...... ...... ..... ...... ..................................128

6 Electrical Specifications ...........................................................................................................135

6.1 DC Voltage and Current Characteristics.......................................................................................................135

6.2 Oscillator Electrical Specifications.................................................................................................................138

6.2.1 32.768 kHz Os ci lla tor Specifi ca tio ns ..................... ................ ...... ...... ..... ................. ...... ..... .... ........138

6.2.2 13.000 MHz Oscillator Specifications .............................................................................................139

6.2.3 Clock Outputs.................................................................................................................................140

7 AC Characteristics ....................................................................................................................143

7.1 External Memory Pin Interface (EMPI) Memory Timings..............................................................................143

7.1.1 DDR SDRAM Timing Diagrams and Specifications........................................................................144

7.2 Data-Flash Interface (DFI) Memory Timing Specifications............................................................................146

7.2.1 Variable Latency I/O (VLIO) Timing Diagrams and Specifications.................................................147

7.2.2 Flash Memory Timing Diagrams and Specifications.......................................................................152

7.2.3 SRAM Timing Diagrams and Specifications...................................................................................159

7.2.4 Compact Flash Timing Diagrams and Specifications.....................................................................165

7.2.5 NAND Timing Diagrams and Specifications...................................................................................168

7.3 Quick Capture Camera Interface Timing Diagrams and Specifications........................................................173

7.3.1 Master-Parallel Timing....................................................................................................................173

7.3.2 Master-Parallel Interface Timing Specifications..............................................................................173

7.3.3 Slave-Parallel Timing......................................................................................................................174

7.3.4 Slave-Parallel Interface Timing Parameters...................................................................................175

7.4 LCD Timing Diagrams and Specifications.....................................................................................................175

7.4.1 LCD Passive Tim ing....................... ...... ..... ...... ................. ..... ...... ...... ..... ................. ...... .. ...............175

7.4.2 LCD Active Panel Timing................................................................................................................177

7.4.3 LCD Smart Panel Timin g...................... ..... ...... ...... ..... ................. ...... ..... ...... ..... .............................179

7.5 SSP Timing Diagrams and Specifications.....................................................................................................181

7.5.1 SSP Slave Mode Timing.................................................................................................................1 82

7.5.2 SSP Mixed Mode Timing - Processor Master to Clock ..................................................................183

7.5.3 SSP Mixed Mode Timing - Processor Master to Frame .................................................................184

7.6 AC ’97 Timing Diagrams and Specifications.................................................................................................184

7.7 USB 2.0 Timing Diagrams and Specifications (PXA32x and PXA30x only)..................................................185

7.8 MultiMedia Card Timing Diagrams and Specifications..................................................................................186

7.9 Secure Digital (SD/SDIO) Timing Diagrams and Specifications...................................................................187

7.10 JTAG Boundary Scan Timing Diagrams and Specifications.........................................................................188

8 Power and Reset Specifications ..............................................................................................191

8.1 Power Up Timings.........................................................................................................................................191

8.2 Powerdown Timings......................................................................................................................................192

8.2.1 S2/D3/C4 Mode Timings.................................................................................................................192

8.2.2 S3/D4/C4 Mode Timings.................................................................................................................194

8.3 Reset Timing.................................................................................................................................................196

8.3.1 Hardware Reset Timing..................................................................................................................196

8.3.2 Watchdog Reset Timing .................................................................................................................196

8.3.3 GPIO Reset Timing.........................................................................................................................196

8.4 Power Consumption......................................................................................................................................197

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FIGURES

Figure 1: PXA32x Processor Block Diagram ...................................................................................................16

Figure 2: PXA31x Processor Block Diagram ...................................................................................................17

Figure 3: PXA30x Processor Block Diagram ...................................................................................................18

Figure 4: PXA320 Processor 14x14 mm VF-BGA Package, Top View...........................................................20

Figure 5: PXA320 Processor 14x14 mm VF-BGA Package, Bottom View......................................................21

Figure 6: PXA320 Processor 14x14 mm VF-BGA Package, Side View..........................................................22

Figure 7: 14x14mm VF-BGA Daisy-Chain Substrate Diagram........................................................................22

Figure 8: PXA322 Processor 15-mm2 PoP Package, Top View .....................................................................24

Figure 9: PXA322 Processor 15-mm2 PoP Package, Bottom View................................................................25

Figure 10: PXA322 Processor 15-mm2 PoP Package, Side View ....................................................................26

Figure 11: PXA322 15-mm2 PoP Daisy-Chain Substrate Diagram...................................................................27

Figure 12: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Top View..............................29

Figure 13: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Bottom View.........................30

Figure 14: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Side View.............................31

Figure 15: PXA301 Processor and PXA311 Processor 15-mm2 MCP Daisy-Chain Substrate Diagram ..........31

Figure 16: PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Top View...............................33

Figure 17: PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Bottom View..........................34

Figure 18: PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Side View..............................35

Figure 19: PXA302 Processor and PXA312 Processor 15-mm2 PoP Daisy-Chain Substrate Diagram............35

Figure 20: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package, Top View.........................37

Figure 21: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package, Bottom View...................38

Figure 23: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Daisy-Chain Substrate Diagram.....39

Figure 22: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package, Side View........................39

Figure 24: PXA303 Processor 19-mm2 VF-BGA Package, Top View...............................................................41

Figure 25: PXA303 Processor 19-mm2 VF-BGA Package, Bottom View..........................................................42

Figure 26: PXA303 Processor 19-mm2 VF-BGA Package, Side View..............................................................42

Figure 27: PXA303 Processor 19-mm2 VF-BGA Daisy-Chain Substrate Diagram ...........................................43

Figure 28: PX3xx (88AP3xx) Processor Family Product Marking Information...................................................45

Figure 29: PXA32x Processor VF-BGA Product Information Decoder .............................................................46

Figure 30: PXA32x Processor Configuration Line Decoding.............................................................................46

Figure 34: PXA320 Processor 14mm2 VF-BGA Ball Map, Left Half..................................................................50

Figure 35: PXA320 Processor 14mm2 VF-BGA Ball Map, Right Half...............................................................51

Figure 40: PXA310 Processor 13mm2 VF-BGA Ball Map, Left side..................................................................57

Figure 41: PXA310 Processor 13mm2 VF-BGA Ball Map, Right side...............................................................58

Figure 42: PXA31x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map, Left side.....59

Figure 43: PXA31x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map, Right

side...................................................................................................................................................60

Figure 44: PXA300 Processor 13mm2 VF-BGA Ball Map, Left side..................................................................61

Figure 45: PXA300 Processor 13mm2 VF-BGA Ball Map, Right side...............................................................62

Figure 46: PXA30x 15mm2 MCP and Package-on-Package (PoP) Bottom Ball Map, Left side.......................63

Figure 47: PXA30x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map, Right

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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side...................................................................................................................................................64

Figure 48: PXA303 Processor 19mm2 VF-BGA Ball Map, Left side..................................................................65

Figure 49: PXA303 Processor 19mm2 VF-BGA Ball Map, Right side...............................................................66

Figure 50: PXA302 Processor and PXA312 Processor PoP Top Ball Map, Left Side.......................................67

Figure 52: DDR SDRAM Timing Diagrams......................................................................................................144

Figure 53: MD<31:0> to DQS Write Skew.......................................................................................................144

Figure 54: CLK to Address/Command Write Skew..........................................................................................144

Figure 55: DQS to CLK Write Skew.................................................................................................................145

Figure 56: MD<31:0> to DQS Read Skew.......................................................................................................145

Figure 57: VLIO Read Timing Diagram............................................................................................................147

Figure 58: VLIO Read Timing Diagram (Latched Addressing Mode)...............................................................148

Figure 59: VLIO Low Order Addressing Read Timing Diagram.......................................................................148

Figure 60: VLIO Low Order Addressing Read Timing Diagram (Latched Addressing Mode)..........................149

Figure 61: VLIO Write Timing Diagram............................................................................................................149

Figure 62: VLIO Write Timing Diagram (Latched Addressing Mode)...............................................................150

Figure 63: VLIO Low Order Addressing Write Timing Diagram.......................................................................150

Figure 64: VLIO Low Order Addressing Write Timing Diagram (Latched Addressing Mode)..........................1 51

Figure 65: Flash Asynchronous Read Timing Diagram...................................................................................153

Figure 66: Flash Asynchronous Read Timing Diagram (Latched Addressing Mode)......................................153

Figure 67: Flash Asynchronous Low-Order Read Timing Diagram .................................................................154

Figure 68: Flash Asynchronous Low-Order Read Timing Diagram (Latched Addressing Mode)....................154

Figure 69: Flash Synchronous Read Timing Diagram.....................................................................................155

Figure 70: Flash Synchronous Read Timing Diagram (Latched Addressing Mode)........................................155

Figure 71: Flash Asynchronous Write Timing Diagrams..................................................................................156

Figure 72: Flash Asynchronous Write Timing Diagrams (Latched Addressing Mode).....................................156

Figure 73: Flash Asynchronous Low-Order Addressing Write Timing Diagrams............................................. 1 57

Figure 74: Flash Asynchronous Low-Order Addressing Write Cycle Timing Diagram.....................................1 57

Figure 75: Synchronous Write Timings Diagrams............................................................................................158

Figure 76: Synchronous Write Timings Diagrams (Latched Addressing Mode) ..............................................158

Figure 77: SRAM Asynchronous Read Timing Diagram..................................................................................160

Figure 78: SRAM Asynchronous Read Timing Diagram (Latched Addressing Mode).....................................160

Figure 79: SRAM Asynchronous Low-Order Addressing Read Timing Diagram.............................................161

Figure 80: SRAM Asynchronous Read Timing Diagram (Non-AA/D Addressing Mode).................................161

Figure 81: SRAM Asynchronous Write Timing Diagram..................................................................................162

Figure 82: SRAM Asynchronous Write Timing Diagram (Latched Addressing Mode).....................................162

Figure 83: SRAM Asynchronous Low-Order Addressing Write Timing Diagram.............................................163

Figure 84: SRAM Asynchronous Low-Order Addressing Write Timing Diagram (Latched Addressing

Mode)..............................................................................................................................................163

Figure 85: Compact Flash 16-Bit Common Memory Read Timing Diagram....................................................165

Figure 86: Compact Flash 16-Bit Common Memory Write Timing Diagram.................................................... 1 66

Figure 87: Compact Flash 16-Bit I/O Memory Read Timing Diagram..............................................................166

Figure 88: Compact Flash 8-Bit I/O Space Write Timing Diagram...................................................................167

Figure 89: NAND Flash Program Timing Diagram...........................................................................................168

Figure 90: NAND Flash Erase Timing Diagram...............................................................................................169

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Figure 91: NAND Flash Small Block Read Timing Diagram............................................................................169

Figure 92: NAND Flash Large Block Read Timing Diagram............................................................................170

Figure 93: NAND Flash Status Read Timing Diagram.....................................................................................170

Figure 94: NAND Flash ID Read Timing Diagram ...........................................................................................171

Figure 95: NAND Flash Reset Timing Diagram............................................................................................... 1 71

Figure 96: Camera Master-Parallel Timing Diagram........................................................................................173

Figure 97: Camera Slave-Parallel Timing Diagram..........................................................................................175

Figure 98: LCD Passive Panel Synchronous Timing Diagram.........................................................................176

Figure 99: LCD Passive Panel Data Timing Diagram......................................................................................176

Figure 100: LCD Active Panel Timing Diagram.................................................................................................178

Figure 101: LCD Active Panel Timing Diagram.................................................................................................178

Figure 102: LCD Smart Panel Timing Diagram .................................................................................................180

Figure 103: SSP Master Mode Timing Diagram ................................................................................................181

Figure 104: SSP Slave Mode Timing Definitions...............................................................................................182

Figure 105: SSP Mixed Mode, Processor Master to Clock Timing Definitions..................................................183

Figure 106: SSP Mixed Mode, Processor Master to Frame Timing Definitions.................................................184

Figure 107: AC ’97 CODEC Timing Diagram.....................................................................................................185

Figure 108: USB 2.0 Timing Diagram................................................................................................................185

Figure 109: MultiMedia Card Timing Diagrams..................................................................................................186

Figure 110: SD/SDIO Timing Diagrams.............................................................................................................187

Figure 111: JTAG Boundary-Scan Timing Diagram ..........................................................................................189

Figure 112: Power Up Reset Timing..................................................................................................................191

Figure 113: S2/D3/C4 Timing ............................................................................................................................193

Figure 114: S3/D4/C4 Timing ............................................................................................................................194

Figure 115: GPIO Reset Timing.........................................................................................................................197

Figure 116: Diagram Showing Steps for Putting PXA30x Processor and PXA31x Processor into High-Z........202

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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TABLES

Table 1: Supplemental Documentation...........................................................................................................13

Table 2: Package Materials............................................................................................................................19

Table 3: PXA320 Processor 14x14 mm VF-BGA Package Dimensions.........................................................23

Table 4: PXA322 Processor 15-mm2 POP Dimensions.................................................................................28

Table 5: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package Dimensions...........................32

Table 6: PXA302 Processor and PXA312 Processor 15-mm2 POP Dimensions...........................................36

Table 7: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package Dimensions...................... 40

Table 8: PXA303 Processor 19-mm2 VF-BGA Package Dimensions............................................................ 44

Table 9: PXA32x Processor Pin Usage Summary......................................................................................................... 69

Table 10: PXA31x Processor Pin Usage Summary..........................................................................................87

Table 11: PXA30x Pin Usage Summary.........................................................................................................104

Table 12: Signal Types...................................................................................................................................126

Table 13: Absolute Maximum Ratings............................................................................................................127

Table 14: Voltage, Temperature, and Frequency Electrical Specifications ....................................................128

Table 15: DDR Input, Output, and I/O Pins AC/DC Operating Conditions......................................................135

Table 16: MFP Input, Output, and I/O Pins DC Operating Conditions............................................................136

Table 17: Typical 32.768 kHz Crystal Requirements 1...................................................................................138

Table 18: Typical External 32.768 kHz Oscillator Requirements...................................................................138

Table 19: Typical 13.000 MHz Crystal Requirements.....................................................................................139

Table 20: Typical External 13.000 MHz Oscillator Requirements...................................................................140

Table 21: CLK_POUT Specifications..............................................................................................................140

Table 22: CLK_TOUT Specifications..............................................................................................................141

Table 23: Standard Input, Output, and I/O-Pin AC Operating Conditions ......................................................143

Table 24: DDR Timing Specifications.............................................................................................................145

Table 25: VLIO Timing Specifications.............................................................................................................151

Table 26: DFI Flash Timing Specifications .....................................................................................................158

Table 27: DFI SRAM Timing Specifications....................................................................................................164

Table 28: Compact Flash Timing Specifications.............................................................................................167

Table 29: NAND Flash Interface Program Timing Specifications...................................................................171

Table 30: Master-Parallel Timing Specifications (PXA32x Processor and PXA30x Processor Only).............173

Table 31: Master-Parallel Timing Specifications (PXA31x Processor Only)...................................................174

Table 32: Slave-Parallel Timing Specifications...............................................................................................175

Table 33: LCD Passive Panel Timing Specifications......................................................................................176

Table 34: LCD Active Panel Timing Specifications.........................................................................................178

Table 35: LCD Smart Panel Timing Specifications.........................................................................................180

Table 36: SSP Master Mode Timing Specifications........................................................................................181

Table 37: SSP Slave Mode Timing Specifications..........................................................................................182

Table 38: SSP Mixed Mode, Processor Master to Clock Timing Specifications.............................................183

Table 39: SSP Mixed Mode, Processor Master to Frame Timing Specifications............................................184

Table 40: AC ’97 CODEC Timing Specifications............................................................................................185

Table 41: USB 2.0 Timing Specifications .......................................................................................................186

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Table 42: MultiMedia Card Timing Specifications...........................................................................................186

Table 43: SD/SDIO Timing Specifications......................................................................................................188

Table 44: Boundary Scan Timing Specifications............................................................................................189

Table 45: Power Up Timing Specifications.....................................................................................................192

Table 46: S2/D3/C4 Timing Specifications.....................................................................................................193

Table 47: S3/D4/C4 (Deep Sleep) Timing Specifications...............................................................................195

Table 48: GPIO Reset Timing Specifications .................................................................................................197

Table 49: PXA32x Processor Power-Consumption Specifications1...............................................................1 97

Table 50: PXA31x Processor Power-Consumption Specifications1...............................................................1 98

Table 51: PXA30x Processor Power-Consumption Specifications1...............................................................1 99

Table 52: Abbreviations Used in Table 53......................................................................................................203

Table 53: Required Balls for Programming the Package Flash Memory........................................................204

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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1Introduction

The Marvell PXA3xx Processor Family is a system-on-chip based on XScale® microarchitecture1

that incorporates the late st M arv ell adv an ces in m ob ile tec hno logy over its predeces so r, the Ma rve ll

PXA27x Processor Family. The PXA32x processor, PXA31x processor, and PXA30x processor

provide high-performance multimedia, low-power capabilities, and rich peripheral integration. The

PXA3xx Processor Family (referred throughout this document as “the processor” for simplicity)

provide enhanced features compared to the PXA27x Processor Family, and are the first Marvell

applications processors to integrate a hardware video accelerator unit. The PXA3xx Processor

Family redefines scalability by operating up to 806 MHz, providing high performance at low power

for many demanding mobile applications and markets such as multimedia-enabled cellular phones,

personal digital assistants (PDA), and embedded devices.

The PXA3xx Processor Family includes Intel® Wirele ss MMX™ 2 technology, enabling

high-perf orm anc e, low -p ower multimedia acce lera tio n wit h a genera l-pu rpos e ins truc tio n set.

Marvell® Quick Capture Interface technology provides a flexible and powerful camera interface for

capturin g digi tal still a nd vid eo images . Whil e perform ance is a key featu re in the PXA3xx Proce ssor

Family, power consumption is also a critical component. Marvell® Scalable Power Manager

technology helps enable low-power consumption with sophisticated power management

capabilities.

1.1 Product Summary

The following table describes the basic features of the processor:

1. XScale is a trademark or registered trademark of Intel Corporation and its subsidiaries in the United States and other

countries.

High-p er fo rm ance processor :

• XScale® micr oar chitect ur e w i th

Intel® Wirele s s MMX™ 2 media

enhancemen t technolo gy

• 7-8 stage pip el ine

• 32 Kby te s i nst ruction cache

• 32 Kby te s data cache

• 2 Kbytes “mi ni ” da ta cache

• Extensive data buffering

Up to 768 Kbytes of internal S RAM

for high sp eed code or data s to ra ge

preser ved during low- power states

Ric h serial peripher al set :

• AC ’97 audio port

• USB v. 2.0 client controller

• USB v. 1.1 client controller

• Up t o 3 USB v. 1. 1 h os t c ont ro ll er

• USB on-t he-go controlle r

• Three hi gh-spee d UA RTs with

hardware flow control

• SIR and C onsume r IR infr ar ed

communi cations ports

Hardware debug features — IEEE

JTAG interface with boundary scan

Hardw ar e per f or m ance-monitoring

features with on-chip trace buffer

Real-ti m e cl ock

Operating-system timers

LCD controller

Quick Capture Interface Controller

Low power:

• Dynami c v ol tage ma nagemen t

support

• Less than 500 mW typical i nternal

power dissi pat io n

• Core supply voltage may be

reduced to 0.95 V

• Five low-power modes

High-perf or manc e memory controller:

• Mobile DDR SDRAM interface

• EMPI an d D ata Flas h i nter fa ce

• Up to four static chip selects

• Companion-chip i nter f ace

Mini-LCD controller

Two Universal Subscriber Identity

Module (USIM) interface

Flexible cl ocking:

• CPU clock from 104 to 806 MHz

• Flexib l e memor y clock ratios

• Frequency change capability

• Functional clock gating

Additio nal peripher al s f or system

connectivity:

• SD/SDIO/MMC Controller (with

SPI mod e su pport)

• Four SSP contr ollers

•Two I

2C contro ller s ( one targeted

for PMIC control)

• Four pulse-w i dth modulators

(PWMs)

• Keypad int er fa ce wit h both dire ct

and matrix keys, rotary encoder

support

• Most per ip heral pins double as

GPIOs

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 12 April 6, 2009 Released

1.2 Document Purpose

This document constitutes the electrical, mechanical, and thermal specifications for the PXA3xx

Processor Family. It contains a functional overview, mechanical data, package signal locations,

targeted ele ctr ica l s pe ci fic ati ons , a nd func ti ona l b us w ave form s . Fo r de t ai led fun cti on al d es cri pti ons

other than parametric performance, refer to the PXA3x x Proces sor Family Devel ope rs Manua l (fou r

volumes).

1.3 Number Representation

All numbers in this document are decimal (base 10) unless designated otherwise. Hexadecimal

numbers have a prefix of 0x, and binary numbers have a prefix of 0b. For example, 107 is

represented as 0x6B in hexadecimal and 0b110_1011 in binary.

1.4 Naming Conventions

All signal and register-bit names appear in uppercase. Active low items are prefixed with a

lowercase “n”.

Pins within a signal name are enclosed in angle brackets:

EXTERNAL_ADDRESS<31:0>

nCS<1>

Bits within a register bit field are enclosed in square brackets:

REGISTER_BITFIELD[3:0]

REGISTER_BIT[0]

Single-bit items have either of two states:

Clear — the item contains the value 0b0.

Set — the item contains the value 0b1.

1.5 Applicable Documents

Table 1 lists supplemental information sources for the PXA30x and PXA31x processor. Contact a

Marvell representative for the latest document revisions and ordering instructions.

Note

This document may contain shortened references to the “PXA32x/PXA31x/PXA30x

processor” or “the processor” in some chapters. Where differences exist among or

between PXA3xx processors, they are called out individually.

Note

The PXA3xx Processor Family consists of the following product SKUs:

PXA30x: 88AP300, 88AP301, 88AP302, 88AP303

PXA31x: 88AP311, 88AP312

PXA32x: 88AP320, 88AP322

These product SKUs are not referenced in this version of the EMTS.

Version -

April 6, 2009 Released Page 13

Table 1: Supplemental Documentation

Document Title

PXA3xx Pro ces sor Family Vol. I: System a nd Timer Conf igur at io n Developer s M anual

PXA3xx Pro ces sor Family Vol. II: Memory C ont r olle r Configurat i on Developer s M anual

PXA3xx Pro cessor Fam ily Vol. III: Graph ic s an d In put C on trol l er C onfi guration D evelopers Ma nual

PXA3xx Processor Family Vol. IV: Serial Controller Configuration Developers Manual

Intel® Wireless MMX™ 2 Technol ogy Devel ope r’s Guide

Usi n g the In tel ® Wireless MMX™ 2 Coproce ssor with Marvell® PXA3xx Processors Programmers Reference Manual

PXA3xx P ro ces sor Family Design Gu ide

ARM* Architecture Version V5TE Specification (Do cu m ent num ber ARM * DDI 0100D-10 ), an d ARM* Architecture

Ref erenc e M anual (Documen t num ber ARM* DD I 0100B)

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

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Version -

April 6, 2009 Released Page 15

2Functional Ove rview

The PXA3xx processors are integrated system-on-a-chip microprocessors for high-performance,

low-po wer port abl e h an dhe ld an d handset devices . T hey i nc orpo rate the XSca le® mi croarc hitec ture

with on-the-fly voltage and frequency scaling and sophisticated power management to provide

industry leading MIPS/mW performance across its wide range of operating frequencies. The

processors comply with the ARM* Architecture V5TE instruction set (excluding floating point

ins tructions) and follow the ARM* pr ogrammers mo del. The multimedia coprocessor provides

enhanced Intel® Wireless MMX™ 2 instructions to accelerate audio and video processing. The

processors are available in a discrete package configuration. They provide a high degree of

backward compatibility with the Marvell PXA27x Processor Family, but they offer significant

performance and feature set enhancements.

The processor memory architecture offers greater flexibility and higher performance than previous

core products. This architecture supports two dedicated memory interfaces for high-speed DDR

SDRAM, VLIO devices, and NAND flash devices. This flexibility enables high-performance “store-

and-download” as well as “execute-in-place” system architectures. The processor memory

architecture features a memory switch that allows multiple simultaneous memory transactions

among differ ent sourc es and t argets. For exam ple , t he pro cess or arc hite ct ure al lows memory tr af f ic

between the core and DDR SDRAM to move in p arallel with DMA-generated traffi c between the LCD

controll er and interna l SRAM . In an architec ture w ith a sin gle sh ared s ystem bu s, these transa ctions

block each other. The PXA32x processor also provides a 256-Kbyte, unified L2 cache to maintain

high memory system performance, lower power with a full feature OS, and several complex

multimedia applications running simultaneously.

The processor incorporates an internal boot ROM and a Marvell® Wireless Trusted Transaction

Techno logy module to provide fle xible boot -loading op tions while mainta ining plat form sec urity. They

have up to six 12 8 Kb yte banks of i nte rnal SRAM fo r a co mb ina t ion o f di sp lay frame b uf f er, program

code, or multimedia data. Each bank can be configured to retain its contents when the processor

enters a low-power mode.

The processor provides OS timer channels and synchronous serial ports (SSPs) that accept an

external network clock input so that they can be synchronized to the cellular network.

An integrated LCD panel controller supports active and passive displays. It permits color depths of

up to 18-bits per pixels (24-bits per pixel for smart panels). The LCD controller also supports

hardware curs or and two display over lays.

The processor incorporates a comprehensive set of system and peripheral functions that make it

useful in a variety of low-power applications. Figure 1 ill us trate s the sy ste m-o n-a -chi p PXA30x

processor, Figure 2 illustrates PXA31x processor and Figure 3 illustrates the PXA32x processor.

The diagra m sh ows a multi -po rt memory switc h and sy stem bu s archit ecture w ith the co re atta ched,

along w ith an LCD c ontroller and USB 1.1 c ontrollers , and internal memory. The key fea tures of al l of

the sub-blocks are described in the PXA3xx Processor Family Developers Manual (four volumes).

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 16 April 6, 2009 Released

Figure 1: PXA32x Processor Block Diagram

Sensor LCD

Panel

DDR

SDRAM

IEEE

802.11

Cellular

Baseband

DMA

Controller Bridge

System Bus

System

Bus #2

Peripheral Bus #1

Peripheral Bus #2

CompactFlash

VLIO

16-Bit

32 / 16 Bits

Sync / As yn c

Flash

NAND

Sync

Flash

16 Bit only if DD R is 16

XCVR

UTMI

Data Flash Interface

Static

Memory

Controller

Data Flash

Controller

Intel® Quick

Capture

Camera

Interface

Mini-

LCD

Cntrlr

LCD

Controller

Graphics

USB2.0

High

Speed

Client

Memory Switch

Driscoll

Intel®

Wireless

MMX™ 2

Intel XScale®

Core

(32K I$, 32K D$)

256 KB L2 Cach e

Dynamic

Memory

Controller

Static

Memory

Controller

Internal

SRAM

768 KB

Boot

ROM

Security

USIM #2

USB1.1 Client

OTG

MMC/SD #2

(4-Bit SDIO)

Consumer

Infrared

1-WireSSP x 4

Touch

Screen

Interrupt

Controller

*coprocessor I/F

Intel® MSL

Interface GPIO

Real-

Time

Clock

Timers

(4F, 8S)

with Watchdog

MMC/SD #1

(4-Bit SDIO)

Power

Management

USIM #1 AC ‘97 I2C

Power

I2CJTAG

USB 1.1 Ho st

UART / SIR x

Pulse-Width

Modulators x 4 Keypad

Interface

DMA

Controller Bridge

Version -

April 6, 2009 Released Page 17

Figure 2: PXA31x Processor Block Diagram

Sensor LCD

Panel

DDR

SDRAM

System B us

System

Bus #2

Peripheral Bus #1

Periph eral B us

VLIO

16-Bit

16 B its

Sync / Async Flash

NAND

XCVR

ULPI

(OTG)

USB2.0

High

Speed

Client

Graphics

Intel X Scale ® Core

(32K I$, 32K D$)

Mini-

LCD

Cntrl

LCD

Controller

Quick

Capture

Camera

Interface

Da ta Flash In te r fa ce

Static

Memory

Controller

NAND Flash

Controller

USB 1.1 H ost

UART / SIR x

3Pulse Width

Modulators x 4 Keypad

Interface

DMA

Controller Bridge

Memory Switch Dynamic

Memory

Controller

Internal

SRAM

256 KB

Boot

ROM

USIM #2

MMC/SD #2

(1 and 4-Bit)

Consumer

Infrared

1-Wire

Inte r rup t

Controller

coprocessor I/F

SSP x 4

GPIO MMC/SD #1

(1 and 4-Bit) USIM #1 AC ‘97 I2C

Real-

Time

Clock

Timers

(4F , 8 S)

with Watchdog

Power

Management Power

I2C JTAG

MMC/SD #3

(1 and 4-Bit)

Video

Accelerator

Security

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 18 April 6, 2009 Released

Figure 3: PXA30x Processor Block Diagram

Sensor LC D

Panel

DDR

SDRAM

System Bu s

System

Bus #2

Peripheral Bus #1

Peripheral Bus

VLIO

16-Bit

16 Bits

Sync / Async Flash

NAND

XCVR

UTMI

USB2.0

High

Speed

Client

Graphics

Intel XScale® C ore

(32K I$, 32K D$)

Mini-

LCD

Cntrlr

LCD

Controller

Quick

Capture

Camera

Interface

Data Flash Interface

Static

Memory

Controller

NAND Flash

Controller

USB 1.1 Host

UART / SIR x

3Pulse Width

Modulators x 4 Keypad

Interface

DMA

Controller Bridge

Memory Switch Dynamic

Memory

Controller

Internal

SRAM

256 KB

Boot

ROM USIM #2

USB1.1 Client

OTG

MMC/SD #2

(1 and 4-Bit)

Consum er

Infrared

1-Wire

Interrupt

Controller

*coprocessor I/F

SSP x 4

GPIO MMC/SD #1

(1 and 4-B it) US IM #1 AC ‘97 I2C

Real-

Time

Clock

Timers

(4F , 8S )

with Watchdog

Power

Management Power

I2C JTAG

Version -

April 6, 2009 Released Page 19

3Package Information

3.1 Introduction

This chapter provides the mechanical specifications for the PXA3xx Processor Family.

3.2 Packaging Materials

Table 2 shows the mold compound and solder ball material list.

3.3 PXA32x Processor Packaging Views

3.3.1 PXA32x Processor 456-Ball VF-BGA Package

The PXA32x Processor package is a 14x14 mm, 456-pin, 0.5-mm VF-BGA, as shown in Figure 5,

Figure 6 sh ow s the dai sy chain vers ion of the pa ck age .

Table 2: Package Materials

Component Material Solder Balls

Mol d c om p oun d Su mitom o E ME-7730L 98.5 S n /1.0 Ag /0.5 Cu

NOTE: Pb-free parts, lead has not be en added in te nt ionally, but lead ma y persist as an i m purity belo w 1000 ppm

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 20 April 6, 2009 Released

Figure 4: PXA320 Processor 14x14 mm VF-BGA Package, Top View

1234567891011121314151617181920212223242526

Top View - Ball side down

Complete In k Mark Not Shown

Ball A1

orner

aaa

-B-

-A- aaa

-B-

Version -

April 6, 2009 Released Page 21

Figure 5: PXA320 Processor 14x14 mm VF-BGA Package, Bottom View

2625242322212019181716151413121110987654321

Bottom View - Ball Side Up

Ball A

Corn

0.15

0.05

456X b

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 22 April 6, 2009 Released

3.3.2 PXA320 Processor Detailed Package Dimensions

Table 3 contains both Imperial (inches) and Metric (millimeters) systems for the package

dimens ions. The Im perial dat a has been rou nded down . The Metric me asurement s are exact an d do

not contain any rounding. Marvell recommends using the Metric (millimeters) data.

Figure 6: PXA320 Processor 14x14 mm VF-BGA Package, Side View

ccc

A1 C

bbb C

-C-

Figure 7: 14x14mm VF-BGA Daisy-Chain Substrate Diagram

Version -

April 6, 2009 Released Page 23

3.3.3 PXA322 Processor Package-on-Package (PoP)

The PXA322 Processor Package-on-Package (PoP) is in a 15-by-15 mm (15 mm2), 416-pin,

0.65-mm ball pitch, as shown in Figure 16, Figure 17, and Figure 18.

Table 3: PXA320 Processor 14x14 mm VF-BGA Package Dimensions

Description Symbol Millimeters

Min Nom Max

Package H e ig ht A 1.000

Ball Heigh t A1 0.200 0.250 0.300

Ball (Lead ) W idth b 0.250 0.300 0.350

Package Body Width D 13.950 14.000 14.050

Package Body Length E 13.950 14.000 14.050

Pitch [e] 0.500

Ball (Lead) Count N 456

Corner to Ball A1 Distance Along D S1 0.750

Corner to Ball A1 Distance Along E S2 0.750

Package Edge Tol er ance aaa 0.15

Mold Flatness bbb 0. 20

Seating Plane Coplan ar i ty ccc 0.10

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 24 April 6, 2009 Released

Figure 8: PXA322 Processor 15-mm2 PoP Package, Top View

12345678910111213141516171819202122

Top View - Ball side down

Ball A1

orner

DAB

160 b1

Version -

April 6, 2009 Released Page 25

Figure 9: PXA322 Processor 15-mm2 PoP Package, Bottom View

21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Bottom View - Ball Side Up

Ball A

Corn

416

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 26 April 6, 2009 Released

Figure 10: PXA322 Processor 15-mm2 PoP Package, Side View

Version -

April 6, 2009 Released Page 27

Figure 11: PXA322 15-mm2 PoP Daisy-Chain Substrate Diagram

K8 connects to

top ball land B3

L8 conn ec ts to

top ball land B1

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 28 April 6, 2009 Released

3.3.4 PXA322 Proces sor Detailed 15mm2 POP Dimensions

Table 4 contains both Imperial (inches) and Metric (millimeters) systems for the package

dimens ions. The Im perial data ha s been rounde d down. The M etric measurem ents ar e exact and do

not co ntain any rounding. Marvell recomm ends usin g the Metric (millimeter s) data.

3.4 PXA31x and PXA30x Processor Package Views

3.4.1 PXA301 Proces sor and PXA311 Processor Multi-Chip

Package (MCP)

The PXA301 Processor and PXA311 Processor Multi-Chip Package (MCP) is available in a

15-by-15 mm (15 mm2), 416-pin, 0.65-mm ball pitch, as shown in Figure 12, Figure 13, Figure 14

and Figure 15.

Table 4: PXA322 Processor 15-mm2 POP Dimensions

Description Symbol Millimeters

Min Nom Max

Package H e ig ht A 0.93 0

Ball Height A1 0.180 0.280

Mold Co m pound Thickness A2 0.27 0.30 0.33

SMD Pad for Package Stack b1 0.29 0.32 0.35

Ball (Lead ) W idth b 0.25 0.30 0.35

Package Body Width D 14.950 15.000 15.050

Package Body Length E 14.950 15.000 15.050

Mold Cap Width F 11.430 11.450 11.470

Mold Cap Width G 11.430 11.450 11.470

Pitch [e] 0.650

Top Pac kage Pitch [e1] 0.650

Ball (Lead) Count N 416

Seating Plane Coplan ar i ty Y 0.100

Corner to Ball A1 Distance Along D S1 1.000

Cor ner to Ball A1 Dis tance Alo ng E S2 1.000

Version -

April 6, 2009 Released Page 29

Figure 12: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Top View - Ball side down

D-B-

-B-

Ball A1

orner

-A-

aaa

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 30 April 6, 2009 Released

Figure 13: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Bottom View

212019181716151413121110987654321

Bottom View - Ball Side Up

Ball A

Corn

416 8

Version -

April 6, 2009 Released Page 31

Figure 14: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package, Side View

bbb C

-C- ccc C

Figure 15: PXA301 Processor and PXA311 Processor 15-mm2 MCP Daisy-Chain

Substrate Diagram

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 32 April 6, 2009 Released

3.4.2 PXA301 Processor and PXA311 Processor Detailed MCP

Package Dimensions

Table 5 contains both Imperial (inches) and Metric (millimeters) systems for the package

dimens ions. The Im perial data ha s been rounde d down. The M etric measurem ents ar e exact and do

not co ntain any rounding. Marvell recomm ends usin g the Metric (millimeter s) data.

3.4.3 PXA302 and PXA312 Processor Package-on-Package (PoP)

The PXA302 Processor and PXA312 Processor Package-on-Package (PoP) is in a 15-by-15 mm

(15 mm2), 416-pin, 0.65-mm ball pitch, as shown i n Figure 16, Figure 17, and Figure 18.

Table 5: PXA301 Processor and PXA311 Processor 15-mm2 MCP Package

Dimensions

Description Symbol Millimeters

Min Nom Max

PXA301 Processor Package

Height A1.400

PXA311 Processor Pac kage

Height A1.500

PXA301 Pro ces sor Ball Heigh t A1 0.270 0. 37 0

PXA311 Processor Ball H eight A1 0.22 0 0.320

PXA301 P rocessor MCP Ba ll

(Lead) Width b 0.330 0.400 0.470

PXA311 Processor Ball (Le ad)

Width b 0.280 0.350 0.420

Package Body Width D 14.900 15.000 15.100

Package Body Length E 14.900 15.000 15.100

Pitch [e] 0.650

Ball (Lead) Count N 416

Corner to Ball A1 Distance Along D S1 0.750

Cor ner to Ball A1 Dis tance Alo ng E S2 0.750

Package Edge Tol er ance aaa 0.15

Mold Flatness bbb 0. 20

Seating Plane Coplan ar i ty ccc 0.10

Version -

April 6, 2009 Released Page 33

Figure 16: PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Top View

12345678910111213141516171819202122

Top View - Ball side down

Ball A1

orner

DAB

160 b1

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 34 April 6, 2009 Released

Figure 17: PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Bottom View

21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

Bottom View - Ball Side Up

Ball A

Corn

416

Version -

April 6, 2009 Released Page 35

Figure 18: PXA302 Processor and PXA312 Processor 15-mm2 PoP Package, Side View

Figure 19: PXA302 Processor and PXA312 Processor 15-mm2 PoP Daisy-Chain

Substrate Diagram

K8 c o nn e cts to

top ball land B3

L8 connects to

top ball land B1

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 36 April 6, 2009 Released

3.4.4 PXA302 Processor and PXA31 2 Processor Detailed 15mm2

POP Dimensi ons

Table 6 contains both Imperial (inches) and Metric (millimeters) systems for the package

dimens ions. The Im perial data ha s been rounde d down. The M etric measurem ents ar e exact and do

not co ntain any rounding. Marvell recomm ends usin g the Metric (millimeter s) data.

3.4.5 PXA300 Processor and PXA31 0 Processor Discrete

Package (VF-BGA)

The PXA300 Processor and PXA310 Processor packages are available in a 13-by-13 mm (13 mm2)

VF-B GA, 400- pin , 0.5 -mm bal l pi tch co nfi gura tio n, as sh own i n Figure 20, Figure 21, and Figure 22.

Table 6: PXA302 Processor and PXA312 Processor 15-mm2 POP

Dimensions

Description Symbol Millimeters

Min Nom Max

Package H e ig ht A 0.93 0

Ball Height A1 0.180 0.280

Mold Co m pound Thickness A2 0.27 0.30 0.33

SMD Pad for Package Stack b1 0.29 0.32 0.35

Ball (Lead ) W idth b 0.25 0.30 0.35

Package Body Width D 14.950 15.000 15.050

Package Body Length E 14.950 15.000 15.050

Mold Cap Width F 11.430 11.450 11.470

Mold Cap Width G 11.430 11.450 11.470

Pitch [e] 0.650

Top Pac kage Pitch [e1] 0.650

Ball (Lead) Count N 416

Seating Plane Coplan ar i ty Y 0.100

Corner to Ball A1 Distance Along D S1 1.000

Cor ner to Ball A1 Dis tance Alo ng E S2 1.000

Version -

April 6, 2009 Released Page 37

Figure 20: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package,

Top View

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Top V iew - Ball side down

Co m p lete In k Mark N ot S h o w n

Ball A1

orner

-A- aaa

-B-

aaa

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 38 April 6, 2009 Released

Figure 21: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package,

Bottom V iew

242322212019181716151413121110987654321

Ball A

Corn

Bottom View - Ball Side Up

0.05

0.15

400

Version -

April 6, 2009 Released Page 39

Figure 22: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Package,

Side View

Figure 23: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA Daisy-Chain

Substrate Diagram

bbb C

-C- ccc C

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 40 April 6, 2009 Released

3.5 PXA30x Processor Package Views

3.5.1 PXA303 Processor 19mm2 Discrete Package (VF-BGA)

The PXA 303 process or p a ckage is provid ed in a 19-b y-1 9 mm (19 mm 2) VF-BGA , 409 -pin, 0.8-m m

ball pitch configuration, as shown in Figure 24, Figure 25, Figure 26, and Figure 27. Table 7 contain

both Imperial (inches) a nd Metric (millim eters) for the package dimensions. The Im perial data has

been rounded down. The Metric measurements are exact and do no t contain any rounding. Marvell

recommends using the Metric (millimeters) data.

Table 7: PXA300 Processor and PXA310 Processor 13-mm2 VF-BGA

Package Dimensions

Description Symbol Millimeters

Min Nom Max

Package H e ig ht A 1.000

Ball Heigh t A1 0.18 0.250 0.300

Ball (Lead ) W idth b 0.260 0.300 0.340

Package Body Width D 12.900 13.000 13.100

Package Body Leng th E 12.9 00 13000 13.100

Pitch [e] 0.500

Ball (Lead) Count N 400

Corner to Ball A1 Distance Along D S1 0.750

Cor ner to Ball A1 Dis tance Alo ng E S2 0.750

Package Edge Tol er ance aaa 0.10

Mold Flatness bbb 0. 10

Seating Plane Coplan ar i ty ccc 0.08

Version -

April 6, 2009 Released Page 41

Figure 24: PXA303 Processor 19-mm2 VF-BGA Package, Top View

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 42 April 6, 2009 Released

Figure 25: PXA303 Processor 19-mm2 VF-BGA Package, Bottom View

Figure 26: PXA303 Processor 19-mm2 VF-BGA Package, Side View

Version -

April 6, 2009 Released Page 43

3.5.2 PXA303 Processor Detailed VF-BGA Package Dimensions

Table 8 contains both Imperial (inches) and Metric (millimeters) systems for the package

dimens ions. The Im perial data ha s been rounde d down. The M etric measurem ents ar e exact and do

not co ntain any rounding. Marvell recomm ends usin g the Metric (millimeter s) data.

Figure 27: PXA303 Processor 19-mm2 VF-BGA Daisy-Chain Substrate Diagram

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

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3.6 PXA3xx Processor Family Markings

Each PXA30x and PXA31x processor includes markings on top of the package. Figure 28 contains

the p rocessor product marking in formation that explains each part of the mark ing. There are two

different decoders, o ne for sam p les, and one for production material.

Table 8: PXA303 Processor 19-mm2 VF-BGA Package Dimensions

Description Symbol Millimeters

Min Nom Max

Package H e ig ht A 1.560

Ball Height A1 0.350 0.450

Package Body Thickn ess A2 1.060

Ball (Lead ) W idth b 0.450 0.500 0.550

Package Body Width D 18.900 19.000 19.100

Package Body Length E 18.900 19.000 19.100

Pitch [e] 0.800

Ball (Lead) Count N 409

Seating Plane Coplan ar i ty Y 0.140

Corner to Ball A1 Distance Along D S1 0.700

Cor ner to Ball A1 Dis tance Alo ng E S2 0.700

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April 6, 2009 Released Page 45

3.6.1 PXA32x Proces sor Markings

Each PXA300 processor or PXA310 processor includes markings on top of the package. Figure 29

contains a “Product Information Decode r” that explains what each part of the marking means. Note

that there are two dif ferent dec oders, one for samples and one for p r oduction material. Figure 30

cont ains the “Configu ration Line De coder” that explain s the co nfig uration line for produc tion m ate rial.

Figure 28: PX3xx (88AP3xx) Processor Family Produc t Marking Information

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 46 April 6, 2009 Released

Figure 29: PXA32x Processor VF-BGA Produc t Information Decoder

Figure 30: PXA32x Processor Configuration Line Decoding

S a mp le Ma rk in g s

T H G P

A M H

N1B

Package T ype:

RT = VF BGA

(Pb - Free)

D ivision (CH G ) Stepping

RCH 1BH 1B

AP = Application Processor

Blank

Mon ahans Processor Fam ily

Production Markings

PX A 3 2 B0 1 8C 60

XS cale-based

Processor

Processor Fam ily

Stepping

Blank

Speed

Temp Range

C F G 1 A

Configuration

Marking

Boot Configuration

1 = x16 NAND

2 = x8 NAND

4 = XIP NOR on the DFI

Power Bin

A = Low Power BIN

B = Standard BIN

C F G 1 A

Configuration

Marking

Boot Configuration

1 = x16 NAND

2 = x8 NAND

4 = XIP NOR on the DFI

Power Bin

A = Low Power BIN

B = Standard BIN

Version -

April 6, 2009 Released Page 47

Figure 32: PXA32x Processor Daisy Chain Samples Markings

Figure 31: PXA32x Processor Engineering Sample Markings

Product

Lot #

QDF #

iRTCHGAPMNHB1

FPO#

Q123 ES B1

M C ‘05

KOREA

PIN 1 INDICATOR

e1 Pb-Free Indicator

Product

Lot #

QDF #

iRTCHGAPMNHB1

FPO#

Q123 ES B1

M C ‘05

KOREA

PIN 1 INDICATOR

e1 Pb-Free Indicator

Laser Mark on top side of Package

Laser Mark on top side of Pac kag e

14x14MM

456L

DAISY CHAIN

KOREA

PIN 1 INDICATOR

PX3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 48 April 6, 2009 Released

Figure 33: PXA32x Processor Productio n Markings

Product

Lot #

Boot Configuration and Power Bin

iPXA320B1C806

FPO#

CFG1A

M C ‘05

KOREA

PIN 1 INDICATOR

e1 Pb-Free Indicator

Product

Lot #

Boot Configuration and Power Bin

iPXA320B1C806

FPO#

CFG1A

M C ‘05

KOREA

PIN 1 INDICATOR

e1 Pb-Free Indicator

Laser Mark on top side of Package

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April 6, 2009 Released Page 49

4Pin Listing and Signal Definitions

This chapter describes the signals and pins for the PXA3xx Processor Family.

Many of the package pins are multiplexed so that they can be configured for use as a

gene ral-purpos e I/O signal or any one of the alternate functions using the G PIO alternate-function

select registers. Some signals can be configured to appear on one of several different pins using

alternate function controls.

4.1 Ball Map View

In th e following ball m ap figures , the lowerc ase lett er “n”, wh ich norm ally indica tes nega tion, appe ars

as uppercase “N”. “RFU” means “Reserved For Future Use”. NC mea ns “No Connect”. Do not

connect these pins. The balls highlighted in yellow show the difference between the PXA30x and

PXA31x processor.

4.1.1 PXA32x Proces sor Ball Maps

4.1.1.1 PXA320 Processor 456-Ball VF-BGA Ball Map

Figure 34 and Figure 35 show the ball map for the 456-ball VF-BGA PXA320 process or discrete

package.

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 50 April 6, 2009 Released

Figure 34: PXA320 Processor 14mm2 VF-BGA Ball Map, Left Half

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ANC NC USBOTG_

NUSBOTG_

PUSBH1_N USBH1_P PWR_EN TMS VSS VCC_BBA

TT NGPIO_R

ESET PW R_ SDA T ES T A

BNC MD1 MD0 TCK VSS_USB TDI NBATT_F

AULT PWR_OUT VSS_BBA

TT PXTAL_IN VSS_OSC

13M VCT CX O_

EN GPIO4_2 B

CMD4 MD2 DQM0 MD3 VCC_USB CLK_TOU

TPWR_CAP

1TXTAL_O

UT NRESET_

OUT PX T AL _O

UT PW R_SCL TESTCLK GPIO2_2 C

DMD7 DQS0 MD5 VC C_MEM TDO NTRST PWR_CAP

0TXTAL_IN VCC_BG VSS_BG CLK_POU

TGPIO5_2 GPIO127 D

EDQS1 MD6 MD8 VSS_MEM SYS_EN NRESET VCC_MVT

VCC_OSC

13M VCC_SRA

MVCC_IO1 VSS_IO1 GPIO0_2 GPIO125 E

FDQM1 MD10 MD9 VCC_MEM EXT_WAK

EUP1 F

GMD14 MD13 MD11 VSS_MEM EXT_WAK

EUP0 G

HMA3 MD15 MD12 VCC_MEM VCC_MVT H

JMA1 MA2 VCC _S RA

MVSS_MEM VCC_MEM J

KMA14 SDMA10 RFU_K3 MA0 VCC_MEM K

LNSDCS0 MA13 MA12 MA15 VSS_MEM VSS VSS VCC _A PP

MSDCLK0 SDCKE NSDWE VCC_MVT VCC_MEM VSS VSS

VCC _APP

NSDCLK1 N SDRAS MA8 NSDCS1 VSS_MEM VCC_APP

VCC_APP

VSS N

PMA5 MA9 MA7 MA11 VCC_MEM

VCC_APP

VSS P

RCOMP_D

DR RFU_R2 MA6 NSDCAS VSS_MEM VSS VSS VCC _APP

TRFU_T1 RFU_T2 RFU_T3 MA4 VCC_MEM VSS VSS

VCC _APP

URFU_U1 RFU_U2 RFU_U3 RFU_U4 VSS_MEM U

VMD18 DQM2 MD17 MD16 VSS_MEM V

WMD19 DQS2 MD23 VCC_MVT VCC_MEM W

YMD20 MD24 MD22 VSS VCC_MEM Y

AA MD21 DQS3 DQM3 MD25 VSS_MEM AA

AB MD26 MD31 MD30 MD27 VCC_MEM

DF_ALE_N

WE2 VCC_DF VCC_MVT VSS DF_IO8 VCC_SRA

MVSS DF_IO12 AB

AC MD28 GPIO2 GPIO1 GPIO0 VSS_MEM VSS_DF VSS_DF D F_ADDR

0VCC_DF VSS_DF DF_IO1 DF_IO4 DF_IO15 AC

AD MD29 GPIO3 GPIO4 RFU_AD4 DF_CLE_

NOE VCC_DF DF_NRE DF_ADDR

1DF_IO0 D F_IO2 DF_IO11 DF_IO13 VSS_DF AD

AE NC NC NXCVREN N BE0 DF_INT_R

NB DF_NCS0 NLUA NLLA DF_ADDR

3DF_IO10 VCC_DF DF_IO6 VCC_DF AE

AF NC NC DF_ALE_N

WE1

DF_SCLK_

ENBE1 DF_NCS1 DF_NWE D F_ADDR

2DF_IO9 D F_IO3 VSS_DF DF_IO5 DF_IO7 AF

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4.1.1.2 PXA322 Processor 15mm2 Package on Package (POP) Bottom Ball

Map

Figure 36 and Figure 37 show the bottom ball map for the bottom PXA322 processor POP package.

Figure 35: PXA320 Processor 14mm2 VF-BGA Ball Map, Right Half

14 15 16 17 18 19 20 21 22 23 24 25 26

AGPIO3_2 GPIO126 GPIO123 GPIO114 VCC_TSI GPIO109 GPIO106 GPIO102 GPIO101 GPIO100 GPIO99 NC NC A

BGPIO 1_2 VC C_PLL GPIO1 21 GPIO11 9 GPIO113 G PIO 110 G PIO1 07 GPIO10 3 VCC_ IO6 G PIO9 4 GPIO98 GPIO97 NC B

CVSS_PLL GPIO122 GPIO118 GPIO115 VSS_TSI GPIO112 VCC_IO6 GPIO105 VSS_IO6 GPIO95 GPIO96 GPIO88 GPIO90 C

DGPIO124 VCC_IO1 VCC _S RA

MGPIO116 TSI_YM TSI_XM VSS_IO6 GPIO93 GPIO87 GPIO92 GPIO91 GPIO89 GPIO84 D

EGPIO120 VSS_IO1 GPIO117 TSI_YP TSI_XP GPIO111 VCC_MVT GPIO108 GPIO104 GPIO85 GPIO86 GPIO81 GPIO82 E

FGPIO83 GPIO80 VCC_MSL GPIO79 VSS_MSL F

GGPIO78 VCC_MVT GPIO77 VSS VSS G

HGPIO15_2 GPIO75 GPIO76 GPIO17_2 VCC_SRA

JGPIO73 GPIO74 GPIO16_2 VSS_LCD VCC_LCD J

KGPIO66 GPIO71 GPIO72 GPIO14_2 GPIO70 K

LVCC_APP

SVSS VSS GPIO11_2 GPIO69 GPIO67 GPIO64 GPIO68 L

VCC_APP

SVSS VSS GPIO9_2 VSS_LCD GPIO63 GPIO13_2 GPIO65 M

NVSS VCC_APP

VCC_APP

VSS GPIO8_2 VCC_LCD GPIO10_2 GPIO12_2 N

PVSS

VCC_APP

VCC_MVT GPIO7_2 GPIO61 GPIO6_2 GPIO62 P

RVCC_APP

SVSS VSS GPIO57 GPIO60 GPIO59 VSS_CI VCC_CI R

VCC_APP

VSS VSS GPIO53 GPIO58 GPIO56

VCC_APP

VSS T

UGPIO51 GPIO52 VSS_CI GPIO54 GPIO55 U

VGPIO48 GPIO50 VC C_CI

VCC_APP

VSS V

WGPIO43 VCC_IO4 GPIO45 GPIO10 GPIO49 W

YGPIO39 GPIO41 VSS_IO4 GPIO47 GPIO46 Y

AA GPIO32 GPIO40 GPIO42 GPIO44 VSS AA

AB DF_IO14 GPIO7 GPIO11 GPIO12 VCC_IO3 GPIO16 GPIO19

VCC_CAR

D1 GPIO28 VSS_IO4 VCC_IO4 GPIO37 VCC_MVT AB

AC VCC_APP

SGPIO8 VCC_APP

SGPIO14 VSS_PLL GPIO17 VCC_APP

SGPIO20 GPIO22 GPIO30 GPIO34 GPIO36 GPIO38 AC

AD VSS VCC_MVT VSS VSS VSS VCC_APP

SVSS_CAR

D1 VSS GPIO25 GPIO27 GPIO31 GPIO33 GPIO35 AD

AE GPIO6 VSS VCC_APP

SVSS_IO3 VCC_PLL VSS GPIO18 VSS GPIO24 VCC_CAR

D2 VSS_CAR

D2 GPIO29 NC AE

AF GPIO5 VCC_APP

SGPIO9 GPIO13 VCC_APP

SGPIO15 VCC_APP

SVC C_APP

SGPIO21 GPIO23 GPIO26 NC NC AF

14 15 16 17 18 19 20 21 22 23 24 25 26

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

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Figure 36: PXA322 Processor 15mm2 POP Bottom Ball Map, Left Half

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ANC_A1 NC_A2 VSS_DF RFU_A4 TDI PWR_EN TXTAL_IN TXTAL_OUT VSS_OSC13

MPWR_SDA GPIO4_2 A

BNC_B1 VCC_MEM RFU_B3 VCC _DFCO

RE DF_NCS1 VCC_USB NRESET_IN PWR_CAP0 VCC_DF RFU_B10 RFU_B11 B

CVSS_MEM MD1 RFU_C3 VSS USBOTG_P CLK_TOUT PWR_OUT VSS_BBATT VSS_BG DF_CLE_N

OE GPIO2_2 C

DVSS MD0 VCC_MEM RFU_D4 USBOTG_N RFU_D6 NGPIO_RES

ET DF_ALE_N

WE1 CLK_POUT TEST VSS_IO1 D

EMD3 MD2 VSS_USB TCK USBH1_N USBH1_P TMS VCC_APPS NBAT T_ FAU

LT PXTAL_OUT GPIO5_2 E

FMD5 MD4 VCC _MVT VCC_MVT MA2 TDO NTRST VSS PXTAL_IN VCC_OSC1

VCTCXO_E

GVCC_SRAM VCC_SRAM MD7 MA3 MD9 MD11 SYS_EN PWR_CAP1 NRESET_O

UT VCC_BG GPIO1_2 G

HVSS_MEM DQM1 NSDWE MD15 MD13 EXT_WAKE

UP1 RFU_H7 EXT _W AKE

UP0 VCC_BBATT GPIO127 PWR_SCL H

JMD6 DQS0 MA1 MA14 VSS MA12 NSDCS1 MA0 J

KDQM0 VSS_MEM SDMA10 NSDCS0 VCC_MEM MA6 MA4 GPIO119 K

LRCOMP_DD

RMA11 VCC_MEM NSDR AS VCC_APPS VCC _APPS RFU_L7 VCC _MVT L

MVSS_MEM DQS1 VCC_MEM VSS VCC_APPS SDCLK1 VCC_MEM GPIO4 M

NMD10 VCC_MEM VSS VCC_MEM MD17 VCC_APPS VCC_APPS MA13 N

PVSS_MEM VCC_MEM VCC_MVT VCC_MVT VCC_APPS DF_IO1 VSS_MEM DF_NCS0 VCC_SRAM DF_IO15 GPIO5 P

RVSS_MEM MD8 MD24 VSS_MEM VSS_MEM GPIO3 GPIO111 DF_IO14 GPIO109 GPIO7 VSS_LCD R

TVSS_MEM MD12 DQM2 MD29 VCC_DF NBE0 D F_ALE_N

WE2 DF_NWE DF_IO4 DF_IO3 DF_IO12 T

UVSS SDCKE GPIO0 MD28 MD31 DF_NRE DF_IO2 NLUA DF_IO0 DF_IO5 VSS U

VVSS VSS GPIO2 GPIO1 NXC VREN VCC_DF VSS DF_ADDR2 DF_IO8 DF_IO6 DF_IO9 V

WDF_INT_RN

BMD14 MD22 DQM3 DF_SCLK_E VSS_DF DF_ADDR0 DF_ADDR1 MD27 DF_IO7 VSS W

YNC_Y1 SDCLK0 MD16 MD26 MD18 NBE1 NC_Y7 DF_ADDR3 DF_IO11 VSS_DF MD25 Y

AA NC_AA1 NC_AA2 VCC_MEMC

ORE MD1 9 MD30 MD20 MD21 NLLA MD 23 DQS2 DQS3 AA

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April 6, 2009 Released Page 53

Figure 37: PXA322 Processor 15mm2 POP Bottom Ball Map, Right Half

12 13 14 15 16 17 18 19 20 21

AGPIO0_2 GPIO126 GPIO120 GPIO116 TSI_XP_HV GPIO108 GPIO104 VCC_SRAM NC_A20 NC_A21 A

BGPIO122 GPIO11 8 G PIO1 14 VCC_IO1 GPIO110 TSI_YP_HV GPIO10 2 G PIO1 06 VSS_DF NC_B21 B

CVSS_PLL GPIO12 4 TSI_YM_HV GPIO112 GPIO105 GPIO100 GPIO99 GPIO103 DF_NW P GPIO95 C

DGPIO121 LOCK_PRE VSS_TSI GPIO107 GPIO88 GPIO90 GPIO101 GPIO97 GPIO87 GPIO96 D

EVCC_TSI GPIO125 VSS VCC_IO6 GPIO94 VCC_MVT GPIO91 VSS_IO6 GPIO93 GPIO92 E

FVCC_PLL GPIO3_2 VCC_SRAM TSI_XM_HV GPIO84 GPIO86 GPIO85 GPIO89 GPIO75 GPIO79 F

GTESTCLK GPIO123 GPIO117 GPIO76 GPIO78 VSS_MSL GPIO83 VCC_MSL GPIO81 GPIO77 G

HGPIO113 GPIO11 5 GPIO80 GPIO16_ 2 GPIO14 _2 G PIO74 GPIO73 GPIO17_2 GPIO71 GPIO15 _2 H

JGPIO70 GPIO68 GPIO7 2 GPIO66 GPIO65 GPIO67 GPIO69 VSS_LCD J

KGPIO98 GPIO9_2 GPIO82 GPIO64 VCC _LCD GPIO63 VCC_LCD GPIO61 K

LGPIO7 _2 GPIO60 GPIO6 2 G PIO1 3_2 G PIO 11_2 GPIO10_2 GPIO 8_2 GPIO12 _2 L

MGPIO52 VCC_CI GPIO5 6 GPIO54 GPIO53 GPIO57 GPIO59 MA5 M

NVCC_APPS VCC_MVT VSS_CI GPIO58 MA15 GPIO55 GPIO6_2 MA7 N

PGPIO9 GPIO14 GPIO10 GPIO50 GPIO4 5 VSS GPIO47 GPIO49 GPIO48 VSS P

RVCC_PLL DF_IO10 VSS_CARD

1GPIO43 G PIO4 1 VSS_IO4 GPIO46 GPIO44 GPIO42 G PIO5 1 R

TVSS_IO3 GPIO16 D F_IO1 3 GPIO39 GPIO3 7 G PIO36 GPIO34 GPIO40 GPIO38 NSDCAS T

UGPIO31 GPIO12 GPIO17 GPIO20 G PIO2 9 G PIO35 VCC_IO4 GPIO28 GPIO30 MA9 U

VVCC_APPS GPIO11 VSS VCC_APPS GPIO27 GPIO22 GPIO33 VSS_CARD

2GPIO32 MA8 V

WGP I O6 VC C_A PP S V SS_P LL GP I O18 G PI O1 9 VCC_CARD

2GPIO25 GPIO24 ND_RST VSS_MEM W

YVSS_DF GPIO13 GPIO15 VCC_APPS VCC_APPS GPIO23 VSS RFU_Y19 RFU_Y20 NC_Y21 Y

AA GPIO8 VCC_IO3 VCC_APPS VCC_APPS GPIO21 VCC_CARD

1VSS GPIO26 NC_AA20 NC_AA21 AA

12 13 14 15 16 17 18 19 20 21

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 54 April 6, 2009 Released

4.1.1.3 PXA322 15mm2 Package-on-Package (PoP) Top Ball Map

Figure 38 and Figure 39 show the top ball map for the 416-ball botto m PXA322 processor POP

package.

NOTES:

1. The LO C K_PRE ba ll (D13) con nects directly to the A14 on the top package. Co nsult the da tash eet fo r th e top package

mem or y device for app ropriate requirem ents for this pin.

2. The DF _N W P ball (C20) connects direct l y to C21 and F22 on t he top package. C ons ul t the datas hee t for th e to p

package m emory device for ap pr opriate requireme nts for these pins.

3. The ND_ R S T ball (W20) connects direct l y to Y21 on the top pack age. Consult the datash eet fo r the top package

mem or y device for app ropriate requirem ents for these pins

4. The VCC _DF b al ls (V6, T5 and B9) c onnect to the VCC _DFQ ba lls (B9, B15, B21 and AB21) on the top package and

are power ed from the VCC_ DF pow er domain. T hese ball s are used for the IO voltage domai n for the device connec t ed

to th e Da ta F lash In terfa ce (DFI).

5. The VCC_DFCORE ball (B4) is directly connected to the VCC_DF balls (B4, B20, AA3 and AA12) on the top package. A

seper a te power supply can be used for th is ball in o rd er to ke ep the core voltage on whi le the pro cessor is in S3/ D 4/C4

powe r mode. If this is not nee ded for the de vi ce connec te d to th e D FI bus connec t thi s pin to the VCC _D F power

domain.

6. The VCC_MEM balls (B2, D3, K5, L3, N2, N4, M3, M7 and P2) are connected to the VCC_MEMQ balls (E2, H2, M2, U2,

AA5, AA8, AA15 and AA18) on the top package and are powered from t he VCC_MEM power domain. Thes e ball s ar e

used fo r the I O vol tag e dom ain for the DD R SDRA M .

7. The VCC_MEMCORE ball (AA3) is connected to the VCC_MEM balls (B2, J21, P2, AA21 and AB2) on the top package.

A separate power supp ly can be used for thi s ball in orde r to keep the DDR SDRAM core voltag e on while the processo r

is in S3/D4/C4 power mode. If power does not need to be supplied to the core voltage for the DDR SDRAM while the

processor is in S3/D4/C4 connect this pin to the VCC_MEM power domain.

Figure 37: PXA322 Processor 15mm2 POP Bottom Ball Map, Right Half

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April 6, 2009 Released Page 55

Figure 38: PXA322 Processor 15mm2 PoP Top Ball Map, Left Side

ANC VSS_MEM DF_IO1 VSS_DF DF_IO3 DF_IO5 DF_IO7 DF_IO9 VSS_DF DF_CLE_N

OE DF_IO11 A

BVSS_MEM VCC_MEM DF_IO0 VCC_DF DF_IO2 DF_IO4 DF_IO6 DF_IO8 VCC_DFQ DF_ALE_N

WE1 DF_IO10 B

CDF_NWE DF_INT_RN

DMD1 MD0 D

EVSS_MEM VCC_MEMQ E

FMD3 MD2 F

GMD5 MD4 G

HVSS_MEM VCC_MEMQ H

JMD7 MD6 J

KDQM0 DQS0 K

LDQM1 DQS1 L

MVSS_MEM VCC_MEMQ M

NMD9 MD8 N

PVSS_MEM VCC_MEM P

RMD11 MD10 R

TMD13 MD12 T

UVSS_MEM VCC_MEMQ U

VMD15 MD14 V

WSDCKE SDCLK0 W

YNC SDCLK1 Y

AA NC VSS_DF VCC_DF MD16 VCC_MEMQ MD18 MD20 VCC_MEMQ MD22 DQS2 DF_SCLK_S A

AB NC VCC_MEM VSS_DF MD17 VSS_MEM MD19 MD21 VSS_MEM MD23 DQM2 NC AB

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

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4.1.2 PXA31x Proces sor Ball Maps

4.1.2.1 PXA310 Processor 13mm2 VF-BGA Ball Map

Figure 40 and Figure 41 show the bottom ball map for the PXA310 processor 13mm2 discrete

package. The balls highlighted in yellow have different functionality on the PXA30x processor.

Figure 39: PXA322 Processor 15mm2 PoP Top Ball Map, Right Side

ADF_IO13 DF_IO15 LOCK _P R

EVSS_DF NC NC NC NC NC VSS_DF NC A

BDF_IO12 DF_IO14 NC VCC_DFQ NC NC NC NC VCC_DF VCC_DFQ VSS_DF B

CDF_NWP NC C

DGPIO3 GPIO4 D

EDF_NCS0 DF_NCS1 E

FDF_NRE DF_NWP F

GDF_ALE_

NWE1 NC G

HNSDWE DF_CLE_

NO E H

JVCC_MEM VSS_MEM J

KMA0 MA1 K

LMA2 MA3 L

MMA4 MA5 M

NMA6 MA7 N

PMA14 MA15 P

RNSDCS0 NSDCS1 R

TNSDRAS NSDCAS T

UMA8 MA9 U

VSDMA10 MA11 V

WMA12 MA13 W

YND_RST VSS_MEM Y

AA VCC_DF DQS3 MD24 VCC_MEMQ MD26 MD28 VCC _ME M Q MD30 NLLA VCC_MEM NC A

AB VSS_DF DQM3 MD25 VSS_MEM MD27 MD29 VSS_MEM MD31 NC VCC_DFQ NC AB

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April 6, 2009 Released Page 57

Figure 40: PXA310 Processor 13mm2 VF-BGA Ball Map, Left side

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ANC NC RFU_A3 VCC_BIAS TCK CLK_TOUT PWR_CAP

0NRESET_O

UT PXTAL_IN PWR_SCL VCC_IO1 GPIO1_2 A

BNC RFU_B2 RFU_B3 RFU_B4 TDI N RESET PWR_OUT VC C_OS C1

3M PXTAL_OU

VCTCXO_E

NVSS_IO1 CLK_POUT B

CVSS_MEM VSS_MEM RFU_C3 TDO PWR_EN NBATT_FA

ULT TXTAL_ IN TXTAL_OU

TVCC_BG VSS_OSC1

3M VCC_PLL GPIO127 C

DMD0 VCC _MEM TMS D

EMD1 MD2 VCC _MEM NT RS T EXT_WAKE

UP0 VSS VCC_BBAT

TNGPIO_RE

SET TESTCLK VCC_APPS VSS E

FMD3 DQM0 VCC_MEM VSS_MEM SYS_EN PWR_CAP

1VSS_BBAT

TVCC _MVT VSS_BG PWR _SDA G PIO125 F

GMD4 MD5 DQS0 VC C_MEM VSS_MEM G

HMD7 MA2 MD6 VSS_MEM VCC_MVT VSS VSS VCC_APPS VSS TEST H

JMA6 MA15 MA14 VCC_MEM VSS_MEM VSS J

KSDMA10 MA8 MA4 VCC_MEM VSS_MEM VCC_APPS K

LSDCLK0 SDCLK1 MA12 VCC_APPS VSS_MEM VSS L

MMA0 NSDCS1 NSDCS0 MA13 VSS VSS M

NMA9 MA11 MA7 VCC_MEM VSS_MEM VSS N

PRCOMP_D

DR NSDRAS MA5 MA3 VCC_MVT VSS P

RRFU_R1 SDCKE NSDWE MA1 VSS_MEM VCC_APPS R

TMD9 MD8 NSDCAS VCC_MEM VSS_MEM VSS T

UDQM1 MD11 MD10 VSS VCC_MVT VSS VSS VCC_APPS VSS VSS U

VMD13 MD12 DQS1 VCC_MEM VSS_MEM V

WGPIO0 MD14 MD15 NC DF_CLE_N

OE NC NC NC DF_NCS0 VCC_SRA

MNC W

YGPIO2 VCC_MEM VSS_MEM VSS_DF VCC_DF DF_IO0 VSS_DF NC VSS_DF VSS_DF DF_IO7 Y

AA NCS1 GPIO1 DF_INT_R

NB AA

AB NCS0 D F_NWE DF_NRE VCC_DF DF_AD DR1 NC VCC_DF DF_IO9 DF_IO3 VCC_DF NLLA DF_IO13 AB

AC NC DF_ALE_N

WE NBE1 DF_ADDR0 DF_ADDR3 NC DF_IO1 VCC_MVT VCC_APPS VSS DF_SCLK_

EVCC_DF AC

AD NC NC NBE0 DF_ADD R2 DF_IO8 DF_IO2 DF_IO10 VSS DF_IO11 NLUA RFU_AD11 DF_IO4 AD

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PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 58 April 6, 2009 Released

Figure 41: PXA310 Processor 13mm2 VF-BGA Ball Map, Right side

13 14 15 16 17 18 19 20 21 22 23 24

AGPIO 0_2 GPIO126 GPIO115 GPIO11 6 GPIO10 7 VSS_ IO1 GPIO1 10 G PIO1 02 G PIO1 00 GPIO97 NC NC A

BGPIO123 GPIO119 GPIO113 GPIO99 VCC_APPS VCC_ MVT GPIO101 GPIO106 VC C_SRA

MVSS_IO1 GPIO96 NC B

CVSS_PLL VCC_APPS GPIO118 VCC_IO1 VSS GPIO108 GPIO104 GPIO103 VCC_MVT GPIO92 GPIO94 GPIO98 C

DGPIO91 GPIO90 GPIO95 D

EGPIO 121 GPIO117 GPIO111 GPIO11 4 NC GPIO9_ 2 NC G PIO7 _2 GPIO88 GPIO87 GPIO93 E

FGPIO 124 GPIO122 GPIO120 GPIO10 9 GPIO10 5 G PIO10_2 GPIO8 _2 GPIO84 GPIO85 GPIO83 VCC_IO1 F

GGPIO75 VSS_MSL GPIO82 GPIO81 GPIO89 G

HVSS VSS VCC_APPS GPIO112 VSS GPIO71 VCC_MSL GPIO77 GPIO80 GPIO86 H

JVSS GPIO63 GPIO79 GPIO74 GPIO76 GPIO78 J

KVCC_APPS VCC_LCD GPIO69 GPIO66 GPIO72 GPIO73 K

LVSS GPIO60 GPIO68 GPIO65 GPIO67 GPIO70 L

MVSS GPIO59 VSS_ LCD GPIO61 GPIO62 GPIO64 M

NULPI_DIR VCC_MVT GPIO52 GPIO55 GPIO57 GPIO51 N

PULPI_NXT GPIO58 GPIO49 GPIO47 GPIO54 GPIO56 P

RVC C_APPS GPIO48 GPIO45 VC C_CI GPIO53 GPIO50 R

TGPIO46 VSS_CI GPIO44 GPIO42 VSS VCC_APPS T

UVSS VSS VCC_APPS VSS ULPI_STP GPIO39 VSS_ULPI GPIO38 GPIO41 GPIO43 U

VGPIO37 GPIO35 VCC_U LPI GPIO36 GPIO40 V

WDF_IO12 VSS_DF GPIO2_2 VCC_MVT G PIO18 GPIO33 GPIO27 GPIO3_2 GPIO31 GPIO32 GPIO34 W

YVSS_DF DF_IO14

VSS_CARD

1GPIO8 G PIO 15 GPIO4_ 2 GPIO6 _2 G PIO5 _2 GPIO21 GPIO28 GPIO29 Y

AA GPIO30 GPIO25 GPIO26 AA

AB VCC_DF GPIO3 GPIO5 VCC_APPS GPIO7 GPIO10 GPIO11 VCC_IO3 GPIO19 GPIO23 GPIO20 VSS_IO3 AB

AC DF_NCS1 GPIO4

VCC_CARD

1VSS VSS VSS_CARD

2GPIO 13 GPIO 12 GPIO17 VCC_ PL L GPIO22 NC AC

AD DF_IO5 DF_IO6 DF_IO15 GPIO9 GPIO6 VCC_CARD

2GPIO16 GPIO14 VSS_PLL GPIO24 NC NC AD

13 14 15 16 17 18 19 20 21 22 23 24

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April 6, 2009 Released Page 59

4.1.2.2 PXA311 and PXA312 15mm2 Multi-Chip Package (MCP) and Package

on Package (P OP) Bottom Ball Map.

Figure 42 and Figure 43 show the bottom ball map for the PXA31x processor 15mm2 MCP and POP

packages. The balls highlighted in yellow have different functionality on the PXA30x processor.

Figure 42: PXA31x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map,

Left side

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AVSS VSS RFU_A3 RFU_A4 RFU_A5 NTRST PWR_CAP0 TXTAL_IN VSS VCC_APPS GPIO0_2 A

BVSS VSS VCC_BIAS NC RFU_B5 CLK_TOUT EXT_WAKE

UP0 TXTAL_OUT PXTAL_IN PWR_SDA TEST B

CNC VSS TMS TCK NC NBATT_FAU

LT PWR_OUT VCC_BBATT PXTAL_OUT VSS_BG CLK_POUT C

DMD0 TDO PWR_EN SYS_EN VCC_MEM NRESET VSS VSS_BBATT VCC_OSC1

3M VCC_BG GPIO1_2 D

EMD 1 MD2 TDI VCC_MVT G PIO3 _2 GPIO2_2 GPIO6_ 2 NGPIO_RES

VSS_OSC13

MVCTCXO_E

NVSS_PLL E

FMD3 MD4 DQS0 VSS GPIO5_2 VSS_MEM VSS_MEM PWR_CAP1 NRESET_O

UT PWR_SCL TESTCLK F

GMD5 MD6 DQM0 NC VCC_MEM VCC_MEM VSS_MEM GPIO4_2 VCC_MVT VC C_IO1 VCC_DF G

HMD7 MA14 MA2 MA4 MA13 VCC_MEM VSS_MEM VSS VSS VCC_APPS VCC_APPS H

JMA8 NSDCS1 SDMA10 MA15 VCC_MVT VCC_MEM VSS_MEM GPIO10_2 J

KSDCLK0 SDCLK1 MA12 MA6 VSS VCC_MEM VSS_MEM GPIO9_2 K

LNSDCS0 MA9 MA0 NC VCC_APPS VCC_MEM VSS_MEM NC L

MMA3 MA7 MA5 MA11 VSS VCC_MEM VSS_MEM NC M

NRCOMP_DD

RRFU_N2 NSDCAS MA1 VCC_APPS VCC_MEM VSS_MEM GPIO8_2 N

PNSDWE NSDRAS MD8 NC NC VCC_MEM VSS_MEM GPIO7_2 VSS VCC_APPS VCC_APPS P

RMD10 SDCKE MD9 DQS1 VSS VCC_MEM VSS_MEM VSS VSS_DF VSS_DF VSS_DF R

TMD12 MD11 MD14 DQM1 VCC_MVT VCC_MEM VSS_MEM VSS VCC_DF VCC_DF VCC_DF T

UMD15 MD13 NC GPIO1 DF_NWP VCC_MEM VSS_MEM DF_IO8 VCC_MVT DF_NCS1 GPIO3 U

VGPIO2 NC GPIO0 NCS1 VCC_MEM D F_ADDR1 DF_ALE_N

WE DF_C LE_N

OE DF_NCS0 DF_IO4 DF_IO7 V

WNCS0 NC DF_INT_RN

BDF_NWE DF_NRE D F_ADDR2 DF_IO2 DF_IO11 RFU_W9 DF_IO13 DF_IO14 W

YVSS_DF VSS_DF NBE0 DF_AD DR3 DF_IO9 DF_IO10 VSS DF_IO3 NLUA NLLA VCC_CARD

AA VSS_DF VSS_DF NBE1 DF_AD DR0 DF_IO0 DF_IO1 VCC_APPS VCC_SRAM VCC_APPS DF_SCLK_E GPIO4 AA

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PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 60 April 6, 2009 Released

4.1.3 PXA30x Proces sor Ball Maps

4.1.3.1 PXA300 Processor 13mm2 VF-BGA Ball

Figure 44 and Figure 45 show the bottom ball map for the PXA300 processor 13mm2 discrete

package. The balls highlighted in yellow have different functionality on the PXA31x processor.

Figure 43: PXA31x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map,

Right side

12 13 14 15 16 17 18 19 20 21

AGPIO126 VCC_APPS GPIO116 VCC_APPS GPIO110 GPIO102 GPIO99 GPIO96 VSS VSS A

BGPIO124 VSS GPIO120 GPIO112 VSS GPIO106 GPIO100 VCC_SRAM VSS VSS B

CGPIO127 GPIO115 GPIO122 GPIO113 GPIO107 GPIO108 VCC_SRAM GPIO101 GPIO95 GPIO98 C

DVCC_PLL GPIO123 GPIO118 GPIO114 GPIO109 GPIO105 GPIO103 NC GPIO97 GPIO94 D

EVSS_PLL GPIO119 GPIO117 VCC_IO1 GPIO86 GPIO89 GPIO91 GPIO104 GPIO93 GPIO92 E

FGPIO125 GPIO121 GPIO111 VSS_IO1 GPIO79 VSS_MSL GPIO87 GPIO85 GPIO88 GPIO90 F

GVSS_DF VSS_IO1 VCC_MVT VCC_IO1 GPIO78 VCC_MSL GPIO81 GPIO83 GPIO82 GPIO84 G

HVCC_APPS VSS VSS VCC_MVT GPIO73 GPIO74 GPIO75 GPIO77 GPIO76 GPIO80 H

JVSS VCC_MVT GPIO71 GPIO65 GPIO67 GPIO69 GPIO70 GPIO72 J

KVCC_APPS VSS_LCD VCC_LCD GPIO64 GPIO68 GPIO61 GPIO63 GPIO66 K

LVCC_APPS VSS_LCD VCC_LCD GPIO59 GPIO56 GPIO62 GPIO58 GPIO60 L

MVCC_APPS VSS_LCD VCC_LCD GPIO53 GPIO55 GPIO57 GPIO52 GPIO54 M

NVSS VCC_MVT GPIO47 GPIO49 GPIO50 GPIO51 VSS VCC_APPS N

PVCC_APPS VSS VSS VCC_CI GPIO43 GPIO45 GPIO46 VSS_CI VCC_CI GPIO48 P

RVSS_DF VSS_DF VCC_MVT VSS_ULPI VCC_ULPI GPIO37 GPIO39 GPIO42 GPIO41 GPIO44 R

TVCC_DF VCC_DF VSS VSS_IO3 VCC_IO3 GPIO38 GPIO35 GPIO40 GPIO34 GPIO36 T

UGPIO9 DF_LOCKP

RE GPIO8 DF_IO12 GPIO12 GPIO19 GPIO31 GPIO33 GPIO32 GPIO28 U

VGPIO5 GPIO6 GPIO11 GPIO13 GPIO16 ULPI_DIR GPIO20 GPIO29 GPIO30 GPIO27 V

WDF_IO6 DF_IO5 GPIO7 DF_IO15 VSS_PLL GPIO17 GPIO18 GPIO21 ULPI_NXT ULPI_STP W

YVSS_CARD

1VCC_APPS GPIO10 GPIO14 GPIO15 GPIO23 GPIO25 GPIO26 VSS_IO3 VSS_IO3 Y

AA VCC_APPS VSS VCC_CARD

2VSS_CARD

2VCC_PLL GPIO22 GPIO24 NC VSS_IO3 VSS_IO3 AA

12 13 14 15 16 17 18 19 20 21

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April 6, 2009 Released Page 61

Figure 44: PXA300 Processor 13mm2 VF-BGA Ball Map, Left side

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ANC NC USBOTG_P VCC_USB TCK CLK_TOUT PW R_ CAP

0NRESET_O

UT PXTAL_IN PWR_SCL VCC_IO1 GPIO1_2 A

BNC VSS_USB USBOTG_

NUSBH1_P TDI N RESET PWR_OUT VCC_OSC1

3M PXTAL_OU

VCTCXO_E

NVSS_IO1 CLK_POUT B

CVSS_MEM VSS_MEM USBH1_N TDO PWR_EN NBATT_FA

ULT TXTAL_ IN TXTAL_OU

TVCC_BG VSS_OSC1

3M VCC _PLL G PIO 127 C

DMD0 VCC _MEM TMS D

EMD1 MD2 VCC _MEM NT RS T EXT_WAKE

UP0 VSS VCC_BBAT

TNGPIO_RE

SET TESTCLK VCC_APPS VSS E

FMD3 DQM0 VCC_MEM VSS_MEM SYS_EN PW R_ CAP

1VSS_BBAT

TVCC _MVT VSS_BG PWR _SDA G PIO 125 F

GMD4 MD5 DQS0 VCC_MEM VSS_MEM G

HMD7 MA2 MD6 VSS_MEM VCC_MVT VSS VSS VCC_APPS VSS TEST H

JMA6 MA15 MA14 VCC_MEM VSS_MEM VSS J

KSDMA10 MA8 MA4 VCC_MEM VSS_MEM VCC_APPS K

LSDCLK0 SDCLK1 MA12 VCC_APPS VSS_MEM VSS L

MMA0 NSDCS1 NSDCS0 MA13 VSS VSS M

NMA9 MA11 MA7 VCC_MEM VSS_MEM VSS N

PRCOMP_D

DR NSDRAS MA5 MA3 VCC_MVT VSS P

RRFU_R1 SDCKE NSDWE MA1 VSS_MEM VCC_APPS R

TMD9 MD8 NSDCAS VC C_MEM VSS_MEM VSS T

UDQM1 MD11 MD10 VSS VCC_MVT VSS VSS VCC_APPS VSS VSS U

VMD13 MD12 DQS1 VCC_MEM VSS_MEM V

WGPIO0 MD14 MD15 NC DF_CLE_N

OE NC NC NC DF_NCS0 VCC_SRA

MNC W

YGPIO2 VCC_MEM VSS_MEM VSS_DF VCC_DF DF_IO0 VSS_DF NC VSS_DF VSS_DF DF_IO7 Y

AA NCS1 GPIO1 DF_INT_R

NB AA

AB NCS0 D F_NWE DF_NRE VCC_DF DF_AD DR1 NC VCC_DF DF_IO9 DF_IO3 VCC_DF NLLA DF_IO13 AB

AC NC DF_ALE_N

WE NBE1 DF_ADDR0 DF_ADDR3 NC DF_IO1 VCC_MVT VCC_APPS VSS DF_SCLK_

EVCC_DF AC

AD NC NC NBE0 DF_ADD R2 DF_IO8 DF_IO2 DF_IO10 VSS DF_IO11 NLUA RFU_AD11 DF_IO4 AD

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PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 62 April 6, 2009 Released

Figure 45: PXA300 Processor 13mm2 VF-BGA Ball Map, Right side

13 14 15 16 17 18 19 20 21 22 23 24

AGPIO0_2 GPIO126 GPIO115 GPIO116 GPIO107 VSS_ IO1 GPIO110 GPIO102 GPIO100 GPIO97 NC NC A

BGPIO123 GPIO119 GPIO113 GPIO99 VCC_APPS VCC_MVT GPIO101 GPIO106 VC C_SRA

MVSS_IO1 GPIO96 NC B

CVSS_PLL VCC_APPS GPIO118 VCC_IO1 VSS GPIO108 GPIO104 GPIO103 VCC_MVT GPIO92 GPIO94 GPIO98 C

DGPIO91 GPIO90 GPIO95 D

EGPIO121 GPIO117 GPIO111 GPIO11 4 NC RFU_E18 NC R FU_E20 GPIO88 GPIO87 GPIO93 E

FGPIO124 GPIO122 GPIO120 GPIO109 GPIO105 R FU_F18 RFU_ F19 GPIO84 GPIO85 GPIO83 VCC_IO1 F

GGPIO75 VSS_MSL GPIO82 GPIO81 GPIO89 G

HVSS VSS VCC_APPS GPIO112 VSS GPIO71 VCC_MSL GPIO77 GPIO80 GPIO86 H

JVSS GPIO63 GPIO79 GPIO74 GPIO76 GPIO78 J

KVCC_APPS VCC_LCD GPIO69 GPIO66 GPIO72 GPIO73 K

LVSS GPIO60 GPIO68 GPIO65 GPIO67 GPIO70 L

MVSS GPIO59 VSS_LCD GPIO61 GPIO62 GPIO64 M

NRFU_N17 VCC_MVT GPIO52 GPIO55 GPIO57 GPIO51 N

PRFU_P17 GPIO58 GPIO49 GPIO47 GPIO54 GPIO56 P

RVC C_APPS GPIO 48 GPIO45 VCC_CI GPIO53 GPIO50 R

TGPIO46 VSS_CI GPIO44 GPIO42 VSS VCC_APPS T

UVSS VSS VCC _APPS VSS RFU_U17 GPIO39 VSS_IO3 GPIO38 GPIO41 GPIO43 U

VGPIO37 GPIO35 VCC_IO3 GPIO36 GPIO40 V

WDF_IO12 VSS_DF GPIO2_2 VCC_MVT GPIO18 GPIO33 GPIO27 GPIO3 _2 GPIO31 GPIO32 GPIO34 W

YVSS_DF DF_IO14

VSS_CARD

1GPIO8 G PIO 15 GPIO4_ 2 GPIO6 _2 G PIO5 _2 GPIO21 GPIO28 GPIO29 Y

AA GPIO30 GPIO25 GPIO26 AA

AB VCC_DF GPIO3 GPIO5 VCC_APPS GPIO7 GPIO10 GPIO11 VCC_IO3 GPIO19 GPIO23 GPIO20 VSS_IO3 AB

AC DF_NCS1 GPIO4

VCC_CARD

1VSS VSS VSS_CARD

2GPIO 13 GP IO 12 GPI O17 VCC_ PL L GPIO22 NC AC

AD DF_IO5 DF_IO6 DF_IO15 GPIO9 GPIO6 VCC_CARD

2GPIO16 GPIO14 VSS_PLL GPIO24 NC NC AD

13 14 15 16 17 18 19 20 21 22 23 24

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April 6, 2009 Released Page 63

4.1.4 PXA30x Processor and PXA302 Processor 15mm2

Multi-Chip Package (MCP) and Package on Package (POP)

Bottom Ball Map

Figure 46 and Figure 47 show the bottom ball map for the PXA30x processor 15mm2 MCP and POP

p ackages.The balls highlig hted in y e llow have different functionality on the PXA31x processor.

Figure 46: PXA30x 15mm2 MCP and Package-on-Package (PoP) Bottom Ball Map, Left side

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AVSS_USB VSS_USB USBOTG_N USBOTG_P USBH1_N NTRST PWR_CAP0 TXTAL_IN VSS VCC_APPS GPIO0_2 A

BVSS_USB VSS_USB VCC_USB NC USBH1_P CLK_TOUT EXT_WAKE

UP0 TXTAL_OUT PXTAL_IN PWR_SDA TEST B

CNC VSS TMS TCK NC

NBATT_FAU

LT PWR_OUT VCC_BBATT PXTAL_OUT VSS_BG CLK_POUT C

DMD0 TDO PWR_EN SYS_EN VCC_MEM NRESET VSS VSS_BBATT VCC_OSC1

3M VCC_BG GPIO1_2 D

EMD1 MD2 TDI VCC _MVT G PIO 3_2 GPIO2_2 G PIO6_2 NGPIO_RES

ET VSS_OSC13

MVCTCXO_E

NVSS_PLL E

FMD3 MD4 DQS0 VSS GPIO5_2 VSS_MEM VSS_MEM PWR_CAP1 NRESET_O

UT PWR_SCL TESTCLK F

GMD5 MD6 DQM0 NC VCC_MEM VC C_MEM VSS_MEM GPIO4_2 VCC_MVT VCC_IO1 VCC_DF G

HM D7 M A1 4 M A2 M A 4 M A13 VC C_M EM V S S_M EM V SS V SS V CC_A PP S VCC_ AP PS H

JMA8 NSDCS1 SDMA10 MA15 VCC_MVT VCC_MEM VSS_MEM RFU_J8 J

KSDCLK0 SDCLK1 MA12 MA6 VSS VCC_MEM VSS_MEM RFU_K8 K

LNSD CS0 MA 9 M A0 NC V CC_A P PS VC C_M EM V S S_M EM N C L

MMA3 MA7 MA5 MA11 VSS VCC_MEM VSS_MEM NC M

NRCOMP_DD

RRFU_N2 NSDCAS MA1 VCC_APPS VCC_MEM VSS_MEM RFU_N8 N

PNSDWE NSDRAS MD 8 NC NC VCC_MEM VSS_MEM RFU_P8 VSS VCC_APPS VCC_APPS P

RMD10 SDCKE MD9 DQS1 VSS VCC_MEM VSS_MEM VSS VSS_DF VSS_DF VSS_DF R

TMD12 MD 11 MD14 DQM1 VCC_MVT VCC_MEM VSS_MEM VSS VCC_DF VCC_DF VCC_DF T

UMD15 MD 13 NC G PIO1 DF_NW P VC C_MEM VSS_MEM D F_IO8 VCC_MVT DF_NCS1 GPIO3 U

VGPIO2 NC GPIO0 NCS1 VCC_MEM DF_ADDR1 DF_ALE_N

WE DF_CLE_N

OE DF_NCS0 DF_IO4 DF_IO7 V

WNCS0 NC DF_IN T_RN

BDF_NWE DF_NRE DF_ADDR2 DF_IO2 DF_IO11 RFU_W9 DF_IO13 DF_IO14 W

YVSS_DF VSS_DF NBE0 DF_ADDR3 DF_IO9 DF_IO10 VSS D F_IO3 NLUA NLLA VCC_CARD

AA VSS_DF VSS_DF NBE1 DF_ADDR0 DF_IO0 DF_IO1 VCC_APPS VCC_SRAM VC C_APPS DF_SC LK_E GPIO4 AA

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PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 64 April 6, 2009 Released

4.1.5 PXA303 Processor 19mm2 VF-BGA Ball

Figure 48 and Figure 49 show the bottom ball map for the PXA303 processor 19mm2 discrete

package.

Figure 47: PXA30x Processor 15mm2 MCP and Package-on-Package (PoP, Bottom) Ball Map,

Right side

12 13 14 15 16 17 18 19 20 21

AGPIO126 VCC_APPS GPIO116 VCC_APPS GPIO110 GPIO102 GPIO99 GPIO96 VSS VSS A

BGPIO124 VSS GPIO120 GPIO112 VSS GPIO106 GPIO100 VCC_SRAM VSS VSS B

CGPIO127 GPIO 115 GPIO122 GPIO113 GPIO107 GPIO108 VCC_ SRAM GPIO101 GPIO95 GPIO98 C

DVCC_PL L GPIO123 GPIO118 GPIO114 GPIO109 GPIO105 GPIO103 N C GPIO97 GPIO94 D

EVSS_PLL GPIO119 GPIO117 VCC_IO1 GPIO86 GPIO89 GPIO91 GPIO104 GPIO93 GPIO92 E

FGPIO125 GPIO121 GPIO111 VSS_IO1 GPIO79 VSS_MSL GPIO87 GPIO85 GPIO88 GPIO90 F

GVSS_DF VSS_IO1 VCC_MVT VCC_IO1 GPIO78 VCC_MSL GPIO81 GPIO83 GPIO82 GPIO84 G

HVCC_APPS VSS VSS VCC_MVT GPIO73 GPIO74 GPIO75 GPIO77 GPIO76 GPIO80 H

JVSS VCC _MVT GPIO7 1 GPIO65 GPIO67 G PIO6 9 GPIO70 GPIO72 J

KVCC_APPS VSS_LCD VCC_LCD GPIO64 GPIO68 GPIO61 GPIO63 GPIO66 K

LVCC_APPS VSS_LCD VCC_LCD GPIO59 GPIO56 GPIO62 GPIO58 GPIO60 L

MVCC_APPS VSS_LCD VCC_LCD GPIO53 GPIO55 GPIO57 GPIO52 GPIO54 M

NVSS VCC_MVT GPIO47 GPIO49 GPIO50 GPIO51 VSS VCC_APPS N

PVCC_APPS VSS VSS VCC_CI GPIO43 GPIO45 GPIO46 VSS_CI VCC_CI GPIO48 P

RVSS_DF VSS_DF VCC_MVT RFU_R15 RFU_R16 GPIO37 GPIO39 GPIO42 GPIO41 GPIO44 R

TVC C_DF VCC_DF VSS VSS_IO3 VCC_IO3 GPIO38 GPIO35 GPIO40 GPIO34 GPIO36 T

UGPIO9 NC GPIO8 D F_IO1 2 G PIO1 2 GPIO19 GPIO31 G PIO3 3 GPIO32 GPIO28 U

VGPIO5 GPIO6 GPIO11 GPIO13 GPIO16 RFU_V17 GPIO20 GPIO29 GPIO30 GPIO27 V

WDF_IO6 DF_IO5 GPIO7 D F_IO15 VSS_ PLL G PIO17 GPIO18 GPIO21 RFU_W 20 RFU_W21 W

YVSS_CARD

1VCC_APPS GPIO10 GPIO14 GPIO15 GPIO23 GPIO25 GPIO26 VSS_IO3 VSS_IO3 Y

AA VCC_APPS VSS VCC_CARD

2VSS_CARD

2VCC_PLL GPIO22 GPIO24 NC VSS_IO3 VSS_IO3 AA

12 13 14 15 16 17 18 19 20 21

Versi on -

April 6, 2009 Released Page 65

Figure 48: PXA303 Processor 19mm2 VF-BGA Ball Map, Left side

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ANC NC USBH1_N USBH 1_P NBATT_FA

ULT PW R_C AP

0NGPIO_RE

SET VCC_OSC1

3M PW R_SCL TEST GPIO1_2 GPIO127 A

BNC NC USBOTG_P VCC_USB SYS_EN PWR_OUT VSS_BBAT

TPXTAL_IN VCC_BG TESTCLK VCC_IO1 GPIO0_2 B

CMD2 MD1 USBOTG_

NVSS_USB NTRST VSS TXTAL_OU

TPXTAL_OU

TVSS_OSC1

3M PWR_ SD A CLK_PO UT G PIO 126 C

DVCC_MEM DQS0 MD 0 TMS TDO CLK_TOUT VCC_BBAT

TTXT AL _IN NRESET_O

UT VCC_MVT VSS_BG VSS_IO1 D

EMD5 VSS_MEM DQM0 PWR_EN TDI TCK EXT_WAKE

UP0 NRESET PWR_CAP

1VSS VCC_APPS

VCTCXO_E

FMD7 MD6 MD4 VSS_MEM VSS_MEM F

GMA14 MA15 VCC_MEM MD3 VCC_MEM G

HMA8 MA6 MA4 VSS_MEM VCC_MVT H

JVCC_MEM VSS_MEM MA12 MA2 VSS VSS VSS VSS VSS J

KNSDCS0 NSDCS1 SDCLK0 SDCLK1 SDMA10 VSS VSS VSS VSS K

LMA13 MA11 MA0 VCC_APPS VSS VSS VSS VSS VSS L

MMA5 MA7 MA9 VSS_MEM VCC_MEM VSS VSS VSS VSS M

NMA1 NSDRAS NSDCAS MA3 RCOMP_D

DR VSS VSS VSS VSS N

PNSDWE SDCKE VCC_MVT RFU VSS_MEM VSS VSS VSS VSS P

RMD8 MD9 MD10 MD11 VCC_MEM VSS VSS VSS VSS R

TDQM1 DQS1 MD12 VSS_MEM VCC_MEM T

UMD13 MD14 MD15 VSS_MEM NCS1 U

VGPIO0 GPIO1 GPIO2 VCC_DF VSS_DF V

WNCS0 DF_IN T_R

NB DF_NWE DF_NRE NBE0 VCC_DF VSS_DF VCC_DF VCC_APPS NC VSS_DF VSS W

YDF_ADDR2 DF_ADDR 1 DF_ALE_N

WE NBE1 DF_ADDR0 DF_AD DR3 DF_IO9 D F_IO10 VC C_S RA

MVSS VCC_DF VCC_APPS Y

AA DF_IO0 DF_IO8 DF_IO1 DF_IO2 NC VSS VCC_MVT NLUA DF_SCLK_

EDF_IO6 GPIO3

VC C_CARD

1AA

AB NC NC DF_CLE_N

OE DF_IO11 DF_IO3 DF_NCS0 NLLA D F_IO12 DF_IO7 DF_NCS1 GPIO5

VSS_CARD

1AB

AC NC NC DF_IO4 DF_IO5 DF_IO13 DF_IO14 DF_IO15 GPIO4 GPIO6 GPIO7 GPIO9 GPIO10 AC

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PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 66 April 6, 2009 Released

Figure 49: PXA303 Processor 19mm2 VF-BGA Ball Map, Right side

13 14 15 16 17 18 19 20 21 22 23

AGPIO 125 GPIO122 GPIO120 GPIO11 5 GPIO11 2 GPIO10 9 GPIO1 06 G PIO1 02 G PIO1 01 NC NC A

BGPIO 124 GPIO121 GPIO117 GPIO11 4 GPIO11 0 GPIO10 8 GPIO1 03 G PIO1 00 RFU_ B2 1 NC NC B

CVCC_PLL GPIO118 GPIO116 GPIO11 1 GPIO10 7 GPIO10 5 RF U_C1 9 RF U_C2 0 GPIO97 GPIO96 GPIO93 C

DVSS_PLL GPIO123 GPIO119 VSS_IO1 GPIO104 RFU_D18 VCC _SRA

MGPIO98 GPIO95 GPIO92 GPIO90 D

EVSS VCC _APPS GPIO113 VCC _IO1 VCC_MVT GPIO99 VSS_IO1 GPIO94 GPIO91 GPIO87 GPIO86 E

FVCC_IO1 GPIO89 GPIO88 GPIO85 GPIO83 F

GVSS VCC_MVT GPIO84 GPIO81 GPIO80 G

HVSS_MSL VCC_MSL GPIO82 GPIO78 GPIO77 H

JVSS VSS VSS GPIO75 GPIO79 GPIO76 GPIO74 GPIO73 J

KVSS VSS VSS VCC_LCD VSS_LCD GPIO71 GPIO72 GPIO70 K

LVSS VSS VSS GPIO69 GPIO67 GPIO65 GPIO68 GPIO66 L

MVSS VSS VSS VCC_LCD VSS_LCD GPIO63 GPIO64 GPIO62 M

NVSS VSS VSS GPIO57 GPIO54 GPIO59 GPIO60 GPIO61 N

PVSS VSS VSS VCC_MVT GPIO52 GPIO55 GPIO56 GPIO58 P

RVSS VSS VSS VCC_CI VCC_APPS GPIO50 GPIO51 GPIO53 R

TVSS_CI GPIO41 GPIO47 GPIO48 GPIO49 T

UGPIO27 VSS_IO3 GPIO44 GPIO45 GPIO46 U

VNC NC GPIO36 GPIO42 GPIO43 V

WVCC_APPS VCC_MVT VSS_PLL VCC_PLL GPIO25 GPIO6_2 NC GPIO30 VCC_IO3 GPIO39 GPIO40 W

YVSS

VCC_CARD

2GPIO15 GPIO19 GPIO24 GPIO4_ 2 NC NC GPIO31 GPIO37 GPIO38 Y

AA GPIO8

VSS_CARD

1GPIO16 VCC _IO3 GPIO23 GPIO3_ 2 NC NC GPIO33 GPIO34 GPIO35 AA

AB GPIO11 GPIO13 GPIO18 VSS_IO3 GPIO22 GPIO2_2 NC NC GPIO32 NC NC AB

AC GPIO12 GPIO14 GPIO17 GPIO20 GPIO21 GPIO26 GPIO5_2 GPIO28 GPIO29 NC NC AC

13 14 15 16 17 18 19 20 21 22 23

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April 6, 2009 Released Page 67

4.1.6 PXA312 and PXA302 Package on Package (POP) Top Ball

Maps

4.1.6.1 PXA312 and PXA3 02 Proc ess or 15mm2 Package-on-Package (PoP)

Top Ball Map

Figure 50: PXA302 Processor and PXA312 Processor PoP Top Ball Map, Left Side

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ANC VSS_MEM NC VSS_DF NC NC NC NC VSS_DF DF_CLE_N

OE NC A

BVSS_MEM VCC_MEM NC VCC_DF NC NC NC NC VCC_DF DF_ALE_N

WE NC B

CDF_NWE DF_INT_R

NB C

DMD1 MD0 D

EVSS_MEM VCC_MEM E

FMD3 MD2 F

GMD5 MD4 G

HVSS_MEM VCC_MEM H

JMD7 MD6 J

KDQM0 DQS0 K

LDQM1 DQS1 L

MVSS_MEM VCC_MEM M

NMD9 MD8 N

PVSS_MEM VCC_MEM P

RMD11 MD10 R

TMD13 MD12 T

UVSS_MEM VCC_MEM U

VMD15 MD14 V

WSDCKE SDCLK0 W

YNC SDCLK1 Y

AA NC VSS_DF VCC_DF DF_IO0 VCC_DF DF_IO2 DF_IO4 VCC_DF DF_IO6 NC DF_SCLK_

EAA

AB NC VCC_MEM VSS_DF DF_IO1 VSS_DF DF_IO3 DF_IO5 VSS_DF DF_IO7 NC NC AB

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PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 68 April 6, 2009 Released

4.2 Pin Use Tables

These tables include the ball number, ball name, an d type for each of pins. See Table 12 to decode

the p in “Type”. Also included is t he sta te of each pin with respect to reset and power modes.

Additionally, at the beginning of each group of pins is th e power domain that powers all the pins in

that gr oup. For example, the VCC_BATT group of pins in Table 11 starts with ball C6 and ends with

C8. The next group of pins are on the VCC_IO1 domain.

Figure 51: PXA302 Processor and PXA312 Processor PoP Top Ball Map, Right Side

NOTE: The DF_nWP signal is used as a write-protect pin for packages that use NAND devices (F22) and as a reset signal

for packages that use a S t atic Memory Controller (SMC) device on GPIO1 (nCS2) (C21). The DF_nWP signal on

the bott om pa cka ge must be connect ed to eithe r an ext er nal reset c ircu it or tied accor di ngly for write pr ot ection of

the NAND device. When making connections to the DF_nWP pin, hardware must ensure the proper voltage levels

are used for the voltage requirements on the top package. For example, when connecting nRESET_OUT (3V) to

DF_n WP as a reset for a OneNAND device (1.8V) , a le vel shifter must be us ed to reduce the voltage .

12 13 14 15 16 17 18 19 20 21 22

ANC NC NC VSS_DF NC NC NC NC NC VSS_DF NC A

BNC NC NC VCC_DF NC NC NC NC VCC_DF VCC_DF VSS_DF B

CDF_NWP NC C

DGPIO1 GPIO2 D

EDF_NCS0 DF_NCS1 E

FDF_NRE DF_NWP F

GDF_ALE_

NWE NC G

HNSDWE DF_CLE_

NOE H

JVCC_ME

MVSS_ME

KMA0 MA1 K

LMA2 MA3 L

MMA4 MA5 M

NMA6 MA7 N

PMA14 MA15 P

RNSDCS0 NSDCS1 R

TNSDRAS NSDCAS T

UMA8 MA9 U

VSD M A 10 M A 11 V

WMA12 MA13 W

YNC VSS_ME

AA VCC_DF NC DF_IO8 VCC_DF DF_IO10 DF_IO12 VCC_DF DF_IO14 NLLA VCC_ME

MNC AA

AB VSS_DF NC DF_IO9 VSS_DF DF_IO11 DF_IO13 VSS_DF DF_IO15 NC VCC_DF NC AB

12 13 14 15 16 17 18 19 20 21 22

Versi on -

April 6, 2009 Released Page 69

Each multi-function pin (MFP) signal alternate fu nction inputs and outputs are shown in the PXA3xx

Processor Family Vol. I: System and Timer Configuration Developers Manual, “Pin De sc rip tio n and

Control” chapter.

4.2.1 PXA32x Proces sor Pin Use

Table 9 lists the mapping of signals to specific PXA32x processor package pins.

Table 9: PXA32x Processor Pin Usage Summary

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

VCC_BBATT

C6 C6 CLK_TOUT CLK_TOUT OC Clk-Out 44

H8 G5 EXT_WAKEUP0 EXT_WAKEUP0 ICOCZ Pd-011 Pd-011 Pd-011

H6 F5 EXT_WAKEUP1 EXT_WAKEUP1 ICOCZ Pu-111 Pu-111 Pu-111

E9 B7 NBATT_FAULT nBATT_FAULT IC Input Input Input

D7 A11 NGPIO_RESET nGPIO_RESET IC Pu-111 Pu-111 Pu-111

B7 E6 NRESET nRESET IC Input7Input Input

G9 C9 NRESET_OUT nRESET_OUT OC Low 12 12

F7 D6 NTRST nTRST IC Input7Input7Input7

B8 D7 PWR_CAP0 PWR_CAP0 OA - - -

G8 C7 PWR_CAP1 PWR_CAP1 OA - - -

A6 A7 PWR_EN PWR_EN OC Low Low Low

C7 B8 PWR_OUT PWR_OUT OA - - -

G7 E5 SYS_EN SYS_EN OC Low Low High

E4 B4 TCK TCK IC Input Input Input

A5 B6 TDI TDI IC Input7Input7Input7

F6 D5 TDO TDO OCZ Hi-Z Hi-Z Hi-Z

E7 A8 TMS TMS IC Input7Input7Input7

A7 D8 TXTAL_IN TXTAL_IN IA 222

A8 C8 TXTAL_OUT TXTAL_OUT OA 222

VCC_MVT

F9 B10 PXTAL_IN PXTAL_IN IA 222

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 70 April 6, 2009 Released

E10 C10 PXTAL_OUT PXTAL_OUT OA 222

VCC_IO1

D9 D11 CLK_POUT CLK_POUT OC Low Float Low

H12 B18 GPIO113 GPIO113 ICOCZ Pd-01Float13

B14 A17 GPIO114 GPIO114 ICOCZ Pd-01Float13

H13 C17 GPIO115 GPIO115 ICOCZ Pd-01Float13

A15 D17 GPIO116 GPIO116 ICOCZ Pd-01Float13

G14 E16 GPIO117 GPIO117 ICOCZ Pd-01Float13

B13 C16 GPIO118 GPIO118 ICOCZ Pd-01Float13

K8 B17 GPIO119 GPIO119 ICOCZ Pd-01Float13

A14 E14 GPIO120 GPIO120 ICOCZ Pd-01Float13

D12 B16 GPIO121 GPIO121 ICOCZ Pd-01Float13

B12 C15 GPIO122 GPIO122 ICOCZ Pd-01Float13

G13 A16 GPIO123 GPIO123 ICOCZ Pd-01Float13

C13 D14 GPIO124 GPIO124 ICOCZ Pd-01Float13

E13 E13 GPIO125 GPIO125 ICOCZ Pd-01Float13

A13 A15 GPIO126 GPIO126 ICOCZ Pd-01]Float

H10 D13 GPIO127 GPIO127 ICOCZ Pd-01Float13

A12 E12 GPIO0_2 GPIO0_2 ICOCZ Pu-11Float13

G11 B14 GPIO1_2 GPIO1_2 ICOCZ Pu-11Float13

C11 C13 GPIO2_2 GPIO2_2 ICOCZ Pd-01Float13

F13 A14 GPIO3_2 GPIO3_2 ICOCZ Pd-01Float13

A11 B13 GPIO4_2 GPIO4_2 ICOCZ Pd-01Float13

E11 D12 GPIO5_2 GPIO5_2 ICOCZ Pd-01Float13

H11 C11 PWR_SCL PWR_SCL ICOCZ Pu-111 Pu-111 Float1

A10 A12 PWR_SDA PWR_SDA ICOCZ Pu-111 Pu-111 Float1

D10 A13 TEST TEST IC Input

5Input5Input5

G12 C12 TESTCLK TESTCLK IC Input5Input 5Input5

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 71

F11 B12 VCTCXO_EN VCTCXO_EN OC Low Float Low

VCC_DF

W7 AC8 DF_ADDR0 DF_ADDR0 OCZ Pd-01Float13

W8 AD8 DF_ADDR1 DF_ADDR1 OCZ Pd-01Float13

V8 AF8 DF_ADDR2 DF_ADDR2 OCZ Pd-01Float13

Y8 AE9 DF_ADDR3 DF_ADDR3 OCZ Pd-01Float13

W1 AE5 DF_INT_RNB DF_RnB ICZ Pu-11Float13

U9 AD9 DF_IO0 DF_IO0 ICOCZ Pd-01Float13

P6 AC11 DF_IO1 DF_IO1 ICOCZ Pd-01Float13

U7 AD10 DF_IO2 DF_IO2 ICOCZ Pd-01Float13

T10 AF10 DF_IO3 DF_IO3 ICOCZ Pd-01Float13

T9 AC12 DF_IO4 DF_IO4 ICOCZ Pd-01Float13

U10 AF12 DF_IO5 DF_IO5 ICOCZ Pd-01Float13

V10 AE12 DF_IO6 DF_IO6 ICOCZ Pd-01Float13

W10 AF13 DF_IO7 DF_IO7 ICOCZ Pd-01Float13

V9 AB10 DF_IO8 DF_IO8 ICOCZ Pd-01Float13

V11 AF9 DF_IO9 DF_IO9 ICOCZ Pd-01Float13

R13 AE10 DF_IO10 DF_IO10 ICOCZ Pd-01Float13

Y9 AD11 DF_IO11 DF_IO11 ICOCZ Pd-01Float13

T11 AB13 DF_IO12 DF_IO12 ICOCZ Pd-01Float13

T14 AD12 DF_IO13 DF_IO13 ICOCZ Pd-01Float13

R8 AB14 DF_IO14 DF_IO14 ICOCZ Pd-01Float13

P10 AC13 DF_IO15 DF_IO15 ICOCZ Pd-01Float13

D8 AF3 DF_ALE_NWE1 DF_ALE OCZ Pu-11Float13

T7 AB6 DF_ALE_NWE2 DF_ALE OCZ Pu-11Float13

P8 AE6 DF_NCS0 DF_nCS0 OCZ Pu-11Float13

B5 AF6 DF_NCS1 DF_nCS1 OCZ Pu-11Float13

U6 AD7 DF_NRE DF_nOE OCZ Pu-11Float13

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 72 April 6, 2009 Released

T8 AF7 DF_NWE DF_nWE OCZ Pu-11Float13

W5 AF4 DF_SCLK_E DF_SCLK_E OCZ Pd-01Float13

V3 AC2 GPIO2 GPIO2 ICOCZ Pd-01Float13

R6 AD2 GPIO3 GPIO3 ICOCZ Pu-11Float13

M8 AD3 GPIO4 GPIO4 ICOCZ Pu-11Float13

P11 AF14 GPIO5 GPIO5 ICOCZ Pu-11Float13

W12 AE14 GPIO6 GPIO6 ICOCZ Pu-11Float13

R10 AB15 GPIO7 GPIO7 ICOCZ Pu-11Float13

AA12 AC15 GPIO8 GPIO8 ICOCZ Pu-11Float13

T6 AE4 NBE0 nBE0 OCZ Pu-11Float13

Y6 AF5 NBE1 nBE1 OCZ Pu-11Float13

C10 AD5 DF_CLE_NOE ND_CLE OCZ Pu-11Float13

AA8 AE8 NLLA nLLA OCZ Pu-11Float13

U8 AE7 NLUA nLUA OCZ Pu-11Float13

V5 AE3 NXCVREN NXCVREN OCZ Pu-11Float13

VCC_IO3

P12 AF16 GPIO9 GPIO9 ICOCZ Pu-11Float13

V13 AB16 GPIO11 GPIO11 ICOCZ Pd-01Float13

U13 AB17 GPIO12 GPIO12 ICOCZ Pd-01Float13

Y13 AF17 GPIO13 GPIO13 ICOCZ Pd-01Float13

P13 AC17 GPIO14 GPIO14 ICOCZ Pu-11Float13

Y14 AF19 GPIO15 GPIO15 ICOCZ Pu-11Float13

T13 AB19 GPIO16 GPIO16 ICOCZ Pu-11Float13

U14 AC19 GPIO17 GPIO17 ICOCZ Pu-11Float13

VCC_IO4

P14 W25 GPIO10 GPIO10 ICOCZ Pd-01Float13

U20 AC23 GPIO30 GPIO30 ICOCZ Pd-01Float13

U12 AD24 GPIO31 GPIO31 ICOCZ Pd-01Float13

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 73

V20 AA22 GPIO32 GPIO32 ICOCZ Pu-11Float13

V18 AD25 GPIO33 GPIO33 ICOCZ Pu-11Float13

T18 AC24 GPIO34 GPIO34 ICOCZ Pd-01Float13

U17 AD26 GPIO35 GPIO35 ICOCZ Pd-01Float13

T17 AC25 GPIO36 GPIO36 ICOCZ Pd-01Float13

T16 AB25 GPIO37 GPIO37 ICOCZ Pd-01Float13

T20 AC26 GPIO38 GPIO38 ICOCZ Pd-01Float13

T15 Y22 GPIO39 GPIO39 ICOCZ Pd-01Float13

T19 AA23 GPIO40 GPIO40 ICOCZ Pu-11Float13

R16 Y23 GPIO41 GPIO41 ICOCZ Pd-01Float13

R20 AA24 GPIO42 GPIO42 ICOCZ Pd-01Float13

R15 W22 GPIO43 GPIO43 ICOCZ Pu-11Float13

R19 AA25 GPIO44 GPIO44 ICOCZ Pu-11Float13

P16 W24 GPIO45 GPIO45 ICOCZ Pu-11Float13

R18 Y26 GPIO46 GPIO46 ICOCZ Pu-11Float13

P18 Y25 GPIO47 GPIO47 ICOCZ Pu-11Float13

P20 V22 GPIO48 GPIO48 ICOCZ Pu-11Float13

VCC_CI

P19 W26 GPIO49 GPIO49 ICOCZ Pd-01Float13

P15 V23 GPIO50 GPIO50 ICOCZ Pd-01Float13

R21 U22 GPIO51 GPIO51 ICOCZ Pd-01Float13

M14 U23 GPIO52 GPIO52 ICOCZ Pd-01Float13

M18 T22 GPIO53 GPIO53 ICOCZ Pd-01Float13

M17 U25 GPIO54 GPIO54 ICOCZ Pd-01Float13

N19 U26 GPIO55 GPIO55 ICOCZ Pd-01Float13

M16 T24 GPIO56 CIF_DD7 ICOCZ Pd-01Float13

M19 R22 GPIO57 GPIO57 ICOCZ Pd-01Float13

N17 T23 GPIO58 GPIO58 ICOCZ Pd-01Float13

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 74 April 6, 2009 Released

M20 R24 GPIO59 CIF_MCLK ICOCZ Pd-01Float13

L15 R23 GPIO60 CIF_PCLK ICZ Pd-01Float13

K21 P24 GPIO61 CIF_HSYNC ICOCZ Pd-01Float13

L16 P26 GPIO62 CIF_VSYNC ICOCZ Pd-01Float13

VCC_IO6

G18 F22 GPIO83 GPIO83 ICOCZ Pd-01Float13

F16 D26 GPIO84 GPIO84 ICOCZ Pd-01Float13

F18 E23 GPIO85 GPIO85 ICOCZ Pd-01Float13

F17 E24 GPIO86 GPIO86 ICOCZ Pd-01Float13

D20 D22 GPIO87 GPIO87 ICOCZ Pu-11Float13

D16 C25 GPIO88 GPIO88 ICOCZ Pu-11Float13

F19 D25 GPIO89 GPIO89 ICOCZ Pu-11Float13

D17 C26 GPIO90 GPIO90 ICOCZ Pu-11Float13

E18 D24 GPIO91 GPIO91 ICOCZ Pd-01Float13

E21 D23 GPIO92 GPIO92 ICOCZ Pd-01Float13

E20 D21 GPIO93 GPIO93 ICOCZ Pd-01Float13

E16 B23 GPIO94 GPIO94 ICOCZ Pd-01Float13

C21 C23 GPIO95 GPIO95 ICOCZ Pd-01Float13

D21 C24 GPIO96 GPIO96 ICOCZ Pd-01Float13

D19 B25 GPIO97 GPIO97 ICOCZ Pd-01Float13

K14 B24 GPIO98 GPIO98 ICOCZ Pd-01Float13

C18 A24 GPIO99 GPIO99 ICOCZ Pu-11Float13

C17 A23 GPIO100 GPIO100 ICOCZ Pu-11Float13

D18 A22 GPIO101 GPIO101 ICOCZ Pu-11Float13

B18 A21 GPIO102 GPIO102 ICOCZ Pu-11Float13

C19 B21 GPIO103 GPIO103 ICOCZ Pu-11Float13

A18 E22 GPIO104 GPIO104 ICOCZ Pu-11Float13

C16 C21 GPIO105 GPIO105 ICOCZ Pu-11Float13

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 75

B19 A20 GPIO106 GPIO106 ICOCZ Pu-11Float13

D15 B20 GPIO107 GPIO107 ICOCZ Pd-01Float13

A17 E21 GPIO108 GPIO108 ICOCZ Pd-01Float13

R9 A19 GPIO109 GPIO109 ICOCZ Pu-11Float13

B16 B19 GPIO110 GPIO110 ICOCZ Pd-01Float13

R7 E19 GPIO111 GPIO111 ICOCZ Pd-01Float13

C15 C19 GPIO112 GPIO112 ICOCZ Pu-11Float13

VCC_LCD

K19 M24 GPIO63 GPIO63 ICOCZ Pu-11Float13

K17 L25 GPIO64 GPIO64 ICOCZ Pd-01Float13

J18 M26 GPIO65 GPIO65 ICOCZ Pd-01Float13

J17 K22 GPIO66 GPIO66 ICOCZ Pd-01Float13

J19 L24 GPIO67 GPIO67 ICOCZ Pd-01Float13

J15 L26 GPIO68 GPIO68 ICOCZ Pd-01Float13

J20 L23 GPIO69 GPIO69 ICOCZ Pd-01Float13

J14 K26 GPIO70 GPIO70 ICOCZ Pd-01Float13

H20 K23 GPIO71 GPIO71 ICOCZ Pd-01Float13

J16 K24 GPIO72 GPIO72 ICOCZ Pd-01Float13

H18 J22 GPIO73 GPIO73 ICOCZ Pu-11Float13

H17 J23 GPIO74 GPIO74 ICOCZ Pd-01Float13

N20 P25 GPIO6_2 GPIO6_2 ICOCZ Pd-01Float13

L14 P23 GPIO7_2 GPIO7_2 ICOCZ Pd-01Float13

L20 N23 GPIO8_2 GPIO8_2 ICOCZ Pd-01Float13

K15 M22 GPIO9_2 GPIO9_2 ICOCZ Pd-01Float13

L19 N25 GPIO10_2 GPIO10_2 ICOCZ Pd-01Float13

L18 L22 GPIO11_2 GPIO11_2 ICOCZ Pd-01Float13

L21 N26 GPIO12_2 GPIO12_2 ICOCZ Pd-01Float13

L17 M25 GPIO13_2 GPIO13_2 ICOCZ Pd-01Float13

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 76 April 6, 2009 Released

H16 K25 GPIO14_2 GPIO14_2 ICOCZ Pd-01Float13

H21 H22 GPIO15_2 GPIO15_2 ICOCZ Pd-01Float13

H15 J24 GPIO16_2 GPIO16_2 ICOCZ Pd-01Float13

H19 H25 GPIO17_2 GPIO17_2 ICOCZ Pd-01Float13

VCC_MEM

K1 C3 DQM0 DQM0 OC High High High

H2 F1 DQM1 DQM1 OC High High High

T3 V2 DQM2 DQM2 OC High High High

W4 AA3 DQM3 DQM3 OC High High High

J2 D2 DQS0 DQS0 ISOCZ Pd-0 Pd-0 Pd-0

M2 E1 DQS1 DQS1 ISOCZ Pd-0 Pd-0 Pd-0

AA10 W2 DQS2 DQS2 ISOCZ Pd-0 Pd-0 Pd-0

AA11 AA2 DQS3 DQS3 ISOCZ Pd-0 Pd-0 Pd-0

U3 AC4 GPIO0 GPIO0 ICOCZ Pd-01Pd-013

V4 AC3 GPIO1 GPIO1 ICOCZ Pd-01Pd-013

J8 K4 MA0 MA0 OC high high high

J3 J1 MA1 MA1 OC high high high

F5 J2 MA2 MA2 OC high high high

G4 H1 MA3 MA3 OC high high high

K7 T4 MA4 MA4 OC high high high

M21 P1 MA5 MA5 OC high high high

K6 R3 MA6 MA6 OC high high high

N21 P3 MA7 MA7 OC high high high

V21 N3 MA8 MA8 OC high high high

U21 P2 MA9 MA9 OC high high high

L2 P4 MA11 MA11 OC high high high

J6 L3 MA12 MA12 OC high high high

N8 L2 MA13 MA13 OC high high high

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 77

J4 K1 MA14 MA14 OC high high high

N18 L4 MA15 MA15 OC high high high

D2 B3 MD0 MD0 ICSOCZ Pd-0 Pd-0 Pd-0

C2 B2 MD1 MD1 ICSOCZ Pd-0 Pd-0 Pd-0

E2 C2 MD2 MD2 ICSOCZ Pd-0 Pd-0 Pd-0

E1 C4 MD3 MD3 ICSOCZ Pd-0 Pd-0 Pd-0

F2 C1 MD4 MD4 ICSOCZ Pd-0 Pd-0 Pd-0

F1 D3 MD5 MD5 ICSOCZ Pd-0 Pd-0 Pd-0

J1 E2 MD6 MD6 ICSOCZ Pd-0 Pd-0 Pd-0

G3 D1 MD7 MD7 ICSOCZ Pd-0 Pd-0 Pd-0

R2 E3 MD8 MD8 ICSOCZ Pd-0 Pd-0 Pd-0

G5 F3 MD9 MD9 ICSOCZ Pd-0 Pd-0 Pd-0

N1 F2 MD10 MD10 ICSOCZ Pd-0 Pd-0 Pd-0

G6 G3 MD11 MD11 ICSOCZ Pd-0 Pd-0 Pd-0

T2 H3 MD12 MD12 ICSOCZ Pd-0 Pd-0 Pd-0

H5 G2 MD13 MD13 ICSOCZ Pd-0 Pd-0 Pd-0

W2 G1 MD14 MD14 ICSOCZ Pd-0 Pd-0 Pd-0

H4 H2 MD15 MD15 ICSOCZ Pd-0 Pd-0 Pd-0

Y3 V4 MD16 MD16 ICSOCZ Pd-0 Pd-0 Pd-0

N5 V3 MD17 MD17 ICSOCZ Pd-0 Pd-0 Pd-0

Y5 V1 MD18 MD18 ICSOCZ Pd-0 Pd-0 Pd-0

AA4 W1 MD19 MD19 ICSOCZ Pd-0 Pd-0 Pd-0

AA6 Y1 MD20 MD20 ICSOCZ Pd-0 Pd-0 Pd-0

AA7 AA1 MD21 MD21 ICSOCZ Pd-0 Pd-0 Pd-0

W3 Y3 MD22 MD22 ICSOCZ Pd-0 Pd-0 Pd-0

AA9 W3 MD23 MD23 ICSOCZ Pd-0 Pd-0 Pd-0

R3 Y2 MD24 MD24 ICSOCZ Pd-0 Pd-0 Pd-0

Y11 AA4 MD25 MD25 ICSOCZ Pd-0 Pd-0 Pd-0

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 78 April 6, 2009 Released

Y4 AB1 MD26 MD26 ICSOCZ Pd-0 Pd-0 Pd-0

W9 AB4 MD27 MD27 ICSOCZ Pd-0 Pd-0 Pd-0

U4 AC1 MD28 MD28 ICSOCZ Pd-0 Pd-0 Pd-0

T4 AD1 MD29 MD29 ICSOCZ Pd-0 Pd-0 Pd-0

AA5 AB3 MD30 MD30 ICSOCZ Pd-0 Pd-0 Pd-0

U5 AB2 MD31 MD31 ICSOCZ Pd-0 Pd-0 Pd-0

T21 R4 NSDCAS nSDCAS OC High High High

K4 L1 NSDCS0 nSDCS0 OC High High High

J7 N4 NSDCS1 nSDCS1 OC High High High

L4 N2 NSDRAS nSDRAS OC High High High

H3 M3 NSDWE nSDWE OC High High High

L1 R1 RCOMP_DDR RCOMP_DDR OA - - -

U2 M2 SDCKE SDCKE OC Low Low Low

Y2 M1 SDCLK0 SDCLK0 OC Low Low Low

M6 N1 SDCLK1 SDCLK1 OC High High High

K3 K2 SDMA10 SDMA10 OC High High High

VCC_MSL

F20 H23 GPIO75 GPIO75 ICOCZ Pd-01Float13

G15 H24 GPIO76 GPIO76 ICOCZ Pd-01Float13

G21 G24 GPIO77 GPIO77 ICOCZ Pd-01Float13

G16 G22 GPIO78 GPIO78 ICOCZ Pd-01Float13

F21 F25 GPIO79 GPIO79 ICOCZ Pd-01Float13

H14 F23 GPIO80 GPIO80 ICOCZ Pd-01Float13

G20 E25 GPIO81 GPIO81 ICOCZ Pd-01Float13

K16 E26 GPIO82 GPIO82 ICOCZ Pu-11Float13

VCC_TSI

F15 D19 TSI_XM TSI_XM IAOA Hi-Z Hi-Z Hi-Z

A16 E18 TSI_XP TSI_XP IAOA Hi-Z Hi-Z Hi-Z

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 79

C14 D18 TSI_YM TSI_YM IAOA Hi-Z Hi-Z Hi-Z / 08

B17 E17 TSI_YP TSI_YP IAOA Hi-Z Hi-Z Hi-Z

VCC_USB

E5 A5 USBH1_N USBH1_N IAOA Pd-0 Note[8]Pd-0

8Pd-08

E6 A6 USBH1_P USBH1_P IAOA Pd-0 Note[8]Pd-0

8Pd-08

D5 A3 USBOTG_N USBOTG_N IAOA Hi-Z Hi-Z or

Pd-09Hi-Z or

Pd-09

C5 A4 USBOTG_P USBOTG_P IAOA Hi-Z Hi-Z or

Pd-0 or

Pu-18,10

Hi-Z or

Pd-0 or

Pu-18,10

VCC_CARD1

W15 AE20 GPIO18 GPIO18 ICOCZ Pd-01Float13

W16 AB20 GPIO19 GPIO19 ICOCZ Pd-01Float13

U15 AC21 GPIO20 GPIO20 ICOCZ Pd-01Float13

AA16 AF22 GPIO21 GPIO21 ICOCZ Pu-11Float13

V17 AC22 GPIO22 GPIO22 ICOCZ Pd-01Float13

Y17 AF23 GPIO23 GPIO23 ICOCZ Pd-01Float13

VCC_CARD2

W19 AE22 GPIO24 GPIO24 ICOCZ Pd-01Float13

W18 AD22 GPIO25 GPIO25 ICOCZ Pd-01Float13

AA19 AF24 GPIO26 GPIO26 ICOCZ Pd-01Float13

V16 AD23 GPIO27 GPIO27 ICOCZ Pu-11Float13

U19 AB22 GPIO28 GPIO28 ICOCZ Pd-01Float13

U16 AE25 GPIO29 GPIO29 ICOCZ Pd-01Float13

No Connect Balls

A1 A1 NC

A2 A2 NC

A20 A25 NC

A21 A26 NC

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 80 April 6, 2009 Released

AA1 B1 NC

AA2 B26 NC

AA20 AE1 NC

AA21 AE2 NC

B1 AE26 NC

B21 AF1 NC

Y1 AF2 NC

Y21 AF25 NC

Y7 AF26 NC

Reserved For Future Use (RFU) Balls

A4 K3 RFU_ A4/

RFU_K3

B10 R2 RFU_ B10/

RFU_R2

B11 T1 RFU_B11/

RFU_T1

B3 T2 RFU_B3/

RFU_T2

C3 T3 RFU_C3/

RFU_T3

D4 U1 RFU_D4/

RFU_U1

D6 U2 RFU_D6/

RFU_U2

H7 U3 RFU_H7/

RFU_U3

L7 U4 RFU_L7/

RFU_U4

Y19 AD4 RFU_Y19/

RFU_AD4

Y20 RFU_Y20

Package on Package (POP) Signals

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 81

D13 LOCK_PRE Input Input Input

W20 ND_RST Input Input Input

C20 DF_NWP Input Input Input

Power Supplies

L5 AC14 VCC_APPS VCC_APPS PS Input Input Input

M5 AC16 VCC_APPS VCC_APPS PS Input Input Input

P5 AC20 VCC_APPS VCC_APPS PS Input Input Input

L6 AD19 VCC_APPS VCC_APPS PS Input Input Input

N6 AE16 VCC_APPS VCC_APPS PS Input Input Input

N7 AF15 VCC_APPS VCC_APPS PS Input Input Input

E8 AF18 VCC_APPS VCC_APPS PS Input Input Input

V12 AF20 VCC_APPS VCC_APPS PS Input Input Input

W13 AF21 VCC_APPS VCC_APPS PS Input Input Input

N14 L13 VCC_APPS VCC_APPS PS Input Input Input

AA14 L14 VCC_APPS VCC_APPS PS Input Input Input

V15 M13 VCC_APPS VCC_APPS PS Input Input Input

Y15 M14 VCC_APPS VCC_APPS PS Input Input Input

AA15 N11 VCC_APPS VCC_APPS PS Input Input Input

Y16 N12 VCC_APPS VCC_APPS PS Input Input Input

N15 VCC_APPS VCC_APPS PS Input Input Input

N16 VCC_APPS VCC_APPS PS Input Input Input

P11 VCC_APPS VCC_APPS PS Input Input Input

P12 VCC_APPS VCC_APPS PS Input Input Input

P15 VCC_APPS VCC_APPS PS Input Input Input

P16 VCC_APPS VCC_APPS PS Input Input Input

R13 VCC_APPS VCC_APPS PS Input Input Input

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

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R14 VCC_APPS VCC_APPS PS Input Input Input

T13 VCC_APPS VCC_APPS PS Input Input Input

T14 VCC_APPS VCC_APPS PS Input Input Input

T25 VCC_APPS VCC_APPS PS Input Input Input

V25 VCC_APPS VCC_APPS PS Input Input Input

H9 A10 VCC_BBATT VCC_BBATT PS Input Input Input

G10 D9 VCC_BG VCC_BG PS Input Input Input

AA17 AB21 VCC_CARD1 VCC_CARD1 PS Input Input Input

W17 AE23 VCC_CARD2 VCC_CARD2 PS Input Input Input

M15 R26 VCC_CI VCC_CI PS Input Input Input

V24 VCC_CI VCC_CI PS Input Input Input

B4 AB7 VCC_DF VCC_DF PS Input Input Input

T5 AC9 VCC_DF VCC_DF PS Input Input Input

V6 AD6 VCC_DF VCC_DF PS Input Input Input

B9 AE11 VCC_DF VCC_DF PS Input Input Input

AE13 VCC_DF VCC_DF PS Input Input Input

B15 D15 VCC_IO1 VCC_IO1 PS Input Input Input

E10 VCC_IO1 VCC_IO1 PS Input Input Input

AA13 AB18 VCC_IO3 VCC_IO3 PS Input Input Input

U18 AB24 VCC_IO4 VCC_IO4 PS Input Input Input

W23 VCC_IO4 VCC_IO4 PS Input Input Input

E15 B22 VCC_IO6 VCC_IO6 PS Input Input Input

C20 VCC_IO6 VCC_IO6 PS Input Input Input

K18 J26 VCC_LCD VCC_LCD PS Input Input Input

K20 N24 VCC_LCD VCC_LCD PS Input Input Input

B2 AB5 VCC_MEM VCC_MEM PS Input Input Input

N2 D4 VCC_MEM VCC_MEM PS Input Input Input

P2 F4 VCC_MEM VCC_MEM PS Input Input Input

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 83

D3 H4 VCC_MEM VCC_MEM PS Input Input Input

L3 J5 VCC_MEM VCC_MEM PS Input Input Input

M3 K5 VCC_MEM VCC_MEM PS Input Input Input

AA3 M5 VCC_MEM VCC_MEM PS Input Input Input

N4 P5 VCC_MEM VCC_MEM PS Input Input Input

K5 T5 VCC_MEM VCC_MEM PS Input Input Input

M7 W5 VCC_MEM VCC_MEM PS Input Input Input

Y5 VCC_MEM VCC_MEM PS Input Input Input

G19 F24 VCC_MSL VCC_MSL PS Input Input Input

F3 AB26 VCC_MVT VCC_MVT PS Input Input Input

P3 AB8 VCC_MVT VCC_MVT PS Input Input Input

F4 AD15 VCC_MVT VCC_MVT PS Input Input Input

P4 E20 VCC_MVT VCC_MVT PS Input Input Input

L8 E7 VCC_MVT VCC_MVT PS Input Input Input

N15 G23 VCC_MVT VCC_MVT PS Input Input Input

E17 H5 VCC_MVT VCC_MVT PS Input Input Input

M4 VCC_MVT VCC_MVT PS Input Input Input

P22 VCC_MVT VCC_MVT PS Input Input Input

W4 VCC_MVT VCC_MVT PS Input Input Input

F10 E8 VCC_OSC13M VCC_OSC13M PS Input Input Input

F12 AE18 VCC_PLL VCC_PLL PS Input Input Input

R12 B15 VCC_PLL VCC_PLL PS Input Input Input

G1 AB11 VCC_SRAM VCC_SRAM PS Input Input Input

G2 D16 VCC_SRAM VCC_SRAM PS Input Input Input

P9 E9 VCC_SRAM VCC_SRAM PS Input Input Input

F14 H26 VCC_SRAM VCC_SRAM PS Input Input Input

A19 J3 VCC_SRAM VCC_SRAM PS Input Input Input

E12 A18 VCC_TSI VCC_TSI PS Input Input Input

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 84 April 6, 2009 Released

B6 C5 VCC_USB VCC_USB PS Input Input Input

D1 AA26 VSS VSS PS Input Input Input

U1 AB12 VSS VSS PS Input Input Input

V1 AB9 VSS VSS PS Input Input Input

V2 AD14 VSS VSS PS Input Input Input

N3 AD16 VSS VSS PS Input Input Input

C4 AD17 VSS VSS PS Input Input Input

M4 AD18 VSS VSS PS Input Input Input

J5 AD21 VSS VSS PS Input Input Input

V7 AE15 VSS VSS PS Input Input Input

F8 AE19 VSS VSS PS Input Input Input

U11 AE21 VSS VSS PS Input Input Input

W11 G25 VSS VSS PS Input Input Input

E14 G26 VSS VSS PS Input Input Input

V14 L11 VSS VSS PS Input Input Input

P17 L12 VSS VSS PS Input Input Input

Y18 L15 VSS VSS PS Input Input Input

AA18 L16 VSS VSS PS Input Input Input

P21 M11 VSS VSS PS Input Input Input

M12 VSS VSS PS Input Input Input

M15 VSS VSS PS Input Input Input

M16 VSS VSS PS Input Input Input

N13 VSS VSS PS Input Input Input

N14 VSS VSS PS Input Input Input

N22 VSS VSS PS Input Input Input

P13 VSS VSS PS Input Input Input

P14 VSS VSS PS Input Input Input

R11 VSS VSS PS Input Input Input

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 85

R12 VSS VSS PS Input Input Input

R15 VSS VSS PS Input Input Input

R16 VSS VSS PS Input Input Input

T11 VSS VSS PS Input Input Input

T12 VSS VSS PS Input Input Input

T15 VSS VSS PS Input Input Input

T16 VSS VSS PS Input Input Input

T26 VSS VSS PS Input Input Input

V26 VSS VSS PS Input Input Input

Y4 VSS VSS PS Input Input Input

A9 VSS VSS PS Input Input Input

C8 B9 VSS_BBATT VSS_BBATT PS Input Input Input

C9 D10 VSS_BG VSS_BG PS Input Input Input

R14 AD20 VSS_CARD1 VSS_CARD1 PS Input Input Input

V19 AE24 VSS_CARD2 VSS_CARD2 PS Input Input Input

N16 R25 VSS_CI VSS_CI PS Input Input Input

U24 VSS_CI VSS_CI PS Input Input Input

A3 AC10 VSS_DF VSS_DF PS Input Input Input

W6 AC6 VSS_DF VSS_DF PS Input Input Input

Y10 AC7 VSS_DF VSS_DF PS Input Input Input

Y12 AD13 VSS_DF VSS_DF PS Input Input Input

B20 AF11 VSS_DF VSS_DF PS Input Input Input

D11 E11 VSS_IO1 VSS_IO1 PS Input Input Input

E15 VSS_IO1 VSS_IO1 PS Input Input Input

T12 AE17 VSS_IO3 VSS_IO3 PS Input Input Input

R17 AB23 VSS_IO4 VSS_IO4 PS Input Input Input

Y24 VSS_IO4 VSS_IO4 PS Input Input Input

E19 C22 VSS_IO6 VSS_IO6 PS Input Input Input

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 86 April 6, 2009 Released

D20 VSS_IO6 VSS_IO6 PS Input Input Input

R11 J25 VSS_LCD VSS_LCD PS Input Input Input

J21 M23 VSS_LCD VSS_LCD PS Input Input Input

C1 AA5 VSS_MEM VSS_MEM PS Input Input Input

H1 AC5 VSS_MEM VSS_MEM PS Input Input Input

M1 E4 VSS_MEM VSS_MEM PS Input Input Input

P1 G4 VSS_MEM VSS_MEM PS Input Input Input

R1 J4 VSS_MEM VSS_MEM PS Input Input Input

T1 L5 VSS_MEM VSS_MEM PS Input Input Input

K2 N5 VSS_MEM VSS_MEM PS Input Input Input

R4 R5 VSS_MEM VSS_MEM PS Input Input Input

R5 U5 VSS_MEM VSS_MEM PS Input Input Input

P7 V5 VSS_MEM VSS_MEM PS Input Input Input

W21 VSS_MEM VSS_MEM PS Input Input Input

G17 F26 VSS_MSL VSS_MSL PS Input Input Input

A9 B11 VSS_OSC13M VSS_OSC13M PS Input Input Input

C12 AC18 VSS_PLL VSS_PLL PS Input Input Input

W14 C14 VSS_PLL VSS_PLL PS Input Input Input

D14 C18 VSS_TSI VSS_TSI PS Input Input Input

E3 B5 VSS_USB VSS_USB PS Input Input Input

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 87

4.2.2 PXA31x Proces sor Pin Use

Table 10 lists the mapping of signals to s pecific PXA31x pr ocessor package pins.

NOTE:

1. GPIO reset / S3 operati on: After an y re set is asser ted or if PXA32x pr ocessor is i n S3/ D 4 /C4 power m ode, these pi ns

are config ur ed as the pri m ary fu nct ion of the MF P (ge nerally as GP I O input ) and default pull up or pul l down occur s.

2. Crystal oscillato r pins: These pins connect the external c rystals to the on-chi p oscillators and are not af fected by either

reset or S2/D3/C4 power mode. For more information, see the “Services Clock Con trol Unit” chapter in the PXA3xx

Processor Family Developers Manual.

3. Each MFP out put val u e is bas ed on MFPRx x[ Sl eep_sel], MF PRxx[sle ep_ data ], M FPRxx[slee p_o e_n],

MFPRxx[ pull_sel], MFPRxx [p ull up_en] and M FPR xx[pulldo w n_en] follow i ng S2 /D3/C4 wak e- up. To preven t

unnecessary current drain, ensure input signals are not floating during low-power modes. Each GPIO to be driven can

be progr am m ed to a 0/1 or be pul led up or pulled down during S2/D3/ C 4 p ow er m ode if the MVT and the IO (HVT)

supplie s are present.

4. Logic low when OSCC[TENSx] bit is cleared, CLK_TOUT when OSCC[TENSx] is set. Configure TENS2 for S2/D3/C4

mode and TENS3 for S3/D4/C4 power mode.

5. Pulldown alw ays enabled.

6. Output functions during S2/D3/C4 power mode.

7. Pullup al ways enabled.

8. AD2D0ER[WETSI] bit is set before entry into S2, TSI_YM is driven low (not pulled low). AD2D0ER[WETSI] bit is clear

before ent ry into S 2, T SI_ YM signal is Hi-Z (n o pulldown or pull up).

9. 20 KΩ nom i nal, 14.5 K Ω min - 2 4.5 KΩ max

10. Pd-0 if UP2OCR[DMPDE] is set, then Pd-0, Hi-Z if UP2OCR[DMPDE] is cleared.

11. Hi-Z if UP2OCR[DPPDE] is cleared and UP2OCR[DPPUE] is cleared; Pu-1 if UP2OCR[DPPDE] is cleared and

UP2OCR[DPPUE] is set; Pd-0 if UP2OCR[DPP DE] is set and UP2OCR[DPPUE] is cleared. Setting

UP2OCR[DPPDE] and UP2OCR[DPPUE] at the same time is not allowed.

12. This signal’s pullup /p ul ldown is ena bl ed during power-o n, har dware, glob al wat chdog and GPIO resets. The

pullup/pulldown must be disabled by software by setting PCFR[PUDH] after the external devices driving these pins

are conf igured.

13. There is no pullup or pulldown on this pin. Asserts if PCFR[SL_ROD] is clear.

14. See Table 12 for type definitions

Table 9: PXA32x Processor Pin Usage Summary (Continued)

15mm2

Ball # 14mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Table 10: PXA31x Processor Pin Usage Summary

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

VCC_BBATT

B6 A6 CLK_TOUT CLK_TOUT OC Clk-Out 44

B7 E6 EXT_WAKEUP

0EXT_WAKEUP0 ICOCZ Pd-010 Pd-010 Pd-010

C6 C6 NBATT_FAULT nBATT_FAULT IC Input Input Input

E8 E9 NGPIO_RESE

TnGPIO_RESET IC Pu-110 Pu-110 Pu-110

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 88 April 6, 2009 Released

D6 B6 NRESET nRESET IC Input7Input Input

F9 A8 NRESET_OUT nRESET_OUT OC Low 11 11

A6 E5 NTRST nTRST IC Input7Input7Input7

A7 A7 PWR_CAP0 PWR_CAP0 OA - - -

F8 F7 PWR_CAP1 PWR_CAP1 OA - - -

D3 C5 PWR_EN PWR_EN OC Low Low Low

C7 B7 PWR_OUT PWR_OUT OA - - -

D4 F6 SYS_EN SYS_EN OC Low Low Low

C4 A5 TCK TCK IC Input Input Input

E3 B5 TDI TDI IC Input7Input7Input7

D2 C4 TDO TDO OCZ Hi-Z Hi-Z Hi-Z

C3 D3 TMS TMS IC Input7Input7Input7

A8 C7 TXTAL_IN TXTAL_IN IA 222

B8 C8 TXTAL_OUT TXTAL_OUT OA 222

VCC_MVT

B9 A9 PXTAL_IN PXTAL_IN IA 222

C9 B9 PXTAL_OUT PXTAL_OUT OA 222

VCC_IO1

A11 A13 GPIO0_2 GPIO0_2 ICOCZ Pd-01Float13

D11 A12 GPIO1_2 GPIO1_2 ICOCZ Pd-01Float13

E18 D22 GPIO91 GPIO91 ICOCZ Pu-11Float13

E21 C22 GPIO92 GPIO92 ICOCZ Pu-11Float13

E20 E24 GPIO93 GPIO93 ICOCZ Pd-01Float13

D21 C23 GPIO94 GPIO94 ICOCZ Pd-01Float13

C20 D24 GPIO95 GPIO95 ICOCZ Pd-01Float13

A19 B23 GPIO96 GPIO96 ICOCZ Pd-01Float13

D20 A22 GPIO97 GPIO97 ICOCZ Pd-01Float13

C21 C24 GPIO98 GPIO98 ICOCZ Pd-01Float13

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 89

A18 B16 GPIO99 GPIO99 ICOCZ Pd-01Float13

B18 A21 GPIO100 GPIO100 ICOCZ Pd-01Float13

C19 B19 GPIO101 GPIO101 ICOCZ Pu-11Float13

A17 A20 GPIO102 GPIO102 ICOCZ Pu-11Float13

D18 C20 GPIO103 GPIO103 ICOCZ Pu-11Float13

E19 C19 GPIO104 GPIO104 ICOCZ Pu-11Float13

D17 F17 GPIO105 GPIO105 ICOCZ Pu-11Float13

B17 B20 GPIO106 GPIO106 ICOCZ Pu-11Float13

C16 A17 GPIO107 GPIO107 ICOCZ Pu-11Float13

C17 C18 GPIO108 GPIO108 ICOCZ Pu-11Float13

D16 F16 GPIO109 GPIO109 ICOCZ Pd-01Float13

A16 A19 GPIO110 GPIO110 ICOCZ Pu-11Float13

F14 E15 GPIO111 GPIO111 ICOCZ Pu-11Float13

B15 H16 GPIO112 GPIO112 ICOCZ Pd-01Float13

C15 B15 GPIO113 GPIO113 ICOCZ Pd-01Float13

D15 E16 GPIO114 GPIO114 ICOCZ Pu-11Float13

C13 A15 GPIO115 GPIO115 ICOCZ Pd-01Float13

A14 A16 GPIO116 GPIO116 ICOCZ Pd-01Float13

E14 E14 GPIO117 GPIO117 ICOCZ Pd-01Float13

D14 C15 GPIO118 GPIO118 ICOCZ Pd-01Float13

E13 B14 GPIO119 GPIO119 ICOCZ Pd-01Float13

B14 F15 GPIO120 GPIO120 ICOCZ Pd-01Float13

F13 E13 GPIO121 GPIO121 ICOCZ Pd-01Float13

C14 F14 GPIO122 GPIO122 ICOCZ Pd-01Float13

D13 B13 GPIO123 GPIO123 ICOCZ Pu-11Float13

B12 F13 GPIO124 GPIO124 ICOCZ Pd-01Float13

F12 F12 GPIO125 GPIO125 ICOCZ Pd-01Float13

A12 A14 GPIO126 GPIO126 ICOCZ Pu-11Float13

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 90 April 6, 2009 Released

C12 C12 GPIO127 GPIO127 ICOCZ Pu-11Float13

P8 E20 GPIO7_2 GPIO7_2 ICOCZ Pd-01Float13

N8 F19 GPIO8_2 GPIO8_2 ICOCZ Pd-01Float13

K8 E18 GPIO9_2 GPIO9_2 ICOCZ Pd-01Float13

J8 F18 GPIO10_2 GPIO10_2 ICOCZ Pd-01Float13

F10 A10 PWR_SCL PWR_SCL ICOCZ Pu-110 Pu-110 Float -

Note[1]

B10 F11 PWR_SDA PWR_SDA ICOCZ Pu-110 Pu-110 Float -

Note[1]

B11 H12 TEST TEST IC Input5Input5Input5

F11 E10 TESTCLK TESTCLK IC Input5Input5Input5

E10 B10 VCTCXO_EN VCTCXO_EN OC Low Note6Note6

C11 B12 CLK_POUT CLK_POUT OC Low Float Low

VCC_DF

AA4 AC4 DF_ADDR0 DF_ADDR0 OCZ Pd-01Float13

V6 AB5 DF_ADDR1 DF_ADDR1 OCZ Pd-01Float13

W6 AD4 DF_ADDR2 DF_ADDR2 OCZ Pd-01Float13

Y4 AC5 DF_ADDR3 DF_ADDR3 OCZ Pd-01Float13

AA5 Y7 DF_IO0 DF_IO0 ICOCZ Pd-01Float13

AA6 AC7 DF_IO1 DF_IO1 ICOCZ Pd-01Float13

W7 AD6 DF_IO2 DF_IO2 ICOCZ Pd-01Float13

Y8 AB9 DF_IO3 DF_IO3 ICOCZ Pd-01Float13

V10 AD12 DF_IO4 DF_IO4 ICOCZ Pd-01Float13

W13 AD13 DF_IO5 DF_IO5 ICOCZ Pd-01Float13

W12 AD14 DF_IO6 DF_IO6 ICOCZ Pd-01Float13

V11 Y12 DF_IO7 DF_IO7 ICOCZ Pd-01Float13

U8 AD5 DF_IO8 DF_IO8 ICOCZ Pd-01Float13

Y5 AB8 DF_IO9 DF_IO9 ICOCZ Pd-01Float13

Y6 AD7 DF_IO10 DF_IO10 ICOCZ Pd-01Float13

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 91

W8 AD9 DF_IO11 DF_IO11 ICOCZ Pd-01Float13

U15 W13 DF_IO12 DF_IO12 ICOCZ Pd-01Float13

W10 AB12 DF_IO13 DF_IO13 ICOCZ Pd-01Float13

W11 Y14 DF_IO14 DF_IO14 ICOCZ Pd-01Float13

W15 AD15 DF_IO15 DF_IO15 ICOCZ Pd-01Float13

V7 AC2 DF_ALE_NWE DF_ALE OCZ Pu-11Float13

V9 W10 DF_NCS0 DF_nCS0 OCZ Pu-11Float13

U10 AC13 DF_NCS1 DF_nCS1 OCZ Pu-11Float13

W5 AB3 DF_NRE DF_nOE OCZ Pu-11Float13

W4 AB2 DF_NWE DF_nWE OCZ Pu-11Float13

W3 AA3 DF_INT_RNB DF_RnB ICZ Pu-11Float13

V8 W6 DF_CLE_NOE ND_CLE OCZ Pu-11Float13

AA10 AC11 DF_SCLK_E DF_SCLK_E OCZ Pd-01Float13

V3 W1 GPIO0 GPIO0 ICOCZ Pd-01Float13

U4 AA2 GPIO1 GPIO1 ICOCZ Pu-11Float13

V1 Y1 GPIO2 GPIO2 ICOCZ Pu-11Float13

Y3 AD3 NBE0 nBE0 OCZ Pu-11Float13

AA3 AC3 NBE1 nBE1 OCZ Pu-11Float13

Y10 AB11 NLLA nLLA OCZ Pu-11Float13

Y9 AD10 NLUA nLUA OCZ Pu-11Float13

W1 AB1 NCS0 nCS0 OC High High High

V4 AA1 NCS1 nCS1 OC High High High

VCC_IO3

W17 AC21 GPIO17 GPIO17 ICOCZ Pd-01Float13

W18 W17 GPIO18 GPIO18 ICOCZ Pd-01Float13

U17 AB21 GPIO19 GPIO19 ICOCZ Pd-01Float13

V18 AB23 GPIO20 GPIO20 ICOCZ Pu-11Float13

W19 Y22 GPIO21 GPIO21 ICOCZ Pu-11Float13

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 92 April 6, 2009 Released

AA17 AC23 GPIO22 GPIO22 ICOCZ Pu-11Float13

Y17 AB22 GPIO23 GPIO23 ICOCZ Pu-11Float13

AA18 AD22 GPIO24 GPIO24 ICOCZ Pd-01Float13

Y18 AA23 GPIO25 GPIO25 ICOCZ Pd-01Float13

Y19 AA24 GPIO26 GPIO26 ICOCZ Pd-01Float13

V21 W19 GPIO27 GPIO27 ICOCZ Pd-01Float13

U21 Y23 GPIO28 GPIO28 ICOCZ Pd-01Float13

V19 Y24 GPIO29 GPIO29 ICOCZ Pd-01Float13

E6 W15 GPIO2_2 GPIO2_2 ICOCZ Pu-11Float13

E5 W20 GPIO3_2 GPIO3_2 ICOCZ Pd-01Float13

G8 Y18 GPIO4_2 GPIO4_2 ICOCZ Pd-01Float13

F5 Y20 GPIO5_2 GPIO5_2 ICOCZ Pd-01Float13

E7 Y19 GPIO6_2 GPIO6_2 ICOCZ Pu-11Float13

VCC_ULPI

V20 AA22 GPIO30 GPIO30 ICOCZ Pd-01Float13

U18 W22 GPIO31 GPIO31 ICOCZ Pd-01Float13

U20 W23 GPIO32 GPIO32 ICOCZ Pu-11Float13

U19 W18 GPIO33 GPIO33 ICOCZ Pu-11Float13

T20 W24 GPIO34 GPIO34 ICOCZ Pu-11Float13

T18 V20 GPIO35 GPIO35 ICOCZ Pu-11Float13

T21 V23 GPIO36 GPIO36 ICOCZ Pu-11Float13

R17 V19 GPIO37 GPIO37 ICOCZ Pu-11Float13

T17 U22 GPIO38 GPIO38 ICOCZ Pd-01Float13

V17 N17 ULPI_DIR ULPI_DIR IC Pd-01Float13

W20 P17 ULPI_NXT ULPI_NXT IC Pd-01Float13

W21 U17 ULPI_STP ULPI_STP 0C Pu-11Float13

VCC_CI

R18 U19 GPIO39 GPIO39 ICOCZ Pd-01Float13

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 93

T19 V24 GPIO40 GPIO40 ICOCZ Pd-01Float13

R20 U23 GPIO41 GPIO41 ICOCZ Pd-01Float13

R19 T22 GPIO42 GPIO42 ICOCZ Pd-01Float13

P16 U24 GPIO43 GPIO43 ICOCZ Pd-01Float13

R21 T20 GPIO44 GPIO44 ICOCZ Pd-01Float13

P17 R20 GPIO45 GPIO45 ICOCZ Pd-01Float13

P18 T17 GPIO46 CIF_DD7 ICOCZ Pd-01Float13

N16 P22 GPIO47 GPIO47 ICOCZ Pd-01Float13

P21 R19 GPIO48 GPIO48 ICOCZ Pd-01Float13

N17 P20 GPIO49 CIF_MCLK ICOCZ Pd-01Float13

N18 R24 GPIO50 CIF_PCLK ICOCZ Pd-01Float13

N19 N24 GPIO51 CIF_HSYNC ICOCZ Pd-01Float13

M20 N20 GPIO52 CIF_VSYNC ICOCZ Pd-01Float13

VCC_LCD

M17 R23 GPIO53 GPIO53 ICOCZ Pu-11Float13

M21 P23 GPIO54 GPIO54 ICOCZ Pd-01Float13

M18 N22 GPIO55 GPIO55 ICOCZ Pd-01Float13

L18 P24 GPIO56 GPIO56 ICOCZ Pd-01Float13

M19 N23 GPIO57 GPIO57 ICOCZ Pd-01Float13

L20 P19 GPIO58 GPIO58 ICOCZ Pd-01Float13

L17 M19 GPIO59 GPIO59 ICOCZ Pd-01Float13

L21 L19 GPIO60 GPIO60 ICZ Pd-01Float13

K19 M22 GPIO61 GPIO61 ICOCZ Pd-01Float13

L19 M23 GPIO62 GPIO62 ICOCZ Pu-11Float13

K20 J19 GPIO63 GPIO63 ICOCZ Pd-01Float13

K17 M24 GPIO64 GPIO64 ICOCZ Pd-01Float13

J17 L22 GPIO65 GPIO65 ICOCZ Pd-01Float13

K21 K22 GPIO66 GPIO66 ICOCZ Pd-01Float13

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 94 April 6, 2009 Released

J18 L23 GPIO67 GPIO67 ICOCZ Pd-01Float13

K18 L20 GPIO68 GPIO68 ICOCZ Pd-01Float13

J19 K20 GPIO69 GPIO69 ICOCZ Pd-01Float13

J20 L24 GPIO70 GPIO70 ICOCZ Pd-01Float13

J16 H19 GPIO71 GPIO71 ICOCZ Pd-01Float13

J21 K23 GPIO72 GPIO72 ICOCZ Pd-01Float13

H16 K24 GPIO73 GPIO73 ICOCZ Pd-01Float13

H17 J22 GPIO74 GPIO74 ICOCZ Pd-01Float13

H18 G19 GPIO75 GPIO75 ICOCZ Pd-01Float13

H20 J23 GPIO76 GPIO76 ICOCZ Pd-01Float13

VCC_MEM

G3 F2 DQM0 DQM0 OC High High High

T4 U1 DQM1 DQM1 OC High High High

F3 G3 DQS0 DQS0 ISOCZ Pd-0 Pd-0 Pd-0

R4 V3 DQS1 DQS1 ISOCZ Pd-0 Pd-0 Pd-0

L3 M1 MA0 MA0 OC High High High

N4 R5 MA1 MA1 OC High High High

H3 H2 MA2 MA2 OC High High High

M1 P5 MA3 MA3 OC High High High

H4 K3 MA4 MA4 OC High High High

M3 P3 MA5 MA5 OC High High High

K4 J1 MA6 MA6 OC High High High

M2 N3 MA7 MA7 OC High High High

J1 K2 MA8 MA8 OC High High High

L2 N1 MA9 MA9 OC High High High

J3 K1 SDMA10 SDMA10 OC High High High

M4 N2 MA11 MA11 OC High High High

K3 L3 MA12 MA12 OC High High High

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 95

H5 M5 MA13 MA13 OC High High High

H2 J3 MA14 MA14 OC High High High

J4 J2 MA15 MA15 OC High High High

D1 D1 MD0 MD0 ICSOCZ Pd-0 Pd-0 Pd-0

E1 E1 MD1 MD1 ICSOCZ Pd-0 Pd-0 Pd-0

E2 E2 MD2 MD2 ICSOCZ Pd-0 Pd-0 Pd-0

F1 F1 MD3 MD3 ICSOCZ Pd-0 Pd-0 Pd-0

F2 G1 MD4 MD4 ICSOCZ Pd-0 Pd-0 Pd-0

G1 G2 MD5 MD5 ICSOCZ Pd-0 Pd-0 Pd-0

G2 H3 MD6 MD6 ICSOCZ Pd-0 Pd-0 Pd-0

H1 H1 MD7 MD7 ICSOCZ Pd-0 Pd-0 Pd-0

P3 T2 MD8 MD8 ICSOCZ Pd-0 Pd-0 Pd-0

R3 T1 MD9 MD9 ICSOCZ Pd-0 Pd-0 Pd-0

R1 U3 MD10 MD10 ICSOCZ Pd-0 Pd-0 Pd-0

T2 U2 MD11 MD11 ICSOCZ Pd-0 Pd-0 Pd-0

T1 V2 MD12 MD12 ICSOCZ Pd-0 Pd-0 Pd-0

U2 V1 MD13 MD13 ICSOCZ Pd-0 Pd-0 Pd-0

T3 W2 MD14 MD14 ICSOCZ Pd-0 Pd-0 Pd-0

U1 W3 MD15 MD15 ICSOCZ Pd-0 Pd-0 Pd-0

N3 T3 NSDCAS nSDCAS OC High High High

L1 M3 NSDCS0 nSDCS0 OC High High High

J2 M2 NSDCS1 nSDCS1 OC High High High

P2 P2 NSDRAS nSDRAS OC High High High

P1 R3 NSDWE nSDWE OC High High High

N1 P1 RCOMP_DDR RCOMP_DDR OA - - -

R2 R2 SDCKE SDCKE OC Low Low Low

K1 L1 SDCLK0 SDCLK0 OC Low Low Low

K2 L2 SDCLK1 SDCLK1 OC High High High

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 96 April 6, 2009 Released

VCC_MSL

H19 H22 GPIO77 GPIO77 ICOCZ Pd-01Float13

G16 J24 GPIO78 GPIO78 ICOCZ Pd-01Float13

F16 J20 GPIO79 GPIO79 ICOCZ Pd-01Float13

H21 H23 GPIO80 GPIO80 ICOCZ Pd-01Float13

G18 G23 GPIO81 GPIO81 ICOCZ Pd-01Float13

G20 G22 GPIO82 GPIO82 ICOCZ Pd-01Float13

G19 F23 GPIO83 GPIO83 ICOCZ Pd-01Float13

G21 F20 GPIO84 GPIO84 ICOCZ Pu-11Float13

F19 F22 GPIO85 GPIO85 ICOCZ Pd-01Float13

E16 H24 GPIO86 GPIO86 ICOCZ Pd-01Float13

F18 E23 GPIO87 GPIO87 ICOCZ Pd-01Float13

F20 E22 GPIO88 GPIO88 ICOCZ Pd-01Float13

E17 G24 GPIO89 GPIO89 ICOCZ Pu-11Float13

F21 D23 GPIO90 GPIO90 ICOCZ Pu-11Float13

VCC_CARD1

U11 AB14 GPIO3 GPIO3 ICOCZ Pd-01Float13

AA11 AC14 GPIO4 GPIO4 ICOCZ Pd-01Float13

V12 AB15 GPIO5 GPIO5 ICOCZ Pd-01Float13

V13 AD17 GPIO6 GPIO6 ICOCZ Pu-11Float13

W14 AB17 GPIO7 GPIO7 ICOCZ Pd-01Float13

U14 Y16 GPIO8 GPIO8 ICOCZ Pd-01Float13

VCC_CARD2

U12 AD16 GPIO9 GPIO9 ICOCZ Pd-01Float13

Y14 AB18 GPIO10 GPIO10 ICOCZ Pd-01Float13

V14 AB19 GPIO11 GPIO11 ICOCZ Pd-01Float13

U16 AC20 GPIO12 GPIO12 ICOCZ Pu-11Float13

V15 AC19 GPIO13 GPIO13 ICOCZ Pd-01Float13

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 97

Y15 AD20 GPIO14 GPIO14 ICOCZ Pd-01Float13

Y16 Y17 GPIO15 GPIO15 ICOCZ Pu-11Float13

V16 AD19 GPIO16 GPIO16 ICOCZ Pu-11Float13

RFU Balls

A3 A3 RFU_A3/RFU_

A3 —————

A4 B2 RFU_A4/RFU_

B2 —————

A5 B3 RFU_A5/RFU_

B3 —————

B5 B4 RFU_B5/RFU_

B4 —————

N2 C3 RFU_N2/RFU_

C3 —————

W9 R1 RFU_W9/RFU_

R1 —————

AD11 RFU_AD11 — — — — —

No Connect (NC) Balls

B4 A1 NC — — — — —

C1 A2 NC — — — — —

C5 A23 NC — — — — —

D19 A24 NC — — — — —

G4 B1 NC — — — — —

L4 B24 NC — — — — —

L8 E17 NC — — — — —

M8 E19 NC — — — — —

P4 W5 NC — — — — —

P5 W7 NC — — — — —

U3 W8 NC — — — — —

U13 W9 NC — — — — —

V2 W12 NC — — — — —

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 98 April 6, 2009 Released

W2 Y9 NC — — — — —

AA19 AB6 NC — — — — —

AC1 NC — — — — —

AC6 NC — — — — —

AC24 NC — — — — —

AD1 NC — — — — —

AD2 NC — — — — —

AD23 NC — — — — —

AD24 NC — — — — —

Internal NAND Signals

U5 DF_NWP DF_NWP Input Input Input Input

Power Supplies

A10 B17 VCC_APPS VCC_APPS PS Input Input Input

A13 C14 VCC_APPS VCC_APPS PS Input Input Input

A15 E11 VCC_APPS VCC_APPS PS Input Input Input

H10 H10 VCC_APPS VCC_APPS PS Input Input Input

H11 H15 VCC_APPS VCC_APPS PS Input Input Input

H12 K8 VCC_APPS VCC_APPS PS Input Input Input

K14 K17 VCC_APPS VCC_APPS PS Input Input Input

L5 L5 VCC_APPS VCC_APPS PS Input Input Input

L14 R8 VCC_APPS VCC_APPS PS Input Input Input

M14 R17 VCC_APPS VCC_APPS PS Input Input Input

N5 T24 VCC_APPS VCC_APPS PS Input Input Input

N21 U10 VCC_APPS VCC_APPS PS Input Input Input

P10 U15 VCC_APPS VCC_APPS PS Input Input Input

P11 AB16 VCC_APPS VCC_APPS PS Input Input Input

P12 AC9 VCC_APPS VCC_APPS PS Input Input Input

Y13 VCC_APPS VCC_APPS PS Input Input Input

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 99

AA7 VCC_APPS VCC_APPS PS Input Input Input

AA9 VCC_APPS VCC_APPS PS Input Input Input

AA12 VCC_APPS VCC_APPS PS Input Input Input

C8 E8 VCC_BBATT VCC_BBATT PS Input Input Input

D10 C9 VCC_BG VCC_BG PS Input Input Input

Y11 AC15 VCC_CARD1 VCC_CARD1 PS Input Input Input

AA14 AD18 VCC_CARD2 VCC_CARD2 PS Input Input Input

P15 R22 VCC_CI VCC_CI PS Input Input Input

P20 VCC_CI VCC_CI PS Input Input Input

G11 Y6 VCC_DF VCC_DF PS Input Input Input

T9 AB4 VCC_DF VCC_DF PS Input Input Input

T10 AB7 VCC_DF VCC_DF PS Input Input Input

T11 AB10 VCC_DF VCC_DF PS Input Input Input

T12 AB13 VCC_DF VCC_DF PS Input Input Input

T13 AC12 VCC_DF VCC_DF PS Input Input Input

E15 A11 VCC_IO1 VCC_IO1 PS Input Input Input

G10 C16 VCC_IO1 VCC_IO1 PS Input Input Input

G15 F24 VCC_IO1 VCC_IO1 PS Input Input Input

T16 AB20 VCC_IO3 VCC_IO3 PS Input Input Input

K16 K19 VCC_LCD VCC_LCD PS Input Input Input

L16 VCC_LCD VCC_LCD PS Input Input Input

M16 VCC_LCD VCC_LCD PS Input Input Input

D5 D2 VCC_MEM VCC_MEM PS Input Input Input

G5 E3 VCC_MEM VCC_MEM PS Input Input Input

G6 F3 VCC_MEM VCC_MEM PS Input Input Input

H6 G5 VCC_MEM VCC_MEM PS Input Input Input

J6 J5 VCC_MEM VCC_MEM PS Input Input Input

K6 K5 VCC_MEM VCC_MEM PS Input Input Input

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 100 April 6, 2009 Released

L6 N5 VCC_MEM VCC_MEM PS Input Input Input

M6 T5 VCC_MEM VCC_MEM PS Input Input Input

N6 V5 VCC_MEM VCC_MEM PS Input Input Input

P6 Y2 VCC_MEM VCC_MEM PS Input Input Input

R6 VCC_MEM VCC_MEM PS Input Input Input

T6 VCC_MEM VCC_MEM PS Input Input Input

U6 VCC_MEM VCC_MEM PS Input Input Input

V5 VCC_MEM VCC_MEM PS Input Input Input

G17 H20 VCC_MSL VCC_MSL PS Input Input Input

E4 B18 VCC_MVT VCC_MVT PS Input Input Input

G9 C21 VCC_MVT VCC_MVT PS Input Input Input

G14 F9 VCC_MVT VCC_MVT PS Input Input Input

H15 H6 VCC_MVT VCC_MVT PS Input Input Input

J5 N19 VCC_MVT VCC_MVT PS Input Input Input

J15 P6 VCC_MVT VCC_MVT PS Input Input Input

N15 U6 VCC_MVT VCC_MVT PS Input Input Input

R14 W16 VCC_MVT VCC_MVT PS Input Input Input

T5 AC8 VCC_MVT VCC_MVT PS Input Input Input

U9 VCC_MVT VCC_MVT PS Input Input Input

D9 B8 VCC_OSC13M VCC_OSC13M PS Input Input Input

D12 C11 VCC_PLL VCC_PLL PS Input Input Input

AA16 AC22 VCC_PLL VCC_PLL PS Input Input Input

B19 B21 VCC_SRAM VCC_SRAM PS Input Input Input

C18 W11 VCC_SRAM VCC_SRAM PS Input Input Input

AA8 VCC_SRAM VCC_SRAM PS Input Input Input

B3 A4 VCC_BIAS VCC_BIAS PS Input Input Input

R16 V22 VCC_ULPI VCC_ULPI PS Input Input Input

A1 VSS VSS PS Input Input Input

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 101

A2 VSS VSS PS Input Input Input

B1 VSS VSS PS Input Input Input

B2 VSS VSS PS Input Input Input

C17 VSS VSS PS Input Input Input

E7 VSS VSS PS Input Input Input

A9 E12 VSS VSS PS Input Input Input

A20 H8 VSS VSS PS Input Input Input

A21 H9 VSS VSS PS Input Input Input

H11 VSS VSS PS Input Input Input

H13 VSS VSS PS Input Input Input

B13 H14 VSS VSS PS Input Input Input

B16 H17 VSS VSS PS Input Input Input

B20 J8 VSS VSS PS Input Input Input

B21 J17 VSS VSS PS Input Input Input

C2 L8 VSS VSS PS Input Input Input

F4 L17 VSS VSS PS Input Input Input

H8 M6 VSS VSS PS Input Input Input

H9 M8 VSS VSS PS Input Input Input

H13 M17 VSS VSS PS Input Input Input

H14 N8 VSS VSS PS Input Input Input

J14 P8 VSS VSS PS Input Input Input

K5 T8 VSS VSS PS Input Input Input

M5 T23 VSS VSS PS Input Input Input

N14 U5 VSS VSS PS Input Input Input

N20 U8 VSS VSS PS Input Input Input

P9 U9 VSS VSS PS Input Input Input

P13 U11 VSS VSS PS Input Input Input

P14 U12 VSS VSS PS Input Input Input

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 102 April 6, 2009 Released

R5 U13 VSS VSS PS Input Input Input

R8 U14 VSS VSS PS Input Input Input

T8 U16 VSS VSS PS Input Input Input

T14 AC10 VSS VSS PS Input Input Input

Y7 AC16 VSS VSS PS Input Input Input

AA13 AC17 VSS VSS PS Input Input Input

D7 AD8 VSS VSS PS Input Input Input

D8 F8 VSS_BBATT VSS_BBATT PS Input Input Input

C10 F10 VSS_BG VSS_BG PS Input Input Input

Y12 Y15 VSS_CARD1 VSS_CARD1 PS Input Input Input

AA15 AC18 VSS_CARD2 VSS_CARD2 PS Input Input Input

P19 T19 VSS_CI VSS_CI PS Input Input Input

G12 W14 VSS_DF VSS_DF PS Input Input Input

R9 Y5 VSS_DF VSS_DF PS Input Input Input

R10 Y8 VSS_DF VSS_DF PS Input Input Input

R11 Y10 VSS_DF VSS_DF PS Input Input Input

R12 Y11 VSS_DF VSS_DF PS Input Input Input

R13 Y13 VSS_DF VSS_DF PS Input Input Input

Y1 VSS_DF VSS_DF PS Input Input Input

Y2 VSS_DF VSS_DF PS Input Input Input

AA1 VSS_DF VSS_DF PS Input Input Input

AA2 VSS_DF VSS_DF PS Input Input Input

F15 A18 VSS_IO1 VSS_IO1 PS Input Input Input

G13 B11 VSS_IO1 VSS_IO1 PS Input Input Input

B22 VSS_IO1 VSS_IO1 PS Input Input Input

T15 AB24 VSS_IO3 VSS_IO3 PS Input Input Input

Y20 VSS_IO3 VSS_IO3 PS Input Input Input

Y21 VSS_IO3 VSS_IO3 PS Input Input Input

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Versi on -

April 6, 2009 Released Page 103

AA20 VSS_IO3 VSS_IO3 PS Input Input Input

AA21 VSS_IO3 VSS_IO3 PS Input Input Input

K15 M20 VSS_LCD VSS_LCD PS Input Input Input

L15 VSS_LCD VSS_LCD PS Input Input Input

M15 VSS_LCD VSS_LCD PS Input Input Input

F6 C1 VSS_MEM VSS_MEM PS Input Input Input

F7 C2 VSS_MEM VSS_MEM PS Input Input Input

G7 F5 VSS_MEM VSS_MEM PS Input Input Input

H7 G6 VSS_MEM VSS_MEM PS Input Input Input

J7 H5 VSS_MEM VSS_MEM PS Input Input Input

K7 J6 VSS_MEM VSS_MEM PS Input Input Input

L7 K6 VSS_MEM VSS_MEM PS Input Input Input

M7 L6 VSS_MEM VSS_MEM PS Input Input Input

N7 N6 VSS_MEM VSS_MEM PS Input Input Input

P7 R6 VSS_MEM VSS_MEM PS Input Input Input

R7 T6 VSS_MEM VSS_MEM PS Input Input Input

T7 V6 VSS_MEM VSS_MEM PS Input Input Input

U7 Y3 VSS_MEM VSS_MEM PS Input Input Input

R15 U20 VSS_ULPI VSS_ULPI PS Input Input Input

F17 G20 VSS_MSL VSS_MSL PS Input Input Input

E9 C10 VSS_OSC13M VSS_OSC13M PS Input Input Input

E11 C13 VSS_PLL VSS_PLL PS Input Input Input

E12 AD21 VSS_PLL VSS_PLL PS Input Input Input

W16 VSS_PLL VSS_PLL PS Input Input Input

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 104 April 6, 2009 Released

4.2.3 PXA30x Proces sor Pin Use

Table 11 lists the mapping of signals to specific PXA30x processor package pins.

NOTE:

1. GPIO rese t /S3/ D4 /C 4 o p er at io n: A f t er an y r ese t i s a ss er te d o r i f P XA3 1x pr oce ss o r is i n S3 /D 4/ C4 po wer mod e, th es e

pins are configur ed as th e pr i m ary fu nct ion of the MF P (ge nerally as G P IO inp ut ) and default pul lup or pulldo wn

occurs.

2. Crystal oscil l at or pin s : Th ese pi ns conn e ct t he ex te rn al cry s t al s to th e on- ch i p os ci ll a to rs and a re no t affe c te d by ei t her

reset or S2/D3/C4 power mode. For more information, see the “Clocks Control and Power Management” chapter in the

PXA3x x Processor Fam ily Vol. I: System and Timer C onfi gur at i on De velopers Manual.

3. Each MF P out pu t v al ue is based on M FPRxx[Sleep_sel] , MF PR xx [s leep_data], MFPRxx[s le ep_oe_n],

MFPRxx[pull_sel], MFPRxx[pullup_en] and MFPRxx[pulldown_en] following S2/D3/C4 wake-up. To prevent

unnecessary current drain, ensure input signals are not floating during low-power modes. Each GPIO to be driven can

be progr am m ed to a 0/1 or be pulled up or pull ed down dur in g S2/ D3/C4 power mode i f the M VT and the IO (HVT)

supplies are present.

4. Logic low when OSCC[TENSx] bit is c le ared, CLK_TOUT when OSCC[TENSx] is set. Confi gure TENS2 for S2/ D3/C4

mode an d TENS3 for S3 /D 4/ C 4 po w er mo de.

5. Pulldown always enable d.

6. Output fu nct i on s dur i ng S2/D3/C 4 power mo de .

7. Pullup alway s enabled.

8. P d -0 if UP2OCR[DMPDE] is set, then Pd-0, Hi-Z if UP2OCR[DMPDE] is cleared.

9. Hi-Z if UP2O C R[ D PPDE] is cleare d and UP2OCR[DPP UE ] is cl ear ed ; Pu-1 if UP2O CR[D PPDE] i s cleared and

UP2OCR[DPPUE] is set; Pd-0 if UP2OCR[DPPDE] is set and UP2OCR[DPPUE] is cleared. Setting UP2OCR[DPPDE]

and UP2OCR[DPPUE] at the same time is not allowed.

10. This signal ’s pullup/ pulldown i s en abl ed during power-on, har dware, glo bal watchdo g and GPIO res ets. The

pull up/ pul ldow n must be disa bled by sof tw are by sett ing PCFR[ PUDH] aft er th e exte rna l devi ce s driv ing t hese pi ns are

configured.

11. There i s no pullup or pull down on this pin. Asserts if PCFR [S L_ROD] is clear.

Table 10: PXA31x Processor Pin Usage Summary (Continued)

15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C

4 Power

Mode

Table 11: PXA30x Pin Usage Summary

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

VCC_BBATT

D6 B6 A6 CLK_TOUT CLK_TOUT OC Clk-Out 44

E7 B7 E6 EXT_WAKE

UP0 EXT_WAKEUP

0ICOC

ZPd-011 Pd-011 Pd-011

A5 C6 C6 NBATT_FAU

LT nBATT_FAULT IC Input Input Input

A7 E8 E9 NGPIO_RE

SET nGPIO_RESET IC Pu-111 Pu-111 Pu-111

E8 D6 B6 NRESET nRESET IC Input7Input Input

D9 F9 A8 NRESET_O

UT nRESET_OUT OC Low 12 12

Versi on -

April 6, 2009 Released Page 105

C5 A6 E5 NTRST nTRST IC Input7Input7Input7

A6 A7 A7 PWR_CAP0 PWR_CAP0 OA - - -

E9 F8 F7 PWR_CAP1 PWR_CAP1 OA - - -

E4 D3 C5 PWR_EN PWR_EN OC Low Low Low

B6 C7 B7 PWR_OUT PWR_OUT OA - - -

B5 D4 F6 SYS_EN SYS_EN OC Low Low Low

E6 C4 A5 TCK TCK IC Input Input Input

E5 E3 B5 TDI TDI IC Input7Input7Input7

D5 D2 C4 TDO TDO OCZ Hi-Z Hi-Z Hi-Z

D4 C3 D3 TMS TMS IC Input7Input7Input7

D8 A8 C7 TXTAL_IN TXTAL_IN IA 22 2

C7 B8 C8 TXTAL_OUT TXTAL_OUT OA 22 2

VCC_MVT

B8 B9 A9 PXTAL_IN PXTAL_IN IA 22 2

C8 C9 B9 PXTAL_OUT PXTAL_OUT OA 22 2

VCC_IO1

B12 A11 A13 GPIO0_2 GPIO0_2 ICOC

ZPd-01Float13

A11 D11 A12 GPIO1_2 GPIO1_2 ICOC

ZPd-01Float13

E21 E18 D22 GPIO91 GPIO91 ICOC

ZPu-11Float13

D22 E21 C22 GPIO92 GPIO92 ICOC

ZPu-11Float13

C23 E20 E24 GPIO93 GPIO93 ICOC

ZPd-01Float13

E20 D21 C23 GPIO94 GPIO94 ICOC

ZPd-01Float13

D21 C20 D24 GPIO95 GPIO95 ICOC

ZPd-01Float13

C22 A19 B23 GPIO96 GPIO96 ICOC

ZPd-01Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 106 April 6, 2009 Released

C21 D20 A22 GPIO97 GPIO97 ICOC

ZPd-01Float13

D20 C21 C24 GPIO98 GPIO98 ICOC

ZPd-01Float13

E18 A18 B16 GPIO99 GPIO99 ICOC

ZPd-01Float13

B20 B18 A21 GPIO100 GPIO100 ICOC

ZPd-01Float13

A21 C19 B19 GPIO101 GPIO101 ICOC

ZPu-11Float13

A20 A17 A20 GPIO102 GPIO102 ICOC

ZPu-11Float13

B19 D18 C20 GPIO103 GPIO103 ICOC

ZPu-11Float13

D17 E19 C19 GPIO104 GPIO104 ICOC

ZPu-11Float13

C18 D17 F17 GPIO105 GPIO105 ICOC

ZPu-11Float13

A19 B17 B20 GPIO106 GPIO106 ICOC

ZPu-11Float13

C17 C16 A17 GPIO107 GPIO107 ICOC

ZPu-11Float13

B18 C17 C18 GPIO108 GPIO108 ICOC

ZPu-11Float13

A18 D16 F16 GPIO109 GPIO109 ICOC

ZPd-01Float13

B17 A16 A19 GPIO110 GPIO110 ICOC

ZPu-11Float13

C16 F14 E15 GPIO111 GPIO111 ICOC

ZPu-11Float13

A17 B15 H16 GPIO112 GPIO112 ICOC

ZPd-01Float13

E15 C15 B15 GPIO113 GPIO113 ICOC

ZPd-01Float13

B16 D15 E16 GPIO114 GPIO114 ICOC

ZPu-11Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 107

A16 C13 A15 GPIO115 GPIO115 ICOC

ZPd-01Float13

C15 A14 A16 GPIO116 GPIO116 ICOC

ZPd-01Float13

B15 E14 E14 GPIO117 GPIO117 ICOC

ZPd-01Float13

C14 D14 C15 GPIO118 GPIO118 ICOC

ZPd-01Float13

D15 E13 B14 GPIO119 GPIO119 ICOC

ZPd-01Float13

A15 B14 F15 GPIO120 GPIO120 ICOC

ZPd-01Float13

B14 F13 E13 GPIO121 GPIO121 ICOC

ZPd-01Float13

A14 C14 F14 GPIO122 GPIO122 ICOC

ZPd-01Float13

D14 D13 B13 GPIO123 GPIO123 ICOC

ZPu-11Float13

B13 B12 F13 GPIO124 GPIO124 ICOC

ZPd-01Float13

A13 F12 F12 GPIO125 GPIO125 ICOC

ZPd-01Float13

C12 A12 A14 GPIO126 GPIO126 ICOC

ZPu-11Float13

A12 C12 C12 GPIO127 GPIO127 ICOC

ZPu-11Float13

A9 F10 A10 PWR_SCL PWR_SCL ICOC

ZPu-111 Pu-111 Float1

C10 B10 F11 PWR_SDA PWR_SDA ICOC

ZPu-111 Pu-111 Float1

A10 B11 H12 TEST TEST IC Input5Input5Input5

B10 F11 E10 TESTCLK TESTCLK IC Input5Input5Input5

E12 E10 B10 VCTCXO_E

NVCTCXO_EN OC Low 66

C11 C11 B12 CLK_POUT CLK_POUT OC Low Float Low

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 108 April 6, 2009 Released

VCC_DF

Y5 AA4 AC4 DF_ADDR0 DF_ADDR0 OCZ Pd-01Float13

Y2 V6 AB5 DF_ADDR1 DF_ADDR1 OCZ Pd-01Float13

Y1 W6 AD4 DF_ADDR2 DF_ADDR2 OCZ Pd-01Float13

Y6 Y4 AC5 DF_ADDR3 DF_ADDR3 OCZ Pd-01Float13

AA1 AA5 Y7 DF_IO0 DF_IO0 ICOC

ZPd-01Float13

AA3 AA6 AC7 DF_IO1 DF_IO1 ICOC

ZPd-01Float13

AA4 W7 AD6 DF_IO2 DF_IO2 ICOC

ZPd-01Float13

AB5 Y8 AB9 DF_IO3 DF_IO3 ICOC

ZPd-01Float13

AC3 V10 AD12 DF_IO4 DF_IO4 ICOC

ZPd-01Float13

AC4 W13 AD13 DF_IO5 DF_IO5 ICOC

ZPd-01Float13

AA10 W12 AD14 DF_IO6 DF_IO6 ICOC

ZPd-01Float13

AB9 V11 Y12 DF_IO7 DF_IO7 ICOC

ZPd-01Float13

AA2 U8 AD5 DF_IO8 DF_IO8 ICOC

ZPd-01Float13

Y7 Y5 AB8 DF_IO9 DF_IO9 ICOC

ZPd-01Float13

Y8 Y6 AD7 DF_IO10 DF_IO10 ICOC

ZPd-01Float13

AB4 W8 AD9 DF_IO11 DF_IO11 ICOC

ZPd-01Float13

AB8 U15 W13 DF_IO12 DF_IO12 ICOC

ZPd-01Float13

AC5 W10 AB12 DF_IO13 DF_IO13 ICOC

ZPd-01Float13

AC6 W11 Y14 DF_IO14 DF_IO14 ICOC

ZPd-01Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 109

AC7 W15 AD15 DF_IO15 DF_IO15 ICOC

ZPd-01Float13

Y3 V7 AC2 DF_ALE_N

WE DF_ALE OCZ Pu-11Float13

AB6 V9 W10 DF_NCS0 DF_nCS0 OCZ Pu-11Float13

AB10 U10 AC13 DF_NCS1 DF_nCS1 OCZ Pu-11Float13

W4 W5 AB3 DF_NRE DF_nOE OCZ Pu-11Float13

W3 W4 AB2 DF_NWE DF_nWE OCZ Pu-11Float13

W2 W3 AA3 DF_INT_RN

BDF_RnB ICZ Pu-11Float13

AB3 V8 W6 DF_CLE_N

OE ND_CLE OCZ Pu-11Float13

AA9 AA10 AC11 DF_SCLK_E DF_SCLK_E OCZ Pd-01Float13

V1 V3 W1 GPIO0 GPIO0 ICOC

ZPd-01Float13

V2 U4 AA2 GPIO1 GPIO1 ICOC

ZPu-11Float13

V3 V1 Y1 GPIO2 GPIO2 ICOC

ZPu-11Float13

W5 Y3 AD3 NBE0 nBE0 OCZ Pu-11Float13

Y4 AA3 AC3 NBE1 nBE1 OCZ Pu-11Float13

AB7 Y10 AB11 NLLA nLLA OCZ Pu-11Float13

AA8 Y9 AD10 NLUA nLUA OCZ Pu-11Float13

W1 W1 AB1 NCS0 nCS0 OC High High High

U5 V4 AA1 NCS1 nCS1 OC High High High

VCC_IO3

AC15 W17 AC21 GPIO17 GPIO17 ICOC

ZPd-01Float13

AB15 W18 W17 GPIO18 GPIO18 ICOC

ZPd-01Float13

Y16 U17 AB21 GPIO19 GPIO19 ICOC

ZPd-01Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 110 April 6, 2009 Released

AC16 V18 AB23 GPIO20 GPIO20 ICOC

ZPu-11Float13

AC17 W19 Y22 GPIO21 GPIO21 ICOC

ZPu-11Float13

AB17 AA17 AC23 GPIO22 GPIO22 ICOC

ZPu-11Float13

AA17 Y17 AB22 GPIO23 GPIO23 ICOC

ZPu-11Float13

Y17 AA18 AD22 GPIO24 GPIO24 ICOC

ZPd-01Float13

W17 Y18 AA23 GPIO25 GPIO25 ICOC

ZPd-01Float13

AC18 Y19 AA24 GPIO26 GPIO26 ICOC

ZPd-01Float13

U19 V21 W19 GPIO27 GPIO27 ICOC

ZPd-01Float13

AC20 U21 Y23 GPIO28 GPIO28 ICOC

ZPd-01Float13

AC21 V19 Y24 GPIO29 GPIO29 ICOC

ZPd-01Float13

W20 V20 AA22 GPIO30 GPIO30 ICOC

ZPd-01Float13

Y21 U18 W22 GPIO31 GPIO31 ICOC

ZPd-01Float13

AB21 U20 W23 GPIO32 GPIO32 ICOC

ZPu-11Float13

AA21 U19 W18 GPIO33 GPIO33 ICOC

ZPu-11Float13

AA22 T20 W24 GPIO34 GPIO34 ICOC

ZPu-11Float13

AA23 T18 V20 GPIO35 GPIO35 ICOC

ZPu-11Float13

V21 T21 V23 GPIO36 GPIO36 ICOC

ZPu-11Float13

Y22 R17 V19 GPIO37 GPIO37 ICOC

ZPu-11Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 11 1

Y23 T17 U22 GPIO38 GPIO38 ICOC

ZPd-01Float13

AB18 E6 W15 GPIO2_2 GPIO2_2 ICOC

ZPu-11Float13

AA18 E5 W20 GPIO3_2 GPIO3_2 ICOC

ZPd-01Float13

Y18 G8 Y18 GPIO4_2 GPIO4_2 ICOC

ZPd-01Float13

AC19 F5 Y20 GPIO5_2 GPIO5_2 ICOC

ZPd-01Float13

W18 E7 Y19 GPIO6_2 GPIO6_2 ICOC

ZPu-11Float13

VCC_CI

W22 R18 U19 GPIO39 GPIO39 ICOC

ZPd-01Float13

W23 T19 V24 GPIO40 GPIO40 ICOC

ZPd-01Float13

T20 R20 U23 GPIO41 GPIO41 ICOC

ZPd-01Float13

V22 R19 T22 GPIO42 GPIO42 ICOC

ZPd-01Float13

V23 P16 U24 GPIO43 GPIO43 ICOC

ZPd-01Float13

U21 R21 T20 GPIO44 GPIO44 ICOC

ZPd-01Float13

U22 P17 R20 GPIO45 GPIO45 ICOC

ZPd-01Float13

U23 P18 T17 GPIO46 CIF_DD7 ICOC

ZPd-01Float13

T21 N16 P22 GPIO47 GPIO47 ICOC

ZPd-01Float13

T22 P21 R19 GPIO48 GPIO48 ICOC

ZPd-01Float13

T23 N17 P20 GPIO49 CIF_MCLK ICOC

ZPd-01Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 112 April 6, 2009 Released

R21 N18 R24 GPIO50 CIF_PCLK ICOC

ZPd-01Float13

R22 N19 N24 GPIO51 CIF_HSYNC ICOC

ZPd-01Float13

P20 M20 N20 GPIO52 CIF_VSYNC ICOC

ZPd-01Float13

VCC_LCD

R23 M17 R23 GPIO53 GPIO53 ICOC

ZPu-11Float13

N20 M21 P23 GPIO54 GPIO54 ICOC

ZPd-01Float13

P21 M18 N22 GPIO55 GPIO55 ICOC

ZPd-01Float13

P22 L18 P24 GPIO56 GPIO56 ICOC

ZPd-01Float13

N19 M19 N23 GPIO57 GPIO57 ICOC

ZPd-01Float13

P23 L20 P19 GPIO58 GPIO58 ICOC

ZPd-01Float13

N21 L17 M19 GPIO59 GPIO59 ICOC

ZPd-01Float13

N22 L21 L19 GPIO60 GPIO60 ICZ Pd-01Float13

N23 K19 M22 GPIO61 GPIO61 ICOC

ZPd-01Float13

M23 L19 M23 GPIO62 GPIO62 ICOC

ZPu-11Float13

M21 K20 J19 GPIO63 GPIO63 ICOC

ZPd-01Float13

M22 K17 M24 GPIO64 GPIO64 ICOC

ZPd-01Float13

L21 J17 L22 GPIO65 GPIO65 ICOC

ZPd-01Float13

L23 K21 K22 GPIO66 GPIO66 ICOC

ZPd-01Float13

L20 J18 L23 GPIO67 GPIO67 ICOC

ZPd-01Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 113

L22 K18 L20 GPIO68 GPIO68 ICOC

ZPd-01Float13

L19 J19 K20 GPIO69 GPIO69 ICOC

ZPd-01Float13

K23 J20 L24 GPIO70 GPIO70 ICOC

ZPd-01Float13

K21 J16 H19 GPIO71 GPIO71 ICOC

ZPd-01Float13

K22 J21 K23 GPIO72 GPIO72 ICOC

ZPd-01Float13

J23 H16 K24 GPIO73 GPIO73 ICOC

ZPd-01Float13

J22 H17 J22 GPIO74 GPIO74 ICOC

ZPd-01Float13

J19 H18 G19 GPIO75 GPIO75 ICOC

ZPd-01Float13

J21 H20 J23 GPIO76 GPIO76 ICOC

ZPd-01Float13

VCC_MEM

E3 G3 F2 DQM0 DQM0 OC High High High

T1 T4 U1 DQM1 DQM1 OC High High High

D2 F3 G3 DQS0 DQS0 ISOC

ZPd-0 Pd-0 Pd-0

T2 R4 V3 DQS1 DQS1 ISOC

ZPd-0 Pd-0 Pd-0

L3 L3 M1 MA0 MA0 OC High High High

N1 N4 R5 MA1 MA1 OC High High High

J4 H3 H2 MA2 MA2 OC High High High

N4 M1 P5 MA3 MA3 OC High High High

H3 H4 K3 MA4 MA4 OC High High High

M1 M3 P3 MA5 MA5 OC High High High

H2 K4 J1 MA6 MA6 OC High High High

M2 M2 N3 MA7 MA7 OC High High High

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 114 April 6, 2009 Released

H1 J1 K2 MA8 MA8 OC High High High

M3 L2 N1 MA9 MA9 OC High High High

L2 M4 N2 MA11 MA11 OC High High High

J3 K3 L3 MA12 MA12 OC High High High

L1 H5 M5 MA13 MA13 OC High High High

G1 H2 J3 MA14 MA14 OC High High High

G2 J4 J2 MA15 MA15 OC High High High

D3 D1 D1 MD0 MD0 ICSO

CZ Pd-0 Pd-0 Pd-0

C2 E1 E1 MD1 MD1 ICSO

CZ Pd-0 Pd-0 Pd-0

C1 E2 E2 MD2 MD2 ICSO

CZ Pd-0 Pd-0 Pd-0

G4 F1 F1 MD3 MD3 ICSO

CZ Pd-0 Pd-0 Pd-0

F3 F2 G1 MD4 MD4 ICSO

CZ Pd-0 Pd-0 Pd-0

E1 G1 G2 MD5 MD5 ICSO

CZ Pd-0 Pd-0 Pd-0

F2 G2 H3 MD6 MD6 ICSO

CZ Pd-0 Pd-0 Pd-0

F1 H1 H1 MD7 MD7 ICSO

CZ Pd-0 Pd-0 Pd-0

R1 P3 T2 MD8 MD8 ICSO

CZ Pd-0 Pd-0 Pd-0

R2 R3 T1 MD9 MD9 ICSO

CZ Pd-0 Pd-0 Pd-0

R3 R1 U3 MD10 MD10 ICSO

CZ Pd-0 Pd-0 Pd-0

R4 T2 U2 MD11 MD11 ICSO

CZ Pd-0 Pd-0 Pd-0

T3 T1 V2 MD12 MD12 ICSO

CZ Pd-0 Pd-0 Pd-0

U1 U2 V1 MD13 MD13 ICSO

CZ Pd-0 Pd-0 Pd-0

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 115

U2 T3 W2 MD14 MD14 ICSO

CZ Pd-0 Pd-0 Pd-0

U3 U1 W3 MD15 MD15 ICSO

CZ Pd-0 Pd-0 Pd-0

N3 N3 T3 NSDCAS nSDCAS OC High High High

K1 L1 M3 NSDCS0 nSDCS0 OC High High High

K2 J2 M2 NSDCS1 nSDCS1 OC High High High

N2 P2 P2 NSDRAS nSDRAS OC High High High

P1 P1 R3 NSDWE nSDWE OC High High High

N5 N1 P1 RCOMP_DD

RRCOMP_DDR OA - - -

P2 R2 R2 SDCKE SDCKE OC Low Low Low

K3 K1 L1 SDCLK0 SDCLK0 OC Low Low Low

K4 K2 L2 SDCLK1 SDCLK1 OC High High High

K5 J3 K1 SDMA10 SDMA10 OC High High High

VCC_MSL

H23 H19 H22 GPIO77 GPIO77 ICOC

ZPd-01Float13

H22 G16 J24 GPIO78 GPIO78 ICOC

ZPd-01Float13

J20 F16 J20 GPIO79 GPIO79 ICOC

ZPd-01Float13

G23 H21 H23 GPIO80 GPIO80 ICOC

ZPd-01Float13

G22 G18 G23 GPIO81 GPIO81 ICOC

ZPd-01Float13

H21 G20 G22 GPIO82 GPIO82 ICOC

ZPd-01Float13

F23 G19 F23 GPIO83 GPIO83 ICOC

ZPd-01Float13

G21 G21 F20 GPIO84 GPIO84 ICOC

ZPu-11Float13

F22 F19 F22 GPIO85 GPIO85 ICOC

ZPd-01Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 116 April 6, 2009 Released

E23 E16 H24 GPIO86 GPIO86 ICOC

ZPd-01Float13

E22 F18 E23 GPIO87 GPIO87 ICOC

ZPd-01Float13

F21 F20 E22 GPIO88 GPIO88 ICOC

ZPd-01Float13

F20 E17 G24 GPIO89 GPIO89 ICOC

ZPu-11Float13

D23 F21 D23 GPIO90 GPIO90 ICOC

ZPu-11Float13

VCC_USB

A3 A5 C3 USBH1_N USBH1_N IAOA Pd-0

8Pd-08Pd-08

A4 B5 B4 USBH1_P USBH1_P IAOA Pd-08Pd-08Pd-08

C3 A3 B3 USBOTG_N USBOTG_N IAOA Hi-Z Hi-Z or Pd-09Hi-Z or

Pd-09

B3 A4 A3 USBOTG_P USBOTG_P IAOA Hi-Z Hi-Z or Pd-0

or Pu-18, 10 Hi-Z or Pd-0

or Pu-18, 10

VCC_CARD1

AA11 U11 AB14 GPIO3 GPIO3 ICOC

ZPd-01Float13

AC8 AA11 AC14 GPIO4 GPIO4 ICOC

ZPd-01Float13

AB11 V12 AB15 GPIO5 GPIO5 ICOC

ZPd-01Float13

AC9 V13 AD17 GPIO6 GPIO6 ICOC

ZPu-11Float13

AC10 W14 AB17 GPIO7 GPIO7 ICOC

ZPd-01Float13

AA13 U14 Y16 GPIO8 GPIO8 ICOC

ZPd-01Float13

VCC_CARD2

AC11 U12 AD16 GPIO9 GPIO9 ICOC

ZPd-01Float13

AC12 Y14 AB18 GPIO10 GPIO10 ICOC

ZPd-01Float13

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 117

AB13 V14 AB19 GPIO11 GPIO11 ICOC

ZPd-01Float13

AC13 U16 AC20 GPIO12 GPIO12 ICOC

ZPu-11Float13

AB14 V15 AC19 GPIO13 GPIO13 ICOC

ZPd-01Float13

AC14 Y15 AD20 GPIO14 GPIO14 ICOC

ZPd-01Float13

Y15 Y16 Y17 GPIO15 GPIO15 ICOC

ZPu-11Float13

AA15 V16 AD19 GPIO16 GPIO16 ICOC

ZPu-11Float13

RFU Balls

P4 J8 E18 RFU_P4/

RFU_J8/

RFU_E18

B21 K8 E2 0 RFU_B21/

RFU_K8/

RFU_E20

C19 N2 F18 RFU_C19/

RFU_N2/

RFU_F18

C20 N8 F19 RFU_C20/

RFU_N8/

RFU_F19

D18 P8 N17 RFU_D18/

RFU_P8/

RFU_N17

—————

R15 P17 RFU_R15/R

FU_P17 —————

R16 R1 RFU_R16/R

FU_R1 —————

V17 U17 RFU_V17/R

FU_U17 —————

W9 AD11 RFU_W9/RF

U_AD11 —————

W20 RFU_W20 — — — — —

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 118 April 6, 2009 Released

W21 RFU_W21 — — — — —

No Connect (NC) Balls

A1 B4 A1 NC — — — — —

A2 C1 A2 NC — — — — —

B1 C5 A23 NC — — — — —

B2 D19 A24 NC — — — — —

A22 G4 B1 NC — — — — —

A23 L4 B24 NC — — — — —

B22 L8 E17 NC — — — — —

B23 M8 E19 NC — — — — —

V19 P4 W5 NC — — — — —

V20 P5 W7 NC — — — — —

W10 U3 W8 NC — — — — —

W19 V2 W9 NC — — — — —

Y19 U13 W12 NC — — — — —

Y20 W2 Y9 NC — — — — —

AA19 AA19 AB6 NC — — — — —

AA20 AC1 NC — — — — —

AB19 AC6 NC — — — — —

AB20 AC24 NC — — — — —

AB1 AD1 NC — — — — —

AB2 AD2 NC — — — — —

AC1 AD23 NC — — — — —

AC2 AD24 NC — — — — —

AB22 NC — — — — —

AB23 NC — — — — —

AC22 NC — — — — —

AC23 NC — — — — —

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 119

AA5 NC — — — — —

Internal NAND Signals

U5 DF_NWP DF_NWP Input Input Input Input

Power Supplies

E11 A10 B17 VCC_APPS VCC_APPS PS Input Input Input

E14 A13 C14 VCC_APPS VCC_APPS PS Input Input Input

L4 A15 E11 VCC_APPS VCC_APPS PS Input Input Input

R20 H10 H10 VCC_APPS VCC_APPS PS Input Input Input

W9 H11 H15 VCC_APPS VCC_APPS PS Input Input Input

W13 H12 K8 VCC_APPS VCC_APPS PS Input Input Input

Y12 K14 K17 VCC_APPS VCC_APPS PS Input Input Input

L5 L5 VCC_APPS VCC_APPS PS Input Input Input

L14 R8 VCC_APPS VCC_APPS PS Input Input Input

M14 R17 VCC_APPS VCC_APPS PS Input Input Input

N5 T24 VCC_APPS VCC_APPS PS Input Input Input

N21 U10 VCC_APPS VCC_APPS PS Input Input Input

P10 U15 VCC_APPS VCC_APPS PS Input Input Input

P11 AB16 VCC_APPS VCC_APPS PS Input Input Input

P12 AC9 VCC_APPS VCC_APPS PS Input Input Input

Y13 VCC_APPS VCC_APPS PS Input Input Input

AA7 VCC_APPS VCC_APPS PS Input Input Input

AA9 VCC_APPS VCC_APPS PS Input Input Input

AA12 VCC_APPS VCC_APPS PS Input Input Input

D7 C8 E8 VCC_BBAT

TVCC_BBATT PS Input Input Input

B9 D10 C9 VCC_BG VCC_BG PS Input Input Input

AA12 Y11 AC15 VCC_CARD

1VCC_CARD1 PS Input Input Input

Y14 AA14 AD18 VCC_CARD

2VCC_CARD2 PS Input Input Input

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 120 April 6, 2009 Released

R19 P15 R22 VCC_CI VCC_CI PS Input Input Input

P20 VCC_CI VCC_CI PS Input Input Input

V4 G11 Y6 VCC_DF VCC_DF PS Input Input Input

W6 T9 AB4 VCC_DF VCC_DF PS Input Input Input

W8 T10 AB7 VCC_DF VCC_DF PS Input Input Input

Y11 T11 AB10 VCC_DF VCC_DF PS Input Input Input

T12 AB13 VCC_DF VCC_DF PS Input Input Input

T13 AC12 VCC_DF VCC_DF PS Input Input Input

B11 E15 A11 VCC_IO1 VCC_IO1 PS Input Input Input

E16 G10 C16 VCC_IO1 VCC_IO1 PS Input Input Input

F19 G15 F24 VCC_IO1 VCC_IO1 PS Input Input Input

W21 V22 VCC_IO3 VCC_IO3 PS Input Input Input

AA16 T16 AB20 VCC_IO3 VCC_IO3 PS Input Input Input

K19 K16 K19 VCC_LCD VCC_LCD PS Input Input Input

M19 L16 VCC_LCD VCC_LCD PS Input Input Input

M16 VCC_LCD VCC_LCD PS Input Input Input

D1 D5 D2 VCC_MEM VCC_MEM PS Input Input Input

G3 G5 E3 VCC_MEM VCC_MEM PS Input Input Input

G5 G6 F3 VCC_MEM VCC_MEM PS Input Input Input

J1 H6 G5 VCC_MEM VCC_MEM PS Input Input Input

M5 J6 J5 VCC_MEM VCC_MEM PS Input Input Input

R5 K6 K5 VCC_MEM VCC_MEM PS Input Input Input

T5 L6 N5 VCC_MEM VCC_MEM PS Input Input Input

M6 T5 VCC_MEM VCC_MEM PS Input Input Input

N6 V5 VCC_MEM VCC_MEM PS Input Input Input

P6 Y2 VCC_MEM VCC_MEM PS Input Input Input

R6 VCC_MEM VCC_MEM PS Input Input Input

T6 VCC_MEM VCC_MEM PS Input Input Input

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 121

U6 VCC_MEM VCC_MEM PS Input Input Input

V5 VCC_MEM VCC_MEM PS Input Input Input

H20 G17 H20 VCC_MSL VCC_MSL PS Input Input Input

D10 E4 B18 VCC_MVT VCC_MVT PS Input Input Input

E17 G9 C21 VCC_MVT VCC_MVT PS Input Input Input

G20 G14 F9 VCC_MVT VCC_MVT PS Input Input Input

H5 H15 H6 VCC_MVT VCC_MVT PS Input Input Input

P3 J5 N19 VCC_MVT VCC_MVT PS Input Input Input

P19 J15 P6 VCC_MVT VCC_MVT PS Input Input Input

W14 N15 U6 VCC_MVT VCC_MVT PS Input Input Input

AA7 R14 W16 VCC_MVT VCC_MVT PS Input Input Input

T5 AC8 VCC_MVT VCC_MVT PS Input Input Input

U9 VCC_MVT VCC_MVT PS Input Input Input

A8 D9 B8 VCC_OSC1

3M VCC_OSC13M PS Input Input Input

C13 D12 C11 VCC_PLL VCC_PLL PS Input Input Input

W16 AA16 AC22 VCC_PLL VCC_PLL PS Input Input Input

D19 B19 B21 VCC_SRAM VCC_SRAM PS Input Input Input

Y9 C18 W11 VCC_SRAM VCC_SRAM PS Input Input Input

AA8 VCC_SRAM VCC_SRAM PS Input Input Input

B4 B3 A4 VCC_USB VCC_USB PS Input Input Input

J9 A9 C17 VSS VSS PS Input Input Input

J10 A20 E7 VSS VSS PS Input Input Input

J11 A21 E12 VSS VSS PS Input Input Input

J12 B13 H8 VSS VSS PS Input Input Input

J13 B16 H9 VSS VSS PS Input Input Input

J14 B20 H11 VSS VSS PS Input Input Input

J15 B21 H13 VSS VSS PS Input Input Input

E10 C2 H14 VSS VSS PS Input Input Input

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 122 April 6, 2009 Released

E13 F4 H17 VSS VSS PS Input Input Input

G19 H8 J8 VSS VSS PS Input Input Input

J5 H9 J17 VSS VSS PS Input Input Input

L5 H13 L8 VSS VSS PS Input Input Input

K9 H14 L17 VSS VSS PS Input Input Input

K10 J14 M6 VSS VSS PS Input Input Input

K11 K5 M8 VSS VSS PS Input Input Input

K12 M5 M17 VSS VSS PS Input Input Input

K13 N14 N8 VSS VSS PS Input Input Input

K14 N20 P8 VSS VSS PS Input Input Input

K15 P9 T8 VSS VSS PS Input Input Input

L9 P13 T23 VSS VSS PS Input Input Input

L10 P14 U5 VSS VSS PS Input Input Input

L11 R5 U8 VSS VSS PS Input Input Input

L12 R8 U9 VSS VSS PS Input Input Input

L13 T8 U11 VSS VSS PS Input Input Input

L14 T14 U12 VSS VSS PS Input Input Input

L15 Y7 U13 VSS VSS PS Input Input Input

M9 AA13 U14 VSS VSS PS Input Input Input

M10 D7 U16 VSS VSS PS Input Input Input

M11 AC10 VSS VSS PS Input Input Input

M12 AC16 VSS VSS PS Input Input Input

M13 AC17 VSS VSS PS Input Input Input

M14 AD8 VSS VSS PS Input Input Input

M15 VSS VSS PS Input Input Input

N9 VSS VSS PS Input Input Input

N10 VSS VSS PS Input Input Input

N11 VSS VSS PS Input Input Input

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 123

N12 VSS VSS PS Input Input Input

N13 VSS VSS PS Input Input Input

N14 VSS VSS PS Input Input Input

N15 VSS VSS PS Input Input Input

P9 VSS VSS PS Input Input Input

P10 VSS VSS PS Input Input Input

P11 VSS VSS PS Input Input Input

P12 VSS VSS PS Input Input Input

P13 VSS VSS PS Input Input Input

P14 VSS VSS PS Input Input Input

P15 VSS VSS PS Input Input Input

R9 VSS VSS PS Input Input Input

R10 VSS VSS PS Input Input Input

R11 VSS VSS PS Input Input Input

R12 VSS VSS PS Input Input Input

R13 VSS VSS PS Input Input Input

R14 VSS VSS PS Input Input Input

R15 VSS VSS PS Input Input Input

W12 VSS VSS PS Input Input Input

Y10 VSS VSS PS Input Input Input

AA6 VSS VSS PS Input Input Input

Y13 VSS VSS PS Input Input Input

C6 VSS VSS PS Input Input Input

B7 D8 F8 VSS_BBATT VSS_BBATT PS Input Input Input

D11 C10 F10 VSS_BG VSS_BG PS Input Input Input

AA14 Y12 Y15 VSS_CARD

1VSS_CARD1 PS Input Input Input

AB12 VSS_CARD

1VSS_CARD1 PS Input Input Input

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 124 April 6, 2009 Released

AA15 AC18 VSS_CARD

2VSS_CARD2 PS Input Input Input

T19 P19 T19 VSS_CI VSS_CI PS Input Input Input

V5 G12 W14 VSS_DF VSS_DF PS Input Input Input

W7 R9 Y5 VSS_DF VSS_DF PS Input Input Input

W11 R10 Y8 VSS_DF VSS_DF PS Input Input Input

R11 Y10 VSS_DF VSS_DF PS Input Input Input

R12 Y11 VSS_DF VSS_DF PS Input Input Input

R13 Y13 VSS_DF VSS_DF PS Input Input Input

Y1 VSS_DF VSS_DF PS Input Input Input

Y2 VSS_DF VSS_DF PS Input Input Input

AA1 VSS_DF VSS_DF PS Input Input Input

AA2 VSS_DF VSS_DF PS Input Input Input

D12 F15 A18 VSS_IO1 VSS_IO1 PS Input Input Input

D16 G13 B11 VSS_IO1 VSS_IO1 PS Input Input Input

E19 B22 VSS_IO1 VSS_IO1 PS Input Input Input

U20 T15 U20 VSS_IO3 VSS_IO3 PS Input Input Input

AB16 Y20 AB24 VSS_IO3 VSS_IO3 PS Input Input Input

Y21 VSS_IO3 VSS_IO3 PS Input Input Input

AA20 VSS_IO3 VSS_IO3 PS Input Input Input

AA21 VSS_IO3 VSS_IO3 PS Input Input Input

K20 K15 M20 VSS_LCD VSS_LCD PS Input Input Input

M20 L15 VSS_LCD VSS_LCD PS Input Input Input

M15 VSS_LCD VSS_LCD PS Input Input Input

E2 F6 C1 VSS_MEM VSS_MEM PS Input Input Input

F4 F7 C2 VSS_MEM VSS_MEM PS Input Input Input

F5 G7 F5 VSS_MEM VSS_MEM PS Input Input Input

H4 H7 G6 VSS_MEM VSS_MEM PS Input Input Input

J2 J7 H5 VSS_MEM VSS_MEM PS Input Input Input

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Versi on -

April 6, 2009 Released Page 125

M4 K7 J6 VSS_MEM VSS_MEM PS Input Input Input

P5 L7 K6 VSS_MEM VSS_MEM PS Input Input Input

T4 M7 L6 VSS_MEM VSS_MEM PS Input Input Input

U4 N7 N6 VSS_MEM VSS_MEM PS Input Input Input

P7 R6 VSS_MEM VSS_MEM PS Input Input Input

R7 T6 VSS_MEM VSS_MEM PS Input Input Input

T7 V6 VSS_MEM VSS_MEM PS Input Input Input

U7 Y3 VSS_MEM VSS_MEM PS Input Input Input

H19 F17 G20 VSS_MSL VSS_MSL PS Input Input Input

C9 E9 C10 VSS_OSC1

3M VSS_OSC13M PS Input Input Input

D13 E11 C13 VSS_PLL VSS_PLL PS Input Input Input

W15 E12 AD21 VSS_PLL VSS_PLL PS Input Input Input

W16 VSS_PLL VSS_PLL PS Input Input Input

C4 A1 B2 VSS_USB VSS_USB PS Input Input Input

A2 VSS_USB VSS_USB PS Input Input Input

B1 VSS_USB VSS_USB PS Input Input Input

B2 VSS_USB VSS_USB PS Input Input Input

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 126 April 6, 2009 Released

4.2.4 Signal Type Definitions

Table 12 contains the signal type de finitions for Table 9, Table 10 and Table 11.

1. GPIO reset/S3 operation: After any reset is asserted or if PXA30x processor is in S3/D4/C4 power mode, these pins are

configur ed as the pri m ar y fu nc tion of the MF P (ge nerally as G P IO in put ) and default pul l up or pulldown oc curs.

2. Crystal oscil la to r pins: These pi ns connect the exter nal crystals to the on- chip oscill at or s and are no t affected by ei t her

reset or S2/D3/C4 power mode. For more information, For more information, see the “Clocks Control and Power

Management ” ch apter in the PXA3x x Pr ocessor F am il y Vol. I: System and Timer C onfi guration D eve lo pers Manua l .

3. Each MFP out put value is based on MFPRx x[ Sl eep_sel] , MFPRxx[s leep_data], MFPRxx[sleep_oe_n] ,

MFPRxx[ pull_sel] , MFPRxx[p ul lup_en] an d M FPR x x[ pulldown_ en] following S2/D3/C 4 w ak e- up. To pre ve nt

unnecessary cu rrent drain , en sure input si gnals are not floating du ring low-p ow er m odes. Each G P I O to be dr i ven can

be progr am m ed to a 0/1 or be pul led up or pulled down du ring S 2/D 3/ C 4 pow er m ode if the MVT and the IO (HVT)

supplie s are present.

4. Logic low when OSCC[TENSx] bit is cleared, CLK_TOUT when OSCC[TENSx] is set. Configure TENS2 for S2/D3/C4

mode and TEN S3 for S3/D4 /C 4 pow e r m o de.

5. Pulldown al ways enabled.

6. Output functions during S2/D3/C4 power mode.

7. Pullup always enabled.

8. 20 KΩ nom i nal, 14.5 K Ω m i n - 24 .5 KΩ max

9. Pd-0 if UP2OCR[DMPDE] is set, then Pd-0, Hi-Z if UP2OCR[DMPDE] is cleared.

10. Hi-Z if UP2OCR[DPPDE] is cleared and UP2OCR[DPPUE] is cleared; Pu-1 if UP2OCR[DPPDE] is cleared and

UP2OCR[DPPUE] is set; Pd-0 if UP2OCR[DPPDE] is set an d UP2OCR[DPPUE] is cleared. Sett in g UP2OCR[DPPDE]

and UP2OCR[D PPU E] at the sam e tim e is not allowe d.

11. This sig nal’s pullup/pull do w n is enabled dur in g power-o n, har dware, glob al wat chdog and GPIO resets. The

pullup/pulldown must be disabled by software by setting PCFR[PUDH] after the external devices driving these pins are

configured.

12. There is no pullup or pulldown on this pin. Asserts if PCFR[SL_ROD] is clear.

Table 11: PXA30x Pin Usage Summary (Continued)

19mm2

Ball # 15mm2

Ball # 13mm2

Ball # Ball Name Function

After Reset Type Reset

State S3/D4/C4

Power

Mode

S2/D3/C4

Power

Mode

Table 12: Signal Types

Abbreviation Type Description Abbreviation Type Description

IC CMOS input ISOCZ SSTL input, CMOS output,

three-stateable

OC CMOS output OA Analog output

OCZ CMOS output, three-stateable IAOA Analog bidirectional

ICOCZ CMOS bidirectional, three-stateable IAOAZ Analog bidirectional - three-stateable

IA Analog input PS Power supply

OS SSTL output IS SSTL Input

ICSOCZ CMOS or SSTL input, CMOS output,

three-stateable

Versi on -

April 6, 2009 Released Page 127

5Maximum Ratings and Operation

Conditions

5.1 Absolute Maximum Ratings

The absolute maximum ratings (shown in Table 13) define limitations for electrical and thermal

stresses. These limits prevent permanent damage to the PXA3xx Processor Family.

Note

Absolute maximum ratings are not operat ing ranges . Operati on at abs o lute maximum

ratings is not guaranteed.

Table 13: Absolute Maximum Ratings

Symbol Description Min Max Units

TSStorage temperature –40 125 °C

Voltage applied to VCC_BBATT 2.0 4 .0 V

VCC_HV

Voltage applied t o high-voltage sup pl y pi ns

VCC_MSL, VCC_CARD2, VCC_CARD1, VCC_ IO1, VCC_CI,

VCC_DF, VCC_LCD).VCC_IO3

VSS–0.3 VSS+4.0

VCC_IO4, VCC_IO6, VCC_TSI (PXA32x Only) V

VCC_USB (PXA32x and PXA30x only) V

VCC_BIAS (PXA3 1x only) V

VCC_ULPI (PXA3 1x only) VSS–0.3 VSS+2.0 V

VCC_MV Voltage appl i ed to l ow - vol tag e supply pin s

(VCC_MVT, VCC_BG, VCC_PLL, VCC_OSC13 M, VCC_MEM) VSS–0.3 VSS+2.0 V

VCC_LV Vo l tage ap pl ied t o l ow - vol tag e supply pin s

(VCC_APPS, VCC_SRAM) VSS–0.3 VSS+1.54 V

VIP Voltage applied to non-sup ply pi ns excep t PXTAL_IN,

PXTAL_OUT, TXTAL_IN, and TXTAL_OUT pins VSS–0.3 VSS+4.0 V

VIP_X Voltage ap pli ed t o XTAL pins

(PXTAL _I N, PXTAL_OUT, TXTAL_IN, TXTAL_OU T) VSS–0.3 VSS+1.9 V

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 128 April 6, 2009 Released

5.2 Operating Conditions

This se cti on dis cu sses op erat ing vo lt a ge, freq uen cy, and tem pe ratu re s pec ifica tio ns for t he PX A 3xx

Processor Family.

Table 14 shows each power domains su pported v o ltages. Table 14 also sh ows the application core

frequency and supply voltage operating ranges for VCC_SRAM and VCC_APPS of the PXA32x

processor, PXA31x processor and the PXA30x processor. Each frequency range is specified in one

of the following formats:

(turbo frequency / run frequency / internal switch bus frequency / internal system bus frequen cy)

(turbo frequency / run frequency / internal switch bus frequency / internal system bus frequen cy /

SRAM freque ncy)

(Power Mode (Sx/Dx/Cx) / SRAM frequency (optiona l))

Refer to the “Clocks Controller and Pow er Management Unit” chapter of the PXA3xx Processor

Family Vol. I: System and Timer Configuration Developers Manual for supported frequencies and

clock -register settings as listed in Table 14.

VESD Maximum ESD stress voltage, three stresses

maximum:

• Any pin to any suppl y pin, ei t her polarity, or

• Any pin to al l non- supply pin s t ogether,

either polarity

HBM1— 2000 V

CDM2—700V

IEOS Maximum DC input current (electrical overstress) for any

non-supply pin —5 mA

NOTE:

1. HBM = human body model

2. CDM = charge device model

Table 13: Absolute Maximum Ratings (Continued)

Symbol Description Min Max Units

Table 14: Voltage, Temperature, and Frequency Electrical Specifications

Symbol Description Min Typical Max Units

Notes

Operating Temperature

Tcase Package operat in g te m perature (Standar d Temp) -25 — +8 5 °C 1

Tcase Package operat in g te m perature (Ex te nded Te m p)

(PXA32x Only) -40 — +85 °C 1

Theta Jc Junction-to-case temperature gradient (VF-BGA) — 2.00 — °C /

watt —

VCC_BBATT Voltage

Vccbatt Voltage applied on VC C_BBATT 2.40 3.00 3.60 V —

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April 6, 2009 Released Page 129

Tbbattra m p R am p R a te 5.0

μV/μs— 20.00 V/μs—

VCC_MVT Voltage

Vccmvt_0 Voltage app lied on VC C_MVT in S3 /D4/C4 — 0 — V —

Vccmvt_1 Voltage app lied on VCC _M VT 1.70 1.80 1.90 V —

Vccmvt_2 Voltage app lied on VCC _M VT 1.80 1.90 2.00 V 3

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs—

VCC_BG Voltage

Vccbg_0 Voltage applied on VCC_BG in S3/D 4 /C4 — 0 — V —

Vccbg_1 Voltage applied on VC C_BG 1.70 1.80 1.90 V —

Vccbg_2 Voltage applied on VC C_BG 1.80 1.90 2.00 V 3

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs—

VCC_PLL Voltage

Vccpll_0 Voltage applied on VC C_PLL in S3/ D4/ C 4 — 0 — V —

Vccpll_1 Voltage applied on VC C_PLL 1.70 1.80 1.90 V —

Vccpll_2 Voltage applied on VC C_PLL 1.80 1.90 2.00 V 3

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs—

VCC_OSC13M Voltage

Vccosc13m_0 Voltage applied on VC C_OSC13M in S3/D4/C4 —0 —V —

Vccosc13m_1 Voltage applied on VCC _O SC 1 3M 1.70 1.80 1.90 V —

Vccosc13m_2 Voltage applied on VCC _O SC 1 3M 1.80 1.90 2.00 V 3

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs—

VCC_APPS Voltage at Frequency Ranges (Turbo/Run/Switch/System Bus), (Power Mode

(Sx/Dx/Cx)) (Standard BIN Only)

Vccapps_0 Voltage app lied on VC C_APP S in S3/ D 4/C 4,

S2/D3/C4 —0—V—

Vccapps_1 Voltage applied on VCC_APPS at S 0/D 0C S/C0,

104/104/104/10 4, 208 /2 08/208/104 1.05 1.10 1.2 V 2, 5

Vccapps_2 Voltage app lied on VC C_APP S at

416/208/208/156 1.05 1.10 1.2 V 2

Table 14: Voltage, Temperature, and Frequency Electrical Specifications (Continued)

Symbol Description Min Typical Max Units

Notes

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 130 April 6, 2009 Released

Vccapps_3 Voltage applied on VCC_APPS at

624/312/312/208 1.31 1.375 1.475 V 2

Vccapps_4 Voltage applied on VCC _APPS in S0/D2/C2,

S0/D1/C2 or at 806/ 403/40 3/ 20 8 7 1.33 1.40 1.50 V 2

Tpwrramp Ramp Rate 2.00 10.00 12.00 mV/μs—

VCC_SRAM Voltage at Frequency Range (Turbo/Run/Switch/System Bus/SRAM), (Power Mode

(Sx/Dx/Cx) @ SRAM frequency) (Standard BIN Only)

Vccsram_0 Voltage applied on VCC_SRAM in S3 /D4 / C4 or

S2/D3/C4 —0 —V —

Vccsram_1 Voltage applied on VCC_SRA M at S0/D0CS/C0,

104/104/104/10 4 or 208/208/2 08/ 104 1.05 1.10 1.20 V 2, 5

Vccsram_2 Voltage applied on VCC_SRA M at

416/208/208/156 1.05 1.10 1.2 V 2

Vccsram_3 Voltage applied on VCC_SRA M at

624/312/312/208 1.31 1.375 1.475 V 2, 5

Vccsram_4 Voltage applied on VCC_SRAM in S2 /D3 / C44,

S0/D2/C2, S0/D1/C2, or 806/403/403/ 20871.33 1.40 1.5 V 2, 5

Tpwrramp Ramp Rate 2.00 10.00 12.00 mV/μs6

VCC_APPS Voltage at Frequency Ranges (Turbo/Run/Switch/System Bus), (Power Mode

(Sx/Dx/Cx)) (Low Power BIN Only)

Vccapps_0 Voltage app lied on VC C_APPS in S3/D4/C4, or

S2/D3/C4 —0 —V —

Vccapps_1 Voltage applied on VCC_APPS at S 0/D 0C S/C0,

104/104/104/10 4, 208 /2 08/208/104 0.975 1.00 1.10 V 2, 5

Vccapps_2 Voltage app lied on VC C_APP S at

416/208/208/156 1.05 1.10 1.2 V 2

Vccapps_3 Voltage applied on VCC_APPS at

624/312/312/208 1.31 1.375 1.475 V 2

Vccapps_4 Voltage applied on VCC_APPS in S0/D2/C2,

S0/D1/C2 or at 806/403/403/2 08 71.33 1.40 1.50 V 2

Tpwrramp Ramp Rate 2.00 10.00 12.00 mV/μs—

VCC_SRAM Voltage at Frequency Range (Turbo/Run/Switch/System Bus/SRAM), (Power Mode

(Sx/Dx/Cx) @ SRAM frequency) (Low Power BIN Only)

Vccsram_0 Voltage applied on VCC_SRA M in S3/D4/C4 or

S2/D3/C4 —0 —V —

Table 14: Voltage, Temperature, and Frequency Electrical Specifications (Continued)

Symbol Description Min Typical Max Units

Notes

Versi on -

April 6, 2009 Released Page 131

Vccsram_ 1 Voltage applied on VCC_SRA M at S0/D0 C S/ C0,

104/104/104/10 4 or 208/208/2 08/ 104 0.975 1.00 1.20 V 2, 5

Vccsram_2 Voltage applied on VCC_SRA M at

416/208/208/156 1.05 1.10 1.2 V 2

Vccsram_3 Voltage applied on VCC_SRA M at

624/312/312/208 1.31 1.375 1.475 V 2, 5

Vccsram_4 Voltage applied on VCC_SRAM in S2 /D3 / C44,

S0/D2/C2, S0/D1/C2 or at 806/403/403/20871.33 1.40 1.5 V 2, 5

Tpwrramp Ramp Rate 2.00 10.00 12.00 mV/μs6

VCC_MEM Voltage

Vccmem_0 Voltage applied on VCC_MEM i n S3/ D4/ C 4 — 0 — V —

Vccmem_1 Voltage applied on VCC_MEM 1.70 1.80 1.90 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_IO1 Voltage

Vccio1_ 0 Vol tage applied on VCC_IO1 in S3/ D 4/ C4 — 0 — V —

Vccio1_ 1 Vol tage applied on VCC_IO1 1.70 1.80 1.98 V —

Vccio1_ 2 Vol tage applied on VCC_IO1 2.70 3.00 3.30 V —

Vccio1_ 3 Vol tage applied on VCC_IO1 2.97 3.30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_IO3 Voltage

Vccio3_ 0 Vol tage applied on VCC_IO3 in S3/ D 4/ C4 — 0 — V —

Vccio3_ 1 Vol tage applied on VCC_IO3 1.70 1.80 1.98 V —

Vccio3_ 2 Vol tage applied on VCC_IO3 2.70 3.00 3.30 V —

Vccio3_ 3 Vol tage applied on VCC_IO3 2.97 3.30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_IO4 Voltage (PXA32x Only)

Vccio4_0 Voltage applied on VCC_IO4 in S3/D4/C4 —0—V—

Vccio4_1 Voltage applied on VCC_IO4 1.70 1.80 1.98 V —

Vccio4_2 Voltage applied on VCC_IO4 2.70 3.00 3.30 V —

Vccio4_3 Voltage applied on VCC_IO4 2.97 3.30 3.63 V —

Table 14: Voltage, Temperature, and Frequency Electrical Specifications (Continued)

Symbol Description Min Typical Max Units

Notes

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 132 April 6, 2009 Released

Tsysramp Ramp Rate —10.00 12.00 mV/μs —

VCC_IO6 Voltage (PXA32x Only)

Vccio6_0 Voltage applied on VCC_IO6 in S3/D 4/ C 4 —0—V—

Vccio6_1 Voltage applied on VCC_IO6 1.70 1.80 1.98 V —

Vccio6_2 Voltage applied on VCC_IO6 2.70 3.00 3.30 V —

Vccio6_3 Voltage applied on VCC_IO6 2.97 3.30 3.63 V —

Tsysramp Ramp Rate —10.00 12.00 mV/μs —

VCC_MSL Voltage

Vccmsl_0 Voltage app lied on VCC _M SL in S3/D4/C 4 — 0 — V —

Vccmsl_1 Voltage applied on VCC_MSL 1.70 1.80 1.98 V —

Vccmsl_2 Voltage applied on VCC_MSL 2.70 3.00 3.30 V —

Vccmsl_3 Voltage applied on VCC_MSL 2.97 3.30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_LCD Voltage

Vcclcd_ 0 Voltage applied on VC C_LCD in S3/D4/C 4 — 0 — V —

Vcclcd_ 1 Voltage app lied on VCC_LCD 1.70 1.80 1.98 V —

Vcclcd_ 2 Voltage app lied on VCC_LCD 2.70 3.00 3.30 V —

Vcclcd_ 3 Voltage app lied on VCC_LCD 2.97 3.30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_BIAS Voltage (PXA310 only)

Vccbias_0 Voltage applied on VCC_BIAS in S3/D4 /C4 — 0 — V —

Vccbias_1 Voltage applied on VCC_BIAS 1.80 3.30 3.6 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_USB Voltage (PXA32x and PXA30x only)

Vccusb_0 Voltage app lied on VCC_USB in S3/D4/C 4 — 0 — V —

Vccusb_1 Voltage app lied on VC C_USB 3.00 3.30 3.6 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_ULPI Voltage (PXA31x only)

Table 14: Voltage, Temperature, and Frequency Electrical Specifications (Continued)

Symbol Description Min Typical Max Units

Notes

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April 6, 2009 Released Page 133

Vcculpi_0 Voltage app lied on VC C_ULP I in S3/D 4 /C4 — 0 — V —

Vcculpi_1 Voltage app lied on VCC _ULPI 1.70 1.80 1.98 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_CARD1 Voltage

Vcccard 1_0 Voltage applied on VC C_CARD1 in S3/D 4/C 4 — 0 — V —

Vcccard 1_1 Voltage applied on VCC_CARD1 1.70 1. 80 1.98 V —

Vcccard 1_2 Voltage applied on VCC_CARD1 2.70 3. 00 3.30 V —

Vcccard 1_3 Voltage applied on VCC_CARD1 2.97 3. 30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_CARD2 Voltage

Vcccard 2_0 Voltage applied on VC C_CARD2 in S3/D 4/C 4 — 0 — V —

Vcccard 2_1 Voltage applied on VCC_CARD2 1.70 1. 80 1.98 V —

Vcccard 2_2 Voltage applied on VCC_CARD2 2.70 3. 00 3.30 V —

Vcccard 2_3 Voltage applied on VCC_CARD2 2.97 3. 30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_DF Voltage

Vccdf_0 Voltage app lied on VC C_DF in S3/D 4/C4 — 0 — V —

Vccdf_1 Voltage app lied on VCC _DF 1.70 1.80 1.98 V —

Vccdf_2 Voltage app lied on VCC _DF 2.70 3.00 3.30 V —

Vccdf_3 Voltage app lied on VCC _DF 2.97 3.30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_CI Voltage

Vccci_0 Voltage applied on VC C_CI in S3/D4/C 4 — 0 — V —

Vccci_1 Voltage applied on VC C_CI 1.70 1.80 1.98 V —

Vccci_2 Voltage applied on VC C_CI 2.70 3.00 3.30 V —

Vccci_3 Voltage applied on VC C_CI 2.97 3.30 3.63 V —

Tsysr am p Ramp Ra te 2.00 10.00 12.00 mV/μs6

VCC_TSI Voltage (PXA32x Only)

Table 14: Voltage, Temperature, and Frequency Electrical Specifications (Continued)

Symbol Description Min Typical Max Units

Notes

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 134 April 6, 2009 Released

Vcctsi_0 Voltage applied on VCC_TSI in S3/D4/C4 —0—V—

Vcctsi_1 Voltage applied on VCC_TSI 2.97 3.30 3.63 V —

Tsysramp Ramp Rate —10.00 12.00 mV/μs —

NOTE:

1. System desi gn must ensur e t hat the device case te mperature i s m aint aine d withi n t he spec i fie d l i m i ts. In some

system applicat ions it may be necessar y t o us e ext er n a l the rm al manag ement (fo r ex am ple, a packag e-m ounte d

heat spreader) or configur e the device to limit pow er cons um pt ion and ma in tain acceptable ca se t em peratur es.

2. The voltage ranges specified for VCC_APPS and VCC_SRAM are the targeted voltage ranges for the product. These

ranges m ay extend or n ar ro w depending on actua l product performan ce and produc t sk ew s . Marvell rec om m ends

that exten ded voltage and current capabilities be designed into the pow er managemen t IC to a ccommodate futu re

changes to this sp ecif i cat i on without req ui ring changes to the po w er managem ent IC.

3. VCC_MV T re quir es t he cap ab ili ty t o inc reas e fro m th e nor mal op erat ing volt ag e of 1 .8 V t o 1. 9 V duri ng ce rt ain time s.

This increased voltage is required under certain conditions, not during normal operation. When VCC_MVT is raised

to 1.9 V, it is opera tin g in “bo os t mode”. Boost mode is onl y u sed during f actory progr am m i ng. I f VC C _PLL,

VCC_O SC 13M and VC C_BG are sup pl ie d by the sam e PMIC s upply, which is the m et ho d Marvell rec om m ends,

these other voltages also operate at 1.9 V. Maximum current capabilities and voltage tolerances are identical in boost

mode and normal ope ra tion.

4. This option allows one or more 128 Kbyte SRAM banks to retain state during S2/D3/C4 mode.

5. Reset voltage for VCC_APPS and VCC_SRAM is 1.4 V and the startup frequency is 104/104/104/104 MHz.

6. Min ramp ra te = (Maximum vol tag e transition) / (LPM _D EL - ((Power I2 C comm and execution time))

7. PXA32x Only

Table 14: Voltage, Temperature, and Frequency Electrical Specifications (Continued)

Symbol Description Min Typical Max Units

Notes

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6Electrical Specifications

This chapter i n cludes DC voltage and current chara cteristics as well as crystal and oscillator

specifications for the PXA3xx Processor Family.

6.1 DC Voltage and Current Characteristics

The DC characteristics for each pin include input-sense levels, output-drive levels, current and

pullup/down resistive values. These parameters can be used to determine maximum DC loading

and to determine maximum transition times for a given load.

Table 15 shows the DC operati ng condition s for the input , output, and I/ O pins use d by the EMP I bus

controlled by the DMEMC. Table 16 applies to all signals powe red by VCC_hi gh. VCC_high is not a

physical supply on the PXA3xx processors, but the term used to refer to the collective groups of high

voltage s upplies which consist of VCC_IO1, VCC_IO3, VCC_IO4 (PXA32x Only), VCC_IO6

(PXA32x Only), VCC_DF, VCC_CI, VCC_CARD1, VCC_CARD2, VCC_LCD, VCC_USB (PXA32x

and PXA30x Only), VCC_BIAS (PXA31x Only), VCC_ULPI (PXA31x Only) and VCC_MSL.

Table 15: DDR Input, Output, and I/O Pins AC/DC Operating Conditions

Symbols Description Min Typical Max Unit Notes

Input DC Operating Conditions (SSTL receiver)1

Vih(dc) Input high voltage 0.7 *

VCC_MEM — VCC_MEM +

0.3 V2

Vil(dc) Input low voltage -0.3 — 0.3 *

VCC_MEM V2

Vih(ac) Input high voltage 0.8 *

VCC_MEM — VCC_MEM +

0.3 V—

Vil(ac) Input low voltage -0.3 — 0.2 *

VCC_MEM V—

RPULLUP Pullup Resistance 653100 1604KΩ5, 6

RPULLDOWN Pulldow n R esistance 553100 1754KΩ5, 6

Output DC Operating Conditions (VCC_MEM = 1.8 V)

VOH High-level output voltage

Absolute Load Current

achiev ing Voh

0.9 *

VCC_MEM — VCC_MEM V IOH =

(min)

-6.5 mA

VOL Low-le vel output voltage

Absolute Load Current

achiev ing Vol

VSS — 0.1 *

VCC_MEM VI

OL =

(min)

6.5 mA

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 136 April 6, 2009 Released

NOTE:

1. Use values w hen SSTL (differentia l) recei v er is enabled. S ee EM PI[SSTL_DMEM_EN] and EMPI [SST_SMEM_EN]

register definitions in the PXA3xx P ro ces sor Family Vol. II: Memory Cont r ol le r Co nf ig ur at ion D eveloper s M anual.

2. The Schmidt trigger must be disabled for SSTL mode. EMPI[SCHM_DMEM_EN] must be cleared. Register definitions

are found in t he PXA3xx Pr ocessor F am il y Vol. II: Memory Controller Configuration Developers Manual.

3. Max vo ltage, M in imum tem per at ur e

4. Min voltage, Maximum temperature

5. Enabl ed during re set , S2/ D 3/C 4 power state, and S3/D4/C 4 power m ode. Not enabled thr ough software c ont r ol .

6. Enabled and disabled using EMPI[PW_DQN] and EMPI[PD_DQS]. See EMPI[PW_DQN] and EMPI[PD_DQS] register

defini tions in the PXA3xx Processor Family Vol. II: Memory Controller Configuration Developers Manual.

Table 16: MFP Input, Output, and I/O Pins DC Operating Conditions

Symbols Description Min Typical Max Unit Notes

Input DC Operating Conditions (vcc = 1.8 V Typical)

Vih In put high voltage VCC_high *

0.8 — VCC_high +

0.3 V3

Vil Input low voltage -0.3 — VCC _hi gh *

0.2 V3

Vhys Hysteresis (VIT+ - VIT-) 0.4 — V C C_high *

0.5 V3

RPULLUP Pullup Resi stan ce 401 110 2002 KΩ4

RPULLDOWN Pulldown Res is tance 401110 2002 KΩ5

Input DC Operating Conditions (vcc = 3.0 and 3.3 V Typical)

Vih In put hi gh vol tage 0.8 *

VCC_high — VCC_high +

0.3 V3

Vil Input low voltage -0.3 — VCC _hi gh *

0.2 V3

Vhys Hysteresis (VIT+ - VIT-) 0.4 — V C C_high *

0.5 V3

RPULLUP Pullup Resi stan ce 20145 1002KΩ4

RPULLDOWN Pulldown Res is tance 20145 1002KΩ5

Table 15: DDR Input, Output, and I/O Pins AC/DC Operating Conditions (Continued)

Symbols Description Min Typical Max Unit Notes

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Output DC Operating Conditions (VCC = 1.8 V Typical)

VOH6

10X

12X

High-level output vol tag e

Absolute Lo ad C urrent

achieving Voh

0.9 *

VCC_high — VCC_high V IOH = (mA min)

-0.4

-0.8

-1.2

-1.6

-2.4

-3.2

-4.0

-4.8

VOL6

10X

12X

Low-level output voltage

Absolute Lo ad C urrent

achieving Vol

VSS — 0.1 *

VCC_high VI

OL = (mA min)

0.5

1.0

1.5

2.0

3.0

4.0

5.0

6.0

Output DC Operating Conditions (vccp = 3.0 and 3.3 V Typical)

VOH6

10X

12X

High-level output vol tag e

Absolute Lo ad C urrent

achieving Voh

VCC_high *

0.9 — VCC_high V IOH = (mA min)

-1.5

-3.0

-4.5

-6.0

-9.0

-12.0

-15.0

-18.0

VOL6

10X

12X

Low-level output voltage

Absolute Lo ad C urrent

achieving Vol VSS — 0. 1 *

VCC_high VI

OL =

(mA min)

1.25

2.5

3.75

7.5

12.5

Output DC Operating Conditions (VCC = 1.8, 3.0 and 3.3 V Typical)

IOZ Thr ee-state outp ut lea kage

current ——40 nA—

IDDQ Quiescent supply cur re nt — — 1 nA —

Table 16: MFP Input, Output, and I/O Pins DC Operating Conditions (Continued)

Symbols Description Min Typical Max Unit Notes

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 138 April 6, 2009 Released

6.2 Oscillator Electrical Specifications

The PXA3xx processors contains two oscillators: a 32.768 kHz oscillator and a 13.000 MHz

oscillator. Each oscillator requires a specific crystal.

6.2.1 32.768 kHz Oscillator Specifications

The 32.768 kHz crystal is connected between the TXTAL_IN (amplifier input) and TXTAL_O UT

(amp lified output). Table 17 lists example 32.768 kHz crystal specifications.

To drive the 32.768 kHz crystal pins from an external source:

1. Drive the TXTAL_IN pin with a digital signal that has low and high levels as listed in Table 17.

2. Ground the TXTAL_OUT pin.

Table 18 lists examp le 32. 768 kHz o scillato r specifi cations.

NOTE:

1. Max voltage, Minimum tempera tu re

2. Min voltage, Maximu m tem peratur e

3. VCC_high references to VCC_IO1, VCC_IO3, VCC_IO4, VCC_IO6, VCC_DF, VCC_CI, VCC_CARD1, VCC_CARD2,

VCC_LCD, VCC_USB supplies.

4. Use MFPRxx[pull_sel] and MF PR xx[pullup_en] bits to ena ble or di sable pullups.

5. Use MFP R xx[pull_s el] an d M FP R xx[pulld own_en] bits to enable or disable pul ldow ns.

6. Multi-Function Pin (M FP) drive strength is progr ammabl e using MFPRxx[dri ve ] bitfield . MFPR regis t er d efin itions are

found in the PXA3xx Pro cessor Fam i ly Vol. I: System and Timer Configurat ion D ev el opers Man ual .

Table 16: MFP Input, Output, and I/O Pins DC Operating Conditions (Continued)

Symbols Description Min Typical Max Unit Notes

Table 17: Typical 32.768 kHz Crystal Requirements 1

Parameter Minimum Typical Maximum Units

Frequency range — 32.768 — kHz

Frequency tolerance –30 — +30 ppm

Frequen cy stability, parab ol ic coefficient — — –0.04 pp m /(Δ°C)2

Drive level — — 1.0 uW

Load capaci tanc e (CL) — 12.5 — pf

Series resistance (RS) — 18 85 kΩ

NOTE:

1. A capacitor is requir ed from TXTAL_IN to gro un d and from TXTAL_OU T to gro und. The capaci tors mu st be 22.0 pF,

5%, +/-3 0ppm/C tem p erature co efficient.

Table 18: Typical External 32.768 kHz Oscillator Requirements

Symbol Description Min Typical Max Units

Amplifier Specifications

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April 6, 2009 Released Page 139

6.2.2 13.000 MHz Oscillator Specifications

The 1 3 .000 MH z crystal is connected between the PXTAL_IN (amplifier input) and PXTAL_OUT

(amp lified output). Table 19 lists the 13.000 MHz cry stal specific ations.

To drive the 13.000 MHz crystal pins from an external source:

1. Drive the PXTAL_IN pin with a digital s ignal with low and high levels as listed in Table 20.

2. Float the P XTAL_OU T pin

Table 20 lists the 13.000 MHz oscillator specifications.

VIH_X Input high voltage, TXTAL_IN 0.8 — 1.0 V

VIL_X Input low voltage, TXTAL_IN –0.10 0.00 0.10 V

IIN_XT Inpu t leak age, TXTAL_IN — — 10 μA

CIN_XT Input capacitance , TXTAL_IN/TXTAL_OUT — 18 25 pf

tS_XT Stabilization time — — 2 s

SR_XT Slew Rate 46 — — mV/μs

Board Specifications

RP_XT Paras itic r esi stance, TXTAL_IN/TX TAL_OUT t o

any node 20 — — MΩ

CP_XT Parasiti c ca paci tance, TX TAL_IN/T XTAL_OUT,

total ——5 pf

COP_X T Par asitic shunt capacitance, TX TAL_IN to

TXTAL_OUT ——0.4 pf

Table 18: Typical External 32.768 kHz Oscillator Requirements (Continued)

Symbol Description Min Typical Max Units

Table 19: Typical 13.000 MHz Crystal Requirements

Parameter Minimum Typical Maximum Units

Frequency ra nge 12.997 13.00 0 13. 002 MHz

Frequency tole ra nce at 25°C –50 — +50 ppm

Oscil lation mode Fundam ental —

Maximum ch ang e over temp er at ur e range – 50 — +50 ppm

Drive level — 10 100 uW

Load capaci tan ce ( C L)—10—pf

Ser ie s resistance (RS)—50—Ω

NOTE: No ext er nal capacitor s ar e needed on the PXTAL_IN or PXTAL_O UT pins for use w ith a 1 3. 000 MHz cr ys tal. The

devic e pr ovi des an effectiv e in ternal load c apacitanc e of 10. 0pF which is the lo ad capacitance defi ned for the

frequ enc y t ol er ance specification.

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 140 April 6, 2009 Released

6.2.3 Clock Outputs

6.2.3.1 CLK_POUT - 13 MHz Clock Output

CLK _ POUT can be used to drive a buffered version of the PXTAL_IN oscillator input. Refer to

Table 21 for CLK_POUT specifications.

6.2.3.2 CLK_TOUT - 32.768 kHz Clock Output

A buf fere d and inver ted ve rsion of the TX TAL_IN oscill ator ou tput is driv en out on CLK _T OU T. Refe r

to Table 22 for CLK_TOUT specifications.

Table 20: Typical External 13.000 MHz Oscillator Requirements

Symbol Description Min Typical Max Units

Amplifier Specifications

VIH _X In put high voltag e, PX TAL_IN 1.7 1 .8 1. 9 V

VIL_X Input low voltage, PXTAL_IN –0.10 0.00 0.10 V

IIN_X P Input leakage, P XTAL_IN — — 10 μA

CIN_XP In put capacitance, PX TAL_IN/PXTAL_OUT — 20 25 pf

tS_XP Stabilization time — — 7 ms

SR_XP Slew Rate 1 — — V/ns

Board Specifications

RP_XP Par as i tic r esistance, PXTAL_IN/PX TAL_OUT t o an y node 20 — — MΩ

CP_XP Parasitic capacitanc e, PXTAL_IN/P XTAL_OUT, total — — 5 pf

COP_XP Parasitic shunt capacitance, P XTAL_IN to PX TAL_OUT — — 0.4 pf

Note CLK_POUT is available only when sof tware sets the OSCC[PEN] bit.

Table 21: CLK_POUT Specifications

Parameter Specifications

Frequency 13 MHz

Frequen cy Accurac y ( der i ved from 13 MHz crystal) +/-200 ppm

Symme t ry /Du ty C ycl e var ia tion 30/70 to 70/30% at V CC

Jitter +/- 20pS max

Load capa citanc e (CL)50 pf max

Rise and Fa ll time (Tr & Tf) 15 nS max with 50 pF lo ad

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April 6, 2009 Released Page 141

Do not route CLK_T OUT close to the 32 kHz crys tal or the 32 kHz crystal signals TXTAL_IN and

TXTAL_OUT. Incorrect la yout can cause the 32 kHz crystal to not lock, or to lock at an incorrect

frequency.

Note

CLK_TOUT is enabled by defa ult. CLK_TO UT can be disabled by w riting to the

OSCC[TENSx] bits.

Table 22: CLK_TOUT Specifications

Parameter Specifications

Frequency 32.768 kHz

Frequency Accu rac y ( der i ved from 32 kHz cr ystal) +/-200 ppm

Sym met ry/Duty Cycle variat i on 3 0/70 to 70/30% at VCC

Jitter +/-2 0 pS m ax

Load capa citanc e (CL) 50 pf max

Rise and Fa ll time (Tr & Tf) 15 nS max wi th 50 pF load

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 142 April 6, 2009 Released

Versi on -

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7AC Characteristics

This chapter includes AC characteristics, timing diagrams and timing parameters for the PXA3xx

Processor Family controllers/interfaces listed below. All memory devices connect to either the

External-Memory Pin Interface (EMPI) or the Data-Flash Interface (DFI).

EMPI:DDR SDRAM Timing Diagrams and Specifications

DFI: Variable Latency I/O (VLIO) Timing Diagrams and Specifications

DFI: Flash Memory Timing D iagrams and Specificatio ns

DFI: SRAM Timing Diagrams and Specifications

DFI: Compact Flash Timing Diagram s and Specifications

DFI: NAND Timing Diagrams and Specifications

Quick Capture Camera Interface Timing Diagrams and Specifications

LCD Timing Diagrams and Specifications

SSP Timing Diagrams and Specifications

AC ’97 Timing Dia grams and Specifications

USB 2.0 Timing Diagrams and Specifications (PXA32x and PXA30x only)

MultiMedia Card Timing D iagrams and Specifications

Secure Digital (SD/SDIO) Timing Diagrams and Specifications

JTAG Boundary Scan Timing Diagrams and Specifications

A pin’s alternating-current (AC) characteristics include input and output capacitance. These factors

determine the loading for external drivers and other load analyses. The AC characteri stics a lso

include a derating factor, which in dicates how much the AC timings might vary with different loads.

Table 23 shows the AC operating conditio ns for the high- and low-strength input, outp ut, and I/O

pins. A ll AC sp ecification values are valid for the device’s entire temperature range.

7.1 External Memory Pin Interface (EMPI) Memory

Timings

This section describes the timing diagrams and timing parameters for the Dynamic Memory

Controller (DMEMC) on the Extern al Memory Pin Interface (EMPI). The following diagram s are

included in t h is section:

Figure 52, DDR SDRAM Timing Diagrams

Figure 53, MD<31:0> to DQS Write Skew

Figure 54, C LK to Ad dress/Command Write Skew

Table 23: Standard Input, Output, and I/O-Pin AC Operating Conditions

Symbol Description Min Typical Max Units

CIN Input capaci tan ce, all stand ar d in put and I/O pins — — 10 pf

COUT_H Output capacitance, all stand ar d hi gh-stren gt h ou tp ut

and I/O pins 20 — 50 pf

COUT_L Output capac itance, all standard lo w - st re ngt h output

and I/O pins 20 — 50 pf

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 144 April 6, 2009, Released

Figure 55, DQS to CLK Write Skew

Figure 56, MD<31:0> to DQS Read Skew

7.1.1 DDR SDRAM Timing Diagrams and Specifications

Figure 52 Shows the D DR SD RA M tim ings that are p rogra mm ab le throu gh th e M D CNF G[ DTC [1:0 ]]

Figure 53 Show s the DQ to DQS skew during write cycles.

Figure 54 Shows the CLK to Address/Command skew during write cycles.

Figure 52: DDR SDRAM Timing Diagrams

NOP ACT NOP READ NOP PRE NOP ACT NOP WRITE NOP PRE NOP

1111 mask0 mask1 mask6 mask7

tCL tWR

tRCD

tRP

tRC tRCD

tRPtRAS

tRCD

tRC

tRAS

tRCD

SDCLK[1]

SDCKE

Command

nSDCS[0]

nSDRAS

nSDCAS

nWE

DQS

MD<31:0>

DQM[1:0]

Figure 53: MD<31:0> to DQS Write Skew

tDQTVA

tDQTVBtDQTVB

DQS

MD<31:0>

Figure 54: CLK to Address/Command Write Skew

tATVA tATVBtATVB

CLOCK

ADD/CMD

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April 6, 2009, Released Page 145

Figure 55 Show s the DQS to CLK skew during wr ite cycles.

Figure 56 Shows the DQ to DQS allowa ble skew during read cycles.

Figure 55: DQS to CLK Write Skew

tDQSTVBtDQSTVA

CLOCK

DQS

Figure 56: MD<31:0> to DQS Read Skew

Table 24: DDR Timing S pecifications

Symbol Description Min Typical Max Units Notes

tRC nSDRAS cycle time 5 MDCNFG[DTCx] 10 SDCLK 1

tRP nSDRAS Precharge 2 MDCNFG[DTCx] 4 SDCLK 1

tCL nSDRAS to first data valid delay 2 MDCNF G[DTCx ] 3 SDCLK 1

tRAS nSDRAS active time (min) 3 MDCNFG[DTCx] 6 SDCLK 1

tRCD nSDRAS assert to nSDCAS assert delay 2 MDCNFG[DTCx] 4 SDCLK 1

tWR Write recovery time 2 SDCLK 2

tDQTVB DQ Valid time before DQS 1.38 — — n s

tDQTVA DQ Valid time after DQS 1.16 — — ns

tATVB CMD/CTL Valid time before CLK 3.2 — — ns

tATVA CMD/CTL Valid time after CLK 3 .0 — — ns

tDQSTVB DQS Fallin g edg e before CL K 3.14 — — n s

tDQSTVA DQS Falling edge after CLK 2.98 — — n s

tDQDQS Ske w betwe en DQ and D Q S permitted

at the input. -1.2 — 1.2 ns

NOTE:

1. SDCLK frequency is one half of the DDR controller frequency. The DDR controller frequency is configured using

ACCR[DMCFS] bits.

2. The write recovery time is hardcoded to two SDCLKs.

3. Refer to the P XA3x x Pr ocessor Fam il y Vol. II: Memory Controller C onfiguration D eve l opers Manual for more

information on the MDC NFG regi st er.

tDQDQStDQDQS

DQS

MD<31:0>

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 146 April 6, 2009, Released

7.2 Data-Flash Interface (DFI) Memory Timing

Specifications

This se ction d escribes the tim ing dia grams and tim ing p aram eters fo r all su pported memor y devi ces

on the Data-Flash Interface (DFI). The following diagrams are included in this section:

Figure 57, VLIO Read Timing Diagram

Figure 58, VLIO Read Timing Diagram (Latched Addressing Mode)

Figure 59, V LIO Low Order Addressing Read Timing Diagram

Figure 60, V LIO Low Order Addressing Read Timing Diagram (Latche d Addressi ng Mode)

Figure 61, VLIO Write Timi ng Diagram

Figure 62, VLIO Write Timing Diagram (Latched Addressing Mode)

Figure 63, VLIO Low Order Addressing Write Timing D iagram

Figure 64, V LIO Low Order Addressing Write Timing Diagram (Latched Addressing Mode)

Figure 65, Flash Asynchronous Read Timing Diagram

Figure 66, Flash Asynchronous Read Timing Diagram (Latched Addressing Mode)

Figure 67, Flash Asynchronous Low-Order Read Timing Diagram

Figure 68, Flash Asynchronous Low-Order Read Timing Diagram (Latched Addressing Mode)

Figure 69, Fl ash Synchronous Read Timing Diagram

Figure 70, Flash Synchronous R ead Timing Diagram (Latched Address ing Mode)

Figure 71, Flash Asynchronous Write Timing Diagram s

Figure 72, Flash Asynchronous Write Timing Diagram s (Latched Addressing Mode)

Figure 73, Flash Asynchronous Low-Order Addressing W rite Timing Diagrams

Figure 74, Flash Asynchronous Low-Order Addressing W rite Cycle Timing Diagram

Figure 75, S ynchronous Write Timings Diagrams

Figure 76, S ynchronous Write Timings Diagrams (Latched Addressing Mode)

Figure 77, SRAM Asynchronous Read Timing D iagram.

Figure 78, S RAM Asynchronous Read Timing D iagram (Latched Addressing Mode)

Figure 79, S RAM Asynchronous Low-Order Addressing Read Timing Diagram

Figure 80, SRAM Asynchronous Read Timing Diagram (Non-AA/D Addressing Mode)

Figure 81, SRAM Asynchronous Write Timing Diagram

Figure 82, SRAM Asynchronous Write Timing Diagram (Latched Addressing Mode)

Figure 83, SRAM Asynchronous Low-Order Add r essing Write Timing Diagram

Figure 84, S RAM Asynchronous Low-Order Addressing Write Timing Diagram (Latched

Addressing Mode)

Figure 85, Compact Flash 16-Bit Common Memory Read Timing Diagram

Figure 86, Compact Flash 16-Bit Common Memory Write Timing Diagram.

Figure 87, Compact Flash 16-Bit I/O Memo ry Read Timing Diagram

Figure 88, Compact Flash 8-Bit I/O Space Write Timing Diagram.

Figure 89, NAND Flas h Program Timing Diagram

Figure 90, NAND Flash Erase Timing Diagram

Figure 91, NAND Flash Small Block Read Timing Diagram

Figure 92, NAND Flash Large Block Read Timing Diagram

Figure 93, N AND Flas h Status Read Timing Diagram

Figure 94, N AND Flas h ID Read Timing Diagram

Figure 95, N AND Flas h Reset Timing Diagram

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April 6, 2009, Released Page 147

7.2.1 Variable Latency I/O (VLIO) Timing Diagrams and

Specifications

The va riable-la tency I/O (VL IO) interface al lows the use of a data-re ady input s ignal, RDY, to ins ert a

variabl e number of memory-cycle wait states. The data-bus width for VLIO on the DFI for each

chip-select region supports 16-bit memory devices. DF_nOE is asserted for all reads; DF_nWE is

asserted for all writes.

In ad dition, VLIO read accesses differ from SRAM read accesses in that the DF_nOE toggles for

each beat of a burst.

The memory controller waits indefinitely for the RDY signal to be asserted. This wait period hangs

the system if the external VLIO is not responding. To prev ent indefin ite system hangs, set the

watchdog tim e r when starting a VLIO transfer, and reset the system if no res ponse is received from

the VLIO.

For Reads, nBE<1:0> are asserted to 0b00. During W r ites, data pins are actively driv en by the

processor (tha t is, they are not thre e-stated), regardless of the state of the individual nBE pins. For

these Writes, the nBE pins are used as Byte Enables.

7.2.1.1 VLIO Read Timing

Figure 57 illustra tes a full La tch-ad dressing mo de Read cycle for a VLIO d evice. Figure 58 illustrates

a full Latch-addressing m ode Read cycle for a VLIO device using the L atched-ad dressing mode

(PXA31x and PXA3 0x only). Refer to Table 25 for det ailed timing p arame ters. O nly one Byte En able

(nBE[1:0]) is ass e rted on a single byte Read.

Figure 57: VLIO Read Timing Diagram

U Add L Add rd0 LAdd+2 rd1

"00"

tRDS

tOEL tRDH

tAOH

tOCS

tOEL

tAOS

tRDH

tAOH

tAOS

tAADVH

tADVL

tAADVS

tADVL

tAADVH

tADVLtADVL

tAADVS

tAADVH

tADVLtADVL

tAADVS

tMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTO

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

nBE[1:0]

RDnWR

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 148 April 6, 2009, Released

7.2.1.2 VLIO Low-Order Addressing Read Timing

Figure 59 illustra tes a Low-order Addressing mode Read cycle for a VLIO device. Figure 60

illustrates a Low-order Addressing mode R ead cycle for a VLIO devic e using the Latched-

addressing mode (PXA31x and PXA30x only). Refer to Table 25 fo r detailed timing para meters.

Only one Byte Enable (nBE[1:0]) is asserted on a single byte Read.

Figure 58: VLIO Read Timing Diagram (Latched Addressing Mode)

U Add L Add rd0 LAdd+2 rd1

"00"

tRDS

tOEL tRDH

tAOH

tOCS

tOEL

tAOS

tRDH

tAOH

tAOS

tAADVH

tADVL

tAADVS

tADVL

tAADVH

tADVLtADVL

tAADVS

tAADVH

tADVLtADVL

tAADVS

tMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTO

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

nBE[1:0]

RDnWR

Figure 59: VLIO Low Order Addressing Read Timing Diagram

U Add L Add rd0 rd1

"00"

tRDStRDS tOCS

tRDH

tAOH

tOEL (2 w a its)

tAOS

tOEL (2 w a its)

tAOH

tRDH

tAOS

tADVL tAADVHtAADVS tADVL

tMBTOtMBTOtMBTOtMBTO

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

RDnWR

nBE[1:0]

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April 6, 2009, Released Page 149

7.2.1.3 VLIO Write Timing

Figure 61 illustrate s a full Latch-a ddressin g mode W rite cy cle for a VLIO device. Figure 62 illustrate s

a full Latch-addressing mode Write cy cle for a VLIO device using the Latched-addressing mode

(PXA31x and PXA30x only). Refer to Table 25 for detailed timing parameters.

Figure 60: VLIO Low Order Addressing Read Timing Diagram (Latched Addressing Mode)

U Add L Add rd0 rd1

"00"

tRDStRDS tOCS

tRDH

tAOH

tOEL (2 wa its)

tAOS

tOEL (2 wa its)

tAOH

tRDH

tAOS

tADVL tAADVHtAADVS tADVL

tMBTOtMBTOtMBTOtMBTO

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

RDnWR

nBE[1:0]

Figure 61: VLIO Write Timing Diagram

U Add L Add wd0 LAdd+2 wd1

"00" m0 "00" m1

tXEWS

tWEL (2 waits) tWCS

tDWH

tWEL (2 waits)

tDWStDWH

tWEL (0 waits)

tDWS

tWEL (0 waits)

tADVL tAADVH

tAADVS

tADVL

tAADVH

tADVL

tAADVS

tADVL

tADVL tAADVH

tADVL

tAADVS

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

RDnWR

nBE[1:0]

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 150 April 6, 2009, Released

7.2.1.4 VLIO Low Order Addressing Write Timing

Figure 63 illustrates a Low -order A ddressing mode Write cycle for a VLIO device. Figure 64

illustra tes a Low -order Add ressi ng mode Writ e cycl e for a VLIO us ing the La tched-a ddress ing mo de

(PXA31x and PXA30x only). Refer to Table 25 for detailed timing parameters.

Figure 62: VLIO Write Timing Diagram (Latched Addressing Mode)

U Add L Add wd0 LAdd+2 wd1

"00" m0 "00" m1

tXEWS

tWEL (2 waits) tWCS

tDWH

tWEL (2 waits)

tDWStDWH

tWEL (0 waits )

tDWS

tWEL (0 waits )

tADVL tAADVH

tAADVS

tADVL

tAADVH

tADVL

tAADVS

tADVL

tADVL tAADVH

tADVL

tAADVS

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

RDnWR

nBE[1:0]

Figure 63: VLIO Low Order Addressing Write Timing Diagram

U Add L Add wd0 wd1

"00" m0 m1

tXEWS

tWEL (2 waits) tWCS

tDWH

tAWH

tAWS

tDWS tWEL (2 waits)tWEL (0 waits)

tAWH

tDWH

tWEL (0 waits)

tDWS

tAADVH

tADVLtADVL

tAADVS

tAADVH

tADVLtADVL

tAADVS

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

RDnWR

nBE[1:0]

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April 6, 2009, Released Page 151

Figure 64: VLIO Low Order Addressing Write Timing Diagram (Latched Addressi ng Mode)

Table 25: VLIO Timing Specifications

Symbol

Description Min2Min3Min4Typical Max Units

Notes

tAADVS Address setup to nLLA/nLUA

asserted 011CSADRCFGx[ALT] 1 DF_SCLK 1

tAADVH Address hold from

nLLA/nL UA deasser ted 011CSADRCFGx[ALT] 1 DF_SCLK 1

ttADVL nLLA/nLUA assert time 112CSADRCFGx[ALW] 7 DF_SCLK 1

tXEWS nXCVREN s etup to DF_nWE

asserted 111MCS0/1[RDN] 15 DF_SCLK 1

tDWS By te Enables and Write Data

setup to D F _n WE asserted ———1—DF_SCLK 1

tDWH Write Data, Byte Enables and

nXCVREN hold from

DF_ nWE de-asserted

111MCS0/1[RDN] 15 DF_SCLK 1

tAOH Address hold from DF_nOE

de-asserted 111MCS0/1[RDN] 15 DF_SCLK 1

tWCS DF_nW E d e-asserte d to n C S

de-asserted 111MCS0/1[RDN] 15 DF_SCLK 1

tOCS DF_nOE d e-a ss er te d to nC S

de-asserted 111MCS0/1[RDN] 15 DF_SCLK 1

U Add L Add wd0 wd1

"00" m0 m1

tXEWS

tWEL (2 waits) tWCS

tDWH

tAWH

tAWS

tDWS tWEL (2 waits)tWEL (0 waits)

tAWH

tDWH

tWEL (0 waits)

tDWS

tAADVH

tADVLtADVL

tAADVS

tAADVH

tADVLtADVL

tAADVS

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

RDY

nXCVREN

RDnWR

nBE[1:0]

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 152 April 6, 2009, Released

7.2.2 Flash Memory Timing Diagrams and Specifications

The DFI bus uses the Static Memory Controller (SMEMC) to interface to 16-bit AA/D muxed Flash

memory. Figure 65 through Figure 76 show the timing diagrams for asynchronous Reads,

synchronous Reads, asynchronous Writes, and synchronous Writes.

An asynchronous Fla sh Read timing is shown in Figure 65. Fo r Reads, nBE<1:0> are asserted to

0b00 . During Flash Writes, nBE<1:0> are ass erted to 0b00. Flash accesses are always 16-bit, so

they are not used.

7.2.2.1 Flash Asynchronous Read Timing

Figure 65 illustra tes a full Latch-addressing mode asynchronou s Read cycle for a flash device.

Figure 66 illustrate s a full La tch-addres sing mode as ynchr onous Read cyc le for a flash de vice using

the latched addressing mode (PXA31x and PXA30x only). Refer to Table 26 for detailed timing

parameters.

tWEL DF_nWE assert time 3 4 7 MCS0/1[ RD F]+ 1 +

Waits516 DF_SCLK 1

tOEL DF_nOE assert time 3 4 7 MCS0/1[RD F]+ 1 +

Waits516 DF_SCLK 1

tAWS Address setup to DF_nWE

assert 111MCS0/1[RDN] 15 DF_SCLK 1

tAWH Address hold from DF_nWE

de-assert 111MCS0/1[RDN] 15 DF_SCLK 1

tAOS Address setup to DF_nOE

assert 111MCS0/1[RDN] 15 DF_SCLK 1

tAOH Address hold from DF_nOE

de-assert 111MCS0/1[RDN] 15 DF_SCLK 1

tRDH Read data hold from sample———0 —ns 1

tRDS Read data setup time 30 30 30 — — ns 1

tMBTOMinimum Bus Turnover time———1 —DF_SCLK1

NOTE:

1. DF_SCLK frequen cy depends on t he ACCR[SM C FS] and MEMC LKCFG[D F_CLKD IV ] programm ed value.

2. DF_SCLK = 52MHz

3. DF_S C LK = 104MH z

4. DF_S C LK = 208MH z

5. Waits are cycl es in ser t ed w hile the RD Y si gnal is low.

6. Re fer to th e PXA3xx Processor Family Vol. II: Memory Controller Configuration Develop er s Man ual for more

informat ion on the CSADRCFGx an d M C S0/1 register s.

Table 25: VLIO Timing Specifications (Continued)

Symbol

Description Min2Min3Min4Typical Max Units

Notes

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April 6, 2009, Released Page 153

7.2.2.2 Flash Asynchronous Low-Order Read Timing

Figure 67 illustra tes a Low-order Addressing mode asynchrono us Read cycle for a flash device.

Figure 68 illustra tes a Low-order Addressing mode asynchrono us Read cycle for a flash device

using the Latched-addressing mode (PXA31x and PXA30x only). Refer to Table 26 for detailed

timing p ara meters .

Figure 65: Flash Asynchronous Read Timing Diagram

Figure 66: Flash Asynchronous Read Timing Diagram (Latched Addressing Mode)

0 1

U Add L Add rd0 LAdd+2 rd1

"00"

tOELtOEL

tRDH

tOEL

tRDL

tOEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVH

tAADVS

tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTO

nCS[x]

F_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RD_nWR

nBE[1:0]

U Add L Add rd0 LAdd+2 rd1

"00"

tOELtOEL

tRDH

tOEL

tRDL

tOEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVH

tAADVS

tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTO

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RD_nWR

nBE[1:0]

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 154 April 6, 2009, Released

7.2.2.3 Flash Synchronous Read Timing

Figure 69 illustrates Continuous-word Burst mode Flash-Read cycles. Figure 70 illustrates

Continuous-word Burst mode Flash-Read cycles using the Latched-addressing mode (PXA31x and

PXA30x only). Refer to Table 26 for detailed timing parameters.

Figure 67: Flash Asynchronous Low-Order Read Timing Diagram

Figure 68: Flash Asynchronous Low-Order Read Timing Diagram (Latched Addressing Mode)

0 1

U Add L Add rd0 rd1

"00"

tOCStRDLtRDL

tADVL tAADVHtAADVS tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTO

tRDH tMBTO

tRDHtMBTOtMBTO

tAOHtAOH

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

0 1

U Add L Add rd0 rd1

"00"

tOCStRDLtRDL

tADVL tAADVHtAADVS tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTO

tRDH tMBTO

tRDHtMBTOtMBTO

tAOHtAOH

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

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April 6, 2009, Released Page 155

7.2.2.4 Flash Asynchronous Write Timing

Figure 71 illustrates full Latch-mode asynchronous Flash-Write cycles. Figure 72 illustrates full

Latch-mode asynchronous Flash-Write cycles using the Latched-addressing mode (PXA31x and

PXA30x only). Refer to Table 26 for detailed t iming parameters.

Figure 69: Flash Synchronous Read Timing Diagram

Figure 70: Flash Synchronous Read Timing Diagram (Latched Addressing Mode)

LAddr[3:0]

U Add L Add d0 d1 d2 d14 d15

"00"

tSDH

tSDA

tOCS

tADVL tAADVHtAADVS tADVL

DF_SCLK

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

LAddr[3:0]

U Add L Add d0 d1 d2 d14 d15

"00"

tSDH

tSDA

tOCS

tADVL tAADVHtAADVS tADVL

DF_SCLK

ADDR[25:16]

ADDR[15:4]

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 156 April 6, 2009, Released

7.2.2.5 Flash Asynchronous Low-Order Addressing Write Timing

Figure 73 illustra tes a Low- order Addressing mode asynchronous Flash-Write cycle. Figure 74

illustrates a Low-order Addressing mode asynchronous Flash-Write cycle u sing the Latched-

addressing mode (PXA31x and PXA30x only). Refer to Table 26 fo r detailed timing parameters.

Figure 71: Flash Asynchronous Write Timing Diagrams

Figure 72: Flash Asynchronous Write Timing Diagrams (Latched Addressing Mode)

0 1

U Add L Add wd0 LAdd+2 wd1

"00"

tWEL

tDWH

tWCS

tWEL

tDWS

tWEL

tDWH

tWEL

tDWS

tADVL tAADVH

tAADVS

tADVL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVH

tAADVS

tADVL

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

U Add L Add wd0 LAdd+2 wd1

"00"

tWEL

tDWH

tWCS

tWEL

tDWS

tWEL

tDWH

tWEL

tDWS

tADVL tAADVHtAADVS tADVL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVHtAADVS tADVL

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

Versi on -

April 6, 2009, Released Page 157

7.2.2.6 Synchronous Write Timings

Figure 75 illustrates sync hronous Flash-Write cycles. Figure 76 illustrates synchronous Flash-Write

cycles using the Latched-addressing mode (PXA31x and PXA30x only). Refer to Table 26 for

detailed timing parameters.

Figure 73: Flash Asynchronous Low-Order Addressing Write Timing Diagrams

0 1

U Add L Add wd0 wd1

"00"

tWEL

tDWH

tWCS

tAWS

tDWS

tWELtWEL tAWH

tDWH

tDWS

tWEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVHtAADVS tADVL

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

Figure 74: Flash Asynchronous Low-Order Addressing Write Cycle Timing Diagram

U Add L Add wd0 wd1

"00"

tWEL

tDWH

tWCS

tAWS

tDWS

tWELtWEL tAWH

tDWH

tDWS

tWEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVHtAADVS tADVL

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 158 April 6, 2009, Released

Figure 75: Synchronous Write Timings Diagrams

Figure 76: Synchronous Write Timings Diagrams (Latched Addressing Mode)

Table 26: DFI Flash Timing Specifications

Symbol Description Min Typical Max Units Notes

tAADVH Address hold from nLLA/nLUA de-asserted 0 CSADRCFGx[ALT] 1DF_SCLK1

tAADVS Address setup to nLLA/nLUA asserted 0 CSADRCFGx[ALT] 1DF_SCLK1

tADVL nLLU/nLLA assert time 1 CSADRCFGx[ALW] 7DF_SCLK1

0 1 2 14 15

U Add L Add wd0 wd1 wd2 wd14 wd15

"00" m0 m1 m2 m14 m15

tSDH

tSDA

tWCS

tADVL tAADVHtAADVS tADVL

DF_SCLK

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

1 2 14 15

U Add L Add wd0 wd1 wd2 wd14 wd15

"00" m0 m1 m2 m14 m15

tSDH

tSDA

tWCS

tADVL tAADVHtAADVS tADVL

DF_SCLK

ADDR[25:16]

ADDR[15:4]

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

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April 6, 2009, Released Page 159

7.2.3 SRAM Timing Diagrams and Specifications

An SRAM Read timing is shown in Figure 77. For Reads, nBE <1 :0> are as serted to 0b00 . Duri ng

Writes, data pins are activ e ly driven by the processor (that is, they are not three-stated), re gardless

of the state of the individual nBE pins. The nBE pins are used as Byte Ena bles for these Writes.

The SRAM accesses shown in Figure 77 and Figure 84 illustrate the Low-orde r Address mode that

uses the DF_ADDR<3:0> bus to change the address without having to go through the

time-consuming address-latching process that uses the nLUA and nLLA signals.

tDWS Data, Byte enables, and XCVREN setup to

DF_nWE asserted —1—DF_SCLK 1

tDWH Dat a, Byte enables, and XCVREN hold from

DF_nWE de-asserted —1—DF_SCLK 1

tWCS DF_nWE de-asserted to nCS

de-asserted —1—DF_SCLK 1

tOCS DF_nOE de-asserted to nCS

de-asserted —6—DF_SCLK 1

tWEL DF_nWE assert time 1 MCS0/1[RDF] +1 16 DF_SCLK 1

tOEL DF_nOE assert time 2 MCS0/1[RDF] + 2 17 DF_SCLK 1

tRDL DF_nOE assertion to read data latch 1 MCS0/1[RDF] + 1 16 DF_SCLK 1

tAOS Address setup to DF_nOE assert —1—DF_SCLK 1

tAWH Address hold from DF_nWE de-assert —1—DF_SCLK 1

tAWS Address setup to DF_nWE assert —1—DF_SCLK 1

tAOH Address hold from data sample —1 — DF_SCLK 1

tRDH Read data hold from sample (Asynchronous

Reads) —1—DF_SCLK 1

tSDH Synchronous Flash R ead Data hold tim e 4 SXCNFG[SXCL2] + 1 11 DF_SCLK 1

tSDA Synchronous Flas h Read Data acces s

time 3SXCNFG[SXCL2] 10 DF_SCLK 1

tSDH Synchronous write data hold time 4 SXCNFG[SXWRCL2]

+ 1 11 DF_SCLK 1

tSDA Synchron ous write da ta acc ess tim e 3 SXCNFG[SXWRCL2] 10 DF_SCLK 1

tMBTO Minimum Bus Turnover time —1—DF_SCLK 1

NOTE:

1. DF_SCLK frequenc y depends on th e AC CR[SMCFS] and MEMCLKCFG[DF_CLKDIV ] pr ogramme d values.

2. The maxim um D F_SCLK frequency for syn chronou s accesses is 52 M H z.

3. Refer to the PXA3xx Proces so r Family Vol. II: Memory Controller Config u ra tio n Devel oper s Manu al for more

information on the CSADRCFGx, SXCNFG and MC S0/ 1 r egi sters.

Table 26: DFI Flash Timing Specifications (Continued)

Symbol Description Min Typical Max Units Notes

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 160 April 6, 2009, Released

7.2.3.1 SRAM Asynchronous Read Timing

Figure 77 illustra tes a full Latch-addressing mode asynchronou s-SRAM Read cycle. Figure 78

illustrates a full Latch-addressing mode asynchronous-SRAM Read cycle using the Latched-

addressing mode (PXA31x and PXA30x only). Refer to Table 27 fo r detailed timing parameters.

7.2.3.2 SRAM Asynchronous Low-Order Addressing Read Timing

Figure 79 illustra tes a Low-order Addressing mode asynchrono us-SRAM Read cycle. Figure 79

illustrates a Low-order Addressing mode as ynchron ous-SRAM Read cycle using the Latched-

addressing mode (PXA31x and PXA30x only). Refer to Table 27 fo r detailed timing parameters.

Figure 77: SRAM Asynchronous Read Timing Diagram.

0 1

U Add L Add rd0 LAdd+2 rd1

"00"

tOELtOEL

tRDH

tOEL

tRDL

tOEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVH

tAADVS

tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTO

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RD_nWR

nBE[1:0]

Figure 78: SRAM Asynchronous Read T iming Diagram (Latched Addressing Mode)

U Add L Add rd0 LAdd+2 rd1

"00"

tOELtOEL

tRDH

tOEL

tRDL

tOEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVH

tAADVS

tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTOtMBTO

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RD_nWR

nBE[1:0]

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April 6, 2009, Released Page 161

7.2.3.3 SRAM Asynchronous Write Timing

Figure 81 illustra tes a full Latch-addressing mode asynchronous-SRAM W r ite cycle. Figure 82

illustrates a full Latch-addressing mode asynchronous-SRAM Write cycle using the Latched-

addressing mode (PXA31x and PXA30x Only). Refer to Table 27 for detaile d timing parameters.

Figure 79: SRAM Asynchronous Low-Order Addressing Read Timing Diagram

0 1

U Add L Add rd0 rd1

"00"

tOCStRDLtRDL

tADVL tAADVHtAADVS tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTO

tRDH tMBTO

tRDHtMBTOtMBTO

tAOHtAOH

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

Figure 80: SRAM Asynchronous Read Timing Diagram (Non-AA/D Addressing Mode)

0 1

U Add L Add rd0 rd1

"00"

tOCStRDLtRDL

tADVL tAADVHtAADVS tADVL

tADVL tAADVH

tAADVS

tADVL

tMBTO

tRDH tMBTO

tRDHtMBTOtMBTO

tAOHtAOH

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 162 April 6, 2009, Released

7.2.3.4 SRAM Asynchronous Low-Order Addressing Write Timing

Figure 83 illustra tes a Low-order Addressing mode asynchronous-SRAM Write cycle. Figure 84

illustrates a Low-order Addressing mode asynchronous-SRA M Write cycle using th e latched

addressing mode (PXA31x and PXA30x Only). Refer to Table 27 for detaile d timing parameters.

Figure 81: SRAM Asynchronous Write Timing Diagram

Figure 82: SRAM Asynchronous W rite Timing Diagram (Latched Addressing Mode)

U Add L A dd wd0 LAdd+2 wd1

"00" m0 00 m1

tWEL

tDWH

tWCS

tWEL

tDWS

tWEL

tDWH

tWEL

tDWS

tADVL tAADVH

tAADVS

tADVL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVH

tAADVS

tADVL

nCS[x]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

U Add L Add wd0 LAdd+2 wd1

"00"

tWEL

tDWH

tWCS

tWEL

tDWS

tWEL

tDWH

tWEL

tDWS

tADVL tAADVHtAADVS tADVL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVHtAADVS tADVL

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

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April 6, 2009, Released Page 163

Figure 83: SRAM Asynchronous Low-Order Addressing Write T iming Diagram

0 1

U Add L Add wd0 wd1

"00" m0 m1

tWEL

tDWH

tWCS

tAWS

tDWS

tWELtWEL tAWH

tDWH

tDWS

tWEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVHtAADVS tADVL

nCS[x]

F_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

Figure 84: SRAM Asynchronous Low-Or der Addressing Write Timing Diagram (Latched

Addressing Mode)

U Add L Add wd0 wd1

"00" m0 m1

tWEL

tDWH

tWCS

tAWS

tDWS

tWELtWEL tAWH

tDWH

tDWS

tWEL

tAADVH

tADVLtADVL

tAADVS

tADVL tAADVHtAADVS tADVL

nCS[x]

ADDR[25:16]

ADDR[15:4]

DF_ADDR[3:0]

DF_IO[15:0]

nLUA

nLLA

DF_nOE

DF_nWE

nXCVREN

RDnWR

nBE[1:0]

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 164 April 6, 2009, Released

Table 27: DFI SRAM Timing Specifications

Symbol

Description Min2Min3Min4Typical Max Units

Notes

tAADVS Address setup to nL LA/ nL U A

asserted 1 1 1 CSADRCFGx[ALT] 1 DF_SCLK 1

tAADVH Addres s hold f rom

nLLA/nL U A deasser ted 1 1 1 CSADRCFGx[ALT] 1 DF_SCLK 1

tADVL nLLA/nLUA assert time 1 1 2 CSADRCFGx[ALW ] 7 DF_SCLK 1

tDWS Data, Byte enables, and

XCVREN setup to DF_nWE

asserted

— — — 1 — DF_SCLK 1

tDWH Data, Byte enables, and

XCVREN hol d f ro m DF_nWE

deasserted

— — — 1 — DF_SCLK 1

tWCS DF_nWE de-as se rted to nCS

de-asserted — — — 1 — DF_SCLK 1

tOCS DF_nOE de-ass erted to nCS

de-asserted — — — 1 — DF_SCLK 1

tWEL DF_nWE assert time 2 2 3 MCS0/1[RDN] + 1 16 DF_SCLK 1

tOEL DF_nOE assert time 3 4 7 MCS0/1[RDF] + 2 17 DF_SCLK 1

tRDL DF_nOE assertion to read data

latch 2 3 6 MCS0 /1 [RDF ] + 1 16 DF_SC LK 1

tAWS Address setup to DF_nWE

assert ———1—DF_SCLK 1

tAWH Address hold from DF_nWE

de-assert ———1—DF_SCLK 1

tAOH Address hold from data sample ———1—DF_SCLK 1

tRDH Read data hold from sample ———1—DF_SCLK 1

tMBTO Minimum Bus Turnover time ———1—DF_SCLK 1

NOTE:

1. DF_SCLK frequency depends on the ACCR[SMCFS] and MEMCLKCFG[DF_CLKDIV] programmed values.

2. DF_SCL K = 52 M Hz

3. DF_SCL K = 104 MHz

4. DF_SCL K = 208 MHz

5. Refer to the PXA3xx Processor Fa m ily Vol. II: Memory Contro lle r Con f ig ur at ion D ev el opers Manu al fo r mor e

informat ion on the CSADRCFGx and M C S0/1 regist er s.

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7.2.4 Compact Flash Timing Diagrams and Specifications

The PXA32x processor card interface provides control for one card, supports 8- and 16-bit

perip herals, and handle s common memory, I/O, and attribute-memory accesses. The duration of

each access is based on programmed values per address space by fields within the MCMEMx,

MCATTx, and MCIOx registers. The proc essors are descri bed in detail in the PXA3xx Processor

Family Vol. II: Memory Controller Configuration Developers Manual.

7.2.4.1 Compact Flas h 16-Bit Common Memory Read Timing.

Table 85 illustrates a read cycle from Compact Flash common memory. Refer to Table 28 for

detailed timing parameters.

Figure 85: Compact Flash 16-Bit Common Memory Read Timing Diagram

UAdd LAdd UAdd rd[15:0] UAdd

tCMD X_ASST_HOLD X_HOLDtCMD

X_ASST_WAIT

X_SET

tADVLtAADVH

tAADVS

tADVL

tAADVH

tADVL

tAADVS

tADVLtADVL tAADVH

tAADVS

tADVLtADVLtAADVH

tAADVS

tADVL

DF_IO[15:0]

nLUA

nLLA

nPCE1

nPCE2

nIOIS16

DF_nWE

DF_nOE

nPWAIT

nXCVREN

RDnWR

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 166 April 6, 2009, Released

7.2.4.2 Compact Flas h 16-Bit Common Memory Write Timing.

Table 86 illustrates a write cycle to Compact Flash common memory. Refer to Table 28 for detailed

timing p ara meters .

7.2.4.3 Compact Flash 16-Bit I/O Space Read Timing

Table 87 illustrates a 16-bit read cycle from Compact Flash I/O space memory. Refer to Table 28 for

detailed timing parameters.

7.2.4.4 Compact Flash 8-Bit I/O Space Write Timing.

Table 88 illustrates a 8-bit write cycle to Compact Flash I/O space memory. Refer to Table 28 for

detailed timing parameters.

Figure 86: Compact Flash 16-Bit Common Memory Write Timing Diagram.

UAdd LAdd UAdd wd[15:0] UAdd

tCXH

tXCS tCMD X_ASST_HOLD X_HOLD

tCMD

X_ASST_WAIT

tADVLtAADVH

tAADVS

tADVL

tADVL tAADVH

tAADVS

tADVLtADVL tAADVH

tAADVS

tADVLtADVLtAADVH

tAADVS

tADVL

DF_IO[15:0]

nLUA

nLLA

nPCE1

nPCE2

nIOIS16

DF_nWE

DF_nOE

nPWAIT

nXCVREN

RDnWR

Figure 87: Compact Flash 16-Bit I/O Memory Read Timing Diagram

UAdd LAdd UAdd rd[15:0] UAdd

tCMD X_ASST_HOLD X_HOLDtCMD

X_ASST_WAIT

X_SET

tADVLtAADVH

tAADVS

tADVL

tADVL tAADVH

tADVL

tAADVS

tADVL tAADVH

tAADVS

tADVLtADVLtAADVH

tAADVS

tADVL

DF_IO[15:0]

nLUA

nLLA

nPCE1

nPCE2

nIOIS16

nPIOW

nPIOR

nPWAIT

nXCVREN

RDnWR

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April 6, 2009, Released Page 167

Figure 88: Compact Flash 8-Bit I/O Space Write Timing Diagram.

Table 28: Compact Flash Timing Specifications

Symbol Description Min Typical Max Units Notes

tAADVS Address setup to nLLA/nLUA

asserted 0CSADRCFGx[ALT] 1DF_SCLK 1

tAADVH Address hold from nLLA/nLUA

de-asserted 0CSADRCFGx[ALT] 1DF_SCLK 1

tADVL nLLA/nLUA assert time 1CSADRCFGx[ALW] 7DF_SCLK 1

tX_HOLD Comm a nd de-ass er t to nPCE

de-assert via nL UA command 1 MCx0[HOLD] 63 DF_SCLK 1

tX_SET Address valid to command assert 1 MCx0[SET] 127 DF_SCLK 1

tX_ASST_

WAIT

Comma nd assert t o w hen nPWAIT

is sampled 1MCx0[0_ASST]+1 32 DF_SCLK 1

tX_ASST_H

OLD

nPWAIT sample high to command

de-asserted 1(2*MCx0[0_ASST])+1 63 DF_SCLK 1

tXCS nXCVR EN assert to com m and

assert 1 MCx0[SET] 127 DF_SCLK 1

tCXH Command de-assert to nXCVREN

de-assert 1 MCx0[HOLD] 63 DF_SCLK 1

tCMD Command assertion time 3 (3*MCx0[0_ASST])+3+

waits 96 DF_SCLK 1

UAdd LAdd UAdd "XX" & wd[7:0] UAdd LAdd+1 UAdd "xx" & wd[15:7] UAdd

tCXHtCXH

tXCStXCS

tCMD

X_ASST_HOLD

tCMD

X_ASST_WAIT

X_SETtCMD

X_ASST_HOLD

X_HOLD

tCMD

X_ASST_WAIT

X_SET

tAADVH

tADVLtADVL

tAADVS

tADVL

tAADVH

tAADVS

tADVL

tAADVH

tADVL

tAADVS

tAADVH

tADVL

tAADVS

tADVL

tAADVH

tADVLtADVL

tAADVS

tADVL

tAADVS

tADVLtADVL

tAADVH

tAADVS

tADVL

DF_IO[15:0]

nLUA

nLLA

nPCE1

nPCE2

nIOIS16

nPIOW

nPIOR

nPWAIT

nXCVREN

RDnWR

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 168 April 6, 2009, Released

7.2.5 NAND Timing Diagrams and Specifications

This section describes the timing diagrams for NAND flash programming, erase, read, status rea d ,

and ID read with timing parameters.

7.2.5.1 NAND Flash Program Timing

Data-flash program operation wr ites data to the Flash. Figure 89 illustrates the programming

sequen ce fo r a Fla sh d evice wi th a p age siz e of 5 12 bytes , an d a spare area o f 16 by tes . The Flash

device is addressed in four cycles. R e fer to Table 29 for the detailed descriptions of the timing

parameters. If the Auto-read Status bit (AUTO_RS) is set in the command, the NAND Flash

Controller performs a status check (command 0x70) to determine whether the program operation

was successful.

7.2.5.2 NAND Flash Erase Timing

Figure 90 illustra tes the erase sequence for a Flash device. The block to be erased in the Flash

device is ad dressed in two cycles. Re fer to Table 29 for the detailed descriptions of the timing

pa rameters. If the A uto-re ad Status bit (AUT O_RS ) is set in the c omma nd, the Data Flash Contro ller

perfo r ms a status check (Command 0x70) to determine whether the Erase operation was

successful.

NOTE:

1. DF_SCLK frequency depends on the ACCR[SMCFS] and MEMCLKCFG[DF_CLKDIV] programmed

values.

6. Refer to the PXA3xx Processor Fam ily Vol. II: Memory Controller Configuration Develop ers M anu al for more

information on the CSADRCFGx, MCMEMx, MCATTx, and MCIOx registers.

Table 28: Compact Flash Timing Specifications (Continued)

Symbol Description Min Typical Max Units Notes

Figure 89: NAND Flash Program Timing Diagram

ta(IO)ta(IO)

th(WH)

tsu(WL)

tsu(WL)tsu(WL)

tsu(WL)

th(WH)th(WH)th(WH)

tWRCYCLEtWRCYCLEtw(WH)tw(WH)

tw(WL)tw(WL)

80h ADDR1 ADDR2 ADDR3 ADDR4 DIN0 DIN1 DIN527 10h 70h Status

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

ND_nRE

ND_IOx

NAND_RnB

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April 6, 2009, Released Page 169

7.2.5.3 Small Block NAND Flash Read Timing

Figure 91 illustra tes the Read sequence for a Small-block Flash device. The Flash device is

addre ssed in four cycles. Refer to Table 29 for detailed descriptions of the timing parameters.

7.2.5.4 Large Block NAND Fla sh Read Timing

Figure 92 illustrates the Read sequence for a Large-block Flash device. The Flash device is

addre ssed in four cycles. Refer to Table 29 for detailed descriptions of the timing parameters.

Figure 90: NAND Flash Erase Timing Diagram

tw(RL)

tsu(WL)td(AHWL)tsu(WL)

th(WH)th(WH)

th(WH)

th(IO)

tsu(IO)

th(IO)

tsu(IO)

tw(WL)tw(WH) tw(WL)tw(WH)

0x60 70h StatusADDR2ADDR1 0xD0

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

ND_nRE

ND_IOx

NAND_RnB

Figure 91: NAND Flash Small Block Read Timing Diagram

tw(RH)tw(RL)td(WHRL)

th(WH)

tw(WH)tw(WL)tsu(WL)tsu(WL)

th(WH)

th(WH

)

th(IO)

tsu(IO)

tRDCYCLEtRDCYCLE

tRDCYLCEtRDCYLCE

00h ADDR1 ADDR2 ADDR3 ADDR4 DOUT0 DOUT1 DOUT511

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

ND_nRE

ND_IOx

AND_RnB

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 170 April 6, 2009, Released

7.2.5.5 NAND Flash Status Read Timing

Figure 93 illustra tes the Status-read sequence for a Flash device. Refer to Table 29 for detailed

desc rip tio ns of the timing pa rameters.

7.2.5.6 NAND Flash ID Read Timing

Figure 94 illustra tes the ID read sequence for a Flash device. Refer to Table 29 for detailed

desc rip tio ns of the timing pa rameters.

Figure 92: NAND Flash Large Block Read Timing Diagram

30h

tw(RH)tw(RL)td(WHRL)

th(WH)

tsu(WL)tw(WH)tw(WL)tsu(WL)tsu(WL)

th(WH)

th(IO)

tsu(IO)

tRDCYCLEtRDCYCLE

00h ADDR1 ADDR2 ADDR3 ADDR4 DOUT0 DOUT1 DOUT2112

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

ND_nRE

ND_IOx

NAND_RnB

Figure 93: NAND Flash Status Read Timing Diagram

tw(RL)td(WHSRL)

tw(WL)

tsu(WL)

th(WH)

th(IO)

tsu(IO)

tw(WH)tw(WH)

70h Status

ND_nCSx

ND_CLE

ND_nWE

ND_nRE

ND_IOx

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April 6, 2009, Released Page 171

7.2.5.7 NAND Flash Rese t Timing

Figure 95 illustra tes the reset sequence for a Flash device. Refer to Table 29 for detailed

desc rip tio ns of the timing pa rameters.

7.2.5.8 NAND Flash Timing Parameters

Table 29 provides the values for th e timing parameters seen in Figure 89, Figure 90, Figure 91,

Figure 92, Figure 92, Figure 93, Figure 94 an d Figure 95.

Figure 94: NAND Flash ID Read Timing Diagram

th(WH)

tsu(WL)

th(WH)

th(IO)tsu(IO)

tw(RH)tw(RL) tw(RH)tw(RL)td(ALRL)

tsu(WL)

tw(WL)tw(WL)

0x90 Byte 1 Byte 20x00

ND_nCSx

ND_CLE

ND_nWE

ND_ALE

ND_nRE

D_IO[7:0]

Figure 95: NAND Flash Reset Timing Diagram

0xFF

tsu(WL)

th(WH)

ND_CLE

ND_nCSx

ND_nWE

ND_ALE

ND_nRE

ND_IOx

NAND_RnB

Table 29: NAND Flash Interface Program Timing Specifications

Symbol Description Min1Min2Typical Max Units

Notes

tsu(WL) Setup time for ND_ALE, ND_CLE

and ND_CSx with respect to

ND_nWE assertion

1 1 NDTR0CS0 [tCS] + 1 8 NCLK 3, 4

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 172 April 6, 2009, Released

th(WH) Hold time for ND_ALE, ND_CLE

and ND_CSx with respect to

ND_nW E de-ass er tion .

2 1 NDTR0CS0 [tCH] + 1 8 NCLK 3, 4

tw(WL) ND_nWE pulse width during

assertion dela y 2 1 NDTR0CS0[tWP] + 1 8 NCLK 3, 4

tw(WH) ND _nWE pulse width during

de-assertion delay 2 1 NDTR0CS0[tWH] + 1 8 NCLK 3, 4

tw(RL) ND_nR E pulse width during

assertion dela y 4 1 NDTR0CS0[tRP] + 1 16 NCLK 3, 4

tw(RH) ND_nRE pu lse wi dth duri ng

de-assertion delay 3 1 NDTR0CS0[tRH] + 1 8 NCLK 3, 4

td(WHRL) ND _nW E high to ND_nRE low

dela y for rea d 3 3 (NDTR1CS0[tR] + 2)

+ (NDTR0CS0[tCH] +

65536 NCLK 3, 4

td(WHSRL) ND_nWE high to ND _nRE low

delay for status read 1 1 NDTR1CS0[tWHR]5,

632 NCLK 3, 4

td(ALRL) ND_ALE high to ND_nRE low

delay for ID read 1 1 NDTR1CS0[tAR]7, 816 NCLK 3, 4

ta(IO) ND_IOx dat a access time 2.5 2.5 — 10 ns —

tsu(IO) ND_IOx se tu p time const ra in t 2 3 23 — — ns —

th(IO) ND_IO x ho ld tim e constrai nt 2 3 23 — — ns —

tRDCYCLE Read cycle times 67.31 30 — — ns —

tWRCYCLE Write cycle time s 38.46 30 — — ns —

NOTE:

1. PXA32x pr ocessor only

2. PXA31x pr ocessor and PXA30x pr oce ssor only

3. NCLK repre sents the clock period using a 156 MHz clock on t he PXA31x pr ocessor and PXA30 x pr oc essor.

4. NCLK represents the cloc k period usi ng a 104 MH z cl ock on the P XA32x processor

5. If NDTR0CS1[ tAR] + NDTR0CS 0[tCH] >= NDTR0C S1[tWHR ] Delay = NDTR0CS0[tCH] + (NDTR0C S1[tAR] + 2)

6. If NDTR0CS1[tAR] + NDTR0CS 0[tCH] < NDTR0CS1[ tWHR] Delay = (NDTR0CS1[tWHR] + 1)

7. If NDTR0CS1[ tAR] + NDTR0CS 0[tCH] >= NDTR0C S1[tWH R] Delay = NDTR0CS1 [tAR] + 1

8. If NDTR0CS1[tAR] + NDTR0CS0[tCH] < NDTR0CS1[tWHR] Delay = (NDTR0CS1[tWHR] - NDTR0CS0[tCH])

9. Refer to the PXA3xx Processo r Family Vol. II: Memory Controller Configuration Dev elop ers Man ual for more

information on the NDTR0CS0 and NDTR0CS1 registers.

Table 29: NAND Flash Interface Program Timing Specifications (Continued)

Symbol Description Min1Min2Typical Max Units

Notes

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7.3 Quick Capture Camera Interface Timing Diagrams

and Specifications

This section describes the timing diagrams for master-parallel mode of operation with timing

parameters.

7.3.1 Master-Parallel Timing

The master-parallel interface timing is shown in Figure 96. See Table 30 for camera timing

parameters. The frame clock (C_FV) must first be asserted to indicate that a new frame has begun.

The valid data is then captured with the active edge of PCLK, after Beginning of Line Wait Count

(CICR2[BLW]) PCLK cycles have elapsed from the assertion of C_LV. At the end of the capture of

the la st line of a fra me, the Quick Capture I nterfac e wait s for the a sserti on of C_FV to begin th e next

frame-capture sequence.

7.3.2 Master-Parallel Interface Timing Specifications

Table 30 describes the camera timing parameters for Figure 96.

Figure 96: Camera Master-Parall el Timing D iagr am

tw(M)

tw(PL)tw(PL)

tw(PH)tw(PH)

tw(ML)tw(ML)

tw(MH)tw(MH)

th(P)

tsu(P)

tw(P)tw(P)

LINE0 DATA LINE1 DATA LINE n DATA

n=LPF-1

_M CLK (optional)

C_PCLK

C_FV

C_LV

C_DDx

Table 30: Master-Parallel Timing Specifications (PXA32x Processor and PXA30x Processor Only)

Symbol Description Min Typical Max Units Notes

tw(M) C_MCL K pulse width freq uency 0.48 — 52 MHz

tw(P) C_PCLK pulse w idth fre quency 3.0 — 48 M H z 1

tw(MH) C_MCL K pul se width high tim e 9.5 — 4352 nS

tw(ML) C_MCLK pul se width low tim e 9. 5 — 4352 nS

tw(PH) C_PCLK puls e wi dth high tim e 10 — 158.3 nS

tw(PL) C_PCLK pu lse w idth low t ime 10 — 158.3 nS

tsu(P) C_DD x to C_PC LK setup tim e constraint 2.2 — — ns

th(P) C_PCLK to C_DDx hol d t ime constr ai nt 3.0 — — ns

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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7.3.3 Slave-Parallel Timing

Figure 97 shows the timing for slave-parallel mode of operation. See Table 32 for the slave-parallel

timing parameters. The timing is very similar to that of m a ster-slave, exce pt that in Slave-Parallel

mode, the Qui ck Capture Interface drives the synchronization signals C_LV and C_FV. C_FV and

C_LV are driven for the duration s pecified by Vertical Sync Wid th (CICR3[VSW]) and Horizontal

Sync Wi d th (CIC R2 [HS W ]), r esp ec tiv ely. The dela y (in PC LK c y cles) be tw een C_FV being as se rted

and C_LV being asserted is configured with CICR2[BFPW]. The number of fra m e clock (C_FV)

periods to wait before valid data is output is configured with C ICR2[FSW].

NOTE:

1. Maxim um al low able fre que ncy of C_PCLK is 1/4 of Syst em bus #1 (Application Subsyst em C lock Configuratio n

Table 30: Master-Parallel Timing Specifications (Continued)(PXA32x Processor and PXA30x

Symbol Description Min Typical Max Units Notes

Table 31: Master-Parallel Timing Specifications (PXA31x Processor Only)

Symbol Description Min Typical Max Units Notes

tw(M) C_MCLK pulse width frequency 0.48 — 52 MHz

tw(P) C_PCLK pulse width frequency 3.0 — 96 MHz 1

tw(MH) C_MCLK puls e w idt h high time 9.5 — 435 2 nS

tw(ML) C_MCLK pulse width low time 9.5 — 4352 nS

tw(PH) C_PCLK pulse width high ti m e 4.95 — 158.3 nS

tw(PL) C_PCLK pulse width low time 4.95 — 158.3 nS

tsu(P) C_DDx to C_PCLK setup time constraint 2.2 — — ns

th(P) C_PCLK to C _DDx hol d time co nstr aint 3.0 — — ns

NOTE:

1. Maxim um al low able fre que ncy of C_PCLK is 1/2 of Syst em bus #1 (Application Subsyst em C lock Configuratio n

Note

Before the Qu ick Capture Interface starts operatin g in this mode, configure the sens or

to float the sy nchron iz ati on pins.

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April 6, 2009, Released Page 175

7.3.4 Slave-Parallel Interface Timing Parameters

Table 32 describes the camera timing parameters for Figure 97.

7.4 LCD Timing Diagrams and Specifications

This sec tion des cribes the ti ming diagra ms for inte rfacin g to Passi ve, Activ e, and Sma rt LCD pane ls

with timing parameters.

7.4.1 LCD Passive Timing

For Pas sive (and Acti ve ) LCD p a nels, t he l ine-cl ock pi n (L_ LCLK_A0) is to ggl ed wh en a n en tire lin e

of pix els has b een o utp ut to th e LCD Co ntro lle r s cr een . L ikew ise, th e fram e-c lock p in (L_ FC LK _RD )

is toggled when an en tire frame of pixels has been outpu t to the LCD Controller scree n .

Switch the power and ground supplies periodic ally to pr event a D C charge from bui lding w ithin a

Pass ive dis play. The LCD con troller sign als the di splay to switch the polari ty by togg ling the AC bias

pin (L_BIAS). Program the number of line-clock transitions between each toggle to control the

frequ ency of th e bias pin.

Figure 97: Camera Slave-Parallel Timing Diagram

tw(M)

tw(PL)tw(PL)

tw(PH)tw(PH)

tw(ML)tw(ML)

th(P)

tsu(P)

tw(P)tw(P)

LINE0 DATA LINE1 DATA LINE n DATA

n=LPF-1

_M CLK (optional)

C_PCLK

C_FV

C_LV

C_DDx

Table 32: Slave-Par alle l Timing Specifications

Symbol Description Min Typical Max Units Notes

tw(M) C_MCLK pulse width frequency 0.203 — 52 MHz

tw(P) C_PCLK pulse width frequency 3.0 — 6.25 MHz

tw(MH) C_M CLK pul se wid th hi gh time 9.5 — 2338 ns

tw(ML) C_MCLK pulse width low time 9.5 — 2338 ns

tw(PH) C_PCLK pulse width high time 76 — 158.3 ns

tw(PL) C_PCLK pul s e w idth low time 76 — 158. 3 ns

tsu(P) C_DDx to C_PCLK setup time constraint 3.7 — — ns

th(P) C_PCLK to C_ DDx hol d time co nstraint 0.0 — — ns

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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The p rogra mm ab le tim ing of th e line- and fram e-c lock pin s su pports both Pa ss ive an d A ctiv e m od e.

Programming options include: wait-st ate insertion both at the beginning and end of each line and

frame ; pixel clo ck; line c lock; fram e clock ; outpu t-enabl e signal po larity; and frame -cloc k puls e widt h.

Figure 98 and Figure 99 illustrate the LCD timing parameters. Table 33 provides the valu es for the

parameters.

Figure 98: LCD Passive Panel Synchronous Timing Diagra m

ro w 0

row 1

ro w 2

ro w n

ro w 0

row 1

tw(P)

td(LDDV) BLW=0

tw(VSP) V SW=0

tw(H SP) H SW=1

tw(L)

td(DVLA) ELW=0

tw(F)

L_FCLK_RD

L_LCLK_A0

_PCLK_WR

LDD<17:0>

Figure 99: LCD Passive Panel Data Timing Diagram

Data

th(DVP)tsu(PDV)

LCLK

L_PCLK_WR

><X:0L_DD

Table 33: LCD Passive Panel Timing Specifications

Symbol Description Min Typical Max Units Notes

tw(P) L_P CL K_WR period

(Pixel Clock Pulse Width) 9.6 LCLK

/(2*(LCCR3[PCD]

+1))

4920 ns 1, 2, 5,

tw(L) L_LCLK_ A0 pulse width

duration

(Horizontal Sync (Line Clock)

Pulse Width )

12 td(LDDV) +

LCCR1[PPL] +

td(DVLA) +

tw(HSP)

1312 tw(P) 1, 3

tw(F) L_FCLK_R D pulse width

duration

(Ve rtical Sync (Frame Clock)

Pulse Width )

2LCCR2[LPP] + 1 +

tw(VSP) 864 tw(L) 1, 3

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7.4.2 LCD Active Panel Timing

For Acti ve (a nd Pas s ive) LC D p ane ls , the line clo ck pin (L_LC LK _A 0) is togg le d when an ent ire li ne

of pix els has b een o utp ut to th e LCD Co ntro lle r s cr een . L ikew ise, th e fram e-c lock p in (L_ FC LK _RD )

is toggled when an en tire frame of pixels has been outpu t to the LCD Controller scree n .

The p ixel clock toggles continuously in this mo de as long as the LCD is enabled. The AC bias pin

(L_BIAS) functions as an Output E nable. When L_BIAS is a sserted, the display latches data from

the L CD pins using the pixel clock. The line-clock pin (L_LCLK_A0) is used a s the horizontal

synchronization signal, and th e frame clock (L_FC LK_RD) as the vertical synchronization s ignal.

The p rogra mm ab le tim ing of th e line- and fram e-c lock pin s su pports both Pa ss ive an d A ctiv e m od e.

Programming options include: wait-st ate insertion both at the beginning and end of each line and

frame ; pixel clo ck; line c lock; fram e clock ; outpu t-enabl e signal po larity; and frame -cloc k puls e widt h.

tw(HSP) Horizontal Sync Puls e W i dth 1 LCCR1[HSW] + 1 64 tw(P) 1, 4

tw(VSP) Vertical Sync Pulse Width 1 LCCR2[VSW] + 1 64 tw(L) 1

td(LDDV) Beginning-of-Line

L_PCL K_WR wait del ay 1LCCR1[BLW] + 1 256 tw(P) 1,5

td(DVLA) End-of-Line L_PCLK_WR wait

delay 1LCCR1[ELW] + 1 256 tw(P) 1

tsu(PDV) L_PCLK_WR to Data valid set

up time when PCLK divisor is

an even number

——2

9 + 0.5ns LCLK 5,6,7

tsu(PDV) L_PCLK_WR to Data valid set

up time when PCLK divisor is

an odd number

——(divisor - 1))/2)9 +

0.5ns LCLK 5,6,7

th(DVP) End-of-Line L_PCLK_WR hold

time when PCLK divisor is an

even number.

29 + 0.5ns — — LCLK 5,6,7

th(DVP) End-of-Line L_PCLK_WR hold

time when PCLK divisor is an

odd num ber

(((divisor - 1)/2) +

1)9 + 0.5ns —— LCLK5,6,7

NOTE:

1. PCLK is short for pi xel cl ock.

2. P ixel clock is programmable based off LCLK. LCLK frequency depends on the ACCR[HSS] programmed value.

3. In this example, horizontal-sync polarity as shown is active high, inactive low . Use LCCR3[HSP] for configuring polarity .

4. In this example vertical-sync polarity is active high, inactive low. Use LCCR3[VSP] for configuring polarity.

5. In this exam ple pixel- cl ock polarit y is configured to sample data o n th e risi n g edg e of L_PCLK_ WR (LCC R 3[ PC P]=0).

6. In this example the LCLK is 104 MHz and the divisor is 5 (20.8 MHz).

7. The divisor is determined by the LCCR3[PCD] register. The setup and hold times are different depending on the divisor

value.

8. LCLK can vary from104 MHz to 208 MHz. Refer to the PXA3xx Processor Family Vol. III: Graphics and Input Controller

Configuration Developers Manual, for more information.

9. LCLK cl ock cycles

10. There are no Beginning-of-Frame LCLK wait to End-of-Frame LCLK wait delay timings for passive panels.

LCCR2[BFW] and LCCR2[EFW] must be zero for passive panels.

Table 33: LCD Passive Panel Timing S pecifications (Continued)

Symbol Description Min Typical Max Units Notes

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 178 April 6, 2009, Released

Figure 100 and Figure 101 illustrate the LCD t iming p arameter s. Table 34 provides the values fo r the

parameters.

Figure 100:LCD Active Panel Timing Diagram

Figure 101:LCD Active Panel Timing Diagram

Line 0

Line 1

Lin e 2

Line n

td(LDDV ) BLW=0tw(P)

tw(L)

td(DV LA) ELW=1

td(FDLD) BFW=1

tw(H SP) H SW=1

tw(F) td(LAFA)tw(V SP) VSW=0

L_FCLK_RD

L_LCLK_A0

L_ BIAS

_PCLK_WR

LDD<17:0>

Data

th(DVP)tsu(PDV)

LCLK

L_PCLK_WR

><X:0L_DD

Table 34: LCD Active Panel Timing Specifications

Symbol Description Min Typical Max Units Notes

tw(P) L_PCLK_WR period

(Pixel Clo ck Pu ls e W idth) 9.6 LCLK

/(2*(LCCR3[P

CD]+1))

4920 ns 1, 2, 5, 6

tw(L) L_LCLK_A0 pulse width duration

(Horizontal Sync (Line Clock) Pulse Width) 12 td(LDDV) +

LCCR1[PPL] +

td(DVLA) +

tw(HSP)

1312 tw(P) 1, 3

tw(F) L_FCLK_RD pul s e w i dth durati on

(Vertical Sync (Frame Clock) Puls e Width) 2 LCCR2[LPP] +

1 + tw(VSP) 1174 tw(L) 1, 3

tw(HSP) Horizontal Sync Pulse Width 1 LCCR1[HSW]

+ 1 64 tw(P) 1, 4

tw(VSP) Vertical Sync Pulse Width 1 LCCR2[VSW]

+ 1 64 tw(L) 1

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April 6, 2009, Released Page 179

7.4.3 LCD Smart Panel Timing

Figure 102 illustrates the LCD timing parameters for Smart p anels. Table 35 provid es the values for

the paramet ers.

td(LDDV) Beginning-of-Line L_PCLK_WR wait delay 1 LCCR1[BLW] +

1256 tw(P) 1,5

td(DVLA) End-of-Line L_PCLK_WR wait delay 1 L CCR1[ELW] +

1256 tw(P) 1

td(FDLD) Beginning-of-Frame LCLK wait delay 0 LCCR2[BFW] 255 PCLK 1

td(LAFA) End-of-Frame LCLK wait delay 0 LCCR2[EFW] 255 ns —

tsu(PDV) L_PCLK_WR to Data valid set up time when

PCLK divisor is an ev en numbe r —— 2

11 +

0.5ns LCLK 5,6,7

tsu(PDV) L_PCLK_WR to Data valid set up time when

PCLK divisor is an od d num ber —— (divisor -

1))/2)11 +

0.5ns

LCLK 8,9,10

th(DVP) End-of-Line L_PCLK_WR hold time when

PCLK divisor is an ev en numbe r. 211 +

0.5ns ——LCLK8,9,10

th(DVP) End-of-Line L_PCLK_WR hold time when

PCLK divisor is an od d num ber (((divis

or -

1)/2) +

1)11 +

0.5ns

——LCLK8,9,10

NOTE:

1. PCLK is shortened fo rm of pixel cl ock.

2. Pixel clock is programmable based off LCLK. LCLK frequency depends on the ACCR[HSS] programmed value.

3. In this exam pl e, horizo ntal-sync pola rit y as shown is acti ve high, inact i ve low. Use LCCR3[HSP] fo r co nf igur i ng

polarity.

4. In this example vertical-sync polarity is active high, inactive low. Use LCCR3[VSP] for configuring polarity.

5. In this example pixel-clock polarity is configure d to sample data on the rising edge of L_PCLK_WR (LCCR3[PCP]=0).

6. In this exam pl e the LCLK is 104 MHz and the d iv isor is 5 (20 .8 MHz).

7. The div isor is d et er m in ed by the LCCR3[PCD] reg i st er. The setup and hol d times are different depending on the

divisor val ue.

8. In this example pixel-clock polarity is configure d to sample data on the rising edge of L_PCLK_WR (LCCR3[PCP]=0).

9. In this exam pl e the LCLK is 104 MHz and the d iv isor is 5 (20 .8 MHz).

10. The divisor is d etermined b y th e LC CR3[PC D] reg i st er. The se tu p and hold times are different depending on the

divisor val ue.

11. LCLK clock cycl es

12. LCLK can va ry from 104 MHz to 20 8 M H z. Ref er to the PXA3 xx Pr ocessor Family Vol. III: Graphics and Input

Contro l le r Con f ig ur at io n Develop er s M anual, for more information.

Table 34: LCD Active Panel Timing Specifications (Continued)

Symbol Description Min Typical Max Units Notes

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 180 April 6, 2009, Released

Figure 102:LCD Smart Panel Timing Diagram

DWR_HLD

RD_PULWD

A0CSRD_SET

WR_PULWD

DWR_SET

A0CSWR_SET

A0CSRD_HL

CMD_INH

A0CSWR_HLD

L_CS

L_LCLK_A0

_PCLK_WR

L_FCLK_RD

L_LDDx

Table 35: LCD Smart Panel Timing Specifications

Symbol Description Min Typical Max Units Notes

tA0CSWR_SET L_CS low to L_PCLK_WR low

delay 1 LC C R 1[E LW] + 1 256 L C LK 1

tWR_PULWD L_P CL K_WR pul se width dur ati on 1 LCC R 1[BLW] + 1 256 LCLK 1

tDWR_SET LDDx write data setup before

PCLK_WR low 1 LC C R1[ ELW] + 1 256 L CLK 1

tA0CSWR_HLD L_PCLK_WR high to L_CS high

delay 1 LC C R 1[E LW] + 1 256 L C LK 1

tDWR_HLD L_LDDx write data hold after

L_PCL K_WR hi gh 1 LCCR1[ E LW] + 1 256 L C LK 1

tCMD_INH L_CS recover time for two

consecutive read or write s

(inclu de w r ite /read and rea d/ w r ite)

1 LCCR3[PCD] + 1 256 L CLK 1

tA0CSRD_SET L_CS low to L_FCLK_RD low

delay 1 LC C R 1[E LW] + 1 256 L C LK 1

tRD_PULWD L _FCLK_R D pul se width durati on 1 LC C R1[ B LW] + 1 256 L C LK 1

tA0CSRD_HLD L_FCLK_ RD hi gh to L_CS high

delay 1 LC C R 1[E LW] + 1 256 L C LK 1

NOTE:

1. LCLK freq uency depe nds on the AC C R[ H SS] pr ogr am m ed value.

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7.5 SSP Timing Diagrams and Specifications

Figure 103 and Table 36 convey the SSP timing parameters with SSP in Master mode. The

processor drives SSPSCLK and SSPSFRM when in Master mode. Figure 104 and Table 37 convey

the SSP timing parameters with SSP in Slave mode. The processor receives SSPSCLK and

SSPSFRM when in Slave mode.

The processor can also provide SSPSCLK while the external peripheral sources SSPSFRM, which

is termed a “mixed mode” as in shown in Figure 105 with the timing parameters specified in

Table 38. Similarly, the processor can also receive SSPSCLK while the external peripheral provides

SSPSFRM, which is termed a “mixed mode” as in shown in Figure 106 with the timi ng parameters

specified in Table 39.

SSP Master Mode Timing

Figure 103:SSP Master Mode Timing Diagram

th(T)

tsu(T)

tw(CH)

tw(CL)

th(R)

tsu(R)

SSPSCLK

SPSFRM

SSPTXD

SSPRXD

Table 36: SSP Master Mode Timing Specifications

Symbol Description Min Max Units Notes

tw(CH) SSPSCLK pulse width high dura t io n 38.46 — ns 1

tw(CH) SSPSCLK pulse width high dura t io n 19.23 — ns 2

tw(CL) SSPSCLK pulse width low durati on 3 8.46 — ns 1

tw(CL) SSPSCLK pulse width low durati on 1 9.23 — ns 2

tsu(T) SSPTXD to SSPSCLK setup time 35 — ns

th(T) SSPSCLK to SSPTXD hold time 33 — ns

tsu(R) SSPRXD to SSPSCLK setup time 4 — ns

th(R) SSPSCLK to SSPRXD hold time 3.6 — ns

NOTE:

1. Timing for PXA32x and PXA30x onl y

2. Timing for P XA31 x only

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 182 April 6, 2009, Released

7.5.1 SSP Slave Mode Timing

Figure 104:SSP Slave Mode Timing Definitions

th(T)

tsu(T)

th(R)

tsu(R)

tw(CH)

tw(CL) tw(CH)

tw(CL)

SSPSCLK

SPSFRM

SSPTXD

SSPRXD

Table 37: SSP Slave Mode Timing Specifications

Symbol Description Min Max Units

tw(CH) SSPS CLK pul se wid th hi gh duration 38.46 — ns

tw(CL) SSPSCLK pulse w i dth l ow dura t ion 38.46 — ns

tsu(T) SSPTXD to SSPSCLK se tup time 35 — ns

th(T) SSPSCLK to SSPTXD hold time 33 — ns

tsu(R) SSPSRXD to SSPSCLK setup time 4 — ns

th(R) SSPSRXD to SSP SSCLK hold time 3.6 — ns

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7.5.2 SSP Mixed Mode Timing - Processor Master to Clock

Figure 105:SSP Mixed Mode, Processor Master to Clock Timing Definitions

th(T)

tsu(T)tw(CH)tw(CL)

th(R)

tsu(R)

SSPSCLK

SPSFRM

SSPTXD

SSPRXD

Table 38: SSP Mixed Mode, Processor Master to Clock Timing Specifications

Symbol Description Min Max Units Notes

tw(CH) SSPSC LK pu lse width high duration 38.46 — ns 1

tw(CH) SSPSC LK pu lse width high duration 19.23 — ns 2

tw(CL) SSPSCLK pu lse width low duration 38.46 — ns 1

tw(CL) SSPSCLK pu lse width low duration 19.23 — ns 2

tsu(T) SSPTXD to SSPSCLK setup time 35 — ns

th(T) SSPSCLK to SSPTXD hold time 33 — ns

tsu(R) SSPSRXD to SSPSCLK setup time 4 — ns

th(R) SSPSRXD to SSPSS CLK hold time 3.6 — ns

NOTE:

1. Timing for PXA32x a nd PX A30 x only

2. Timing for PXA31x only

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 184 April 6, 2009, Released

7.5.3 SSP Mixed Mode Timing - Processor Master to Frame

7.6 AC ’97 Timing Diagrams and Specifi cations

Figure 107 and Table 40 defines the AC ’97 CODEC inte rfac e AC tim in g specifi ca tio ns .

Figure 106:SSP Mixed Mode, Processor Master to Frame Ti ming Definitions

Table 39: SSP Mixed Mode, Processor Master to Frame Timing Specifications

Symbol Description Min Max Units Notes

tw(CH) SSPSCLK puls e w idth high duration 38.46 — ns 1

tw(CH) SSPSCLK puls e w idth high duration 19.23 — ns 2

tw(CL) SSPSC LK pulse w idth low dur at i on 38.46 — ns 1

tw(CL) SSPSC LK pulse w idth low dur at i on 19.23 — ns 2

tsu(T) SSPTXD to SSPSCLK setup time 35 — ns

th(T) SSPSCLK to SSPTXD hold time 33 — ns

tsu(R) SSPSRX D to SSPSCLK setup time 4 — ns

th(R) SS PSRX D to SSPSSCLK hold time 3.6 — ns

NOTE:

1. 0Timing for PXA32 x an d PXA3 0x only

2. 0Timing for PX A31 x only

th(T)

tsu(T)

th(R)

tsu(R)

tw(CH)

tw(CL) tw(CH)

tw(CL)

SSPSCLK

SPSFRM

SSPTXD

SSPRXD

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April 6, 2009, Released Page 185

7.7 USB 2.0 Timing Diagrams and Specifications

(PXA32x and PXA30x only)

Figure 108 and Table 41 defines the AC characteristics for the USB 2.0 timing specification s.

Figure 107:AC ’97 CODEC Timing Diagram

tw(S)

td(BH-SDV)

td(BH-SV)

th(D)

tsu(D)

tw(B)tw(B)

AC97_RESET_N

AC97_BITCLK

AC97_SYNC

AC97_SDATA_OUT

AC97_SDATA_INx

AC97_SYSCLK

Table 40: AC ’97 CODEC Timing Specifications

Symbol Parameter Min Max Units Notes

tw(B) AC97 _BI TC L K pul se width const ra int 40.69 — ns 1

td(BH-SV) AC97 _BI TC LK high to AC9 7_SYNC va lid del ay 8.18 22.68 ns 1

td(BH-SDV) A C97_BITCLK high to AC9 7_SDATA_O UT vali d delay 7 .78 23.08 ns 1

tsu(D) AC97_SDATA_INx t o AC97_BITC LK setup time

constraint 4.33 — ns 1

th(D) A C 97 _BI TC L K to AC 97_SDATA_INx hold time

constraint 0.93 — ns 1

tw(S) AC97 _SYSCLK pulse w idth de lay 20.34 — ns

NOTE:

1. Slew rate for incom ing BI TCLK is 0.5 V/ns

Figure 108:USB 2.0 Timing Diagram

Valid

tDCO

TCCO

tDH_MINtDSU_MIN

tCH_MINtCSU_MIN

UTM_CLK

Control In

Data In

Control Out

Data Out

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 186 April 6, 2009, Released

7.8 MultiMedia Card Timing Diagrams and Specifications

Figure 109 and Table 42 define the MultiMedia Card controller AC timing specification s.

Table 41: USB 2.0 Timing Specifications

Symbol Parameter Min Max Unit Notes

tCSU_MIN Minimum setup time for TxValid 4.8 15.5 ns —

tCH_MIN Minimum Hold time for TxValid 1 —ns —

tDSU_MIN Minimum setup time for Data in (Transmit) 4.8 15.5 ns —

tDH_MIN Minimum hold time for Transmit Data 1 —ns —

tCCO Clock to Control Out time for TxReady, RxValid, RxActive and

RxError 18ns —

tCDO Clock to Data Out time (recei ve ) 1 8 ns —

Figure 109:MultiMedia Card Timing Diagrams

Data In Invalid Data In

Data Out Invalid Data Out

tOHtOSU

tIHtISU

tWL

tFREQ

tWH tWLtWH tFREQ

MMCLK

MMDAT0/1

MMDAT2/3

Table 42: MultiMedia Card Timing Specifications

Symbol Parameter Min Max Unit Notes

tFREQ M M C LK Frequ ency Data Transfer

Mode 0 19.5 MHz 2

tFREQ M M C LK Frequ ency Data Transfer

Mode 026MHz3

tFREQ MMCL K Frequency Identification

Mode 0400 kHz

tWH Clock high time 10 —ns 1

tWL Clock low time 10 —ns 1

trise Clock rise time — 10 ns 1

tfall Clock fall time — 10 ns 1

tISU Data input setu p t ime 3—ns 1

tIH Data input hold time 3—ns 1

tOSU Output data set up ti m e 13.1 —ns 1

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7.9 Secure Digital (SD/SDIO) Timing Diagrams and

Specifications

Figure 110 and Table 43 define the Secure Digital (SD/SDIO) controller AC timing specifications.

tOH Output data hol d time 9.7 —ns 1

NOTE:

1. Rise and fall tim es meas ur ed f ro m 10% - 90 % of voltage lev el.

2. Timing for PXA32x processor only.

3. Timing for PXA31x processor and PXA30x processor only.

4. 0 KHz is when the clock is s to ppe d. T he m ini m um 100 KHz frequ ency rang e is wher e a continous

clock is required.

Table 42: MultiMedia Card Timing Specifications (Continued)

Symbol Parameter Min Max Unit Notes

Figure 110:SD/SDIO Timing Diagrams

Data In Invalid

Invalid Data Out

td(Q)td(ID)

tIHtISU

tFREQ

tWHtWL tWH

tFREQ

tWL

MMCLK

MMDAT0/1

MMDAT2/3

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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7.10 JTAG Boundary Scan Timing Diagrams and

Specifications

Figure 111 and Table 44 defines t he AC specifications for the JTAG boundary-scan test signals.

Table 43: SD/SDIO Timing Specifications

Symbol Parameter Min Max Unit Notes

tFREQ MMCLK Frequency Data Transfer Mode 0 19.5 MHz 2

tFREQ MMCLK Frequency Data Transfer Mode 026MHz 3

tFREQ MMCLK Frequency Identification Mode 01/100 400 kHz

tWH Clock high t ime 50 —ns—

tWL Clock low time 50 —ns —

trise Clock rise time — 10 ns 4

tfall Clock fall time — 10 ns 4

tISU Data input setup time 5—ns—

tIH Data input hold time 5—ns—

td(Q) Output Delay time during Data Transfer Mode 014ns —

td(ID) Output Delay time during Identification Mode 050ns —

NOTE:

1. 0 KHz is when the clo ck i s stopped. The m i ni m um 100 KHz frequency ra nge is where continuo us clock is required.

2. Timing f or PXA32x proc es sor only.

3. Timing f or PXA31x proc es sor and PXA30x pr ocessor only.

4. Rise an d fa ll t imes mea sur ed fr om 10% - 90% of voltage le vel.

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Figure 111:JTAG Boundary-Scan Timing Diagram

Table 44: Boundary Scan Timing Specifications

Symbol Parameter Min Max Units Notes

TBSF TCK Frequ ency 0.0 13 M Hz —

TBSCH TCK H igh Time 15.0 — ns 3

TBSCL TCK Low Time 15 .0 — ns 3

TBSCR T CK Rise Time — 5.0 ns 1

TBSCF TCK Fall Time — 5.0 ns 2

Capture-IR

Shift-IR Run-Test/Idle

TOF1

TBSOV1

TBSIH1

TBSIS1

TBSIH1

TBSIS1

TBSIH

TBSIS2

TBSCL

TBSCH

TBSF

TCK

nTRST

TMS

TDI

TDO

ontroller State

Test-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Exit1-IR

Update-IR

Test-Logic-Reset

TnTRS

PXA3xx Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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TBSIS1 Input Setup to TCK TDI, TMS 4.0 — n s —

TBSIH1 Input Hold from TCK TDI, TMS 6.0 — ns —

TBSIS2 Input Setup to TCK nTRST 25.0 — ns —

TBSIH2 Input Hold from TCK nTRST 3.0 — ns —

TnTRST Assertion time of nTRST 6 — ms —

TBSOV1 TDO Valid Delay 1.5 6.9 ns 4

TOF1 T DO Float Delay 1.1 5.4 ns 4

NOTE:

1. Not shown i n diagram. Th i s is th e transition tim e f or TC K from 0.8 V to 2.0 V.

2. Not shown i n diagram. Th i s is th e transition tim e f or TC K from 2.0 V to 0.8 V.

3. Meas ured at 1.5 V

4. Relative to fall ing edge of TCK

Table 44: Boundary Scan Timing Specifications (Continued)

Symbol Parameter Min Max Units Notes

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8Power and Reset Specifications

This section includes s pecifications for the fol lowing:

Power up

Power down

Reset timing

Power consumption

8.1 Power Up Timings

The external voltage regulator and other power-on devices must provide the processor with a

specif ic s equ ence of pow er an d res ets to en sure prop er ope rati on. Figure 112 shows this s equ enc e

and is detailed in Table 45.

Figure 112:Power Up Reset Timing

tSHROH

tSEHPH

tRSTHSEH

tPHLVTH

tVMHVSH

tSEHVMH

tVMAINBFH

tBFHRSTH

tVBHRSTH

VCC_MAIN

VCC_BBATT

nRESET

nBATT_FAULT

SYS_EN

VCC_MVT

VCC_SYSEN

PWR_EN

PWR_SCL

PWR_SDA

nRESET_OUT

CC_APPS, VCC_SRAM

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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8.2 Powerdown Timings

This section has the following powerdown t imings:

S2/D3/C4 - Sleep

S3/D 4/C4 - Deep Sleep

8.2.1 S2/D3/C4 Mode Timings

During S2/D3/C4 (Sleep) mode, the nRESET_OUT and PWR_EN s ignals change state. The

sequen ce ind ic ate d in Figure 113 and detailed in Table 46 is the required timing param eters for

S2/D 3/C4 mode.

Table 45: Power Up Timing Specifications

Symbol Description Min Max Units Notes

tVBHRSTH VCC_BBATT enabled to nRESET high constraint 8 + PMIC

ramp rate —ms1

tVMAINBFH VCC_MAIN enabled to nBATT_FAULT high

constraint 0—ms2

tBFHRSTH nBATT_FAULT high to nRES ET hi gh constraint 165 — μs3

tRSTHSEH nR ESET high to S YS_EN high de lay — 2.00 5 s —

tSEHVMH SYS_EN high to VCC_MVT stable 0 SYS_DEL

time μs5

tVMHVSH VCC_MVT enabled to VCC_SY SEN stable 0 SYS _DEL

time -

tSEHVMH

μs4, 5

tSEHPH SYS_EN high to PWR _EN high delay 182 SYS_DEL

time + 183 μs5

tSHROH SYS_EN high to nRESET_OUT high delay SYS_DEL

time + 213 SYS_DEL

time + 214 μs5

tPHLVTH PWR_EN high to VCC_APPS and VCC_SRAM

supplies stable 0PWR_DEL

time μs6

NOTE:

1. PMIC Ramp Rate is the time for PMIC voltages to ramp to the preferred volt a g e levels . Incre asing the ramp rate

decreas es the ove ra ll power-u p tim ing.

2. VCC_MA I N is th e m ai n battery su pp ly vol tage

3. nBATT_FA U LT is the signal that is used to deter m ine if th e ma i n pow e r supply is con nected. If nBATT_FAULT occurs

after nRESET, the processor enters an S3/D4/C4 before going into S0/D0/C0.

4. VCC_SYSEN = All supplies exc ep t VCC_BBATT, VCC_APPS, VCC_ SRAM an d VCC_MVT.

5. Defined by programm i ng PCF R [SYS_ DEL]

6. Defined by pro gr amming PCFR[PW R _D EL]

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Figure 113:S2/D3/C4 Timing

NOTE:

1. nRESET _OUT as sertion is an option for S2/D3/C4 entry. By clea rin g the PCFR [SL_ROD], nRESET_OUT is

asserted upon entry into S2/D3/C4.

SLEEP (ENTRY) SLEEP SLEEP (EXIT) NORMAL

tPHROHtPHROH

tEXIT

tENTRY

tWAKEDETECT

tPHLVTHtPLLVTL

tEWHEWV

tEWLEWH

tEWHEWV

tEWLEWH

Wakeup Event Detected

EXT_WAKEUPx

PWR_EN

PWR_SCL

PWR_SDA

VCC_APPS, VCC_SRAM

nRESET_OUT

Table 46: S2/D3/C4 Timing Specifications

Symbol Description Min Typical Max Units Notes

tENTRY PWRMODE S2/ D 3/C4 state com m and

issued to PWR_EN low delay 78 μs4

tPLLVTL PWR_EN low to VCC_ APPS and

VCC_SRAM supplies disabled constraint 0— — s—

tPLROL /

tPHROH

PWR_EN low to nRESET_OUT low and

PWR _EN hi gh to nRESET_OUT hi gh

delay

-62.5 — 62.5 μs2

tEWLEWH E XT_WAKEUPx low pu lse width

constraint 5— — ns1, 3

tEWHEWV EXT_WAKEUPx high pulse width

constraint 5— — ns1, 3

tPHLVTH PWR_EN high to VCC_AP PS and

VCC_SRAM supplies stable — — PWR_DE

L time μs2

tWAKEDETEC

Ack nowle dge the external wak e-up edge

and to be gi n t he w ak e- u p sequence delay —— 150 μs—

tEXIT Wake-up event to th e ru n m ode delay — 7.9 — ms 4

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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8.2.2 S3/D4/C4 Mode Timings

During S3/D4/C4 (Deep Sleep) mode, nRESET_OUT, PWR_EN and SYS_EN change state. The

sequen ce ind ic ate d in Figure 114 and detailed in Table 47 is the required timing param eters for

S3/D 4/C4 (Deep Sleep) mode.

NOTE:

1. EXT_WAKEUPx signal show n in th e di agram is for fall ing edge det ec t. H ow e ver, either edge or bot h edge dete ct can

be enabled. PWER[WERx] and FWER[WEFx] configures which edge is used for detection.

2. S2/D3/C4 state nRESET_OUT Disable (PCFR[SL_ROD]) — Prevents the nRESE T_OUT pin from asserting upon

entry into S2 /D3/C4 or S 3/D 4/ C4 m odes.

3. EXT_WAKEUPx sign al sho w n in this diagr am i s ba sed of PWE R[E D F] bit be in g set.

4. Time with PC FR [ PW R _DEL] = 0b0 and no Pow e r I2C comm ands.

Table 46: S2/D3/C4 Timing S pecifications (Continued)

Symbol Description Min Typical Max Units Notes

Figure 114:S3/D4/C4 Timing

NOTE:

1. VCC_SYSEN = All supplies except VCC_BBATT, VCC_APPS, VCC_SRAM and VCC_MVT.

2. nRESET _OUT ass ertion is an op tion for S3/D4/C4 entry. By clearing the PCFR[SL_ROD], nRESET_OUT is

asserted upon entry into S3/D4/C4.

DEEP SLEEP (ENTRY) DEEP SLE EP DEE P SLEEP (EXIT) NORMAL

tSHROH

tDENTRY

tROLSL

tPLSL

tSEHPH

tDEXIT

tWAKEDETECT

tBFHBFLtBFLBFH tBFHBFLtBFLBFH

tVMHVSHtVSLVML

tLVTLVSL

tSLVSL

tSEHMVTH

tPHLVTHtPLLVTL

tEWHEWV

tEWLEWH

tEWHEWV

tEWLEWH

Wakeup Signal

EXT_WAKEUPx

PWR_EN

PWR_SCL

PWR_SDA

CC_APPS, VCC_ SRAM

SYS_EN

VCC_MVT

VCC_SYSEN

nRESET_OUT

nBATT_FAULT

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April 6, 2009 Released Page 195

Table 47: S3/D4/C4 (Deep Sleep) Timing Specifications

Symbol Description Min Typical Max Units Notes

tDENTRY PWRMODE S3/D 4/C4 stat e comma nd

issued to SYS_EN low delay —1.4 —ms3,7

tPLLVTL PWR_EN low to VCC_AP PS and

VCC_SRAM supplies di sabled

constraint

0— —s—

tPLSL PWR_EN low to SYS_EN low delay — — 6 2 μs—

tROLSL nRESET_OUT low to SYS_ EN low

delay — — 123 μs4

tBFLBFH nBATT_FAULT low pulse width

constraint 100 — — μs

tLVTLVSL VCC_APPS and VCC_SRAM supplies

disabled to VCC_SYSEN disabled

constraint

0— —s2

tSLVSL SYS_EN low to VCC_SYSEN supplies

disabled constraint 0— —ns2,3

tVSLVML VCC _SYSEN supplies dis abl ed to

VCC_M VT supply disabled const r ai nt 0 — 100 ns 2

tEWLEWH EXT_W AKEUPx low to

EXT_WAKEUPx high constraint 5— —ns1

tEWHEWV EXT_WAKEUPx high to

EXT_WAKEUPx valid delay 5— —ns1

tWAKEDETECT Acknow ledge the ex ternal wake -u p

edge and t o begin the wake-up

sequence dela y

— — 150 μs4

tBFHSEH nBATT_FAULT high to SYS_EN high

delay — — 150 μs—

tPHLVTH PWR_EN high to VCC_APP S and

VCC_SRAM supplies stable 0 — PWR_DEL

time μs—

tSEHMVTH SYS_EN to VCC_ MVT supply stable 0 — SYS_DEL

time μs—

tSEHPH SYS_EN hig h to PWR _EN hig h dela y 182 — SYS_DEL

time + 18 3 μs—

tDEXIT Wakeup event to run mode delay — OSCC[VCX

OST] +

SYS_DEL +

PWR_DEL +

1ms

ms 6,7

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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8.3 Reset Timing

The processor asserts the nRESET_OUT pin in one of several different reset modes:

Hardware reset timing

Watchdog res e t timin g

GPIO reset timing (Can be configured by softw are)

The fo llowing sections provide the timing and specifications for the entry and exit of these modes.

8.3.1 Hardware Reset Timing

Hardware reset timing sequences assume stable power supplies at the assertion of nRESET. They

follow the ti mings indicated in Section 8.1, Powe r Up Timings. Refer to Figure 112.

8.3.2 Watchdog Reset Timing

Watchdog reset is an internally generated reset and therefore has no external-pin dependencies.

The nRESET_OUT pin is the only indicator of watchdog reset, and it stays asserted for tGRLGRH.

nBAUTT_FAULT and nRESET are assumed to be in their asserted states.

8.3.3 GPIO Reset Timing

GPIO reset is usually generated externally to a dedicated signal nGPIO_RESET. A GPIO reset can

also occur by setting the PMCR[SWGR ] register. Figure 115 shows the timing of GPIO reset.

tVMHVSH VCC_MVT supply enabl ed to

VCC_SYSEN supplies stable 0 — SYS_DEL

time -

tSEHVMH

μs2

tSHROH SYS_EN high to nRESET_OU T high

delay SYS_DEL

time + 213 — SYS_DEL

time + 21 4 μs4

tBFHBFL nBATT_FAULT hig h pu ls e wi dth

constraint 0— —s

NOTE:

1. EXT_WAKEUPx signal shown in th e di ag ram is f or falli ng edge detect. Howe ver, edg e det ection ca n be enabled f or

either ed ge or both edges. PW ER [ W ER x] and FWER[ WEFx] conf igur es which e dge (s ) is/ ar e us ed f or det ec tion .

2. VCC_SYSEN = All supplies exc ep t VCC_BBATT, VCC_APPS, VCC_ SRAM an d VCC_MVT.

3. To get the m ost power savings, Mar vell recom m ends turning off VCC_SYSEN as close to the S YS_EN asser tio n as

possible

4. S2/D3/C4 state nRESET_OUT Disable (PCFR[SL_ROD]) — Pr events the nRESE T_OUT pin from asser t ing upon

entry into S2/D3/C 4 or S3/ D 4/C 4 m odes.

5. The time inter val betwee n th e software Write to Cor e PW R M O D E r eg is te r (C P14 Register 7) to initiate a Low-power

mode and the wak e- detection w i ndow activation is 1μs (max).

6. The follow i ng ar e t he a ssumpti ons for exit times -

• There ar e no transfe rs pending wit hi n t he system t hat ca use exit sequence to stall

• There ar e no external t ra nsf er s pending th at cause exit s equence t o stall

• All coun ters that are user prog ra m m able that c an cause exit sequence to stall are set to m in i m um val ues: including

sys_del , pw r _del, lpm_d el and vctos t

• Exit times provid ed are typic al

7. T i me with PCFR[PWR_DEL] = 0b0 and no Power I2C com mands.

Table 47: S3/D4/C4 (Deep Sleep) Timing Specifications (Continued)

Symbol Description Min Typical Max Units Notes

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8.4 Power Consumption

Power consumption depends on the following:

Operating volt age

Oper ating frequency

Periph era ls ena ble d

Extern al sw it ch ing activity

Extern al loa d in g

Table 49 contains PXA32x Processor power-consumption information.

Table 50 contains PXA31x Processor power-consumption information.

Table 51 contains PXA30x Processor power-consumption information.

Figure 115:GPIO Reset Timing

tGRHROHtGRLROL

tGRLGRHtGRLGRH

PIO_RESET

RESET_OUT

nDF_CS2

Table 48: GPIO Reset Timing Specifications

Symbol Description Min Max Units Notes

tGRLGRH nGPIO_RESET pulse width constraint 100 — μs—

tGRLROL nGPIO_RESET low to nRESET_ OUT low delay 153 — μs1

tGRHROH nGPIO_RESET high to nRESET_OUT high

delay 92 — μs1

NOTE:

1. GPIO R eset Disable (PCFR[GP_ROD])—Enables/disables assertion of nRESET_OUT during GPIO reset.

Table 49: PXA32x Processor Power-Consumption Specifications1

Parameter Description Low

Power

Typical

(mW)

Low

Power

Maximum

(mW)

Standard

Typical

(mW)

Standard

Maximum

(mW)

Test

Conditions

Active Power (Turbo/Run/Switch/System Bus)

806 MHz Active Power (806/403/403/208) —— — 1950 1

208 MHz Active Power (—/208/208/104) 4855—5824—1

104 MHz Active Power (—/104/104/104) 3005—3604—1

Low Power Modes (S3/D4/C4, S2/D3/C4)

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

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S3/D4/C4 — — — 0.120 2

S2/D3/C4 — — — 0.800 3

Test Conditions:

1. VCC_APPS = 1.4V; VCC_SRAM = 1.4V; VCC_PLL = 1.8V; VCC_IO = 3.0V; VCC_MEM = 1.8V; Ta = 0C; 8 DMA

channel s w i th m em or y t o m em ory trans act i ons

2. VCC_BBATT = 3 .0V; VCC_APPS = 0V; VCC_SRAM = 0V; VCC_PLL=0; VCC_IO=0V; VCC_MEM=0V; Ta = 0C

3. VCC_BBATT = 3.0V; VCC_APPS = 0V; VCC_SRAM = 0V; VCC_PLL=0; VCC_IO=3V; VCC_M EM=1.8V; Ta =

0°C

4. VCC_APPS = 1.1V; VCC_SRAM = 1.1V; VCC_PLL = 1.8V; VCC_IO = 3.0V; VCC_MEM = 1.8V; Ta = 0C; 8 DMA

channel s w i th m em or y t o m em ory trans act i ons

5. VCC_APPS = 1.0V; VCC_SRAM = 1.0V; VCC_PLL = 1.8V; VCC_IO = 3.0V; VCC_MEM = 1.8V; Ta = 0C; 8 DMA

channel s w i th m em or y t o m em ory trans act i ons

NOTE:

1. Number s ar e re pr esentative of m ed i an pl us 1 sigma (85% of the u nits will be below these numb er s)

2. VCC_ IO is a combination of the VCC_IO1, VCC_DF, VCC_IO3, VCC_I04, VCC_CI, VCC_IO6, VCC_LCD,

VCC_MSL,VCC_USB, VCC_CARD1 , VCC_CA RD2 and VCC_TS voltage domains.

3. Only voltage d om ai ns listed fo r ea ch t est cond ition w ere used to me asure power cons um pt i on.

Table 49: PXA32x Processor Power-Consumption Specifications1 (Continued)

Parameter Description Low

Power

Typical

(mW)

Low

Power

Maximum

(mW)

Standard

Typical

(mW)

Standard

Maximum

(mW)

Test

Conditions

Table 50: PXA31x Processor Power-Consumption Specifications1

Parameter Description Ty p ic a l ( m W ) Maximum (mW) Test Conditions

Active Power (Turbo/Run/Switch/System Bus)

624 MHz Active Power (624/312/312/208) —1525 1

Low Power Modes (S3/D4/C4, S2/D3/C4, S0/D2/C2, S0/D1/C2)

S3/D4/C4 —0.120 2

S2/D3/C4 —0.800 3

S0/D2/C2 —0.975 4

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April 6, 2009 Released Page 199

S0/D1/C2 —0.975 5

Test Conditions:

1. VCC_APPS = 1.375 V; VCC_SRAM = 1.375V; VCC_PLL = 1. 8V; VCC_IO = 3.0V; VCC_MEM = 1.8V; Ta = 0C; 8 DMA

channels with memory to memory transactions

2. VCC_BBATT = 3 .0V; VCC_APPS = 0V; VCC_SRAM = 0V; VCC_PLL=0; VCC_ IO=0V; VCC_MEM=0V;Ta = 0C

3. VCC_BBATT = 3.0V; VCC_APPS = 0V; VCC_SRAM = 0V; VCC_PLL=0; VCC_IO=3V; VCC_M EM=1.8V; Ta = 0°C

4. VCC_BBATT = 3.0V; VCC_APPS = 1.4V; VCC_SRAM =1.4V; VCC_PLL = 1.8V; VCC_IO = 3.0V; VCC_MEM = 1. 8V; Ta

= 0C;

5. VCC_BBATT = 3.0V; VCC_APPS = 1.4V; VCC_SRAM =1.4V; VCC_PLL = 1.8V; VCC_IO = 3.0V; VCC_MEM = 1.8V; Ta

= 0C;

NOTE:

1. Number s ar e re pr esentative of m ed i an pl us 1 sigma (85% of the u nits will be below these numb er s)

2. VCC_ IO is a combination of the VCC_IO1, VCC_DF, VCC_IO3, VCC_CI, VCC_LCD, VCC_MSL,VCC_USB,

VCC_CARD1 and VCC_CARD2 volta ge domains.

3. Only voltage d om ai ns listed fo r ea ch t est conditi on w ere used to measure power cons um pt i on.

Table 50: PXA31x Processor Power-Consumption Specifications1 ( Co ntinued)

Parameter Description Ty p ic a l ( m W ) Maximum (mW) Test Conditions

Table 51: PXA30x Processor Power-Consumption Specifications1

Parameter Description Ty p ic a l ( m W ) Maximum (mW) Test Conditions

Active Power (Turbo/Run/Switch/System Bus)

624 MHz Active Power (624/312/312/208) —1525 1

Low Power Modes (S3/D4/C4, S2/D3/C4, S0/D2/C2, S0/D1/C2)

S3/D4/C4 —0.120 2

S2/D3/C4 —0.800 3

S0/D2/C2 —0.975 4

S0/D1/C2 —0.975 5

Test Conditions:

1. VCC_APPS = 1.375 V; VCC_SRAM = 1.375V; VCC_PLL = 1.8V; VCC_IO = .0V; VCC_MEM = 1.8V; Ta = 0C; 8 DM A

channel s w i th m em or y t o m em ory trans act i ons

2. VCC_BBATT = 3 .0V; VCC_APPS = 0V; VCC_SRAM = 0V; VCC_PLL=0; VCC_ IO=0V; VCC_MEM=0V;Ta = 0C

3. VCC_BBATT = 3.0V; VCC_APPS = 0V; VCC_SRAM = 0V; VCC_PLL=0; VCC_IO=3V; VCC_M EM=1.8V; Ta =

0°C

4. VCC_BBATT = 3.0V; VCC_APPS = 1.4V; VCC_SRAM =1.4V; VCC _PL L = 1. 8V; VCC_IO = 3.0V; VCC_MEM = 1. 8V;

Ta = 0C;

5. VCC_BBATT = 3.0V; VCC_APPS = 1.4V; VCC_SRAM =1.4V; VCC _PL L = 1. 8V; VCC_IO = 3.0V; VCC_MEM = 1. 8V;

Ta = 0C

NOTE:

1. Number s ar e re pr esentative of m ed i an pl us 1 sigma (85% of the u nits will be below these numb er s)

2. VCC_ IO is a combination of the VCC_IO1, VCC_DF, VCC_IO3, VCC_CI, VCC_LCD, VCC_MSL,VCC_USB,

VCC_CARD1, VCC_CAR D2 and VCC_ULPI voltage domains.

3. Only voltage d om ai ns listed fo r ea ch t est cond ition w ere used to me asure power cons um pt i on.

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

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APXA30x and PXA31x Programmer

Enabling

The PXA30x and PXA31x processors are high-performance, low-power microprocessors now

available with additi onal memory ch ips.

A.1 Introduction

This chapter describes how to prepare the PXA30x and PXA31x processors for flash memory

progra m ming, a nd how to reduce pr ogrammi ng time in a factory environment.

The PXA30x and PXA31x processors can be enabled to program flash using one of two different

methods. One method focuses on programming the PXA30x and PXA31x processor prior to

assembly of the system; the other focus e s on waiting until after the processors have been

assembled i n the system before progra mming. Both methods may be suitable, depe nding on the

design requirements. This chapter explains the trade-offs between dif ferent methods, thus helping

reduce time in a factory environment and/or reducing cost of develo pment.

The direct-access programming method requires minimum software development and takes less

time to program the flash memory. Direct-access programming requires that all other memory

devices along with the PXA30x and PXA31x processors be placed into high-z (by issuing a JTAG

high-z instruction) while program ming the NAND flash memory. All the pow e r domains must be

brought up to their required volt ages to prevent damage to the part. All other memories are placed

into high-z by applying power and ensuring the de-assertion of their chip-select signals.

The second method for programming flash within the PXA30x and PXA31x processors requires a

great er amount of code developm ent through the JTAG co ntroller. It is a slower programming

method but requires fewer pins. This method does not require any of the memory address , data, or

control signals to be pinned out. Flash loader code is loaded into the PXA30x and PXA31x

processors mini-instruction cache. The code is then executed and uses the PXA30x and PXA31x

processors m emory controller to program the flas h and de-select the other memory devices that

might be present within the package. This method is referred to as JTAG flash programm ing . All the

power domains on PXA30x and PXA31x processors must be brought up to their required voltages to

prevent damage to the part. All input signals not used must be driven to prevent excessive current

usage. Refer to the PXA30x and PXA31x Processor Developers Manual “Debug Interface” chapter

for JTAG-specific command information.

A.2 Device Configuration

The PXA30x and PXA31x processors stacked package uses a processor die combined with flash

memory die and/or SDRAM memory chips all packaged together . Currently available PXA30x and

PXA31x processors package configurations are as follows:

1 Gbits of NAND flash memory + 512 Mbits of low-power DDR (PXA30x processor)

2 Gbits of NAND flash memory + 1 Gbits of low-power DDR (PXA31x processor)

Note Device configurations are su bject to change before final production qualification.

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 202 April 6, 2009 Released

A.3 Procedure to Prepare PXA3xx (88AP3xx) Processor

Family for Programming Flash

The following steps describe the procedure to prepare the PXA30x processor or PXA31x processor

using either the direct-access programming method or the JTAG-flash programming method. To

prep are for direct-access programming, the internal memories other than flash are de-selected by

de-asserting the dedicated chip-select signals and the PXA30x processor or PXA31x processor

must be placed i nto high-Z using high-Z JTAG command.

To prepare for JTAG flash programming, bring the PXA30x processor or PXA31x processor out of

rese t. It is responsible for controlling all the memory signals and receiving the data to pro g ram the

flash devices through the JTAG contr o ller.

A.3.1 Sequence Required for Direct-Access Programming

Follow these steps to prepare the PXA30x processor or PXA31x processor for direct-access

progra mm ing. U se the p ower-o n t im ing spec if ica tio ns w it h re sp ect to ap pl yin g powe r to th e re qui red

domains.

1. If required , drive a ll memory chip selects (other than NAND flash) to their inactive state to

guar antee the other memories are not contending w ith the NA ND flash signals.

2. Drive EXT_WAKEUP0 pin low, NBATT_FAULT pin high, and NGPIO_RESET pin high.

3. Apply a hardware reset to the package by asserting nRESET and nTRST together.

4. Release reset by de-asserting nRESET and nTRST together.

5. Wait for nRESET_OUT to de-assert.

6. Issue the High-Z JTAG command (0x002) to place the PXA30x processor or PXA31x processor

signals into high-z state.

7. Begin prog ramming the flash devices in the package.

Figure 116:Diagram Showing Steps for Putting PXA30x Processor and PXA31x Processor into

High-Z

st-Logic-Reset

Run-Test/Idle

Select-DR-Scan

Select-IR-Scan

Capture-IR

Shift-HighZ Ins tru ction

Exit1-IR

Update-IR

Run-Test/Idle

TCK

nTRST

TMS

TDI

oll

er State

Versi on -

April 6, 2009 Released Page 203

A.3.2 Sequence Required for JTAG Flash Programming

Follow the steps below to prepare the PXA30x processor or PXA31x processor for JTAG flash

progra mm ing. U se the p ower-o n t im ing spec if ica tio ns w it h re sp ect to ap pl yin g powe r to th e re qui red

domains.

1. Drive EXT_WAKEUP0 pin low, NBATT_FAULT pin high, and NGPIO_RESET pin high.

2. Apply a hardware reset to the package by asserting nRESET and nTRST together.

3. Release JTAG reset by de-asserting nTRST.

4. Follow steps docum ent ed in Do wnlo ad Co de in the instru ction cac he seen in the P XA30x and

PXA31x Processor Developers Manual.

5. Download the flash loa der utility into the mini-instruction cache, start execution of the flash

loader utility.

6. 10 μs must elapse after nTRST is de-asserted befo re proceeding with any JTAG operation.

7. De-assert nRESET.

8. Wait for nRESET_OUT to de-assert.

9. Begin sending raw data through the JTAG port to program the flash devices in the package .

A.4 PXA30x Processor or PXA31x Processor:

Connections for Flash Programming

Table 53 describes the connections for existing PXA30x processor or PXA31x processor

configurations. Table 53 shows the mi nimum num ber of balls that must be c onnected to pr ogram the

NAND flash m emory intern al to the p ackage for eac h of t he two p rogramm ing m ethod s as described

in Section A.3.

For direct-access flash programming, the balls needed are determined based on the power signals

and control signals required for placing the PXA30x and PXA31x processors into a high-z state. For

the JTAG-flash programming method, the signals needed are only those that power up the PXA30x

and PXA31x processors such that the JTAG controller can program flash through the PXA30x and

PXA31x processors memory controllers.

Table 53 shows the con nections required for programming the NAND flash memory within the

PXA30x and PXA31x processors. The first two columns in Table 53 show which signals must be

accessed depending on the method used to program the NAND flash memory. Use the list in the

next table to decode the letter representing the die within the PXA30x and PXA31x processors.

Table 52: Abbreviations Used in Table 53

f ball required to program flash

b ball required by the PXA30x and PX A31x pr ocess ors

s ball required to deselect SDRAM

v voltage supply co nnection r equired

nc no conne ct

rfu reserved for future use

dnu do not use. do not phys ical l y co nnect to anyt hing

o optiona l (may not be required depend in g on system design)

shade Shading i ndi c at es ball is used differe nt ly betw een PXA30x proce ss or and PXA31x pr ocessor .

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 204 April 6, 2009 Released

Table 53: Required Balls for Programming the Package Flash Memory

Required Balls

(JTAG Flash Programming)

Required Balls

(Direct Access Programming)

Ball #

PXA30x processor Function

PXA31x processor Function

NAND Function

Signal Instruction

Power Contr ol Signals (VCC_BBATT)

b b D3 PWR_EN PWR_EN — use power-on timing specifications.

b b D4 SYS_EN SYS_EN —

b b D6 nRESET_IN nRESET_IN —

b b F9 nRESET_OUT nRESET_OUT —

b b B7 EXT_WAKEUP

0EXT_WAKEUP

0— P ull-down to gro und. This signals

internal pull-dow n is enabled during

power-on, hardware, global

watchdog and GP I O res ets and i s

disabled when the PCFR[PUDH] bit

is set.

b b C6 nBATT_FAULT nBATT_FAULT — Pull-up to VCC_BBATT.

b b E8 nGPIO_RESET nGPIO_RESET — Pull-up to VCC_BBATT. This signals

internal pull-up is en abl ed during

power-on, hardware, global

watchdog and GP I O res ets and i s

disabled when the PCFR[PUDH] bit

is set.

b b A7 PWR_CAP0 PWR_CAP0 — External 0.1 µF capacitor connected

between PWR_CAP0 and

PWR_C AP1. If a pol ari zed c ap acit or

is used, th e + plat e m ust be

connected to PWR_CAP1.

b b F8 PWR_CAP1 PWR_CAP1 —

b b C7 PWR_OUT PWR_OUT — External 0.1 µF capacitor connected

to ground.

Versi on -

April 6, 2009 Released Page 205

JTAG Interface (VCC_BBAT T)

b b A6 nTRST nTRST — JTAG interface.

b b C4 TCK TCK —

bb E3 TDI TDI —

b b D2 TDO TDO —

bb C3 TMS TMS —

Processor Clo ck Signals

b b A8 TXTAL_IN TXTAL_IN — Can be connected to an external

32.768 k H z cr ystal or to an ext ern al

clock so ur ce. N ot e: The maxim um

voltage leve l on TXTAL_IN i s 1. 0 V.

b b B8 TXTAL_OUT TXTAL_OUT — Can be connected to an external

32.768 k H z cr ystal or grounded

when an e xternal cloc k source is

connected to TXTAL_IN.

Processor Clo ck Signals

b b B9 PXTAL_IN PXTAL_IN — Mus t be connected t o a 13 MHz

crystal or ex ternal cl ock sourc e .

b b C9 PXTAL_OUT PXTAL_OUT — Must be con nected to a 13 MHz

crystal or left floati ng w hen using an

extern al cl ock sourc e.

TEST Signals

b b B11 TEST TEST — Reserve d fo r manufacturing test.

Must be gro unded fo r no rm a l

operation.

b b F11 TESTCLK TESTCLK — Reserved for manufacturing test.

Must be gro unded fo r no rm a l

operation.

Table 53: Required Balls for Programming the Package Flash Memory (Continued)

Required Balls

(JTAG Flash Programming)

Required Balls

(Direct Access Programming)

Ball #

PXA30x processor Function

PXA31x processor Function

NAND Function

Signal Instruction

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 206 April 6, 2009 Released

Data Flash Interface (VCC_DF)

f W3 DF_INT_RNB DF_INT_RNB R/B NAND Read/Busy. Must have an

external 10 Ko hm pull-up t o

VCC_DF.

f AA5 DF_IO0 DF_IO0 I/O<0:15

>NAND I/O interface.

f AA6 DF_IO1 DF_IO1

f W7 DF_IO2 DF_IO2

f Y8 DF_IO3 DF_IO3

f V10 DF_IO4 DF_IO4

f W13 DF_IO5 DF_IO5

f W12 DF_IO6 DF_IO6

f V11 DF_IO7 DF_IO7

f U8 DF_IO8 DF_IO8

f Y5 DF_IO9 DF_IO9

f Y6 DF_IO10 DF_IO10

f W8 DF_IO11 DF_IO11

f U15 DF_IO12 DF_IO12

f W10 DF_IO13 DF_IO13

f W11 DF_IO14 DF_IO14

f W15 DF_IO15 DF_IO15

f V7 DF_ALE_NWE DF_ALE_NWE ALE ALE - Address Latch Enable

Table 53: Required Balls for Programming the Package Flash Memory (Continued)

Required Balls

(JTAG Flash Programming)

Required Balls

(Direct Access Programming)

Ball #

PXA30x processor Function

PXA31x processor Function

NAND Function

Signal Instruction

Versi on -

April 6, 2009 Released Page 207

f V9 DF_NCS0 DF_NCS0 CE CE - Chip Enable.

Note: Ref er to in di vidual packag e

specifi cat io n s to det er mine wh ic h

chip enables to use for programming

NAND.

f U10 DF_NCS1 DF_NCS1

f W5 DF_NRE DF_NRE RE RE - Read Enable

f W4 DF_NWE DF_NWE WE WE - Write Enable

f V8 DF_CLE_NOE DF_CLE_N O E CLE CLE - Command Latch Enable

f U5 DF_NWP DF_NWP WP WP - Write Protect. When logic Low ,

pro vides a hardw are protection

against undesired modify (program /

erase) operations.

Must be connect ed to VC C _DF

when programming NAND.

No Connect Signals

rfu C1, N2, V2,

W2, U3, B4,

G4, L4, P4,

C5, P5, L8,

M8, D19,

AA19

RFU RFU — Reserved for Future Use. Tr eat as a

No Connect.

dnu W9 DNU DNU Do Not Use. Do not physically

connect to anything.

Power Supplies

Table 53: Required Balls for Programming the Package Flash Memory (Continued)

Required Balls

(JTAG Flash Programming)

Required Balls

(Direct Access Programming)

Ball #

PXA30x processor Function

PXA31x processor Function

NAND Function

Signal Instruction

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 208 April 6, 2009 Released

v v L5, N5,

AA7, AA9,

A10, H10,

P10, H11,

P11, H12,

P12, AA12,

A13, Y13,

K14, L14,

M14, A15,

N21

VCC_APPS VCC_A PPS — Apply 1.41 V

v v AA8, C18,

B19 VCC_SRAM VCC_SRAM —

v v C8 VCC_BBATT VCC_B BATT — Apply 3.3 V

v v D12, AA16 VCC_PLL VCC_PLL — Apply 1. 8 V

v v E4, J5, T5,

G9, U9,

G14, R14 ,

H15, J15,

N15

VCC_MVT VCC_MVT —

v v D9 VCC_OSC13M VCC_OSC13M —

v v D10 VCC_BG VCC_BG —

v v Y11 VCC_CARD1 VCC_CARD1 — Apply 3.3 V

v v AA14 VCC_CARD2 VCC_CARD2 —

v v E15, G10,

G15 VCC_IO1 VCC_IO1 —

v v T16 VCC_IO3 VCC_IO3 —

v v K16 , L1 6,

M16 VCC_LCD VCC_LCD —

v v G17 VCC_MSL VCC_MSL —

Table 53: Required Balls for Programming the Package Flash Memory (Continued)

Required Balls

(JTAG Flash Programming)

Required Balls

(Direct Access Programming)

Ball #

PXA30x processor Function

PXA31x processor Function

NAND Function

Signal Instruction

Versi on -

April 6, 2009 Released Page 209

v v B3 VCC_USB VCC _BIAS — Ap ply 3. 3 V for b ot h processors

v v P15, P20 VCC_CI VCC_C I — Ap ply 3.3 V

v v R16 RFU VCC_U LPI — Apply 1.8 V for PXA31x processor

v v D5, G5, V5,

G6, H6, J6,

K6, L6, M6,

N6, P6, R6,

T6, U6

VCC_M EM VCC_M EM — Appl y 1. 8 V.

v v G11, T9,

T10, T11,

T12, T13

VCC_DF VCC_DF VCC

(for

NAND)

Apply 1.8 V.

v v C2, F4, K5,

M5, R5, Y7,

H8, R8, T8,

A9, H9, P9,

B13, H13,

P13, AA13,

H14, J14,

N14, P14,

T14, B16,

A20, B20,

N20, A21,

B21

VSS VSS — Connect to ground.

v v D8 VSS_BBATT VSS_BBATT — Connect to ground.

v v C10 VSS_BG VSS_BG — Connect to ground.

v v Y12 VSS_CARD1 VSS_CARD1 — Connect to ground.

v v AA15 VSS_CARD2 VSS_CARD2 — Connect to ground.

v v P19 VSS_CI VSS_CI — Connect to ground.

Table 53: Required Balls for Programming the Package Flash Memory (Continued)

Required Balls

(JTAG Flash Programming)

Required Balls

(Direct Access Programming)

Ball #

PXA30x processor Function

PXA31x processor Function

NAND Function

Signal Instruction

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 210 April 6, 2009 Released

A.5 PXA30x Processor and PXA31x Processor

Processor Mechanical Drawings

Refer to Section 3 for the PXA30x and PXA31x processors mechanical drawings.

v v Y1, AA1,

Y2, AA2,

R9, R10,

R11, G12,

R12, R13

VSS_DF VSS_DF VSS

(for

NAND)

Connect to ground.

v v G13, F15 VSS_IO1 VSS_IO1 — Connect to ground.

vv T15, Y20,

AA20, Y21,

AA21

VSS_IO3 VSS_IO3 — Connect to ground.

v v K15 , L1 5,

M15 VSS_LCD VSS_LCD — Connect to ground.

v v F6, F7, G7,

H7, J7, K7,

L7, M7, N7,

P7, R7, T7,

VSS_MEM VSS_MEM — Connect to ground.

v v F17 VSS_MSL VSS_MSL — Connect to ground.

v v E9 VSS_OSC13M VSS_OSC13M — Connect to ground.

v v D7 VSS_OSC32K VSS_OSC32K — Connect to ground.

v v E11, E12,

W16 VSS_PLL VSS_PLL — Connect to ground.

v v A1, B1, A2,

B2 VSS_USB VSS — Connect to ground.

v v R15 RFU VSS_ULPI — Connect to ground for PXA31x

processor.

Table 53: Required Balls for Programming the Package Flash Memory (Continued)

Required Balls

(JTAG Flash Programming)

Required Balls

(Direct Access Programming)

Ball #

PXA30x processor Function

PXA31x processor Function

NAND Function

Signal Instruction

Versi on -

April 6, 2009 Re leased Page 211

A.6 PXA30x Processor and PXA31x Processor

Processor Ballouts

Refer to Section 4 for the PXA30x and PXA31x processors ballouts.

PXA3xx (88AP3xx) Processor Family

Electrical, Mechanical, and Thermal Functional Specification

Doc. No. MV-S105156-00 Rev. 2.0

Page 212 April 6, 2009 Released

THIS PAGE INTENTIONALLY LEFT BLANK

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