5962-8755601SA - NATIONAL SEMICONDUCTOR

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544E – OCTOBER 1995 – REVISED OCT OBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.5-V to 5.5-V VCC Operation

Inputs Accept Voltages to 5.5 V

Max tpd of 10 ns at 5 V

Inputs Are TTL-Voltage Compatible

description/ordering information

These 8-bit latches feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

The eight latches are D-type transparent latches.

When the latch-enable (LE) input is high, the Q

outputs follow the data (D) inputs. When LE is

taken low, the Q outputs are latched at the logic

levels set up at the D inputs.

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

increased drive provide the capability to drive bus

lines in bus-organized systems without need for

interface or pullup components.

OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered

while the outputs are in the high-impedance state.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TAPACKAGE†ORDERABLE

PART NUMBER TOP-SIDE

MARKING

PDIP – N Tube SN74ACT373N SN74ACT373N

SOIC DW

Tube SN74ACT373DW

ACT373

40°Cto85°C

SOIC

–

Tape and reel SN74ACT373DWR

ACT373

–

40°C

85°C

SOP – NS Tape and reel SN74ACT373NSR ACT373

SSOP – DB Tape and reel SN74ACT373DBR AD373

TSSOP – PW Tape and reel SN74ACT373PWR AD373

CDIP – J Tube SNJ54ACT373J SNJ54ACT373J

–55°C to 125°CCFP – W Tube SNJ54ACT373W SNJ54ACT373W

LCCC – FK Tube SNJ54ACT373FK SNJ54ACT373FK

†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

VCC

SN54ACT373 ...J OR W PACKAGE

SN74ACT373 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

5D 8Q

GND

LE VCC

SN54ACT373 . . . FK PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544E – OCTOBER 1995 – REVISED OCT OBER 2002

2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each latch)

INPUTS OUTPUT

OE LE D Q

L H H H

LHL L

LLX Q

H X X Z

logic diagram (positive logic)

1D 1Q

To Seven Other Channels

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544E – OCTOBER 1995 – REVISED OCT OBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

SN54ACT373 SN74ACT373

UNIT

MIN MAX MIN MAX

UNIT

VCC Supply voltage 4.5 5.5 4.5 5.5 V

VIH High-level input voltage 2 2 V

VIL Low-level input voltage 0.8 0.8 V

VIInput voltage 0 VCC 0 VCC V

VOOutput voltage 0 VCC 0 VCC V

IOH High-level output current –24 –24 mA

IOL Low-level output current 24 24 mA

∆t/∆vInput transition rise or fall rate 8 8 ns/V

TAOperating free-air temperature –55 125 –40 85 °C

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

TA = 25°C SN54ACT373 SN74ACT373

UNIT

PARAMETER

TEST

CONDITIONS

CC MIN TYP MAX MIN MAX MIN MAX

UNIT

IOH = 50 µA

4.5 V 4.4 4.49 4.4 4.4

OH = –

5.5 V 5.4 5.49 5.4 5.4

VOH

IOH = 24 mA

4.5 V 3.86 3.7 3.76

OH = –

5.5 V 4.86 4.7 4.76

IOH = –50 mA†5.5 V 3.85

IOH = –75 mA†5.5 V 3.85

IOL =50µA

4.5 V 0.1 0.1 0.1

OL =

5.5 V 0.1 0.1 0.1

VOL

IOL =24mA

4.5 V 0.36 0.44 0.44

OL =

5.5 V 0.36 0.44 0.44

IOL = 50 mA†5.5 V 1.65

IOL = 75 mA†5.5 V 1.65

IOZ VO = VCC or GND 5.5 V ±0.25 ±5±2.5 µA

IIVI = VCC or GND 5.5 V ±0.1 ±1±1µA

ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA

∆ICC‡One input at 3.4 V,

Other inputs at GND or VCC 5.5 V 0.6 1.5 1.5 mA

CiVI = VCC or GND 5 V 4.5 pF

†Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.

‡This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

timing requirements over recommended operating free-air temperature range, VCC = 5 V ±0.5 V

(unless otherwise noted) (see Figure 1)

TA = 25°C SN54ACT373 SN74ACT373

UNIT

MIN MAX MIN MAX MIN MAX

UNIT

twPulse duration, LE high 7 8.5 8 ns

tsu Setup time, data before LE↓7 8.5 8 ns

thHold time, data after LE↓0 1 1 ns

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544E – OCTOBER 1995 – REVISED OCT OBER 2002

4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range,

VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)

PARAMETER

FROM TO TA = 25°C SN54ACT373 SN74ACT373

UNIT

PARAMETER

(INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX

UNIT

tPLH

2.5 8.5 10 1.5 12.5 1.5 11.5

tPHL

2 8 10 1.5 12.5 1.5 11.5

tPLH

2.5 8.5 11 1.5 12.5 2 11.5

tPHL

2 8 10 1.5 11.5 1.5 11.5

tPZH

2 8 9.5 1.5 11.5 1.5 10.5

tPZL

2 7.5 9 1.5 11 1.5 10.5

tPHZ

2.5 9 11 1.5 14 2.5 12.5

tPLZ

1.5 7.5 8.5 1.5 11 1 10

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

Cpd Power dissipation capacitance CL = 50 pF, f = 1 MHz 40 pF

SN54ACT373, SN74ACT373

OCTAL D-TYPE TRANSPARENT LATCHES

WITH 3-STATE OUTPUTS

SCAS544E – OCTOBER 1995 – REVISED OCT OBER 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

50% VCC

3 V

0 V

tsu

VOLTAGE WAVEFORMS

Data Input

tPLH tPHL

VOH

VOL

3 V

0 V

Input

Output

Timing Input

50% VCC

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1 2 × VCC

500 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × VCC

(see Note B)

Output

W aveform 2

S1 at Open

(see Note B)

VOL

VOH

tPZL

tPZH

tPLZ

tPHZ

≈VCC

0 V

50% VCC VOL + 0.3 V

50% VCC ≈0 V

Open

VOLTAGE WAVEFORMS

tPLH/tPHL

tPLZ/tPZL

tPHZ/tPZH

Open

2 × VCC

Open

TEST S1

3 V

0 V

VOLTAGE WAVEFORMS

Input

VOH – 0.3 V

3 V

NOTES: A. CL includes probe and jig capacitance.

B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.

D. The outputs are measured one at a time with one input transition per measurement.

VOLTAGE WAVEFORMS

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

Figure 1. Load Circuit and Voltage Waveforms

PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-87556012A ACTIVE LCCC FK 20 1 Non-RoHS

& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-

87556012A

SNJ54ACT

373FK

5962-8755601RA ACTIVE CDIP J 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8755601RA

SNJ54ACT373J

5962-8755601SA ACTIVE CFP W 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8755601SA

SNJ54ACT373W

5962-8755601VRA ACTIVE CDIP J 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8755601VR

SNV54ACT373J

SN74ACT373DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD373

SN74ACT373DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT373

SN74ACT373DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT373

SN74ACT373N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74ACT373N

SN74ACT373NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ACT373

SN74ACT373PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD373

SN74ACT373PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AD373

SNJ54ACT373FK ACTIVE LCCC FK 20 1 Non-RoHS

& Green POST-PLATE N / A for Pkg Type -55 to 125 5962-

87556012A

SNJ54ACT

373FK

SNJ54ACT373J ACTIVE CDIP J 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8755601RA

SNJ54ACT373J

SNJ54ACT373W ACTIVE CFP W 20 1 Non-RoHS

& Green SNPB N / A for Pkg Type -55 to 125 5962-8755601SA

SNJ54ACT373W

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2021

Addendum-Page 2

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54ACT373, SN54ACT373-SP, SN74ACT373 :

•Catalog: SN74ACT373, SN54ACT373

•Enhanced Product: SN74ACT373-EP, SN74ACT373-EP

•Military: SN54ACT373

•Space: SN54ACT373-SP

NOTE: Qualified Version Definitions:

PACKAGE OPTION ADDENDUM

www.ti.com 4-Feb-2021

Addendum-Page 3

•Catalog - TI's standard catalog product

•Enhanced Product - Supports Defense, Aerospace and Medical Applications

•Military - QML certified for Military and Defense Applications

•Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

SN74ACT373DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1

SN74ACT373DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

SN74ACT373NSR SO NS 20 2000 330.0 24.4 8.4 13.0 2.5 12.0 24.0 Q1

SN74ACT373PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74ACT373DBR SSOP DB 20 2000 853.0 449.0 35.0

SN74ACT373DWR SOIC DW 20 2000 367.0 367.0 45.0

SN74ACT373NSR SO NS 20 2000 367.0 367.0 45.0

SN74ACT373PWR TSSOP PW 20 2000 853.0 449.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

18X 0.65

5.85

20X 0.38

0.22

8.2

7.4 TYP

SEATING

PLANE

0.05 MIN

0.25

GAGE PLANE

0 -8

2 MAX

B5.6

5.0

NOTE 4

7.5

6.9

NOTE 3

0.95

0.55

(0.15) TYP

SSOP - 2 mm max heightDB0020A

SMALL OUTLINE PACKAGE

4214851/B 08/2019

10 11

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-150.

A 15

DETAIL A

TYPICAL

SCALE 2.000

www.ti.com

EXAMPLE BOARD LAYOUT

0.07 MAX

ALL AROUND 0.07 MIN

ALL AROUND

20X (1.85)

20X (0.45)

18X (0.65)

(7)

(R0.05) TYP

SSOP - 2 mm max heightDB0020A

SMALL OUTLINE PACKAGE

4214851/B 08/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

10 11

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

20X (1.85)

20X (0.45)

18X (0.65)

(7)

(R0.05) TYP

SSOP - 2 mm max heightDB0020A

SMALL OUTLINE PACKAGE

4214851/B 08/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

10 11

www.ti.com

PACKAGE OUTLINE

TYP

10.63

9.97

2.65 MAX

18X 1.27

20X 0.51

0.31

11.43

TYP

0.33

0.10

0 - 8

0.3

0.1

0.25

GAGE PLANE

1.27

0.40

NOTE 3

13.0

12.6

B7.6

7.4

4220724/A 05/2016

SOIC - 2.65 mm max heightDW0020A

SOIC

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.

5. Reference JEDEC registration MS-013.

120

0.25 C A B

PIN 1 ID

AREA

NOTE 4

SEATING PLANE

0.1 C

SEE DETAIL A

DETAIL A

TYPICAL

SCALE 1.200

www.ti.com

EXAMPLE BOARD LAYOUT

(9.3)

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

20X (2)

20X (0.6)

18X (1.27)

(R )

TYP

0.05

4220724/A 05/2016

SOIC - 2.65 mm max heightDW0020A

SOIC

SYMM

LAND PATTERN EXAMPLE

SCALE:6X

10 11

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(9.3)

18X (1.27)

20X (0.6)

20X (2)

4220724/A 05/2016

SOIC - 2.65 mm max heightDW0020A

SOIC

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SYMM

10 11

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE:6X

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE

DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”

AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY

IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD

PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate

TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable

standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you

permission to use these resources only for development of an application that uses the TI products described in the resource. Other

reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party

intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,

costs, losses, and liabilities arising out of your use of these resources.

TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available either

on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s

applicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265