SPC5743PGK1AMMM9 - FREESCALE

1.35V DDR3L SDRAM SODIMM

MT8KTF12864HZ – 1GB

MT8KTF25664HZ – 2GB

MT8KTF51264HZ – 4GB

Features

• DDR3L functionality and operations supported as

defined in the component data sheet

• 204-pin, small-outline dual in-line memory module

(SODIMM)

• Fast data transfer rates: PC3-14900, PC3-12800, or

PC3-10600

• 1GB (128 Meg x 64), 2GB (256 Meg x 64), 4GB (512

Meg x 64)

• VDD = 1.35V (1.283–1.45V)

• VDD = 1.5V (1.425–1.575V)

• Backward compatible with standard 1.5V (±0.075V)

DDR3 systems

• VDDSPD = 3.0–3.6V

• Nominal and dynamic on-die termination (ODT) for

data, strobe, and mask signals

• Single rank

• Fixed burst chop (BC) of 4 and burst length (BL) of 8

via the mode register set (MRS)

• On-board I2C serial presence-detect (SPD) EEPROM

• Gold edge contacts

• Halogen-free

• Fly-by topology

• Terminated control, command, and address bus

Figure 1: 204-Pin SODIMM (MO-268 R/C B2, B4)

Module height: 30mm (1.181in)

Options Marking

• Operating temperature

– Commercial (0°C ≤ TA ≤ +70°C) None

• Package

– 204-pin DIMM (halogen-free) Z

• Frequency/CAS latency

– 1.07ns @ CL = 13 (DDR3-1866) -1G9

– 1.25ns @ CL = 11 (DDR3-1600) -1G6

– 1.5ns @ CL = 9 (DDR3-1333) -1G4

Table 1: Key Timing Parameters

Speed

Grade

Industry

Nomenclature

Data Rate (MT/s)

tRCD

(ns)

tRP

(ns)

tRC

(ns)

CL =

10 CL = 9 CL = 8 CL = 7 CL = 6 CL = 5

-1G9 PC3-14900 1866 1600 1333 1333 1066 1066 800 667 13.125 13.125 47.125

-1G6 PC3-12800 – 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125

-1G4 PC3-10600 – – 1333 1333 1066 1066 800 667 13.125 13.125 49.125

-1G1 PC3-8500 – – – – 1066 1066 800 667 13.125 13.125 50.625

-1G0 PC3-8500 – – – – 1066 – 800 667 15 15 52.5

-80B PC3-6400 – – – – – – 800 667 15 15 52.5

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Features

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Products and specifications discussed herein are subject to change by Micron without notice.

Table 2: Addressing

Parameter 1GB 2GB 4GB

Refresh count 8K 8K 8K

Row address 16K A[13:0] 32K A[14:0] 64K A[15:0]

Device bank address 8 BA[2:0] 8 BA[2:0] 8 BA[2:0]

Device configuration 1Gb (128 Meg x 8) 2Gb (256 Meg x 8) 4Gb (512 Meg x 8)

Column address 1K A[9:0] 1K A[9:0] 1K A[9:0]

Module rank address 1 S0# 1 S0# 1 S0#

Table 3: Part Numbers and Timing Parameters – 1GB Modules

Base device: MT41K128M8,1 1Gb 1.35V DDR3L SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT8KTF12864HZ-1G6__ 1GB 128 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT8KTF12864HZ-1G4__ 1GB 128 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

Table 4: Part Numbers and Timing Parameters – 2GB Modules

Base device: MT41K256M8,1 2Gb 1.35V DDR3L SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT8KTF25664HZ-1G6__ 2GB 256 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT8KTF25664HZ-1G4__ 2GB 256 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

Table 5: Part Numbers and Timing Parameters – 4GB Modules

Base device: MT41K512M8,1 4Gb 1.35V DDR3L SDRAM

Part Number2

Module

Density Configuration

Module

Bandwidth

Memory Clock/

Data Rate

Clock Cycles

(CL-tRCD-tRP)

MT8KTF51264HZ-1G9__ 4GB 512 Meg x 64 14.9 GB/s 1.07ns/1866 MT/s 13-13-13

MT8KTF51264HZ-1G6__ 4GB 512 Meg x 64 12.8 GB/s 1.25ns/1600 MT/s 11-11-11

MT8KTF51264HZ-1G4__ 4GB 512 Meg x 64 10.6 GB/s 1.5ns/1333 MT/s 9-9-9

Notes: 1. The data sheet for the base device can be found on Micron’s web site.

2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.

Consult factory for current revision codes. Example: MT8KSF51264HZ-1G9P1.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Features

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Pin Assignments

Table 6: Pin Assignments

204-Pin DDR3 SODIMM Front 204-Pin DDR3 SODIMM Back

Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol

1 VREFDQ 53 DQ19 105 VDD 157 DQ42 2 VSS 54 VSS 106 VDD 158 DQ46

3 VSS 55 VSS 107 A10 159 DQ43 4 DQ4 56 DQ28 108 BA1 160 DQ47

5 DQ0 57 DQ24 109 BA0 161 VSS 6 DQ5 58 DQ29 110 RAS# 162 VSS

7 DQ1 59 DQ25 111 VDD 163 DQ48 8 VSS 60 VSS 112 VDD 164 DQ52

9 VSS 61 VSS 113 WE# 165 DQ49 10 DQS0# 62 DQ3# 114 S0# 166 DQ53

11 DM0 63 DM3 115 CAS# 167 VSS 12 DQS0 64 DQ3 116 ODT0 168 VSS

13 VSS 65 VSS 117 VDD 169 DQS6# 14 VSS 66 VSS 118 VDD 170 DM6

15 DQ2 67 DQ26 119 A13 171 DQS6 16 DQ6 68 DQ30 120 NC 172 VSS

17 DQ3 69 DQ27 121 NC 173 VSS 18 DQ7 70 DQ31 122 NC 174 DQ54

19 VSS 71 VSS 123 VDD 175 DQ50 20 VSS 72 VSS 124 VDD 176 DQ55

21 DQ8 73 CKE0 125 NC 177 DQ51 22 DQ12 74 NC 126 VREFCA 178 VSS

23 DQ9 75 VDD 127 VSS 179 VSS 24 DQ13 76 VDD 128 VSS 180 DQ60

25 VSS 77 NC 129 DQ32 181 DQ56 26 VSS 78 NF/A151130 DQ36 182 DQ61

27 DQS1# 79 BA2 131 DQ33 183 DQ57 28 DM1 80 NF/A142132 DQ37 184 VSS

29 DQS1 81 VDD 133 VSS 185 VSS 30 RESET# 82 VDD 134 VSS 186 DQS7#

31 VSS 83 A12 135 DQS4# 187 DM7 32 VSS 84 A11 136 DM4 188 DQS7

33 DQ10 85 A9 137 DQS4 189 VSS 34 DQ14 86 A7 138 VSS 190 VSS

35 DQ11 87 VDD 139 VSS 191 DQ58 36 DQ15 88 VDD 140 DQ38 192 DQ62

37 VSS 89 A8 141 DQ34 193 DQ59 38 VSS 90 A6 142 DQ39 194 DQ63

39 DQ16 91 A5 143 DQ35 195 VSS 40 DQ20 92 A4 144 VSS 196 VSS

41 DQ17 93 VDD 145 VSS 197 SA0 42 DQ21 94 VDD 146 DQ44 198 NF

43 VSS 95 A3 147 DQ40 199 VDDSPD 44 VSS 96 A2 148 DQ45 200 SDA

45 DQS2# 97 A1 149 DQ41 201 SA1 46 DM2 98 A0 150 VSS 202 SCL

47 DQS2 99 VDD 151 VSS 203 VTT 48 VSS 100 VDD 152 DQS5# 204 VTT

49 VSS 101 CK0 153 DM5 – – 50 DQ22 102 CK1 154 DQS5 – –

51 DQ18 103 CK0# 155 VSS – – 52 DQ23 104 CK1# 156 VSS – –

Notes: 1. Pin 78 is NF for 1GB and 2GB; A15 for 4GB.

2. Pin 80 is NF for 1GB; A14 for 2GB and 4GB.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Pin Assignments

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Pin Descriptions

The pin description table below is a comprehensive list of all possible pins for all DDR3

modules. All pins listed may not be supported on this module. See Pin Assignments for

information specific to this module.

Table 7: Pin Descriptions

Symbol Type Description

Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column ad-

dress and auto precharge bit (A10) for READ/WRITE commands, to select one location

out of the memory array in the respective bank. A10 sampled during a PRECHARGE

command determines whether the PRECHARGE applies to one bank (A10 LOW, bank

selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code

during a LOAD MODE command. See the Pin Assignments table for density-specific ad-

dressing information.

BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or

PRECHARGE command is being applied. BA define which mode register (MR0, MR1,

MR2, or MR3) is loaded during the LOAD MODE command.

CKx,

CKx#

Input Clock: Differential clock inputs. All control, command, and address input signals are

sampled on the crossing of the positive edge of CK and the negative edge of CK#.

CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circui-

try and clocks on the DRAM.

DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data

is masked when DM is sampled HIGH, along with that input data, during a write ac-

cess. Although DM pins are input-only, DM loading is designed to match that of the

DQ and DQS pins.

ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termi-

nation resistance internal to the DDR3 SDRAM. When enabled in normal operation,

ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input

will be ignored if disabled via the LOAD MODE command.

Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.

RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being

entered.

RESET# Input

(LVCMOS)

Reset: RESET# is an active LOW asychronous input that is connected to each DRAM

and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitial-

ized as though a normal power-up was executed.

Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command

decoder.

SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM ad-

dress range on the I2C bus.

SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communi-

cation to and from the temperature sensor/SPD EEPROM on the I2C bus.

CBx I/O Check bits: Used for system error detection and correction.

DQx I/O Data input/output: Bidirectional data bus.

DQSx,

DQSx#

I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with

read data; input with write data; center-aligned with write data.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Pin Descriptions

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Table 7: Pin Descriptions (Continued)

Symbol Type Description

SDA I/O Serial data: Used to transfer addresses and data into and out of the temperature sen-

sor/SPD EEPROM on the I2C bus.

TDQSx,

TDQSx#

Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD

MODE command to the extended mode register (EMR). When TDQS is enabled, DM is

disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are

no function.

Err_Out# Output

(open drain)

Parity error output: Parity error found on the command and address bus.

EVENT# Output

(open drain)

Temperature event: The EVENT# pin is asserted by the temperature sensor when crit-

ical temperature thresholds have been exceeded.

VDD Supply Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The

component VDD and VDDQ are connected to the module VDD.

VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.

VREFCA Supply Reference voltage: Control, command, and address VDD/2.

VREFDQ Supply Reference voltage: DQ, DM VDD/2.

VSS Supply Ground.

VTT Supply Termination voltage: Used for control, command, and address VDD/2.

NC – No connect: These pins are not connected on the module.

NF – No function: These pins are connected within the module, but provide no functional-

ity.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Pin Descriptions

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DQ Maps

Table 8: Component-to-Module DQ Map, R/C B2 (PCB 1092)

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U1 0 2 15 U2 0 22 50

1 1 7 1 17 41

2 6 16 2 18 51

3 5 6 3 21 42

4 7 18 4 23 52

5 0 5 5 16 39

6 3 17 6 19 53

7 4 4 7 20 40

U3 0 34 141 U4 0 50 175

1 36 130 1 53 166

2 38 140 2 54 174

3 33 131 3 49 165

4 35 143 4 55 176

5 32 129 5 48 163

6 39 142 6 51 177

7 37 132 7 52 164

U6 0 61 182 U7 0 45 148

1 62 192 1 42 157

2 57 183 2 44 146

3 58 191 3 46 158

4 60 180 4 40 147

5 59 193 5 47 160

6 56 181 6 41 149

7 63 194 7 43 159

U8 0 29 58 U9 0 9 23

1 26 67 1 10 33

2 25 59 2 13 24

3 31 70 3 11 35

4 24 57 4 12 22

5 30 68 5 15 36

6 28 56 6 8 21

7 27 69 7 14 34

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

DQ Maps

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Table 9: Component-to-Module DQ Map, R/C B4 (PCB 1348)

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

Component

Reference

Number

Component

DQ Module DQ

Module Pin

Number

U1 0 2 13 U2 0 22 48

1 1 7 1 17 39

2 6 16 2 18 49

3 5 6 3 21 42

4 7 18 4 23 50

5 0 5 5 16 37

6 3 15 6 19 51

7 4 4 7 20 40

U3 0 34 145 U4 0 50 177

1 36 134 1 53 168

2 38 142 2 54 174

3 33 135 3 49 167

4 35 147 4 55 176

5 32 133 5 48 165

6 39 144 6 51 179

7 37 136 7 52 166

U6 0 61 182 U7 0 45 150

1 62 192 1 42 159

2 57 185 2 44 148

3 58 191 3 46 160

4 60 180 4 40 151

5 59 193 5 47 162

6 56 183 6 41 153

7 63 194 7 43 161

U8 0 29 56 U9 0 9 21

1 26 63 1 10 31

2 25 57 2 13 24

3 31 68 3 11 33

4 24 55 4 12 22

5 30 66 5 15 36

6 28 54 6 8 19

7 27 65 7 14 34

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

DQ Maps

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Functional Block Diagram

Figure 2: Functional Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DM CS# DQS DQS#

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM CS# DQS DQS#

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DM CS# DQS DQS#

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DM CS# DQS DQS#

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DM CS# DQS DQS#

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DM CS# DQS DQS#

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DM CS# DQS DQS#

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM CS# DQS DQS#

DQS0#

DQS0

DM0

S0#

DQS1#

DQS1

DM1

DQS2#

DQS2

DM2

DQS3#

DQS3

DM3

DQS4#

DQS4

DM4

DQS5#

DQS5

DM5

DQS6#

DQS6

DM6

DQS7#

DQS7

DM7

VSS

SPD EEPROM

A1 A2

SA0VSS VSS

SA1

SDA

SCL

BA[2:0]

A[15/14/13:0]

RAS#

CAS#

WE#

CKE0

ODT0

RESET#

BA[2:0]: DDR3 SDRAM

A[15/14/13:0]: DDR3 SDRAM

RAS#: DDR3 SDRAM

CAS#: DDR3 SDRAM

WE#: DDR3 SDRAM

CKE0: DDR3 SDRAM

ODT0: DDR3 SDRAM

RESET#: DDR3 SDRAM

DDR3 SDRAM x 8

CK0

CK0#

CK1

CK1#

VREFCA

VSS

DDR3 SDRAM

VDD

Control, command,

and address termination

VDDSPD SPD EEPROM

VTT

DDR3 SDRAM

VREFDQ

Clock, control, command, and address line terminations:

CKE0, A[15/14/13:0],

RAS#, CAS#, WE#,

S0#, ODT0, BA[2:0]

DDR3

SDRAM

VTT

CK#

DDR3

SDRAM

VDD

Note: 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor

that is tied to ground. It is used for the calibration of the component’s ODT and output

driver.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Functional Block Diagram

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General Description

DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-

ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-

ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-

tially an 8n-prefetch architecture with an interface designed to transfer two data words

per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-

ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-

nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers

at the I/O pins.

DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK

and CK# to capture commands, addresses, and control signals. Differential clocks and

data strobes ensure exceptional noise immunity for these signals and provide precise

crossing points to capture input signals.

Fly-By Topology

DDR3 modules use faster clock speeds than earlier DDR technologies, making signal

quality more important than ever. For improved signal quality, the clock, control, com-

mand, and address buses have been routed in a fly-by topology, where each clock, con-

trol, command, and address pin on each DRAM is connected to a single trace and ter-

minated (rather than a tree structure, where the termination is off the module near the

connector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-

nals can be easily accounted for by using the write-leveling feature of DDR3.

Serial Presence-Detect EEPROM Operation

DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a

256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with

JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM

Modules." These bytes identify module-specific timing parameters, configuration infor-

mation, and physical attributes. The remaining 128 bytes of storage are available for use

by the customer. System READ/WRITE operations between the master (system logic)

and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL

(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to VSS, per-

manently disabling hardware write protection. For further information refer to Micron

technical note TN-04-42, "Memory Module Serial Presence-Detect."

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

General Description

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Electrical Specifications

Stresses greater than those listed may cause permanent damage to the module. This is a

stress rating only, and functional operation of the module at these or any other condi-

tions outside those indicated in each device's data sheet is not implied. Exposure to ab-

solute maximum rating conditions for extended periods may adversely affect reliability.

Table 10: Absolute Maximum Ratings

Symbol Parameter Min Max Units

VDD VDD supply voltage relative to VSS –0.4 1.975 V

VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V

Table 11: Operating Conditions

Symbol Parameter Min Nom Max Units Notes

VDD VDD supply voltage 1.283 1.35 1.45 V

1.425 1.5 1.575 V 1

VREFCA(DC) Input reference voltage command/address bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V

VREFDQ(DC) I/O reference voltage DQ bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V

IVTT Termination reference current from VTT –600 – 600 mA

VTT Termination reference voltage (DC) – command/

address bus

0.49 × VDD -

20mV

0.5 × VDD 0.51 × VDD +

20mV

V 2

IIInput leakage current; Any input

0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN

≤ 0.95V (All other pins not under

test = 0V)

Address inputs,

RAS#, CAS#,

WE#, S#, CKE,

ODT, BA, CK,

CK#

–16 0 16 µA

DM –2 0 2

IOZ Output leakage current; 0V ≤

VOUT ≤ VDD; DQ and ODT are disa-

bled; ODT is HIGH

DQ, DQS, DQS# –5 0 5 µA

IVREF VREF supply leakage current; VREFDQ = VDD/2 or

VREFCA = VDD/2 (All other pins not under test = 0V)

–8 0 8 µA

TAModule ambient operating temperature 0 – 70 °C 3, 4

TCDDR3 SDRAM component case operating tempera-

ture

0 – 95 °C 3, 4, 5

Notes: 1. Module is backward-compatible with 1.5V operation. Refer to device specification for

details and operation guidance.

2. VTT termination voltage in excess of the stated limit will adversely affect the command

and address signals’ voltage margin and will reduce timing margins.

3. TA and TC are simultaneous requirements.

4. For further information, refer to technical note TN-00-08: “Thermal Applications,”

available on Micron’s web site.

5. The refresh rate is required to double when 85°C < TC ≤ 95°C.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Electrical Specifications

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DRAM Operating Conditions

Recommended AC operating conditions are given in the DDR3 component data sheets.

Component specifications are available at micron.com. Module speed grades correlate

with component speed grades, as shown below.

Table 12: Module and Component Speed Grades

DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades

Module Speed Grade Component Speed Grade

-2G1 -093

-1G9 -107

-1G6 -125

-1G4 -15E

-1G1 -187E

-1G0 -187

-80C -25E

-80B -25

Design Considerations

Simulations

Micron memory modules are designed to optimize signal integrity through carefully de-

signed terminations, controlled board impedances, routing topologies, trace length

matching, and decoupling. However, good signal integrity starts at the system level.

Micron encourages designers to simulate the signal characteristics of the system's

memory bus to ensure adequate signal integrity of the entire memory system.

Power

Operating voltages are specified at the DRAM, not at the edge connector of the module.

Designers must account for any system voltage drops at anticipated power levels to en-

sure the required supply voltage is maintained.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

DRAM Operating Conditions

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IDD Specifications

Table 13: DDR3 IDD Specifications and Conditions – 1GB (Die Revision J)

Values are for the MT41K128M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 1Gb

(128Meg x 8) component data sheet

Parameter Symbol 1600 1333 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 272 264 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 360 344 mA

Precharge power-down current: Slow exit IDD2P0 96 96 mA

Precharge power-down current: Fast exit IDD2P1 96 96 mA

Precharge quiet standby current IDD2Q 120 120 mA

Precharge standby current IDD2N 136 136 mA

Precharge standby ODT current IDD2NT 200 192 mA

Active power-down current IDD3P 112 112 mA

Active standby current IDD3N 192 184 mA

Burst read operating current IDD4R 664 576 mA

Burst write operating current IDD4W 704 616 mA

Refresh current IDD5 1280 1240 mA

Self refresh temperature current: MAX TC = 85°C IDD6 96 96 mA

Self refresh temperature current (SRT-enabled): MAX TC = 95°C IDD6ET 112 112 mA

All banks interleaved read current IDD7 1192 1152 mA

Reset current IDD8 112 112 mA

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

IDD Specifications

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Table 14: DDR3 IDD Specifications and Conditions – 2GB (Die Revision K)

Values are for the MT41K256M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 2Gb

(256 Meg x 8) component data sheet

Parameter Symbol 1600 1333 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 312 304 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 416 400 mA

Precharge power-down current: Slow exit IDD2P0 96 96 mA

Precharge power-down current: Fast exit IDD2P1 112 112 mA

Precharge quiet standby current IDD2Q 160 160 mA

Precharge standby current IDD2N 168 168 mA

Precharge standby ODT current IDD2NT 248 232 mA

Active power-down current IDD3P 168 168 mA

Active standby current IDD3N 256 240 mA

Burst read operating current IDD4R 752 656 mA

Burst write operating current IDD4W 776 680 mA

Refresh current IDD5 1440 1432 mA

Self refresh temperature current: MAX TC = 85°C IDD6 96 96 mA

Self refresh temperature current (SRT-enabled): MAX TC = 95°C IDD6ET 120 120 mA

All banks interleaved read current IDD7 1248 1200 mA

Reset current IDD8 112 112 mA

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

IDD Specifications

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Table 15: DDR3 IDD Specifications and Conditions – 4GB (Die Revision E)

Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb

(512 Meg x 8) component data sheet

Parameter Symbol 1866 1600 1333 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 496 440 376 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 560 528 469 mA

Precharge power-down current: Slow exit IDD2P0 144 144 144 mA

Precharge power-down current: Fast exit IDD2P1 296 256 224 mA

Precharge quiet standby current IDD2Q 280 256 224 mA

Precharge standby current IDD2N 280 256 232 mA

Precharge standby ODT current IDD2NT 336 312 280 mA

Active power-down current IDD3P 328 304 280 mA

Active standby current IDD3N 328 304 280 mA

Burst read operating current IDD4R 1392 1256 1120 mA

Burst write operating current IDD4W 1128 1000 880 mA

Refresh current IDD5 1936 1880 1824 mA

Self refresh temperature current: MAX TC = 85°C IDD6 160 160 160 mA

Self refresh temperature current (SRT-enabled): MAX TC = 95°C IDD6ET 200 200 200 mA

All banks interleaved read current IDD7 2008 1760 1520 mA

Reset current IDD8 160 160 160 mA

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

IDD Specifications

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Table 16: DDR3 IDD Specifications and Conditions – 4GB (Die Revision N)

Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb

(512 Meg x 8) component data sheet

Parameter Symbol 1866 1600 1333 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 392 376 360 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 512 488 464 mA

Precharge power-down current: Slow exit IDD2P0 64 64 64 mA

Precharge power-down current: Fast exit IDD2P1 128 112 96 mA

Precharge quiet standby current IDD2Q 208 192 176 mA

Precharge standby current IDD2N 208 192 176 mA

Precharge standby ODT current IDD2NT 240 224 208 mA

Active power-down current IDD3P 224 208 192 mA

Active standby current IDD3N 256 240 224 mA

Burst read operating current IDD4R 840 760 680 mA

Burst write operating current IDD4W 840 760 680 mA

Refresh current IDD5 1440 1400 1360 mA

Self refresh temperature current: MAX TC = 85°C IDD6 96 96 96 mA

Self refresh temperature current (SRT-enabled): MAX TC = 95°C IDD6ET 128 128 128 mA

All banks interleaved read current IDD7 1120 1040 960 mA

Reset current IDD8 80 80 80 mA

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

IDD Specifications

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Table 17: DDR3 IDD Specifications and Conditions – 4GB (Die Revision P)

Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4Gb

(512 Meg x 8) component data sheet

Parameter Symbol 1866 1600 Units

Operating current 0: One bank ACTIVATE-to-PRECHARGE IDD0 232 224 mA

Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD1 352 344 mA

Precharge power-down current: Slow exit IDD2P0 88 80 mA

Precharge power-down current: Fast exit IDD2P1 88 88 mA

Precharge quiet standby current IDD2Q 120 120 mA

Precharge standby current IDD2N 136 128 mA

Precharge standby ODT current IDD2NT 176 160 mA

Active power-down current IDD3P 120 120 mA

Active standby current IDD3N 168 160 mA

Burst read operating current IDD4R 816 720 mA

Burst write operating current IDD4W 904 808 mA

Refresh current IDD5 1216 1216 mA

Self refresh temperature current: MAX TC = 85°C IDD6 120 120 mA

Self refresh temperature current (SRT-enabled): MAX TC = 95°C IDD6ET 184 184 mA

All banks interleaved read current IDD7 1168 1040 mA

Reset current IDD8 104 104 mA

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

IDD Specifications

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Serial Presence-Detect EEPROM

For the latest SPD data, refer to Micron's SPD page: micron.com/spd.

Table 18: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VDDSPD

Parameter/Condition Symbol Min Max Units

Supply voltage VDDSPD 3.0 3.6 V

Input low voltage: Logic 0; All inputs VIL –0.45 VDDSPD x 0.3 V

Input high voltage: Logic 1; All inputs VIH VDDSPD x 0.7 VDDSPD + 1.0 V

Output low voltage: IOUT = 3mA VOL – 0.4 V

Input leakage current: VIN = GND to VDD ILI 0.1 2.0 µA

Output leakage current: VOUT = GND to VDD ILO 0.05 2.0 µA

Table 19: Serial Presence-Detect EEPROM AC Operating Conditions

Parameter/Condition Symbol Min Max Units Notes

Clock frequency tSCL 10 400 kHz

Clock pulse width HIGH time tHIGH 0.6 – µs

Clock pulse width LOW time tLOW 1.3 – µs

SDA rise time tR – 300 µs 1

SDA fall time tF 20 300 ns 1

Data-in setup time tSU:DAT 100 – ns

Data-in hold time tHD:DI 0 – µs

Data-out hold time tHD:DAT 200 900 ns

Data out access time from SCL LOW tAA:DAT 0.2 0.9 µs 2

Start condition setup time tSU:STA 0.6 – µs 3

Start condition hold time tHD:STA 0.6 – µs

Stop condition setup time tSU:STO 0.6 – µs

Time the bus must be free before a new transition can

start

tBUF 1.3 – µs

WRITE time tW – 10 ms

Notes: 1. Guaranteed by design and characterization, not necessarily tested.

2. To avoid spurious start and stop conditions, a minimum delay is placed between the fall-

ing edge of SCL and the falling or rising edge of SDA.

3. For a restart condition, or following a WRITE cycle.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Serial Presence-Detect EEPROM

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Module Dimensions

Figure 3: 204-Pin DDR3 SODIMM

3.8 (0.150)

MAX

Pin 1

67.75 (2.667)

67.45 (2.656)

20.0 (0.787)

TYP

1.8 (0.071)

(2X)

0.6 (0.024)

TYP

0.45 (0.018)

TYP

2.0 (0.079) R

(2X)

Pin 203

Pin 204 Pin 2

Front view

2.0 (0.079)

TYP

6.0 (0.236)

TYP

63.6 (2.504)

TYP

2.55 (0.10)

TYP

1.0 (0.039)

TYP

30.15 (1.187)

29.85 (1.175)

Back view

1.10 (0.043)

0.90 (0.035)

39.0 (1.535)

TYP

21.0 (0.827)

TYP

3.0 (0.12)

TYP

4.0 (0.157)

TYP

24.8 (0.976)

TYP

45° 4X

U1 U2

U3 U4

U6 U7 U8 U9

Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.

2. The dimensional diagram is for reference only.

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www.micron.com/products/support Sales inquiries: 800-932-4992

Micron and the Micron logo are trademarks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMM

Module Dimensions

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