MCS7820
USB-2.0 to Two Serial Ports
MosChip Semiconductor ♦ 3335 Kifer Rd, Santa Clara, CA 95051 ♦ Tel (408) 737-7141 ♦ Fax (408) 737-7708
Features
• USB-2.0 Device Controller
• On-Chip USB-2.0 PHY
• On-Chip Voltage Regulators
• Two 16c450/16c550 compatible UARTs
• Supports SIR IrDA Mode on any/all ports
• Supports RS-232, RS-485 and RS-422
Serial Ports
• 5, 6, 7 and 8-bit Serial Data support
• Hardware and Software Flow Control
• Serial Port speeds from 50 bps to 6 Mbps
• Custom BAUD Rates supported through
external clock and/or by programming the
internal PLL
• On-Chip 512-Byte FIFOs for upstream and
downstream data transfers for each Serial
Port
• Supports Remote Wakeup and Power
Management features
• Serial Port Transceiver Shut-Down
support
• Two-Wire I2C Interface for EEPROM
• EEPROM read/write through USB
• iSerial feature support with EEPROM
• One Bi-directional multi-function GPIO
• On-Chip buffers for Serial Port signals to
operate without external Transceivers over
short cable lengths
• Bus-Powered Device
Applications
• Serial Attached Devices
• Modems, Serial Mouse, Generic Serial
Devices
• Serial-Port Server
• Data Acquisition System
• POS Terminal and Industrial PC
General Description
The MCS7820 is a USB-2.0 to Dual-Serial Port
device. It has been developed to connect a wide
range of standard serial devices to a USB host.
The MCS7820 has a USB Device Controller
connected to two (2) individual UARTs.
Support for the following serial communication
programs is included:
HyperTerminal, PComm, Windows direct
connection, Windows dial-up connection through
modem, Networking over IrDA and Windows direct
connection over IrDA, Minicom.
Application Note
• AN-7820
Evaluation Board
• MCS7820-EVB
Package
• 48-pin LQFP Package
Driver Support
• Windows
(98SE / ME / 2000 / XP / 2003 Server)
• Linux Kernel 2.6.5 and above
• MAC 10.2 and above
• Windows CE5.0
• Windows Vista
Utility Support
• Windows based EEPROM Tool
• Mass Production Utility
Ordering Information
Commercial Grade (0 °C to +70 °C)
MCS7820CV 48-LQFP RoHS
MCS7820
USB-2.0 to Two Serial Ports
Page 2 Rev. 1.2
Block Diagram
DP
DM
USB-2.0
PHY
USB-2.0
Device
Controller
Bridge
PLL
Interrupt-In
Block
VSPEC_CMD_
Processor
XTAL OUT
XTAL IN
Clock
Recovery Resets
I C EEPROM
Controller
2
Serial Port
x2
Tx
Buffer
Rx
Buffer
DTR
RTS
TXD
RXD
DCD
CTS
DSR
Wake-Up
Block
BAUD Clock
Generator
x2
Bulk
In
FIFOs
Bulk
Out
FIFOs
SCL SDA
RI
Ext_Clock
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 3
Pin-Out Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
MCS7820CV
GND
USB_XSCI
USB_XSCO
Vcc
GND
USB_RREF
USB_DM
USB_DP
Vcc
GND
Vcc
TEST_MODE
K
A
A
A
A
K
TXD_1
DTR_1_N
RTS_1_N
RXD_1
RI_1_N
Vcc
GND
Vcc
DSR_1_N
DCD_1_N
CTS_1_N
SHTD_1_N
K
K
3IO
EE_SDA
EE_SCL
RESET
GPIO
GND
Vcc
GND
Vcc
REG02_V18
GND
Vcc
REG06_VCC33
K
18A_PLL
18A_PLL
5A
5A
Vcc
CTS_2_N
DCD_2_N
DSR_2_N
RI_2_N
RXD_2
RTS_2_N
DTR_2_N
TXD_2
Vcc
EXT_CLOCK
GND
K
3IO
K
MCS7820
USB-2.0 to Two Serial Ports
Page 4 Rev. 1.2
Pin Assignments
Pin Name Type Functional Description
1 GNDKPower Core Ground
2 USB_XSCI Input Crystal Oscillator Input
3 USB_XSCO Output Crystal Oscillator Output
4 VccAPower Power Pin (A3V3)
5 GNDAPower Analog Ground
6 USB_RREF Input External Reference Resistor (12.1 KΩ, 1%)
Connect resistor to Analog GND.
7 USB_DM I/O USB D- Signal
8 USB_DP I/O USB D+ Signal
9 VccAPower Power Pin (A3V3)
10 GNDAPower Analog Ground
11 VccKPower Power Pin (1.8V)
12 TEST_MODE Input
Test Mode Pin, (active high). Default = Low (0)
When TEST_MODE = 1, PLL, Core, and SCAN/BIST/
Memory BIST testing can be performed.
Set TEST_MODE = 0 for normal operation.
13 TXD_1 Output Serial Port 1 Transmit Data out to transceiver or IrDA data
out to IR LED
14 DTR_1_N Output Serial Port 1 Data Terminal Ready (in serial protocol), active
low.
15 RTS_1_N Output Serial Port 1 Request To Send (in serial protocol), active low.
16 RXD_1 Input Serial Port 1 Serial Receive Data in from transceiver or IrDA
data in from IrDA detector.
17 RI_1_N Input Serial Port 1 Ring Indicator, active low
18 VccKPower Power Pin (1.8V)
19 GNDKPower Core Ground
20 Vcc3IO Power Power Pin (D3V3)
21 DSR_1_N Input Serial Port 1 Data Set Ready (in serial protocol), active low
22 DCD_1_N Input Serial Port 1 Data Carrier Detect (in serial protocol), active
low
23 CTS_1_N Input Serial Port 1 Clear To Send (in serial protocol), active low
24 SHTD_1_N Output Shut Down External Serial Transceiver during normal
operation, active low by default, can be confi gured active
high by using DCR setting.
25 REG06_VCC33 Power Power Pin (3.3V OUTPUT)
26 Vcc5A Power Power Pin (5V INPUT)
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 5
Pin Name Type Functional Description
27 GND5A Power Ground Pin for 5V Input
28 REG02_V18 Power Power Pin (1.8V OUTPUT)
29 Vcc18A_PLL Power PLL Power (1.8V)
30 GND18A_PLL Power PLL Ground
31 VccKPower Power Pin (1.8V)
32 Gnd Power Ground.
33 GPIO I/O GPIO_MODE - Bidirectional GPIO bit. The direction (Input or
Output) is controlled by the DCR for Serial Port #1.
34 RESET Input Power-On Reset signal (active high).
35 EE_SCL I/O 2-Wire EEPROM Clock. Default = High (1)
36 EE_SDA I/O 2-Wire EEPROM Data in/out. Default = High (1)
37 GNDKPower Core Ground.
38 EXT_CLOCK Input
Input Clock from external world. In normal operation mode,
clock can be supplied to serial ports and used for custom
BAUD Rate of user’s choice. In test mode, clock will be the
test clock input from external world.
39 Vcc3IO Power Power Pin (D3V3).
40 TXD_2 Output Serial Port 3 Transmit Data out to transceiver, or IrDA data
out to IR LED.
41 DTR_2_N Output Serial Port 3 Data Terminal Ready (in serial protocol), active
low.
42 RTS_2_N Output Serial Port 3 Request To Send (in serial protocol), active low.
43 RXD_2 Input Serial Port 3 Serial Receive Data in from transceiver, or IrDA
data in from IrDA detector.
44 RI_2_N Input Serial Port 3 Ring Indicator, active low.
45 DSR_2_N Input Serial Port 3 Data Set Ready (in serial protocol), active low.
46 DCD_2_N Input Serial Port 3 Data Carrier Detect (in serial protocol), active
low.
47 CTS_2_N Input Serial Port 3 Clear To Send (in serial protocol), active low.
48 VccKPower Power Pin (1.8V)
MCS7820
USB-2.0 to Two Serial Ports
Page 6 Rev. 1.2
Functional Block Descriptions
Internal Regulators
An internal DC-DC Regulator is provided to convert
5V to 1.8V for Core Logic. An additional regulator is
provided to convert the 5V input to 3.3V for I/O functions.
These regulators eliminate the need for external voltage
sources.
USB-2.0 PHY
This is the physical layer of the USB interface. The
USB-2.0 PHY communicates with the USB-2.0 Device
Controller logic through a UTMI interface to send/receive
data on the USB bus.
USB-2.0 Device Controller
The USB-2.0 Device Controller interfaces to the internal
bridge and communicates with the serial ports through
the bridge logic. The device controller logic is connected
to a physical layer USB-2.0 PHY which provides the USB
bus interface for the chip. The device controller responds
to standard as well as vendor specifi c requests from
USB-2.0 and USB-1.1 Hosts.
Bridge
The bridge logic controls traffi c between the USB-2.0
Device Controller and the Serial Port Controllers. The
bridge logic has synchronous RAM memories with ping-
pong FIFO control logic to buffer data in either direction
(Bulk-In and Bulk-Out) and send it to the other side
without loss. Control logic prevents overfl ow or underfl ow
conditions in the memory.
UART / Serial Port Controllers
The Serial Port Controllers are linked to the bridge and
send/receive data from the bridge interface. Each serial
port controller has register logic controlling BAUD rates
(50 bps – 6 Mbps), stop-bits, and parity bit settings.
Each serial port has synchronous RAM memories acting
as transmit and receive FIFOs to buffer outgoing and
incoming data. This block has registers for interrupts, line
status, and line control features which can be accessed
by software. The Serial Port Controllers can interface to
external RS-232 / RS-422 / RS-485 transceivers.
Vendor Specifi c Command Processor
The bridge logic interfaces to a vendor specifi c command
processor block containing commands/register settings
(BAUD settings etc.) which are specifi c to this device.
Interrupt-In Block
The Interrupt-In controller block gives the status of the
serial port interrupt registers to the USB-2.0 Device
Controller. The USB host controller periodically polls the
interrupt endpoint and reads the status of the interrupts.
Wakeup Block
The Wakeup block is used for remote wakeup control.
The USB host can suspend operation of the device. The
remote wakeup block checks for activity on the serial port
pins, and if information is available, it issues a remote
wakeup request to the USB-2.0 Device Controller. The
Device Controller in turn requests a remote wakeup
by the external host. The host issues the “Resume
Signaling” command to the device, which then resumes
normal operation.
I2C EEPROM Controller
The I2C EEPROM Controller interfaces to an external
EEPROM and retrieves information necessary for serial
port settings, Product-IDs, Vendor-IDs and other control
information. The EEPROM controller logic communicates
with the USB-2.0 Device Controller block which uses the
information from the external EEPROM.
Clock Generation and Resets
The Clock Generation logic is used to generate the clocks
for the various BAUD rates supported by the device. The
Resets block has logic for synchronous de-assertion and
asynchronous assertion of Resets in the respective clock
domains to various blocks.
BAUD Clock Generators
The BAUD Clock Generator block generates clocks for
each of the Serial Port Controllers depending on the
BAUD settings from the host. A source clock is generated
from the Clock Recovery block which is further divided or
used as is by the BAUD Clock Generator logic depending
on the BAUD settings.
PLL Clock Generator
The PLL generates a master clock which the other
blocks use to generate the various BAUD rates. The PLL
supports a wide range of clock inputs to support industrial
standard serial port bit rates, as well as custom BAUD
rates.
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 7
UART Functional Description
Overview
The UARTs are high performance serial ports that comply with the 16c550 specifi cation. All UARTs are similar
in operation and function, and are described in this section. The function of a single UART is described below.
Operation Modes
The UARTs are backward compatible with 16c450 and 16c550 devices. The operation of the port depends
upon the mode settings, which are described throughout the rest of this section. The modes, conditions and
corresponding FIFO depth are tabulated below.
UART Mode FIFO Size FCR[0]
450 1 0
550 16 1
450 Mode
After the hardware reset, bit-0 of the FIFO Control
Register (FCR) is cleared, and the UART is
compatible with the 16c450 mode of operation.
The transmitter and receiver FIFOs (referred to as
the “Transmitter Holding Register” and “Receiver
Holding Register” respectively) have a depth of
one.
This mode of operation is known as “Byte Mode”.
550 Mode
After the hardware reset, writing a 1 to FCR[0]
will increase the FIFO size to 16, providing
compatibility with 16c550 devices.
In 16c550 mode, the device has the following
features:
• RTS/CTS hardware fl ow control or
DSR/DTR hardware fl ow control
• Infrared IrDA format transmit and receive
mode
• Deeper (16-Byte) FIFOs
MCS7820
USB-2.0 to Two Serial Ports
Page 8 Rev. 1.2
UART Register-Set and Register Descriptions
The UART has 10 registers, but only three address lines to access those registers. The mapping of the
registers is dependent upon the Line Control Register (LCR).
LCR[7] enables the Divider Latch Registers (DLL and DLM).
The following table gives the various UART registers and their offsets.
Register
Name Offset R/W Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
THR 0 W Data to be transmitted ( Transmitter Holding Register)
RHR 0 R Data to be received (Receiver Holding Register)
IER 1 R/W Reserved Sleep
Mode
Modem
Int
Mask
Rx
Stat
Int
Mask
Tx Rdy
Int
Mask
Rx Rdy
Int
Mask
FCR 2 W RHR
Trigger Level Reserved Reserved Flush
THR Flush
RHR FIFO
Enable
ISR 2 R FIFOs
Enabled Reserved Interrupt Priority Interrupt
Pending
LCR 3 R/W DLE Tx
Break Force
Parity Odd/Even
Parity Parity
Enable Stop
Bits Data Length
MCR 4 R/W DTR – DSR/
DCD
Flow Control
RTS/CTS
Flow
Control Loop Unused RTS DTR
LSR 5 R Data
Error Tx
Empty THR
Empty Rx
Break Framing
Error Parity
Error Overrun
Error Rx
Rdy
MSR 6 R DCD RI DSR CTS ΔDCD Teri ΔDSR ΔCTS
SPR 7 R/W Scratch Pad Register
Additional standard registers - these are accessed when LCR[7] = 1
DLL 0 R/W Divisor Latch bits[7:0]
DLM 1 R/W Divisor Latch bits[15:8]
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 9
Transmitter Holding Register and Receiver Holding Register (THR and RHR):
Data is written into the bottom of the THR queue and read from the top of the RHR queue completely
asynchronously to the operation of the transmitter and receiver. The size of the FIFOs is dependent upon the
setting of the FCR register.
Data written to the THR when it is full, is lost. Data read from the RHR when it is empty, is invalid. The empty
and full status of the FIFOs is indicated in the Line Status Register.
Register: THR
Description: Data to be transmitted
Offset: 0
Permissions: Write Only
Access Condition: LCR[7] = 0
Default Value: (unknown) – based on memory
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Data to be transmitted
Register: RHR
Description: Data to be received
Offset: 0
Permissions: Read Only
Access Condition: LCR[7] = 0
Default Value: (unknown) – based on memory
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Data to be received
MCS7820
USB-2.0 to Two Serial Ports
Page 10 Rev. 1.2
Interrupt Enable Register (IER):
Serial channel interrupts are enabled using the Interrupt Enable Register (IER).
Register: IER
Description: Interrupt Enable Register
Offset: 1
Permissions: Read/Write
Access Condition: LCR[7] = 0
Default Value: 0x0C
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Reserved Sleep
Mode Modem
Int Mask Rx Stat
Int Mask Tx Rdy
Int Mask Rx Rdy
Int Mask
Bit Description Operation
0Rx Rdy
Interrupt Mask Logic 0: Disable the Receiver Ready Interrupt
Logic 1: Enable the Receiver Ready Interrupt
1Tx Rdy
Interrupt Mask Logic 0: Disable the Transmitter Ready Interrupt
Logic 1: Enable the Transmitter Ready Interrupt
2Rx Stat
Interrupt Mask
Logic 0: Disable the Receiver Status Interrupt
(Normal Mode)
Logic 1: Enable the Receiver Status Interrupt
(Normal Mode)
3Modem
Interrupt Mask Logic 0: Disable the Modem Status Interrupt
Logic 1: Enable the Modem Status Interrupt
4 Sleep Mode Logic 0: Disable Sleep Mode
Logic 1: Enable Sleep Mode where by the internal clock
of the channel is switched OFF
[7:5] Reserved Reserved
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 11
FIFO Control Register (FCR):
The FCR controls the UART behavior in various modes.
Register: FCR
Description: FIFO Control Register
Offset: 2
Permissions: Write
Access Condition:
Default Value: 0x00
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
RHR T rigger Level Reserved Reserved Flush
THR Flush
RHR Enable
FIFOs
Bit Description Operation
0 Enable FIFO Mode Logic 0: Byte Mode
Logic 1: FIFO Mode
1 Flush RHR
Logic 0: No change
Logic 1: Flushes the contents of RHR, This is operative
only in FIFO mode. The RHR is automatically
fl ushed whenever changing between Byte Mode
and FIFO Mode. The bit will return to zero after
clearing the FIFO.
2 Flush THR Logic 0: No change
Logic 1: Flushes the content of the THR, in the same
manner as FCR[1] does the RHR
3 Reserved Reserved
[5:4] Reserved Reserved
[7:6] RHR T rigger Level See Table Below
In 550 Mode, the receiver FIFO trigger levels are
defi ned by FCR[7:6].
The interrupt trigger level and fl ow control trigger level
where appropriate are defi ned by L2 in the table.
L1 defi nes a lower fl ow control trigger level. The two
trigger levels used together introduce a hysteresis
element into the hardware RTS/CTS fl ow control.
In Byte Mode (450 Mode) trigger levels are all set to 1.
FCR[7:6] 550 Mode (FIFO = 16)
L1 L2
2’b00 1 1
2’b01 1 4
2’b10 1 8
2’b11 1 14
MCS7820
USB-2.0 to Two Serial Ports
Page 12 Rev. 1.2
Interrupt Status Register (ISR):
The source of the highest priority pending interrupt is indicated by the contents of the Interrupt Status
Register. There are fi ve sources of interrupts and four levels of priority (1 is the highest) as tabulated below:
Register: ISR
Description: Interrupt Status Register
Offset: 2
Permissions: Read
Access Condition:
Default Value: 0x00
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
FIFOs Enabled Interrupt Priority
(Enhanced Mode) Interrupt Priority
(All Modes) Interrupt
Pending
Interrupt
Source and Priority
Table
Priority Level Interrupt Source ISR[5:0]
- No interrupt pending 6’b000001
1Receiver Status Error
or address bit detected in 9-bit mode 6’b000110
2a Receiver Data Available 6’b000100
2b Receiver T ime-Out 6’b001100
3 T ransmitter THR Empty 6’b000010
4 Modem Status Change 6’b000000
Note: ISR[0] indicates whether any interrupt is pending
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 13
Line Control Register (LCR):
The LCR specifi es the data format that is common to both transmitter and receiver.
Register: LCR
Description: Line Control Register
Offset: 3
Permissions: Read/Write
Access Condition:
Default Value: 0x00
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
DLE TX
Break Force
Parity Odd/Even
Parity Parity
Enable Number of
Stop-Bits Data
Length
LCR[1:0] Data Length of serial characters.
LCR[2] Number of Stop-Bits per serial character.
LCR[5:3] Parity Type
The selected parity type will be generated
during transmission and checked by the
receiver, which may produce a parity
error as a result. In 9-bit mode parity is
disabled and LCR[5:3] are ignored.
LCR[6] Transmission Break
Logic 0: Transmission Break Disabled.
Logic 1: Forces the transmitter data
output SOUT low to alert the
communications channel, or
sends zeroes in IrDA mode.
LCR[7] Divisor Latch Enable
Logic 0: Accesses to DLL and DLM
registers disabled.
Logic 1: Accesses to DLL and DLM
registers enabled.
LCR[1:0] Data Length
2’b00 5 bits
2’b01 6 bits
2’b10 7 bits
2’b11 8 bits
LCR[2] Data Length Number of
Stop-Bits
0 5, 6, 7, 8 1
1 5 1.5
1 6, 7, 8 2
LCR[5:3] Parity Type
3’bxx0 No Parity
3’b001 Odd Parity
3’b011 Even Parity
3’b101 Parity bit forced to 1
3’b111 Parity bit forced to 0
MCS7820
USB-2.0 to Two Serial Ports
Page 14 Rev. 1.2
Line Status Register (LSR):
This register provides the status of the data transfer to CPU.
Register: LSR
Description: Line Status Register
Offset: 5
Permissions: Read
Access Condition:
Default Value: 0x00
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Data
Error Tx
Empty THR
Empty Rx
Break Framing
Error Parity
Error Overrun
Error Rx
Rdy
Bit Description Operation
0RHR
Data Available Logic 0: RHR is empty
Logic 1: RHR is not empty. Data is available to be read
1RHR
Overrun
Logic 0: No overrun error
Logic 1: Data was received when the RHR was full, An
overrun has occurred. The error is fl agged when
the data would normally have been transferred
to the RHR.
2Received Data
Parity Error
Logic 0: No parity error in normal mode or 9th bit received
data is “0” in 9-bit mode.
Logic 1: Data has been received that did not have correct
parity
3Received Data
Framing Error Logic 0: No framing error
Logic 1: Data has been received with an invalid stop-bit.
4Receiver Break
Error Logic 0: No receiver break error
Logic 1: The receiver received a break error
5 THR Empty Logic 0: Transmitter FIFO is not empty
Logic 1: Transmitter FIFO is empty
6Transmitter and
THR Empty
Logic 0: The transmitter is not idle
Logic 1: THR is empty and the transmitter has completed
the character in the shift register and is in the
idle mode
7Receiver
Data Error
Logic 0: Either there is no receiver data error in the FIFO
or it was cleared by an earlier read of LSR
Logic 1: At least one parity error, framing error or break
indication is present in the FIFO.
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 15
Modem Control Register (MCR):
This register controls the UART’s fl ow control and self diagnostic features.
Register: MCR
Description: Modem Control Register
Offset: 4
Permissions: Read/Write
Access Condition:
Default Value: 0x00
550 Mode
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
DTR-DSR/DCD
Flow Control
CTS/RTS
Flow
Control
Internal
Loop Back
Enable Reserved Reserved RTS DTR
Bit Description Operation
0 DTR Logic 0: Forces DTR# output to inactive (high)
Logic 1: Forces DTR# output to active (low)
1RTS
Logic 0: Forces RTS# output to inactive (high)
Logic 1: Forces RTS# output to active (low)
2 Reserved Reserved.
3 Reserved Reserved.
4Loop-Back
Mode Logic 0: Normal operating mode
Logic 1: Enable local Loop-Back Mode
5CTS/RTS
Flow Control Logic 0: CTS/RTS fl ow control disabled in 550 mode
Logic 1: CTS/RTS fl ow control enabled in 550 mode
6DTR/DSR
Flow Control Logic 0: DTR/DSR fl ow control disabled in 550 mode
Logic 1: DTR/DSR fl ow control enabled in 550 mode
7DCD
Flow Control Logic 0: DCD fl ow control disabled in 550 mode
Logic 1: DCD fl ow control enabled in 550 mode
MCS7820
USB-2.0 to Two Serial Ports
Page 16 Rev. 1.2
Modem Status Register (MSR):
This register provides the status of the modem control lines to CPU.
Register: MSR
Description: Modem Status Register
Offset: 6
Permissions: Read
Access Condition:
Default Value: 0x00
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
DCD RI DSR CTS ΔDCD Teri ΔDSR ΔCTS
Bit Description Operation
0 Delta CTS Logic 0: No change in the CTS signal
Logic 1: Indicates that the CTS input has changed since
the last time the MSR was read
1 Delta DSR Logic 0: No change in the DSR signal
Logic 1: Indicates that the DSR input has changed since
the last time the MSR was read
2 Trailing Edge of RI Logic 0: No change in the RI signal
Logic 1: Indicates that the RI input has changed from low
to high since the last time the MSR was read
3 Delta DCD Logic 0: No change in the DCD signal
Logic 1: Indicates that the DCD input has changed since
the last time the MSR was read
4 CTS Logic 0: CTS# line is 1
Logic 1: CTS# line is 0
5 DSR Logic 0: DSR# line is 1
Logic 1: DSR# line is 0
6RI
Logic 0: RI# line is 1
Logic 1: RI# line is 0
7 DCD Logic 0: DCD# line is 1
Logic 1: DCD# line is 0
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 17
Scratch Pad Register (SPR):
The scratch pad register does not infl uence operation of the UART in RS-232 mode in any way, and is used
for temporary data storage. When using RS-422/485 Mode, bit[6] and bit[7] of the Scratch Pad Register are
used for mode setting and DTR active level settings.
Register: SPR
Description: Scratch Pad Register
Offset: 7
Permissions: Read/Write
Access Condition:
Default Value: 0x00
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Scratch Pad Register Data
MCS7820
USB-2.0 to Two Serial Ports
Page 18 Rev. 1.2
Divisor Latch Registers (DLL and DLM):
The Divisor Latch Registers are used to program the BAUD Rate divisor.
This is a value between 1 and 65535 by which the input clock is divided in order to generate serial BAUD
rates.
After the hardware reset, the BAUD Rate used by the transmitter and receiver is given by:
BAUD Rate = Input Clock / (16 * Divisor)
where divisor is given by (256 * DLM) + DLL.
More fl exible BAUD rate generation options are also available.
Register: DLL
Description: Divisor Latch (Least Signifi cant Byte)
Offset: 0
Permissions: Read/Write
Access Condition: LCR[7] = 1
Default Value: 0x01
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Least Signifi cant Byte of divisor latch
Register: DLM
Description: Divisor Latch (Most Signifi cant Byte)
Offset: 1
Permissions: Read/Write
Access Condition: LCR[7] = 1
Default Value: 0x00
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Most Signifi cant Byte of divisor latch
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 19
RS-422 / RS-485 Mode Support
Two additional modes of serial port operation are supported, these are:
• RS-422 Mode – Full Duplex Serial Port for industrial applications
• RS-485 Mode – Half Duplex Serial Port for industrial applications
RS-485
The RS-485 mode can be set using the Scratch
Pad Register bit[6] and bit[7] for each serial port.
This mode is a half duplex mode and the external
transceiver is controlled for transmission or
reception using the enable signal.
Scratch Pad
Bit[7] Scratch Pad
Bit[6] Operation
Summary
0X
RS-485 Mode
Disabled
10
RS-485 Mode
Enabled,
DTR High = Rx
DTR Low = Tx
11
RS-485 Mode
Enabled
DTR Low = Rx
DTR High = Tx
This is the
default selection
when RS485
mode is selected
through driver
property sheets.
RS-422
This is the full duplex mode.
This mode will work without the use of the DTR
signal for external transceiver control.
MCS7820
USB-2.0 to Two Serial Ports
Page 20 Rev. 1.2
Confi guration Options
Two serial ports can be confi gured for operation.
To program and access the serial ports via software, endpoint numbers have been assigned so that serial
ports can be confi gured from the USB side.
Endpoint Type Function Size (Bytes)
(USB-1.1 / USB-2.0)
0 Control Endpoint Default Functionality 8 / 64
1 Bulk-In Serial Port – 1 64 / 512
2 Bulk-Out Serial Port – 1 64 / 512
3 Bulk-In Serial Port – 2 64 / 512
4 Bulk-Out Serial Port – 2 64 / 512
5 Interrupt Status Endpoint 5 or 13 *
* Controlled by DCR1 bit-6
Serial Port Set/Get Commands
Vendor commands are the vendor specifi c USB setup commands. The purpose of the vendor commands is
to set/get the contents of the application registers. The following table provides information on the various
vendor specifi c commands.
Windex [7:0] is the register index from where data is to be read.
Brequest specifi es whether to read or write.
• 0x0E = write to the application register
• 0x0D = read from the application register
Wvalue specifi es the application number and data to be written (ww = data).
• 0x01ww is the application number for Serial Port-1
• 0x03ww is the application number for Serial Port-2
• 0x09ww is the application number for EEPROM Write/Read
• 0x00ww is the application number provided for accessing the Control Registers which control the
UARTs. It is possible to enable higher BAUD rates, and features like auto hardware fl ow control using
the Control Registers.
Note: “N” in Wvalue and Register Name columns indicate the corresponding serial port number.
Windex is the offset of the register to read/write.
Wlength is the length of the data to read/write.
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 21
Get Application
Vendor Specifi c
Command
(Serial Port -N)
Set Application
Vendor Specifi c
Command
(Serial Port -N)
bmrequestType Brequest Wvalue Windex Wlength Register
Name
0xC0 0x0D 0x0N00 0x0000 0x0001 SPN_RHR
0xC0 0x0D 0x0N00 0x0001 0x0001 SPN_IER
0xC0 0x0D 0x0N00 0x0002 0x0001 SPN_IIR
0xC0 0x0D 0x0N00 0x0003 0x0001 SPN_LCR
0xC0 0x0D 0x0N00 0x0004 0x0001 SPN_MCR
0xC0 0x0D 0x0N00 0x0005 0x0001 SPN_LSR
0xC0 0x0D 0x0N00 0x0006 0x0001 SPN_MSR
0xC0 0x0D 0x0N00 0x0007 0x0001 SPN_SPR
0xC0 0x0D 0x0N00 0x0000 0x0001 SPN_DLL
0xC0 0x0D 0x0N00 0x0001 0x0001 SPN_DLM
bmrequestType Brequest Wvalue Windex Wlength Register
Name
0x40 0x0E 0x0Nww 0x0000 0x0001 SPN_THR
0x40 0x0E 0x0Nww 0x0001 0x0001 SPN_IER
0x40 0x0E 0x0Nww 0x0002 0x0001 SPN_FCR
0x40 0x0E 0x0Nww 0x0003 0x0001 SPN_LCR
0x40 0x0E 0x0Nww 0x0004 0x0001 SPN_MCR
0x40 0x0E 0x0Nww 0x0005 0x0001 SPN_LSR
0x40 0x0E 0x0Nww 0x0006 0x0001 SPN_MSR
0x40 0x0E 0x0Nww 0x0007 0x0001 SPN_SPR
0x40 0x0E 0x0Nww 0x0000 0x0001 SPN_DLL
0x40 0x0E 0x0Nww 0x0001 0x0001 SPN_DLM
MCS7820
USB-2.0 to Two Serial Ports
Page 22 Rev. 1.2
USB Device Descriptors
Device Descriptor Location Data
BLength 0 8’h12
BDescriptorType 1 8’h01
BcdUSB 2 8’h00
BcdUSB 3 8’h02
BDeviceClass 4 8’hFF
BDeviceSubClass 5 8’h00
BDeviceProtocol 6 8’hFF
bMaxPacketSize0 7 8’h40
IdVendor 8 8’h10
IdVendor 9 8’h97
IdProduct 10 8’h20
IdProduct 11 8’h78
BcdDevice 12 8’h01
BcdDevice 13 8’h00
iManufacturer 14 8’h00 / 02 *
iProduct 15 8’h00 / 03 *
iSerialNumber 16 8’h00 / 01 *
BNumConfi gurations 17 8’h01
* Values returned Without / With the Serial EEPROM present.
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 23
USB
Confi guration
Descriptors
USB
Interface
Descriptors
Confi guration
Descriptor Index Data
BLength 0 8’h09
BDescriptorType 1 8’h02
WtotalLength(L) 2 8’h35
WtotalLength(M) 3 8’h00
BNumInterfaces 4 8’h01
BConfi gurationValue 5 8’h01
IConfi guration 6 8’h00
BmAttributes 7 8’hA0
BMaxPower 8 8’h32
(100 mA)
Confi guration
Descriptor Index Data
BLength 0 8’h09
BDescriptorType 1 8’h04
BInterfaceNumber 2 8’h00
BAlternateSetting 3 8’h00
BNumEndpoints 4 8’h09
BInterfaceClass 5 8’hFF
BInterfaceSubClass 6 8’h00
BInterfaceProtocol 7 8’hFF
IInterface 8 8’h00
MCS7820
USB-2.0 to Two Serial Ports
Page 24 Rev. 1.2
Endpoint-1
Serial Port 1
Bulk-In
Endpoint-2
Serial Port 1
Bulk-Out
Endpoint-3
Serial Port 2
Bulk-In
Endpoint-4
Serial Port 2
Bulk-Out
Confi guration Descriptor Index Data
bLength 0 8’h07
bDescriptorType 1 8’h05
bEndpointAddress 2 8’h81
bmAttributes 3 8’h02
wMaxPacketSize(L) 4 8’h40/8’h00 *
wMaxPacketSize(M) 5 8’h00/8’h02 *
bInterval 6 8’hFF
Confi guration Descriptor Index Data
bLength 0 8’h07
bDescriptorType 1 8’h05
bEndpointAddress 2 8’h02
bmAttributes 3 8’h02
WmaxPacketSize(L) 4 8’h40/8’h00 *
WmaxPacketSize(M) 5 8’h00/8’h02 *
bInterval 6 8’hFF
Confi guration Descriptor Index Data
bLength 0 8’h07
bDescriptorType 1 8’h05
bEndpointAddress 2 8’h85
bmAttributes 3 8’h02
wMaxPacketSize(L) 4 8’h40/8’h00 *
wMaxPacketSize(M) 5 8’h00/8’h02 *
bInterval 6 8’hFF
Confi guration Descriptor Index Data
bLength 0 8’h07
bDescriptorType 1 8’h05
bEndpointAddress 2 8’h06
bmAttributes 3 8’h02
wMaxPacketSize(L) 4 8’h40/8’h00 *
wMaxPacketSize(M) 5 8’h00/8’h02 *
bInterval 6 8’hFF
* Values for Full Speed and High
Speed USB
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 25
Endpoint-5
Interrupt Endpoint
Confi guration Descriptor Index Data
bLength 0 8’h07
bDescriptorType 1 8’h05
bEndpointAddress 2 8’h89
bmAttributes 3 8’h03
wMaxPacketSize(L) 4 8’h0A
wMaxPacketSize(M) 5 8’h00
bInterval 6 * 8’h01 / 8’h05
(default FS/HS)
* programmable using intr_pg_fs ,
intr_pg_hs
MCS7820
USB-2.0 to Two Serial Ports
Page 26 Rev. 1.2
EEPROM Content Layout
Bytes # of Bytes Name Description
[1:0] 2 EE Check EEPROM Present Check value = 0x9710
[3:2] 2 VID Vendor ID = 0x9710
[5:4] 2 PID Product ID = 0x7840
[7:6] 2 RN Release Number in BCD format = 0x0001
8 1 SER1_DCR0 Device Confi guration Registers (SER1_DCR0)
9 1 SER1_DCR1 Device Confi guration Registers (SER1_DCR1)
10 1 SER1_DCR2 Device Confi guration Registers (SER1_DCR2)
14 1 SER2_DCR0 Device Confi guration Registers (SER2_DCR0)
15 1 SER2_DCR1 Device Confi guration Registers (SER2_DCR1)
16 1 SER2_DCR2 Device Confi guration Registers (SER2_DCR2)
20 1 intr_pg_fs Binterval value for Full Speed
21 1 intr_pg_hs Binterval value for High Speed
[23:22] 2 Language ID Language ID in HEX Format (0x0409 default)
[71:24] 48 Manufacture ID “MosChip Semiconductor” in UNICODE
[113:72] 42 Product Name “USB-Serial Controller” in UNICODE
[129:114] 16 Serial Number “X7X6X5X4X3X2X1X0” in UNICODE
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 27
EEPROM Contents for MCS7820
(Example Contents)
EE_Check,
VID,
PID,
RN,
SER1_DRC0, SER1_DRC1, SER1_DRC2,
Reserved (3),
SER2_DRC0, SER2_DRC1, SER2_DRC2,
Reserved (3),
INTR_PG_FS,
INTR_PG_HS,
Language ID,
Manufacture ID,
MosChip
4D 6F 73 43 68 69 70
Semi conduc t o r
20 53 65 6D 69 63 6F 6E 64 75 63 74 6F 72
Product Name,
USB - Se r i a l
55 53 42 2D 53 65 72 69 61 6C
Con t r o l l er
20 43 6F 6E 74 72 6F 6C 6C 65 72
Serial Number
Location HEX ASCII Location HEX ASCII Location HEX ASCII
0 10 44 6D m 88 61 a
1 97 4500 8900
2 10 46 69 i 90 6C l
3 97 4700 9100
4 40 48 63 c 92 20 Space
5 78 4900 9300
6 01 50 6F o 94 43 C
7 00 5100 9500
8 01 52 6E n 96 6F o
9 85 5300 9700
10 24 54 64 d 98 6E n
11 01 55 00 99 00
12 80 56 75 u 100 74 t
13 24 57 00 101 00
14 01 58 63 c 102 72 r
15 80 59 00 103 00
16 24 60 74 t 104 6F o
17 01 61 00 105 00
18 80 62 6F o 106 6C l
19 24 63 00 107 00
20 01 64 72 r 108 6C l
21 05 65 00 109 00
22 09 66 20 Space 110 65 e
23 04 67 00 111 00
24 4D M 68 20 Space 112 72 r
25 00 69 00 113 00
26 6F o 70 20 Space 114 4D M
27 00 71 00 115 00
28 73 s 72 55 U 116 6F o
29 00 73 00 117 00
30 43 C 74 53 S 118 73 s
31 00 75 00 119 00
32 68 h 76 42 B 120 43 C
33 00 77 00 121 00
34 69 i 78 2D - 122 68 h
35 00 79 00 123 00
36 70 p 80 53 S 124 69 i
37 00 81 00 125 00
38 20 Space 82 65 e 126 70 p
39 00 83 00 127 00
40 53 S 84 72 r 128 20 Space
41 00 85 00 129 00
42 65 e 86 69 i
43 00 87 00
MCS7820
USB-2.0 to Two Serial Ports
Page 28 Rev. 1.2
Device Confi guration Bit Fields and Descriptions
Bytes 8, 9, 10, 14, 15 and 16 form six 8-bit DCR Registers. These Bytes are read from the EEPROM, and
loaded into the Global Device Confi guration Registers after Power-On Reset. They can be programmed by
software using the following application number and register indexes as shown in the table.
EEPROM
Location DCR Bit DCR Name Application
Number Register
Index Default
Value
8 SER1_DCR[7:0] SER1_DCR0 0 4 0x01
9 SER1_DCR[15:8] SER1_DCR1 0 5 0x85
10 SER1_DCR[23:16] SER1_DCR2 0 6 0x24
14 SER2_DCR[7:0] SER2_DCR0 0 25 0x01
15 SER2_DCR[15:8] SER2_DCR1 0 26 0x84
16 SER2_DCR[23:16] SER2_DCR2 0 27 0x24
The following tables describe the function of each bit in the DCR registers. There are three DCR registers
for each Serial Port (IrDA). In the absence of an EEPROM, the default values are taken from the Device
Confi guration Registers.
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 29
Serial Port 1 – Device Confi guration Register 0
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Reserved IrDA_
Mode RTS_
CM GPIO_
Mode Reserved RS_
SDM
DCR0
Bit Name Defi nition Default
Value
0RS_
SDM
RS-232 / RS-422 / RS-485
Transceiver Shut-Down Mode:
0: Do not shut down the transceiver
Even when USB SUSPEND is engaged
1: Shut down the transceiver
when USB SUSPEND is engaged
1
1 Reserved Reserved. 0
[3:2] GPIO_
Mode
00: GPIO = Input
10: GPIO = Output 00
[5:4] RTS_
CM
RTSM RTS Control Method:
00: RTS is controlled by Control Bit Map.
Signal is active low;
01: RTS is controlled by Control Bit Map.
Signal is active high;
10: Drive RTS active
when Downstream Data Buffer is NOT EMPTY;
Otherwise Drive RTS inactive.
11: Drive RTS inactive
when Downstream Data Buffer is NOT EMPTY;
Otherwise Drive RTS active.
00
6IrDA_
Mode 0: RS-232 / RS-422 / RS-485 Serial Port Mode.
1: IrDA Mode. 0
7 Reserved Reserved 0
MCS7820
USB-2.0 to Two Serial Ports
Page 30 Rev. 1.2
Serial Port 1 – Device Confi guration Register 1
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Reserved Interrupt IN
Endpoint
Status
PLL_
Power-Down
Bypass
Control
RW_
INHB Tx_I_
PMG GPIO_I_
PMG
DCR1
Bit Name Defi nition Default
Value
[1:0] GPIO_I_
PMG
These two bits set the output current
of the GPIO lines:
00: 6 mA
01: 8 mA (Default)
10: 10 mA
11: 12 mA
01
[3:2] Tx_I_
PMG
These two bits set the output current
of Serial output signals TxD, DTR_n and RTS_n:
00: 6 mA
01: 8 mA (Default)
10: 10 mA
11: 12 mA
01
4RW_
INHB
RW_INH Remote Wake Inhibit:
0: Enable the USB Remote Wakeup function
1: Inhibit the USB Remote Wakeup function
0
5
PLL_
Power-Down
Bypass
Control
0: Enables PLL Power-Down
1: Disables PLL Power-Down 0
6Interrupt IN
Endpoint
Status
0: Interrupt Endpoint returns 5 Bytes of data.
1: Interrupt Endpoint returns 5 Bytes + 8 Bytes of the Bulk-In/Out
memory controller status 0
7 Reserved Reserved. 1
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 31
Serial Port 1 – Device Confi guration Register 2
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
SHDN_
POL Reserved RWU_
Mode EWU_
Rx EWU_
DSR EWU_
RI EWU_
DCD EWU_
CTS
DCR2
Bit Name Defi nition Default
Value
0EWU_
CTS
Enable Wake Up Trigger on CTS:
0: Disabled
1: Enable Wake Up Trigger on CTS State Changes.
0
1EWU_
DCD
Enable Wake Up Trigger on DCD:
0: Disabled
1: Enable Wake Up Trigger on DCD State Changes.
0
2EWU_
RI
Enable Wake Up Trigger on RI:
0: Disabled
1: Enable Wake Up Trigger on RI State Changes.
1
3EWU_
DSR
Enable Wake Up Trigger on DSR:
0: Disabled
1: Enable Wake Up Trigger on DSR State Changes.
0
4EWU_
Rx
Enable Wake Up Trigger on RXD:
0: Disabled
1: Enable Wake Up Trigger on RXD State Changes.
0
5RWU_
Mode
Remote Wakeup Mode:
0: Engages Remote Wakeup,
The device issues Disconnect Signal.
1: Engages Remote Wakeup,
The device issues Resume Signal.
1
6 Reserved Reserved. 0
7SHDN_
POL
SHDN Polarity:
0: Pin 12 Active Low Shut-Down Signal.
1: Pin 12 Active High Shut-Down Signal.
0
Note: Wake up defi ned above only works when DCR0[6] = 0 and DCR1[4] = 0.
MCS7820
USB-2.0 to Two Serial Ports
Page 32 Rev. 1.2
Serial Port 2 – Device Confi guration Register 0
The Confi guration Registers for this Serial Port are very similar to Serial Port 1, but have a few less
confi guration options.
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Reserved IrDA_
Mode RTS_
CM Reserved Reserved RS_
SDM
DCR0
Bit Name Defi nition Default
Value
0RS_
SDM
RS-232 / RS-422 / RS-485
Transceiver Shut-Down Mode:
0: Do not shut down the transceiver
Even when USB SUSPEND is engaged
1: Shut down the transceiver
when USB SUSPEND is engaged
1
[3:1] Reserved Reserved 000
[5:4] RTS_
CM
RTSM RTS Control Method:
00: RTS is controlled by Control Bit Map.
Signal is active low;
01: RTS is controlled by Control Bit Map.
Signal is active high;
10: Drive RTS active
when Downstream Data Buffer is NOT EMPTY;
Otherwise Drive RTS inactive.
11: Drive RTS inactive
when Downstream Data Buffer is NOT EMPTY;
Otherwise Drive RTS active.
00
6IrDA_
Mode 0: RS-232 / RS-422 / RS-485 Serial Port Mode.
1: IrDA Mode. 0
7 Reserved Reserved 0
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 33
Serial Port 2 – Device Confi guration Register 1
The Confi guration Registers for this Serial Port are very similar to Serial Port 1, but have a few less
confi guration options.
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Reserved Reserved Reserved RW_
INHB Tx_I_
PMG Reserved
DCR1
Bit Name Defi nition Default
Value
[1:0] Reserved Reserved 00
[3:2] Tx_I_
PMG
These two bits set the output current
of Serial output signals TxD, DTR_n and RTS_n:
00: 6 mA
01: 8 mA (Default)
10: 10 mA
11: 12 mA
01
4RW_
INHB
RW_INH Remote Wake Inhibit:
0: Enable the USB Remote Wakeup function
1: Inhibit the USB Remote Wakeup function
0
[7:5] Reserved Reserved 0
MCS7820
USB-2.0 to Two Serial Ports
Page 34 Rev. 1.2
Serial Port 2 – Device Confi guration Register 2
The Confi guration Registers for this Serial Port are very similar to Serial Port 1, but have a few less
confi guration options.
Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
Reserved Reserved RWU_
Mode EWU_
Rx EWU_
DSR EWU_
RI EWU_
DCD EWU_
CTS
DCR2
Bit Name Defi nition Default
Value
0EWU_
CTS
Enable Wake Up Trigger on CTS:
0: Disabled
1: Enable Wake Up Trigger on CTS State Changes.
0
1EWU_
DCD
Enable Wake Up Trigger on DCD:
0: Disabled
1: Enable Wake Up Trigger on DCD State Changes.
0
2EWU_
RI
Enable Wake Up Trigger on RI:
0: Disabled
1: Enable Wake Up Trigger on RI State Changes.
1
3EWU_
DSR
Enable Wake Up Trigger on DSR:
0: Disabled
1: Enable Wake Up Trigger on DSR State Changes.
0
4EWU_
Rx
Enable Wake Up Trigger on RXD:
0: Disabled
1: Enable Wake Up Trigger on RXD State Changes.
0
5RWU_
Mode
Remote Wakeup Mode:
0: Engages Remote Wakeup,
The device issues Disconnect Signal.
1: Engages remote wakeup,
the Device issues resume signal.
1
[7:6] Reserved Reserved. 0
Note: Wake up defi ned above only works when DCR0[6] = 0 and DCR1[4] = 0.
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 35
Electrical Specifi cations
Absolute Maximum Ratings:
Core Power Supply (VccK) -0.3 to 2.16 V
Power Supply of 3.3V I/O (Vcc3I0) -0.3 to 4.0 V
Input Voltage of 3.3V I/O (Vin3 ) -0.3 to 4.0 V
Input Voltage of 5V Tolerant I/O (Vin5) -0.3 to 5.8 V
Operating Temperature 0 to +70 °C
Storage Temperature -40 to +150 °C
ESD HBM (MIL-STD 883E Method 3015-7 Class 2) 2000 V
ESD MM (JEDEC EIA/JESD22 A115-A) 200 V
CDM (JEDEC/JESD22 C101-A) 500 V
Latch-up (JESD No. 78, March 1997) 200 mA, 1.5 x VCC
Junction Temperature (Tj) 115 °C
Thermal Resistance of Junction to Ambient (Still Air) 80 °C/W
Operating Conditions:
Symbol Parameter Min Typ Max Units
Vcc5A 5V Power Supply Input 4.5 5.0 5.5 V
VccKCore Power Supply 1.62 1.8 1.98 V
Vcc3IO Power Supply of 3.3V I/O 2.97 3.3 3.63 V
REG02_V18 1.8V Regulator Output 1.71 1.8 1.89 V
IREG02_V18 1.8V Regulator Current 70 mA
REG06_VCC33 3.3V Regulator Output 3.14 3.3 3.46 V
IREG06_VCC33 3.3V Regulator Current 250 mA
I5V Operating current of 5V when 3.3V and 1.8V
internal regulators are used. No serial load. 70 mA
I3.3V Operating current of 3.3V. No serial load. 45 mA
I1.8V Operating current of 1.8V. No serial load. 25 mA
MCS7820
USB-2.0 to Two Serial Ports
Page 36 Rev. 1.2
DC Characteristics of 3.3V I/O Cells
Symbol Parameter Condition Min Typ Max Units
VccKCore Power Supply Core Area 1.62 1.8 1.98 V
Vcc3IO Power Supply 3.3V I/O 2.97 3.3 3.63 V
ViLInput Low Voltage LVTTL 0.8 V
ViHInput High Voltage LVTTL 2.0 V
Vt Switching Threshold LVTTL 1.5 V
Vt-
Vt+ Schmitt T rigger
Threshold Voltage LVTTL 0.8 1.1
1.6 2.0 V
VoLOutput Low Voltage IoL= 2 to 24mA 0.4 V
VoHOutput High Voltage IoH= -2 to -24mA 2.4 V
DC Characteristics of 5V Tolerant I/O Cells
Symbol Parameter Condition Min Typ Max Units
Vcc5A 5V Power Supply 5V I/O 4.5 5.0 5.5 V
ViLInput Low Voltage LVTTL 0.8 V
ViHInput High Voltage LVTTL 2.0 V
Vt Switching Threshold LVTTL 1.5 V
Vt-
Vt+ Schmitt T rigger
Threshold Voltage LVTTL 0.8 1.1
1.6 2.0 V
VoHOutput Low Voltage IoL= 2 to 24 mA 0.4 V
VoHOutput High Voltage IoH= -2 to -24 mA 2.4 V
MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 37
SYMBOL MILLIMETERS
MIN TYPICAL MAX
A1 0.05 0.15
A2 1.35 1.45
b0.17 0.27
c0.09 0.20
e0.50
L0.45 0.75
HD 8.80 9.20
D6.80 7.20
HE 8.80 9.20
E6.80 7.20
48-Pin “CV” LQFP
Package Dimensions
E
HE
D
HD
e
b
A2
A1
L
c
1
12
13 24
36
48
25
37
MCS7820
USB-2.0 to Two Serial Ports
Page 38 Rev. 1.2
IMPORTANT NOTICE
MosChip Semiconductor Technology, LTD products are not authorized for use as critical components in life
support devices or systems. Life support devices are applications that may involve potential risks of death,
personal injury or severe property or environmental damages. These critical components are semiconductor
products whose failure to perform can be reasonably expected to cause the failure of the life support systems
or device, or to adversely impact its effectiveness or safety. The use of MosChip Semiconductor Technology
LTD’s products in such devices or systems is done so fully at the customer risk and liability.
As in all designs and applications it is recommended that the customer apply suffi cient safeguards and guard
bands in both the design and operating parameters. MosChip Semiconductor Technology LTD assumes no
liability for customer’s applications assistance or for any customer’s product design(s) that use MosChip
Semiconductor Technology, LTD’s products.
MosChip Semiconductor Technology, LTD warrants the performance of its products to the current specifi cations
in effect at the time of sale per MosChip Semiconductor Technology, LTD standard limited warranty. MosChip
Semiconductor Technology, LTD imposes testing and quality control processes that it deems necessary to
support this warranty. The customer should be aware that not all parameters are 100% tested for each device.
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MCS7820
USB-2.0 to Two Serial Ports
Rev. 1.2 Page 39
Revision History
Revision Changes Date
0.1 Preliminary Release. 19-May-2006
0.2 Switched to new Page-1 Layout. 30-May-2006
0.3 Corrected MaxPacketSize, Endpoint Numbers, Package dimensions. 31-May-2006
0.4 Corrected Wlength fi elds in “Set Application Vendor Specifi c Command”. 05-Jun-2006
1.0
Removed Preliminary Notice.
Made change throughout to refl ect one GPIO port instead of two.
Added Driver Support entries on page 1.
Made bits 2 and 3 of the MCR register reserved.
Made bit 5 of the Mode register reserved.
Replaced Raid_reg1 with Rx_sampling_reg1 throughout document.
Modifi ed product ID value in EEPROM Content Layout table.
Modifi ed description of bits 3, 2, and 1 of Device Confi guration register 0.
Made bit 6 of Device Confi guration register 2 reserved and added note.
28-Aug-2006
1.1 Clarifi ed Linux Kernel support in Features.
Deleted Windows CE5.0 and Vista release dates.
Verifi ed state of all Reserved fi eld default values. 16-Sept-2006
1.2
Updated Absolute Maximum Rating table
Deleted Leakage Current table
Updated Operating Conditions table
Updated 3.3V DC Characteristics table
Updated 5V DC Characteristics table
Removed dimensions in Inches from Package Dimensions table
Removed ‘Confi dential’ notice from all pages
5-August-2007
