SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I − OCTOBER 1995 − REVISED JULY 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DOperating Range 2-V to 5.5-V VCC
DLatch-Up Performance Exceeds 250 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54AHC86 ...J OR W PACKAGE
SN74AHC86 ...D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
VCC
4B
4A
4Y
3B
3A
3Y
3212019
910111213
4
5
6
7
8
18
17
16
15
14
4A
NC
4Y
NC
3B
1Y
NC
2A
NC
2B
1B
1A
NC
3Y
3A
V
4B
2Y
GND
NC
SN54AHC86 . . . FK PACKAGE
(TOP VIEW)
CC
NC − No internal connection
SN74AHC86 . . . RGY PACKAGE
(TOP VIEW)
114
78
2
3
4
5
6
13
12
11
10
9
4B
4A
4Y
3B
3A
1B
1Y
2A
2B
2Y
1A
3Y V
GND
CC
description/ordering information
The ’AHC86 devices are quadruple 2-input exclusive-OR gates. These devices perform the Boolean function
Y = A ⊕ B or Y = AB + AB in positive logic.
A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74AHC86RGYR HA86
PDIP − N Tube SN74AHC86N SN74AHC86N
SOIC D
Tube SN74AHC86D
AHC86
SOIC − D Tape and reel SN74AHC86DR AHC86
−40°C to 85°CSOP − NS Tape and reel SN74AHC86NSR AHC86
SSOP − DB Tape and reel SN74AHC86DBR HA86
TSSOP PW
Tube SN74AHC86PW
HA86
TSSOP − PW Tape and reel SN74AHC86PWR HA86
TVSOP − DGV Tape and reel SN74AHC86DGVR HA86
CDIP − J Tube SNJ54AHC86J SNJ54AHC86J
−55°C to 125°CCFP − W Tube SNJ54AHC86W SNJ54AHC86W
55 C
to
125 C
LCCC − FK Tube SNJ54AHC86FK SNJ54AHC86FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I − OCTOBER 1995 − REVISED JULY 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each gate)
INPUTS OUTPUT
A B
OUTPUT
Y
L L L
LHH
HLH
H H L
exclusive-OR logic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
= 1
EXCLUSIVE OR
These are five equivalent exclusive-OR symbols valid for an SN74AHC86 gate in positive logic; negation may be shown at any two ports.
= 2k 2k + 1
LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT ODD-PARITY ELEMENT
The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).
The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.
The output is active (high) if
an odd number of inputs
(i.e., only 1 of the 2) are
active.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I − OCTOBER 1995 − REVISED JULY 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54AHC86 SN74AHC86
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 3 V 2.1 2.1 V
VIH
High level
input
voltage
VCC = 5.5 V 3.85 3.85
V
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 3 V 0.9 0.9 V
VIL
Low level
input
voltage
VCC = 5.5 V 1.65 1.65
V
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V −50 −50 mA
IOH High-level output current VCC = 3.3 V ± 0.3 V −4 −4
mA
IOH
High level
output
current
VCC = 5 V ± 0.5 V −8 −8 mA
VCC = 2 V 50 50 mA
IOL Low-level output current VCC = 3.3 V ± 0.3 V 4 4
mA
IOL
Low level
output
current
VCC = 5 V ± 0.5 V 8 8 mA
Δt/Δv
Input transition rise or fall rate
VCC = 3.3 V ± 0.3 V 100 100
ns/V
Δt/ΔvInput transition rise or fall rate VCC = 5 V ± 0.5 V 20 20 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C SN54AHC86 SN74AHC86
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT
2 V 1.9 2 1.9 1.9
IOH = −50 mA3 V 2.9 3 2.9 2.9
V
OH
IOH
50
mA
4.5 V 4.4 4.5 4.4 4.4 V
VOH
IOH = −4 mA 3 V 2.58 2.48 2.48
V
IOH = −8 mA 4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
IOL = 50 mA3 V 0.1 0.1 0.1
V
OL
IOL
50
mA
4.5 V 0.1 0.1 0.1 V
VOL
IOL = 4 mA 3 V 0.36 0.5 0.44
V
IOL = 8 mA 4.5 V 0.36 0.5 0.44
IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1mA
ICC VI = VCC or GND, IO = 0 5.5 V 2 20 20 mA
CiVI = VCC or GND 5 V 4 10 10 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I − OCTOBER 1995 − REVISED JULY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHC86 SN74AHC86
UNIT
PARAMETER
(INPUT)
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
C15 pF
7* 11* 1* 13* 1 13
ns
tPHL
A or B Y CL = 15 pF 7* 11* 1* 13* 1 13 ns
tPLH
C=50pF
9.5 14.5 1 16.5 1 16.5
ns
tPHL
A or B Y CL = 50 pF 9.5 14.5 1 16.5 1 16.5 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHC86 SN74AHC86
UNIT
PARAMETER
(INPUT)
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
C15 pF
4.8* 6.8* 1* 8* 1 8
ns
tPHL
A or B Y CL = 15 pF 4.8* 6.8* 1* 8* 1 8 ns
tPLH
C=50pF
6.3 8.8 1 10 1 10
ns
tPHL
A or B Y CL = 50 pF 6.3 8.8 1 10 1 10 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 5)
PARAMETER
SN74AHC86
UNIT
PARAMETER MIN TYP MAX UNIT
VOL(P) Quiet output, maximum dynamic VOL 0.3 0.8 V
VOL(V) Quiet output, minimum dynamic VOL −0.3 −0.8 V
VOH(V) Quiet output, minimum dynamic VOH 4.4 V
VIH(D) High-level dynamic input voltage 3.5 V
VIL(D) Low-level dynamic input voltage 1.5 V
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 18 pF
SN54AHC86, SN74AHC86
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SCLS249I − OCTOBER 1995 − REVISED JULY 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
≈VCC
0 V
50% VCC VOL + 0.3 V
50% VCC
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 kΩ
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH − 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9681601Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9681601QCA ACTIVE CDIP J 14 1 TBD Call TI Call TI
5962-9681601QDA ACTIVE CFP W 14 1 TBD Call TI Call TI
SN74AHC86D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DBLE OBSOLETE SSOP DB 14 TBD Call TI Call TI
SN74AHC86DBR ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DBRE4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DBRG4 ACTIVE SSOP DB 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DE4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DGVRE4 ACTIVE TVSOP DGV 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DGVRG4 ACTIVE TVSOP DGV 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86N ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AHC86NE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
SN74AHC86NSR ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74AHC86NSRE4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86NSRG4 ACTIVE SO NS 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86PW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86PWLE OBSOLETE TSSOP PW 14 TBD Call TI Call TI
SN74AHC86PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74AHC86RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74AHC86RGYRG4 ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SNJ54AHC86FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54AHC86J ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type
SNJ54AHC86W ACTIVE CFP W 14 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC86, SN74AHC86 :
•Catalog: SN74AHC86
•Military: SN54AHC86
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHC86DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74AHC86DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHC86DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AHC86NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AHC86PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHC86RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC86DBR SSOP DB 14 2000 367.0 367.0 38.0
SN74AHC86DGVR TVSOP DGV 14 2000 367.0 367.0 35.0
SN74AHC86DR SOIC D 14 2500 367.0 367.0 38.0
SN74AHC86NSR SO NS 14 2000 367.0 367.0 38.0
SN74AHC86PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74AHC86RGYR VQFN RGY 14 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194