ESMT
M13S2561616A (2A)
Operation Temperature Condition -40°C~85°C
Elite Semiconductor Memory Technology Inc. Publication Date : Sep. 2012
Revision : 1.1 16/49
Burst Address Ordering for Burst Length
Burst
Length
Starting
Address (A2, A1, A0) Sequential Mode Interleave Mode
xx0 0, 1 0, 1
2 xx1 1, 0 1, 0
x00 0, 1, 2, 3 0, 1, 2, 3
x01 1, 2, 3, 0 1, 0, 3, 2
x10 2, 3, 0, 1 2, 3, 0, 1
4
x11 3, 0, 1, 2 3, 2, 1, 0
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
8
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
DLL Enable / Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning
to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode,
the DLL is enabled automatically). Any time the DLL is enabled, 200 clock cycles must occur before a READ command
can be issued.
Output Drive Strength
The normal drive strength for all outputs is specified to be SSTL_2, Class II. The device also support reduced drive
strength options, intended for lighter load and/or point-to-point environments.
Mode Register
01 234 567
COMMAND
tCK
Precharge
All Banks MRS / EMRS
tRP
*2
*1
CLK
CLK
Any
Command
tMRD
*1: MRS/EMRS can be issued only at all banks precharge state.
*2: Minimum tRP is required to issue MRS/EMRS command.