NJW1109
– 1 –
Headphone Amplifier with Electronic Volume
■
■■
■ GENERAL DESCRIPTION
The NJW1109 is a headphone amplifier with electronic volume. It
includes widely gain adjustable volume, +20 to –80 dB, and mute
function. These are controlled by I
2
C bus. The NJW1109 is
suitable for headphone output on TV set.
■
■■
■ FEATURES
● Operating Voltage 7.5 to 10 V
● Electronic Volume +20dB to -80dB / 0.5dB step, Mute
● I
2
C Bus Interface
● Bi-CMOS Technology
● Package Outline DIP14, DMP14, SSOP14
■
■■
■ BLOCK DIAGRAM
■
■■
■ PIN FUNCTION
■
■■
■PACKAGE OUTLINE
1
7 8
14
No.
SYMBOL
FUNCTION No.
SYMBOL
FUNCTION
1 V+ Power Supply 8 SCL I
2
C Bus Clock Input
2 OUTb Bch Output
9 Vref Reference voltage stabilized
capacitor connect terminal
3 N.C. No Connect 10 INa Ach Input
4 CAPb Balance control click noise
absorbing capacitor connect
terminal
11 CAPa Volume control click noise
absorbing capacitor connect
terminal
5 INb Bch Input
12 N.C. No Connect
6 ADR I
2
C Bus Slave Address
Select
13 OUTa Ach Output
7 SDA I
2
C Bus Data Input 14 GND Ground
NJW1109D NJW1109M NJW1109V
VOL
IN b
IN a
VOL
Vref
V+ GND
OUTa
OUTb
ADR
Bias
I
2
C
CAPa
CAPb
Interface
SDA SCL
NJW1109
– 2 –
■
■■
■ ABSOLUTE MAXIMUM RATING (Ta=25°
°°
°C)
PARAMETER SYMBOL RATING UNIT
Supply Voltage V
+
12 V
Power Dissipation P
D
500 (DIP14)
500* (DMP14)
440* (SSOP14)
mW
Operating Temperature Range Topr -20 to +75 °C
Storage Temperature Range Tstg -40 to +125 °C
*(Note) EIA/JEDEC STANDARD Test board(76.2 x 114.3 x 1.6mm, 2layers, FR-4)mounting
■
■■
■ ELECTRICAL CHARACTERISTICS
(V
+
=9V, V
IN
=-20dBV, f=1kHz, R
L
=100Ω,
VOL = 0dB
, Ta=25
°C
)
●
●●
●POWER SUPPLY
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Operating Voltage V
+
7.5 9 10 V
Operating Current I
CC
No Signal - 5 8 mA
Reference Voltage V
REF
4.0 4.5 5.0 V
●
●●
●AMPLIFIER
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Volume Maximum Gain G
VMAX
VOL = +20dB setting
18 20 22 dB
Volume Minimum Gain G
VMIN
VOL = -80dB setting
-80
Voltage Gain Channel Balance ∆Gv
VOL = 0dB setting
-1.5 0 1.5 dB
Maximum Input Voltage V
IM
VOL = -10dB setting
THD=3%
8.9
(2.8)
9.5
(3.0) - dBV
(Vrms)
Output Power P
O
VOL = 10dB,
THD=10%
70 100 - mW
Total Harmonic Distortion THD
VOL = 0dB setting
- 0.1 1 %
Channel Separation CS
Rg=600Ω, Vin = 0dBV
70 80 - dB
Mute Level Mute
VOL =
Mute, Vin = 0dBV
- -100 -90 dB
Output Noise Voltage 1 V
NO1
Rg=0Ω, A-Weighted
- -95
(18)
-85
(56)
dBV
(µVrms)
Output Noise Voltage 2 V
NO2
VOL =
Mute
Rg=0Ω, A-Weighted
- -105
(5.6)
-95
(18)
dBV
(µVrms)
Power Supply Ripple Rejection PSRR
Vripple=-20dBV, Rg=0Ω
- 70 - dB
●
●●
●CONTROL
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
High Level Input Voltage
V
ADRH
High : Slave Address 84H
V
+
/2 - - V
Low Level Input Voltage
V
ADRL
Low : Slave Address 80H
- - 1.0 V
NJW1109
– 3 –
!TIMING ON THE I
2
C BUS (SDA,SCL)
!CHARACTERISTICS OF I/O STAGES FOR I
2
C BUS (SDA,SCL)
I
2
C BUS Load Conditions
STANDARD MODE : Pull up resistance 4kΩ (Connected to +5V), Load capacitance 200pF (Connected to GND)
FAST MODE : Pull up resistance 4k
Ω
(Connected to +5V), Load capacitance 50pF (Connected to GND)
Standard mode Fast mode
PARAMETER SYMBOL
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT
Low Level Input Voltage V
IL
0.0 - 1.5 0.0 - 1.5 V
High Level Input Voltage V
IH
2.5 - 5.0 2.5 - 5.0 V
Low level output voltage (3mA at SDA pin) V
OL
0 - 0.4 0 - 0.4 V
Input current each I/O pin with an input voltage
between 0.1V
DD
and 0.9V
DDmax
I
i
-10 - 10 -10 - 10 µA
SDA
SCL
t
f
t
HD:STA
t
LOW
t
r
t
HD:DAT
t
HIGH
t
f
t
SU:DAT
S
t
SU:STA
t
HD:STA
t
SP
t
SU:STO
Sr
t
r
t
BUF
PS
NJW1109
– 4 –
!CHARACTERISTICS OF BUS LINES (SDA,SCL) FOR I
2
C-BUS DEVICES
Standard mode Fast mode
PARAMETER SYMBOL
MIN. TYP. MAX. MIN. TYP. MAX.
UNIT
SCL clock frequency f
SCL
- - 100 - - 400 kHz
Hold time (repeated) START condition. t
HD:STA
4.0 - - 0.6 - - µs
Low period of the SCL clock t
LOW
4.7 - - 1.3 - - µs
High period of the SCL clock t
HIGH
4.0 - - 0.6 - - µs
Set-up time for a repeated START condition t
SU:STA
4.7 - - 0.6 - - µs
Data hold time
NOTE)
t
HD:DAT
0 - - 0 - - µs
Data set-up time t
SU:DAT
250 - - 100 - - ns
Rise time of both SDA and SCL signals t
r
- - 1000 - - 300 ns
Fall time of both SDA and SCL signals t
f
- - 300 - - 300 ns
Set-up time for STOP condition t
SU:STO
4.0 - - 0.6 - - µs
Bus free time between a STOP and START condition t
BUF
4.7 - - 1.3 - - µs
Capacitive load for each bus line C
b
- - 400 - - 400 pF
Noise margin at the Low level V
nL
0.5 - - 0.5 - - V
Noise margin at the High level
V
nH
1 - - 1 - -
V
C
b
; total capacitance of one bus line in pF.
NOTE). Data hold time : t
HD:DAT
Please hold the Data Hold Time (t
HD:DAT
) to 300ns or more to avoid status of unstable at SCL falling edge.
The SDA block in the NJW1109 does not hold data. Add external data-delay-circuit of the SDA terminal, in case of not
providing a hold time of at least 300nsec for the SDA in the master device.
The time-consists of the data-delay-circuit of the SDA terminal are as follows.
(a) Low level ! High level : T
LH
≈ R
P
*C
D
(b) High level ! Low level : T
HL
≈ R
D
*C
D
In addition, Schottky barrier diode (SBD) influences a Low level at the Acknowledge. Therefore choose the low forward
voltage (Vf) as much as possible.
MA STER
SCL
SDA
V
DD
R
P
R
P
R
D
SBD
C
D
NJW1109
NJW1109
– 5 –
■
■■
■TERMINAL DESCRIPTION
No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE
5
10
INb
INa
Bch Input
Ach Input
V+/2
2
13
OUTb
OUTa
Bch Output
Ach Output
V+/2
4 CAPb
Balance control click noise
absorbing capacitor connect
terminal
3.8V
11 CAPa
Volume control click noise
absorbing capacitor connect
terminal
3.1V
17k
12k
8k
8k
NJW1109
– 6 –
■
■■
■TERMINAL DESCRIPTION
No. SYMBOL FUNCTION EQUIVALENT CIRCUIT VOLTAGE
6 ADR
I
2
C Bus Slave Address
Select
-
7
8
SDA
SCL
I
2
C Bus Data Input
I
2
C Bus Clock Input
-
9 Vref
Reference voltage stabilized
capacitor connect terminal
V+/2
1 V+ Power Supply - -
14 GND Ground - -
12k
4k
12k
4k
1.3k
200k
200k
NJW1109
– 7 –
■
■■
■ TEST CIRCUIT
TEST CIRCUIT
1 (G
VMAX
, G
VMIN
, ∆Gv,
V
IM
, P
O
, THD, Mute)
0.47
µ
F
10
µ
F100
µ
F
Input A
Output A
Input B Output B
10
µ
F
0.47
µ
F100
µ
F
1
µ
F
1
µ
F
100Ω
100 Ω
V+
BPF:400Hz to 30KHz
BPF:400Hz to 30KHz
76 5 4321
89 10 11 12 13 14
VOL
CAPbADR INb NC OUTbSDA V+
CAPaVref INa NC OUTaSCL GND
VOL
Bias
I
2
C Bus
Interface
V
ADRL
V
ADRH
NJW1109
– 8 –
TEST CIRCUIT
2 (Icc, V
REF
, V
NO1
,V
NO2
)
0.47
µ
F
10
µ
F
100
µ
F
Input A
Output A
Input B Output B
10
µ
F
0.47
µ
F100
µ
F
1
µ
F
1
µ
F
100Ω
100 Ω
A
-Weighted
A
-Weighted
7 6 54321
8 9 10 11 12 13 14
VOL
CAPbADR INb NC OUTbSDA V+
CAPaVref INa NC OUTaSCL GND
VOL
Bias
I
2
C Bus
Interface
V
ADRL
V
ADRH
[V
REF
]
V+
[Icc]
NJW1109
– 9 –
TEST CIRCUIT
3 (CS)
0.47
µ
F
10
µ
F
100
µ
F
Input A
Output A
Input B
10
µ
F
0.47
µ
F
100
µ
F
1
µ
F
1
µ
F
100 Ω
100 Ω
Rg=600 Ω
BPF:400Hz to 30KHz
BPF:400Hz to 30KHz
Rg=600 Ω
Rg=600 Ω
7 6 54321
8 9 10 11 12 13 14
VOL
CAPbADR INb NC OUTbSDA V+
CAPaVref INa NC OUTaSCL GND
VOL
Bias
I
2
C Bus
Interface
V
A
DRL
V
A
DRH
V+
Output B
NJW1109
– 10 –
TEST CIRCUIT
4 (PSRR)
0.47
µ
F
10
µ
F
100
µ
F
Input A
Output A
Input B Output B
10
µ
F
0.47
µ
F
100
µ
F
1
µ
F
1
µ
F
100 ΩBPF:400Hz to 30KHz
Rg=0 Ω
100 ΩBPF:400Hz to 30KHz
Rg=0 Ω
V+
76 5 4321
89 10 11 12 13 14
VOL
CAPbADR INb NC OUTbSDA V+
CAPaVref INa NC OUTaSCL GND
VOL
Bias
I
2
C Bus
Interface
V
ADRL
V
A
DRH
NJW1109
– 11 –
■
APPLICATION CIRCUIT
0.47
µ
F
10
µ
F100
µ
F
Input A
Input B
10
µ
F
0.47
µ
F 100
µ
F
1
µ
F
1
µ
F
V+
7 6 5 4 3 2 1
8 9 10 11 12 13 14
VOL
CAPbADR INb NC OUTbSDA V+
CAPaVref INa NC OUTaSCL GND
VOL
Bias
I
2
C Bus
Interface
Output B
30Ω
Output A
30 Ω
30Ω
30 Ω
Mute
Mute
NJW1109
– 12 –
■
■■
■ DEFINITION OF I
2
C REGISTER
●
●●
● I
2
C BUS FORMAT
MSB LSB MSB LSB MSB LSB
S Slav e Address A Select Address A Data A P
1bit 8bit 1bit 8bit 1bit 8bit 1bit 1bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
●
●●
● SL AVE ADDRE SS
MSB LSB
1 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0
●
●●
● SELECT ADDRE SS
The auto-increment function cycles the select address as follows.
00H→01H→00H
BIT
Select
Address D7 D6 D5 D4 D3 D2 D1 D0
00H VOL
01H CHS BAL Don’t Care
!CONTROL REGISTER DEFAULT VALUE
Control register default value is all “0”.
BIT
Select
Address D7 D6 D5 D4 D3 D2 D1 D0
00H 0 0 0 0 0 0 0 0
01H 0 0 0 0 0 0 0 0
!CONTROL COMMAND TABLE
a) Master Volume
BIT
Select
Address D7 D6 D5
D4 D3 D2 D1 D0
00H VOL
•
••
•VOL : Master Volume
Attenuation level : +20 to –80dB(0.5dB/step), MUTE
b) Balance
BIT
Select
Address D7 D6 D5
D4 D3 D2 D1 D0
01H CHS BAL Don’t Care
•
••
•CHS : Balance channel select
“0” : Ach “Bch is attenuated” “1” : Bch “Ach is attenuated”
•
••
•BAL : Ac h and Bch Ac h and Bch Balance
Balance Level : 0 to –30dB (1dB/Step) , MUTE
80H (ADR = Low)
84H (ADR = High)
NJW1109
– 13 –
!CONTROL COMMAND TABLE
a) Master Volume (Select Address: 00H)
Volume level : +20 to –80dB(0.5dB/step), MUTE
VOL
Gain(dB) HEX D7 D6 D5 D4 D3 D2 D1 D0
20 FF 1 1 1 1 1 1 1 1
19.5 FE 1 1 1 1 1 1 1 0
19 FD 1 1 1 1 1 1 0 1
18.5 FC 1 1 1 1 1 1 0 0
18 FB 1 1 1 1 1 0 1 1
17.5 FA 1 1 1 1 1 0 1 0
17 F9 1 1 1 1 1 0 0 1
16.5 F8 1 1 1 1 1 0 0 0
16 F7 1 1 1 1 0 1 1 1
15.5 F6 1 1 1 1 0 1 1 0
15 F5 1 1 1 1 0 1 0 1
14.5 F4 1 1 1 1 0 1 0 0
14 F3 1 1 1 1 0 0 1 1
13.5 F2 1 1 1 1 0 0 1 0
13 F1 1 1 1 1 0 0 0 1
12.5 F0 1 1 1 1 0 0 0 0
12 EF 1 1 1 0 1 1 1 1
11.5 EE 1 1 1 0 1 1 1 0
11 ED 1 1 1 0 1 1 0 1
10.5 EC 1 1 1 0 1 1 0 0
10 EB 1 1 1 0 1 0 1 1
9.5 EA 1 1 1 0 1 0 1 0
9 E9 1 1 1 0 1 0 0 1
8.5 E8 1 1 1 0 1 0 0 0
8 E7 1 1 1 0 0 1 1 1
7.5 E6 1 1 1 0 0 1 1 0
7 E5 1 1 1 0 0 1 0 1
6.5 E4 1 1 1 0 0 1 0 0
6 E3 1 1 1 0 0 0 1 1
5.5 E2 1 1 1 0 0 0 1 0
5 E1 1 1 1 0 0 0 0 1
4.5 E0 1 1 1 0 0 0 0 0
4 DF 1 1 0 1 1 1 1 1
3.5 DE 1 1 0 1 1 1 1 0
3 DD 1 1 0 1 1 1 0 1
･･･ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・
-79.5 38 0 0 1 1 1 0 0 0
-80 37 0 0 1 1 0 1 1 1
･･･ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・ ・・・
Mute 00 0 0 0 0 0 0 0 0
NJW1109
– 14 –
b) Balance (Select Address: 01H)
Balance level : 0 to –30dB(1dB/step), MUTE
Channel Setting (CHS) D7
Attenuated Bch Gain 0
Attenuated Ach Gain 1
BAL
Gain(dB) D6 D5 D4 D3 D2
0 0 0 0 0 0
-1 0 0 0 0 1
-2 0 0 0 1 0
-3 0 0 0 1 1
-4 0 0 1 0 0
-5 0 0 1 0 1
-6 0 0 1 1 0
-7 0 0 1 1 1
-8 0 1 0 0 0
-9 0 1 0 0 1
-10 0 1 0 1 0
-11 0 1 0 1 1
-12 0 1 1 0 0
-13 0 1 1 0 1
-14 0 1 1 1 0
-15 0 1 1 1 1
-16 1 0 0 0 0
-17 1 0 0 0 1
-18 1 0 0 1 0
-19 1 0 0 1 1
-20 1 0 1 0 0
-21 1 0 1 0 1
-22 1 0 1 1 0
-23 1 0 1 1 1
-24 1 1 0 0 0
-25 1 1 0 0 1
-26 1 1 0 1 0
-27 1 1 0 1 1
-28 1 1 1 0 0
-29 1 1 1 0 1
-30 1 1 1 1 0
MUTE 1 1 1 1 1
NJW1109
– 15 –
[CAUTION]
The specifications on this data book are only
given for information, without any guarantee
as regards either mistakes or omissions. The
application circuits in this data book are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
