IDT71P74104S300BQ - Integrated Device Technology, Inc.

MARCH 2004

DSC-6111/00

1

18Mb Pipelined

QDR™II SRAM

Burst of 4

Advance

Information

IDT71P74204

IDT71P74104

IDT71P74804

IDT71P74604

Features

◆18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)

◆Separate, Independent Read and Write Data Ports

- Supports concurrent transactions

◆Dual Echo Clock Output

◆4-Word Burst on all SRAM accesses

◆Multiplexed Address Bus One Read or One Write request

per clock cycle

◆DDR (Double Data Rate) Data Bus

- Four word burst data per two clock cycles on

each port

- Four word transfers per clock cycle

◆Depth expansion through Control Logic

◆HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V .

◆Scalable output drivers

- Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V .

- Output Impedance adjustable from 35 ohms to 70

ohms

◆1.8V Core V oltage (VDD)

◆165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package

◆JT AG Interface

Description

The IDT QDRIITM Burst of four SRAMs are high-speed synchronous

memories with independent, double-data-rate (DDR), read and write

data ports. This scheme allows simultaneous read and write access for

the maximum device throughput, with four data items passed with each

read or write. Four data word transfers occur per clock cycle, providing

quad-data-rate (QDR) performance. Comparing this with standard SRAM

common I/O (CIO), single data rate (SDR) devices, a four to one in-

crease in data access is achieved at equivalent clock speeds. Consider-

ing that QDRII allows clock speeds in excess of standard SRAM de-

vices, the throughput can be increased well beyond four to one in most

applications.

Using independent ports for read and write data access, simplifies

system design by eliminating the need for bi-directional buses. All buses

associated with the QDRII are unidirectional and can be optimized for

signal integrity at very high bus speeds. The QDRII has scalable output

impedance on its data output bus and echo clocks, allowing the user to

tune the bus for low noise and high performance.

The QDRII has a single SDR address bus with read addresses and

write addresses multiplexed. The read and write addresses interleave

with each occurring a maximum of every other cycle. In the event that no

operation takes place on a cycle, the subsequest cycle may begin with

either a read or write. During write operations, the writing of individual

bytes may be blocked through the use of byte or nibble write control

signals.

The QDRII has echo clocks, which provide the user with a clock

Functional Block Diagram

DATA

REG

ADD

REG

CTRL

LOGIC

CLK

GEN

(

Note1

)

D

(

Note2

)

SA

R

W

(

Note3

)

BW

x

K

C

SELECT OUTPUT CONTROL

WRITE/READDECODE

SENSEAMPS

OUTPUTREG

OUTPUTSELECT

WRITE DRIVER

(

Note2

)

CQ

Q

(

Note1

)

18M

MEMORY

ARRAY

CQ

Notes

1) Represents 8 data si

g

nal lines for x8, 9 si

g

nal lines for x9, 18 si

g

nal lines for x18, and 36 si

g

nal lines for x36

2) Represents 19 address si

g

nal lines for x8 and x9, 18 address si

g

nal lines for x18, and 17 address si

g

nal lines for x36.

3) Represents 1 si

g

nal line for x9, 2 si

g

nal lines for x18, and four si

g

nal lines for x36. On x8 parts, the BW is a “nibble write

”

andthereare2si

g

nal lines.

OUTPUTSELECT

6111 drw16

6.422

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

edge of CQ, and the falling edge of CQ. The rising edge of C generates

the rising edge of CQ and the falling edge of CQ. This scheme improves

the correlation of the rising and falling edges of the echo clock and will

improve the duty cycle of the individual signals.

The echo clock is very closely aligned with the data, guaranteeing that

the echo clock will remain closely correlated with the data, within the

tolerances designated.

Read and Write Operations

QDRII devices internally store the 4 words of the burst as a single,

wide word and will retain their order in the burst. There is no ability to

address to the single word level or reverse the burst order; however, the

byte and nibble write signals can be used to prevent writing any indi-

vidual bytes, or combined to prevent writing one word of the burst.

Read and write operations may be interleaved with each occurring

on every other clock cycle. In the event that two reads or two writes are

requested on adjacent clock cycles, the operation in progress will com-

plete and the second request will be ignored. In the event that both a

read and write are requested simultaneously , the read operation will win

and the write operation will be ignored.

Read operations are initiated by holding the read port select (R) low ,

and presenting the read address to the address port during the rising

edge of K which will latch the address. The data will then be read and will

appear at the device output at the designated time in correspondence

with the C and C clocks.

Write operations are initiated by holding the write port select (W) low

and presenting the designated write address to the address bus. The

QDRII SRAM will receive the address on the rising edge of clock K. On

the following rising edge of K clock, the QDRII SRAM will receive the first

data item of the four word burst on the data bus. Along with the data, the

byte (BW) or nibble write (NW) inputs will be accepted, indicating which

bytes of the data inputs should be written to the SRAM. On the rising

edge of K, the next word of the write burst and BW/NW will be accepted.

The following K and K will receive the last two words of the four word

burst, with their BW/NW enables.

Output Enables

The QDRII SRAM automatically enables and disables the Q[X:0]

outputs. When a valid read is in progress, and data is present at the

output, the output will be enabled. If no valid data is present at the output

(read not active), the output will be disabled (high impedance). The

echo clocks will remain valid at all times and cannot be disabled or turned

off. During power-up the Q outputs will come up in a high impedance

state.

Programmable Impedance

An external resistor , RQ, must be connected between the ZQ pin on

the SRAM and Vss to allow the SRAM to adjust its output drive imped-

ance. The value of RQ must be 5X the value of the intended drive

impedance of the SRAM. The allowable range of RQ to guarantee

impedance matching with a tolerance of +/- 10% is between 175 ohms

and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted

every 1024 clock cycles to correct for drifts in supply voltage and tem-

perature. If the user wishes to drive the output impedance of the SRAM

to it’s lowest value, the ZQ pin may be tied to VDDQ.

The device is capable of sustaining full bandwidth on both the input

and output ports simultaneously. All data is in two word bursts, with

addressing capability to the burst level.

Clocking

The QDRII SRAM has two sets of input clocks, namely the K, K clocks

and the C, C clocks. In addition, the QDRII has an output “echo” clock,

The K and K clocks are the primary device input clocks. The K clock

is, used to clock in the control signals (R, W and BWx/NWx), the ad-

dress, first and third words of the data burst during a write operation.

The K clock is used to clock in the control signals (BWx or NWx) and the

second and fourth words of the data burst during a write operation. The

K and K clocks are also used internally by the SRAM. In the event that

the user disables the C and C clocks, the K and K clocks will be used to

clock the data out of the output register and generate the echo clocks.

The C and C clocks may be used to clock the data out of the output

register during read operations and to generate the echo clocks. C and

C must be presented to the SRAM within the timing tolerances. The

output data from the QDRII will be closely aligned to the C and C input,

through the use of an internal DLL. When C is presented to the QDRII

SRAM, the DLL will have already internally clocked the data to arrive at

the device output simultaneously with the arrival of the C clock. The C

and second data item of the burst will also correspond. The third and

fourth data items will follow on the next clock cycle.

Single Clock Mode

The QDRII SRAM may be operated with a single clock pair . C and C

may be disabled by tying both signals high, forcing the outputs and echo

clocks to be controlled instead by the K and K clocks.

DLL Operation

The DLL in the output structure of the QDRII SRAM can be used to

closely align the incoming clocks C and C with the output of the data,

generating very tight tolerances between the two. The user may disable

the DLL by holding Doff low . With the DLL off, the C and C (or K and K

if C and C are not used) will directly clock the output register of the SRAM.

With the DLL off, there will be a propagation delay from the time the clock

enters the device until the data appears at the output.

Echo Clock

The echo clocks, CQ and CQ, are generated by the C and C clocks

(or K, K if C, C are disabled). The rising edge of C generates the rising

that is precisely timed to the data output, and tuned with matching imped-

ance and signal quality. The user can use the echo clock for down-

stream clocking of the data. Echo clocks eliminate the need for the user

to produce alternate clocks with precise timing, positioning, and signal

qualities to guarantee data capture. Since the echo clocks are generated

by the same source that drives the data output, the relationship to the data

is not significantly affected by voltage, temperature and process, as would

be the case if the clock were generated by an outside source.

All interfaces of the QDRII SRAM are HSTL, allowing speeds beyond

SRAM devices that use any form of TTL interface. The interface can be

scaled to higher voltages (up to 1.9V) to interface with 1.8V systems if

necessary. The device has a VDDQ and a separate Vref, allowing the

user to designate the interface operational voltage, independent of the

device core voltage of 1.8V VDD. The output impedance control allows

the user to adjust the drive strength to adapt to a wide range of loads and

transmission lines.

CQ, CQ.

6.42

3

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Symbol Pin Function Description

D[ X: 0] Inp ut S ync hro no us

Data input signals, sampled on the rising edge of K and K clocks during valid write operations

2M x 8 -- D[7:0]

2M x 9 -- D[8:0]

1M x 18 -- D[17:0]

512K x 36 -- D[ 35:0 ]

BW

0

, BW

1

BW

2

, BW

3

Inp ut Synchronous

Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K

clocks during write operations. Used to select which b yte is writte n into the device during the current p ortion o f the write

operations . Bytes not written remain unaltered. All the byte writes are sampled on the sam e edge as the data.

Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not writte n in to the device.

2M x 9 -- BW

0

c o ntro ls D[ 8:0 ]

1M x 18 -- BW

0

c o ntro ls D[ 8:0 ] and BW

1

c o ntro ls D[ 17: 9]

512K x 36 -- BW

0

co ntrols D[8:0], BW

1

c o ntro ls D[ 17: 9], BW

2

c o ntro ls D[ 26: 18] and BW

3

c o ntro ls D[ 35: 27]

NW0, NW1Input Synchronous

Nibble Write Select 0 and 1 are active LOW. Available only o n x8 bit parts instead of Byte Write Selec ts. Sampled on the

rising edge of the K and K clocks during write op erations. Used to select which nibble is written into the device during the

c urre nt p o rtio n o f the wri te o p e rations . Nib b le s not wri tte n re main unaltere d . A l l the ni b ble writes a re s amp l ed o n the s ame

ed ge as the data. De se lecting a Nibb le Write Sele ct will c ause the co rre sp onding nib ble of d ata to be ignored and not

written in to the dev ic e.

SA Inp ut Synchronous Address inputs are sampled on the rising edg e of K clock during active read or write operations. The se address inputs are

multiplexed so a read and write can b e initiate d on alternate clock cycles. The se inputs are ignore d when the appropriate

port is deselected.

Q[ X:0] Outp ut S yn chrono us Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the ris ing

edge of both the C and C clo cks during Read operations or K and K when operating in single clock mode. When the Read

port is deselected, Q[X:0] are automatically three-stated .

WInp ut Synchronous

Write Control Lo gic active Low. Sampled on the rising e dge of the positive input clock (K). Whe n asserted active, a write

op eration i n ini tiate d. Deas serting will d ese lect the Write po rt, causing D[X:0] to b e ig no red. If a write op eratio n has

succe ssfully b een initiated , it will continue to co mple tion, ig noring the W on the follo wing clock cycle. This allows the user to

co ntinuously hold W low while burs ting d ata into the SRAM.

RInp ut Synchronous

Read Control Logic, ac tive LOW. Sampled on the rising e dge of Positive Input Clock (K). When active, a read operation is

ini tiate d. Deasserting will caus e the Read p ort to b e d ese lected . When dese lected , the pending acc ess is allowed to

complete and the output d rivers are automatically three -sta ted follo wing the ne xt rising edge o f the C clock. Each read

access consists of a burst of four sequential tr ansfer. If a read operati on has successfull y been i niti ated, it will continue to

co mpletion, ignoring the R o n the fo llo win g c lo ck cyc le . This all ows the use r to c o ntinuous ly ho ld R low while burs ting data

from the S RAM .

CInput C lo ck

P ositive Ou tput Clock Input. C is used in conjun ct ion w ith C to clock out the Rea d data fr om th e device. C an d C can b e

used toge ther to d eskew the flight times o f various de vices on the board back to the controller. See application e xample

for further details.

CInput C lo ck Nega tive Ou tput Clock In put. C is used in conjunc tion with C to clo ck out the Read data from the device. C and C can b e

used toge ther to d eskew the flight times o f various de vices on the board back to the controller. See application e xample

for further details.

K Inp ut Clo c k Positive Input Clock Input. The rising edge of K is used to capture synchrono us inputs to the device and to d rive out data

throug h Q[X:0] when in single cloc k mode. All accesses are initiated on the rising edge o f K.

KInput C lo ck Ne gative Input Clock Input. K is used to capture synchrono us inputs being pres ented to the device and to drive out data

through Q[X:0] when in single clock mod e.

CQ, CQ Output Clo ck

Synchronous E cho clo ck outputs. The rising edg es o f these outputs are ti g htly matched to the synchronous d ata o utputs

and can be used as a data valid indication. These signals are free running and do no t sto p when the output d ata is three-

stated.

ZQ Input

Ou tp ut Im p e d a nc e Matc hing Inp ut. This in p ut i s use d to tune the de v ic e outp uts to the s y ste m d ata b us im p e da nc e . Q[ X: 0]

output impedance is s et to 0.2 x RQ, where RQ is a resistor conne cted be twe en ZQ and g round. Alte rnate ly, this pin can

be co nnected dire ctly to V

DDQ,

which enab les the minimum impedance mo de. This pi n cannot be connected directly to

GND o r l eft unc o nne cte d .

6111 tb l 02 a

Pin Definitions

6.424

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Symbol

Pin Function

Description

Doff

Input

DLL Turn Off. Whe n low this input will turn off the DLL inside the device. The AC timings with

the DLL turned off will be d ifferent from those listed in this data shee t. There will be an

increased propagation delay from the incidence o f C and

C

to Q, o r K and

K

to Q a s

config ured. The propagation delay is not a tested parameter, but will be similar to the

propagation delay of other SRAM devices in this speed grade.

TDO

Output

TDO pi n for J TA G.

TCK

Input

TCK pin for JTAG.

TDI

Input

TDI pin fo r J TA G. An inte rnal re si sto r wil l p ul l TDI to V

DD

when the p i n is unc o nnec te d .

TMS

Input

TMS p in for JTAG. An internal resisto r will pull TMS to V

DD

whe n the p i n is u nconne c ted .

NC

No Co nnec t

No co nne c ts insid e the p ack ag e. Can be tie d to any vo ltag e le ve l

V

REF

Input

Reference

Re fe re nc e Vo ltag e inp ut. Static inp ut us e d to se t the re fe renc e lev el fo r HSTL inp uts and

Outp uts as we ll as A C me as ure me nt p o ints .

V

DD

Power

Supply

Power supply inputs to the co re of the device. Should be connected to a 1.8V power

supply.

V

SS

Ground

Ground for the device. Should be connected to ground of the system.

V

DDQ

Power

Supply

Power supply for the outputs of the device. Should be connected to a 1.5V power supply

for HSTL or scaled to the desired output voltage.

6111 tbl 02b

Pin Definitions continued

6.42

5

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Pin Configuration 2M x 8

1234567891011

ACQ V

SS

/

SA (2) SA WNW

1

KNC RSA V

SS/

SA (1) CQ

BNC NC NC SA NC K NW

0

SA NC NC Q3

CNC NC NC V

SS

SA NC SA V

SS

NC NC D3

DNC D4NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC

ENC NC Q4V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC D2Q2

FNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

GNC D5Q5V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC Q1D1

KNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

LNC Q6D6V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC Q0

MNC NC NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC D0

NNC D7NC V

SS

SA SA SA V

SS

NC NC NC

PNC NC Q7SA SA C SA SA NC NC NC

RTDO TCK SA SA SA CSA SA SA TMS TDI

6111 tbl 12

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A10 is reserved for the 36Mb expansion address.

2. A2 is reserved for the 72Mb expansion address.

6.426

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Pin Configuration 2M x 9

1234567891011

ACQ V

SS/

SA (2) SA WNC KNC RSA V

SS/

SA (1) CQ

BNC NC NC SA NC K BW SA NC NC Q3

CNC NC NC V

SS

SA NC SA V

SS

NC NC D3

DNC D4NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC

ENC NC Q4V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC D2Q2

FNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

GNC D5Q5V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC Q1D1

KNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

LNC Q6D6V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC Q0

MNC NC NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC D0

NNC D7NC V

SS

SA SA SA V

SS

NC NC NC

PNC NC Q7SA SA C SA SA NC D8Q8

RTDO TCK SA SA SA CSA SA SA TMS TDI

6 111 tbl 12a

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A10 is reserved for the 36Mb expansion address.

2. A2 is reserved for the 72Mb expansion address.

6.42

7

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Pin Configuration 1M x 18

1234567891011

ACQ V

SS/

SA (3) NC/

SA (1) WBW

1KNC RSA V

SS/

SA (2) CQ

BNC Q9D9SA NC K BW0SA NC NC Q8

CNC NC D10 V

SS

SA NC SA V

SS

NC Q7D8

DNC D11 Q10 V

SS

V

SS

V

SS

V

SS

V

SS

NC NC D7

ENC NC Q11 V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC D6Q6

FNC Q12 D12 V

DDQ

VDD VSS V

DD

V

DDQ

NC NC Q5

GNC D13 Q13 V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC D5

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JNC NC D14 V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC Q4D4

KNC NC Q14 V

DDQ

V

DD

VSS V

DD

V

DDQ

NC D3Q3

LNC Q15 D15 V

DDQ

VSS VSS V

SS

V

DDQ

NC NC Q2

MNC NC D16 V

SS

V

SS

V

SS

V

SS

V

SS

NC Q1D2

NNC D17 Q16 V

SS

SA SA SA V

SS

NC NC D1

PNC NC Q17 SA SA C SA SA NC D0Q0

RTDO TCK SA SA SA CSA SA SA TMS TDI

6111 tbl 12b

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A3 is reserved for the 36Mb expansion address.

2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.

3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.

6.428

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Pin Configuration 512K x 36

165-ball FBGA Pinout

TOP VIEW

1234567891011

ACQ VSS/

SA (4) NC/

SA (2) WBW

2KBW

1RNC/

SA (1) VSS

SA (3) CQ

BQ

27

Q

18

D

18

SA BW3KBW0SA D

17

Q

17

Q

8

CD

27

Q

28

D

19

VSS SA NC SA VSS D

16

Q

7

D

8

DD

28

D

20

Q

19

VSS VSS VSS VSS VSS Q

16

D

15

D

7

EQ

29

D

29

Q

20

VDDQ VSS VSS VSS VDDQ Q

15

D

6

Q

6

FQ

30

Q

21

D

21

VDDQ VDD VSS VDD V

DDQ

D

14

Q

14

Q

5

GD

30

D

22

Q

22

VDDQ V

DD

VSS VDD VDDQ Q

13

D

13

D

5

HDoff V

REF

V

DDQ

VDDQ V

DD

VSS VDD VDDQ V

DDQ

V

REF

ZQ

JD

31

Q

31

D

23

VDDQ V

DD

VSS VDD VDDQ D

12

Q

4

D

4

KQ

32

D

32

Q

23

VDDQ V

DD

VSS VDD VDDQ Q

12

D

3

Q

3

LQ33 Q

24

D

24

VDDQ VSS VSS VSS VDDQ D

11

Q

11

Q

2

MD

33

Q

34

D

25

VSS VSS VSS VSS VSS D

10

Q

1

D

2

ND

34

D

26

Q

25

VSS SA SA SA V

SS

Q

10

D

9

D

1

PQ

35

D

35

Q

26

SA SA C SA SA Q

9

D

0

Q

0

RTDO TCK SA SA SA CSA SA SA TMS TDI

6111 tb l 12c

NOTES:

1. A9 is reserved for the 36Mb expansion address.

2. A3 is reserved for the 72Mb expansion address.

3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.

4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.

6.42

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Absolute Maximum Ratings(1) (2) Capacitance (TA = +25°C, f = 1.0MHz)(1)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

2. VDDQ must not exceed VDD during normal operation.

NOTE:

1 . Tested at characterization and retested after any design or process change that

may affect these parameters.

Symbol

Parameter

Conditions

Max.

Unit

C

IN

Inp ut Cap a citanc e V

DD

= 1.8V

V

DDQ

= 1.5V

5pF

C

CLK

Clock Input Capacitance 6 pF

C

O

Output Capacitance 7 pF

6111 tbl 06

Symbol Rating Value Unit

VTERM Supply Voltage on VDD wi th

Re s pe c t to G ND –0.5 to +2.9 V

VTERM Supply Voltage on VDDQ with

Re s pe c t to G ND –0. 5 to VDD +0.3 V

VTERM Voltage on Input termin als with

re s p e ct to G ND –0. 5 to VDD +0.3 V

VTERM Vo lta ge o n O utp ut and I/ O

te r m i na ls with res pe c t to G ND. –0. 5 to VDDQ +0.3 V

TBIAS Temperature Under Bias –55 to +125 °C

TSTG Storage Temperature –65 to +150 °C

IOUT Continuo us Current into Outputs + 20 mA

6111 t bl 05

Recommended DC Operating and

Temperture Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

VDD Power Supply

Voltage 1.7 1.8 1.9 V

VDDQ I/O Sup ply Vo ltage 1.4 1.5 1.9 V

VSS Ground 0 0 0 V

VREF Inpu t R e fer e n c e

Voltage 0.68 VDDQ/2 0.95 V

TAAmbient

Temperature (1) 025+70

o

c

6 111 tb l 04

NOTES:

1) All byte write (BWx) and nibble write (NWx) signals are sampled on the

rising edge of K and again on K. The data that is present on the data bus in the

designated byte/nibble will be latched into the input if the corresponding BWx or

NWx is held low. The rising edge of K will sample the first and third bytes/

nibbles of the four word burst and the rising edge of K will sample the second

and fourth bytes/nibbles of the four word burst.

2) The availability of the BWx or NWx on designated devices is described in

the pin description table.

3) The QDRII Burst of four SRAM has data forwarding. A read request that is

initiated on the cycle following a write request to the same address will produce

the newly written data in response to the read request.

Signal

BW0BW1BW2BW3NW0NW1

Write Byte 0 LXXXXX

Write By te 1 X L X X X X

Write By te 2 X X L X X X

Write Byte 3 XXX LXX

Write Nibble 0 X X X X L X

Write Nibble 1 XXXXXL

6111 tbl 09

Write Descriptions(1,2)

NOTE:

1. During production testing, the case temperarure equals the ambient

temperature.

6.4210

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Application Example

SRAM #1

SA WBW

0BW1C

Q

ZQ 250

Ω

R

D

K

C

Data In

R

MEMORY

CONTROLLER

Return CLK

Source CLK

Return CLK

Source CLK R=50Ω

R

VT=V

REF

R

6111 drw 20

VT

W

Address

Data Out

R

VT

R

VT

R

SRAM #4

SA WBW

0BW1C

Q

ZQ 250

W

R

D

K

C

Ω

BWx/NWx

R

VT

6.42

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

DC Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range (VDD = 1.8 ± 100mV , V DDQ = 1.4V to 1.9V)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Note

Input Leakage Current

I

IL

V

DD

= Max V

IN

= V

SS

to V

DDQ

-10

+10

µ

A

Output Leakage Current

I

OL

Output Disabled

-10

+10

µ

A

Operating Current

(x36,x18,x9,x8): DDR

I

DD

V

DD

= Max,

I

OUT

= 0mA (outputs open),

Cycle Time

>

t

KHKH

Min

333MH

Z

-

TBD

mA

1

300MH

Z

-

TBD

250MH

Z

-

TBD

300MHz

-

TBD

167MHz

-

TBD

Standb y Current: NOP

I

SB1

Device Desele cted (in NOP state)

I

OUT

= 0mA (outputs open),

f=Max,

All Inp uts

<

0.2V or

>

VDD -0.2V

333MH

Z

-

TBD

mA

2

300MH

Z

-

TBD

250MH

Z

-

TBD

200MHz

-

TBD

167MHz

-

TBD

Output High Voltag e

V

OH1

RQ = 250

Ω,

I

OH

= -15mA

V

DDQ

/2-0.12

V

DDQ

/2+0.12

V

3,7

Output Low Voltage

V

OL1

RQ = 250

Ω,

I

OL

= 15mA

V

DDQ

/2-0.12

V

DDQ

/2+0.12

V

4,7

Output High Voltag e

V

OH2

I

OH

= -0.1mA

V

DDQ

-0.2

V

DDQ

V

5

Output Low Voltage

V

OL2

I

OL

= 0.1mA

V

SS

0.2

V

6

6111 tb l 10 c

NOTES:

1. Operating Current is measured at 100% bus utilization.

2. Standby Current is only after all pending read and write burst operations are completed.

3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This

parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This

parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an

impedance measurement point.

6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance

measurement point.

7. Programmable Impedance Mode.

6.4212

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

PARAMETER

SYMBOL

MIN

MAX

UNIT

NOTES

Input High Voltage, DC

V

IH

(DC

)

V

REF

+0.1

V

DDQ

+0.3

V

1,2

Input Low Voltage, DC

V

IL

(DC)

-0.3

V

REF

-0. 1

V

1,3

Input High Voltage, AC

V

IH

(AC)

V

REF

+0.2

-

V

4,5

Input Low Voltage, AC

V

IL

(AC)

-

V

REF

-0. 2

V

4,5

6 111 tbl 10 d

Input Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)

1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.

2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))

3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))

4. This conditon is for AC function test only, not for AC parameter test.

5. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)

b) Reach at least the target AC level.

c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)

NOTES:

AC Test Load

Device R

L

=50

Ω

Z

0

=50

Ω

V

DDQ

/2

Under

Test

0.75V

V

REF

OUTPUT

6111 drw 04

ZQ R

Q

= 250

Ω

AC Test Conditions

Parameter

Symbol

Value

Unit

Co re P ow er S up p l y Vo l tag e

V

DD

1.7-1.9

V

Outp ut Po we r Supp ly Vo ltag e

V

DDQ

1.4-1.9

V

Input High/Low Level

V

IH

/V

IL

1.25/0.25

V

Inp ut Refere nc e Le v el

VREF

0.75

V

In p ut Ri s e / Fal l Tim e

TR/TF

0.6/0.6

ns

Outp ut Timing Refe re nce Le ve l

V

DDQ

/2

V

6111tbl 11a

NOTE:

1. Parameters are tested with RQ=250Ω

1.25V

0.25V

6111 drw 06

0.75V

V

I

L

V

D

V

D

+0.25

V

D

+0.5

20% tKHKH (MIN)

6111 drw 21

VSS

V

IH

VSS-0.25V

VSS-0.5V

20% tKHKH (MIN)

6111 drw 22

Overshoot Timing Undershoot Timing

6.42

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V,TA = 0 TO 70°C)(3,8)

Symbol Parameter

333MHz 300MHz 250MHz 200MHz 167MHz

Unit Notes

Min. Max Min. Max Min. Max Min. Max Min. Max

Cl ock Parameters

tKHKH Averag e clock cyc le time (K,K,C,C) 3.00 3.47 3.30 5.25 4.00 6.30 5.00 7.88 6.00 8.40 ns

tKC v a r Cyc l e to Cy cl e P e ri o d J i tte r ( K,K,C,C) - 0.20 - 0.20 - 0.20 - 0.20 - 0.20 ns 1,5

tKHKL Clo ck High Time (K,K,C,C) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9

tKLKH Clo ck LOW Time (K,K,C,C) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9

tKHKHClo ck to clock (K→K,C→C

) 1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10

tKHKH Cl oc k to clock (K→K,C→C) 1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10

tKHCH Clock to data clock (K→C,K→C

) 0.00 1.30 0.00 1.45 0.00 1.80 0.00 2.30 0.00 2.80 ns

tKC l o c k DLL lo c k time (K , C) 1024 - 1024 - 1024 - 102 4 - 1024 - c yc le s 2

tKC re se t K s ta ti c to DL L re s e t 30 - 30 - 30 - 30 - 30 - ns

Output P arameters

tCHQV C,C HIGH to o utp ut val id - 0. 45 - 0. 45 - 0. 45 - 0. 45 - 0. 50 ns 3

tCHQX C,C

HIGH to o utput h o ld -0 .45 - -0 .45 - -0. 45 - -0 .4 5 - -0 .5 0 - ns 3

tCHCQV C,C

H IGH to e c ho cl oc k v ali d - 0. 45 - 0. 45 - 0. 45 - 0. 45 - 0. 50 ns 3

tCHCQX C,C

HIGH to echo clock ho ld -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3

tCQHQV CQ,CQ HIGH to o utp ut v al id - 0. 25 - 0. 27 - 0. 30 - 0. 35 - 0. 40 ns

tCQHQX CQ,CQ HIGH to o utp ut ho ld -0 .25 - -0 .27 - -0. 30 - -0 .3 5 - -0 .4 0 - ns

tCHQZ C HIGH to o utp ut Hig h-Z - 0. 45 - 0. 45 - 0. 45 - 0. 45 - 0. 50 ns 3, 4,5

tCHQX1 C HIGH to outp ut Lo w-Z -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3,4,5

Se t-Up Ti mes

tAVKH Address valid to K,K rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6

tIVKH Control inputs valid to K,K rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7

tDVKH D ate -in val id to K, K rising edge 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns

Ho l d T i m es

tKHAX K,K rising edge to address hold 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6

tKHIX K,K rising edge to control inputs hold 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7

tKHDX K, K rising edge to data-in hold 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns

6111 tbl 11

NOTES:

1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10

2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.

3. If C,C are tied High, K,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.

The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions

(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

5. This parameter is guaranteed by device characterization, but not production tested.

6. All address inputs must meet the specified setup and hold times for all latching clock edges.

7. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36)

8. During production testing, the case temperature equals TA.

9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).

10. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).

6.4214

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Timing Waveform of Combined Read and Write Cycles

K

123

R

SA

Q

tKHCH

t

K

H

K

L

t

K

H

I

X

t

I

V

K

H

t

K

H

A

X

t

A

V

K

H

C

CQ

tCHQX

tCHQX1

tKLKH

tCHCQV

tCHCQX

W

D

t

D

V

K

H

t

D

V

K

H

4567

t

K

L

K

H

t

K

H

K

H

t

K

H

K

H

A2A1

A0 A3

t

K

H

D

X

t

K

H

D

X

D10 D12

Qx3

tCHQV

tCHQV tCHQX

tCQHQV

tKHCH tKHKH tKHKHtKHKL

tCHCQX

tCHCQV

NOP Read A0 Write A1 Write A3Read A2 NOP

t

K

H

I

X

t

I

V

K

H

D11 D13 D30 D32

D31 D33

Qx2 Q00 Q01 Q02 Q03 Q20 Q21 Q22 Q23

tCHQZ

NOP

6

1

d

r

w

0

9

.

tCQHQX

6.42

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1 149.1 Compatible T est Access Port (T AP). The package pads are monitored by the Serial Sca n circuitry

when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1 149.1, the

SRAM contains a T AP controller , Instruction register, Bypass Register and ID register. The T AP controller has a standard 16-st ate machine that

resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizi ng the T AP. T o disable

the T AP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI

are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may

also be tied to VDD through a register . TDO should be left unconnected.

JTAG Block Diagram JTAG Instruction Coding

IR2

IR1

IR0

Instruction

TDO Output

Notes

0 0 0 EXTEST Bo undary Scan Register

0 0 1 IDCODE Identification register 2

0 1 0 SAMPLE-Z Bo undary Scan Re gister 1

0 1 1 RESERVED Do Not Use 5

1 0 0 SAMPLE/PRELOAD Boundary Scan reg iste r 4

1 0 1 RESERVED Do Not Use 5

1 1 0 RESERVED Do Not Use 5

1 1 1 BYPASS Bypass Register 3

6111t b l 1 3

NOTES:

1. Places Qs in Hi-Z in order to sample all input data regardless of

other SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the

serial shift of the external TDI data.

3. Bypass register is initialized to Vss when BYP ASS instruction is

invoked. The Bypass Register also holds serially loaded TDI when

existing the Shift DR states.

4. SAMPLE instruction does not place output pins in Hi-Z.

5. This instruction is reserved for future use.

TAP Controller State Diagram

Test Logic Reset

Run Test Idle Select DR

Capture DR

Pause DR

Exit 2 DR

UpdateDR

Shift DR

Exit 1 DR

Select IR

Capture IR

Pause IR

Exit 2 IR

Update IR

Shift IR

Exit 1 IR

0

1

0

6111 drw 17

0

1

0

1

0

SRAM

CORE

BYPASS Reg.

Identification Reg.

Instruction Reg

.

Control Signal

s

TAP Controller

A,D

K,K

C,C

Q

CQ

TDI

TMS

TCK

TDO

6

1

d

r

w

1

8

S

6.4216

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Part

Instrustion Register

Bypass Register

ID Register

Boundry Scan

512Kx36 3 b its 1 b it 32 bi ts 107 bits

1Mx18 3 b its 1 bit 32 bits 107 b its

2Mx8/x 9 3 b its 1 b it 32 bits 107 b its

6111 tbl 14

INSTRUCTION FIELD

ALL DEVICES

DESCRIPTION

PART NUMBER

Revision Number (31:29) 000 Revision Number

Dev ice ID (28:12) 0 0000 0010 0100 0000

0 0000 0010 0100 0001

0 0000 0010 0100 0010

0 0000 0010 0100 0011

512Kx36 QDRII BURST OF 4

1Mx18

2Mx9

2Mx8

71P74604S

71P74804S

71P74104S

71P74204S

IDT JEDEC ID CODE (11:1) 000 0011 0011 Allows uniq ue ide ntification of SRAM

vendor.

ID Register Presence

Ind ic ator (0) 1 Indicates the presenc e of an ID register.

6111 t bl 15

Scan Register Definition

Identification Register Definitions

6.42

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

ORDER PI N ID

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 10P

12 10N

13 9P

14 10M

15 11N

16 9M

17 9N

18 11L

19 11M

20 9L

21 10L

22 11K

23 10K

24 9J

25 9K

26 10J

27 11J

28 11H

29 10G

30 9G

31 11F

32 11G

33 9F

34 10F

35 11E

36 10E

6111 tbl 16a

Boundary Scan Exit Order (2M x 8-Bit, 2M x 9-Bit)

ORDER PIN ID

37 10D

38 9E

39 10C

40 11D

41 9C

42 9D

43 11B

44 11C

45 9B

46 10B

47 11A

48 Internal

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 2A

65 1A

66 2B

67 3B

68 1C

69 1B

70 3D

71 3C

72 2D

6111 tb l 17a

ORDER PI N ID

73 3E

74 2C

75 1D

76 2E

77 1E

78 2F

79 3F

80 2G

81 3G

82 1F

83 1G

84 1J

85 2J

86 3K

87 3J

88 3L

89 2L

90 1K

91 2K

92 1M

93 1L

94 3N

95 3M

96 2N

97 3P

98 2M

99 1N

100 2P

101 1P

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

6111 t bl 18 a

6.4218

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Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Boundary Scan Exit Order (1M x 18-Bit, 512K x 36-Bit)

ORDER PI N I D

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 10P

12 10N

13 9P

14 10M

15 11N

16 9M

17 9N

18 11L

19 11M

20 9L

21 10L

22 11K

23 10K

24 9J

25 9K

26 10J

27 11J

28 11H

29 10G

30 9G

31 11F

32 11G

33 9F

34 10F

35 11E

36 10E

6111 tb l 16

ORDER PI N ID

37 10D

38 9E

39 10C

40 11D

41 9C

42 9D

43 11B

44 11C

45 9B

46 10B

47 11A

48 Internal

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 1H

65 1A

66 2B

67 3B

68 1C

69 1B

70 3D

71 3C

72 1D

6111 tbl 17

ORDER PI N ID

73 2C

74 3E

75 2D

76 2E

77 1E

78 2F

79 3F

80 1G

81 1F

82 3G

83 2G

84 1J

85 2J

86 3K

87 3J

88 2K

89 1K

90 2L

91 3L

92 1M

93 1L

94 3N

95 3M

96 1N

97 2M

98 3P

99 2N

100 2P

101 1P

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

6111 tbl 1 8

6.42

19

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Parameter

Symbol

Min

Typ

Max

Unit

Note

Output Power Supply

V

DDQ

1.4

-

1.9

V

Power Supply Voltage

V

DD

1.7

1.8

1.9

V

Inp ut Hig h Le v e l

V

IH

1.3

-

V

DD

+0.3

V

Inp ut Lo w Le v e l

V

IL

-0.3

-

0.5

V

O utp ut Hig h Vo ltag e (IO H = -1m A )

V

OH

V

DDQ

- 0.2

-

V

DDQ

V

1

Output Low Voltage (IOL = 1m A)

V

OL

V

SS

-

0.2

V

1

6111 tbl 19

Parameter Symbol Min Unit Note

Input High/Low Level V

IH

/V

IL

1.3/0.5 V

Input Rise/Fall Time TR/TF 1.0/1.0 ns

Inp ut and Outp ut Timing Re fe re nce Le ve l V

DDQ

/2 V 1

6111 tbl 20

JTAG DC Operating Conditions

NOTE:

1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to Z Q.

JTAG AC Test Conditions

Parameter Symbol Min Max Unit Note

TCK Cy c l e Tim e tCHCH 50 - ns

TCK High Pulse Width tCHCL 20 - ns

TCK Low Pulse Width tCLCH 20 - ns

TMS Inp ut S etup Time tMVCH 5-ns

TMS Inp ut Ho ld Tim e tCHMX 5-ns

TDI Inp ut S e tup Tim e tDVCH 5-ns

TDI Inp ut Ho ld Time tCHDX 5-ns

SRAM Input Setup Time tSVCH 5-ns

SRA M Inp ut Ho ld Time tCHSX 5-ns

Cloc k Lo w to Output Valid tCLQV 010ns

6111 tbl.21

JTAG AC Characteristics

JTAG Timing Diagram

6

1

d

r

w

1

9

TC

K

TM

S

t

CHCH

TD

I

/

SR

A

M

Inp

u

t

s

TD

O

t

MVCH

t

DVCH

t

SVCH

t

CHCL

t

CHMX

t

CHDX

t

CHSX

t

CLCH

t

CLQV

SR

A

M

Out

p

u

t

s

NOTE:

1. See AC test load on page 12.

6.4220

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Package Diagram Outline for 165-Ball Fine Pitch Grid Array

6.42

21

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range

Ordering Information

CORPORA TE HEADQUARTERS for SALES: for T ech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726

www.idt.com

“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

S

Power

XXX

Speed

BQ

Package

BQ

IDT 71P74XXX

333

300

250

200

167

6111 drw 15

Device

Type

165 Fine Pitch Ball Grid Array (fBGA)

Clock Frequency in MegaHertz

IDT71P74204 2M x 8 QDR II SRAM Burst of 4

IDT71P74104 2M x 9 QDR II SRAM Burst of 4

IDT71P74804 1M x 18 QDR II SRAM Burst of 4

IDT71P74604 512K x 36 QDR II SRAM Burst of 4

Process

Temperature

Range

Blank Commercial (0 C to +70 C)

X

Revision History

REVISION DATE PAGES DESCRIPTION

O 03/30/04 1-21 Initial Advance Information Data Sheet Release

IDT71P74204 (2M x 8-Bit), 71P74104 (2M x 9-Bit), 71P74804 (1M x 18 x -Bit) 71P74604 (512K x 36-Bit)

Advance Information

18 Mb QDR II SRAM Burst of 4 Commercial Temperature Range