QS52807T/AT GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER QS52807T/AT FEATURES: DESCRIPTION - - - - - The QS52807T clock driver/buffer circuits can be used for clock buffering schemes where low skew is a key parameter. The QS52807T generates ten non-inverting outputs. Designed in IDT's proprietary QCMOS process, these devices provide low propagation delay buffering with on-chip skew of 0.35ns for same-transition, same bank signals. The QS52807T has on-chip series termination resistors for lower noise clock signals. The QS52807T series resistor version is recommended for driving unterminated lines with capacitive loading and other noise sensitive clock distribution circuits. These clock buffer products are designed for use in high-performance workstations, embedded and personal computing systems. Several devices can be used in parallel or scattered throughout a system for guaranteed low skew, system-wide clock distribution networks. - - 10 output, low skew clock signal buffer TTL output voltage swing 25 on-chip resistors available for low noise Input hysteresis for better noise margin Guaranteed low skew: * 0.35ns output skew (same bank) * 0.45ns output skew (opposite bank) * 0.75ns part-to-part skew Std. and A speed grades Available in QSOP and SOIC packages The QS52807T is characterized for operation at -40C to +85C. FUNCTIONAL BLOCK DIAGRAM O1 O2 O3 O4 O5 IN O6 O7 O8 O9 O 10 INDUSTRIAL TEMPERATURE RANGE AUGUST 2000 1 c 1999 Integrated Device Technology, Inc. DSC-5239/- QS52807T/AT GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Symbol VTERM(2) (1) Description Supply Voltage to Ground Max. - 0.5 to +7 Unit V IN 1 20 VCC DC Output Voltage VOUT - 0.5 to +7 V G ND 2 19 O 10 VTERM(3) DC Input Voltage VIN - 0.5 to +7 V O1 3 18 O9 VAC AC Input Voltage (pulse width 20ns) -3 V V CC 4 17 G ND IOUT DC Output Current VIN < 0 -20 mA O2 5 O8 G ND 6 SO 20-2 16 SO 20-8 15 O3 7 14 O7 V CC 8 13 G ND O4 9 12 O6 G ND 10 11 O5 DC Output Current Max. Sink Current/Pin VCC 120 mA TSTG Storage Temperature - 65 to +150 C TJ Junction Temperature 150 C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc Terminals. 3. All terminals except Vcc. QSOP/ SOIC TOP VIEW CAPACITANCE (TA = +25OC, f = 1.0MHz, VIN = 0V) QSOP Pins CIN SOIC Max. (1) Typ. 3 6 Max. (1) 7 Typ. 5 NOTE: 1. This parameter is guaranteed but not production tested. PIN DESCRIPTION 2 Pin Names IN I/O I Description Clock Input Ox O Clock Outputs Unit pF QS52807T/AT GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 5.0V 10% Symbol VIH Parameter Input HIGH Voltage Test Conditions Guaranteed Logic HIGH for All Inputs Min. 2 Typ.(1) -- Max. -- Unit V VIL Input LOW Voltage Guaranteed Logic LOW for All Inputs -- -- 0.8 V Vcc = Min., IIN = -18mA -- -0.7 -1.2 V (3) VIC Clamp Diode Voltage VOH Output HIGH Voltage Vcc = Min., VIN = VIH or VIL, IOH = -8mA 2.4 3.3 -- V VOL Output LOW Voltage Vcc = Min., VIN = VIH or VIL, IOL = 8mA -- -- 0.5 V IIN Input Leakage Current Vcc = Max., VIN = Vcc or GND -- -- 1 A IOFF Input/Output Power Off Leakage Vcc = Max., VIN or VOUT = Vcc or GND IOS Short Circuit Current VT Input Hysteresis ROUT Output Resistance (2,3) (4) -- -- 1 A Vcc = Max., VOUT = GND -60 -- -250 mA VTLH - VTHL for All Inputs -- 0.2 -- V Vcc = Min., IOL = 12mA -- 28 -- NOTES: 1. Typical values are at VCC = 5.0V, TA = 25C. 2. Not more than one output should be used to test this high power condition. Duration is less than one second. 3. Guaranteed by design but not tested. 4. Output resistance represents the total output inpedance of the logic device and includes added series termination resistance. POWER SUPPLY CHARACTERISTICS Symbol ICC Parameter Quiescent Power Supply Current Test Conditions VCC = Max., VIN = GND or Vcc Typ. 0.2 Max. 1.5 Unit mA ICC Power Supply Current per Input HIGH 0.5 2.5 mA ICCD Dynamic Power Supply Current per Output (1) VCC = Max., VIN = 3.4V Input toggling at 50% duty cycle VCC = Max., Outputs Enabled 0.09 0.2 mA/MHz mA IC Total Power Supply Current Examples (2) VCC = Max., Input at 50% duty cycle fI = 10MHz VIN = GND or Vcc 8.5 21.5 VIN = GND or 3.4V 9.5 23 VCC = Max., Input at 50% duty cycle fI = 2.5MHz VIN = GND or Vcc 2.5 7 VIN = GND or 3.4V 3 8 NOTES: 1. Guaranteed by design but not tested. CL = 0pF. 2. IC = ICC + (ICC)(DH)(NT) + ICCD (fO)(NO) where: DH = Input Duty Cycle NT = Number of TTL HIGH inputs at DH (one) fO = Output Frequency NO = Number of outputs at fO (ten) 3 QS52807T/AT GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE SWITCHING CHARACTERISTICS OVER OPERATING RANGE TA = -40C to +85C, VCC = 5.0V 10% CLOAD = 50pF, RLOAD = 500 unless otherwise noted. QS52807T Symbol Parameter (1) Min. QS52807/AT Max. Min. Max. Unit tSK(01) Skew between all outputs, same transition -- 0.6 -- 0.5 ns tSK(P) Pulse Skew; skew between opposite transitions of the same output (tPHL - tPLH) -- 0.75 -- 0.75 ns tSK(T) Part-to-part skew (2) -- 1 -- 1 ns tPLH tPHL Propagation Delay (3) IN to Ox 1.5 5 1.5 4.5 ns tR Output Rise Time -- 1.5 -- 1.5 ns tF Output Fall Time -- 1.5 -- 1.5 ns NOTES: 1. Skew parameters are guaranteed across temperature range, but not tested. 2. tSK(T) only applies to devices of the same transition, part type, temperature, power supply voltage, loading, package, and speed grade. 3. The propagation delay range indicated by Min. and Max. specifications results from process and environmental variables. These propagation delay limits do not imply skew. 4 QS52807T/AT GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS VCC V IN V O UT Pulse Generator DUT 50pF 50 500 Pulse g enerator for a ll puls es: f 1.0M Hz; t F 2.5ns; t R 2.5ns PULSE SKEW -- tSK(P) PROPAGATION DELAY 3V 3V 1.5V INPU T INPU T 1.5V 0V tPLH 0V tPHL t PHL tPLH VOH VOH OUTPUT 2.0V OUTPUT 1.5V 1.5V 0.8V VOL tR VOL t SK(p) = t PHL - tP LHL tF OUTPUT SKEW -- tSK(O1) PART-TO-PART SKEW -- tSK(T) 3V 3V 1.5V INPU T 1.5V INPUT 0V tP HL1 t P LH1 0V t P HL1 t P LH 1 VOH VOH PART 1 O UTPUT 1.5V 1.5V OUPUT 1 VOL VOL tSK (O 1) tSK(t) t SK(t) VOH tSK (O 1) VOH OUPUT 2 PART 2 O UTPUT 1.5V 1.5V VOL tP LH 2 VOL tP LH 2 tP HL2 tP HL2 tSK(01) = t PLH2 - t PLH 1 or t PHL 2 - t PHL1 tSK(p) = t PLH2 - tPLH1 or t PHL2 - t PHL1 5 QS52807T/AT GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION QS XXXX Device Type X Package Sm all Outline IC (300 m il) (SO20-2) Quarter-size Sm all Ou tline Package (SO20-8) SO Q 52807T Guaranteed Low Skew CM OS Clock D river/Buffer 52807AT CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* *To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. 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