1
QS52807T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE
AUGUST 2000
1999 Integrated Device Technology, Inc. DSC-5239/-c
QS52807T/AT
INDUSTRIAL TEMPERATURE RANGE
GUARANTEED LOW
SKEW CMOS CLOCK
DRIVER/BUFFER
FUNCTIONAL BLOCK DIAGRAM
IN
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
DESCRIPTION
The QS52807T clock driver/buffer circuits can be used for clock
buffering schemes where low skew is a key parameter. The QS52807T
generates ten non-inverting outputs. Designed in IDT's proprietary
QCMOS process, these devices provide low propagation delay buffer-
ing with on-chip skew of 0.35ns for same-transition, same bank signals.
The QS52807T has on-chip series termination resistors for lower noise
clock signals. The QS52807T series resistor version is recommended
for driving unterminated lines with capacitive loading and other noise
sensitive clock distribution circuits. These clock buffer products are
designed for use in high-performance workstations, embedded and
personal computing systems. Several devices can be used in parallel
or scattered throughout a system for guaranteed low skew, system-wide
clock distribution networks.
The QS52807T is characterized for operation at -40°C to +85°C.
FEATURES:
− 10 output, low skew clock signal buffer
− TTL output voltage swing
− 25Ω on-chip resistors available for low noise
− Input hysteresis for better noise margin
− Guaranteed low skew:
• 0.35ns output skew (same bank)
• 0.45ns output skew (opposite bank)
• 0.75ns part-to-part skew
− Std. and A speed grades
− Available in QSOP and SOIC packages
2
INDUSTRIAL TEMPERATURE RANGE
QS52807T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
PIN CONFIGURATION
QSOP/ SOIC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
IN
GND
O1
GND
VCC
GND
GND
GND
O2
O3
O4
O5
O6
O7
O8
O9
O10
VCC
VCC
VCC
SO20-2
SO20-8
ABSOLUTE MAXIMUM RATINGS (1)
Symbol Description Max. Unit
VTERM(2) Supply Voltage to Ground – 0.5 to +7 V
DC Output Voltage VOUT – 0.5 to +7 V
VTERM(3) DC Input Voltage VIN – 0.5 to +7 V
VAC AC Input Voltage (pulse width ≤20ns) -3 V
IOUT DC Output Current VIN < 0 -20 mA
DC Output Current Max. Sink Current/Pin 120 mA
TSTG Storage Temperature – 65 to +150 °C
TJJunction Temperature 150 °C
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any o ther c ondit ions above those i ndic ated in the operati onal sect ions
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals exce pt Vcc.
CAPACITANCE (TA = +25OC, f = 1.0MHz, VIN = 0V)
QSOP SOIC
Pins Typ. Max. (1) Typ. Max. (1) Unit
CIN 3657pF
NOTE:
1. This parameter is guaranteed but not producti on tested.
PIN DESCRIPTION
Pin Names I/O Description
IN I Clock Input
Ox O Cl ock Outputs
3
QS52807T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = -40°C to +85°C, VCC = 5.0V ± 10%
Symbol Parameter Test Conditions Min. Typ.(1) Max. Unit
VIH Input HIGH Voltage Guaranteed Logic HIGH for All Inputs 2 — — V
VIL Input LOW Voltage Guaranteed Logic LOW for All Inputs — — 0.8 V
VIC Clamp Diode Voltage (3) Vcc = Min., IIN = -18mA — –0.7 –1.2 V
VOH Output HIGH Voltage Vcc = Min., VIN = VIH or VIL, IOH = -8mA 2.4 3.3 — V
VOL Output LOW Voltage Vcc = Min., VIN = VIH or VIL, IOL = 8mA — — 0.5 V
IIN Input Leakage Current Vcc = Max., VIN = Vcc or GND — — ±1 µA
IOFF Input/Output Power Off Leakage Vcc = Max., VIN or VOUT = Vcc or GND — — ±1 µA
IOS Short Circuit Current (2,3) Vcc = Max., VOUT = GND –60 —–250 mA
∆VTInput Hysteresis VTLH - VTHL for All Inputs — 0.2 — V
ROUT Output Resistance (4) Vcc = Min., IOL = 12mA — 28 — Ω
NOTES:
1. Typical v al ues are at VCC = 5. 0V, TA = 25°C.
2. Not more than one output should be used to test this high power condi tion. Durati on is less tha n one second.
3. Guaranteed by design but no t tested.
4. Output resistance r epresents t he total output inpedance of the logic device and i ncludes added series termination resis tanc e.
POWER SUPPLY CHARACTERISTICS
Symbol Parameter Test Conditions Typ. Max. Unit
ICC Quiescent Power Supply Current VCC = Max., VIN = GND or Vcc 0.2 1.5 mA
∆ICC Power Supply Current per Input HIGH VCC = Max., VIN = 3.4V
Input toggling at 50% duty cycle 0.5 2.5 mA
ICCD Dynamic Power Supply Current per Output (1) VCC = Max., Outputs Enabled 0.09 0.2 mA/MHz
ICTotal Power Supply Current Examples (2) VCC = Max.,
Input at 50% duty cycle VIN = GND or Vcc 8.5 21.5 mA
fI = 10MHz VIN = GND or 3.4V 9.5 23
VCC = Max.,
Input at 50% duty cycle VIN = GND or Vcc 2.5 7
fI = 2.5MHz VIN = GND or 3.4V 3 8
NOTES:
1. Guaranteed by design but not tested. CL = 0pF.
2. IC = ICC + (∆ICC)(DH)(NT) + ICCD (fO)(NO)
where:
DH = Input Duty Cycle
NT = Number of TTL HIGH inputs at DH (one)
fO = Output Frequency
NO = Number of out puts at fO (ten)
4
INDUSTRIAL TEMPERATURE RANGE
QS52807T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
TA = -40°C to +85°C, VCC = 5.0V ± 10%
CLOAD = 50pF, RLOAD = 500Ω unless otherwise noted. QS52807T QS52807/AT
Symbol Parameter (1) Min. Max. Min. Max. Unit
tSK(01) Skew between all outputs, same transition — 0.6 — 0.5 ns
tSK(P) Pulse Skew; skew between opposite transitions of the same output (tPHL - tPLH) — 0.75 — 0.75 ns
tSK(T) Part-to-part skew (2) —1—1
ns
tPLH
tPHL Propagation Delay (3)
IN to Ox 1.5 5 1.5 4.5 ns
tROutput Rise Time — 1.5 — 1.5 ns
tFOutput Fall Time — 1.5 — 1.5 ns
NOTES:
1. Sk ew parameters are guaranteed acros s temperat ure range, but not t ested.
2. tSK(T) only appl i es to devices of the same transi tion, part t ype, temperature, power supply voltage, l oading, pac k age, and speed grade.
3. The propagation delay range indicat ed by Min. and M ax. s pecific ations res ults from process and envi ronm ental variabl es. These propagation delay
limits do not imply skew.
5
QS52807T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER INDUSTRIAL TEMPERATURE RANGE
50pF 500Ω
VIN
Pulse
Generator DUT
50Ω
VCC
VOUT
Pulse gene rator for all pulses: f ≤ 1 .0 MH z; tF ≤ 2.5ns; tR ≤ 2.5ns
INPUT
PART 1 O UT PUT
PART 2 O UT PUT
tPLH1 tPHL1
tPLH2 tPHL2
tSK(t)
tSK(t)
1.5V
3V
0V
VOH
1.5V
1.5V
VOH
VOL
VOL
tSK(p) = tPLH2 - tPLH1 or tPHL2 - tPHL1
INPUT
OUTPUT 2.0V
0.8V
1.5V
3V
0V
VOH
1.5V
VOL
tPLH tPHL
tRtF
INPUT
OUTPUT
tPLH tPHL
1.5V
3V
0V
VOH
1.5V
VOL
tSK(p) = tPHL - tPLHL
INPUT
OUPUT 1
tPLH1
1.5V
3V
0V
VOH
1.5V
1.5V
VOH
VOL
VOL
OUPUT 2
tPHL1
tSK(O1) tSK(O1)
tPLH2 tPHL2
tSK(01) = tPLH2 - tPLH1 or tPHL2 - tPHL1
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY PULSE SKEW — tSK(P)
OUTPUT SKEW — tSK(O1) PART-TO-PART SKEW — tSK(T)
6
INDUSTRIAL TEMPERATURE RANGE
QS52807T/AT
GUARANTEED LOW SKEW CMOS CLOCK DRIVER/BUFFER
ORDERING INFORMATION
CORPORATE HEADQUARTERS for SALES:
2975 Stender Way 800-345-7015 or 408-727-6116
Santa Clara, CA 95054 fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo, QuickSwitch, and SynchroSwitch are registered trademarks of Integrated Device Technology, Inc.
QS XXXX
D evice Typ e X
Package
SO
Q
52807T
52807AT Guaranteed Low Skew CM O S Clock Driver/Buffer
Sm all O utline IC (300 m il) (SO20-2)
Qua rter-size Sm all O u tline P ackage (SO 20-8)
