ADVANCE INFORMATION MICRONAS CDC32xxG-B V3.0 Automotive Controller - Family Hardware Manual CDC3205G-B Automotive Controller Specification Edition Dec.3, 2001 6251-546-4AI MICRONAS CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Page Section Title 7 7 9 10 1. 1.1. 1.2. 1.3. Introduction Features Abbreviations Block Diagrams 13 13 16 17 17 21 22 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. Packages and Pins Pin Assignment Package Outline Dimensions Multiple Function Pins Pin Function Description External Components Pin Circuits 25 25 26 27 34 3. 3.1. 3.2. 3.3. 3.4. Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Quartz Crystal Characteristics 35 35 35 37 39 40 41 43 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. CPU and Clock System ARM7TDMI` CPU CPU Modes Clock System EMI Reduction Module (ERM) Memory Controller Registers PLL/ERM Application Notes 45 46 47 48 5. 5.1. 5.2. 5.3. Memory and Boot System RAM and ROM I/O Map Boot System 49 49 50 52 54 57 6. 6.1. 6.2. 6.3. 6.4. 6.5. Core Logic Control Word CW Standby Registers UVDD Analog Section Reset Logic Test Registers 59 59 60 60 7. 7.1. 7.2. 7.3. JTAG Interface Functional Description External Circuit Layout JTAG ID 61 61 8. 8.1. Embedded Trace Module (ETM) Functional Description 63 63 9. 9.1. IRQ Interrupt Controller Unit (ICU) Functional Description 2 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Contents Micronas ADVANCE INFORMATION CDC32xxG-B V3.0 3 DEC 01 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Contents Page Section Title 66 66 68 68 9.2. 9.3. 9.4. 9.5. Timing Registers Principle of Operation Application Hints 71 71 71 72 10. 10.1. 10.2. 10.3. FIQ Interrupt Logic Functional Description Registers Principle of Operation 73 11. Port Interrupts 75 75 76 78 80 81 12. 12.1. 12.2. 12.3. 12.4. 12.5. Ports Analog Input Port Universal Ports U0 to U8 Universal Port Registers High Current Ports H0 to H7 High Current Port Registers 83 84 84 84 84 85 85 87 13. 13.1. 13.2. 13.3. 13.4. 13.5. 13.6. 13.7. AVDD Analog Section VREFINT Generator BVDD Regulator Wait Comparator P0.6 Comparator PLL/ERM A/D Converter (ADC) Registers 89 89 91 14. 14.1. 14.2. Timers (TIMER) Timer T0 Timer T1 to T4 93 93 94 15. 15.1. 15.2. Pulse Width Modulator (PWM) Principle of Operation Registers 97 97 98 16. 16.1. 16.2. Pulse Frequency Modulator (PFM) Principle of Operation Registers 99 101 103 17. 17.1. 17.2. Capture Compare Module (CAPCOM) Principle of Operation Registers 105 105 109 110 18. 18.1. 18.2. 18.3. Stepper Motor Module VDO (SMV) Principle of Operation Registers Timing 111 111 19. 19.1. LCD Module Principle of Operation Micronas 3 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Page Section Title 114 114 19.2. 19.3. Registers Application Hints for Cascading LCD Modules 115 115 117 118 119 20. 20.1. 20.2. 20.3. 20.4. DMA Controller Functions Registers Principle of Operation Timing Diagrams 123 123 123 124 21. 21.1. 21.2. 21.3. Graphic Bus Interface Functions GB Registers Principle of Operation 127 128 129 130 22. 22.1. 22.2. 22.3. Serial Synchronous Peripheral Interface (SPI) Principle of Operation Registers Timing 131 132 134 136 23. 23.1. 23.2. 23.3. Universal Asynchronous Receiver Transmitter (UART) Principle of Operation Timing Registers 139 140 141 24. 24.1. 24.2. I2C-Bus Master Interface Principle of Operation Registers 143 144 144 150 155 157 25. 25.1. 25.2. 25.3. 25.4. 25.5. CAN Manual Abbreviations Functional Description Application Notes Bit Timing Logic Bus Coupling 159 159 159 160 161 26. 26.1. 26.2. 26.3. 26.4. DIGITbus System Description Bus Signal and Protocol Other Features Standard Functions Optional Functions 163 163 164 166 169 172 27. 27.1. 27.2. 27.3. 27.4. 27.5. DIGITbus Master Module Context Functional Description Registers Principle of Operation Timings 173 174 28. 28.1. Audio Module (AM) Functional Description 4 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Contents Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION Micronas CDC32xxG-B V3.0 3 DEC 01 Contents Page Section Title 178 28.2. Registers 179 179 180 181 29. 29.1. 29.2. 29.3. Hardware Options Functional Description Listing of Dedicated Addresses of the Hardware Options Field HW Options Registers and Code 187 187 192 30. 30.1. 30.2. Register Cross Reference Table 8 Bit I/O Region 32 Bit I/O Region 193 31. Register Quick Reference 217 217 220 32. 32.1. 32.2. Control Register and Memory Interface Control Register CR External Memory Interface 226 33. Data Sheet History 5 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 Page 6 Section ADVANCE INFORMATION 3 DEC 01 Contents Title Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 1. Introduction The device is a microcontroller for use in automotive applications. The on-chip CPU is ARM processor ARM7TDMI with 32bit data and address bus, which supports Thumb format instructions. The chip contains timer/counters, interrupt controller, multi channel AD converter, stepper motor and LCD driver, CAN interfaces and PWM outputs and a crystal clock multiplying PLL. 1.1. Features Table 1-1: CDC32xxG Family Feature List This Device: All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Item CDC3205G-A EMU CDC3205G-B EMU CDC3207G-B MCM-Flash Example Mask ROM Part Core CPU 32bit ARM7TDMI CPU operation modes DEEP SLOW, SLOW, FAST and PLL CPU clock multiplication PLL delivering up to 24MHz PLL delivering up to 50MHz EMI Reduction Mode - selectable in PLL mode Quartz oscillator 4 to 5MHz RAM, 32bit wide 16kByte 32kByte 32kByte 12kByte ROM ROMless, Flash Port for connection of external program storage with up to 16Mbyte, internal 4KByte Boot ROM ROMless, Flash Port for connection of external program storage with up to 16Mbyte, internal 8KByte Boot ROM 512kByte Flash EEPROM, top boot configuration, internal 8KByte Boot ROM 256kByte ROM Digital Watchdog Central Clock Divider Interrupt Controller expanding IRQ 40 inputs,16 priority levels Port Interrupts including Slope Selection 6 inputs Boot System allows in-system downloading of external code to Flash memory via JTAG Micronas 32 inputs,16 priority levels - 7 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 1-1: CDC32xxG Family Feature List This Device: Item CDC3205G-A EMU CDC3205G-B EMU CDC3207G-B MCM-Flash Example Mask ROM Part Reset/Alarm Combined Input for Regulator Input Supervision Clock and Supply Supervision 10 Bit ADC, charge balance type 16 channels (6 selectable as digital input) 16 channels (each selectable as digital input) ADC Reference VREF Pin VREF Pin, P1.0 Pin, P1.1 Pin or VREFINT Internal Bandgap selectable Comparators P06COMP with 1/2 AVDD reference P06COMP with 1/2 AVDD reference, WAITCOMP with Internal Bandgap reference LCD Internal processing of all analog voltages for the LCD driver Communication DMA 1 DMA Channel for servicing a port or an SPI 3 DMA Channels, one each for servicing the Graphics Bus interface, SPI0 and SPI1 UART 2: UART0 and UART1 Synchronous Serial Peripheral Interfaces 2: SPI0 and SPI1 Full CAN modules V2.0B 3: CAN0, CAN1 and CAN2 with 256bytes of object RAM each (LCAN0009) DIGITbus 1 master module I2C 2 master modules: I2C0 and I2C1 3: CAN0, CAN1 and CAN2 with 512bytes of object RAM each (LCAN0009) 2: CAN0 and CAN1 with 512bytes of object RAM each (LCAN0009) Input & Output 8 Universal Ports selectable as 4:1 mux LCD Segment/Backplane lines or Digital I/O Ports up to 54 I/O or 50 LCD segment lines (=200 segments) up to 52 I/O or 48 LCD segment lines (=192 segments), individually configurable as I/O or LCD Universal Port Slew Rate Mask selectable SW selectable Stepper Motor Control Modules with high current ports 7 Modules, 32 dI/dt controlled ports PWM Modules, each configurable as two 8Bit PWMs or one 16Bit PWM 6 Modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/11 Phase-Frequency Modulator - Audio Module with auto-decay SW selectable Clock outputs 2 1: PFM0 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Analog CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 1-1: CDC32xxG Family Feature List This Device: Item CDC3205G-A EMU CDC3205G-B EMU CDC3207G-B MCM-Flash Example Mask ROM Part Timers & Counters 16bit free running counters with Capture/Compare modules CCC0 with 4 CAPCOM CCC1 with 2 CAPCOM 16bit timers 1: T0 8bit timers 4: T1, T2, T3 and T4 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Miscellaneous Scalable layout in CAN, RAM and ROM - Various randomly selectable HW options Most options SW programmable, copy from user program storage during system start-up Mask programmed according to user specification JTAG test interface allows Flash programming On Chip Debug Aids Embedded Trace Module, JTAG JTAG Core Bond-Out - Supply Voltage 4.5 to 5.5V Ambient Temperature Range -40 to +85C 3.5 to 5.5V (limited I/O performance below 4.5V) Package Type Ceramic 257PGA Plastic 128QFP 0.5mm pitch Bonded Pins 256 128 ARM and Thumb are the registered trademarks of ARM Limited. ARM7TDMI is the trademark of ARM Limited. 1.2. Abbreviations AM CAN CAPCOM CCC CPU DMA ERM ETM ICU I2C LCD P06COMP PINT PWM SM SPI T Micronas Audio Module Controller Area Network Module Capture/Compare Module Capture/Compare Counter Central Processing Unit Direct Memory Access Module EMI Reduction Mode Embedded Trace Module Interrupt Controller I2C Interface Module Liquid Crystal Display Module P0.6 Alarm Comparator Port Interrupt Module 8Bit Pulse Width Modulator Module Stepper Motor Control Module Serial Synchronous Peripheral Interface Timer UART Universal Asynchronous Receiver Transmitter WAITCOMP Wait Comparator 9 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 1.3. Block Diagrams VDD VSS Reset/Alarm Test Watchdog Clock EVDD EVSS ARM7TDMI CPU JTAG Test and Debug Interface DMA Logic Bridge Boot ROM 2K x 16 Bridge 8 8Bit Timer 2 CAPCOM 1 CAPCOM 2 8Bit Timer 3 Clock Out 1 8/16B PWM 3 8Bit PWM 6 8/16B PWM 7 8Bit PWM 8 DIGITbus I2C 0 8/16B PWM 9 4 CAPCOM 4 5 4 6 8Bit PWM 10 8/16B PWM 11 I2C 1 16Bit CCC 1 CAPCOM 5 CAN 1 4 CAPCOM 3 8Bit Timer 4 8Bit PWM 4 8/16B PWM 5 UPort4 HPort3 HPort4 HPort7 CAPCOM 0 8Bit PWM 2 SPI 1 CAN 2 HVDD0 HVSS0 HVDD1 HVSS1 HVDD2 HVSS2 HVDD3 HVSS3 8Bit Timer 1 8/16B PWM 1 CAN 0 4 16Bit CCC 0 UPort5 Audio Module 8Bit PWM 0 UART 1 16Bit Timer 0 UPort6 Stepper Motor Control Clock Out 0 4 7 UPort7 HPort1 HPort2 LCD Control SPI 0 6 8 8 UART 0 6 ROMless or 512K Flash P06 Comp. 10Bit ADC 6 16 8 UPort8 6 Memory Controller HPort0 8 PPort1 32 5 UPort0 PPort0 SRAM 4K x 32 UPort1 VREF AVDD AVSS 8 PLL 40 Input Interrupt Controller XTAL1 XTAL2 UPort2 21 TEST TEST2 UPort3 ETM (Emu only) RESETQ UVDD UVSS Fig. 1-1: CDC3205G-A block diagram 10 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Data-, address- and control bus, (Emu only) 52 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Reset/Alarm EVDD EVSS 2.5V Reg. Watchdog Clock ETM (Emu only) 21 WAIT WAITH 4 16 ROMless or 512K Flash P06 Comp. Boot ROM 4K x 16 Bandgap Ref. Bridge 10Bit ADC 8 8 7 8 LCD Control Stepper Motor Control Audio Module 8Bit PWM 0 UART 1 16Bit Timer 0 16Bit CCC 0 8Bit Timer 1 CAPCOM 0 8Bit Timer 2 CAPCOM 1 8/16B PWM 1 SPI 0 CAPCOM 2 8Bit Timer 3 Clock Out 0 8Bit PWM 2 SPI 1 CAN 0 Clock Out 1 Phase-Freq.Modulator 8/16B PWM 3 8Bit PWM 6 CAN 2 8/16B PWM 7 8Bit PWM 8 DIGITbus I2C 0 8/16B PWM 9 4 CAPCOM 4 3 4 6 8Bit PWM 10 8/16B PWM 11 I2C 1 16Bit CCC 1 CAPCOM 5 CAN 1 4 CAPCOM 3 8Bit Timer 4 8Bit PWM 4 8/16B PWM 5 UPort4 UART 0 UPort5 8 UPort6 HPort4 HVDD0 HVSS0 HVDD1 HVSS1 HVDD2 HVSS2 HVDD3 HVSS3 32 5 UPort7 4 DMA Logic Memory Controller XTAL1 XTAL2 JTAG Test and Debug Interface SRAM 8K x 32 Wait Comp. TEST TEST2 UPort8 4 HPort5 4 HPort6 4 2.5V Reg. Bridge PPort1 HPort1 4 HPort3 4 HPort2 4 PPort2 2 HPort7 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 8 HPort0 8 PLL/ERM 40 Input Interrupt Controller ARM7TDMI CPU PPort0 VREFINT VREF AVDD AVSS BVDD Test UPort0 3.3V Reg. RESETQ UPort1 Data-, address- and control bus, (Emu only) 52 VDD VSS UPort2 UVDD UVSS UPort3 FVDD FVSS UVDD UVSS Fig. 1-2: CDC3205G-B block diagram Micronas 11 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 12 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 2. Packages and Pins 2.1. Pin Assignment All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Y 129 125 121 117 113 109 105 101 99 97 95 93 91 89 85 81 77 73 69 65 Y W 133 127 123 119 115 111 107 103 104 98 96 90 87 83 79 75 71 67 63 61 W V 137 131 128 124 120 116 114 110 108 102 92 86 84 80 76 72 68 64 59 57 V U 141 135 132 130 126 122 118 112 106 100 94 88 82 78 74 70 66 60 55 53 U T 145 139 136 134 62 56 51 49 T R 149 143 140 138 58 52 47 45 R P 153 147 144 142 54 50 43 41 P N 155 151 148 146 48 46 39 37 N M 157 154 150 152 42 44 40 35 M L 159 160 156 158 36 38 34 33 L Top View K 161 162 166 164 30 28 32 31 K J 163 168 172 170 24 22 26 29 J H 165 167 174 176 18 20 23 27 H G 169 171 178 182 14 16 19 25 G F 173 175 180 186 10 12 15 21 F E 177 179 184 190 257 6 8 11 17 E D 181 183 188 194 198 202 206 210 216 222 228 234 240 246 250 254 2 4 7 13 D C 185 187 192 196 200 204 208 212 214 220 230 236 238 242 244 248 252 256 3 9 C B 189 191 195 199 203 207 211 215 218 224 226 232 231 235 239 243 247 251 255 5 B A 193 197 201 205 209 213 217 219 221 223 225 227 229 233 237 241 245 249 253 1 A 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 65 129 Top View 193 257 1 A1 Fig. 2-1: Pin Map of CPGA257 Package Micronas 13 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 2-1: Pin Assignment for CPGA257 Package Table 2-1: Pin Assignment for CPGA257 Package Pin No. Pin No. 14 LCD Mode SEG5.3 SEG5.2 SEG5.1 SEG5.0 SEG2.1 SEG2.0 SEG1.7 SEG1.6 SEG1.5 SEG1.4 SEG1.3 SEG1.2 SEG1.1 SEG1.0 SEG0.7 SEG0.6 SEG0.5 SEG0.4 SEG0.3 SEG0.2 SEG0.1 SEG0.0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Coord. Basic Function Y1 EVSS6 U4 D0 W3 OEQ V4 CE0Q Y2 BWQ3 U5 BWQ2 W4 BWQ1 V5 BWQ0 Y3 EMUTRI U6 ABORT W5 EXTERN0 V6 EXTERN1 Y4 H7.3 U7 H7.2 W6 H7.1 V7 H7.0 Y5 HVDD2 U8 HVSS2 W7 H6.3 V8 H6.2 Y6 H6.1 V9 H6.0 W8 H5.3 U9 H5.2 Y7 HVDD0 W9 HVSS0 Y8 H5.1 V10 H5.0 Y9 H4.3 U10 H4.2 Y10 H4.1 W10 H4.0 Y11 H3.3 W11 H3.2 Y12 H3.1 U11 H3.0 Y13 H2.3 V11 H2.2 W13 HVDD1 W12 HVSS1 Y14 H2.1 U12 H2.0 W14 H1.3 V12 H1.2 Y15 H1.1 V13 H1.0 W15 HVDD3 U13 HVSS3 Y16 H0.3 V14 H0.2 W16 H0.1 V15 H0.0 Y17 nTRST U14 ETDI W17 ETMS V16 ETCK Y18 ETDO U15 ABE W18 CE1Q V17 FBUSQ Y19 AMCS1 U16 AICU2 W19 AICU3 V18 EVSS5 Port Special In SME-COMP Pin Functions Port Special Out LCD Mode SME1+/PWM4 SME1-/PWM6 SME2+/PWM8 SME2-/PWM9 PWM8 PWM9 PWM10 PWM11 SMD1+ SMD1- SMD-COMP SMA-COMP SMB-COMP SMD2+ SMD2SMA1+ SMA1SMA2+ SMA2SMB1+ SMB1SMB2+ SMB2SMC1+ SMC1- SMF-COMP SMC2+ SMC2SMF1+ SMF1SMF2+ SMF2- SMG-COMP SMG1+/PWM1 SMG1-/PWM3 SMG2+/PWM5 SMG2-/PWM7 SMC-COMP All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 CoPin Functions ord. Basic Port Port Function Special In Special Out A1 U5.3/GD3 CC4-IN CC4-OUT D4 U5.2/GD2 SDA1 SDA1 C2 U5.1/GD1 SCL1 SCL1 D3 U5.0/GD0 PFM0 B1 U2.1 SDA0/CAN0-RX SDA0 E4 U2.0 SCL0 SCL0/CAN0-TX D2 U1.7 PINT0 PFM0 E3 U1.6 PINT1 CO0/INTRES C1 U1.5 PINT2 CO0Q/CO1 F4 TEST E2 RESETQ/ALARMQ F3 XTAL2 D1 XTAL1 G4 VSS F2 VDD G3 U1.4 ITSTOUT/AM-OUT E1 U1.3 MTO/AM-PWM H4 U1.2 MTI/ITSTIN T0-OUT/INTRES G2 U1.1 T1-OUT H3 U1.0 T2-OUT F1 U0.7 T3-OUT J3 U0.6 CC3-IN T4-OUT/CC3-OUT H2 U0.5 PINT4 CC3-OUT J4 U0.4 PINT5 CO1 G1 U0.3 PWM0 J2 U0.2 PWM1 H1 U0.1 PWM2 K3 U0.0 PWM3 J1 D31 K4 D30 K1 D29 K2 D28 L1 D27 L2 D26 M1 D25 L4 EVDD8 N1 EVSS8 L3 D24 N2 D23 M2 D22 P1 D21 M4 D20 P2 D19 M3 D18 R1 D17 N3 D16 R2 D15 N4 D7 T1 D14 P3 EVDD7 T2 EVSS7 R3 D6 U1 D13 P4 D5 U2 D12 T3 D4 V1 D11 R4 D3 V2 D10 U3 D2 W1 D9 T4 D1 W2 D8 V3 EVDD6 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 3 DEC 01 Table 2-1: Pin Assignment for CPGA257 Package Table 2-1: Pin Assignment for CPGA257 Package Pin No. Pin No. 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 CoPin Functions ord. Basic Port Port Function Special In Special Out Y20 EVDD5 U17 AICU4 V19 AICU5 U18 AICU6 W20 AICU7 T17 A8 U19 A18 T18 A19 V20 EVDD4 R17 EVSS4 T19 WEQ/RWQ R18 A9 U20 A10 P17 A11 R19 A12 P18 A13 T20 A14 N17 A15 P19 EVDD3 N18 EVSS3 R20 A16 M18 A17 N19 A20 M17 A21 P20 A22 M19 A23 N20 AMCM21 L18 AMCM22 M20 EVDD2 L17 EVSS2 L20 AMCM23 L19 SEQ K20 nMREQ K19 MAS0 J20 MAS1 K17 nRESET H20 P1.7 PINT5 K18 P1.6 PINT4 H19 P1.5 PINT3 J19 P1.4 PINT2 G20 P1.3 PINT1 J17 P1.2 PINT0 G19 P1.1 VREF1 J18 P1.0 VREF0 F20 VREF H18 VREFINT F19 AVDD H17 AVSS E20 BVDD G18 WAIT E19 WAITH F18 P0.7 D20 P0.6 P0.6 Comp. G17 P0.5 D19 P0.4 E18 P0.3 C20 P0.2 F17 P0.1 C19 P0.0 CC4-IN D18 P2.1 B20 P2.0 E17 U6.2 GWEQ B19 U6.1 CAN1-RX GOEQ C18 U6.0 CAN1-TX Micronas LCD Mode SEG6.2 SEG6.1 SEG6.0 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 CoPin Functions ord. Basic Port Port Function Special In Special Out LCD-SYNC-OUT A20 U8.5 CAN2-RX/PINT3 D17 U8.4 LCD-SYNC-IN CAN2-TX B18 U8.3 (CAN3-RX) LCD-CLK-OUT C17 U8.2 LCD-CLK-IN (CAN3-TX) A19 U8.1 CC3-OUT D16 U8.0 CC4-OUT B17 U4.3 CAN0-RX TO2 C16 U4.2 CAN0-TX A18 U4.1 CC0-IN SPI1-D-OUT D15 U4.0 SPI1-D-IN CC0-OUT B16 U3.7 SPI1-CLK-IN SPI1-CLK-OUT C15 U3.6 SPI0-D-OUT A17 U3.5 SPI0-D-IN TO3 D14 U3.4 SPI0-CLK-IN SPI0-CLK-OUT B15 U3.3 CO0/TDO C14 U3.2 CC0-IN / TCK CC0-OUT A16 U3.1 CC1-IN / TMS CC1-OUT D13 U3.0 CC2-IN / TDI CC2-OUT B14 TEST2 C13 UVDD1 A15 UVSS1 C12 TRACEPKT0 / TBIT B13 TRACEPKT1 / nM0 D12 TRACEPKT2 / nM1 A14 TRACEPKT3 / nM2 B12 TRACEPKT4 / nM3 A13 TRACEPKT5 / nM4 C11 EVDD1 A12 EVSS1 D11 TRACEPKT6 / LOCK A11 TRACEPKT7 / nEXEC B11 TRACEPKT8 / nOPC A10 TRACEPKT9 / nTRANS B10 TRACEPKT10 / A5 A9 TRACEPKT11 / A6 D10 TRACEPKT12 / RANGEOUT0 A8 TRACEPKT13 / RANGEOUT1 C10 TRACEPKT14 / A7 B8 TRACEPKT15 / BREAKPT B9 PIPESTAT0 / nRW A7 PIPESTAT1 / A0 D9 PIPESTAT2 / A1 B7 EVDD0 C9 EVSS0 A6 TRACESYNC/A2 C8 TRACECLK/A3 B6 EXTTRIG/A4 D8 FSYS A5 nWAIT C7 DBGACK B5 DBGRQ C6 UVDD A4 UVSS D7 U2.6 DIGIT-IN DIGIT-OUT B4 U2.5 UART0-RX CC1-OUT C5 U2.4 CC1-IN UART0-TX A3 U2.3 UART1-RX CC2-OUT D6 U2.2 CC2-IN UART1-TX B3 U7.7/GD7 CO0 C4 U7.6/GD6 CO1 A2 U7.5/GD5 LCK(/PFM1) D5 U7.4/GD4 CC5-IN CC5-OUT B2 FVDD C3 FVSS E5 Extra insertion Pin: connect to system ground LCD Mode SEG8.5 SEG8.4 SEG8.3 SEG8.2 SEG8.1 SEG8.0 BP3 BP2 BP1 BP0 SEG3.7 SEG3.6 SEG3.5 SEG3.4 SEG3.3 SEG3.2 SEG3.1 SEG3.0 SEG2.6 SEG2.5 SEG2.4 SEG2.3 SEG2.2 SEG7.7 SEG7.6 SEG7.5 SEG7.4 15 50.8 0.5 20.7 0.1 18.85 0.1 16 INDEX MARK PLATING OPTION 1 0.1 0.2 4.80 0.20 0.2 1 0.1 0.46 0.05 0.8 A B C D E F G H J K L M N P R T U V W Y 1 2 3 4 5 2.540 0.15 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 0.4 0.1 2.1 0.20 6 7 8 9 EXTRA PIN 10 11 12 13 14 15 16 17 18 19 20 2.540 x 19 = 48.26 0.2 2.540 x 19 = 48.26 0.2 2.540 0.15 D0029/1E CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 2.2. Package Outline Dimensions Fig. 2-2: CPGA257 Ceramic Pin Grid Array 257-Pin (Weight approx. 32g. Dimensions in mm) Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 2.3. Multiple Function Pins 2.3.1. U-Ports 2.3.3. Emulator Bus Beside their basic function (digital I/O), Universal Ports (prefix "U") have overlaid alternative functions (see Table 2-1 on page 14). In contrast to the PQFP128 standard package, the CPGA257 package has additional pins (Emulator Bus) which serve as memory interface, Emulation JTAG interface or connection to an external emulation or trace hardware (Trace Bus). How to enable Basic Function, Special In and Special Out mode is explained in the functional description of the UPorts. How to enable LCD mode is explained in the functional descriptions of LCD module and U-Ports. 2.3.2. H-Ports Beside their basic function (digital I/O), High Current Ports (prefix "H") have overlaid alternative functions (see Table 2-1 on page 14). The functionality of the memory interface and the Trace Bus is controlled by register CR. Refer to section "Control Word" for more information. Some of the following pins are marked as being ARM or ETM signals. For details of the functionality please refer to ARM7TDMI Data sheet (Document Number: ARM DDI 0029) or Embedded Trace Macro Cell (Document Number: ARM IHI 0014 and ARM DDI 0158). All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. How to enable Basic Function, Special In and Special Out mode is explained in the functional description of the HPorts. 2.4. Pin Function Description A0 to A7 (ARM) 1) A8 to A23 (ARM) 4) These 24 lines are the original CPU addresses. Some are used for external memory access on the Emulator Bus. The function is controlled by register CR. AVDD This is the positive power supply for ADC, P06COMP, WAITCOMP and BVDD regulator. AVDD should be kept at UVDD 0.5V. It must be buffered by an external capacitor to analog ground ABE (ARM) 1) 2) This pin outputs the "Address bus enable" signal of the ARM. It indicates that the CPU does not access the data and address bus when low. It is not possible to influence the CPU via this pin. AVSS This is the negative reference for the ADC and the negative power supply for ADC, P06COMP, WAITCOMP and PLL. Connect to analog ground. ABORT (ARM) 3) This is an input which allows the memory system to tell the processor that a requested access is not allowed. AICU2 to AICU7 4) These pins correspond to the ARM address bus lines A2 to A7 but can be modified by the ICU. In the latter case AICUx and Ax are not equal. ALARMQ This is the second input comparator level on the RESETQ pin. AMCM21 to AMCM23 4) These pins correspond to the ARM address bus lines A21 to A23 but can be modified by the memory controller. In the latter case AMCMx and Ax are not equal. AMCS1 4) This pin corresponds to the ARM address bus line A1 but can be modified by the memory controller. In the latter case AMCS1 and A1 are not equal. AM-OUT This is the output signal of the Audio Module. AM-PWM This is the output signal of the 8-bit PWM of the Audio Module. It is intended for testing only. These signals are the compare outputs of the CAPCOM0 to Micronas BP0 to BP3 These pin functions serve as Backplane drivers for a 4:1 multiplexed LCD. BREAKPT (ARM) 3) This is the input pin for the ARM BREAKPT signal in Full Trace mode. It allows external hardware to halt the execution of the processor for debug purposes. BVDD This is the output of the internal 2.5V regulator for the PLL. It must be buffered by an external capacitor to analog ground. BWQ0 to BWQ3 4) This is the byte write control signal to an external 32bit memory. CAN0-RX, CAN1-RX, CAN2-RX These signals provide the input lines for the CAN0, CAN1, CAN2 and CAN3 modules. CAN0-TX, CAN1-TX, CAN2-TX These signals provide the output lines for the CAN0, CAN1, CAN2 and CAN3 modules. CC0-IN, CC1-IN, CC2-IN, CC3-IN, CC4-IN, CC5-IN These signals are the capture inputs of the CAPCOM0 to CAPCOM5 modules. CC0-OUT, CC1-OUT, CC2-OUT, CC3-OUT, CC4-OUT, CC5-OUT CAPCOM5 modules. 17 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 CE1Q 4) Chip Enable output signal connects to external RAM or Boot ROM memory's CEQ pin and reduces it's power consumption when CPU operates in slow mode. Active LOW. CO0, CO0Q, CO1 These signals provide frequency outputs. They are connected to internal prescaler and multiplexer. They can be hard wired by HW Option. Refer to section "Hardware Options" for setting the CO0/CO1 options and section "CPU and Clock System" setting the Clock Out 0 Selection register. For testing purposes it is possible to drive clocks and other signals of internal peripheral modules out of CO0 and CO1. Selection is done via register TST2. D0 to D31 (ARM) 4) These 32 signals are the original CPU bidirectional Data Bus lines. They provide the 32bit data bus for use during data exchanges between the microprocessor and external memory or peripherals. EXTERN0, EXTERN1 (ARM) 3) These are inputs to the ICEBreaker logic of the ARM which allows breakpoints and/or watch points to be dependent on an external condition. EXTTRIG (ETM) 2) This is a trigger input to the ETM. FBUSQ 4) This signal is the reference for access to external synchronous memory. It is active for memory access only. FSYS This signal provides the system frequency clock fSYS. It is the PLL output frequency if PLL is enabled. FVDD This is the output of the internal 3.3V regulator for the external Flash chip. It must be buffered by an external capacitor to FVSS. FVSS This is the ground reference of the internal 3.3V regulator for the external Flash chip. GD0 to GD7 These eight Graphics IC Data lines provide an 8-bit DMA controlled data link to an external IC. DBGACK (ARM) This is the debug acknowledge output signal of the ARM. When high indicates ARM is in debug state. GOEQ This Graphics IC Read line provides the control signal for read accesses via the GD7 to GD0 bus. Active LOW. DBGRQ (ARM) 3) This is the debug request input of the ARM. It is a level-sensitive input, which when high causes ARM to enter debug state after executing the current instruction. GWEQ This Graphics IC Write line provides the control signal for write accesses via the GD7 to GD0 bus. Active LOW. DIGIT-IN This is the receive input line of the DIGITbus module. H0.0 to H7.3 The High Current Ports are intended for use as digital I/O which can drive higher currents than the Universal Ports. DIGIT-OUT This is the transmit output line of the DIGITbus module. EMUTRI This input signal allows to tristate (= high) the interface pins to external memory (A8 to A23, AMCS1, AICU2 to AICU7, AMCM21 to AMCM23, CE1Q, FBUSQ and WEQ/RWQ). ETCK (ARM) This pin is the ARM "Test clock" input (TCK) of the Emulation JTAG interface. ETDI (ARM) This pin is the ARM "Test data input" (TDI) of the Emulation JTAG interface. ETDO (ARM) This pin is the ARM "Test data output" (TDO) of the Emulation JTAG interface. ETMS (ARM) This pin is the ARM "Test mode select" (TMS) input of the Emulation JTAG interface. EVDD0 to EVDD8 These 9 lines form the positive power supply of the Emulator and Trace Bus drivers. EVDD0 to EVDD8 may be connected to any voltage between 3 to 5.5V. Normally they are connected to FVDD. EVSS0 to EVSS8 These 9 lines form the negative supply of the Emulator Bus and Trace drivers. EVSS0 to EVSS8 have to be hard wired to system ground. 18 HVDD0 to HVDD3 The pins HVDD0 to HVDD3 are the positive power supply of the high current ports H0.0 to H7.3. HVDD0 to HVDD3 should be kept at UVDD 0.5V. Be careful to design the PCB traces for carrying the considerable operating current on these pins. HVSS0 to HVSS3 The pins HVSS1 to HVSS3 are the negative power supply for the high current ports H0.0 to H7.3. HVSS0 to HVSS3 have to be hard wired to system ground. Be careful to layout sufficient PCB traces for carrying the considerable operating current on these pins. INTRES Test output of internal reset signal. Only for testing and available only in test mode. ITSTIN Test input signal for Interrupt Controller. Only for testing and available only in test mode. ITSTOUT Test output signal of internal peripheral modules. Only for testing and available only in test mode. LCD-CLK-IN The Clock input of the LCD module receives the clock of an optional external LCD master driver which is used to extend the LCD driver capability. This input is active if the internal LCD module is configured as slave and the external LCD driver operates as master. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CE0Q 4) Chip Enable output signal connects to external program memory's CEQ pin. With CR.EFLA set it serves to reduce program memory's power consumption when CPU operates in slow mode. Active LOW. ADVANCE INFORMATION CDC32xxG-B V3.0 3 DEC 01 LCD-CLK-OUT The Clock output of the LCD module provides a clock signal to optional external LCD slave drivers if the internal LCD module is configured as master and the other LCD drivers are slaves. LCD-SYNC-IN The Synchronization input of the LCD module receives the sync signal from an optional external LCD master driver. This input is active if the internal LCD module is configured as slave and the external LCD driver serves as master. LCD-SYNC-OUT The Synchronization output of the LCD module provides a sync signal to optional external LCD slave drivers if the internal LCD module is configured as master and the other LCD drivers are slaves. LCK This output signal indicates that the PLL has locked. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. LOCK (ARM) 1) This is the LOCK output signal of the ARM indicating that the processor is performing a "locked" memory access when high. MAS0, MAS1 (ARM) 1) 2) These are ARM output signals used by the processor to indicate to the external memory system when a word transfer or a half-word or a byte length is required. MTI This is a test input line. It is intended for factory test only. The application should not use this signal. MTO This is a test output line. It is intended for factory test only. The application should not use this signal. nEXEC (ARM) 1) This is the "Not executed" signal of the ARM indicating that the instruction in the execution unit is not being executed when high. nM0 to nM4 (ARM) 1) These pins output the "Not processor mode" signal of the ARM. nMREQ (ARM) 1) 2) This pin outputs the "Not memory request" signal of the ARM. The processor requires memory access during the following cycle when low. nOPC (ARM) 1) This pin outputs the "Not op-code fetch" signal of the ARM. The processor is fetching an instruction from memory when low. nRESET (ARM) This pin outputs the "Not reset" signal of the ARM. This pin is not an input. nRW (ARM) 1) This pin outputs the "Not read/write" signal of the ARM. High indicates a processor write cycle, low a read cycle. nTRANS (ARM) 1) This pin outputs the "Not memory translate" signal of the ARM. When low it indicates that the processor is in user mode. nTRST (ARM) This pin is the "Not test reset" signal of the ARM. It resets the boundary scan logic of the CPU when low. It is also the reset Micronas for the Emulation JTAG interface (not for the application JTAG interface). nWAIT (ARM) 1) 2) This pin outputs the "Not wait" signal of the ARM. It is not possible to cause a wait via this pin. OEQ 4) The Output Enable signal connects to the OEQ pin of external memory for read access. Active LOW. P0.0 to P0.7, P1.0 to 1.7 and P2.0 to P2.1 P0.0 to P1.7 are 16 analog ports that are the multiplexed input channels of the ADC. All analog ports P0.0 to P2.1 can also be used as digital input lines. The analog ports P1.2 to P1.7 can also be used as port interrupts. P06 Comp. The analog port P0.6 is additionally input to the P06 comparator. PFM0 This is the output of the Pulse Frequency Module, PFM. PINT0 to PINT5 The Port Interrupt 0 to 5 inputs serves as inputs to the interrupt controller via the port interrupt module. HW option PM.PINT has to be set to determine which of the possible input pins are used as source of PINT0 to 5. PIPESTAT0 to PIPESTAT2 (ETM) 2) These signals indicate the pipeline status of the ETM. PWM0 to PWM11 These are the outputs of the PWM module. Some of these PWM signals are directed to two pins. RANGEOUT0, RANGEOUT1 (ARM) 1) These pins output the "ICEBreaker rangeout" signals of the ARM. They indicate that ICEBreaker watch point register 0 or 1 has matched the conditions currently present on the address, data and control busses. RESETQ This bidirectional signal is used to initialize all modules and start program execution. Two comparators distinguish three input levels: - A low level resets all internal modules. - A medium level activates all internal modules and starts program execution. An alarm signal is generated which can be directed to the interrupt controller. - A high level keeps all internal modules active and cancels the alarm signal. The RESETQ input signal must be held low for at least two clock cycles after VDD reaches operating voltage. Internal reset sources output their reset request on the RESETQ pin via an internal open drain pull-down transistor. Thus RESETQ can be wire-ored with external reset sources. The internally limited pull-down current allows direct connection to large capacitors. The connection of such a capacitor (e.g. 10nF) is recommended to reduce the capacitive influence of the neighboring XTAL2 pin. RESETQ must be pulled up by an external pull-up resistor (e.g. 10k). RWQ 4) This is an interface signal to external memory. SCL0 to SCL1 These are the serial clock lines of the I2C modules. 19 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 SDA0 to SDA1 These are the serial data lines of the I2C modules. TEST2 serves to enable the JTAG interface. Refer to section "JTAG Interface" for detailed information. SEG0.0 to SEG8.5 These pin functions serve as Segment drivers for a 4:1 multiplexed LCD. For normal operation with internal code connect TEST and TEST2 to System Ground or leave it floating (internal pulldown). SEQ (ARM) 1) 2) This pin outputs the "Sequential address" signal of the ARM. High indicates that the address of the next memory cycle will be related to that of the last memory access. TMS (ARM) This pin is the ARM "Test mode select" input of the application JTAG interface. SMA-COMP to SMG-COMP These lines are comparator inputs that connect to one line each of the SMA to SMG lines. They serve to distinguish rotation from stand-still during zero detection in each stepper motor. SPI0-CLK-IN, SPI1-CLK-IN The Serial Synchronous Peripheral Interface Clock input receives the bit clock from an external master, to shift data in or out of SPI0 resp. SPI1 in slave mode. This means that the external master controls the bit stream. SPI0-CLK-OUT, SPI1-CLK-OUT The Serial Synchronous Peripheral Interface Clock output supplies the bit clock of SPI0 resp. SPI1 to an external slave, to shift data in or out of SPI0 resp. SPI1 in master mode. This means that the internal SPI controls the bit stream. SPI0-D-IN, SPI1-D-IN These are the data input lines of the SPI0 and SPI1 modules. SPI0-D-OUT, SPI1-D-OUT These are the data output lines of the SPI0 and SPI1 modules. T0-OUT The Timer 0 output is connected to the zero output of T0 by a divide by 2 scaler. The scaler generates a 50% pulse duty factor. T1-OUT to T4-OUT These signals are connected to the overflow outputs of T1 to T4. TBIT (ARM) 1) This pin outputs the TBIT signal of the ARM. High indicates that the processor is executing the THUMB instruction set. TCK (ARM) This pin is the ARM "Test clock" input of the application JTAG interface. TDI (ARM) This pin is the ARM "Test data input" of the application JTAG interface. TDO (ARM) This pin is the ARM "Test data output" of the application JTAG interface. TEST, TEST2 Pins TEST and TEST2 define the source for the Control Word fetch during reset. Please refer to section "Core Logic" for detailed information. 20 TO2 and TO3 Test outputs. TRACECLK (ETM) 2) This is the output of the modified CLK signal of the ETM. TRACEPKT0 to TRACEPKT15 (ETM) 2) This is the trace packet port of the ETM. TRACEPKT15 is pulled low to prevent floating, when full trace mode is enabled. TRACESYNC (ETM) 2) This is the synchronization signal from the ETM, indicating the start of a branch sequence on the trace packet port. U0.0 to U8.5 Universal ports are intended for use as digital I/O or as LCD driver outputs. UART0-RX, UART1-RX These are the Receive input lines of UART0 and UART1. Polarity of the signals is settable by HW options UA0 resp. UA1. UART0-TX, UART1-TX These are the data output lines of UART0 and UART1. Polarity of signals is settable by HW options UA0 resp. UA1. UVDD, UVDD1 The pins UVDD and UVDD1 are the positive 5V supply for the U-Port output stages, for the VDD regulator and the FVDD regulator. (see Fig. 2-3 for external connection). It must be buffered by an external capacitor to UVSS resp. UVSS1. UVSS, UVSS1 The pins UVSS and UVSS1 are the negative power supply for the U-Port output stages, and the ground reference for the VDD and FVDD regulators. They have to be connected to system ground (see Fig. 2-3). VDD This is the output of the internal 2.5V regulator for the internal digital modules (see Fig. 2-3 for external connection). It must be buffered by an external capacitor to VSS. VREF, VREF0, VREF1 These pins are selectable as positive reference inputs for the ADC. The voltage on these pins should be set to a level between 2.56 Volts and AVDD. VREFINT This pin is the positive reference output of the ADC. The voltage at this pin is generated internally (approx. 2.5V) and must be buffered by an external capacitor to AVSS. No DC load is allowed. VSS The pin VSS is the negative supply terminal of the internal digital modules (see Fig. 2-3 for external connection). WAIT This is the positive input to the WAIT comparator. The nega- Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. SMA to SMG These lines are intended for driving stepper motors. They are the outputs of the SM. Two of these lines together with an external coil form an H-bridge. Thus each of the signals SMA to SMG can drive a two phase bipolar stepper motor. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 tive input is VREFINT. The comparator level can be adjusted by an external voltage divider. memory's WEQ pin and activates it for write access. Active LOW. WAITH This is the output of the WAIT comparator. The hysteresis can be adjusted by an external feedback resistor to the voltage divider connected to the WAIT pin. XTAL1 This is the quartz oscillator or clock input pin (see Fig. 2-3 for external connection). WEQ 4) The output signal Write Enable connects to the external XTAL2 This is the quartz oscillator output pin for two pin oscillator circuits (see Fig. 2-3 for external connection). 1) Trace Bus output. Active in Analyzer mode. 2) Trace Bus output. Active in ETM mode. 3) Trace Bus input. Always active. 4) Memory interface signal. Tristate if EMUTRI is high. Please refer to section "Memory Interface" (see Table 32-1 on page 217) for details about interfaces and Trace Bus modes. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 2.5. External Components To provide effective decoupling and to improve EMC behaviour, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. Too low a frequency will reduce decoupling effectiveness, will increase RF emissions and may adversely affect device operation. strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. The RESETQ pin adjacent to XTAL2 should be supplied with a small capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, and to prevent XTAL2 from coupling into RESETQ. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other pc board signals. It is FVDD 3.3 Tantal ESR < 14 470n Ceramic X7R +5V Supply EVDD0 to 8 9 x 100n to 150n 3.3V FVSS 5V UVDD UVDD1 EVSS0 to 8 System Ground HVDD0 to 3 +5V Supply 2 x 100n to 150n System Ground 3.3V/5V Supply 4 x 100n to 150n UVSS UVSS1 5V HVSS0 to 3 System Ground AVDD Analog Supply 2.5V VDD 10 Tantal Low ESR 220n Ceramic X7R VSS 100n to 150n XTAL1 18p VREFINT 5V 10n, Ceramic 2.5V 18p XTAL2 Resetq Analog Ground AVSS BVDD 150n Ceramic, X7R RESETQ Fig. 2-3: CDC3205G-B: Recommended external supply and quartz connection. Micronas 21 VSUPIN Input Logic GNDIN 22 Input Logic GNDIN GNDIN GNDOUT GNDOUT Fig. 2-4: Input Pins VSUPOUT VSUPIN GNDH Fig. 2-5: Input Pins with Pull-Down weak VSUPOUT GNDOUT GNDL Fig. 2-10: Regulator Pins VSUPOUT VSUPIN Input Logic GNDIN GNDOUT Fig. 2-6: Push Pull I/O Pins All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Input Logic weak CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 2.6. Pin Circuits VSUPOUT VSUPIN Fig. 2-9: Push Pull I/O Pins with switchable Pull-Down VSUPH Regulator Logic VSUPL VSUPOUT VSUPIN Input Logic GNDIN GNDOUT Fig. 2-7: Open Drain I/O VSUPOUT GNDOUT Fig. 2-8: Push Pull Output Pins Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 2-2: I/O Supply Catalog Pin Names Figure VSUPOUT GNDOUT VSUPIN GNDIN XTAL1, XTAL2 2-4 UVDD UVSS UVDD UVSS WAIT AVDD AVSS AVDD AVSS TCK, TDI, TMS EVDD EVSS EVDD EVSS UVDD UVSS UVDD UVSS H-Ports HVDD HVSS HVDD HVSS P-Ports AVDD AVSS AVDD AVSS A31 to A0, ABE, AICU7 to 2, AMCM21 to 23, AMCS1, BWQ0 to 3, CE0Q, CE1Q, D31 to D0, DBGACK, EXTTRIG, FBUSQ, FSYS, MAS0, MAS1, nMREQ, nRESET, nTRST, nWAIT, OEQ, PIPSTAT0 to 2, SEQ, TDO, TRACECLK, TRACEPKT0 to 14, TRACESYNC EVDD EVSS EVDD EVSS UVDD UVSS EMUTRI, ABORT, EXTERN0, EXTERN1, DBGRQ 2-5 TEST, TEST2 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. U-Ports 2-6 RESETQ 2-7 UVDD UVSS WAITH 2-8 AVDD AVSS TRACEPKT15 2-9 EVDD EVSS EVDD EVSS Regulator Figure VSUPH GNDH VSUPL GNDL VDD 2-10 UVDD UVSS VDD VSS FVDD UVDD UVSS FVDD FVSS BVDD AVDD AVSS BVDD AVSS Table 2-3: Regulator Pin Supply Catalog Micronas 23 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 24 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 3. Electrical Characteristics 3.1. Absolute Maximum Ratings Table 3-1: UVSS=UVSS1=HVSSn=FVSS=EVSSn=AVSS=0V Symbol Parameter Pin Name Min. Max. Unit VSUP Main Supply Voltage Analog Supply Voltage SM Supply Voltage Flash Port Supply Voltage UVDD, UVDD1 AVDD HVDD0 .. HVDD3 EVDD0 .. EVDD8 -0.3 6.0 V VEXT External Flash Supply Voltage FVDD -0.3 4.0 V External Core Supply Voltage External Regul. Analog Supply Voltage VDD BVDD -0.3 3.0 V Core Supply Current Main Supply Current VDD, VSS, UVDD, UVDD1, UVSS, UVSS1 -100 100 mA Flash Port Supply Current EVDD0 .. EVDD8 EVSS0 .. EVSS8 -100 100 Analog Supply Current AVDD, AVSS -20 20 SM Supply Current @Tj=105C, Duty Factor=0.71 1) HVDD0 .. HVDD3 HVSS0 .. HVSS3 -250 250 FVDD Regulator Output Current FDD, FVSS -50 50 BVDD Regulator Output Current BVDD -20 20 Input Voltage U-Ports, XTAL, RESETQ, TEST, TEST2 UVSS-0.5 UVDD+0.7 V P-Ports, VREF UVSS-0.5 AVDD+0.7 V H-Ports HVSS-0.5 HVDD+0.7 V E-Ports EVSS-0.5 EVDD+0.7 V All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ISUP Vin 1 Iin Input Current all Inputs 0 2 mA Io Output Current U-Ports, E-Ports, RESETQ, WAITH -5 5 mA H-Ports -60 60 mA indefinite s toshsl Duration of Short Circuit to UVSS or UVDD, Port SLOW Mode enabled Tj Junction Temperature under Bias -45 115 C Ts Storage Temperature -45 125 C Pmax Maximum Power Dissipation 0.8 W U-Ports, except in DP Mode ) This condition represents the worst case load with regard to the intended application Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions/Characteristics" of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Micronas 25 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 3.2. Recommended Operating Conditions Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD=UVDD1=AVDD during all power-up and power-down sequences. Failure to comply with these recommendations will result in unpredictable behaviour of the device and may result in device destruction.. Symbol Parameter Pin Name Min. Typ Max. Unit VSUP Main Supply Voltage Analog Supply Voltage UVDD=UVDD1 =AVDD 3.5 5 5.5 V Flash Port Supply Voltage EVDDn 3 5.5 V HVSUP SM Supply Voltage HVDDn 4.75 5 5.25 V VEXT External Flash Supply Voltage FVDD 3 3.3 3.6 V External Core Supply Voltage External Regulated Analog Supply Voltage VDD BVDD 2.25 2.5 2.75 V dVDD Ripple, Peak to Peak UVDD AVDD BVDD FVDD VDD 200 mV dVDD/dt Supply Voltage Up/Down Ramping Rate UVDD AVDD 20 V/s fXTAL XTAL Clock Frequency XTAL1 5 MHz fSYS CPU Clock Frequency, PLL on fBUS Program Storage Clock Frequency, PLL on Vil (see Table 2-2 for a list of input types and their supply voltages) Automotive Low Input Voltage U-Ports H-Ports P-Ports 0.5*xVDD V CMOS Low Input Voltage U-Ports, TEST, TEST2 H-Ports P-Ports 0.3*xVDD V TTL Low Input Voltage E-Ports 0.8 V Automotive High Input Voltage U-Ports H-Ports P-Ports 0.86*xVDD V CMOS High Input Voltage U-Ports,TEST, TEST2 H-Ports P-Ports 0.7*xVDD V TTL High Input Voltage E-Ports 2.2 V RVil Reset Active Input Voltage RESETQ RVim Reset Inactive and Alarm Active Input Voltage RESETQ Vih (see Table 2-2 for a list of input types and their supply voltages) 26 4 For a list of available settings see Tables 4-5 and 4-6. 1.5 0.75 V 2.3 V Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Table 3-2: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 3-2: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V Symbol Parameter Pin Name Min. RVih Reset Inactive and Alarm Inactive Input Voltage RESETQ 3.2 VREFi Ext. ADC Reference Input Voltage VREF 2.56 AVDD V PVi ADC Port Input Voltage referenced to ext. VREF Reference P-Ports 0 VREFi V 0 VREFINT ADC Port Input Voltage referenced to int. VREFINT Reference Typ Max. Unit V All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Clock Input from External Generator XVil Clock Input Low Voltage XTAL1 XVih Clock Input High Voltage XTAL1 0.8*UVDD DXTAL Clock Input High to Low Ratio XTAL1 0.45 0.2*UVDD V V 0.55 3.3. Characteristics Table 3-3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V, 3V<EVDDn<5.5V, TCASE=-40 to +85C, fXTAL=5MHz, external components according to Fig. 2-3 Symbol Parameter Pin Na. Min. Typ. Max. Unit Test Conditions Package Rthjc Thermal Resistance from Junction to Case 15 C/W Supply Currents (CMOS levels on all inputs, no loads on outputs) UIDDp UVDD PLL Mode Supply Current UVDD+ UVDD1 35 mA CPU PLL Mode ON, fSYS=24MHz, ETM off UIDDpe UVDD PLL Mode Supply Current UVDD+ UVDD1 TBD mA CPU PLL Mode ON, fSYS=24MHz, ETM on UIDDf UVDD FAST Mode Supply Current UVDD+ UVDD1 10 mA CPU FAST Mode ON, all Modules OFF, 2) UIDDs UVDD SLOW Mode Supply Current UVDD+ UVDD1 1 mA CPU SLOW Mode ON, all Modules OFF, 2) UIDDd UVDD DEEP SLOW Mode Supply Current UVDD+ UVDD1 0.7 mA CPU DEEP SLOW Mode ON, all Modules OFF UVDD+ UVDD1 1 mA CPU DEEP SLOW Mode ON, only LCD Module ON 0.3 0.5 mA ADC ON, Buffer and PLL OFF 0.35 0.6 mA ADC and Buffer ON, PLL OFF 1 2 mA ADC, Buffer and PLL ON, fSYS=24MHz AIDDa Micronas AVDD Active Supply Current AVDD 27 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 3-3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V, 3V<EVDDn<5.5V, TCASE=-40 to +85C, fXTAL=5MHz, external components according to Fig. 2-3 Symbol Parameter Pin Na. AIDDq Quiescent Supply Current Min. Typ. Max. Unit Test Conditions AVDD 10 uA ADC and PLL OFF EIDDq EVDDn 10 uA no Output Activity HIDDq Sum of all HVDDn 100 uA no Output Activity, SM Module OFF 0.68* xVDD 0.76* xVDD 0.84* xVDD V 4.5V<xVDD<5.5V, 3 Automotive Input High to Low Threshold Voltage 0.53* xVDD 0.61* xVDD 0.69* xVDD V (see Table 2-2 for a list of input types and their supply voltages) Vilha-Vihla Automotive Input Hysteresis 0.1* xVDD 0.15* xVDD 0.2* xVDD V Vilhc CMOS Input Low to High Threshold Voltage 0.5* xVDD 0.6* xVDD 0.7* xVDD V 4.5V<xVDD<5.5V, 3 Vihlc CMOS Input High to Low Threshold Voltage 0.3* xVDD 0.4* xVDD 0.5* xVDD V (see Table 2-2 for a list of input types and their supply voltages) Vilhc-Vihlc CMOS Input Hysteresis 0.1* xVDD 0.2* xVDD 0.25* xVDD V Ii Input Leakage Current uA Vilha Automotive Input Low to High Threshold Voltage Vihla Ipd Ipu Input Pull-Down Current Input Pull-Up Current U-Ports H-Ports P-Ports U-Ports H-Ports P-Ports TEST, TEST2 0<Vi<UVDD 0<Vi<HVDD 0<Vi<AVDD U-Ports H-Ports P-Ports P06, WAIT VREF E-Ports -1 -10 -1 1 10 1 -0.2 -1 -1 0.2 1 1 TEST, TEST2 E-Ports 10 80 180 10 80 180 E-DB -180 -80 -10 uA Vi=0, when unused 0.4 V Io=2mA Io=27mA Io=40mA@TCASE=-40C Io=30mA@TCASE=25C 0<Vi<AVDD 0<Vi<AVDD 0<Vi<EVDD uA Vi=UVDD Vi=EVDD, when unused Outputs (4.5V<UVDD=EVDD<5.5V) Vol Port Low Output Voltage U-Ports, E-Ports RESETQ H-Ports 0.125 0.5 V 50 mV Vol Spread of Vol Values within one SM Driver Module H-Ports -50 Voh Port High Output Voltage U-Ports UVDD0.4 EVDD0.4 E-Ports H-Ports 28 HVDD0.5 HVDD0.125 V Io=-2mA V Io=-27mA Io=-40mA@TCASE=-40C Io=-30mA@TCASE=25C Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Inputs CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 3-3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V, All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 3V<EVDDn<5.5V, TCASE=-40 to +85C, fXTAL=5MHz, external components according to Fig. 2-3 Symbol Parameter Pin Na. Min. Voh Spread of Voh Values within one SM Driver Module H-Ports -50 dVoH/dt H-Port Slew Rate with Inductive Load H-Ports by first order approximation defined by the quotient of the inductive load current and the external capacitances on the port pin V/ns LVol LCD Port Zero Output Voltage U-Ports -0.05 0.05 V no load LVo1 LCD Port Low Output Voltage U-Ports 1/3 *UVDD -0.05 1/3 *UVDD +0.05 V no load LVo2 LCD Port High Output Voltage U-Ports 2/3 *UVDD -0.05 2/3 *UVDD +0.05 V no load LVoh LCD Port Full Output Voltage U-Ports UVDD 0.05 UVDD +0.05 V no load LIo1 Internal LCD-Low Supply Short Circuit Current U-Ports 0.3 mA Pin Short to 2/3*UVDD Internal LCD-High Supply Short Circuit Current U-Ports Ishf Port FAST Short Circuit Current U-Ports TBD 9 TBD mA Pin Short to UVDD or UVSS, Port FAST Mode Ishs Port SLOW Short Circuit Current U-Ports TBD 2.5 TBD mA Pin Short to UVDD or UVSS, Port SLOW Mode Ishsd Port SLOW Short Circuit Current, DP Mode U-Ports TBD 5 TBD mA Pin Short to UVDD, Port SLOW and Double PullDown Modes Typ 2% TBD (~2.50) Typ +2% V External load current < 1uA 500 us LIo2 Typ. Max. Unit 50 mV Pin Short to UVSS -0.3 0.3 Test Conditions mA Pin short to UVDD Pin short to 1/3*UVDD -0.3 References and Comparators, AVDD Section VREFINT VREFINT Generator Reference Output Voltage VREFINT tREFINT VREFINT Generator Setup Time after Power-Up on AVDD VREFINT VREFP06 P06 Comparator Reference Voltage P06 0.49* AVDD 0.51* AVDD V P06VlhP06Vhl P06 Comparator Hysteresis, symmetrical to VREFP06 P06 0.02 * AVDD 0.05 * AVDD V VREFW WAIT Comparator Reference Voltage WAIT 0.98* VRE- 1.02* VRE- V FINT FINT VWol WAIT Comparator Low Output Voltage WAITH VWoh WAIT Comparator High Output Voltage WAITH Micronas 0.4 AVDD0.4V 3) V 4.5V<xVDD<5.5V Io=50uA V 4.5V<xVDD<5.5V Io=-50uA 29 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 3-3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V, 3V<EVDDn<5.5V, TCASE=-40 to +85C, fXTAL=5MHz, external components according to Fig. 2-3 Symbol Parameter Pin Na. tACDEL P06, WAIT Comparator Delay Time P06 WAIT Min. Typ. Max. Unit Test Conditions 100 ns Overdrive=50mV 2.75 V 50 us References and Comparators, UVDD Section VBG VBG Generator Reference Output Voltage tBG VBG Generator Setup Time after Power-Up on UVDD VREFR RESET Comparator Reference Voltage RESETQ 0.45* VBG 0.45* VBG V RVlhRVhl RESET Comparator Hysteresis, symmetrical to VREFR RESETQ 0.25 0.375 V VREFA ALARM Comparator Reference Voltage RESETQ 1.1* VBG 1.1* VBG V AVlhAVhl ALARM Comparator Hysteresis, symmetrical to VREFA RESETQ 0.1 0.15 V VREFPOR UVDD Power On Reset Threshold UVDD 1.125* VBG 1.125* VBG V tUCDEL RESET, ALARM, Comparator Delay Time RESETQ 100 ns 1/9* HVDD +0.07 V 100 ns Overdrive=50mV 1.02* VBG -30mV 1.02* VBG +30mV V DEEP SLOW Mode 1.02* VBG 105mV 1.02* VBG 0mV V PLL Mode, fSYS=50MHz 275 460 mA 120 400 us 2.5 3) 3) Overdrive=50mV References and Comparators, HVDD Section VREFSM SM Comparator Reference Voltage H00, H04, H20, H24, H32, H40, H70 tHCDEL SM Comparator Delay Time H00, H04, H20, H24, H32, H40, H70 1/9* HVDD -0.07 VDD Regulator VDD_ro Regulator Output Voltage VDD IDD_rlim Regulator Internal Output Current Limit VDD tVDD_su Regulator Setup Time after Power-Up on UVDD VDD 30 120 FAST Mode Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 2.25 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 3-3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V, 3V<EVDDn<5.5V, TCASE=-40 to +85C, fXTAL=5MHz, external components according to Fig. 2-3 Symbol Parameter Pin Na. Min. BVDD Typ. Max. Unit Test Conditions VRE- VRE- V PLL Mode FINT FINT BVDD Regulator BVDD_ro Regulator Output Voltage -25mV BIDD_rlim Regulator Internal Output Current Limit BVDD tBVDD_su Regulator Setup Time after Power-Up on AVDD BVDD 17 +25mV 40 70 mA 70 230 us FAST Mode VBG *1.34 -40mV VBG *1.34 +40mV V no load VBG *1.34 -170m VBG *1.34 -40mV V IFVDD=-40mA 120 200 mA 100 330 us FVDD Regulator All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. FVDD_ro Regulator Output Voltage FVDD FIDD_rlim Regulator Internal Output Current Limit FVDD tFVDD_su Regulator Setup Time after Power-Up on UVDD FVDD 52 IFVDD=-40mA ADC (conversion reference VREFC either equal to external reference VREF or internal reference VREFINT) LSB LSB Value R Conversion Range A Conversion Result VREFC /1024 P-Ports AVSS V VREFC INT (Vin/ LSB) 000 3FF V 2.56V<VREF<AVDD or TBD<VREFINT<TBD hex AVSS<Vin<VREFC hex Vin<=AVSS hex Vin>=VREFC TSAMP=0 tc Conversion Time 4 us ts Sample Time 2 us TUE Total Unadjusted Error -4 4 LSB 2.56V<VREF<AVDD or TBD<VREFINT<TBD, 4.5V<AVDD<5.5V DNL Differential Non-Linearity -1 2 LSB 2.56V<VREF<AVDD or TBD<VREFINT<TBD, 4.5V<AVDD<5.5V Ci Input Capacitance during Sampling Period TBD pF Buffer off Serial Input Resistance during Sampling Period TBD Ri Micronas TBD Buffer on kOhm 31 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 3-3: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V, 3V<EVDDn<5.5V, TCASE=-40 to +85C, fXTAL=5MHz, external components according to Fig. 2-3 Symbol Parameter Pin Na. Min. Typ. Max. Unit Test Conditions 100 s @fXTAL=4 MHz, fSYS=16MHz PLL and ERM tSUPLL PLL Locking Time dtPLL I/O Clock Uncertainty due to PLL Jitter, short term and long term -TBD TBD ns ERM off dtERM I/O Clock Modulation due to ERM action, short term and long term 0 0 7.5 12.5 ns 0 20 ERM on, WEAK setting ERM on, NORMAL setting ERM on, STRONG setting 70 350 kHz 60 4) ns @Cl=30pF, Port FAST mode 60 4) ns @Cl=30pF, Port FAST mode 3/ fIO +60 4) ns @Cl=30pF, Port FAST mode @Cl=30pF, Port FAST mode FSUP Clock Supervision Threshold Frequency XTAL1 SPI (Fig. 3-1, Fig. 3-2) tsoci Data out Setup Time with internal clock SPI-DOUT thoci Data out Hold Time with internal clock SPI-DOUT tsoce Data out Setup Time with external clock SPI-DOUT thoce Data out Hold Time with external clock SPI-DOUT 2/ fIO 60 ns tsi Data in Setup Time with external clock SPI-D-IN 1/ fIO+60 ns Data in Hold Time with external clock SPI-D-IN 1/ fIO+60 ns thi -60 4) 4) CAN (Fig. 3-3) tsrx rx-strobe Time CAN rx 0 10 4) ns reference is XTAL1 rising edge tdtx tx-drive Time CAN tx 15 60 4) ns reference is XTAL1 falling edge @Cl=30pF, Port FAST mode DIGITbus (Fig. 3-4) tbtj Bit Time jitter DIGITOUT tfed Falling edge delay DIGITOUT 15 5) 10 4) ns rising edges, internal clock master tBIT/64 +60 4) ns reference is nominal falling edge 2 ) Value may be exceeded with unusual Hardware Option setting 3 ) Design value only, the actually observable hysteresis may be lower due to system activity and related supply noise 32 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Clock Supervision CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 4 ) When ERM is active, this time value is increased by 7.5ns with WEAK ERM setting, by 12.5ns with NORMAL ERM setting and by 20ns with STRONG ERM setting. 5 ) When ERM is active, this time value is decreased by 7.5ns with WEAK ERM setting, by 12.5ns with NORMAL ERM setting and by 20ns with STRONG ERM setting. SPI-CLK-OUT tsoci thoci SPI-D-OUT SPI-D-IN Fig. 3-1: SPI: Send and Receive Data with Internal Clock. Timing is valid for inverted clock too (Data valid at positive edge). SPI-CLK-IN thi All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. tsi SPI-D-IN SPI-CLK-IN tsoce thoce SPI-D-OUT Fig. 3-2: SPI: Send and Receive Data with External Clock. Timing is valid for inverted clock too (Data valid at positive edge). tcyc XTAL1 tdtx tsrx TX RX Fig. 3-3: CAN I/O Timing. Micronas 33 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 tBIT DIGIT-IN DIGIT-OUT tfed tbtj tbtj nominal pulse tNPL tNPL: Nominal programmed Pulse Length. Depends on programmed phase, Baudrate and transmitted sign (0, 1, T). Should be 1/4 for sign 0, 1/2 for sign 1 and 3/4 for sign T of tBIT. Fig. 3-4: DIGITbus I/O Timing Table 3-4: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.75V<HVDDn<5.25V, 3V<EVDDn<5.5V, TCASE=-40 to +85C, external components according to Fig. 2-3 Symbol Parameter Min. fP Parallel Resonance Frequency @ CL=12pF 4 R1 Series Resonance Res. for 50ms Oscillation Start-Up Time @CL=12pF @ fP=4MHZ Typ. @ fP=5MHz CEXT 34 External Oscillation Capacitances, connected to VSS 18 Max. Unit 5 MHz 340 380 210 270 240 280 140 180 Ohm Test Conditions START-UP START-UP, 4.5V<UVDD<5.5V RUN RUN, 4.5V<UVDD<5.5V START-UP START-UP, 4.5V<UVDD<5.5V RUN RUN, 4.5V<UVDD<5.5V pF Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 3.4. Recommended Quartz Crystal Characteristics CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 4. CPU and Clock System 4.1. ARM7TDMI CPU The CPU is an ARM7TDMI 32-bit RISC processor. This is a member of the Advanced RISC Machines (ARM) family. The ARM7TDMI is a 3 stage pipeline machine and supports a 4 Gbit address range. Besides the 32bit standard ARM instruction set the ARM7TDMI supports the 16bit Thumb instruction set which allows a higher code density. It includes a 64bit result multiplier and a JTAG interface with an embedded debug module. 4.1.1. CPU States The ARM7TDMI CPU allows operation in two states: - ARM state: 32bit instructions - Thumb state: 16bit instructions After reset and exceptions, ARM state is active. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 4.2. CPU Modes The CPU can be operated in four different clock modes (Table 4-2). Core modules that are also affected by CPU speed modes are: 1. Interrupt Controller with all internal and external interrupts 2. RAM, ROM/Flash and DMA Activating the PLL modes is done in FAST mode by the following routine: 1. For initialization, choose a pair of settings for the clock multiplication factor and the clock prescaler from Tables 4-5 or 4-6 and write them to PLLC.PMF and IOC.IOP. 3. Watchdog 2. Wait for at least 100s or PLLC.LCK to be set, to make sure that the PLL has locked. Table 4-1 shows the operability of the peripheral modules in the various clock modes. 3. Enable PLL mode by writing 0x03, or PLL2 mode by writing 0x07 to SR1.CPUM. 4.2.1. FAST Mode 4. As the System Frequency Divider and the Prescaler need some time to synchronize, the PLL mode is not active until PLLC.PLLM reads as 1. After reset the CPU is in FAST mode. The CPU clock and the I/O clock both equal the oscillator frequency fXTAL. Internal clock frequencies higher than fXTAL are not available in this mode. Modules requiring f0 = 2fXTAL for operation will not work properly, as f0 is set to f1 = fXTAL. Returning CPU from any other mode to FAST mode is done by selecting the appropriate mode in the standby registers field SR1.CPUM (Table 4-2). 4.2.2. PLL Modes To increase CPU performance, a PLL allows to multiply fXTAL. The CPU will operate at this higher frequency fSYS and its speed is automatically reduced only for accesses to slower modules (ROM/Flash, I/O). Table 4-5 gives recommended settings for control registers and the various resulting operating frequencies for the PLL mode. These recommended settings achieve f0 = 2*fXTAL, f1 = fXTAL and so forth, for unlimited operation of peripheral modules. A PLL2 mode allows bypassing of the first stage of the divider chain. It allows a clock system with fSYS = n*fXTAL and f0 = f1 = fXTAL for special applications, where the unlimited operation of peripheral circuits has to be sacrificed (see Table 4-6 for settings). In both PLL modes, the EMI Reduction Module (ERM) can be operated, which reduces electromagnetic energy emission (see Section 4.4. on page 39). Micronas 5. At this point the ERM may be activated (see Section 4.4.3. on page 39). Returning to FAST mode is done by the following routine: 1. Deactivate the ERM, if active (see Section 4.4.4. on page 39). 2. Return to FAST mode by setting SR1.CPUM to 0x01. 3. Wait for PLLC.PLLM to read as 0. 4. Now the program may resume. Attention: The PLL modes must be entered and left only via FAST mode. The registers PLLC.PMF and IOC.IOP may only be changed in FAST mode. To reduce the power consumption in other modes than PLL modes, the registers PLLC.PMF and IOC.IOP should be programmed to zero. 4.2.3. SLOW Mode To considerably reduce power consumption, the user can reduce the internal CPU clock frequency to 1/128 of the normal fXTAL value. In this CPU SLOW mode, program execution is reduced to 1/128 of fXTAL. Some modules must not be operated during CPU SLOW mode (e.g. CAN). Refer to module sections for details (see Table 4-1 on page 36). 35 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 4-1: CPU clock modes and their effect on peripheral modules Module PLL PLL2 FAST SLOW DEEP SLOW Digital Watchdog IRQ Interrupt Controller Unit FIQ Interrupt Logic Port Interrupts A/D Converter 1) 1) 1) ALARM, P06 and WAIT Comparators LCD Module 1) 1) 1) 3) DMA DMA Timer, GBus 1) 1) 1) 3) UART 1) 1) 1) SPI 1) 1) 1) CAN 1) 1) 1) 4) DIGITbus 1) 1) 1) 4) I2C Ports Stepper Motor Module 1) 1) PWM, PFM 1) 1) Audio Module 1) 1) Clock Outputs 1) 1) 1) Capture Compare Module 1) 1) 2) Timers 1) 1) 1) 3) JTAG Embedded Trace Module Core Analog 3) 4) Input & Output 1) 3) Timers & Counters Miscellaneous 1) Possibly affected by f0 equaling f1 2) Avoid write access to CCxI 3) Only clocks f5 and slower are available from Clock Divider 4) Don't access registers or CAN RAM 36 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Communication CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Internal clock frequencies higher than fXTAL are not available in this mode. Modules requiring f0 = 2*fXTAL for operation will not work properly, as f0 is set to f1 = fXTAL. 4.2.4. DEEP SLOW Mode For switching between SLOW and FAST modes, use the following routine: To further reduce power consumption beyond SLOW mode, DEEP SLOW mode also disables most of the internal peripheral clocking system. Table 4-1 shows which peripheral modules can be operated in DEEP SLOW mode. 1. Select the desired mode in the standby registers field CPUM (Table 4-2). The new fBUS is effective after 2 fXTAL cycles at most. Only peripheral module clocks f5 and slower are available from the divider chain. T0 can be operated only with this limitation. 2. Now the program may resume. For switching between DEEP SLOW and FAST modes, use the routine given for SLOW mode. The IC contains a quartz oscillator circuit that only requires external connection of a quartz and of 2 oscillation capacitors. Its start-up and run properties are controllable by SW. See section "Core Logic" for details. fXTAL = 4/5MHz The oscillator clock fXTAL drives a clock system that supplies the various modules with its specific clock. PLLC.PMF PLL xn ERMC.LCK pll_lock ERMC.EOM ERM ERMC.INPH A frequency multiplying PLL allows to select the system clock fSYS to be higher than fXTAL for high speed CPU and module operation. A divider chain divides fIO down to supply peripheral module clocks f0 to f17. Module clock selection is software defined in some cases, hardware or HW option defined in other cases. The module descriptions give details. n fXTAL SR1.CPUM=3, 7 SR1.CPUM=0, 2 1/128 The standby register field SR1.CPUM selects the CPU mode (Table 4-2). fSYS CPU ICU DMA Mem. Ctrl. nWAIT Table 4-2: Clock Selection 1 waitq SR1.CPUM CPU Mode fBUS fIO f0 f1 0 0 0 SLO W fXTAL/ 128 fXTAL/ 128 fXTAL fXTAL 0 0 1 FAST fXTAL fXTAL fXTAL fXTAL IOC.IOP n/m fXTAL 1/m SR1.CPUM=3, 7 0 1 0 DEEP SLO W fXTAL/ 128 fXTAL/ 128 f0 to f4 = 0 0 1 1 PLL n fXTAL n/m fXTAL n/m fXTAL 1 1 0 1 x 0 Don't use 1 1 1 PLL2 fBUS ROM Flash RAM & SR1.CPUM=0, 2 stpclk & fIO I/O Bus fSUP f0perm n/2m fXTAL 1/2 VDD SR1.CPUM=2 f0 SR1.CPUM=3 f1 n fXTAL n/m fXTAL n/m fXTAL n/m fXTAL Divider Chain All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 4.3. Clock System f2 f3 f4 f17 Fig. 4-1: Clock System Micronas 37 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 4.3.1. PLL The phase-locked state of the PLL is signaled by a lock signal. It is available as flag PLLC.LCK. It may be routed to the LCK special output by selection in field ANAU.LS (UVDD Analog Section). The block multiplies fXTAL by n = PMF+1 to achieve fSYS. PLL Control register PLLC allows to set the desired value. fXTAL Phase Comp. fREF VP ~ f(XTAL - REF) VP PMF = 0 VCO n fXTAL 1/(PMF+1) PMF = 1..15 Fig. 4-2: PLL Block Diagram CO0SEL.CO00, CO0SEL.CO01 HW Option 2 HW Option CO0Mux0 CO0Mux1 CO0Mux2 fXTAL 4:1 Mux 1/1 1/1.5 1/2.5 1 CO0Q CO0 CO0 Interrupt Source HW Option Clock Out 1/1 1/1.5 1/2.5 CO1 CO1 Interrupt Source Fig. 4-3: Clock Outputs Diagram Signal CO0 is the output of a prescaler and a 4 to 1 multiplexer. Prescaler and input for the multiplexer are selectable by HW options (see Table 4-3). The output selection of the multiplexer is done by register CO0SEL, bits CO01 and CO00. The outputs of the pre scalers are fed not only to the ports, but may also serve as interrupt source. The U-Ports assigned to function as clock outputs (see Table 4-3) have to be configured Special Out. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. 4.3.2. I/O Clock Prescaler CO0 and CO1 are not affected by CPU SLOW mode. This prescaler derives the clock for the peripheral modules (the I/O clock fIO) from the system clock fSYS. It divides fSYS by an integer number m. I/O Clock Control register IOC allows to set the desired value. m is recommended to be set equal to n/2. Table 4-3: HW Options and Ports 4.3.3. Divider Chain and Clock Outputs CO0 and CO1 Signal CO0 Section "HW Options" gives details about HW option controlled clocks, their selection and their activation. Initialization Item Address Item Setting CO0 Prescaler CO00C CO0 output U1.6, U3.3 or U7.7 special out CO0Q output U1.5 special out 1) CO1 output U0.4, U1.5 or U7.6 special out1) CO0Mux0 The peripheral module divider chain receives fSYS/m and supplies the various modules with their specific clocks. Each stage of the divider chain divides its input clock by two. Thus only powers of two of the divider chain input clock are obtainable for the peripheral modules. Table 4-2 shows the effect of CPU mode selection on the divider output frequencies f0 through f17. Note that in modes FAST, PLL and SLOW, with n = 2m (which is recommended), f1 always equals fXTAL. Thus f1 and all further subdivided clocks are unaffected by switching between these modes. HW Options CO1 CO0Mux1 CO01C CO0Mux2 CO02C CO1 Prescaler CO1C Clock Out 1) HW Options register flag PM.U15 switches between CO0Q and CO1 at U1.5 special out. Note that specifying 1/1.5 and 1/2.5 prescaled clocks result in clock signals with 33% resp. 20% duty factor. Two Clock Output signals CO0 and CO1 provide external visibility of internal clocks (Figure 4-3). Clocks are selected by register CO0SEL. 38 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The PLL is composed of a Phase Comparator, a Voltage Controlled Oscillator VCO, a Frequency Divider and an internal bypass. The Phase Comparator compares the input frequency fXTAL with the output frequency of the Frequency Divider, fREF. It outputs the voltage VP, which is proportional to the phase difference of the two input frequencies. VP controls the VCO which outputs the desired frequency. This frequency is fed back by the Frequency Divider to the Phase Comparator. The Frequency Divider divides the input frequency down to fREF which ideally is the same as fXTAL. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 4.4. EMI Reduction Module (ERM) The IC contains an EMI Reduction Module (ERM), which is capable of reducing electromagnetic radiation that might cause interference to other electronic equipment. The concept of this circuit uses precisely defined time offsets of the master clock phases as generated by the PLL. Thus, the module is only available in PLL modes. Each fSYS multiplier n and each mode requires its own set of parameters. For individual settings other than those given in Table 4-5 the rules are given below. For mode 1 the limits are: All internal clock signals except fXTAL are affected. Thus also the sampling time points of clocked inputs and outputs of all internal modules are modulated. To avoid a possible performance degradation of, e.g., communication modules in a user environment, the maximum possible delay of the sampling clock phase can be controlled with the parameters given in table 4-5. In critical applications, I/O sampling time point modulation and EMI reduction can thus be compromised. Section 4.7.gives application hints. - The suppression strength has no effect and should be kept at 0. Features - The clock tolerance must be equal to or less than (suppression strength +1)/2. - Strong suppression of electromagnetic radiation - Precisely controlled effect on sampling time points of clocked I/O (ADC, CAN, UART, SPI etc.) All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 4.4.2. Rules for Setting Parameters - All parameters fully controllable and reproducible - Three operation modes for different purposes - Works for clock frequencies of up to 48 MHz - The clock tolerance must not exceed the values given in the columns for strong settings. For modes 2 and 3 the limits are: - Numbers must not exceed the values given in the columns for strong settings. - In mode 2 the suppression strength must not exceed 43. - In mode 3 the sum of clock tolerance and suppression strength must not exceed 43. 4.4.3. Initialization - No degradation of CPU performance For operation of the ERM, the clock system has to be in one of the PLL modes. After Reset, the ERM is in mode 0. All internal registers are reset to their default values. 4.4.1. Modes The initialization must be done in the following order: The ERM has 4 modes of operation: 1. Set the clock tolerance (ERMC.TOL) to 1. - Mode 0, ERM off. 2. Set the suppression strength (ERMC.SUP) to 1 (modes 2 and 3 only). - Mode 1 is intended for the low fSYS frequencies of 8 MHz or 10 MHz with a clock multiplier of n = 2 (PLLC.PMF = 1). Mode 1 with a clock tolerance of 7 has a similar harmonics suppression as the formerly used EMI Reduction Module V3.1. - Mode 2. This mode is primarily intended for the deactivation process of mode 3 but may also be used for operation. It performs best at high clock frequencies. - Mode 3 gives best results at medium and high fSYS frequencies. At medium frequencies it is even capable of a certain suppression of the fundamental. In each of the three operation modes the parameters may be particularly chosen with the help of registers ERMC.SUP and ERMC.TOL, to achieve an optimum suppression while keeping phase modulation of fIO as low as possible. In Table 4-5, three sets of parameters with maximum fIO sampling delays of: - 7.5 ns (weak), - 12.5 ns (normal) and - 20 ns (strong) 3. Select the desired mode (1...3) in ERMC.EOM according to Table 4-5. 4. Select the desired suppression strength (ERMC.SUP). 5. Select the desired clock tolerance (ERMC.TOL). 4.4.4. Deactivation To deactivate the ERM, the following sequence must be observed: 1. If in mode 3, enter mode 2 by writing 2 to field ERMC.EOM. 2. Set the clock tolerance parameter (ERMC.TOL) to 1 (steps 1. and 2. may be done in one operation). 3. Set the suppression strength (ERMC.SUP) to 1 (modes 2 and 3 only). 4. Wait at least 8 fSYS cycles (e.g. CPU NOPs) before checking the In-Phase flag ERMC.INPH. 5. Wait for flag ERMC.INPH to be set (may take up to 80 fSYS cycles), then clear the field ERMC.EOM to return to mode 0 This will turn off the ERM. are given as examples. However, other individual settings are possible (see section 4.4.2.). At fSYS frequencies of 40 MHz and above only a limited EMI suppression is possible. At an fSYS of 50 MHz the ERM must be switched off (mode 0). Micronas 39 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The Memory Controller connects the CPU to the complex memory system. It controls the various types of access and wait states. for access to asynchronous memory are programmed. The access to the synchronous memory (I/O) works right after reset, independent from any setting by software. Endian mode is set by the Control Word via bit CR.ENDIAN. Features First, initialize the wait state register WSR (cf. Table 4-5). Then the PLL or PLL2 mode may be enabled, if desired. Don't change the wait state register while in PLL mode, this may lead to a memory access with undetermined wait state count in the following cycle. - support of one synchronous- and up to three different asynchronous memory areas - different wait state values for sequential and nonsequential accesses to asynchronous memory - allows 8, 16 and 32bit memory accesses from CPU 4.5.1.3. Operation - supports access to 8, 16 and 32bit wide memory With proper SW initialization, the Memory Controller is also ready to access the asynchronous memory systems (ROM/ Flash, RAM, Boot ROM). - allows big or little endianness. SWS NWS WSR Mux WS Counter In presence of a Patch Module, the PATCHACC signal from the Patch Module signals to the MMU that the next access will be an access to the Patch Module instead to normal ROM/Flash, RAM or Boot ROM. Memory Controller The DMAACC signal from the DMA Module signals, that the next address value will be driven by DMA and not by CPU. Due to the fact that DMA always reads a location in ROM/ Flash, RAM or Boot ROM and writes to a location in the I/O area within the same bus cycle, the MMU also preselects the I/O area and the Memory Controller times the whole DMA cycle to the restrictions of the slow synchronous I/O area. fSYS fIO Addr CR.MAP SR1.CPUM=3, 7 PATCHACC ICUACC DMAACC CR.ENDIAN CR.PSA The MMU decides from the address and the CR setting, which area in memory space contains a 8, 16 or 32bit memory system. It preselects the different types of memory (ROM/Flash, RAM, Boot ROM and I/O-Pages) and computes the address for ROM/Flash minus 200000hex, if ROM/ Flash should be mapped to base address 200000hex. predecrom predecram predecboot predecio waitq 4.5.1.4. Inactivation Returning the Memory Controller to CPU FAST mode (SR1.CPUM=1) will immediately switch the CPU to FAST mode and change any further access to asynchronous memory to non-wait-state operation. Bridge I/O Bridge ROM Boot Bridge Emu Flash CPU Bus Fig. 4-4: Memory Controller Block Diagram 4.5.1. Principle of Operation 4.5.1.1. General The Memory Controller contains a Memory Mapping Unit (MMU) to control the mapping of the whole memory system, a Wait State Register (WSR) to initialize the various wait states, a Final State Machine and a Wait State Counter to control the various types of access and wait states. 4.5.1.2. Initialization After reset, the CPU runs in CPU FAST mode, the Wait State Counter is disabled due to SR1.CPUM=1 and no wait states 40 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 4.5. Memory Controller CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 4.6. Registers PLLC r/w PLL Control 7 6 5 4 ACT LCK PLLM x x x x x 3 2 1 0 PMF 0 0 w 0 0 Res PLL Active PLL started (PMF > 0) PLL not activated (PMF = 0) LCK r1: r0: PLL Locked PLL locked PLL not locked PLLM r1: r0: PLL Mode Acknowledge The clock chain has switched to PLL mode Not PLL mode f SYS = n f XTAL = ( PMF + 1 ) f XTAL 5 4 r/w x r/w r/w 3 2 1 x EOM INPH x x x x 3 x x x x TOL SUP 0x00000000 TSEL r/w Test Select Factory use only. EOM r/w3: r/w2: r/w1: r/w0: ERM Operation Mode Mode 3 Mode 2 Mode 1 Off TOL r/w15-0: Clock Tolerance (see Table 4-5 and 4-6) INPH r1: r0: In Phase (during deactivation) Phase is 0 or 1 Phase > 1 SUP r/w63-0 Suppression Strength (see Table 4-5 and 4-6) Micronas 3 x x x x x x x x x x 2 1 0 IOP 0 0 0 Res I/O Clock Prescaler (Table 4-5) IOP is a write only field. WSR Wait State Register 7 6 w 5 4 3 2 NWS 1 0 SWS 0x00 Res NWS w: Nonsequential Wait State Bits Number of wait states at nonsequential memory access. SWS w: Sequential Wait State Bits Number of wait states at sequential access. 0 TSEL r/w 4 CO0SEL ERM Control 6 5 The WSR influences access to ROM, Flash and Boot ROM. Above formula relates to PLL mode. 7 6 Above formula relates to PLL mode. PMF is a write only field. Don't modify PMF in PLL mode. ERMC 7 f SYS f SYS PMF + 1 f 0 = --------- = ------------------ = --------------------- f XTAL IOP + 1 m IOP + 1 PLL Multiplication Factor (Table 4-5) PLL is switched off and internally bypassed. This is the standby mode for the PLL. Starts PLL with the corresponding frequency. If not active anyway, the VREFINT Generator and BVDD Regulator are enabled w15-1: I/O Control IOP w ACT r1: r0: PMF w0: All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. IOC x w 2 1 0 Res Clock Out 0 Selection 7 6 5 4 3 2 1 0 x x x x x x CO01 CO00 x x x x x x 0 0 Res CO00, CO01 Clock Out Bit 0 and 1 w: Clock selection Table 4-4: CO00 and CO01 Usage CO01 CO00 Selection 0 0 CO0Mux0 0 1 CO0Mux1 1 0 CO0Mux2 1 1 fXTAL 41 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 4.6.1. Recommended Settings It is required not to operate I/O faster than Flash. Tables 4-5 and 4-6 list settings available for the EMU device. When emulating a specific target device (MCM or mask ROM), use the Recommended Settings of that device only. Settings differing from these two lists shall not be used and may result in undefined behaviour. Suppression Strength (SUP) and Clock Tolerance (TOL) may be varied between zero and the values for strong settings according to the rules in Section 4.4.2. The given limits must not be exceeded Table 4-5: PLL and ERM Modes: Recommended Settings and Resulting Operating Frequencies (MHz) SUP TOL Strong TOL Normal SUP TOL TOL Weak PLLC. PMF fBUS WSR fIO= f0 IOC. IOP 8 1 8 0x00 8 0 0 4 0 7 0 11 4 2 7 4 11 6 16 3 16 0x00 1 0 8 0 14 0 15 8 4 14 7 22 11 8 0x11 0 8 0 14 0 15 8 4 14 7 22 11 24 0x00 0 2 0 2 0 2 12 1 21 1 33 1 12 0x11 0 12 0 15 0 15 12 6 21 11 31 12 8 0x22 0 12 0 15 0 15 12 6 21 11 31 12 16 0x11 0 12 0 12 0 12 16 8 28 12 31 12 10.7 0x22 0 12 0 12 0 12 16 8 28 12 31 12 20 0x11 0 6 0 6 0 6 21 6 35 6 37 6 13.3 0x22 0 6 0 6 0 6 21 6 35 6 37 6 10 0x33 0 6 0 6 0 6 21 6 35 6 37 6 24 0x11 0 1 0 1 0 1 25 1 42 1 42 1 16 0x22 0 1 0 1 0 1 25 1 42 1 42 1 12 0x33 0 1 0 1 0 1 25 1 42 1 42 1 0 0 5 0 8 0 14 5 3 8 4 14 7 1 0 10 0 13 0 13 10 5 17 6 28 6 0 10 0 15 0 15 10 5 17 9 28 12 0 14 0 14 0 14 15 8 26 12 31 12 0 14 0 14 0 14 15 8 26 12 31 12 0 6 0 6 0 6 21 6 35 6 37 6 32 40 48 5 7 9 11 2 3 4 5 10 1 10 0x00 20 3 20 0x00 10 0x11 15 0x11 10 0x22 20 0x11 13.3 0x22 0 6 0 6 0 6 21 6 35 6 37 6 10 0x33 0 6 0 6 0 6 21 6 35 6 37 6 25 0x11 16.7 0x22 12.5 0x33 30 40 50 42 Strong fSYS 24 5 Normal 5 7 9 10 2 3 4 set ERMC.EOM=0 set ERMC.EOM=0 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 4 SUP Weak ERMC.EOM = 2 or 3 SUP ERMC.EOM = 1 TOL I/O SUP Program Storage TOL CPU SUP fXTAL CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 4-6: PLL2 and ERM Modes: Settings Sacrificing Unlimited Operation of Peripheral Modules and Resulting Operating Frequencies (MHz) 4 5 12 2 6 0x11 4 2 12 0x00 20 4 10 0x11 15 2 7.5 0x11 5 Strong TOL IOC. IOP Normal SUP fIO= f0 Weak TOL WSR Strong SUP fBUS Normal TOL PLLC. PMF TOL fSYS SUP Weak ERMC.EOM = 2 or 3 SUP ERMC.EOM = 1 TOL I/O SUP Flash TOL CPU SUP fXTAL 0 6 0 10 0 15 6 3 10 5 16 8 0 5 0 5 0 5 6 2 10 2 16 2 4 0 10 0 15 0 15 10 5 17 8 28 8 2 0 7 0 13 0 15 7 4 13 7 21 11 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 4.7. PLL/ERM Application Notes 4.7.1. PLL Jitter The embedded PLL synchronizes every n-th fSYS cycle to the externally applied fXTAL signal. This synchronization smoothly tries to cancel out influences from power supply noise and fXTAL fluctuations. Depending on the application, this permanent re-synchronization process is expected to introduce some nanoseconds of phase jitter to fIO. It is important to note that PLL jitter does not introduce a noticeable frequency error, because the phase stays locked to the fXTAL reference and fluctuates, even over long times, only within the same tight limits. Even with a PLL induced fIO jitter of 10ns, the maximum observable frequency error between two fIO clocks - spaced 1us apart is (1us210ns)/1us=2%, - spaced 1ms apart is (1ms210ns)/1ms=20ppm, - spaced 1s apart is (1s210ns)/1s=0.02ppm, and so forth. 4.7.2. ERM "Jitter" The effect of the ERM on fIO phase and frequency is similar to that of PLL jitter in that it adds limited phase modulation. However, this ERM induced jitter is especially tailored to improve the electromagnetic emission properties of the device. Section 4.4.1. gives details on setting the maximum phase delay: - 7.5ns (weak) translates to 3.75ns of fIO jitter, - 12.5ns (normal) translates to 6.25ns of fIO jitter, - 20ns (strong) translates to 10ns of fIO jitter. From these figures it is evident, that ERM introduces a jitter that, in its extent, is comparable to PLL jitter. Both influences may be added to estimate the combined PLL/ERM effect on I/O module operation. 4.7.3. Influence of PLL/ERM on Module Operation DIGITbus, SPI and I2C synchronize external devices to one master clock. Their operation is hardly impeded by PLL/ERM jitter. Modules like UART and CAN communicate with external fixed-frequency devices, and there is a maximum frequency Micronas offset between transmitting and receiving station, that can be tolerated without transmission error. Viewed from the receiving station, a frequency offset of the transmitting station is tolerable, as long as over the length of a complete telegram, every bit can still be detected unambiguously. Once the tolerable frequency offset is exceeded, communication is fatally disturbed. This tolerable offset is dependent on the capability of the involved circuitry to detect and compensate for frequency offset. In the further discussion, the clock tolerance TOL is defined as percentage offset of the actual from the nominal frequency f act - f nom TOL = -------------------------f nom Note that each transmitting and receiving station are allowed this same tolerance from nominal: ftrans=fnomTOL and frec=fnomTOL The resulting maximum offset between transmitter and receiver thus is 2 x TOL. 4.7.3.1. UART Let's consider the tolerable frequency offset in the case of the UART. The Baud Rate frequency is always the sample clock frequency, divided by 8. The max. telegram length is 12 bit. A transmitter frequency offset is tolerable as long as 12*8 3 receiver sample clocks equal 12*8 transmitter sample clocks, which gives a transmitter frequency of fTrans=fRec(12*8/(12*83))=fRec3.23% and TOL=1.61%. PLL and ERM jitter claim a certain portion of this tolerable offset. Let's assume that both influences add up to 20ns of fIO jitter, and that fIO=f0=8MHz. With the Baud rate set to 1MBaud, fSAMPLE equals 8MHz. With this setting, PLL and ERM jitter consume 2*20ns/375ns=10.7% of the tolerable transmitter frequency offset and reduce TOL to 1.44%. 43 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 4.7.3.2. CAN The CAN Module contains logic that re-synchronizes a receiver to a transmitter several times during a telegram. By these means, a receiver is able to adapt to the transmitter frequency within narrow limits. Two situations have to be distinguished: 1. Bit stuffing guarantees a maximum of 10 bit periods between two consecutive re-synchronization edges. Therefore the accumulated phase error must be less than the programmed re-synchronization jump width (SJW). The limitation that this situation imposes on the maximum TOL can be expressed as: t SJW 2 x TOL ------------------10 x t Bit Example (f0 = 8MHz) With the Baud rate set to 1MBd, tBit equals 1s and is divided into 8 time quants (tQ = 125ns). tSJW and tTSEG2 are programmed to 2 tQ (= tPhase Seg1 = tPhase Seg2). 3 tQ are reserved for the propagation delay segment. In the first case the maximum tolerance TOL is 1.25% (edge to edge): 2 TOL ------------------------ = 0.0125 2 x 10 x 8 In the second case, TOL is 0.98% (edge to sample point): 2 TOL -------------------------------------- = 0.0098 2 x ( 13 x 8 - 2 ) The smaller value of the above (0.98%) is relevant. Following the UART example, PLL/ERM jitter consumes up to 2*20ns of 250ns (SJW = 2 time quants). This gives 40ns/ 250ns=16% of this tolerance, thus reducing TOL to 0.82%. With the Baud rate set to 500kBd, tBit=2s and tQ=250ns. The maximum tolerance TOL of 0.98% reduces by 2*20ns/ 500ns=8.0% to 0.9%. or t SJW TOL ----------------------------2 x 10 x t Bit 2. Another limit on the maximum TOL is set by the situation where the CAN logic must be able to correctly sample the first bit after an error frame. This is the 13th bit after the last re-synchronization. This limitation can be expressed as: min ( t Phase Seg1, t Phase Seg2 ) 2 x TOL ---------------------------------------------------------------13 x t Bit - t Phase Seg2 or min ( t Phase Seg1, t Phase Seg2 ) TOL ---------------------------------------------------------------2 x ( 13 x t Bit - t Phase Seg2 ) Example (f0 = 10MHz) With the Baud rate set to 1MBd, tBit equals 1s and is divided into 10 time quants (tQ = 100ns). tSJW and tTSEG2 are programmed to 3 tQ (= tPhase Seg1 = tPhase Seg2). 3 tQ are reserved for the propagation delay segment. In the first case the maximum tolerance TOL is 1.5% (edge to edge): 3 TOL --------------------------- = 0.015 2 x 10 x 10 In the second case, TOL is 1.2% (edge to sample point): 3 TOL ----------------------------------------- = 0.012 2 x ( 13 x 10 - 3 ) 4.7.3.3. DIGITbus The DIGITbus master synchronizes with external devices via the serial data line. The slave node recovers the transmission clock from the data signal via an own PLL. This PLL will lock to the long-term average frequency of the master, and the slave node sees PLL/ERM jitter as a short-term frequency offset. Following the UART example, one can define the tolerable frequency offset: Every bit starts with a rising edge and thus every bit has a resynchronization point. The bit period (tBit) is divided into four equal length parts. Falling edges happen nominally after 1/4, 2/4 or 3/4 of the bit period. After 4/4 of the bit period a rising edge indicates the beginning of the next bit. The DIGITbus logic tolerates a jitter of these edges up to 1/8 of the bit period. Thus, a transmitter frequency offset is tolerable up to fTrans = fRec(11/8) = fRec12.5% and TOL = 6.25%. Again following the UART example, ERM/PLL jitter influences this tolerable offset: With the Baud rate set to 31.25kBd, 1/8 of the bit period is 4s. PLL/ERM jitter reduces the maximum tolerance TOL of 6.25% by 2*20ns/4s=1% to 6.19%. 4.7.3.4. SPI and I2C Modules like SPI and I2C synchronize with external devices by the serial clock. Thus, no frequency offset between transmitting and receiving station can develop, and no adverse effects of PLL/ERM operation are expected. The smaller value of the above (1.2%) is relevant. Following the UART example, PLL/ERM jitter consumes up to 2*20ns of 300ns (SJW = 3 time quants). This makes 40ns/ 300ns=13.3% of this tolerance, thus reducing TOL to 1.04%. With the Baud rate set to 500kBd, tBit=2s and tQ=200ns. The maximum tolerance TOL of 1.2% reduces by 2*20ns/ 600ns=6.7% to 1.12%. 44 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. With the Baud Rate set to 19.23kBaud, fSAMPLE equals 153.84kHz. With this setting, PLL and ERM jitter consume 2*20ns/19.5us=0.2% of the tolerable transmitter frequency offset and reduce TOL only slightly to 1.605%. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION address range (16M) F0.0000 E0.0000 Micronas CR.MAP = 00 .5M .5M 2M CDC32xxG-B V3.0 3 DEC 01 5. Memory and Boot System RESETQ = 1 CR.MAP = 01 ROM/Flash 0 CR.MAP = 1x F8.0000 rsvd debug 2M I/O I/O I/O Boot Boot Boot RAM RAM RAM ROM/Flash Boot TEST2-Pin = 0 RESETQ = 0 00FF.FFFF TEST2-Pin = 1 C0.0000 A0.0000 8M ROM/Flash 20.0000 ROM/Flash RAM Boot Fig. 5-1: Address Map. Most Common Settings 45 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 On-chip RAM is composed of static RAM cells. It is protected against disturbances during reset as long as the specified operating voltages are available. The 128PQFP Multi Chip Module also contains a 512K byte Flash EEPROM of the AMD Am29LV400BT type (top boot configuration). This device exhibits electrical byte program and sector erase functions. Refer to the AMD data sheet for details. Future mask ROM derivatives may be specified to contain less or more internal RAM and ROM than this IC: - ROM will grow upward from 0x0200000 to 0x09FFFFF (8MByte) and can be remapped to physical address 0 (growing upward to 0x07FFFFF). It is 16bit wide and is asynchronously accessed with wait states. - RAM will always grow upward from physical address 0x0C00000to 0x0DFFFFF (2MByte) and can be mirrored to physical address 0. It is 32bit wide and is asynchronously accessed without wait states. - Boot ROM will grow upward from physical address 0x0F00000 to 0x0F7FFFF (0.5MByte) and can be mir- rored to physical address 0. The I/O area will grow upward from physical address 0x0F80000 to 0x0FFFFFF (0.5MByte). It is 16bit wide and is asynchronously accessed with wait states. Mirrored means the memory is accessible at both locations. Remapped means the memory is accessible at the new location only. All parts (ROM, Flash and Emu) contain at least the I/O, the RAM and the Boot ROM. 5.1.1. Reserved Addresses Reserved Addresses are memory locations which define the behavior of internal HW or external systems. In our system the memory locations at address 0 and following have dedicated functions. The function of these memory locations depend on which kind of physical memory is mapped to these locations. As you can see at table 5-1 ROM/Flash or Boot ROM has to be mapped to location 0 at reset. Otherwise Control Word can not define the HW behavior and no ingenious instruction is available at the reset start address. As long as RAM is mirrored to location 0 addresses 20 and following have no influence on the internal HW. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 5.1. RAM and ROM Table 5-1: Reserved Addresses Addresses Size [byte] Usage if mapped/mirrored to 0 RAM ROM/Flash General purpose RAM. No HW defined action. HW Options 030 - 5F 48 02C - 2F 4 Factory ID 02A - 2B 2 reserved 028 - 29 2 ROM ID 024 - 27 4 Security Vector 020 - 23 4 Control word 01C - 1F 4 FIQ (Fast Interrupt) 018 - 1B 4 IRQ (Interrupt) 014 - 17 4 Reserved 010 - 13 4 Data Abort 00C - 0F 4 Prefetch Abort 008 - 0B 4 SWI (Software Interrupt) 004 - 07 4 Undefined instruction 000 - 03 4 Reset 5.1.1.1. HW Options Please refer to section "Hardware Options" for information about layout of the HW Options field and the corresponding Registers in the I/O area. To activate the HW Options related functions, the SW has to copy them to the corresponding locations in the I/O area. 46 Boot ROM ARM ID But nevertheless this are HW Options. It is not intended to modify them by SW in ROM parts. In this case the result is unpredictable. Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 5.1.1.2. ROM ID The ROM ID serves as identification of the corresponding application/boot program. It will be read by an external system (test, debug) and doesn't influence internal HW. 1. Clear the Security Vector (0x00000000). 2. Clear the Flash ROM (Security Vector = 0xFFFFFFFF). The ROM ID contains a half-word sized hexadecimal value. The range is 0x0000 to 0xFFFF. 3. Program all of the Flash ROM without the Security Vector. 5.1.1.3. Factory ID 5. If ok, write 0x55AA55AA to the Security Vector. Otherwise go to step 2 again. The Factory ID contains a factory defined code. It contains information about the HW version, frequency, etc. It will be read by an external system (test, debug) and doesn't influence internal HW. The Boot system may use this information and adopt its behavior according to the Factory ID. The layout of the Factory ID is not yet defined TBD. 5.1.1.4. Security Vector All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The following sequence of actions has to be done in order to reprogram a Flash ROM: The main job of the Security Vector is to enable the JTAG interface via Boot ROM if the Flash ROM does not contain a correct application program (see Section 5.3. on page 48). The Boot ROM program can not enable the JTAG interface if the Security Vector contains the value 0x55AA55AA. This is the way the application program can disable JTAG access. An empty (not programmed) Flash ROM contains all ones. Hence the Security Vector contains a non valid pattern and the Boot ROM enables the JTAG interface. 4. Verify the Flash ROM. This proceeding guarantees that the JTAG interface will be enabled after reset via Boot ROM, if something goes wrong during Flash ROM programming. A correct application program should provide a different way and interface to enable JTAG and to modify the Security Vector. During developing and debugging the Security Vector can be written to a non valid value to allow easy JTAG access. 5.1.1.5. ARM ID The ARM core can contain a System Control Coprocessor (CP15) which contains among other things an ID Register. It allows the identification of the implemented processor. There is no CP15 implemented up to now, but the ARM ID field may contain the same information. 5.1.1.6. Control Word The Control Word defines the behavior of the HW during reset. Refer to section "Core Logic" for information about Control Word definition. 5.2. I/O Map The I/O region is divided into the lower part (addresses 00F80000 to 0x00FBFFFF) which is connected to the 8 bit wide bus and into the upper part (addresses 00FC0000 to 0x00FFFFFF) which is connected to the 32 bit wide bus. Please refer to section "Register Cross Reference Table" for detailed I/O register mapping. Access to I/O modules which are connected to the 8 bit wide bus is restricted: If not otherwise mentioned those modules must be accessed by byte access only. This memory area is organized in little endian format. If the CPU operates in big endian format, only byte access is recommended. Table 5-2: I/O Map Address Size Access What 190k 8bit, synchronous, wait states 2k Free 00F8FFFF 00F81200 59.5k Free 00F811FF 00F81000 512 00F80FFF 00F80000 4k 00FBFFFF 00F90800 00F907FF 00F90000 Registers Table 5-2: I/O Map Address Size Access What 256 32bit, asynchronous, no wait states 256 IRQ and FIQ registers 00FFFDFF 00FFFC00 512 Core registers 00FFFBFF 00FC0000 255k 00FFFFFF 00FFFF00 00FFFEFF 00FFFE00 Micronas CAN registers CAN-RAM DMA registers Free 47 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 5.3. Boot System The job of the Boot System is to enable the JTAG interface if necessary. Further actions as there are download, Flash ROM programming or debugging and monitoring has to be done via JTAG interface. If TEST2 pin is held high during reset, the Control Word from the Boot ROM is copied to the Control Register by HW. The Boot ROM Control Word is configured to start program execution from the Boot ROM, mirrored to location 0. The Boot ROM Control Word disables JTAG. 5.3.1. Principle of operation All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The Boot ROM is accessible at two locations, originally at address 0xF00000 and mirrored at address 0x0. The first instruction of the Boot ROM (Reset Vector) loads the address of the next instruction in the original Boot ROM (0xF00100, above the Boot ROM HW Options) into the program counter. This causes a jump from the mirrored Boot ROM to the original Boot ROM. The remaining part of the program is running in the original Boot ROM and remapping of the memory does not influence correct operation of the boot program. The program reads the TEST pin in order to distinguish between application and factory boot program. In case of the security vector is set in the application program, the application is started, otherwise the JTAG interface is enabled and program stays in an endless loop. In case of factory boot program a test program is started. The watchdog is not triggered in the Boot ROM program. Especially when the program is in the endless loop this may cause problems. But this endless loop will not be reached in ROM parts, where the watchdog may be HW enabled (option), as long as the security vector is valid. In Flash ROM parts the watchdog should not be HW enabled. boot() { Jump to 0xF00100; if(TEST pin low) { /* Custom boot */ if(security vector) { /* Application available */ Load Control Registers with application Control Word; Jump to location 0x0; } else { /* No application */ Enable JTAG; Endless loop; } } else /* TEST pin high */ { /* Factory boot */ Run test program; } } Fig. 5-2: Boot program 48 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 6. Core Logic 6.1. Control Word CW Some system configuration items are freely selectable during device start-up by means of a unique Control Word (CW). Table 6-2: CW fetch in EMU parts (CPGA257) Control Word Fetch desired from 6.1.1. Reset Active During Reset, the device fetches this CW from address locations 0x20 to 0x23 of a source that is determined by the state of pins TEST and TEST2, see Table 6-1 for MCM and ROM parts and Table 6-2 for EMU parts. Table 6-1: CW fetch in MCM and ROM parts (QFP128) All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Control Word Fetch desired from Necessary Reset config. of pins TEST2 TEST Internal ROM/Flash 0 0 External via Multi Function port 0 1 Internal Boot ROM 1 x Necessary Reset Config. of pins TEST2 TEST External via Emu port 0 0 External via Multi Function port 0 1 Internal Boot ROM 1 x 6.1.2. Reset Inactive When exiting Reset, the CW is loaded into the Control Register (CR) and the system will start up according to the configuration defined therein. Normally the CW is fetched from the same memory that the system will later start executing code from. Table 6-3 gives fix CWs for a list of the most commonly used configurations. For special purposes, the CW source and the program source may differ. For these purposes, a detailed description of the CW and CR function is given in the chapter "Control Register and Memory Interface". Table 6-3: Some common system configurations and the corresponding CW setting Part Type EMU Program Start desired from Additional desired properties Necessary CW 31:16 15:0 Trace Bus ETM mode 0xFFBA 0x835F 16-Bit ROM/Flash emulation, Trace Bus ETM mode 0xFFBB 0x835F 16-Bit ROM/Flash emulation, Trace Bus Analyzer mode, Appl. JTAG released 0xFFBB 0xA3DF ext. 32-Bit async auto-power-down Flash (2x Am29LV400BT) on EMU port - 0xFFBA 0x675F ext. 16-Bit async. auto-power-down Flash (Am29LV400BT) on EMU port Trace Bus Analyzer mode Don't care 0x2F5F Trace Bus ETM mode Don't care 0x4F5F ext. 32-Bit sync SRAM (e.g. MT55L256L32F) on EMU port MCM int. 16-Bit Flash (Am29LV400BT) - Don't care 0x7F5F ROM int. 16-Bit ROM - Don't care 0x7F5F Micronas 49 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The Standby Registers SR0 to SR1 allow the user to switch on/off power or clock supply of single modules. With these flags it is possible to greatly influence power consumption and its related electromagnetic interference. For details about enabling and disabling procedures and the standby state refer to the specific module descriptions. SR0 Standby Register 0 7 6 5 4 3 2 1 0 r/w I2C1 I2C0 x x x x CAN2 CAN1 3 r/w TIM2 TIM3 TIM4 UART1 x DGB CCC1 x 2 r/w LCD x PSLW UART0 ADC x TIM1 XTAL 1 r/w SM x x x SPI1 CAN0 CCC0 SPI0 0 0x00000100 Offs Res UART0 r/w1: r/w0: UART 0 Module active. Module off. ADC r/w1: r/w0: ADC Module Module active. Module off. TIM1 r/w1: r/w0: Timer 1 Module active. Module off. XTAL r/w1: r/w0: Quartz Oscillator Mode Start-Up Mode active (default after Reset). Run Mode active. SM r/w1: r/w0: Stepper Motor Module active. Module off. SPI1 r/w1: r/w0: SPI 1 Module active. Module off. CAN0 r/w1: r/w0: CAN Module 0 Module active. Module off. CCC0 r/w1: r/w0: Capture Compare Counter 0 Module active. Module off. SPI0 r/w1: r/w0: SPI 0 Module active. Module off. I2C1 r/w1: r/w0: I2C Module 1 Enabled Disabled I2C0 r/w1: r/w0: I2C Module 0 Enabled Disabled CAN2 r/w1: r/w0: CAN Module 2 Module active. Module off. CAN1 r/w1: r/w0: CAN Module 1 Module active. Module off. TIM2 r/w1: r/w0: Timer 2 Module active. Module off. TIM3 r/w1: r/w0: Timer 3 Module active. Module off. TIM4 r/w1: r/w0: Timer 4 Module active. Module off. UART1 r/w1: r/w0: UART 1 Module active. Module off. PFM0 r/w1: r/w0: Pulse Frequency Modulator 0 On Off DGB r/w1: r/w0: DIGITbus Master Module active. Module off. PWM11 r/w1: r/w0: Pulse Width Modulator 11 On Off CCC1 r/w1: r/w0: Capture Compare Counter 1 Module active. Module off. PWM9 r/w1: r/w0: Pulse Width Modulator 9 On Off LCD r/w1: r/w0: LCD Module Module active. Module off. PWM7 r/w1: r/w0: Pulse Width Modulator 7 On Off PSLW r/w1: r/w0: Port Slow Mode Slow mode. Fast mode. PWM5 r/w1: r/w0: Pulse Width Modulator 5 On Off 50 SR1 Standby Register 1 7 6 5 4 3 2 1 0 Offs r/w x x x x x x x x 3 r/w x x x x x x x x 2 r/w x PFM0 PWM11 PWM9 PWM7 PWM5 PWM3 PWM1 1 r/w IRQ FIQ x x x CPUM 0x00000001 0 Res Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 6.2. Standby Registers All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION PWM3 r/w1: r/w0: Pulse Width Modulator 3 On Off PWM1 r/w1: r/w0: Pulse Width Modulator 1 On Off IRQ r/w1: r/w0: IRQ Interrupt Controller Enabled Disabled FIQ r/w1: r/w0: FIQ Interrupt Controller Enabled Disabled Micronas CDC32xxG-B V3.0 3 DEC 01 CPUM CPU Mode Clock selection for CPU and peripheral modules (Section "CPU and Clock System"). 51 VBG ANAU.LS LCK SR0.LCD SR0.XTAL 52 2.5V 10% VBG Generator + - err 1.2V + - err RESETQ ALARM Comp. fvdd_err vdd_err MUX bvdd_err pll_lock ANAU.FVE ANAU.VE Supply Supervision UVDD Logic VDD Regulator + VDD Logic 3.3V FVDD Regulator + - & ANAU.EAL fIO + 1 ext. Flash FVDD FVSS RESET/ ALARM Interrupt Source 2 global reset VREFR RESET Comp. + - POR en + 2/ 3UVDD + 1/ 3UVDD LCD Supply VSS run XTAL1 XTAL Oscillator XTAL2 Fig. 6-1: UVDD Analog Section Block Diagram Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 6.3. UVDD Analog Section UVDD UVSS 2.5V VDD VSS VDD Auxiliary ADVANCE INFORMATION CDC32xxG-B V3.0 3 DEC 01 6.3.1. VBG Generator The low-power VBG Generator generates bias signals which are necessary for the operation of all UVDD Analog Section modules. Furthermore, it produces a reference voltage VBG, that is delivered to the VDD and FVDD Regulators, the RESET and ALARM Comparators and the UVDD Supply Supervision. This module is permanently enabled. 6.3.2. VDD Regulator The VDD Regulator generates the 2.5V VDD supply voltage for the internal core logic from the 5V UVDD. It derives its reference from the VBG Generator. VDD must be buffered externally by a 220nF ceramic capacitor in parallel with a 10uF tantalum capacitor. This module is permanently enabled. A certain set-up time has to elapse after power-up of UVDD for VDD to stabilize. During this time, the Supply Supervision (cf. 6.3.7.) generates a Power-On Reset. An overload condition in the regulator (current or voltage drop-out) generates an immediate Reset and is stored in flag ANAU.VE. The immediate overload signal may be routed to the LCK special output by selection in field ANAU.LS. 6.3.3. VDD Auxiliary Regulator All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The low-power VDD Auxiliary Regulator is designed to deliver a halt mode supply voltage to the core logic, where no clocked operation is required. This module is permanently disabled and available only in Test modes. 6.3.4. FVDD Regulator The FVDD Regulator generates the 3.3V FVDD supply voltage for the external Flash memory device from the 5V UVDD. It derives its reference from the VBG Generator. FVDD must be buffered externally by a 470nF ceramic capacitor in parallel with a 3.3uF tantalum capacitor. This module is permanently enabled. A certain set-up time has to elapse after power-up of UVDD for FVDD to stabilize. During this time, the Supply Supervision (cf. 6.3.7.) generates a Power-On Reset. An overload condition in the regulator (current or voltage drop-out) generates an immediate Reset and is stored in flag ANAU.FVE. The immediate overload signal may be routed to the LCK special output by selection in field ANAU.LS. 6.3.5. ALARM Comparator The Alarm Comparator on the pin RESETQ allows the detection of a threshold higher than the reset threshold. An alarm interrupt can be triggered with the output of this comparator. To obtain a result that is independent from UVDD, the level of pin RESETQ is compared to the VBG reference voltage. The comparator features a small built-in hysteresis. The output constitutes the RESETQ/ALARM Interrupt Source and must be enabled by setting flag ANAU.EAL. Please refer to section 6.4.1. for functional details. The interrupt source output is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The alarm interrupt is a level triggered interrupt. The interrupt is active as long as the voltage on pin RESETQ remains between the two thresholds of the ALARM and the RESET comparator. 6.3.6. RESET Comparator As long as the Reset Comparator on the pin RESETQ detects the low level, the overall IC is reset. Please refer to sections 6.4.2. and 6.4.4. for functional details. To obtain a result that is independent from UVDD, the level of pin RESETQ is compared to the scaled down VBG reference voltage. The comparator features a built-in hysteresis. 6.3.7. Supply Supervision When UVDD drops below a level VREFPOR of approx. 2.8V, or when the internal VDD or FVDD Regulators detect an overload condition, this module generates a Power-On reset signal POR that is routed to the Reset Logic. Refer to section 6.4.2.1. for more details. 6.3.8. XTAL Oscillator The XTAL Oscillator generates a 4 to 5 MHz reference signal from an external quartz resonator, cf. section "Electrical char- Micronas acteristics" for quartz data. 53 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 A reset sets the module to START-UP mode, where, at the expense of a higher current consumption, marginal quartzes receive more drive to ease start-up of oscillation. After start-up of the CPU program, register SR0.XTAL may be cleared by SW to set the XTAL Oscillator to RUN mode, where current consumption is at its standard level. For operation at UVDD levels between 3.5V and 4.5V, continuous operation of the module in START-UP mode may be necessary, to guarantee sufficient drive to the connected quartz. Switching between START-UP and RUN modes must not be done in CPU modes PLL or PLL2, as this might lead to unpredictable behaviour of the clock system. ANAU r/w 7 6 EAL x 0 EAL Analog UVDD Register 5 4 LS 0 3 2 1 0 x x FVE VE 0 0 0 r/w1: r/w0: Enable RESET/ALARM Interrupt Source output Enabled. Disabled. LS w0: LCK output Select PLL Lock Signal. w1: w2: w3: VDD Regulator Error. FVDD Regulator Error. BVDD Regulator Error. FVE r1: r0: w1: w0: FVDD Regulator Error Flag Out of specification. Normal operation. Reset flag. No action. VE r1: r0: w1: w0: VDD Regulator Error Flag Out of specification. Normal operation. Reset flag. No action. 6.4. Reset Logic 6.4.1. Alarm Function The Alarm Comparator on the pin RESETQ allows the detection of a threshold higher than the reset threshold. An alarm interrupt can be triggered with the output of this comparator. The intended use of this function is made, when a system uses a 5V regulator with an unregulated input. In this case, the unregulated input, scaled down by a resistive divider, is fed to the RESETQ pin. With falling regulator input voltage this alarm interrupt is triggered first. Then the reset threshold is reached and the IC is reset before the regulator drops out. The time interval between the occurrence of the alarm interrupt and the reset may be used to save process data to nonvolatile memory. In addition, power saving steps like turning off stepper motor drivers may be taken to increase the time interval until reset. 6.4.2. Internal Reset Sources This IC contains four internal circuits that are able to generate a system reset: watchdog, supply supervision, clock supervision and FHR flag. All internal resets are directed to the open drain output of pin RESETQ. Thus a "wired or" combination with external reset sources is possible. The RESETQ pin is current limited and therefore large external capacitances may be connected. All internal reset sources initially set a reset request flag. This flag activates the pull-down transistor on the RESETQ pin. An internal reset timer starts, as soon as no internal reset source is active any more. It counts 2048 fXTAL periods (for alternative settings refer to HW options register CR) and then resets the reset request flag, thus releasing the RESETQ pin. 54 As long as the Reset Comparator on the pin RESETQ detects the low level, the overall IC is reset. The state of the flags CSW1.FHR, CSW1.CLM, CSW1.PIN, CSW1.POR and CSW1.WDRES, read directly after a system reset, allows to distinguish the cause of this last system reset (Table 6-5). 6.4.2.1. Supply Supervision A UVDD level below the Supply Supervision threshold VREFPOR, or an overload condition in the internal VDD or FVDD Regulators will permanently pull the pin RESETQ low and thus hold the IC in reset (see Fig. 6-2 on page 55). With HW Option CM.WCM = 0, this reset source can be enabled/disabled by flag CMA in register CSW0 (see Section 6.4.2.2. on page 54). 6.4.2.2. Clock Supervision The Clock Supervision monitors the frequency at the oscillator input XTAL1 and also the frequency fSUP that is present at the input of the central clock divider (see Fig. 4-1). Frequencies below the clock supervision threshold of approx. 200kHz will permanently pull the pin RESETQ low and thus hold the IC in reset (see Fig. 6-2 on page 55). With HW Option CM.WCM = 0, this reset source can be enabled/disabled by flag CMA in register CSW0. Frequencies exceeding the specified IC frequency are not detected. There are two general operation options which can be selected in the HW Options field CM: 1. Flag WCM = 1: Clock and Supply Supervision are permanently active. They Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 6.3.9. UVDD Analog Registers CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 watchdog timer register to 0xFF, thus forcing the Watchdog to create a maximum reset interval. can not be deactivated. The Watchdog must be serviced by SW. This mode is recommended for all stand-alone applications requiring high operational reliability. The Watchdog is controlled by register CSW1. The first write access to it loads the timer register value setting the Watchdog's unretriggered reset interval. The desired interval can be programmed by setting the CSW1 value to: 2. Flag WCM = 0: Clock and Supply Supervision are active after reset, but can be enabled/disabled by the clock monitor active flag CMA of register CSW0. The Watchdog must be serviced only after a first write access to register CSW1. This mode is recommended for test and evaluation purposes only. Interval x f 15 -1 FAST and PLL modes: Value = ------------------------------1 6.4.2.3. Watchdog Interval x f 15 SLOW modes: Value = ------------------------------- - 1 128 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The Watchdog module serves to monitor undisturbed program execution. A failure of the program to retrigger the Watchdog within a preselectable time will pull the pin RESETQ low and thus reset the IC (Fig. 6-2 and 6-3). With HW Option CM.WCM = 0, this reset source is only enabled after a write access to register CSW1 (see Section 6.4.2.2. on page 54). The second and all following even numbered write accesses load watchdog trigger register 1, the third and all following odd numbered write accesses load watchdog trigger register 2. In all future, the SW has to write alternatingly to register CSW1 value and bit complement value, thus retriggering the up-counter. Failure to retrigger will result in an overflow of the up-counter generating a Watchdog reset. The Watchdog contains a down-counter that generates a reset when it wraps from zero to 0xFF. It is reloaded with the content of the watchdog timer register, when, on a write access to register CSW1, watchdog trigger registers 1 and 2 contain bit complemented values. An IC reset resets the + VREFR global reset RESETQ Reset extension 8 or 2048 oscillator pulses & reset in Watchdog WDRES HW option CM.WCM CSW0.CMA 0 VDD fXTAL fSUP UVDD VREFPOR S Q R >1 1 clock supervision + POR wr CSW1 wr1 CSW0.FHR power on & 1 CLS & 1 res CSW1 SQ R CSW1.FHR SQ R CSW1.CLM SQ R CSW1.POR SQ R CSW1.PIN Fig. 6-2: Reset Logic Block Diagram Micronas 55 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 CSW1 2.write & even Trigger Reg1 3.write & odd CSW1 CSW1 1. write Trigger Reg2 8 Timer Register 8 8 clk pll,fast: f15 slow: f15 /128 1. write = 1 & load 8-Bit-Counter zero & 2.write & even 3.write & odd 1 D Q C S reset in HW Option power on S Q R & WDRES VDD S Q R res CSW1 CSW1.WDRES Fig. 6-3: Watchdog Block Diagram It is not allowed to change a chosen value. Writing a wrong value to CSW1 immediately prohibits further retriggering of the watchdog counter. The flag WDRES is set as soon as the watchdog counter reaches zero. 6.4.5. Summary of Module Reset States WDRES is true after a Watchdog reset. Only a Supply Supervision reset or a write access to register CSW1 clears it. Table 6-4: Status after Reset After reset the IC modules are set to the reset state (Fig. 6- 4) Module Status 6.4.3. Forced Hardware Reset CPU CPU Fast mode (fOSC). Setting flag CSW0.FHR immediately forces the RESETQ pin low. This allows the SW to restart the whole system by HW reset. Interrupt Controller Interrupts are disabled. Priority registers, request flip flops and stack are cleared. U-Ports Normal mode. Output is tristate. High current ports Normal mode. Output is low. LCD module Registers are reset. No display. Watchdog Depends on mask option. EMU option: Switched off. SW activation is possible. Stand-alone option: Permanently active. Clock monitor Depends on mask option. EMU option: Active. SW may toggle. Stand-alone option: Permanently active. 6.4.4. External Reset Sources As long as the Reset Comparator on the pin RESETQ detects the low level, the overall IC is reset. On this pin, external reset sources may be wire-ored with the IC internal reset sources, leading to a system wide reset signal combining all system reset sources. 56 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 1. write CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 6.4.6. Reset Registers 4 3 2 1 0 FHR x x x x x x CMA 0 x x x x x x 1 Table 6-5: Source of last Hardware Reset Res This register controls the Supply and Clock Supervision modules and allows to force a system reset. FHR w1: w0: Forced Hardware Reset Reset forced no action All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CMA Clock and Supply Monitor Active w1: Both Enabled. w0: Both Disabled. Can be written to zero only after power on reset or clock supervision reset and before first write access to register CSW1 if allowed by HW option. CSW1 r Watchdog Reset (Table 6-5)) WDRES 5 WDRES Source POR 6 Supply Supervision Reset (Table 6-5) PIN 7 POR CLM w Clock, Supply & Watchdog Register 0 RESETQ Pin Reset (Table 6-5) FHR CSW0 PIN 0 0 1 0 0 external from RESETQ pin 0 0 1 0 1 internal Watchdog Reset 0 1 1 0 0 internal Clock Supervision Reset 0 1 1 1 0 internal Supply Supervision Reset 1 0 1 0 0 internal Forced Hardware Reset The registers sum up the source of all HW resets that ocurred since the last write to register CSW1. Any write access to CSW1 resets all flags to 0. Clock, Supply & Watchdog Register 1 7 6 5 4 3 2 1 0 TST x x FHR CLM PIN POR WDRES - - - 0 0 0 0 0 CSW1 7 Res Clock, Supply & Watchdog Register 1 6 w The Reset state in the register frame above describes the state after a write to register CSW1. 5 4 3 2 1 0 1 1 Watchdog Time and Trigger Value 1 1 1 1 1 1 Res This register controls the Watchdog module. Only values between 1 and 255 are allowed. TST r1: r0: TEST Pin State TEST is 1. TEST is 0. FHR Force Hardware Reset (Table 6-5 CLM Clock Supervision Reset (Table 6-5) First write the desired watchdog time value to this register. On further writes, to retrigger the Watchdog, alternatingly write a value (not necessarily the former time value) and its bit complemented value. Never change the latter value. 6.5. Test Registers Test registers are for manufacturing test only. They must not be written by the user with values other than their reset values (00h). They are valid independent of the TEST input state. In all applications where a hardware reset may not occur over long times, it is good practice to force a software reset on these registers within appropriate intervals. TST1 7 Test Register 1 6 5 w 4 3 Micronas 0 0 0 0 7 Test Register 2 6 1 5 w 0 0 0 7 0 0 0 Res 3 2 1 0 0 0 0 0 0 2 1 0 0 0 0 Res Test Register 3 6 5 w 0 4 For testing purposes only TST3 2 For testing purposes only 0 TST2 4 3 For testing purposes only 0 0 0 0 0 Res 57 TST4 7 0 7 0 7 0 7 0 58 6 0 TST5 6 0 TSTAD2 6 0 TSTAD3 6 0 5 w 0 5 w 0 5 w 0 5 w 0 4 0 4 0 4 0 4 0 3 For testing purposes only 0 Test Register 5 3 For testing purposes only 0 Test Register AD2 3 For testing purposes only 0 Test Register AD3 3 For testing purposes only 0 2 1 0 0 0 0 2 1 0 0 0 0 2 1 0 0 0 0 2 1 0 0 0 0 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Test Register 4 Res Res Res Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 7. JTAG Interface This module provides JTAG style access to 5 internal scan chains. These allow testing, debugging, EmbeddedICE and ETM (Embedded Trace Module) programming. The scan chains are controlled by a JTAG style Test Access Port (TAP) controller. For further details on operating TAP controller, EmbeddedICE and ETM, please refer to ARM7TDMI Data Sheet (Document Number: ARM DDI 0029), Embedded Trace Macrocell Specification (Document Number: ARM IHI 0014) and ETM7 Technical Reference Manual (Document Number: ARM DDI 0158). Features - 2 Interfaces selectable - Access to CPU periphery - Access to EmbeddedICE - Access to Embedded Trace Module ETCK ETMS JTAG TAP Controller 0 TDI ETDI TDO nTRST ETDO & nTRST POR Emulation JTAG Ifc CPGA257 only TCK TMS MUX TCK/U3.2 TMS/U3.1 1 TDI/U3.0 TDO/U3.3 1) TEST2 Application JTAG Ifc All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 7.1. Functional Description & 1) Gnd @ PQFP128 CR.JTAG Fig. 7-1: JTAG Interface Block Diagram The TAP controls the access to the scan chains. Scan chain 0 allows access to the entire periphery of the CPU. Scan chain 1 is a subset of the scan chain 0. Scan chain 2 allows programming of the EmbeddedICE debug module. Scan chain 3 is reserved for the boundary scan of the pads of the packaged device. Scan chain 6 allows programming of the ETM. Table 7-1: Scan Chains Number Size [Bit] Function 0 105 ARM7 Macrocell 1 33 Part of scan chain 0 2 38 EmbeddedICE 3 - reserved for Boundary scan 6 40 ETM Micronas Two interfaces can be selected to access the TAP controller. The selection has to be done by the control register flag CR.JTAG and the pins TEST2 and nTRST. 7.1.1. Application JTAG Interface The application JTAG interface is connected to the special inputs and outputs of U-Ports. The U-Port for the signal TDO has to be configured as special out, those for the signals TCK, TMS and TDI as special in. The application JTAG interface is available if enabled and the external circuit layout allows it. It is enabled if the TEST2 pin is high, the nTRST pin is low and the flag CR.JTAG is set to one. The TEST2 pin is the nTRST input of the application JTAG interface. If TEST2 pin is high during reset, U-Port U3.3 (= JTAG TDO) is forced to Port, Special, Output mode until programmed by SW. Otherwise the emulation JTAG interface couldn't be operated without internal SW support. To avoid conflicts between JTAG mode and SW control on this port bit, never mix these two modes in one application. The application SW must not initialize the involved U-Ports if flag CR.JTAG is set to one. 59 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 7.1.2. Emulation JTAG Interface 7.1.4. Pin TEST2 The emulation JTAG interface is connected to dedicated pins of the emulation parts (CPGA257 package). Series parts (PQFP128 package) do not provide this interface. It is enabled as long as the application JTAG interface is disabled. The pin TEST2 is weakly pulled down to UVSS by the current Ipd. Refer to section "Electrical Characteristics" for details. Besides JTAG, the pin TEST2 controls the behavior of the IC during reset. Refer to section "Core Logic" for further details. 7.1.3. Boundary Scan The boundary scan is not implemented in this IC. The emulation JTAG interface uses TTL level input comparators. The emulation JTAG inputs ETCK, ETMS, ETDI and nTRST need external pull-up resistors to EVDD. This has to be done in a way, that the TAP controller sees a logic one if the emulation JTAG interface is enabled but not driven. The application JTAG interface shares its input and output pins with the I/O of U-Ports. The external circuit layout has to be done carefully in order to guarantee functionality of the JTAG interface. As long as the application JTAG interface is enabled and not driven, the TAP controller inputs TMS and TDI shall see logic one level. If it is enabled and driven, the external application circuit shall not influence proper operation of the JTAG interface. The external host must be able to drive the levels at the inputs TCK, TMS and TDI to CMOS logic one and logic zero levels and it must be the only source of these signals. The TAP controller must be able to drive the output TDO to both CMOS levels, logic one and zero, and must be the only source of this signal. Common JTAG tools expect to see pull-up resistors at nTRST (TEST2), TCK,TMS and TDI. 7.3. JTAG ID The JTAG ID is not implemented in this IC. The JTAG TAP controller contains a HW coded JTAG ID which can be read serially via the JTAG interface. The CPU can't access this ID. Version Part Number 31 28 27 26 25 24 23 20 19 12 11 Device Number 1 c2 c1 c0 Family Bits 1 to 19 are manufacturer defined. Bits 0 and 20 to 31 are ARM defined. Manufacturer ID 1 0 1 Fig. 7-2: JTAG ID Format Bit 31 to 28 0: 1: 2: Version ARM core revision 0. ARM core revision 1. etc. Bit 27 0: 1: ARM core ID. Non ARM core ID. Bit 26 0: 1: Capability bit 2 Standard part. `E' part. Bit 25 Capability bit 1 (Reserved) Bit 24 0: 1: Capability bit 0 Hard macro. Synthesisable. Bit 23 to 20 Family 7: ARM7. 60 9: A: etc. ARM9. ARM10. Bit 19 to 12 Device Number Manufacturer device number 0 to 255. Bit 11 to 1 Manufacturer ID Manufacturer ID is the compressed JEDEC code (0x06C). Bit 0 Marker Fixed value. The necessity of using bits 19 to 12 as manufacturer device number forces us to use the Non ARM core ID format of the JTAG ID. This is the reason why some debug tools can't use auto configuration, but must be configured by the user for the correct core and revision. The part number shall be selected in a way that no two component types in the same package with TAP pins in the same location have the same part number. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 7.2. External Circuit Layout CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 8. Embedded Trace Module (ETM) This module provides instruction and data trace capability. The ETM is controlled by a JTAG style Test Access Port (TAP) controller. For further details on the installed Rev1A please refer to Embedded Trace Macrocell Specification (Document Number: ARM IHI 0014) and ETM7 Technical Reference Manual (Document Number: ARM DDI 0158). - Data trace - Trace before, about, after trigger - Trigger and filter capabilities - Access to Embedded Trace Module - Normal trace data format - Full-rate and half-rate clocking Features - 4/8/16bit maximum port width - Instruction trace 8.1. Functional Description PIPESTAT0 to 2 ETM7 Rev1A TRACEPKT0 to 15 TRACESYNC EXTTRIG 1 PWRDOWN ETCK DBGRQ nRESET ETMS 0 ETDI TCK ETDO TMS JTAG TAP Controller nTRST MUX TDI TCK/U3.2 TDO nTRST Emulation JTAG Ifc CLK FSYS TMS/U3.1 & POR 1 TDI/U3.0 TDO/U3.3 TEST2 Application JTAG Ifc All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. TRACECLK & CR.JTAG 1 & RESETQ CR.TETM DBGRQ DBGACK ARM and EmbeddedICE BREAKPT EXTERN0 EXTERN1 RANGEOUT0 RANGEOUT1 nEXEC nRESET nRESET Fig. 8-1: ETM Interface Block Diagram Micronas 61 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The ETM is controlled via scan chain 6 of the JTAG interface. The process of remapping or loading code to RAM and execute it there is a problem for the ETM because one address can contain different code (overlay). The solution is based on the requirement that the memory map into which overlays are loaded exists in multiple places in the address space. The memory controller of the IC decodes the 24 LSB address lines A0 to A23. This results in an memory map of 16 MByte. This memory map is repeated 256 times within the 32 bit ARM core address space of 4 GByte. Thus it is possible to have one static image of the code being executed for the trace tool, with different possible overlays statically linked into the appropriate area of the address space. Loading code into the RAM and execute it there means, copy the code into the RAM and then jump to its overlay. The ETM sees the full 32 bit address and reports this jump to the trace tool which has the static image with a memory map for each configuration at different places of its address space. The memory controller sees the 24 lower address lines only, therefor the jump is directed to the correct location. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The supported trace features are listed in Tabel 8-1. Table 8-1: Trace Features Features Supported Demultiplexed trace data format - Multiplexed trace data format - Normal trace data format Full-rate clocking Half-rate clocking Maximum port width 4/8/16-bit 62 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 9. IRQ Interrupt Controller Unit (ICU) The Interrupt Controller Unit manages up to 63 interrupt sources. Each interrupt source has its own interrupt vector pointing to an interrupt service routine. One of 16 priorities can be assigned to each channel or it can be disabled. The Interrupt Controller Unit is connected to the nIRQ input of the CPU. Features - Expanding nIRQ input of ARM7TDMI - Up to 63 interrupt sources (39 implemented) - 16 priority levels - HW vectoring - HW prioritization - HW stacking of priority levels - 2 cycles maximum from input to CPU nIRQ All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 9.1. Functional Description IntSrc IntSrc IntSrc Int. Src. Node ISN ISN E P IRQ: PC = 0x00000018 IAck <- Read from address [VTB] IExit <- Write to address [VTB]+0x100 src prio. level a prio 4 a>b Priority Encoder src# 6 CRI.GE IExit IAck Vect. Tab. Base & nIRQ Act. Prio. Level act. prio. 4 24 b CRI.TE Address Bus from CPU 24 Vector Table Logic force prio 24 Address Bus to Mem. Ctrl. LDR PC,[PC,# <12_bit_offset>] LDR PC,[VTB] Fig. 9-1: Block Diagram The Interrupt Controller Unit (ICU) is composed of an Interrupt Source Node (ISN) for each interrupt source, of a Priority Encoder, of a Vector Table Logic, of an Active Priority Level Logic and a comparator (Fig. 9-1). Each falling edge of an interrupt source signals an interrupt request to its ISN and sets its Pending flag P (Fig. 9-2). Besides the P flag each ISN consists of an Enable flag (E) and a Source Priority register containing the priority of the corresponding interrupt source. As long as both flags (E and P) are true, the ISN outputs its priority. Otherwise it outputs the lowest priority (that is no priority). The Priority Encoder outputs number and priority of the ISN with the highest active priority. If several ISNs with the same priority are active at the same time, the ISN with the lowest source number is selected, thus the ISNs are operated in a HW defined order. The interrupt vector table contains the start addresses of the interrupt service routines (ISR). The Vector Table Base register points to the first entry of the interrupt vector table. Thus the location of the interrupt vector Micronas table is programmable to any memory location. This allows easy switching between different tables. DB D Q IntSrc DB S Q P & src prio level 4 D R IAck src# E & 6 to Priority Encoder Fig. 9-2: ISN Flags The Active Priority Level Logic outputs the priority of the currently running task (lowest priority is the background task). The comparator activates its output if this priority is lower than the priority output from the Priority Encoder. 63 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The SW has to read the address where the Vector Table Base register points to ([VTB]) in order to get the start address of the ISR for the ISN with the currently highest active priority (Fig. 9-3). A data fetch from this location generates an internal interrupt acknowledge signal (IAck). With IAck the Active Priority Level Logic accepts the new priority and internally saves the priority of the interrupted task. IAck clears the P flag in the corresponding ISN and deactivates the nIRQ output. The ICU is ready for new interrupts now. Before leaving the interrupt service routine, the SW has to write to the address where VTB points to plus 0x100 ([VTB]+0x100). A write to this location generates an internal interrupt exit signal (IExit). With IExit the Active Priority Level Logic internally deletes the priority of the current task and outputs the priority of the interrupted task where the immediately following return instruction jumps to. ning task. Writing the maximum priority to the Forced Priority register is another way to disable the ICU because no ISN can generate an IRQ. Raising of the priority in this way does not take effect as long as nIRQ is active. The Global Enable (GE) signal at the output of the comparator disables the ICU output. It is impossible to inactivate an active nIRQ output by modifying an ISN, the GE flag or forcing the priority. Only IAck resets the nIRQ output. The size of the ICU can be scaled in steps of 8 ISNs. This IC has 40 Interrupt Source Nodes implemented (ISN0 to ISN39). Derived parts can contain 40, 32 (ISN0 to ISN31), 24 (ISN0 to ISN23) or less ISNs. The Pending flags P in the ISNs are operating even when the ICU is disabled (CRI.GE = 0). To be exact, only the ICU output is disabled. This avoids further interrupts. Interrupted ISRs will be finished and the Act. Prio. Level stack will be handled properly if those ISRs generate IExit before returning. reset 100 0FC 0F8 0F4 0F0 Exit ISN63 ISR ISN62 ISR ISN61 ISR ISN60 ISR ISN2 ISR ISN2 ISR ISN1 ISR ISN0 ISR CRI.GE R Q R Q reset CRI, AFP, ISN and internal logic disable nIRQ interrupt exit address Fig. 9-4: Reset Structure source number 00C 008 004 000 SR1.IRQ Figure 9-4 shows the reset structure. Registers can't be written until the IRQ flag in the standby register SR1 is set. The pending flags P in the ISNs are not reset by the standby register. It can be operated by HW even while SR1.IRQ is zero. Reading and writing of the P flags is impossible unless SR1.IRQ is set to one. interrupt entry address Vector Table Base 32 Bit Fig. 9-3: Interrupt Vector Table Each ISN has a dedicated source number. A maximum of 64 ISNs can be connected to the Priority Encoder. The Priority Encoder outputs source number 0 as long as all ISNs output priority 0 or no ISN is active or the comparator output is inactive. This is to guarantee a valid state of the Priority Encoder and return a valid start address even if no interrupt source is active. The corresponding vector is the first in the vector table (default vector). For this reason ISN0 can't be used for connecting an interrupt source, because ISN0 is not the only user of the corresponding interrupt vector. For example, reading the address location pointed to by the Vector Table Base register while nIRQ is inactive will return the ISR start address of ISN0. Additional to the ISNs whose inputs are connected to a HW module, some ISNs are necessary whose inputs are not connected or unused. Those interrupts can be activated by SW solely (delayed interrupt). The output of the Active Priority Level Logic may be forced by writing a higher priority to the Forced Priority register. This allows temporary raising of the priority of the currently run- 64 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. If the ICU's output is enabled by the Global Enable flag (GE) the nIRQ input of the CPU is activated and held active until acknowledged. The IRQ is granted by the CPU as soon as the CPU internal IRQ flag (flag I in CPU register CPSR) is enabled by SW. In the meantime between interrupt activation in the ICU and granting by the CPU, higher priority interrupt requests may be signaled to the ICU, raising the priority output of the Priority Encoder. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION Table 9-1: Interrupt Assignment Micronas CDC32xxG-B V3.0 3 DEC 01 Table 9-1: Interrupt Assignment ISN Interrupt Source ISN Interrupt Source 32 PINT5 0 Default vector, not connected 33 CAN2 1 CC0OR 34 CC0COMP 2 CC1OR 35 CC1COMP 3 PINT0 36 CC2COMP 4 PINT1 37 CC3COMP 5 CAN0 38 PINT4 6 SPI0 39 GBus 7 Timer 1 8 Timer 0 9 P06 COMP 10 RESET/ALARM 11 WAIT COMP 12 UART0 13 PINT2 14 reserved for WAPI 15 CC2OR 16 CC3OR 17 Timer 2 18 reserved for RTC 19 I2C0 20 Timer 3 21 SPI1 22 COMMRX 23 COMMTX 24 PINT3 25 DIGITbus 26 I2C1 27 CAN1 28 CC4OR 29 CC5OR 30 Timer 4 31 UART1 65 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 9.2. Timing CPU fSYS (ECLK) prio comp IntSrc nIRQ src# Fig. 9-5: Timing another cycle. The CPU finally evaluates with the next falling edge of fSYS. This results in a maximum delay of 2 fSYS cycles from request to CPU input. 9.3. Registers CRI r/w FPRIO Forced Priority r/w: (Table 9-3) Writing a value higher than the APRIO value to this location raises the priority of the actual running ISR. It doesn't change APRIO. Only ISRs with a priority higher than the forced priority are able to interrupt now. Control Register IRQ 7 6 5 4 3 2 1 0 GE TE x x x x x x 0 0 x x x x x x Res GE Global Enable r/w1: Enable IRQ. r/w0: Disable IRQ. Disabling happens as soon as nIRQ is inactive. An active nIRQ will not be interrupted by writing a zero to GE. TE Table Enable r/w1: Enable. r/w0: Disable. The Vector Table Logic doesn't work if TE is disabled. Neither the correct ISR start address is returned nor the internal signals IAck and IExit are generated on accessing the dedicated memory location. AFP Actual and Forced Priority Register 7 6 r/w 5 4 3 2 APRIO 0 0 1 0 0 0 r 0 0 Res Priority Encoder Priority output 7 6 5 4 x x x x x x x x 3 2 1 0 0 0 Priority 0 0 Res This register shows the priority of the highest pending and enabled interrupt source. PESRC r APRIO Actual Priority r: (Table 9-3) This field indicates the programmed priority of the actually running ISR. It is modified by HW only. 66 PEPRIO 0 FPRIO 0 It is necessary to first save the original FPRIO value before raising the own priority by overwriting FPRIO. The saved FPRIO value has to be restored before ISR exit. Priority Encoder Source output 7 6 x x x x 5 4 3 2 1 0 0 0 0 Source 0 0 0 Res This register shows the number of the highest pending and enabled interrupt source. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The sample period of an incoming interrupt request lasts one cycle in the worst case. It is sampled by an ISN with the falling edge of fSYS. Priority Encoder and comparator require CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 VTB r/w Vector Table Base 7 6 5 4 0 0 0 0 r/w 3 0 2 1 0 0 0 0 Address bit 23 to 16 r/w r/w this interrupt source node is enabled, this flag is cleared by HW as soon as the corresponding ISR is called. 0 0 0 0 3 0 0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. r/w M P E x 0 x 0 x Not pending Don't modify P Pending Res 1 0 Not possible 1 1 2 1 0 0 0 PRIO 0 0 1 Interrupt Source Node Register x 3 0 0 Accessing these locations ([VTB] and [VTB]+0x100) without generating IAck or IExit is possible when the Vector Table Logic is disabled (CRI.TE = 0). 4 Write 0 Every word write access to the location addressed by VTB plus 0x100 activates the internal signal IExit. 5 Read 0 Every word read access to the location addressed by VTB deactivates the nIRQ output. If the comparator output is active, the internal signal IAck is activated, which returns the ISR start address of the ISN with the highest active priority, clears the corresponding P flag and saves the interrupted priority. 6 P 1 The register VTB has to be programmed with the memory base address of the interrupt vector table. The interrupt vector table has to start at an even page address (9 LSB are zero) and is not longer than one page (256 bytes). Besides the start address of the interrupt vector table VTB defines two addresses which perform HW actions when accessed and CRI.TE is set. 7 M 0 0x00000000 ISNx Table 9-2: Pending Flag Access 2 Address bit 15 to 9 0 Offs 0 Clear P Set P E Enable r/w1: Enable interrupt. r/w0: Disable interrupt. This flag is modified by SW only. PRIO Interrupt Source Node Priority This field is modified by SW only (Table 9-3). Table 9-3: Priority Encoding PRIO Priority number 3 2 1 0 0 0 0 0 0 (No priority) 0 0 0 1 1 (Lowest priority) 0 0 1 0 2 : : : : : 1 1 1 0 14 1 1 1 1 15 (Highest priority) Res M Modify Pending Flag (Table 9-2) w1: Modify Pending flag. r/w0: Don't modify Pending flag. This flag is modified by SW only and always reads as 0. It allows modification of register ISNx without influence to flag P. Without this flag a HW modification of flag P could be corrupted by a simultaneous read-modify-write of register ISNx. P Pending (Table 9-2) r/w1: Interrupt is pending. r/w0: No interrupt pending. This flag can be modified by HW and SW. It is set by HW when the corresponding interrupt source input is activated. If Micronas 67 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 9.4. Principle of Operation Clearing standby register flag SR1.IRQ resets the ICU (see Fig. 9-4 on page 64). The registers are reset to their mentioned values (see Section 9.3. on page 66) and cannot be modified. The nIRQ output is inactive and the actual priority level logic is cleared. 9.4.2. Initialization Proper configuration of the interrupt sources in the peripheral modules has to be made prior to initialization of the ICU. Initialization is possible after the standby register flag SR1.IRQ has been written to one. Now the registers can be modified by SW. But no interrupt request is generated to the CPU. Install the vector table beginning at an even page address (9 LSB are zero). Each entry has to be a 32 bit start address of an interrupt service routine. The vector table has to be located near (4kB) the load PC instruction. Write the start address of the vector table to the Vector Table Base register VTB. Further access to register VTB is not necessary until you want to switch to another vector table at another location. Set up the Interrupt Source Node registers ISNx with the necessary priority and enable them. The pending flags have to be cleared, because they are not cleared by SR1.IRQ and are operative all the time. Clearing an active pending flag and enabling the corresponding ISN must not be done with a single instruction. This might lead to an unwanted (spurious) interrupt which is directed to the default vector. First clear P and then set E in two instructions. Interrupt sources which shall not generate interrupts must not be enabled and need no priority (PRIO=0), but can be operated by polling and resetting the pending flag P by SW. 9.4.3. Operation The ICU is operable in all CPU modes. Setting both flags CRI.GE and CRI.TE enables the ICU at last. When an interrupt occurs, execution starts at address 0x18. For proper operation of the ICU the jump to the inter- rupt service routine has to be done by the PC relative load PC instruction LDR PC,[PC,#<12_bit_offset>], where the operand [PC,#<12_bit_offset>] must point to the first entry of the vector table. Due to the 12_bit_offset the vector table has to be located within 4kB from the above instruction. Above instruction is called vectoring. There are two possibilities for the point of time, direct and delayed, when vectoring takes place. 9.4.3.1. Direct Vectoring Above instruction is the first instruction which is executed when an interrupt occurs. The address 0x18 contains the PC relative load PC instruction. 9.4.3.2. Delayed Vectoring Above instruction is delayed. The address 0x18 contains a jump to a short piece of code which does all what has to be done for every ISR (Save LR, SPSR and working registers). After this common prefix the jump to the appropriate ISR is launched by the PC relative load PC instruction. 9.4.4. Inactivation An interrupt source can be disabled locally by clearing the enable flag E in the corresponding ISN register. Even a pending interrupt can be disabled this way. A disabled ISN does not participate in sending interrupt requests to the CPU. All interrupt sources can be disabled globally by clearing the global enable flag CRI.GE. It is impossible to inactivate an active nIRQ output signal by clearing CRI.GE. An active nIRQ will be served and only further IRQs can be suppressed by setting the GE flag. The pending flag P stays operative in both cases and may be polled by SW. A zero in the standby register flag SR1.IRQ immediately resets registers and logic and forces the nIRQ output to inactive. 9.5. Application Hints 9.5.1. Hardware Triggered Interrupts Normally the connected peripheral modules are setting the pending flag P. If the ISN is enabled (E=1) and the priority is not zero, an IRQ is generated. The P flag will be reset as soon as the corresponding interrupt service routine is called. It is not required and should be avoided to modify the P flag of those ISNs by SW. 9.5.2. Software Triggered Interrupts Any ISN which is not used by the connected peripheral module can be used for generating IRQ interrupts by SW. It must be avoided that the interrupt source of this ISN is also generating interrupt requests. Either the corresponding peripheral 68 module has to be switched off or its interrupt source output has to be disabled. The ISN has to be enabled (E=1) and programmed to the desired priority (PRIO>0). Setting the pending flag P by SW generates an interrupt. This interrupt will be processed as soon as possible. When the CPU responds to the interrupt request and jumps to the corresponding ISR, the pending flag is cleared automatically. 9.5.2.1. Delayed Interrupt Any ISN which is not used by the connected peripheral module can be used for implementing the delayed interrupt mechanism for an operating system. The ISN has to be Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 9.4.1. Reset CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 enabled (E=1) and programmed to priority 1 (the lowest priority which can generate an interrupt). Setting the pending flag P by OS-SW within a higher priority interrupt service routine generates a delayed interrupt, which is processed after all higher priority interrupts are finished. 9.5.3. Polling Polling means that the pending flag P is observed by SW. Set by the corresponding interrupt source, the SW recognizes the P flag to be set, calls the corresponding routine and clears the P flag. The ISN should be disabled (E=0), otherwise unwanted IRQs would be generated. 9.5.4. Operating Nested Interrupts All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Nested interrupt service routines use common data resources. Every routine, which may have interrupted a lower priority routine, has to save common data resources upon interrupt entry and restore them before returning to the interrupted routine. This is efficiently done by an entry and an exit sequence which are enclosing the interrupt service routine. 9.5.4.1. Interrupt Entry Sequence The IRQ disable flag I in the core register CPSR is set after an IRQ, thus disabling further IRQs. Before the interrupt is enabled again, the user has to take the following steps: 1. For direct vectoring: Jump to the corresponding interrupt service routine by loading the first element from the vector table into the program counter by an LDR instruction. 2. Save Link Register (R14), SPSR and working registers to stack. 3. For delayed vectoring: Jump to the corresponding interrupt service routine by loading the first element from the vector table into the program counter an LDR instruction. 4. Clear CPSR.I to re-enable IRQs. Now the actual application ISR can start. 9.5.4.2. Interrupt Exit Sequence Before returning, it is necessary to clear the interrupt cause. Upon exit from an ISR some actions have to be taken without being interrupted: 1. Set CPSR.I to disable further IRQs. 2. Restore Link Register (R14), SPSR and working registers from stack. not be re-enabled by clearing the I flag of the CPSR. No IExit shall be generated on interrupt exit by writing to [VTB]+0x100 because there was no IAck at interrupt entry. Unintentional inactivation of an active comparator output signal can be caused by modifying the ISN which is the only source for the momentary active nIRQ output. This can be done by disabling (E=0), or clearing the P flag, or lowering the priority of this ISN. Those actions may lead to a default vector interrupt. 9.5.6. Debugger Unintentional access to vector table addresses [VTB] and [VTB]+0x100 can result in malfunction of the interrupt system (HW and SW). If it is necessary, for instance, to dump the vector table, there are two ways to do this without generation of IAck or IExit: The first way is to clear the flag CRI.TE which controls the vector table logic. Clearing it disables HW actions on accessing above addresses. But ensure that no interrupts are possible while TE is disabled. The second way is to access above addresses by byte or half word operations only. The HW actions are only generated by word access. Disabling interrupts is not required in the latter case. 9.5.7. Critical Code Critical code is a sequence of instructions which must not be interrupted, because it modifies common data resources. Protection from being interrupted can be achieved by disabling interrupts during critical code. There are several ways of doing this: 9.5.7.1. ARM core's Interrupt Disable Flag I and F The ARM core itself provides the interrupt disable bits I and F in the program status register CPSR. The control bits of the CPSR (I, F and others) can be SW altered only when the processor is in a privileged mode. ARM recommends to modify the CPSR by a read-modifywrite instruction sequence in order to leave the reserved bits unchanged. MRS ORR MSR r0,cpsr r0,r0,#I_Bit cpsr_c,r0 ;disable interrupts 4. Returning to the interrupted routine has to be done by an instruction, which simultaneously writes the PC (R15) and CPSR with the values in R14 and SPSR (e.g. SUBS PC,R14_irq,#4). The interesting case is when an interrupt comes in during execution of the MSR instruction. The core commits to taking an interrupt before the instruction being executed completes. Therefore even though an MSR instruction may have written to the CPSR to disable interrupts, the interrupt will still be taken. A NOP between the MSR instruction and the first instruction of the critical code is not necessary. If an interrupt occurs during an MSR instruction, it will return to the instruction immediately following the MSR. 9.5.5. Default Vector 9.5.7.2. Global Enable Flag GE Any read access to vector table address [VTB] will deliver the default vector, but will not generate IAck as long as the comparator output is inactive or the priority output of the priority encoder is zero. Due to this the default vector ISR runs with the priority of the interrupted routine. This is the only ISR which could be interrupted by itself. As long as this default vector ISR is not programmed reentrant, interrupts should Protection of critical code can be achieved by disabling the nIRQ output with the global enable flag CRI.GE. The GE flag changes its value in the cycle after the data transfer of the store instruction. In this cycle the next instruction is in the execution stage of the CPU and will be executed. Due to this one NOP is required between the store instruction, which clears CRI.GE, and the first instruction of the critical code. 3. Generate the signal IExit by performing a word write by an STR instruction to the interrupt exit address at [VTB]+0x100. Micronas 69 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 9.5.7.3. Force Priority To protect critical code, further IRQ interrupts can be disabled by writing the maximum priority to the forced priority register AFP. Modifying AFP works like clearing the GE flag. One NOP is required between the store instruction, which writes AFP, and the first instruction of the critical code. 9.5.7.4. Disabling via ISN At last, critical code protection can be achieved by disabling all ISNs by clearing their enable flag E. The priority encoder is calculated at the beginning of a cycle. Due to this, changing an ISN register becomes effective only in the next cycle. Two NOPs are required between the store instruction, which clears the flag E, and the first instruction of the critical code. 9.5.8. Switching an Interrupt Vector Interrupt service routines of an interrupt source can easily be changed by entering the start address of the new ISR at the corresponding entry of the interrupt vector table. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 9.5.9. Switching the Vector Table It can be switched between different vector tables if they have been installed. Changing the vector table is simply done by writing the base address of the new vector table to register VTB. All subsequent interrupt service routines must relate to this vector table. Due to this, it is necessary for an ISR in such an environment, to read the location of the current vector table from register VTB before accessing it. Be careful when doing vector table switching within an ISR. Interrupted ISRs could try to do the IExit from an outdated table. 70 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 10. FIQ Interrupt Logic The FIQ Interrupt Logic selects one out of eight interrupt sources as the CPU's nFIQ input. An interrupt request is latched in a pending flag until it is cleared by SW. The output can be disabled. Features - Expanding nFIQ input of ARM7TDMI - 1 of 8 selection - IRQ or FIQ selectable 10.1. Functional Description Interrupt Sources All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CRF.SEL FIQ0 FIQ1 FIQ2 FIQ3 FIQ4 FIQ5 FIQ6 FIQ7 0 1 DB D Q 1 S Q DB CRF.GE nFIQ & CRF.P D to ISNs Fig. 10-1: Block Diagram FIQ At one time, only one interrupt source can be connected to the nFIQ input of the CPU. The interrupt source which is connected to the nFIQ, is disconnected from the corresponding ISN. This ISN can then be used by SW. SR1.FIQ reset R Q reset CRF Fig. 10-2: Reset Structure Figure 10-2 shows the reset structure. Registers can't be written until the FIQ flag in the standby register SR1 is set. 10.2. Registers PRF r/w This Flag is set by HW and SW. It must be cleared by SW before re-enabling FIQ by bit F in the core's CPSR register, or no further interrupt can occur. Pending Register FIQ 7 6 5 4 3 2 1 0 x x x x x x x P x x x x x x x 0 CRF P r/w1: r/w0: Micronas FIQ Pending Pending FIQ. No pending FIQ. Control Register FIQ Res r/w 7 6 5 4 GE x x x 0 x x x 3 2 1 0 0 0 SEL 0 0 Res 71 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 SEL r/w: Select FIQ Source (Table 10-1) Table 10-1: FIQ Source Selection SEL Switched to nFIQ 3 2 1 0 Select ISN Interrupt Source 0 x x x None 1 0 0 0 FIQ0 6 1 0 0 1 FIQ1 11 WAIT COMP 1 0 1 0 FIQ2 12 UART0 1 0 1 1 FIQ3 13 PINT2 1 1 0 0 FIQ4 15 CC2OR 1 1 0 1 FIQ5 17 Timer 2 1 1 1 0 FIQ6 19 I2C0 1 1 1 1 FIQ7 5 CAN0 SPI0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. GE Global Enable FIQ r/w1: Enable FIQ. r/w0: Disable FIQ. Disabling happens as soon as nFIQ is inactive. An active nFIQ will not be interrupted by clearing GE. 10.3. Principle of Operation 10.3.1. Reset Clearing standby register flag SR1.FIQ resets the FIQ Interrupt Logic (see Fig. 10-2 on page 71). The registers are reset to their mentioned values (see Section 10.2. on page 71) and cannot be modified. The nFIQ output is inactive. 10.3.2. Initialization Proper configuration of the interrupt sources in the peripheral modules has to be made prior to initialization of the FIQ Interrupt Logic. Initialization is possible after the standby register flag SR1.FIQ has been set. Now the registers can be modified by SW. But no interrupt request is generated to the CPU. The FIQ Interrupt Logic is operable in all CPU speed modes. 10.3.3. Operation Setting flag CRF.GE enables the FIQ Interrupt Logic. When an interrupt occurs, execution starts from address 0x1C. 10.3.4. Inactivation The FIQ Interrupt Logic can be disabled by clearing the global enable flag CRF.GE. An active nFIQ will be served, however, and only future FIQs will be suppressed by clearing the GE flag. Clearing the standby register flag SR1.FIQ immediately resets registers and logic and forces the nFIQ output to inactive. 72 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 11. Port Interrupts Port interrupts are the interface of the Interrupt Controller to the external world. Six U-Port pins and alternatively six PPort pins are connected to the module via their special input lines (Fig. 11-1). HW Option programmable multiplexers define which port signal is actually connected to the Trigger Mode Logic (Table 11-1). The P-Ports are actually analog input ports, thus Schmitt Triggers are enabled if the P-Ports are selected as port interrupts. The input sampling frequency is f0perm, which is not disabled by CPU SLOW or DEEP SLOW modes. HW Option PM.PINT 0 U1.7 1 PINT0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Module Name HW Options Initialization Item Address Item IPRM0 PINT0 Port Multiplexers PM.PINT PINT0 U1.7 special in PINT0 Interrupt Source Setting P1.2 PINT1 PINT1 Trigger Mode P1.3 U1.5 Table 11-1: Module specific settings f0perm P1.2 U1.6 Trigger is enabled. This is the reason why input levels other than ground or digital supply may cause quiescent currents in the Schmitt Trigger circuit and thus lead to higher power consumption. PINT2 PINT1 Interrupt Source PINT1 U1.6 special in P1.3 PINT2 PINT2 U1.5 special in P1.4 PINT2 Interrupt Source PINT3 PINT3 U8.5 special in P1.5 P1.4 PINT4 U8.5 PINT3 PINT3 Interrupt Source P1.5 PINT4 U0.5 special in P1.6 PINT5 PINT5 U0.4 special in P1.7 U0.5 PINT4 IPRM1 Trigger Mode P1.6 PINT4 Interrupt Source IRPM0 7 U0.4 PINT5 PINT5 Interrupt Source r/w Interrupt Port Mode Register 0 6 5 PIT3 0 4 3 PIT2 0 0 2 1 PIT1 0 0 0 PIT0 0 0 0 Res P1.7 Fig. 11-1: Port Interrupts The user can define the trigger mode for each port interrupt by the interrupt port mode register. The Trigger Mode defines on which edge of the interrupt source signal the Interrupt Controller is triggered. The triggering of the Interrupt Controller is shown in figure 11-2. IRPM1 r/w Interrupt Port Mode Register 1 7 6 5 4 x x x x x x x x 3 2 1 PIT5 0 0 PIT4 0 0 0 Res For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). Precautions Parallel usage of a P-Port as analog and port interrupt input is possible but not recommended. In this case the Schmitt Micronas 73 PITn Trigger Mode 0h Interrupt source is disabled 1h Rising edge 2h Falling edge 3h Rising and falling edges Interrupt (low active) Falling edge Interrupt (low active) Rising edge Interrupt (low active) Falling and rising edge trigger mode Fig. 11-2: Interrupt Timing 74 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 PITn Port interrupt trigger number n This field defines the trigger behavior of the associated port interrupt (Table 11-2). Table 11-2: PITn usage port input CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 12. Ports This chapter describes the P-, U- and H-Ports. The analog input ports, P0 and P1, serve as input for the analog to digital converter and may be used as digital inputs. P2 may be used as digital input, only. The universal ports U0 to U8 serve as digital I/O and can be configured as LCD drivers. The high current ports H0 to H7 serve as digital I/O and can be configured as stepper motor drivers. 12.1. Analog Input Port The 16 pin analog input port is composed of ports P0 and P1. All port pins can be configured as digital input. P0.6 is connected to a comparator, which may be selected as interrupt source. P1.2 to P1.7 can be used as port interrupts. The 2-pin port P2 solely serves as digital input. Features - 16 pin analog input multiplexer. - 18 pins configurable as digital input ports. - Schmitt hysteresis digital input buffer, CMOS level (2.5V) or Automotive level (3.3V) selectable. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. - 6 pins configurable as port interrupts. 8 P0.0 to P0.7 8 P1.0 to P1.7 P0.6 to Alarm Comparator 8 16:1 MUX 8 To A/D converter 2 P2.0 to P2.1 P1.2 to P1.7 to port interrupts 0 to 5 18 PxPIN.Py PxLVL.Ay PxIE.Iy rd Fig. 12-1: P-Ports with Input Multiplexer and P0.6 Alarm Comparator P0 and P1 analog input lines are connected to a multiplexer. The output of this multiplexer is connected to the 10-bit A/D converter. Port P0.6 is, in addition, the input of the P0.6 Alarm Comparator, described in the chapter on the Analog Section. P0 and P1 pins may alternatively, P2 may exclusively be used as digital input if enabled by setting the individual pin's enable flag PxIE.Iy. CMOS or Automotive Schmitt trigger input level may individually be selected by writing registers PxLVL. The digital value of the input pins is obtained by reading registers PxPIN. Disabled inputs read as 1. Pins should either be used as analog or digital inputs, not both at the same time. Six of the analog input pins (P1.2 to P1.7) may be used as port interrupt input if selected by HW Option PM.PINT (see sections "Port Interrupts" and "HW Options" for more details). Configure as digital input for this operation. P0 to 7 r: PxLVL r/w Port x Input Level Register 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 A0 to 7 r/w1: r/w0: Port x Pin Register Res Automotive Flag 0 to 7 Schmitt trigger input level is Automotive Schmitt trigger input level is CMOS PxIE r/w PxPIN Pin Data 0 to 7 Read Pin state Port x Input Enable Register 7 6 5 4 3 2 1 0 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 Res I r 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 1 1 1 1 1 1 1 1 Micronas I0 to 7 r/w1: r/w0: Digital Input Enable 0 to 7 Enable input buffer Disable input buffer Res 75 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 12.2. Universal Ports U0 to U8 Universal Ports are pin-configurable as SW I/O port, Special Input/Output port (SI/SO) to special internal hardware modules or direct drive of 4:1 multiplexed LCD segment and backplane lines (LCD port). Features The output drivers feature a current fold-back characteristic to allow shorting the output and to improve EMI performance. - PORT mode: push-pull or open-drain output. - Pin-configurable as I/O or Special Port or LCD driver. - LCD mode: 1:4 multiplex, 5V supply. - Two output current fold-back characteristics selectable - Schmitt hysteresis input buffer, CMOS level (2.5V) or Automotive level (3.3V) selectable. UxMODE.Ly UVDD Special In UxPIN.Py UxLVL.Cy UxSLOW.Sy UxTRI.Ty UxD.Dy Special Out UxNS.Sy UVSS 0 1 & 1 From LCD Current Fold Back 0 1 Current Fold Back Ux.y UVSS UxDPM.Dy Analog Switch and Segment Driver MUX 2/ 3UVDD 1/ 3UVDD x: Port number 0 to 8 y: Port pin number 0 to 7 Fig. 12-2: Universal Port Pin Circuit Diagram The Universal Port pins can be configured for several basic operating modes (Table 12-1) Table 12-1: Universal Port basic Operating Modes Modes Port Mode LCD Mode Function Normal Input The SW uses the port as digital input. Special Input The port input is additionally connected to specific hardware modules. Normal Output The SW uses the port as latched digital tristateable output. Special Output The output signals of specific hardware modules are directly port output source. The port pin serves as backplane/segment driver for a 4:1 multiplexed LC display See the chapter on Pinning for information about specific hardware module connections to individual port pins for Special Input and Special Output purposes. After reset, all Universal Ports are in Port, Normal, tristate, CMOS input level condition. SLOW mode is disabled. Universal Port control is distributed among eight registers. Four of these registers have duplicate functions for Port and LCD mode. All register bits corresponding to one U-Port pin are controlled by the same bus bit. 12.2.1. Port Mode For Port mode, the respective UxMODE register bit has to be cleared for mode selection. In both LCD and Port modes, the SLOW mode may be defined for each individual U-Port pin. It reduces the current drive capability of the output stage. Set flag SR0.PSLW to enable this operation mode. 76 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. UVDD CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The function of the seven remaining registers is given in Table 12-2. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Table 12-2: Register Functions in Port Mode The output sequence timing on backplane and segment output ports in LCD Mode is controlled by the LCD module. Please refer to section LCD Module for information about operation of this module. As generation of the backplane port output sequence is fully done by the LCD module, no segment line data setting is necessary for these ports. Register Function UxD r/w Data register UxTRI enable/disable output 12.2.3. Port Fast and Slow Modes UxNS select Data register or specific hardware module as output source Once individual port pins have been enabled for Port Slow mode by setting registers UxSLOW, set flag SR0.PSLW to simultaneously enter this mode in all respective ports. UxDPM select push-pull or open-drain, double drive mode for output drivers UxSLOW enable/disable Port Slow mode for output drivers UxLVL select CMOS or Automotive Schmitt trigger input level UxPIN read pin state In Port Mode, the Special Input path is always operative. This allows manipulating the input signal to the specific hardware module through Normal Output operations by software. Because register UxPIN allows reading the pin level also in Special Output mode, the output state of the specific hardware module may be read by the CPU. All U-Ports exhibit two operating regions in the DC output characteristic (see Fig. 12-3). Near zero output voltage the internal driver transistors operate non-limited, to offer a linear, low on-resistance. With larger output voltages, however, the output current folds back to a a limited value. This measure helps to fight supply current transients and related EMI noise during port switching. In the fold-back region, Port Fast mode and Port Slow mode select two different current limits Ishf and Ishs. Port Slow mode sets a limit where the output may even be shorted continuously to either supply rail. Thus, wired-or configurations may be realized. The external load resistance should be greater than 5kOhms in Port Slow mode. For actually switching to Port Slow mode, both registers UxSLOW and SR0.PSLW have to be set. In all other cases, Port Fast mode is selected. It is recommended to place all LCD ports in Port Slow mode. 12.2.2. LCD Mode For LCD Mode, the respective UxMODE register bit has to be set for mode selection. Io Nonlimited region The function of the seven remaining registers is given in Table 12-3. Limited region Table 12-3: Register Functions in LCD Mode Register Function UxD r/w phase 0 segment line data UxTRI r/w phase 1 segment line data UxNS r/w phase 2 segment line data UxDPM r/w phase 3 segment line data UxSLOW enable/disable Port Slow mode for output drivers UxLVL no function UxPIN no function By writing segment line data registers, only a master is changed. Any write to global register ULCDLD will transfer all master settings to the respective slaves and thereby change the LC display in one instant. Ishf Port Fast Mode Ishs Port Slow Mode 0 1V 2V 3V 4V 5V Vol Fig. 12-3: Typical U-Port pull-down DC output characteristic (pull-up characteristic is complementary). Registers UxD, UxTRI, UxNS and UxDPM compose a wordaligned 32bit register and may be accessed by one 32bit operation. Micronas 77 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 12.3. Universal Port Registers Eight U-Port registers are basically available for 9 U-Ports U0 to U8, each. Because some U-Ports are less than 8 pins wide, not all of the described bits are available for every port. Furthermore, the respective device's pinning may require a reduction in available U-Ports. See the respective pinning table for details. UxNS Universal Port x Normal-Special / Segment 2 Register 7 6 5 4 3 2 1 0 r/w S7 S6 S5 S4 S3 S2 S1 S0 Port r/w SG7_2 SG6_2 SG5_2 SG4_2 SG3_2 SG2_2 SG1_2 SG0_2 LCD 0 0 0 0 0 0 0 0 Res The general U-Port register model is given below. r/w Universal Port Mode Register 7 6 5 4 3 2 1 0 L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 0 S0 to 7 r/w1: r/w0: Normal/Special Mode Flag 0 to 7 Special Mode. Special hardware drives pin. Normal Mode. Data latch drives pin. Res UxDPM L0 to 7 Port Mode Flag Select the mode of the corresponding port pins. r/w1: Port pin is in LCD mode. r/w0: Port pin is in Port mode. UxD 7 6 5 4 3 2 1 0 r/w D7 D6 D5 D4 D3 D2 D1 D0 Port r/w SG7_3 SG6_3 SG5_3 SG4_3 SG3_3 SG2_3 SG1_3 SG0_3 LCD 0 0 0 0 0 0 0 0 Res Universal Port x Data / Segment 0 Register D0 to 7 r/w1: 7 6 5 4 3 2 1 0 r/w D7 D6 D5 D4 D3 D2 D1 D0 Port r/w SG7_0 SG6_0 SG5_0 SG4_0 SG3_0 SG2_0 SG1_0 SG0_0 LCD 0 0 0 0 0 0 0 0 Res D0 to 7 w: r: SG0_0 to 7_3 Segment Data Latch w: Write latch. r: Read latch. In LCD mode, U-Port registers UxD, UxTRI, UxNS and UxDPM store LCD segment information. Segment register bits UxY.SGm_n contain the information for segment line m during phase n, which controls segment m_n. Thus, register bits UxD.SG0_0, UxTRI.SG0_1, UxNS.SG0_2 and UxPIN.SG0_3 contain the complete information for segment line 0 in U-Port x. r/w0: All U-Port pins may be switched into a Double Pull-down Mode (DPM) by setting the appropriate DPMx flag, where - the output configuration is pull-down, not the standard push-pull. By these means these ports may be configured to operate as connection to a wired-or, single-wire bus (e.g. DIGITbus or I2C) with external pull-up resistor. UxSLOW r/w Please refer to Pin Assignment and Description for segment/ pin number assignment. Information about the usage of the LCD Segment field will be found at the functional description of the LCD Module. Universal Port x Tristate / Segment 1 Register 7 6 5 4 3 2 1 0 r/w T7 T6 T5 T4 T3 T2 T1 T0 Port r/w SG7_1 SG6_1 SG5_1 SG4_1 SG3_1 SG2_1 SG1_1 SG0_1 LCD 1 1 1 1 1 1 1 1 Res 78 Output Tristate Flag 0 to 7 Output driver is disabled (tristate) Output driver is enabled Universal Port x Slow Mode Register 7 6 5 4 3 2 1 0 S7 S6 S5 S4 S3 S2 S1 S0 0 0 0 0 0 0 0 0 S0 to 7 r/w1: r/w0: Universal Port x Input Level Register 7 6 5 4 3 2 1 0 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 A0 to 7 r/w1: r/w0: Res Slow Flag 0 to 7 Output driver is in Port Slow mode Output driver is in Port Fast mode UxLVL r/w T0 to 7 r/w1: r/w0: Double Pull-Down Mode Output driver is pull-down, Ishs (Port Slow mode) doubled. Standard. - the short circuit current Ishs is doubled (with Port Slow Mode enabled for these ports, and SR0.PSLW set to 1) Data Latch Write latch. Read latch. UxTRI Universal Port x Double Pull-Down Mode / Segment 3 Register Res Automotive Flag 0 to 7 Schmitt trigger input level is Automotive Schmitt trigger input level is CMOS Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. UxMODE CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 UxPIN r Universal Port x Pin Register 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 x x x x x x x x P0 to 7 r: Pin Data 0 to 7 Read Pin state. ULCDLD 7 w LCDSLV 0 Res Universal Port LCD Load Register 6 5 4 3 2 1 0 x x x x x x x 0 0 0 0 0 0 0 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. LCDSLV LCD Module is Slave Select the mode of the LCD module. w1: LCD module is slave. w0: LCD module is master. A write access to this memory location simultaneously loads all segment information of all U-Ports in LCD mode to the display. The flag LCDSLV is available only in LCD mode. 12.3.1. Special Register Layout of U-Port 4 U4.0 to U4.3 provide backplane signals in LCD Mode. To operate any ports as LCD segment driver it is necessary to switch all these ports to LCD mode. This has to be done by setting flags U4MODE.L0 through U4MODE.L3. As backplane ports U4.0 to U4.3 require no segment data setting, SG0_0 through SG3_3 bits are not available in U4 registers. Micronas 79 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 12.4. High Current Ports H0 to H7 Features High Current Ports 0 to 7 are used to drive coils of stepper motors. All ports are 4 pins wide to facilitate control of individual stepper motors. The H-Ports are similar to universal ports but as the name says, they can drive higher currents. H-Ports can be operated by software like Universal Ports (Port Mode). Their Special Out inputs are connected to the stepper motor module or to PWM outputs. - Pin-configurable as I/O or Special Port driver - 30mA output current - Schmitt hysteresis input buffer, CMOS level (2.5V) or Automotive level (3.3V) selectable. - Reduced slew rate of current and voltage for driving resistive, capacitive or inductive loads. HVDD Special In HxPIN.Py HxLVL.Cy x: Port number 0 to 7 y: Port pin number 0 to 3 HVSS HVDD 0 1 & Slew Rate Control & Slew Rate Control Hx.y HVSS Fig. 12-4: High Current Port Pin Circuit Diagram The H-Port pins can be configured for several basic operating modes (Table 12-4) The function of the five registers is given in Table 12-5. Table 12-5: Register Functions Table 12-4: High Current Port basic Operating Modes Mode Function Normal Input The SW uses the port as digital input. Special Input The port input is additionally connected to specific hardware modules. Normal Output The SW uses the port as latched digital tristateable output. Special Output The output signals of specific hardware modules are directly port output source. See the chapter on Pinning for information about specific hardware module connections to individual port pins for Special Input and Special Output purposes. Register Function HxD r/w Data register HxTRI enable/disable output HxNS select Data register or specific hardware module as output source HxLVL select CMOS or Automotive Schmitt trigger input level HxPIN read pin state The Special Input path is always operative. This allows manipulating the input signal to the specific hardware module through Normal Output operations by software. Because register HxPIN allows reading the pin level also in Special Output mode, the output state of the specific hardware module may be read by the CPU. H-Port control is distributed among five registers. All register bits corresponding to one H-Port pin are controlled by the same bus bit. Two high current ports together with a coil build a H-bridge. Two H-bridges are necessary to operate a stepper motor. After reset, all H-Ports are in Normal, Output, Low, CMOS input level condition. The n-channel and the p-channel transistor of the output driver are controlled separately, to eliminate crossover currents. The reset output levels of the ports are low to avoid floating coils. 80 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. HxTRI.Ty HxD.Dy Special Out HxNS.Sy CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 12.5. High Current Port Registers Five H-Port registers are basically available for 8 H-Ports H0 to H7, each. But the respective device's pinning may require a reduction in available H-Ports. See the respective pinning table for details. P0 to 3 r: Pin Data 0 to 3 Read Pin state. The general H-Port register model is given below. HxD r/w High Current Port x Data Register 7 6 5 4 3 2 1 0 x x x x D3 D2 D1 D0 x x x x 0 0 0 0 D0 to 3 w: r: Data Latch Write latch. Read latch. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. HxTRI r/w High Current Port x Tristate Register 7 6 5 4 3 2 1 0 x x x x T3 T2 T1 T0 x x x x 0 0 0 0 T0 to 3 r/w1: r/w0: High Current Port x Normal/Special Register 7 6 5 4 3 2 1 0 x x x x S3 S2 S1 S0 x x x x 0 0 0 0 S0 to 3 r/w1: r/w0: High Current Port x Input Level Register 7 6 5 4 3 2 1 0 x x x x A3 A2 A1 A0 x x x x 0 0 0 0 A0 to 3 r/w1: r/w0: High Current Port x Pin Register 7 6 5 4 3 2 1 0 x x x x P3 P2 P1 P0 x x x x 0 0 0 0 Micronas Res Automotive Flag 0 to 3 Schmitt trigger input level is Automotive Schmitt trigger input level is CMOS HxPIN r Res Normal/Special Mode Flag 0 to 3 Special Mode. Special hardware drives pin. Normal Mode. Data latch drives pin. HxLVL r/w Res Output Tristate Flag 0 to 3 Output driver is disabled (tristate) Output driver is enabled HxNS r/w Res Res 81 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 82 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 13. AVDD Analog Section The Analog Section operates from the AVDD supply pin and comprises the PLL/ERM module, the ADC, the P06 and the WAIT Comparators. In addition it contains support circuits like the VREFINT Generator, the BVDD Regulator and the necessary biasing circuits. Fig. 13-1 gives an overview. External Internal components components VREFINT 2k AVDD 2.5V 2% en VREFINT Generator AVSS bvdd_err ANAA.BVE err +12V en + - BVDD BVDD Regulator WAIT All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 2.5V + WAITH en ANAA.WAIT & WAIT COMP Interrupt Source & P06 COMP Interrupt Source WAIT Comp. fIO ANAA.EP06 P06 SR0.ADC en + R R ANAA.P06 P06 Comp. 1 RESETQ SR1.CPUM = 1, 3, 7 en 1 VREF, VREF0, VREF1 ADC PLLC.PMF > 0 en lck pll_lock PLL/ERM Fig. 13-1: AVDD Section Table 13-1: Activation of AVDD Analog Section modules CPU Mode VREFINT Gen. PLL/ERM and BVDD Regulator ADC, P06, WAIT RESET on off off FAST, PLL and PLL2 modes on on if PLLC.PMF > 0 on if SR0.ADC=1 SLOW and DEEP SLOW modes on if PLLC.PMF > 0 or SR0.ADC=1 Micronas 83 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 13.1. VREFINT Generator The VREFINT Generator generates bias signals which are necessary for the operation of all Analog-Section modules. Furthermore, it produces a tightly controlled reference voltage VREFINT, that is delivered to the BVDD Regulator and the WAIT Comparator. Via a decoupling resistor it also is routed to the VREFINT pin. The VREFINT-pin voltage, which has to be buffered externally by a 10-nF ceramic capacitor, is input to the ADC as alternative, internally generated, reference voltage. This module is permanently enabled during reset, in the CPU modes FAST, PLL and PLL2, and whenever SR0.ADC or PLLC.PMF is not 0. A certain set-up time has to elapse after enabling the module for VREFINT to stabilize. No resistive load must be connected to the VREFINT pin. The BVDD Regulator generates the 2.5-V BVDD supply voltage for the internal PLL/ERM module from the 5-V AVDD. It derives its reference from the VREFINT Generator. This module is permanently enabled whenever PLLC.PMF is not 0. A certain set-up time has to elapse after enable for BVDD to stabilize. BVDD must be buffered externally by a 150-nF ceramic capacitor. An overload condition in the regulator (current or voltage drop-out) is stored in flag ANAA.BVE. The immediate overload signal may be routed to the LCK special output by selection in field ANAU.LS (UVDD Analog Section). 13.3. Wait Comparator The level on pin WAIT is compared to the internal reference VREFINT. The state of the comparator output is available as flag ANAA.WAIT and as WAIT Comparator interrupt source. Furthermore, the output is available on pin WAITH, so that the hysteresis of this comparator can be set with an external positive-feedback resistor (100kOhms min.). After reset, the module is off (zero standby current). The module is enabled by setting flag SR0.ADC, together with the P0.6 Comparator and the ADC. If the VREFINT Generator is powered up as well (cf. Table 13-1), the user has to assure that the necessary VREFINT set-up time has elapsed, before using comparator results (flag and interrupt). The interrupt source output is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The WAIT Comparator interrupt source toggles with fIO, to generate interrupts as long as the level on pin WAIT is lower than the internal reference. 13.4. P0.6 Comparator The level on port P0.6 is compared to AVDD/2. The comparator features a small built-in hysteresis. The state of the comparator output is available as flag ANAA.P06 and as P0.6 Comparator interrupt source. The P0.6 Comparator interrupt source toggles with fIO, to generate interrupts as long as the level on pin P0.6 is lower than the internal reference. After reset, the module is off (zero standby current). The module is enabled by setting flag SR0.ADC, together with the WAIT Comparator and the ADC. If the VREFINT Generator is powered up as well (cf. Table 13-1), the user has to assure that the necessary VREFINT set-up time has elapsed, before using comparator results (flag and interrupt). The interrupt source output, which must be enabled by setting flag ANAA.EP06, is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. 84 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 13.2. BVDD Regulator CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 13.5. PLL/ERM The PLL and ERM modules are operated on the internally generated 2.5V BVDD supply voltage. For details on operating this module please refer to section "CPU and Clock System". 13.6. A/D Converter (ADC) The Analog to Digital Converter allows the conversion of an analog voltage ranging from AVSS to either one of three external references VREF, VREF0, VREF1 (2.5 to 5V) or the internal reference VREFINT (~2.5V), to a 10-bit digital value. A multiplexer connects one of 16 analog input ports to the ADC. A sample and hold circuit holds the analog voltage during conversion. The duration of the sampling time is programmable. - 16 channel input multiplexer. - Input buffering for high ohmic sources selectable. - Sample and hold circuit. - 4/8/16/32s conversion selectable for optimum throughput/accuracy balance. - 2.5V internal reference (VREFINT) or 2.5 to 5V external references (VREF, VREF0, VREF1) selectable Features - 10-bit resolution. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. - Successive approximation, charge balance type. - Zero standby current 2 AD0.REF VREF VREFINT VREF0 MUX VREF1 AVDD P0.0 P0.1 P0.2 P0.3 AD1.BUF P0.4 P0.5 Buf P0.6 P0.7 P1.0 1 0 MUX S&H A 10 D AD0.EOC 2 P1.1 P1.2 P1.3 ADx.AN0 to AN9 Bypass ADC-Block en AD0.TSAMP SR0.ADC P1.4 P1.5 P1.6 P1.7 AVSS 4 AD0.CHANNEL Fig. 13-2: ADC Block Diagram 13.6.1. Principle of Operation After reset, the module is off (zero standby current). The module is enabled by setting flag SR0.ADC. The user has to Micronas assure that the necessary VREFINT-set-up time has elapsed. Before starting a conversion, select input-buffer usage or bypass with flag AD1.BUF. Note that the input buffer requires 85 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Before starting a conversion, check flag AD0.EOC to be set. A conversion is started by a write access to register AD0, selecting sample time (AD0.TSAM), reference source (AD0.REF) and input channel (AD0.CHANNEL). Sampling starts one f0 clock cycle after completion of the write access to AD0. Flag AD0.EOC signals the end of conversion. The 10-bit result is stored in the registers AD1 (8 MSB) and AD0. The conversion time depends on f0 and the programmed sample time (Table 13-2). For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 13.6.1.1. Conversion Law The result of A/D conversion is described by the following formula: U In DV = INT -------------- 1LSB where has to make sure that at the end of this sampling period, the voltage on the sampling capacitance is within 0.1 LSB from the source voltage. Measurement errors may occur, when the voltage of highimpedance sources has to be measured: - To reduce these errors, the sampling time may be increased by programming the field AD0.TSAMP. - In cases where high-impedance sources are only rarely sampled, a 100nF capacitor from the input to AVSS is a sufficient measure to ensure that the voltage on the sampling capacitance reaches the full source voltage, even with the shortest sampling time. - In some high-impedance applications a charge-pumping effect may noticeably influence the measurement result: Charge pumping from a high-potential to a low-potential source will occur when such two sources are measured alternatingly. This results in a current that appears as flowing from the high-potential source through the IC into the low-potential source. This current explains from the fact that during the respective sampling period the highpotential source always charges the sampling capacitance, while the low-potential source always discharges it. Usage of the input buffer (AD1.BUF) substantially reduces this effect. U Ref 1LSB = ----------1024 DV = Digital Value; INT = Integer part of the result DV 3FF 3FE 3FD 03 02 01 00 1 2 3 1021 1023 UIn [LSB] Fig. 13-3: Characteristic Curve The voltage on the reference-input pins VREF, VREF0 and VREF1 may be set to any level in the range from AVSS to AVDD. However, accuracy is only specified in the range from 2.56V (1 LSB = 0.25mV) to 5.12V (1 LSB = 0.5mV). 13.6.1.2. Measurement Errors The result of the conversion mirrors the voltage potential of the sampling capacitance (typically 8pF) at the end of the sampling time. This capacitance has to be charged by the source through the source impedance within the samplingtime period. To avoid measurement errors, system design 86 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. a 1us setup time before usage. When the buffer is never used, leave flag AD1.BUF cleared. When the buffer is always used, leave this flag set. When toggling buffer usage, set this flag at least 1us before starting a conversion. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 13.7. Registers AD0 r register AD0. The result is available until a new conversion is started. ADC Register 0 7 6 5 4 3 2 1 0 EOC x x x x TEST AN1 AN0 w TSAMP 0 REF 0 0 CHANNEL 0 0 0 0 0 BUF w1: w0: Input Buffer Usage Buffer used Buffer bypassed TEST for factory use only Res ANAA AD1 6 5 4 3 2 1 0 EP06 P06 WAIT x x x x BVE ADC Register 1 7 6 5 4 3 2 1 0 r AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 w x x x x x x x BUF r/w Analog AVDD Register 7 0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 0 EP06 Res EOC End of Conversion r1: End of conversion r0: Busy EOC is reset by a write access to the register AD0. EOC must be true before starting the first conversion after enabling the module by setting SR0.ADC. TSAMP Sampling Time TSAMP adjusts the sample conversion times. Table 13-2: TSAMP Usage: Sample and Conversion Time TSAMP tSample tConversion 0H 20/f0 40/f0 1H 60/f0 80/f0 2H 140/f0 160/f0 3H 300/f0 320/f0 REF w0: w1: w2: w3: 0 Res r/w1: r/w0: Enable P06 Comparator Interrupt Source output Enabled. Disabled. P06 r1: r0: P06 Comparator Output P0.6 is lower than AVDD/2. P0.6 is higher than AVDD/2. WAIT r1: r0: WAIT Comparator Output WAIT is lower than VREFINT. WAIT is higher than VREFINT. BVE r1: r0: w1: w0: BVDD Regulator Error Flag Out of specification. Normal operation. Reset flag. No action. Conversion Reference External reference from VREF pin used Internal reference on VREFINT pin used External reference from VREF0 pin used External reference from VREF1 pin used CHANNEL Channel of Input Multiplexer CHANNEL selects from which pin of port P0 or P1 the conversion is done. The MSB of CHANNEL is bit 3. Table 13-3: CHANNEL Usage: ADC Input Selection CHANNEL Port Pin 0 to 7 P0.0 to P0.7 8 to 15 P1.0 to P1.7 AN 9 to 0 Analog Value Bit 9 to 0 The 10-bit data format is positive integer, i.e. 000H for lowest and 3FFH for highest possible input signal. The 8 MSB can be read from register AD1. The two LSB can be read from Micronas 87 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 88 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 14. Timers (TIMER) Five general purpose timers are implemented. T0 is a 16 bit timer, T1 to T4 are 8 bit timers. 14.1. Timer T0 Timer T0 is a 16bit auto reload down counter. It serves to deliver a timing reference signal to the ICU, to output a frequency signal or to produce time stamps. Features - 16bit auto reload counter - Time value readable - Interrupt source output - Frequency output All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. TIM 0 w Reload-reg. clk HW Option r 16 16 bit Auto-reload Down counter TIM 0 T0 Interrupt Source underflow 1/2 T0-OUT Fig. 14-1: Timer T0 Block Diagram 14.1.1. Principle of Operation 14.1.1.1. General The timer's 16bit down-counter is clocked by the input clock and counts down to zero. One clock count after reaching zero, it generates an output pulse, reloads with the content of the TIM0 reload register and restarts its travel. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 14.1.1.2. Operation The clock input frequency is settable by HW option (see Table 14-1 on page 90). Prior to entering active mode, proper SW initialization of the U-Ports assigned to function as T0-OUT outputs has to be made (Table 14-1). The ports have to be configured Special Out. Refer to "Ports" for details. On reaching zero, the counter generates a reload signal, which can be used to trigger an interrupt. The same signal is connected to a divide by two scaler to generate the output signal T0-OUT with a pulse duty factor of 50%. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. The state of the down-counter is readable by reading the 16bit register TIM0, low byte first. Upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. Thus, for time stamp applications, read consistency between low and high byte is guaranteed. 14.1.1.3. Precautions Use 8bit load/store operations to access Timer 0 register rather than 16bit access. T0 is always active (no standby mode). After reset the timer starts counting with reload value 0xFFFF generating a maximum period output signal. A new time value is loaded by writing to the 16bit register TIM0, high byte first. Upon writing the low byte, the reload register is set to the new 16bit value, the counter is reset, and immediately starts down-counting with the new value. Micronas 89 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 14-1: Module specific settings Module Name HW Options T0 Initialization Enable Bit Item Address Item Setting Input clock T0C T0-OUT output U1.2 special out 14.1.2. Registers TIM0L 6 5 4 3 2 1 r Read low byte of down-counter and latch high byte w Write low byte of reload value and reload down-counter 1 1 1 TIM0H 7 1 1 1 1 1 2 1 0 1 1 Res T0 high byte 6 5 4 3 r Latched high byte of down-counter w High byte of reload value 1 0 1 1 1 1 1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 7 T0 low byte Res TIM0 has to be read low byte first and written high byte first. Table 14-2: Reload Register Programming Reload value Output interrupt source frequency is divided by Output T0-OUT is divided by 0x0000 1 2 0x0001 2 4 0x0002 3 6 : : : 0xFFFF 65536 131072 90 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 14.2. Timer T1 to T4 Timer T1 to T4 are 8bit auto reload down counters. They serve to deliver timing reference signals to the ICU or to output frequency signals. Table 14-3 describes implementation specific HW Option addresses and enable flags of T1 to T4. Features - 8bit auto reload counter - Interrupt source output - Frequency output TIMx Reload-reg. w 0 clk HW Option 8 1 0 8 bit Auto-reload Down counter underflow 1 Tx Interrupt Source All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. enable 1/2 1 Tx-OUT 0 Fig. 14-2: Timer T1 to T4 Block Diagram 14.2.1. Principle of Operation 14.2.1.1. General The timer's 8bit down-counter is clocked by the input clock and counts down to zero. One clock count after reaching zero, it generates an output pulse, reloads with the content of the TIMx reload register and restarts its travel. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). On reaching zero, the counter generates a reload signal, which can be used to trigger an interrupt. The same signal is connected to a divide by two scaler to generate the output signal Tx-OUT with a pulse duty factor of 50%. The interrupt source output of this module may be but must not be connected to the interrupt controller. Please refer to section Interrupt Controller. Returning Tx to standby mode by resetting its respective enable bit will halt its counter and will set its outputs LOW. The register TIMx remains unchanged. The state of the down-counter is not readable. 14.2.1.2. Operation The clock input frequencies are settable by HW options (see Table 14-3 on page 92). After reset, the 8bit timer is in standby (inactive). Prior to entering active mode, proper SW initialization of the U-Ports assigned to function as Tx-OUT outputs has to be made (Table 14-3). The ports have to be configured Special Out. Refer to "Ports" for details. To initialize a timer, reload register TIMx has to be set to the desired time value, still in standby mode. For entering active mode, set the corresponding enable bit in the standby registers (see Table 14-3 on page 92). The timer will immediately start counting down from the time value present in register TIMx. During active mode, a new time value is loaded by simply writing to register TIMx. Upon writing, the counter is reset, and immediately starts counting down from the new time value. Micronas 91 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 14-3: Module specific settings Module Name HW Options Initialization Enable Bit Item Address Item Setting T1 Input clock T1C T1-OUT output U1.1 special out SR0.TIM1 T2 Input clock T2C T2-OUT output U1.0 special out SR0.TIM2 T3 Input clock T3C T3-OUT output U0.7 special out SR0.TIM3 T4 Input clock T4C T4-OUT output U0.6 special out, PM.U06 = 0 SR0.TIM4 14.2.2. Registers TIMx 7 Timer x 6 5 3 2 1 0 0 0 0 Reload value 0 0 0 0 0 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. w 4 Table 14-4: Reload Register Programming Reload value Output interrupt source frequency is divided by Output Tn-OUT is divided by 0x00 1 2 0x01 2 4 0x02 3 6 : : : 0xFF 256 512 92 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 15. Pulse Width Modulator (PWM) Features A PWM is an auto reload down-counter with fixed reload interval. It serves to generate a frequency signal with variable pulse width or, with an external low pass filter, as a digital to analog converter. - Two 8bit or one 16bit pulse width modulator - Wide range of HW option selectable cycle frequencies This module is combined of two independently operatable 8bit PWMs which can be combined to a single 16bit PWM. The number of PWMs implemented is given in table 15-1. The "x" in register names distinguishes the module number and can be 1, 3, 5, 7, 9, 11. PWMx-1 8 LSB PxP PxC period clock HW Option S Q R 1 PWMx-1 0 1 clk load All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. PWMx 8 MSB en clk load ovf 8bit down counter 1 1 0 en ovf 8bit down counter S Q R 1 PWMx 0 0 SR1.PWMx 1 x = 1, 3, 5, 7, 9, 11 PWMC.P16x Fig. 15-1: PWM Block Diagram 15.1. Principle of Operation 15.1.1. General 15.1.3. Initialization A PWM's down-counter is clocked by its input clock and counts down to zero. Reaching zero, it stops and sets the output to LOW. A period input pulse reloads the counter with the content of the PWM register, restarts it and sets the output to HIGH. Prior to entering active mode, proper SW initialization of the H-Ports and U-Ports assigned to function as PWMx outputs has to be made (Table 15-1). The ports have to be configured Special Out. Refer to "Ports" for details. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). It has to be decided which PWM module shall work as one 16bit or as two 8bit PWMs. Selection has to be done via the PWM control register PWMC as long as the PWM module is disabled. 15.1.2. Hardware settings 15.1.4. Operation The clock and period input frequencies are settable by HW option (Table 15-1). There is one common source for both 8bit PWMs, one for clock and one for period, thus clock and period are not independently selectable for the two 8bit PWMs. For full resolution a clock to period frequency ratio of 256 (65536 in 16bit mode) is recommended. Should other ratios be used, make sure that the combination of clock, period and pulse width setting allow the PWM to generate an output signal with a LOW transition. After reset, a PWM is in standby mode (inactive) and the output signal PWMx is LOW. Some of the PWM outputs share pins with outputs of other modules. The output multiplexer is controlled by HW option (Table 15-1). During active mode, a new pulse width value is set by simply writing to the register PWMx. Upon the next subsequent input pulse on its period input the PWM will start producing an output signal with the new pulse width value, starting with a HIGH level. Micronas For entering active mode, select the desired mode (8-/16bit mode) and then set the respective enable bit (Table 15-1). Then write the desired pulse width value to register PWMx (write low byte first in 16bit mode). Each PWM will start producing its output signal immediately after the next subsequent input pulse on its period input. 93 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 15-1: Module specific settings PWM1 PWM3 PWM5 PWM7 PWM9 PWM11 HW Options Initialization Enable Bit Item Address Item Setting Clock and period P1C, P1P PWM0 U0.3 special out H0.3 SMG/PWM1 output multiplexer PM.H0 PWM1 U0.2 and/or H0.3 special out Clock and period P3C, P3P PWM2 U0.1special out H0.2 SMG/PWM3 output multiplexer PM.H0 PWM3 U0.0 and/or H0.2 special out Clock and period P5C, P5P H7.3 SME/PWM4 output multiplexer PM.H7 PWM4 H7.3 special out H0.1 SMG/PWM5 output multiplexer PM.H0 PWM5 H0.1 special out Clock and period P7C, P7P H7.2 SME/PWM6 output multiplexer PM.H7 PWM6 H7.2 special out H0.0 SMG/PWM7 output multiplexer PM.H0 PWM7 H0.0 special out Clock and period P9C, P9P H7.1 SME/PWM8 output multiplexer PM.H7 PWM8 H7.1 and/or H6.3 special out H7.0 SME/PWM9 output multiplexer PM.H7 PWM9 H7.0 and/or H6.2 special out Clock and period P11C, P11P PWM10 H6.1 special out PWM11 H6.0 special out SR1.PWM1 SR1.PWM3 SR1.PWM5 SR1.PWM7 SR1.PWM9 SR1.PWM11 Returning a PWM to standby mode by resetting its respective enable flag will immediately set its output LOW. Due to EMI reduction the start of a period is delayed for different PWMs (Table 15-2). The 8bit PWM output PWMx-1 is not usable in 16bit mode. Table 15-2: Module Delay The state of the down-counters and the PWM registers is not readable. Module Number Delay PWM 0, 4, 8 0 PWM 1, 5, 9 1/f0 PWM 2, 6, 10 2/f0 PWM 3, 7, 11 3/f0 15.2. Registers PWMx 7 PWMx Register 6 5 w 3 2 1 0 7 Pulse width value 0 94 4 PWMx-1 0 0 0 0 PWMx-1 Register 6 5 w 0 0 0 Res 4 3 2 1 0 0 0 0 Pulse width value 0 0 0 0 0 Res Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Module Name CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 15-3: 8bit Mode Pulse Width Programming Pulse width value Pulse duty factor 0x00 0% (Output is permanently low) 0x01 1/256 0x02 2/256 : : 0xFE 254/256 0xFF 100% (Output is permanently high) 1) All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 1) Pulse duty factor 255/256 is not selectable. Table 15-4: 16bit Mode Pulse Width Programming Pulse width value Pulse duty factor 0x0000 0% (Output is permanently low) 0x0001 1/65536 0x0002 2/65536 : : 0xFFFE 65534/65536 0xFFFF 100% (Output is permanently high) 1) 1) Pulse duty factor 65535/65536 is not selectable. PWMC w PWM Control Register 7 6 5 4 3 2 1 0 x x P1611 P169 P167 P165 P163 P161 x x 0 0 0 0 0 0 P16x w1: w0: Micronas Res PWM 16 Mode of Module x 16bit mode. 8bit mode. 95 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 96 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 16. Pulse Frequency Modulator (PFM) The PFM generates a signal with variable frequency and variable pulse width. Together with external elements it may serve to generate a negative voltage for LCD elements. Features - Pulse width and period separately controllable - Pulse width and period counters operate with HW option selectable clock - Output polarity selectable - Standby mode 8 Bit Reload-reg. HW Option PF0C 1 0 PFM0.INV clk ld en All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Pulse Width ld clk 1 0 8 Bit Down Counter 16 Bit Down Counter 16 Bit Reload-reg. zero 1 1 0 1 PFM0 zero Period Length SR1.PFM0 Fig. 16-1: PFM Block Diagram 16.1. Principle of Operation 16.1.1. General The pulse width and the period counter start synchronously with down-counting. As long as the pulse width counter is running, it's zero output is LOW. When this counter reaches zero it stops counting and sets the zero output to HIGH. When the period counter reaches zero, it reloads both counters, which starts a new count cycle. The zero output of the pulse width counter can be driven out directly or inverted via pin PFM0. The module is operable in PLL, FAST and SLOW mode. As long as PF0C is available it is also operable in DEEP SLOW mode. See also chapter "CPU and Clock System" for further details. Table 16-1: Module specific settings HW Options Initialization Item Address Item Setting Input clock PF0C PFM0 U5.0 and/or U1.7 special out Enable Bit SR1.PFM0 16.1.2. Hardware Settings 16.1.3. Initialization The clock input frequency PF0C is settable by HW option (see Table 16-1). Prior to entering active mode, proper SW initialization of the U-Ports assigned to function as PFM0 output has to be made (Table 16-1). The ports have to be configured Special Out. Refer to "Ports" for details. 16.1.4. Operation After reset the PFM is in standby mode (inactive) and the output signal is LOW. To prepare for active mode, write new values, if needed, for the pulse width and the period length to the respective PFM0 register and select output inversion, if necessary, with flag INV. For entering active mode set the enable bit SR1.PFM0. Micronas 97 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Changing the PFM0 register setting during active mode, is simply done by writing a 32bit word to this register. After the register has been updated, the PFM will produce an output signal with the new pulse width and period length starting with the next subsequent load signal of the period counter. For data consistency, when using 8bit and 16bit writes, new values will only become valid after a write to the pulse width register (byte 2 in the PFM0 register). Returning the PFM to standby mode by clearing its Enable Bit SR1.PFM0 will immediately set its output to INV and disable the clock input. The content of the PFM0 register is not affected by standby mode. The state of the counters and the reload registers is not readable. 16.2. Registers w Pulse Width and Period Register 7 6 5 4 INV x x x 3 2 x x 1 x 0 x Offs 3 w Pulse Width 2 w Period Length (High Byte) 1 w Period Length (Low Byte) 0 0x00 INV r/w1: r/w0: All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. PFM0 Res Invert Output Signal inverted direct The pulse width counter zero output HIGH time is calculated by Pulse Width t HIGH = ----------------------------F PF0C and the duration of the period time by Period Length t Period = ---------------------------------F PF0C Therefore, the pulse width counter zero output LOW time is t LOW = t Period - t HIGH Table 16-2 shows the relation of the Pulse Width and the Period Length and its effect on the PFM0 output. Table 16-2: Pulse Width to Period Length Relation Pulse Width Period Length INV PFM0 output 0 x 0 Always low >0 Pulse Width Always high >0 > Pulse Width High pulses 0 x >0 Pulse Width Always low >0 > Pulse Width Low pulses 98 1 Always high Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 17. Capture Compare Module (CAPCOM) The IC contains two Capture Compare Modules (CAPCOM). - 16bit free running counter with read out. A CAPCOM is a complex relative timer. It comprises a free running 16bit Capture Compare Counter (CCC) and a number of Subunits (SU). The timer value can be read by SW. - 16bit capture register. - 16bit compare register. - Input trigger on rising, falling or both edges. A SU is able to capture the relative time of an external event input and to generate an output signal when the CCC passes a predefined timer value. Three types of interrupts enable interaction with SW. Special functionality provides an interface to the asynchronous external world. HW Option fC1C fCC1IN - Output action: toggle, low or high level. - Three different interrupt sources: overflow, input, compare - Designed for interface to asynchronous external events clk CCC1OFL Interrupt Source CCC1 Timer Value SR0.CCC1 ofl 16 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 2 2 CC4I 1 CC4-IN CC4-OUT 0 7 0 0 0 1 1 0 1 1 Input Action Logic 3 CC4M CAP CMP OFL LAC RCR 6 5 4 X 3 X 2 X 1 MCAP MCMP MOFL 0 7 6 5 FOL 4 OAM 3 IAM 2 1 0 & & CC4OR Interrupt Source & 2 LOW 0 0 TOGGLE 0 1 1 0 1 1 Output Action Logic >1 >1 16 A reset load Subunit 4 16-Bit Capture-Register r 16-Bit Compare-Register w CC4 = B CC4COMP Interrupt Source 16 Timer Value ofl 16 CC5-IN CC5-OUT CC5OR Subunit 5 CC5COMP Fig. 17-1: CAPCOM Module 1 Block Diagram Micronas 99 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 HW Option fC0C fCC0IN clk CCC0OFL Interrupt Source CCC0 Timer Value SR0.CCC0 ofl 16 2 2 CC0I CC0-IN CC0-OUT 7 0 0 0 1 1 0 1 1 Input Action Logic 3 CC0M CAP CMP OFL LAC RCR 0 6 5 4 X 3 X 2 X 1 MCAP MCMP MOFL 0 7 6 5 FOL 4 OAM 3 IAM 2 1 0 & >1 & & 2 LOW 0 0 TOGGLE 0 1 1 0 1 1 Output Action Logic CC0OR Interrupt Source >1 16 A reset load Subunit 0 16-Bit Capture-Register r 16-Bit Compare-Register w CC0 = B CC0COMP Interrupt Source 16 Timer Value ofl 16 CC1-IN CC1-OUT CC1OR Subunit 1 CC1COMP Timer Value ofl 16 CC2-IN CC2-OUT CC2OR Subunit 2 CC2COMP Timer Value ofl 16 CC3-IN CC3-OUT CC3OR Subunit 3 CC3COMP Fig. 17-2: CAPCOM Module 0 Block Diagram 100 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 1 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 17.1. Principle of Operation 17.1.1. General The Capture Compare Module (CAPCOM, Fig. 17-1, 17-2) contains one common free running 16bit counter (CCC) and a number of capture and compare subunits (SU). More details are given in Tables 17-1 and 17-2. The timer value can be read by SW from 16bit register CCC. The CCC provides an interrupt on overflow. Table 17-1: Unit 0 specific settings Subunit Item All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Thus, a SU contains a 16bit capture register CCx to store the input event CCC value, a 16bit compare register CCx to program the Output Action CCC value, an 8bit interrupt register CCxI and an 8bit mode register CCxM. Two types of interrupts per SU enable interaction with SW. Input PM. CACO SU2 For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 17.1.2. Hardware Settings PM. CACO SU1 Input Input SU3 PM. CACO Output PM. U06 The CCC0 and CCC1 clock frequency must be set via HW option (Table 17-1 and 17-2). Some SUs use several ports. They can be selected via HW Option Port Multiplexer (PM). Refer to "HW Options" for setting them. 17.1.3. Initialization After system reset the CCC and all SUs are in standby mode (inactive). In standby mode, the CCC is reset to value 0x0000. Capture and compare registers CCx are reset. No information processing will take place, e.g. update of interrupt flags. However, the values of registers CCxI and CCxM are only reset by system reset, not by standby mode. Thus it is possible to program all mode bits in standby mode and a predetermined start-up out of standby mode is guaranteed. SU0, SU1, SU2, SU3 Clock Please note that the compare register CCx is reset in standby mode. It can only be programmed in active mode. Setting CC0OUT U3.2, U4.0 special out CC0-IN U3.2, U4.1 special in CC1OUT U3.1, U2.5 special out CC1-IN U3.1, U2.4 special in CC2OUT U3.0, U2.3 special out CC2-IN U3.0, U2.2 special in CC3OUT U0.5, U0.6, U8.1 special out CC3-IN U0.6 special in SR0. CCC0 Table 17-2: Unit 1 specific settings Subunit HW Options Item Input PM. CC4I SU5 SU4, SU5 Clock Initialization Address Item 17.1.3.1. Subunit For a proper setup the SW has to program the following SU control bits in registers CCxI and CCxM: Interrupt Mask (MSK), Force Output Logic (FOL, 0 recommended), Output Action Mode (OAM), Input Action Mode (IAM), Reset Capture Register (RCR, 0 recommended), and Lock After Capture (LAC). Refer to section 17.2. for details. Enable Bit C0C SU4 Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as Input Capture inputs and Output Action outputs has to be made (Table 17-1, 17-2). The Output Action ports have to be configured as special out and the Input Capture ports as special in. Refer to "Ports" for details. Initialization Address Item SU0 Each SU is able to capture the CCC value at a point of time given by an external input event processed by an Input Action Logic. A SU can also change an output line level via an Output Action Logic at a point of time given by the CCC value. HW Options Enable Bit Setting CC4OUT U5.3, U8.0 special out CC4-IN U5.3, P0.0 special in CC5OUT U7.4 special out CC5-IN U7.4 special in SR0. CCC1 C1C 17.1.4. Operation of CCC For entering active mode of the entire CAPCOM module set the enable bit (Table 17-1 and 17-2). The CCC will immediately start up-counting with the selected clock frequency and will deliver this 16bit value to the SUs. Micronas 101 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The state of the counter is readable by reading the 16bit register CCC, low byte first. Upon reading the low byte, the high byte is saved to a temporary latch, which is then accessed during the subsequent high byte read. Thus, for time stamp applications, read consistency between low and high byte is guaranteed. The CCC is free running and will overflow from time to time. This will cause generation of an overflow interrupt event. The interrupt (CCCxOFL) is directly fed to the Interrupt Controller and also to all SUs where further processing takes place. overwrite the capture register, lock the Input Action logic if in LAC mode and generate an interrupt. Make sure that SW is prepared to handle such a situation. For testing purposes, a permanent reset (0xFFFF) may be forced on capture register CCx by setting bit CCxI.RCR. Make sure that the reset is only temporary. 17.1.5.3. Interrupts Each SU supplies two internal interrupt events: 1. Input Capture event and 17.1.5.1. Compare and Output Action To activate a SUs compare logic the respective 16bit compare register CCx has to be programmed, low byte first. The compare action will be locked until the high byte write is completed. As soon as CCx setting and CCC value match, the following actions are triggered: - The flag CMP in the CCxI register is set. - The CCxCOMP interrupt source is triggered. - The CCxOR interrupt source is triggered if activated. - The Output Action logic is triggered. Four different reactions are selectable for the Output Action signal: according to field CCxM.OAM (Table 17-3) the equal state will lead to a high or low level, toggling or inactivity on this output. Another way to control the Output Action is bit CCxM.FOL. E.g. rise-mode and force will set the output pin to high level, fall-mode and force to low level. This forcing is static, i.e. it will be permanently active and may override compare events. Thus it is recommended to set and reset shortly after that, i.e. to pulse the bit with SW. Toggle mode of the Output Action logic and forcing leads to a burst with clock-frequency and is not recommended. 17.1.5.2. Capture and Input Action The Input Action logic operates independently of the Output Action logic and is triggered by an external input in a way defined by field CCxM.IAM. Following Table 17-4 it can completely ignore events, trigger on rising or falling edge or on both edges. When triggered, the following actions take place: - Flag CCxI.CAP is set. - The CCxOR interrupt source is triggered if activated. - The 16bit capture register CCx stores the current CCC value, i.e. the "time" of the external event. Read CCx low byte first. Further capture and input action will be locked until the subsequent high byte read is completed. Thus a coherent result is ensured, no matter how much time has elapsed between the two reads. Some applications suffer from fast input bursts and a lot of capture events and interrupts in consequence. If the SW cannot handle such a rate of interrupts, this could evoke stack overflow and system crash. To prevent such fatal situations the Lock After Capture (LAC) mode is implemented. If bit CCxI.LAC is set, only one capture event will pass. After this event has triggered a capture, the Input Action logic will lock until it is unlocked again by writing an arbitrary value to register CCxM. Make sure that this write only restores the desired setting of this register. Programming the Input Action logic while an input transition occurs may result in an unexpected triggering. This may 102 2. Comparator equal state. In addition to the above mentioned two, the CCC Overflow interrupt event sets flag CCxI.OFL in each SU. Thus, three interrupt events are available in each SU. As previously explained, interrupt events will set the corresponding flags in register CCxI. The corresponding flags are masked with their mask bits in register CCxM and passed to a logical or. The result (CCxOR) is fed to the interrupt controller as a first interrupt source. In addition, the Comparator equal (CCxCOMP) interrupt is directly passed to the interrupt controller as second interrupt source. Thus a SU offers four types of interrupts: CCC overflow (maskable ored), input capture event (maskable ored) and comparator equal state (maskable ored and non-maskable direct). All interrupt sources act independently, parallel interrupts are possible. The interrupt flags enable SW to determine the interrupt source and to take the appropriate action. Before returning from the interrupt routine the corresponding interrupt flag should thus be cleared by writing a 1 to the corresponding bit location in register CCxI. The interrupts generated by internal logic (CCC Overflow and Comparator equal) will trigger in a predetermined and known way. But as explained in 17.1.5.2. erroneous input signals may cause some difficulties concerning the Input Capture input as well as interrupt handling. To overcome possible problems the Input Capture Interrupt flag CCxI.CAP is double buffered. If a second or even more input capture interrupt events occur before the interrupt flag is cleared (i.e. SW was not able to keep track), the flag goes to a third state. Two consecutive writes to this bit in register CCxI are then necessary to clear the flag. This enables SW to detect such a multiple interrupt situation and eventually to discard the capture register value, which always relates to the latest input capture event and interrupt. The internal CAPCOM module control logic always runs on the clock divider chain f0 frequency, regardless of CPU clock mode. Avoid write accesses to the CCxI register in CPU Slow mode since the logic would interpret one CPU access as many consecutive accesses. This may yield to unexpected results concerning the functionality of the interrupt flags. The following procedure should be followed to handle the capture interrupt flag CAP: 1. SW responds to a CAPCOM interrupt, switching to CPU Fast or PLL mode if necessary and determining that the source is a capture interrupt (CAP flag =1). 2. The interrupt service routine is processed. 3. Just before returning to main program, the service routine acknowledges the interrupt by writing a 1 to flag CAP. 4. The service routine reads CAP again. If it is reset, the routine can return to main program as usual. If it is still set an external capture event overrun has happened. Appropriate actions may be taken (i.e. discarding the capture register value etc.). Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 17.1.5. Operation of Subunit CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 17.1.7. Precautions 5. go to 3. 17.1.6. Inactivation The CAPCOM module is inactivated and returned to standby mode (power down mode) by setting the enable bit to 0. Section 17.1.3. applies. The CCxI register must not be written in CPU Slow mode (see Section 17.1.5.3. on page 102). Read-Modify-Write operations on single flags of register CCxI must be avoided. Unwanted clearing of other flags of this register may be the result otherwise. CCxI and CCxM are only reset by system reset, not by standby mode. 17.2. Registers All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The CAPCOM counter and the Capture/Compare registers have to be read/written low byte first to avoid inconsistencies. The memory controller accesses multiple byte quantities low byte first. Thus the 16 bit CAPCOM counter and the 16 bit Capture/Compare registers can be accessed 16 bit wide. CCCyL 7 CAPCOM Counter low byte 6 r 4 3 2 1 Output Action Mode Defines behavior of Output Action logic. Table 17-3: OAM usage Bit 32 Output Action Logic Modes 00 Disabled, ignore trigger, output low level. 01 Toggle output. 10 Output low level. 11 Output high level. 0 Read low byte and lock CCC 0 0 CCCyH 7 0 0 0 0 0 0 Res CAPCOM Counter high byte 6 r 5 4 3 2 1 0 0 0 IAM r/w: 0 CCxM 0 0 0 0 Res CAPCOM x Mode Register 7 6 5 4 MCAP MCMP MOFL FOL 0 0 0 0 MCAP r/w1: r/w0: Mask CAP Flag Enable. Disable. MCMP r/w1: r/w0: Mask CMP Flag Enable. Disable. MOVL r/w1: r/w0: Mask OVL Flag Enable. Disable. 3 2 1 OAM 0 Bit 10 Input Action Logic Modes 00 Disabled, don't trigger. 01 Trigger on rising edge. 10 Trigger on falling edge. 11 Trigger on rising and falling edge. 0 IAM 0 0 0 Res FOL Force Output Action Logic r/w1: Force Output Action logic. r/w0: Release Output Action logic. This flag is static. As long as FOL is true neither comparator can trigger nor SW can force, by writing another "one", the Output Action logic. After forcing it is recommended to clear FOL unless Output Action logic should not be locked. Micronas Input Action Mode Defines behavior of Input Action logic. Table 17-4: IAM usage Read high byte and unlock CCC 0 r/w 5 OAM r/w: CCxI r/w CAPCOM x Interrupt Register 7 6 5 4 3 2 1 0 CAP CMP OFL LAC RCR x x x 0 0 0 0 0 0 0 0 CAP r1: r0: w1: w0: Capture Event Event. No Event. Clear flag. No change. CMP r1: r0: Compare Event Event. No Event. Res 103 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 w1: w0: Clear flag. No change. OFL r1: r0: w1: w0: Overflow Event Event. No Event. Clear flag. No change. LAC Lock After Capture r/w1: Enable. r/w0: Disable. Refer to section 7.1.5.2 Reset Capture Register Reset capture register permanently to 0xFFFF. Release capture register. r/w0: CCxL 7 CAPCOM x Capture/Compare Register low byte 6 5 4 3 2 1 r Read low byte of capture register and lock it. w Write low byte of compare register and lock it. 1 1 CCxH 7 1 1 1 1 1 6 5 4 3 2 1 Read high byte of capture register and unlock it. w Write high byte of compare register and unlock it. 104 1 Res CAPCOM x Capture/Compare Register high byte r 1 0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. RCR r/w1: 1 1 1 1 1 1 0 1 Res Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 18. Stepper Motor Module VDO (SMV) The SMV module serves to control air cored movements or stepper motors that are directly coupled in H-bridge formation to H-Ports. Upon CPU programming it creates all waveforms necessary to position the drive pointer as desired. In addition it supports the Rotor Zero Position Detection by supplying motor blockage information. The Rotor Zero Position Detection capability is protected by a patent from Mannesmann VDO and may only be used with VDO's prior approval. The number of motors that are controllable by subunits (control units) of the module is given in Table 18-1. Features - Multi channel pulse width modulated output - Outputs offset for improved EMC properties - Four quadrant operation - 8bit resolution - Analog voltage sampling for Rotor Zero Position Detection support - HW Option selectable output cycle frequency 18.1. Principle of Operation All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 18.1.1. General An 8bit, free-running counter FRC (Fig. 18-1) operates on the fSM input clock (generally 4MHz) and creates an 8bit counter word that is fed to a number of control units SMx. A control unit (Fig. 18-1) contains 8bit sine and cosine compare registers. One comparator each is associated with these registers and creates a compare signal when register content and FRC word are equal. An output flip-flop associated with each comparator is set when the FRC word is zero and reset by the respective compare signal. A delay stage associated with each control unit delays the flip-flop output signals by a fixed number of fSM cycles to achieve non-synchronism between the output signals of the various control units, thus achieving an improved EMC behavior of the SMV (cf. Fig. 18-3). According to the setting of a quadrant register associated with each control unit, each of a unit's two output signals is multiplexed to signals SMxn+ and SMxn- so as to properly control 2 individual H-Ports that form an H-bridge together with the connected motor coil. By these means, a control unit supplies two H-bridges with signals SMx1+, SMx1-, SMx2+ and SMx2- to function as variable pulse width modulator outputs with selectable polarity. Summing up: when the compare registers are set to the sine and cosine value of a desired rotor angle and the quadrant register is set to the desired quadrant, an air cored movement or a stepper motor connected to the unit's 4 H-Ports will carry the proper average coil currents of proper polarity so that its rotor will assume the desired rotary angle. Three registers control readjustment of a rotor to a new angle. Sine, cosine and unit/quadrant registers serve as temporary storage of new sine, cosine, related quadrant and unit selection values. A scheduler logic times the synchronous downloading of the three buffered words to the respective unit's sine, cosine and quadrant registers, so as to avoid inconsistencies among them. A Busy bit may be read out signaling completion of the downloading. Each control unit contains circuitry to detect an induced voltage resulting from the rotation of the connected motor's rotor (Fig. 18-2). A comparator compares the input voltage from one of the unit's H-Ports to 1/9th of the supply voltage. A capture logic opens a capture window and samples the comparator output. The capture result signal supplies a rotor blockage information necessary for the Rotor Zero Position Detection in all cases where the CPU has lost track of the Micronas display angle of a pointer that is driven by the motor via a mechanical transmission. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 18.1.2. Hardware settings Prior to entering active mode, the fSM input clock has to be set by HW Option (see Table 18-1 on page 106). A frequency value of 4MHz is recommended resulting in a pulse width modulator cycle frequency of 4MHz/256. Some H-Ports may receive the output signals either of the SMV module or of PWM modules as an alternative. Refer to Table 18-1 for the necessary settings. Refer to section "HW Options" for details. 18.1.3. Initialization Prior to entering active mode, proper SW initialization of the H-Ports assigned to function as H-bridge outputs SMxn+ and SMxn- has to be made (Table 18-1). The H-Ports have to be configured Special Out. Refer to "Ports" for details. 18.1.4. Operation After reset, the SMV is in standby mode (inactive). The output lines to the H-Ports are low. For entering active mode, set bit SR0.SM. The FRC will immediately start counting but the control units' output lines will still be low. 18.1.4.1. Generating Output After entering active mode, the SMV's control units are ready to receive sine, cosine and quadrant values. First load the unit/quadrant information to register SMVC, then the cosine value to register SMVCOS and last the sine value to register SMVSIN. Upon writing SMVSIN, the scheduler logic will set flag SMVSIN.BUSY and load the buffered values to the respective unit's sine, cosine and quadrant registers on the next zero transition of the FRC, after a maxi- 105 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 18-1: Unit specific settings HW Options Item Initialization Address SMA SMB SMC SMD SME SME/PWM selection PM.H7 SMF SMG All SMG/PWM selection Input clock selection PM.H0 Enable Bit Item Setting SMAn+/- outputs H4.0 to H4.3 special out SMA-COMP input H4.0 special in SMBn+/- outputs H3.0 to H3.3 special out SMB-COMP input H3.0 special in SMCn+/- outputs H2.0 to H2.3 special out SMC-COMP input H2.0 special in SMDn+/- outputs H5.0 to H5.3 special out SMD-COMP input H5.0 special in SMEn+/- outputs H7.0 to H7.3 special out SME-COMP input H7.0 special in SMFn+/- outputs H1.0 to H1.3 special out SMF-COMP input H1.0 special in SMGn+/- outputs H0.0 to H0.3 special out SMG-COMP input H0.0 special in SR0.SM SM mum of 256 fSM input clock cycles. After completing the download, flag BUSY is reset and the respective unit will immediately start producing the output signals with the desired timing (see Table 18-4) on the proper pins (see Table 18-3). The above procedure for loading values to a first unit is repeated for all others. Make sure that the BUSY flag is 0 before rewriting registers SMVC, SMVCOS and SMVSIN. 18.1.4.2. Rotor Zero Position Detection During Rotor Zero Position Detection one of a unit's H-Ports (Table 18-1) has temporarily to be operated as input to an internal analog comparator. Reconfigure this port as Special Input. Refer to "Ports" for details. Parallel Rotor Zero Position Detection on all control units is permitted. After completion of Rotor Zero Position Detection, reconfigure the comparator input port as Special Out. 18.1.5. Inactivation Returning the SMV module to standby mode by resetting bit SR0.SM will immediately halt the FRC, return all output signals to 0, reset all internal registers and disconnect the comparators from supply. Reading of the induced voltage at the measured motor winding is started by setting the questioned unit's control bit SMVCMP.ACRx to 1. The respective analog comparator's output will now be sampled. Once three consecutive "1" samples (spaced 1/fCPU) - indicating a sufficient analog comparator input voltage - are received, a 1 may be read from the questioned unit's result flag SMVCMP.ACRx, indicating that the Rotor Zero Position Detection is under way. Resetting the questioned unit's control bit SMVCMP.ACRx to 0 stops the sampling and resets the result flag. When after a restart of the above sampling procedure and after a sufficiently long capture period still no 1 was read from the questioned unit's result flag SMVCMP.ACRx, this indicates that Rotor Zero Position Detection is complete. 106 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Contr. Unit CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 SMVC w x x SR0.SM SEL x QUAD 3 fSM fSM /256 Busy 7 Load r x x x x x x x B Sine register w SMVCOS Cosine register fCLK 8bit FRC OVFL R S Comparator sin A "=" sin A comp. latch (reload register) DELAY Q 0/f SM cos A comp. latch (reload register) R S SMA1- Quadrant register and decoder Load A Comparator cos A "=" SMA1+ sin DELAY Q 0/f SM SMA2+ SMA2- cos SMA SMB1+ SMB1- sin B / cos B DELAY 1 / fSM SMB2+ SMB SMB2- SMC1+ w All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. SMVSIN ftrig Scheduler SMC1sin C / cos C DELAY 2 / fSM SMC2+ SMC SMC2- SMD1+ SMD1sin D / cos D DELAY 3 / fSM SMD2+ SMD SMD2HW Option PWM4 PWM6 sin E / cos E DELAY 4 / fSM SME PWM8 PWM9 SME1+ SME1SME2+ SME2- SMF1+ SMF1sin F / cos F DELAY 5 / fSM SMF2+ SMF SMF2HW Option SMG1+ PWM1 SMG1- sin G / cos G PWM3 DELAY 6 / fSM SMG2+ SMG PWM5 SMG2PWM7 Fig. 18-1: Block Diagram of Output Generation Circuit Micronas 107 SMA SMA-COMP SMB-COMP SMC-COMP SMD-COMP SME-COMP SMF-COMP SMG-COMP 108 + - + + + + + + Debouncer and measurement window - - - - - SMB 4 SMC 1 SMD 5 SME 2 SMF 6 SMG 3 - SR0.SM HVDD0 8R R r/w x F D B G E C A SMVCMP 6 5 4 3 2 1 0 HVDD1 HVDD2 HVDD3 Fig. 18-2: Block Diagram of Rotor Zero Position Detection Circuit Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 fSM 0 R S Result latch CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 18.2. Registers SMVC w Stepper Motor VDO, Control Register 7 6 x x x x 5 4 3 2 SEL 0 0 1 x 0 x SMVCOS 7 0 6 5 w QUAD 0 Stepper Motor VDO, Cosine Register 0 SEL Control unit Selection field (Table 18-2) QUAD Quadrant selection field (Table 18-3) 4 3 2 1 0 0 0 0 8bit Cosine Value 0 Res 0 BUSY r0: r1: 0 0 0 Res Scheduler Busy Flag Scheduler not busy Scheduler busy, do not write registers SMVC, SMVCOS, SMVSIN Table 18-2: SEL usage All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Table 18-4: Usage of SMVSIN and SMVCOS registers SEL selected control unit 000 SMA 001 SMB 010 Value Duty factor 00h 0/256 (continuously low) SMC 01h 1/256 011 SMD 02h 2/256 100 SME : : 101 SMF FEh 254/256 110 SMG FFh 255/256 1) 111 Not permitted 1) Table 18-3: QUAD setting and resulting control unit output signal function QUAD SMVCMP r/w SMx1- SMx2+ SMx2- 00 sine VSS cosine VSS 01 sine VSS VSS cosine 10 VSS sine VSS cosine 11 VSS sine cosine VSS SMVSIN r x 256/256 (continuously high) is not available. Stepper Motor VDO, Comparator Register 7 6 5 4 3 2 1 0 x ACRF ACRD ACRB ACRG ACRE ACRC ACRA x 0 0 0 0 0 0 0 Control unit output signal function SMx1+ 7 Pulse Diagram ACRA to G r0: r1: w0: w1: Res Analog Comparator Control and Result for SMA to SMG Capture result: no induced voltage detected Capture result: induced voltage detected Stop capture and clear result flag Start capture Stepper Motor VDO, Sine Register 6 x 5 x w 4 x 3 2 1 0 x x x BUSY 0 0 0 8bit Sine Value 0 Micronas 0 0 0 0 Res 109 SMA1- SMA2+ SMB1+ SMB1- SMB2+ 110 Example: SMB in 4th quadrant SMB2- tdB = 1/ fSM Fig. 18-3: Timing Diagram of Output Signals Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 18.3. Timing 1/ftrig ftrig =fSM /28 SMA1+ Example: SMA in 1st quadrant SMA2- tdA = 0/ fSM CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 19. LCD Module The Liquid Crystal Display (LCD) Module is designed to directly drive a 1:4 multiplexed liquid crystal display. It generates all signals necessary to drive 4 backplane and 48 segment lines which are output via U-Ports in LCD mode. Up to 192 segments or pixels can be controlled if all U-Ports are designated as segment outputs. In addition, the module provides functions that enable the user to cascade it with external expansion ICs providing more segment lines. It can be operated as master or slave in such an extended system. Features - 1:4 multiplex - 5V supply - Maximum of 192 segments - Cascadable with external expansion ICs - 0.3mA buffered 1/3 and 2/3 voltage divider - Zero standby current - 200A no load active current - Frame frequency HW Option selectable All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 19.1. Principle of Operation 19.1.1. General 19.1.2. Hardware settings Each LCD pixel or segment which is controlled by the LCD module is located at the crossing point of a segment line and a backplane line. The LCD module co-ordinates the output sequences of backplane and segment lines (see Fig. 19-3 on page 113). The LCD frame frequency is settable by HW option LC. The resulting frame frequency is the selected input frequency, divided by 120. It should be in the range from 50 to 200Hz. BP3 BP2 BP1 BP0 SEGn-1 SEGn For best electromagnetic interference results it is recommended to operate all segment and backplane U-Ports in Port Slow mode. Refer to "Ports" for more details and to "HW-Options" for setting the corresponding HW options. Set flag PSLW in register SR0 to HIGH to enable Port Slow mode. 19.1.3. Initialization SEGn+1 After reset, the LCD module is in standby mode (inactive) and all U-Ports are in Port mode, non-conducting. Fig. 19-1: Segments and Backplanes All U-Ports designated to function as backplane or segment outputs are to be set to LCD mode. Refer to "Ports" for more details. This will set these U-Ports to output LOW state. A segment pin can drive 4 different voltage levels (UVSS, 1/3 UVDD, 2/3 UVDD, UVDD) in LCD mode. The output of each segment pin is controlled by the corresponding segment bits of the registers UxD, UxTRI, UxNS and UxDPM (further called segment registers). Each such register contains one bit (of a 4 bit segment field) for each of its port pins. Each segment bit (0 to 3) of a segment field corresponds to a backplane line (BP0 to BP3). If the segment bit, corresponding with the backplane line BPx is true, then the segment at the crossing of the two lines is on (black). The LCD module does not contain a display ROM translating character information into segment code. The advantage is that arbitrary characters or displays can be generated just by changing the program code. Segment information is directly entered by writing to the corresponding segment bit. It is validated (loaded to all corresponding slave registers) for all segment U-Ports simultaneously by a write access to register ULCDLD. Two internal voltage sources provide the U-Port circuits and the backplane generator with the voltage levels 1/3 UVDD and 2/3 UVDD. These levels are generated by a buffered resistor divider. Micronas After reset the content of the segment registers is undefined. It must be set by writing the desired segment information to the segment registers and by validating it by a write access to register ULCDLD (write 0x00 for master mode, 0xFF for slave mode), before the LCD module is enabled. 19.1.4. Operation For entering active mode, set flag LCD in register SR0. Each segment and backplane U-Port will immediately start producing its LCD output signal according to the segment information provided during initialization. During active mode, a new segment information is entered by simply writing the desired segment information to the segment registers and by validating it by a write access to register ULCDLD (write 0x00 while in master mode, 0xFF while in slave mode). Each segment and backplane U-Port will immediately start producing an LCD output signal according to the new segment information. Returning the LCD module to standby mode by resetting flag LCD in register SR0 will immediately return all segment and backplane U-Ports to the output LOW state. 111 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 ULCDLD.LCDSLV SR0.LCD HW Option fCLK 1/1 1/1.5 1/2.5 8 x frame frequency 0 1 1 3 1/15 LCD-CLK-IN LCD-CLK-OUT overflow 0 LCD-SYNC-IN reset UVDD 8 State Counter 2 wr ULCDLD 1 1/ UV 3 DD UVSS load LCD-SYNC-OUT UVDD en + 2/ 3UVDD + 1/ 3UVDD LCD Supply U0MODE.L0 U0D.SG0_0 U0TRI.SG0_1 U0NS.SG0_2 U0DPM.SG0_3 Analog Switch and Segment Driver U0D.SG1_0 U0TRI.SG1_1 U0NS.SG1_2 U0DPM.SG1_3 Analog Switch and Segment Driver U8D.SG5_0 U8TRI.SG5_1 U8NS.SG5_2 U8DPM.SG5_3 Analog Switch and Segment Driver Backplane Generator SR0.LCD /3UVDD 1 U0.0 U0MODE.L1 1 U0.1 U8MODE.L5 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 1 U8.5 U4MODE.L0 Analog Switch and 0 Backplane Driver Analog Switch and 1 Backplane Driver Analog Switch and 2 Backplane Driver Analog Switch and 3 Backplane Driver 1 1 1 1 U4.0 U4.1 U4.2 U4.3 Fig. 19-2: Block Diagram For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 19.1.5. Cascading of LCD Driver Modules For expansion purposes, the LCD module may be cascaded with external LCD driver ICs. Master or slave mode is selectable for the LCD module while in standby. Special signals provide phase and frequency synchronism for the LCD frame among the cascaded ICs. 112 For master mode, set flag LCDSLV in register ULCDLD LOW. The module always directs signal LCD-SYNC-OUT to pins U8.5 and LCD-CLK-OUT to pins U8.3. They connect to external slave ICs' SYNC-IN and CLK-IN inputs for synchronization. For slave mode, set flag LCDSLV in register ULCDLD HIGH. Configure pins U8.4 and U8.2 to receive signals LCD-SYNCIN and LCD-CLK-IN from an external master IC's SYNCOUT and CLK-OUT outputs. These signals will then substitute the LCD module's own HW option frame frequency settings. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. HW Option CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Starting up and shutting down such an expanded system is described in section 19.3. 1 Frame VDD 2/3 BP0 1/3 0 Segment off Segment on Backplane BP1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. BP2 BP3 Pin Segment Data Latches SEG0.0 U0D.SG0_0 = 0 U0TRI.SG0_1 = 0 U0NS.SG0_2 = 0 U0DPM.SG0_3 = 0 SEG0.1 U0D.SG1_0 = 0 U0TRI.SG1_1 = 0 U0NS.SG1_2 = 0 U0DPM.SG1_3 = 1 SEG0.2 U0D.SG2_0 = 0 U0TRI.SG2_1 = 1 U0NS.SG2_2 = 1 U0DPM.SG2_3 = 0 SEG0.3 U0D.SG3_0 = 0 U0TRI.SG3_1 = 1 U0NS.SG3_2 = 0 U0DPM.SG3_3 = 1 SEG0.4 U0D.SG4_0 = 1 U0TRI.SG4_1 = 1 U0NS.SG4_2 = 1 U0DPM.SG4_3 = 1 Fig. 19-3: Frame Timing Diagram A segment at a crossing of backplane and segment lines is turned black when at the same time the backplane driver outputs a full swing and the segment driver outputs a full swing of opposite polarity. Micronas 113 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 19.2. Registers Please refer to section "Universal Port Registers" for details on segment register layout. ULCDLD 7 w LCDSLV 0 19.2.1. Special Register Layout of U-Port 4 Universal Port LCD Load Register 6 5 4 3 2 1 0 x x x x x x x 0 0 0 0 0 0 0 A write access to this memory location simultaneously loads all segment information of all U-Ports in LCD mode to the display. Res LCDSLV LCD Module is Slave Select the mode of the LCD module. w1: LCD module is slave. w0: LCD module is master. U4.0 to U4.3 provide backplane signals in LCD Mode. To operate any ports as LCD segment driver it is necessary to switch all these ports to LCD mode. This has to be done by setting flags U4MODE.L0 through U4MODE.L3. As backplane ports U4.0 to U4.3 require no segment data setting, SG0_0 through SG3_3 bits are not available in U4 registers. 19.3.1. Power On and Start Up Procedure 1. The SW in master and slave configures the corresponding IC. Table 19-1: Suggested sequence Master Slave Load LCD display register. Load LCD display register. Clear flag LCDSLV. Set flag LCDSLV. LCD-CLK-OUT, and LCD-SYNC-OUT: Configure universal ports as Special Out Ports. LCD-CLK-IN, and LCD-SYNC-IN: Configure universal ports as Special In Ports. lag between write accesses to ULCDLD of the master and of the slave is kept as small as possible. Suggestion: Lower ms range or customer specification. 19.3.3. Power Off Procedure 1. (Optional) The processor which decides that the display is to be switched off signals this to the other via IPI. 2. The slave continuously scans the inputs LCD-CLK-IN and LCD-SYNC-IN for the bit combination "11" (SW debouncing required). 3. The master LCD module is switched off. LCD-CLK-OUT and LCD-SYNC-OUT switch to "11". 4. The slave CPU detects the bit combination "11" and immediately switches off the slave LCD module. Note: Keep time delay as short as when switching on. 2. Optionally the slave signals to the master via handshake link or an inter processor interface (IPI) that it is ready to display. 5. All LCD ports output a low signal now. The LCD display is now inactive. 3. The slave continuously scans the inputs LCD-CLK-IN and LCD-SYNC-IN for the bit combination "01" (SW debouncing required). 4. The master LCD module is switched on. LCD-CLK-OUT and LCD-SYNC-OUT switch to "01". 5. The slave CPU detects the bit combination "01" and immediately switches on the slave LCD module. The slave LCD now generates a display. Note: During the time that the slave needs to detect the bit combination "01", master and slave operate asynchronously. Suggestion: limit time to approximately 100 to 200ms. 6. The LCD modules now operate in controlled synchronization. 19.3.2. Operation In order to obtain optimum synchronization of LCD switchover, a change of display must be coordinated between master and slave (preferably via IPI) in such a way, that the time 114 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 19.3. Application Hints for Cascading LCD Modules CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 20. DMA Controller The DMA controller allows transferring data fields between internal memory and either an external IC via U-Ports (GBus), or an SPI module, with minimum CPU interaction. tion, to construct long serial data transfer sequences. It frees the CPU of repeatedly reloading data, e.g. under interrupt control. DMA transfers can be triggered by the interrupt source output of the corresponding module (self timed), a dedicated DMA Timer output or a port interrupt. Features The G-Bus is intended to support the operation of external LCD driver ICs (e.g. SED1560 by Epson): The DMA module copies 8bit pixel data bytes by direct memory access (DMA) to the external IC's graphic RAM with help of that IC's internal autoincrement address counter, and without CPU interaction. Other off-chip registers, allowing control of the display behavior (blinking, scrolling, etc.), have to be addressed by CPU operations. - 256 byte maximum DMA block size - one byte DMA block alignment - CPU cycle steal - Interrupt on DMA sequence finished 20.1. Functions The DMA Controller contains one DMA channel logic for each DMA channel, the priority encoder, the control logic, the DMA vector base register, address and cycle count buffer, and the bus interface (see Fig. 20-2 on page 116). CPU ICU 3 Bus Controller DMA Controller Bridge 3 SRAM ROM Flash 4 The DMA vector base register points to the beginning of the DMA table which is filled with a DMA vector for each DMA channel. Location zero contains the default vector and is not assigned to any DMA channel. Each DMA vector is composed of a 24 bit source/destination address and a 8 bit cycle counter value (see Fig. 20-5 on page 117). A DMA cycle is divided in a sequence of three steps: 1. Output Address of the DMA vector and read source/destination address and cycle counter. 2. Output Address of the DMA vector and write back incremented source/destination address and decremented cycle counter. 3. Output source/destination address and write/read data to/ from I/O module. I/O-Module Bridge All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. In SPI mode, the DMA module copies data bytes by direct memory access (DMA) to the SPIxD data register, self timed or under timing of the DMA timer and without CPU interac- - 3 DMA channels: direct 8bit data read or write between memory and UPorts U5 and U7 (G-Bus), direct 8bit data read or write between memory and SPI0, direct 8bit data read or write between memory and SPI1 Each step is one bus access which holds the CPU (cycle stealing). The DMA Controller generates the necessary control signals for above bus accesses. An I/O module requests a DMA cycle via its interrupt source output which is connected to the DMA request input (DREQ) of the corresponding DMA channel logic. The DMA interrupt output (DINT) is connected to the ICU instead where it indicates the end of a DMA sequence (see Fig. 20-3 on page 117). The signal DINT is connected to the G-Bus logic too, where it sets a flag indicating the end of the DMA sequence (see Fig. 20-4 on page 117). Fig. 20-1: System Block Diagram The DMA Controller transfers bytes (8 bit) between I/O modules and memory. One transfer is called a DMA cycle. The transfer of a block of bytes is called a DMA sequence. Micronas 115 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 BYPx DREQx fDMA HW Opt. PINT0 PINT1 DMATx & Mux TRIGx ENx pending S Q R & DMA Channel Logic enable DINTx to ICU 1 src# 2 3 Priority n Encoder 31 D Q R DACKx Once per DMA channel fSYS DWAIT Memory Controller & DMA Control Logic LOCK DACC A<23:0> D<31:0> DACK MAS<1> nRW D<31:0> DMA Vec. Base Fig. 20-2: DMA Controller The DMA channel logic contains an input multiplexer which selects one of four possible DMA request sources (see Table 20-2 on page 118). The output of this multiplexer sets a pending flag which is automatically reset when the DMA cycle is finished. An enable flag (EN) masks the pending flag output to the priority encoder. A bypass flag (BYP) allows to redirect DREQ to DINT and thus generate no DMA request but an interrupt. The priority encoder assigns each DMA channel a fixed unique priority (Table 20-1). This is necessary when more than one DMA channel signals a DMA request at the same time. The priority encoder outputs the source number with the highest priority. The control logic controls the above described three steps of bus accesses and generates the DMA acknowledge signal (DACKx) which indicates to the requesting module that the DMA transfer has finished. There are two fundamentally different modes to operate DMA sequences. - Self timed describes the situation where the corresponding I/O module requests a DMA transfer when it's ready. In this case the I/O module starts the DMA module when there is something to transfer and the DMA controller starts the I/O module after the transfer is finished. This is the fastest possible way to transfer information via DMA. Trying to get it faster enforces the danger that one of the communication partners is not ready. - External triggered describes the situation where a third party requests a DMA transfer. This can be a DMA timer or a port interrupt. The SW design has to guarantee that the I/O module as well as DMA controller can do their work between two consecutive DMA requests. Table 20-1: DMA Channels Priority I/O-Module 0 Default 1 U-Port GD 2 SPI 0 SPI0D 3 SPI 1 SPI1D 116 Register Name Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. MAS<0> CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 SPI0 DMA Int Src start SPI0 DREQx DACKx DINTx rd 1 ICU 32 Bit 00C 008 004 000 SPIx DMA Vector 3 DMA Vector 2 DMA Vector 1 Default DMA Vector Base + DMA Channel * 4 DMA Vector Base rd SPI0D & 8-bit count & nRW wr SPI0D 7 6 5 4 3 2 1 0 Fig. 20-3: DMA SPI Interaction All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. GBus DMA DREQ1 DACK1 DINT1 ICU DREQ1 DACK1 DINT1 rd 1 nRW 24-bit DMA Block Addr. Data Data Data Data Data Data Data Data Fig. 20-5: DMA Vector Table GBus & rd GD & wr GD Fig. 20-4: DMA Port Interaction 20.2. Registers The DMA registers can be read or written 32-bit wide, asynchronous and without wait states. DVB r/w DMA Vector Base 7 6 5 4 0 0 0 0 3 0 2 0 1 0 0 0 DE DMA Enable r/w1: enable DMA controller r/w0: disable DMA controller Enables the DMA controller clock (fSYS) and the clock for all DMA Timer (fDMA).Before setting to 0, make sure that all individual DMA channels are terminated. Offs SRC r31-0: 3 r/w A23 to A16 2 r/w A15 to A8 1 Priority source output The number of the highest pending and enabled DMA request. DCxM r/w A7 0 0 0 0 0 0 0 7 0x0000 DST DMA Channel x Mode Register 0 6 5 4 3 2 r/w P r/w EN DMAT 0 x x TRIG Offs x BYP DIR 1 MAS 0 DMA Status Register 0x0000 r/w 1 Res 7 6 5 DE x x 4 3 SRC 0x00 Micronas 2 1 0 Res Offs 0 Res P r1: r0: w1: w0: DMA Pending DMA transfer pending No DMA transfer pending No action Clear P 117 CDC32xxG-B V3.0 ADVANCE INFORMATION DMAT r/w7-0: DMA Timer DMA timing, equation: f DMA f DMAT = ---------------------DMAT +1 2 TRIG r/w15-0: Trigger Source (see Table 20-2) Table 20-2: DMA Trigger Sources TRIG Source 3 2 1 0 x x 0 0 DMA request from I/O-module x x 0 1 DMATx x x 1 0 PINT0 x x 1 1 PINT1 EN r1: r0: w1: w0: Enable DMA channel DMA sequence active DMA sequence finished enable DMA channel disable DMA channel BYP r/w1: r/w0: Bypass Interrupt don't bypass DMA-Request to ICU bypass DMA-Request to ICU. DIR r/w1: r/w0: DMA Direction write to I/O-module read from I/O-module MAS r/w3: r/w2: r/w1: r/w0: Memory Access Size reserved 32-bit (not supported) 16-bit (not supported) 8-bit 20.3. Principle of Operation The DMA Controller is operable in all CPU modes. 20.3.4. Self Timed DMA Read from I/O Operation 20.3.1. Initialization of the DMA Controller Flag DIR in register DCxM must contain a zero for reading from an I/O module. The DMA vector table has to be installed starting at a 128 byte aligned address. See figure 20-5 for DMA vector layout. Write the start address of the DMA vector table as a 32 bit address to the DMA Vector Base register (DVB) and note that only bits 7 to 23 may be modified. The other bits are forced to zero. Enable the DMA controller by setting flag DE in the DMA Status register (DST). Write the destination address (24 bit), pointing to the first element, and the block size (8 bit) to the corresponding DMA vector table entry. The input frequency fDMA for all DMA timer can be selected by the register DMAC in the HW Options field. Start a Graphic Bus DMA sequence by reading from register GD. The data of this read may be omitted. Then enable the DMA channel. Start an SPI DMA sequence by writing to register SPIxD of the corresponding SPI module. The data of this write may be omitted. Then enable the DMA channel. 20.3.2. Initialization of a DMA Channel All steps necessary to initialize the involved I/O module have to be taken according to the description in the respective chapter. Write the appropriate values to the DMA Channel Mode register (DCxM). Select the trigger source by field TRIG, program the DMA timer by field DMAT if necessary, select transfer direction (DIR) and size (MAS) and set BYP to one. 20.3.3. Self Timed DMA Write to I/O Operation Flag DIR in register DCxM must contain a one for writing to an I/O module. Write the source address (24 bit), pointing to the first plus one element, and the block size (8 bit) to the corresponding DMA vector table entry. Start the DMA sequence by writing the first element to be transferred to the data register of the corresponding I/O module and enable the DMA channel. 118 20.3.5. External Triggered DMA Operation The procedure is the same as with the self timed operation with some distinctions. In both cases (read/write) the SW initiates the first action in the peripheral module. Enable the DMA channel after this module has finished it's work. Otherwise a DMA cycle may happen to early transferring invalid data. It is possible to do external triggered DMA transfers without the SW initiating the first action. In this case the maximum block size is limited to 255 byte because the count value in the DMA vector has to be programmed with block size plus one. In a write case (Fig. 20-7), the sequence starts with data D1. In a read case (Fig. 20-8), the first DMA cycle reads invalid data D0. The first element of the transferred block has to be omitted in the latter case. 20.3.6. End of DMA Sequence The end of the DMA sequence is indicated by the enable flag (EN=0) and an interrupt which calls the ISR of the corresponding I/O module. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 3 DEC 01 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The address field of the corresponding DMA vector points to the next element after the last transferred element. The counter field is at zero. 20.3.7. Enabling of a DMA Channel Setting the flag EN to one enables the DMA channel. Make sure that there is no pending DMA request at that point of time. Clearing an active pending flag P and enabling the corresponding DMA channel must not be done with a single instruction. This might lead to an unwanted DMA cycle. First clear P and then set EN in two instructions. 20.3.8. Termination of a DMA Sequence A final termination of a DMA sequence can be achieved by first disabling the DMA channel (DCxM.EN=0) and the source of the DMA requests and secondly clearing the pending flag (DCxM.P=0). 20.3.9. Disabling of the DMA Controller First terminate all DMA channels (see 20.3.8.) and then clear flag DST.DE. Do not simply clear flag DST.DE, as this might result in undefined clock system behaviour. 20.4. Timing Diagrams fSYS All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. DREQx DACC A D DMA Vector DMA Vector Adr Adr Adr++ Data nRW DACKx pending DINTx EN Fig. 20-6: DMA Cycle Timing Micronas 119 A,D A,D counter 120 CPU D0 counter DMA D1 SPIio D0 4 CPU Start SPIio D0 4 DMA D2 D1 D2 D3 3 2 1 EN Fig. 20-7: SPI Write Sequence (serial out) DREQx DMA D0 DMA D1 DMA D2 DMA D3 DACKx SPIwr D1 D2 D3 3 2 1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 20.4.1. DMA Sequences SPI DREQx DMA D3 DACKx SPIwr 0 DINTx pending 0 DINTx pending EN Fig. 20-8: SPI Read Sequence (serial in) Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION A,D GDB A,D GDB Micronas CDC32xxG-B V3.0 3 DEC 01 20.4.2. DMA Sequences Graphic Bus Interface DREQx CPU D0 DMA D1 D0 CPU Start D0 DMA D2 D1 DMA D0 D1 DMA D3 DACKx wr GD D2 DMA D1 D2 D3 GWEQ DINTx DTA, EN Fig. 20-9: Graphic Bus Write Sequence (parallel out) DREQx DMA D2 DMA D3 DACKx rd GD D3 GOEQ DINTx DTA, EN Fig. 20-10: Graphic Bus Read Sequence (parallel in) The final DMA request pulse clears the DMA Transfer Active (DTA) flag additional to generating an interrupt. 121 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 122 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 21. Graphic Bus Interface The Graphic Bus Interface (GB) is intended to support the operation of external LCD driver ICs (e.g. SED1560 by Epson). Features - DMA read/write to external device - CPU read/write to external device - Read/write timing generation - Read/write control signals generation 21.1. Functions All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The DMA module copies 8bit pixel data bytes by direct memory access (DMA) to the external IC's graphic RAM with help of that IC's internal autoincrement address counter, and without CPU interaction. Other off-chip registers, allowing control of the display behavior (blinking, scrolling, etc.), have to be written and read by CPU operations. fIO D The register GD provides the data interface for the GB. Writing to GD outputs the data byte at U5.0 to U5.3 (low nibble) and U7.4 to U7.7 (high nibble). Reading from GD inputs a data byte from above pins. The assignment to external signals is shown in table 21-1. Table 21-1: Port Assignment GOEQ GWEQ GD0 to7 wr GD rd GD DACKx DINTx DREQx nRW the CPU. Please refer to section DMA for information about GB DMA interaction. Graphic Bus Interface Fig. 21-1: Port Bus Block Diagram The necessary timing is done autonomously by the GB logic. Any U-Port may be used as address output port operated by Port Name U5.0 GDB0 : : U7.7 GDB7 1) GADB External address bus U6.2 GWEQ External write signal U6.1 GOEQ External read signal External data bus 1) Any U-Port may be used as address output port. 21.2. GB Registers GD Graphic Bus Data Register 7 r/w 6 5 4 3 2 1 GC 0 7 Offs Data 0 0x00 Res A write access to this register generates the DACK signal and writes to registers UxD. A read access to this register generates the DACK signal and reads from registers UxPIN. Graphic Bus Control Register r/w 6 5 4 3 TIM E 0x00 TIM w15-1: 2 1 0 BSY SEQ DTA Offs 0 Res GB Timer GB timing, equation: 2 TIM + 1 t GB = -----------------f IO w0: Micronas GB logic is disabled, clock input is disabled 123 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 E r/w1: r/w0: Enable Enable timing generation Disable timing generation BSY Busy r1: GB timing is active r0: GB timing is not active Every DACKx signal or access to GD sets this flag and every DREQx signal clears it again. SEQ r1: r0: DMA Sequence DMA sequence is active DMA sequence is not active Every DACKx or access to GD signal sets this flag and the DINTx signal clears it again. DTA DMA Transfer Active r1: DMA sequence started r0: DMA sequence is finished w1: Set DTA w0: No action This flag indicates the end of a DMA sequence. It has to be set by SW before a DMA sequence is started. It is cleared by signal DINTx. 21.3. Principle of Operation Table 21-2 shows the necessary settings of the port configuration registers. Table 21-2: Port Configurations Register Setting Mode U5MODE, U7MODE, U6MODE 0x00 Port mode U5NS, U7NS 0x00 Normal U6NS 0x06 Special U5TRI, U7TRI, U6TRI 0x00 Out not finished and read the register GD. The DMA Controller reads the remaining bytes from register GD and generates an interrupt when finished. DTA low marks the end of the DMA sequence. 21.3.2.3. CPU Write Access Writing the byte to register GD is sufficient. The end of the transfer is indicated by flag BSY. 21.3.2.4. CPU Read Access The read access must be initiated by a dummy read access to register GD. After BSY is low the desired byte can be read from register GD. This last step automatically initiates the next read timing of the GB logic. If this is not desired, because GOEQ stays active until the next access to GD, after BSY became low, first disable the GB timing generation by clearing flag E in register GC and then read register GD. 21.3.3. Inactivation Enable the timing generation by setting flag E in register GC. Enable the clock input and select the desired timing of the control signals GOEQ and GWEQ in the field GC.TIM. The minimum high time of the control signals is one fIO cycle. 21.3.2. Data transfer Data to/from an external device can be transferred directly by CPU access or, especially for bigger amounts of data and with help of the external device's autoincrement address counter, a DMA sequence can be started. Make sure not to start a GB transfer unless the flags DTA, SEQ and BSY are zero. Inactivation is easily done by writing GC.TIM to zero. Make sure not to switch off the GB as long as a transfer is active (DTA or SEQ or BUSY are set). 21.3.4. Precautions A write to register GD alters the universal ports data latches U5D and U7D even if the GB is disabled (GC.TIM = 0). 21.3.2.1. DMA Write Sequence After initialization of the corresponding DMA channel, set flag DTA to show others that a DMA sequence was initiated but not finished and write the first value to be transferred via the GB to the register GD. The DMA Controller writes the remaining bytes to register GD and generates an interrupt when finished. DTA low marks the end of the DMA sequence. 21.3.2.2. DMA Read Sequence After initialization of the corresponding DMA channel, set flag DTA to show others that a DMA sequence was initiated but 124 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 21.3.1. Initialization CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 21.3.5. Timings DREQx A A,D A++ D1 A A++ D2 DACKx Enable tGB Count (fIO) D1 GDB tWDS D2 tWDH GWEQ All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. tWH DTA 1) Fig. 21-2: DMA Write (parallel out) DREQx A A,D A++ D2 A A++ D3 DACKx Enable tGB Count (fIO) GDB D2 D3 tACC GOEQ tRH DTA 1) Fig. 21-3: DMA Read (parallel in) 1) DTA at the end of the last DMA cycle. tWDS: Write data setup time tWDH: Write data hold time tWH: DMA write high time tRH: DMA read high time tACC: Read access time tGB: GB time Micronas DACKx can be replaced by write to GD or read from GD if direct CPU access is desired. The signals Enable and Count are internal signals. 125 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 126 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 22. Serial Synchronous Peripheral Interface (SPI) A SPI module provides a serial input and output link to external hardware. An 8 or 9 bit data frame can be transmitted in synchronism to an internally or externally generated clock. Features - 8 or 9 bit frames - Internal or external clock The SPI module can be operated via direct access or via DMA. - Programmable data valid edge - Programmable clock polarity The number of SPIs implemented is given in Table 22-1. The "x" in register names distinguishes the module number. - Three internal clock sources programmable - Input deglitcher for clock and data - DMA interface SPIx-D-IN SI 0 HW Option 0 Deglitcher 1 0 shift in 1 1 SPIx-D-OUT SO 0 SPIxD shift out 8 1 1 7 6 5 4 3 2 1 0 1 HW Option RXSEL Deglitcher BIT8 INTERN SPIxM 7 6 5 4 3 2 1 0 LEN9 3xT0 SPIx Interrupt Source shift clock All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 1 0 Scheduler clk 1 SR0.SPIx 0 SPIx-CLK-OUT SO clkout 2 1 1 SPIx-CLK-IN SI 0 Deglitcher 1 1 HW Option HW Option F1SPI 0 extclk F0SPI 1/1 3:1 MUX 1/1,5 1/2,5 F2SPI 1 intclk 1 INTERN 0 CSF0/1 2 Fig. 22-1: Block Diagram Micronas 127 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 22.1. Principle of Operation A SPI serves as an 8 or 9 bit wide input/output shift register. Either an internally or an externally generated clock can be used to shift data in and out. The input SPIx-D-IN is connected to the LSB of the shift register. The output of the shift register is connected to output signal SPIx-D-OUT. Thus each time a frame is transmitted by shifting bits out, bits are shifted in simultaneously and vice versa. Deglitchers in the data and clock input paths are active only in external clock mode. The input and output can be inverted by HW Option. If the deglitcher is active, input changes polarity after three consecutive samples have shown the same new polarity. Thus, a delay of three oscillator clock cycles is introduced. This feature imposes a limit on the maximum transmission frequency. Table 22-1: Module specific settings Module HW Options Initialization Name Item Address Item Setting All SPIs F0SPI SP0C clock F1SPI SP1C clock F2SPI SP2C clock SPI0 The interrupt is generated after the last bit is clocked out. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). D in inversion SP0C SPI0-D- U3.5 IN special input in D out inversion SP0C SPI0-D- U3.6 OUT special output out Prescaler SMC SPI0CLK-IN input U3.4 special in SPI0CLKOUT output U3.4 special out 22.1.2. Hardware settings Clock frequency settings and the polarity of the data connections of the SPIs are settable by HW Options (Table 22-1). Refer to "HW Options" for setting them. 22.1.3. Initialization After reset, a SPI is in standby mode (inactive). Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as data in- or outputs and clock in- or outputs has to be made (Table 22-1). Refer to "Ports" for details. SPI1 D in inversion SP1C SPI1-D- U4.0 IN special input in D out inversion SP1C SPI1-D- U4.1 OUT special output out Prescaler SMC SPI1CLK-IN input U3.7 special in SPI1CLKOUT output U3.7 special out For entering active mode of a SPI, set the respective enable bit (Table 22-1). Prior to operation, the desired clock frequency and telegram length have to be selected. 22.1.3.1. Clock Source The SPI can be operated as clock master, using an internally generated clock, or as clock slave, using an externally generated clock. The flag INTERN must be set in the SPIxM Mode register to operate the SPI as clock master. There are several options for selection of the internal clock. Each input of a 3 to 1 multiplexer can be programmed by HW Options to a different frequency. These three input frequencies F0SPI, F1SPI and F2SPI are used for all SPIs. The output of the 3 to 1 multiplexer is programmed by way of clock selection field (CSF) in register SPIxM. This clock can be used as shift clock directly, inverted and divided by 1.5 or 2.5. The shift clock is output by signal SPIx-CLK-OUT. 128 Enable Bit SR0. SPI0 SR0. SPI1 If flag INTERN is zero, the SPI operates as clock slave and an externally generated clock is used. The external clock is input by signal SPIx-CLK-IN. The polarity and the sampling edge of the clock is defined by field SCLK in register SPIxM. 22.1.3.2. Telegram Length Flag LEN9 in register SPIxM defines the length of a transferred frame. The ninth bit of the shift register is read or written at the location of flag BIT8 in register SPIxM. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 22.1.1. General CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 22.1.4. Operation 22.1.5. Inactivation 22.1.4.1. Transmit Mode Transmission is initiated by a write access to data register SPIxD. The SPI will immediately begin transmitting the selected number of data bits out from its shift register, in synchronism with the selected clock. A write access during a transmission is ignored. The frame is transmitted MSB first. In nine-bit mode flag BIT8 is MSB of the shift register (Fig. 22-2 to 22-5). At the end of the frame, an interrupt source signal is generated which may be selected to trigger an interrupt. 22.1.4.2. Receive Mode The receive mode must be activated by a write access to register SPIxD. The SPI will immediately begin clocking in the selected number of data bits into its shift register, in synchronism with the selected clock. At the end of the frame, an interrupt source signal is generated which may be selected to trigger an interrupt. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 22.1.4.3. DMA Please refer to section "DMA" for information about operation of the SPI in DMA mode. Returning a SPI module to standby mode by resetting its respective enable bit (Table 22-1) will immediately terminate any running receive or transmit operation and will reset all internal registers. 22.1.6. Precautions A single wire bus is easiest implemented by a wired-or configuration of the SPIx-D-OUT output port and the open drain output of the external transmitter: simply configure the SPIx-D-OUT output port in Port Slow mode, always operate it in Port Special Output mode and connect it directly to the external open drain output. An external pull-up resistor is not necessary in this configuration because the SPIx-D-OUT output port supplies the necessary pull-up drive. If the SPIx-D-OUT output port has to be operated in Port Fast mode, this simple scheme is not possible, because the pull-down action of the external open drain output may exceed the absolute maximum current rating of the SPIx-DOUT output port. A discrete external wired-or is recommended for this situation. During operation, make sure, that the external clock does not start until after SPIxD has been written, otherwise correct data transfer is not be guaranteed. 22.2. Registers The following registers are available once for SPI0 and SPI1 each. SPIxD 7 5 4 3 2 Sample Clock Clock polarity and edge of data sampling. (Table 22-2) Table 22-2: SCLK usage SPI x Data Register 6 SCLK r/w: 1 0 SCLK r/w Bit 7 to 0 of Rx/Tx Data 0 0 SPIxM r/w 0 0 0 0 0 0 SPI x Mode Register 7 6 BIT8 LEN9 0 0 5 4 3 RXSEL INTERN 0 0 2 1 SCLK 0 0 CSF 0 0 0 BIT8 Bit 8 of Rx/Tx Data r/w: Rx/Tx data bit. In 8 bit mode (LEN9 = 0) this bit is undefined when read. LEN9 r/w0: r/w1: Frame Length 9 Bit Selection 8 bit mode. 9 bit mode. RXSEL r/w0: r/w1: Receive Selection Input active. Low level at input. INTERN r/w0: r/w1: Internal/External Clock Selection Use external clock. Use internal clock. Micronas Res 1 0 0 0 0 1 1 0 1 1 Clock Polarity Sampling Edge See Fig. low falling 22-3 rising 22-5 rising 22-2 falling 22-4 high Res CSF wr: Clock Selection Field Source of internal clock (Table 22-3) Table 22-3: CSF usage CSF Source of internal clock 1 0 0 0 F0SPI 0 1 F1SPI 1 x F2SPI 129 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 22.3. Timing wr SPIxD clk out SPIx-D-OUT D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx Int. Src. Fig. 22-2: Nine bit frame. Data valid at rising edge. Clock inactive high wr SPIxD SPIx-D-OUT D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D7 D6 D5 D4 D3 D2 D1 D0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. clk out SPIx Int. Src. Fig. 22-3: Eight bit frame. Data valid at falling edge. Clock inactive low wr SPIxD clk out SPIx-D-OUT D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D8 D7 D6 D5 D4 D3 D2 D1 D0 SPIx Int. Src. Fig. 22-4: Nine bit frame. Data valid at falling edge. Clock inactive high wr SPIxD clk out SPIx-D-OUT D7 D6 D5 D4 D3 D2 D1 D0 SPIx-D-IN D7 D6 D5 D4 D3 D2 D1 D0 SPIx Int. Src. Fig. 22-5: Eight bit frame. Data valid at rising edge. Clock inactive low 130 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 23. Universal Asynchronous Receiver Transmitter (UART) A UART provides a serial Receiver/Transmitter. A 7bit or 8bit telegram can be transferred asynchronously with or without a parity bit and with one or two stop bits. A 13bit baud rate generator allows a wide variety of baud rates. A two word receive FIFO unburdens the SW. Incoming telegrams are compared with a register value. Interrupts can be triggered on transmission complete, reception complete, compare and break. Features The number of UARTs implemented is given in Table 23-1. The "x" in register names distinguishes the module number. - Two word receive FIFO. UAxIF 2 1 0 - Full duplex. - 7bit or 8bit frames. - Parity: None, odd or even. - One or two stop bits. - Receive compare register. - 13bit baud rate generator. UAxIM 2 r 1 UAxD w 0 w RCVD BRK RCVD BRK ADR = 8 8 3 >1 compare address register 8 & & break & received 2 of 3 rx shift register rx 4 rx control TBUSY FULL EMPTY PAER OVRR FRER BRKD tx control RBUSY 3 2 1 0 r 7 6 5 4 3 2 1 0 w clk tx UAxD tx data register w 4 UAxBR1 f0 1 LEN 4 PAR 5 ODD 6 UAxC tx tx shift register 7 STPB All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADR rx FIFO UART Interrupt Source UAxCA r 5 bit down cnt zero UAxBR0 clk 8 bit down counter 1/8 fBR fsample zero Fig. 23-1: Block Diagram Micronas 131 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 23.1. Principle of Operation 23.1.1. General 23.1.3. Initialization A UART module contains a receive shift register that serves to receive a telegram via its RX input. A FIFO is affixed to it that stores two previously received telegrams. After reset, a UART is in standby mode (inactive). Other features include a receive compare function, flexible interrupt generation and handling, and a set of control, error and status flags that facilitate management of the UART by SW. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. A programmable baud rate generator generates the required bit clock frequency. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). A UART module is only capable to receive telegrams that differ by no more than 2.5% from its own baud rate setting. 23.1.2. Hardware settings The polarity of most RX and TX connections of the UART is settable by HW Options (See table 23-1 and figure 23-2). Refer to "HW Options" for setting them. 0 clk 23.1.3.1. Baud Rate Generator The receive and transmit baud rate is internally generated. The Baud Rate registers UAxBR0 (low byte) and UAxBR1 (high byte) serve to enter the desired 13bit setting. Write UAxBR0 first, UAxBR1 last. The baud rate generator is a 13bit down-counter which is clocked by f0. It generates the sample frequency: f0 f sample = ------------------------------------------------------------------------------Value of Baud Rate Registers + 1 Its output frequency fsample is divided by eight to generate the baud rate (bit/second). UARTx-TX tx f0 Prior to operation, the desired baud rate, telegram format, compare address and interrupt source configuration have to be made. f sample f0 = -------------BR = ---------------------------------------------------------------------------------------------( Value of Baud Rate Registers + 1 ) x 8 8 HW Option SR0.UARTx For entering active mode of a UART, set the respective enable bit (Table 23-1). SO 1 1 UARTx f0 Value of Baud Rate Registers = -----------------1 BR x 8 UARTx-RX 0 rx 1 SI 1 HW Option Fig. 23-2: Context Diagram 23.1.3.2. Telegram Format The format of a telegram is configured in the Control and Status register UAxC. A telegram starts with a start bit followed by the data field. The data field consists of 7 or 8 data bit. There can be a parity bit after the data field. The telegram is finished by one or two stop bits (see Table 23-3 on page 136). 132 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. A transmit shift register serves to transmit a telegram via its TX output. Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as RX input and TX output has to be made (Table 23-1). The RX port has to be configured Special In and the TX port has to be configured Special Out. Refer to "Ports" for details. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 23-1: Module specific settings Module Name HW Options UART0 Initialization Item Address Item Setting RX inversion UA0 UART0-RX input U2.5 special in UART0-TX output U2.4 special out UART1-RX input U2.3 special in UART1-TX output U2.2 special out TX inversion UART1 Enable Bit RX inversion UA1 TX inversion SR0.UART0 SR0.UART1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ter UAxIF and can be enabled by setting bits in the Interrupt Mask register UAxIM. S 0 1 2 3 4 5 6 7 P T0 T1 S 0 1 2 3 4 5 6 7 T0 T1 S 0 1 2 3 4 5 6 T0 S 0 1 2 3 4 5 6 S = Start bit P = Parity bit 1. When the flag TBUSY in register UAxC is set to zero, the interrupt source output is triggered. This indicates that a transmission is finished and the transmit buffer is empty. There is neither an interrupt flag to indicate this event, nor a mask flag to disable this interrupt. 2. RCVD is generated by the receive control logic at the end of each received telegram even if the FIFO is full. This signal is enabled by setting the corresponding bit in register UAxIM. 7 P T0 T0 = 1. stop bit T1 = 2. stop bit 3. BRK is generated by the receive control logic each time a break is detected. This signal is enabled by setting the corresponding bit in register UAxIM. 4. ADR is generated by the address comparator. This signal is enabled by setting the corresponding bit in register UAxIM. Fig. 23-3: Examples of Telegram Formats The level of the start bit is always opposite to the neutral level. The level of the stop bits is always the same as the neutral level. If a parity bit is programmed, odd or even parity can be selected. Table 23-2: Definition of Parity Bit BRK and ADR also set flags in the Interrupt Flag register UAxIF when enabled. The first RCVD interrupt, when the FIFO has been empty before, sets a flag in UAxIF too. Even if all interrupts are enabled in register UAxIM, the interrupt source output is triggered only once within a telegram. UAxIF flags remain valid until the end of the next telegram. ADR is not generated and the ADR flag is not set if a frame or parity error was detected in the corresponding telegram. Parity Flag Number of Ones Parity Bit 23.1.4. Operation odd odd 0 odd even 1 With proper HW configuration and SW initialization, a UART module is ready to transmit and receive telegrams in the selected format. even odd 1 23.1.4.1. Transmit even even 0 A write access to UART Data register UAxD immediately loads the transmit shift register and starts transmission with sending the start bit. The flag TBUSY in register UAxD is set. As a general rule, the parity bit completes the number of ones in the data field to the selected parity. 23.1.3.3. Compare Address The content of the Compare Address register UAxCA is compared with each received telegram. On a match, the interrupt flag ADR is set and the interrupt source signal is triggered. The MSB of register UAxCA must be set to zero if transmission of a seven bit data field is configured in register UAxC. 23.1.3.4. Interrupt Four signals can trigger the UART interrupt source output. Three of them set their own flags in the Interrupt Flag regis- Micronas At the end of transmission the interrupt source signal is triggered and the flag TBUSY is reset. To avoid data corruption, ensure that flag TBUSY is LOW before writing to UAxD 23.1.4.2. Receive A first negative edge of a telegram on the RX line of a UART starts a receive cycle and sets the flag RBUSY in UAxC. After reception of the last bit of the telegram, the telegram content, together with its status information, is transferred to the receive FIFO and an interrupt is generated. RBUSY is resetted. Telegram data are available in register UAxD, telegram status in register UAxC. 133 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 During reception, the following checks are performed according to the register UAxC setting: too. The flags PAER, FRER and BRKD in register UAxC apply to a certain telegram and are thus double buffered. 1. A parity error is detected if the parity of the received telegram does not match the programmed parity. The flag PAER in register UAxC is set in this case. Differing telegram length settings in register UAxC and receiver may also cause parity errors. The receive FIFO is full if two telegrams were received but the SW did not yet read register UAxD. If there is a third telegram, it is not written to the FIFO and its data are lost. The flags EMPTY, FULL and OVRR show the status of the FIFO. EMPTY indicates that there is no entry in the FIFO. FULL will be set with the second entry in the receive FIFO and indicates that there is no more entry free. OVRR indicates that there was a third telegram which could not be written to the FIFO. 3. A break condition is detected if the receive input remains low for one complete telegram duration. When a break starts during telegram, this condition must extend over another telegram length to be properly detected. This event sets the flag BRKD in register UAxC and can trigger the interrupt source output if enabled. After a break, the receive input must be high for at least 1/4 of the bit length before a new telegram can be received. Telegrams of an external RS232 interface are correctly received, even if they are transmitted without gaps (the start bit immediately follows the stop bit of the preceding telegram). 23.1.4.3. Receive FIFO The receive FIFO is able to buffer the data fields of two consecutive telegrams. But not only the data field of a telegram is double buffered, the related information is double buffered Status flags are readable as long as the corresponding data field was not read from register UAxD. As soon as a FIFO entry is read out, the status flags of this entry are lost. They are overwritten by the flags of the second entry. SW first has to read the flags and then the corresponding FIFO entry. The flags PAER, FRER and BRKD apply to a certain telegram and are only valid if there is at least one entry in the FIFO (EMPTY = 0). The flags EMPTY, FULL and OVRR apply to the FIFO and are valid all the time. 23.1.5. Inactivation Returning a UART module to standby mode by resetting its respective enable bit (Table 23-1) will immediately terminate any running receive or transmit operation and will reset all internal registers. 23.2. Timing The duration of a telegram results from the total telegram length in bits (LTG) (see Table 23-3 on page 136) and the baud rate (BR). L TG t TG = --------BR The incoming signal is sampled with the sample frequency and filtered by a 2 of 3 majority filter. A falling edge at the output of the majority filter starts the receive timing frame for the telegram. An individual bit is sampled with the fifth sample clock pulse within that timing frame (cf. Fig. 23-4 and 23-5). If a bit was the last bit of its telegram, reception of a new telegram can start immediately after this sample. With a receive telegram, interrupt source is triggered and flags are set just after the sample of the last stop bit. With a transmit telegram, interrupt source is triggered and BUSY reset after the nominal end of the last stop bit. 134 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 2. A frame error is detected if the level of start or stop bits violate the transmission rule. The flag FRER in register UAxC is set in this case. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION rxdat asynchron Rx Interrupts Micronas CDC32xxG-B V3.0 3 DEC 01 1 rxdat asynchron start 1 2 2 3 3 1. stopbit 4 4 5 5 6 6 7 7 8 fsample startbit bit 0 2. stopbit bit 1 1. sample 2. sample 3. sample indicates the recognition of the low level of the filtered input signal data sample clock Fig. 23-4: Start of Telegram fsample 8 startbit 1. sample 2. sample 3. sample start data sample clock Flags are set Tx Interrupt BUSY Fig. 23-5: End of Telegram 135 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 23.3. Registers UAxD 7 LEN w0: w1: UART x Data Register 6 5 4 3 r Receive register w Transmit register 2 1 Length of Frame 7bit frame. 8bit frame. 0 x x x UAxC 7 r RBUSY w x x x x x Res UART x Control and Status Register 6 5 4 3 2 1 0 BRKD FRER OVRR PAER EMPTY FULL TBUSY 0 x x 0 x 1 0 0 x x x x STPB ODD PAR LEN x x x x 0 0 0 0 RBUSY r0: r1: Receiver Busy Not busy. Busy. BRKD r0: r1: Break Detected No break. Break. FRER r0: r1: Frame Error Detected No error. Error. OVRR r0: r1: Overrun Detected No overrun. Overrun. PAER r0: r1: Parity Error Detected No error. Error. Res Res EMPTY Rx FIFO Empty r0: Not empty. r1: Empty. There is at least one entry present if EMPTY is zero. PAER, FRER and BRKD are not valid if EMPTY is set. FULL r0: r1: Rx FIFO Full Not full. Full. TBUSY Transmitter Busy r0: Not busy. r1: Busy. Do not write to register UAxD as long as BUSY is true. STPB w0: w1: Stop Bits One stop bit. Two stop bits. ODD w0: w1: Odd Parity Even parity. Odd parity. PAR w0: w1: Parity On No parity. Parity on. 136 LEN PAR STPB Format LTG 0 0 0 S, 7D, T0 9 0 0 1 S, 7D, T0, T1 10 0 1 0 S, 7D, P, T0 10 0 1 1 S, 7D, P, T0, T1 11 1 0 0 S, 8D, T0 10 1 0 1 S, 8D, T0, T1 11 1 1 0 S, 8D, P, T0 11 1 1 1 S, 8D, P, T0, T1 12 UAxBR0 UART x Baud Rate Register low byte 7 6 5 w 3 2 1 0 0 0 0 Bit 7 to 0 of Baud Rate 0 0 UAxBR1 0 0 0 Res UART x Baud Rate Register high byte 7 w 4 6 5 x x x - - - 4 3 2 1 0 Bit 12 to 8 of Baud Rate 0 0 0 0 0 Res The Baud Rate Registers UAxBR0 and UAxBR1 have to be written low byte first to avoid inconsistencies. UAxBR0 is the low byte. Valid entries in the Baud Rate Registers range from 1 to 8191. Don't operate the baud rate generator with its reset value zero. UAxCA 7 UART x Compare Address Register 6 5 w 4 3 2 1 0 0 0 0 Bit 7 to 0 of address 0 0 0 0 0 Res Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Table 23-3: Telegram Format and Length CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 UAxIM w UART x Interrupt Mask Register 7 6 5 4 3 2 1 0 x x x x x ADR BRK RCVD - - - - - 0 0 0 ADR w0: w1: Mask Compare Address Detected Disable interrupt. Enable interrupt. BRK w0: w1: Mask Break Detected Disable interrupt. Enable interrupt. RCVD w0: w1: Mask Received a Telegram Disable interrupt. Enable interrupt. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. UAxIF r UART x Interrupt Flag Register 7 6 5 4 3 2 1 0 Test Test Test Test Test ADR BRK RCVD - - - - - x 0 0 Test Reserved for test (do not use) ADR r0: r1: Compare Address Detected No Interrupt. Interrupt pending. BRK r0: r1: Break Detected No Interrupt. Interrupt pending. RCVD r0: r1: Received a Telegram No Interrupt. Interrupt pending. Micronas Res Res 137 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 138 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 24. I2C-Bus Master Interface The IC contains two independent I2C-bus Master Interface units (I2C), 0 and 1. They are pure master systems, multi master busses are not realizable. The units contain read and write buffers with interrupt logic which makes automatic and software independent operation possible for most types of I2C telegrams. Because of the internal clock pre scaler, telegram clock rate does not depend on system clock rate. WR_Data (subaddress=control info) Address Decoder D0 to D7 WR 0 Write FIFO 5 x 11 half full f1 1 SR0.I2Cx empty control in 2 Write Logic out SR SDAx SCLx busy I2CMx.DGL Read Logic Read FIFO 3x8 empty S R S R Q Q RD_Data Start Condition resets ACK flags ADR_ACK D0 to D7 Deglitcher Ack = 0 received DAT_ACK All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Clock Prescaler Status Register I2C Interrupt Source D0 to D7 RD_Status Fig. 24-1: Block diagram of I2C-Bus Master Interface Micronas 139 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 24.1. Principle of Operation 24.1.1. General value. By default, the input deglitcher is on, which limits the obtainable bit rate to 208.3kbit/s (see Table 24-2). 24.1.2. Hardware Settings In standby mode the clock is halted, no information processing is possible. It is recommended to exit standby mode before programming any of the I2C registers. See section "Core Logic" for details. Since the telegram clock rate is register programable there is no HW option for the I2C-Bus Master Interface. 24.1.3. Initialization After system reset the I2C is in standby mode, i.e. the block internal clock is halted and all registers are set to their reset Prior to operation, proper SW configuration of the U-Ports assigned to function as I2C Double Pull-down port has to be made. See table 24-1 and section "Ports" for details. Table 24-1: Module specific settings I2C0 HW Options Initialization Enable Bit Item Address Item Setting U2.0 CAN0/SCL0 output multiplexer PM.U20 SCL0 U2.0 special out, double pull-down mode SR0.I2C0 SDA0 U2.1 special out, double pull-down mode SCL1 U5.1 special out, double pull-down mode SR0.I2C1 SDA1 U5.2 special out, double pull-down mode U2.1 CAN0/SDA0 output multiplexer I2C1 After exiting standby mode only the bit rate and the desired input deglitcher configuration has to be set up in register I2CMx in order to get into an active and useful mode. All other registers serve I2C data I/O purposes. If telegrams longer than 3 bytes (1 address, 2 data bytes) are received, the software must check the filling condition of the Write-FIFO and, if necessary, fill it up and read out the Read-FIFO. A variety of status flags is available for this purpose: 24.1.4. Operation - The `half full' flag I2CRSx.WFH is set if the Write-FIFO is filled with exactly three bytes. A complete telegram is assembled by the software out of individual sections. Each section contains 8-bit data. This data is written into one of the six possible write registers. Depending on the chosen address, a certain part of an I2C-bus cycle is generated: start, data, stop, with or without acknowledge. By means of corresponding calling sequences it is therefore possible to join even very long telegrams (e.g. long data files for auto increment addressing of I2C slaves). - The `empty' flag I2CRSx.RFE is set if there is no more data available in the Read-FIFO. - The `busy' flag I2CRSx.BUSY is activated by writing any byte to any one of the Write registers. It stays active until the I2C-bus activities are stopped after the stop condition generation. The software interface contains a 5 word deep Write-FIFO for the control-data registers as well as a 3 word deep ReadFIFO for the received data. Thus most of the I2C telegrams can be transmitted to the hardware without the software having to wait for empty space in the FIFO. Moreover the ACK-bit is recorded separately on the bus lines for the address and the data fields. However, the interface itself can set the address ACK=0. In any case the two ACK flags show the actual bus condition. These flags will be reset with the next I2C start condition. An interrupt is generated on two conditions: There is only one data acknowledge (DACK) flag available. It will be cleared to zero with the reception of the first received zero within the acknowledge field of a data byte. Thus it indicates that at least one of the data bytes was acknowledged. - The Write-FIFO was filled with 5 entries and reaches the `half full' state. - The Write-FIFO is empty and stop condition is completed. There is no `Write-FIFO half full' interrupt unless the WriteFIFO was previously filled completely. Disabled interrupts during filling guarantees this requirement. All address and data fields appearing on the bus are constantly monitored and written into the Read-FIFO. The software can then check these data in comparison with the scheduled data. The bus activity starts immediately after the first write to the Write-FIFO. The transmission can be synchronized by an artificial extension of the low phase of the clock line. Transmission is not continued until the state of the clock line is high once again. Thus an I2C slave device can adjust the transmission rate to its own abilities. The figures 24-2, 24-3 and 24-4 show the basic principle of I2C telegram transmission as a quick reference. Refer to the official I2C documentation for more details. If a read instruction is handled, the interface must send the data word 0xFF so that the responding slave can insert its data. In this case the Read-FIFO contains the read-in data. 140 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Module Name CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 24.1.4.1. Example of Operation The software has to work in the following sequence (ACK=1) to read a 16-bit word from an I2C device address 0x10 (on condition that the bus is not active): -write 0x21 to -write 0xFF to -write 0xFF to -read RFE bit from -read dev. address from -read RFE bit from -read 1st databyte from -read RFE bit from -read 2nddatabyte from I2CWS0x I2CWD0x I2CWP1x I2CRSx I2CRDx I2CRSx I2CRDx I2CRSx I2CRDx 1T SDA SCL 1/2T The value 0x21 in the first step results from the device address in the 7 MSBs and the R/W-bit (read=1) in the LSB. If the telegrams are longer, the software has to ensure that neither the Write-FIFO nor the Read-FIFO can overflow. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. To write data to this device: -write 0x20 to -write 1st databyte to -write 2nd databyte to Note: The I2C block uses U-Ports as connection to the outside world. This implies that neither logic output low level switching specs nor logic input value specs of the official I2C specification document are literally met. Refer to section "Ports" for the actual spec values of this implementation. I2CWS0x I2CWD0x I2CWP0x 1T 1/4T Fig. 24-2: Start or Restart Condition I2C-Bus 1T SDA repeated 8 times 24.1.5. Inactivation SCL I2C master, all I2C bus activis reached. I2C slaves can Since the described block is an ity stops if the end of a telegram not start any bus activity on their own. However, the block internal clock is always running at full speed of I2C clock (4 or 5 MHz), independent of the bit rate divider setting. The standby mode is therefore intended for the lowest possible power consumption. Make sure to switch off the module only if it is not active. Switching off during transmission of a telegram may cause an output to stay at low level. Hence lowest possible power consumption can't be achieved because SDA and SCL use open drain output ports. 1/4T Fig. 24-3: Single Bit on I2C-Bus SDA SCL 3/4T 1/4T 24.1.6. Precautions 1/4T 1/2T Fig. 24-4: Stop Condition I2C-Bus For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 24.2. Registers I2CWS0x 7 w I2C Write Start Register 0 6 5 4 3 2 1 I2CWS1x 0 7 I2C Address 0x00 w Res Writing this register moves I2C start condition, I2C Address and ACK=1 into the Write FIFO. Micronas I2C Write Start Register 1 6 5 4 3 2 1 0 I2C Address 0x00 Res Writing this register moves I2C start condition, I2C Address and ACK=0 into the Write FIFO. 141 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 7 I2C Write Data Register 0 6 5 w 4 3 2 1 0 I2C Data 0x00 7 I2C Write Data Register 1 6 5 w 4 DACK r1: r0: Data Acknowledge Not acknowledged (received a one) Acknowledged (received a zero) BUSY r1: r0: Busy I2C Master Interface is busy. I2C Master Interface is not busy. WFH r1: r0: Write-FIFO Half Full Write-FIFO is contains exactly 3 bytes. Write-FIFO is contains more or less than 3 bytes. RFE r1: r0: Read-FIFO Empty Read-FIFO is empty. Read-FIFO is not empty. Res Writing this register moves I2C Data and ACK=1 into the Write FIFO. I2CWD1x Address Acknowledge Not acknowledged (received a one) Acknowledged (received a zero) 3 2 1 0 I2C Data 0x00 Res Writing this register moves I2C Data and ACK=0 into the Write FIFO. I2CMx 7 I2CWP0x 7 w I2C Write Stop Register 0 6 5 w 4 3 2 1 0x00 Res Writing this register moves I2C Data, ACK=1 and I2C stop condition into the Write FIFO. 7 6 5 4 3 2 1 I2C Data 1 0x02 I2CRDx I2C Read Data Register 6 5 r 4 3 2 1 1 0 Res Speed Select (Table 24-2) I2C Bit Rate = f1 / (4 * SPEED). I2C Data Res Reading this register returns the content of the Read FIFO. I2CRSx SPEED f1 Division by Bit Rate @ f1=5MHz Bit Rate @ f1=4MHz 0 128*4 (!) 9.8 kbit/s 7.8 kbit/s 1 1) 1*4 1.25 Mbit/s 1.00 Mbit/s 2 1) 2*4 625 kbit/s 500 kbit/s 3 1) 3*4 416.7 kbit/s 333.3 kbit/s 4 1) 4*4 312.5 kbit/s 250 kbit/s 5 1) 5*4 250 kbit/s 200 kbit/s 6 6*4 208.3 kbit/s 166.7 kbit/s 7 7*4 178.6 kbit/s 142.9 kbit/s 0 0x00 142 2 DGL Input Deglitcher w1: Deglitcher is active. w0: Deglitcher is bypassed. If the deglitcher is active, the maximum bit rate is limited. SPEED must be programmed to 6 at least. The maximum bit rate may be further reduced by the bus load. Res Writing this register moves I2C Data, ACK=0 and I2C stop condition into the Write FIFO. OACK r: 3 Table 24-2: SPEED Usage: I2C Bit Rates 0 0x00 r 4 I2C Write Stop Register 1 w 7 5 SPEED SPEED w: I2CWP1x 6 DGL 0 I2C Data I2C Mode Register ... I2C Read Status Register 7 6 5 4 3 2 1 0 x OACK AACK DACK BUSY WFH RFE x 0 0 0 0 0 0 0 0 127 Res ... 127*4 9.8 kbit/s 7.9 kbit/s 1) These bit rates may only be set with a bypassed input deglitcher (I2CMx.DGL=0) "OR"ed Acknowledge AACK OR DACK. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. I2CWD0x AACK r1: r0: CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 25. CAN Manual This manual describes the user interface of the CAN module. For further information about the CAN bus, please refer to the CAN specification 2.0B from Bosch. Features - Bus controller according to CAN Licence Specification 1992 2.0B - Supports standard and extended telegrams - FullCAN: up to 32 Rx and Tx telegrams - Variable number of receive buffers - Programmable acceptance filter Single, group or all telegrams received. - Time stamp for each telegram - Overwrite mode programmable for each telegram All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. - Programmable baud rate. Max. 1 MBd @ 8 MHz - Sleep mode The CAN interface is a VLSI module which enables coupling to a serial bus in compliance with CAN specification 2.0B. It controls the receiving and sending of telegrams, searches for Tx telegrams and interrupts and carries out acceptance filtering. It supports transmission of telegrams with standard (11 bit) and extended (29 bit) addresses. The CAN interface can be configured as BasicCAN or FullCAN. It enables several active receive and transmit telegrams and supports the remote transmission request. The number of telegrams which can be handled depends mainly on the size of the communication RAM (16 byte per telegram), the system clock and the transmission speed. A maximum of 254 telegrams can be handled. A mask register makes it possible to receive different groups of telegram addresses with different receive telegrams. Transmitting or receiving of a telegram as well as the occurrence of an error can trigger an interrupt. CPU Address CAN Bus Error Managem. Logic Global Control and Status Register Data Interrupt Source CAN RAM (Com. Area) Bit Timing Logic f0 Rx. Obj. Protocol Manager Interface Managm. Logic Tx. Obj. Rx/TxBuffer Fig. 25-1: Block diagram of the CAN bus interface Micronas 143 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 BI CAN Bus Interface ID Identifier BTL Bit Timing Logic IML Interface Management Logic CAN Controller Area Network Rx. Obj. Receive Object CA Communication Area RxTg Receive Telegram CO Communication Object Std. ID Standard Identifier CM Communication Mode Std. Tg Standard Telegram CRC Cyclic Redundancy Code TD Telegram Descriptor DLC Data Length Code Tg Telegram EoCA End of CA TQ Time Quantum Ext. ID Extended Identifier Tx. Obj. Transmit Object Ext. Tg Extended Telegram TxTg Transmit Telegram GCS Global Control and Status Register 25.2. Functional Description 25.2.1. HW Description The CAN bus interface consists of the following components: Bit Timing Logic: Scans the bus and synchronizes the CAN bus controller to the bus signal. Protocol Manager: The PM monitors or generates the composition of a telegram and performs the arbitration, the CRC and the bit stuffing. It controls the data flow between Rx/Tx buffer and CAN bus. It also drives the Error Management Logic. Error Management Logic: Adds up the error messages received from the protocol manager and generates error messages when particular values are exceeded. Guarantees the error limitation as per the CAN Spec. V2.0B. Interface Management Logic: The IML scans the Communication Area (CA) in the CAN-RAM for transmit telegrams. As soon as it finds one, it enters it into the Rx/Tx buffer and reports it to the protocol manager as ready for transmission. If a telegram is received, the IML carries out the acceptance filtering, i.e. scans the CA, taking into account the Identifier Mask Register in the GCS, for a Tg with the appropriate address. After correct reception, it copies the Tg from the Rx/ Tx buffer to the CA. The IML also reports to the CPU the valid transfer of a telegram or given errors per interrupt. The interrupt source output of this module is routed to the Interrupt Controller logic. But this does not necessarily select it as input to the Interrupt Controller. Check section "Interrupt Controller" for the actually selectable sources and how to select them. Rx/Tx buffer: This is used to buffer a full telegram (ID, DLC, data) during sending and receiving. Global Control and Status Register: The GCS contains registers for the configuration of the BI. It also contains error and status flags and an identifier mask. The Error Counter and the Capture Timer can be read from the GCS. 144 Receive Object: The BI enters received telegrams into a matching Rx-Object. It can be retrieved from the application. Transmit Object: The application enters data into the TxObject and reports it ready for transmission. The BI sends the telegram as soon as the bus traffic allows. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 25.2.2. Memory Map From the CAN bus interface the user sees two storage areas in the user RAM area. The BI is configured with the Global Control and Status Registers (GCS). It also indicates the status here. The communication area (CA) contains the Rx and Tx telegrams. The communication area lies in the CAN-RAM. The end of the Com. Area is fixed by the first control byte of an object whose 3 MSBs contain only ones (Communication Mode = 7 = EoCA). The area after this is available to the user. The CA consists of communication objects (COs). A CO consists of 6 bytes telegram descriptor (TD), 8 data bytes and the Time Stamp which is 2 bytes long. The TD contains the address (ID) and the length of a telegram (DLC) as well as control bits which are needed for access to the CO and for the transmission of a telegram. In the BasicCAN and the FullCAN versions, all the communication objects have the same, maximum size of 16 byte. Unassigned storage locations in the data area of a CO can be freely used. The maximum number of COs is limited by the time which the CAN interface has to search for an identifier in the Com. Area. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 25.1. Abbreviations CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 25.2.3. Global Control and Status Registers (GCS) timing, error status, output control registers, baud rate prescalers, Tx and Rx error counters as well as the capture timer. The GCS registers can be used to determine the behavior of the CAN interface. As well as flags for the interrupts, halt and sleep modes, they also contain interrupt index, ID mask, bus Communication Area Global Control and Status CTR STR ESTR IDX All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 0 Control Status Error Status Interrupt Index ID Mask 28 ... 21 ID Mask 20 ... 13 ID Mask 12 ... 5 ID Mask 4 ... 0 Bit Timing 1 Bit Timing 2 Bit Timing 3 Input Control Output Control Transmit Error Counter Receive Error Counter 15 Capture Timer low 16 Capture Timer high 0 Control 1 ID 28 ... 21 2 ID 20 ...13 ID 12 ... 5 ID 4 ... 0 and Control DLC and Control Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Time Stamp low 15 Time Stamp high 16 TD IDM BT1 BT2 BT3 ICR OCR TEC REC CTIM Com.-Obj. 0 Telegram Descriptor TD Com.-Obj. 1 Data and Time Stamp 31 32 TD Com.-Obj. 2 Data and Time Stamp 47 n*16 TD Com.-Obj. n Data and Time Stamp n*16+15 (n+1)*16 Control: CM = 7 End of Com. Area Fig. 25-2: Memory allocation Puts the CAN interface in the halt mode. Transmissions which have been started are brought to an end. The halt acknowledge is indicated in the status register (HACK). Reinitialization can be carried out in the halt mode (HACK is set). After this, the halt flag must be deleted again. After a reset, HLT is set. Access modes: r: read w: write i: init (BI halted) w0: clear w1: set CANxCTR r/w Control Register 7 6 5 4 3 2 1 0 HLT SLP GRSC EIE GRIE GTIE rsvd rsvd 1 0 0 0 0 0 x x HLT r/w0: r/w1: Micronas If HLT is set during a Tx-Tg and this has to be repeated (error or no acknowledge), the BI stops yet. The corresponding TxCO is still reserved, however, and can no longer be operated from BI. Therefore, when HLT is set, the CA should always be re-initialized if the last Tx-Tg has not been correctly transmitted (Status Transfer Flag is still deleted). Halt Run. Halt. Res If HLT is set during the BI is in Bus-Off mode, the BI stops after Bus-Off mode is finished. Flag BOFF is cleared then and receive and transmit error counters are reset to zero. 145 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 GRSC Global Rescan r0: Don't rescan. r/w1: Rescan. The microprocessor can set this flag in order to initiate a transmit telegram search at the beginning of the Com. Area. The BI resets the bit. The BI also sets the GRSC flag if the flag RSC has been set in a telegram descriptor of a Tx-Tg just operated, and thereby initiates a rescan. If the microprocessor writes a zero, nothing happens. entered in the register CANxIDX as soon as it is free, and the interrupt source output is triggered. To erase a bit in the CANxESTR the user must write a one at the appropriate place. Places at which he writes a zero will not be changed. Because it makes sense to erase only those bits which have previously been read, only the byte which has been read has to be re-written. CANxESTR r/w Error Status Register 7 6 5 4 3 2 1 0 GDM CTOV ECNT BIT STF CRC FRM ACK 0 0 0 0 0 0 0 0 Res EIE r/w0: r/w1: Error-Interrupt-Enable Disabled. Enabled. Read-Modify-Write operations on single flags of this register must be avoided. Unwanted clearing of other flags of this register may be the result otherwise. GRIE r/w0: r/w1: Global Rx-Interrupt-Enable Disabled. Enabled. GTIE r/w0: r/w1: Global Tx-Interrupt-Enable Disabled. Enabled. GDM Good Morning r0: No wake-up. r1: Wake-up. w0: Unaffected. w1: Clear. Is set by the BI when it is aroused from the sleep mode by a dominant bus level. The user must delete it. CANxSTR r Status Register 7 6 5 4 3 2 1 0 HACK BOFF EPAS ERS rsvd rsvd rsvd rsvd 1 0 0 0 x x x x Res HACK Halt-Acknowledge r0: Running. r1: Halted. Is set by the BI when it enters the halt mode. It is deleted again when the halt mode is exited. BOFF Bus-Off r0: Bus active. r1: Bus off. With this flag the BI indicates whether the node is still actively participating in the bus. If the transmit error counter reaches a value of > 255 (overflow), the node is separated from the bus and the flag is set. EPAS Error-Passive r0: Error active. r1: Error passive. With this flag the BI indicates whether the node is still participating in the bus with active Error Frames. If an error counter has reached a value > 127, the node only transmits passive error frames and the flag is set. ERS Error-Status r0: No Errors. r1: Errors. This flag is set when the BI detects an error. It is set even if an error counter is greater than 96. It means that a bit has been set in the error status register. As soon as all the flags in the error status register are deleted, ERS is also deleted. As long as a bit is set in the CANxESTR, the ERS bit is also set in the status register. If EIE has been set in the control register, an interrupt is triggered too; i.e. the value 254 is 146 CTOV Capture Time Overflow r0: No overflow. r1: Overflow. w0: Unaffected. w1: Clear. Is set by the BI when the capture timer (CTIM) overflows. The user must delete it. ECNT Error Counter Level r0: No error counter. r1: Error counter. w0: Unaffected. w1: Clear. Is set by the BI as soon as the transmit error counter or the receive error counter exceeds a limit value. The user must delete it. BIT Bit Error r0: No bit error. r1: Bit error. w0: Unaffected. w1: Clear. Is set by the BI when a transmitted bit is not the same as the bit received. The user must delete the flag. STF Stuff Error r0: No stuff error. r1: Stuff error. w0: Unaffected. w1: Clear. Is set by the BI when 6 identical bits are received successively in one Tg. The user must delete it. CRC CRC Error r0: No stuff error. r1: Stuff error. w0: Unaffected. w1: Clear. Is set by the BI when the CRC received does not coincide with the CRC calculated. The user must delete it. FRM r0: Form Error No form error. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. SLP Sleep r/w0: Run. r/w1: Sleep. The BI goes into the sleep mode when the sleep flag is set and a started Tg is terminated. The sleep mode is finished as soon as a dominant bus level is detected, or the sleep flag is deleted. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 r1: Form error. w0: Unaffected. w1: Clear. Is set by the BI when an incorrect bit is received in a field with specified bit level (start of frame, end of frame, ...). The user must delete it. ACK Acknowledge Error r0: No acknowledge error. r1: Acknowledge error. w0: Unaffected. w1: Clear. Is set by the BI when there is no acknowledge for a transmitted Tg. The user must delete it. CANxIDX 7 Interrupt Index Register 6 5 r/w 4 3 2 1 1 1 1 BPR Baud Rate Pre-scaler r/w: Pre-scaler value. The baud rate pre-scaler sets the length of a time quantum for the bit timing logic. tQ = (BPR + 1) / f0. With the 6-bit counter it is possible to extend tQ by a factor of 1...64. Values from 0 to 63 are allowed. 0: tQ = 1 / f0 1: tQ = 2 / f0 2: tQ = 3 / f0 3: tQ = 4 / f0 1 1 1 1 7 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. r/w 7 r/w Identifier Mask Register 6 5 4 3 2 Identifier Mask Bits 4 to 0 x x x r/w Identifier Mask Bits 20 to 13 1 r/w Identifier Mask Bits 28 to 21 0 0 0 0 0 Res r/w0: Don't care. r/w1: Compare. The identifier mask register is 29 bits long; the MSB is in the MSB position in the lowest byte address. The CANxIDM defines a mask for the acceptance of address groups. Only the permitted bits are used for comparison with a received identifier. Whether the mask is used can be determined individually for each receive object. CANxBT1 r/w 6 MSAM SYN 0 0 Micronas 2 0 0 1 0 0 0 TSEG1 0 0 0 Res TSEG2 Time Segment 2 r/i: TSEG2 value. TSEG2 determines the number of time quanta after the sample point. Permitted entries: 1...7 (result in 2...8 TQ). TSEG1 Time Segment 1 r/i: TSEG1 value. TSEG1 determines the number of time quanta before the sample point. Permitted entries: 2...15 (result in 3...16 TQ). Bit Timing Register 3 7 6 5 4 3 rsvd rsvd rsvd rsvd rsvd x x x x x 2 1 0 SJW 0 0 0 Res SJW Synchronization Jump Width r/i: SJW value. SJW defines by how many TQs a bit may be lengthened or shortened because of resynchronization. Permitted entries: 1...4 (result in 1...4 TQ). Values greater than 4 must not be used. CANxICR r/w Input Control Register 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rsvd XREF REF1 REF0 x x x x x 0 0 0 Res Bit Timing Register 1 7 MSAM r/w0: r/w1: 3 TSEG2 0 r/w 0 4 3 2 0 rsvd 5 0 Identifier Mask Bits 12 to 5 0 Bit Timing Register 2 6 CANxBT3 1 r/w 0 etc. CANxBT2 The interrupt index indicates the source of the interrupt. If a transmission has been the cause of an interrupt, the interrupt index points to the corresponding telegram descriptor (CANxIDX = 0..253). If an error has been responsible for the interrupt, the interrupt index designates the error status register (CANxIDX = 254). After dealing with the interrupt, the user must eliminate the cause of the interrupt and set the interrupt index to minus one (255 = EMPTY). As soon as CANxIDX is empty, the BI can enter a new index and initiate an interrupt. An interrupt can only be initiated when CANxIDX contains the value 255. CANxIDM Sync On Synchronization with falling edges only. Synchronization with rising edges too. 0 Interrupt Index 1 SYN r/w0: r/w1: 5 4 3 2 1 0 0 0 0 BPR 0 0 0 Res Multi Sample Bus level is determined only once per bit. Bus level is determined three times per bit. XREF r/w0: r/w1: able. External Reference The internal reference is used. The external reference is used where avail- REF1 r/w0: r/w1: nal. Use Reference for RxD1 RxD is used as inverted input signal. Supply voltage is used as inverted input sig- 147 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Use Reference for RxD0 RxD is used as input signal. Ground is used as input signal. CANxOCR r/w The Capture Timer is incremented with a clock pulse derived from the CAN bus. Because it can only be read byte-wise, the low byte must be read first. The corresponding high byte is latched at the same time. When CANxCTIM overflows, the flag CTOV in the error status register is set. The Capture Timer will not be incremented during CAN module sleep mode (SLP = 1). Output Control Register 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rsvd rsvd rsvd ITX x x x x x x x 0 2 1 0 0 0 0 ITX r/w0: r/w1: Res Inverted transmission Tx output is not inverted. output is inverted. CANxTEC Transmit Error Counter 7 6 5 4 r 3 Counter Bit 7 to 0 0 0 0 CANxREC 7 r 25.2.4. Communication Area (CA) 0 6 5 4 3 2 1 0 0 0 The COs are entered in order of priority into the CA. This starts with the highest priority (the lowest identifier). The identifier defines the priority of a Tg. If the first eleven bits of an ext. Tg are the same as the identifier of a std. Tg, the Tg with standard identifier has higher priority. 0 0 0 0 0 Res Capture Timer 6 5 4 3 2 1 0 Timer Bit 15 to 8 1 r Timer Bit 7 to 0 0 0 0 0 0 0 0 0 25.2.4.1. Telegram Descriptor (TD) The telegram descriptor is 6 bytes (TD0 to TD5) long and forms the beginning of a CO. Telegrams with std. and ext. identifiers have different TDs. They differ only in the length of the identifiers. 18 bits therefore are not allocated in the TD of a std. Tg. They cannot be used by the application because they are overwritten by the reception of a Tg. r 0 Every telegram which this node is to receive or transmit is represented by a CO. As well as the data and the time stamp, this also contains a header, the telegram descriptor (TD), in which the attributes of the communication object are stored. Counter Bit 6 to 0 CANxCTIM 7 Res Receive Error Counter x x 0 The CA is located in the CAN-RAM. It consists of com. objects each of which is 16 bytes long. The CA begins at address 0 of the CAN-RAM with the first byte of a CO. It ends with the first byte of a CO which contains ones in its 3 MSBs (communication mode = 7 = EoCA). The following bytes can be used by the application. If the CAN-RAM is filled completely with COs, there is no place left and no need to mark the end of CA. Res Extended Addr. Format (EXF is set) 0 7 6 5 CM 4 3 Standard Addr. Format (EXF is deleted) 2 RSC MID OW 1 0 rsvd LCK 0 7 6 5 CM 4 1 28 ID 21 1 28 2 20 ID 13 2 20 3 12 ID 5 3 0 EXF RSR ACC 4 don't use 5 DLC 4 4 5 ID DLC TIE RIE SR TS 3 2 RSC MID OW 1 ID ID 0 rsvd LCK 21 18 don't use don't use EXF RSR ACC TIE RIE SR TS Fig. 25-3: Extended and Standard TD Map 148 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. REF0 r/w0: r/w1: CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Forms of access: r: read w: write i: init (BI halted or CM = inactive) w0: clear w1: set CM Communication Mode r/i: Mode. CM defines the type of telegram. 0: Inactive 1: Send 2: Receive 3: Fetch 4: Provide 5: Rx-All 6: rsvd 7: EoCA Inactive. No participation in the bus traffic. Send data. Receive data. Fetch data via remote frame. Have data fetched via remote frame. Receive every telegram. Don't use (provis. EoCA). End of Communication Area. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. As long as the CO is inactive (CM = 0) or locked (LCK = TRUE), the BI accesses the first byte of the CO only by reading. All other bytes are neither read nor written. The inactive mode is suitable therefore for re-configuration of a CO online; i.e. while the node is taking part in the bus traffic. RSC Rescan r/w0: Don't rescan. r/w1: Rescan. If the rescan bit has been set in a transmit object just processed, the search for active Tx objects is started at the beginning of the communication area. Otherwise, the search continues at this transmit object until the end of the CA is reached. From there, the system jumps back to the beginning of the CA. MID Mask Identifier r/w0: Don't mask. r/w1: Mask. If MID has been deleted, the identifier received is compared bit-by-bit with the identifier from the telegram descriptor, i.e. the entire identifier must be the same so that the telegram received is transferred into this CO. If MID has been set, only bits which are allowed in the ID mask register of the GCS are used for the comparison. OW Overwrite r/w0: Don't overwrite. r/w1: Overwrite. When OW is set, the com. object may be overwritten even if the application has not yet fetched the contents (TS set). The BI must of course obtain right of access (LCK deleted). LCK Lock r/w0: BI has right of access. r/w1: BI does not have right of access. Lock determines the right of access for the BI. ID Identifier r/i: Identifier. The ID contains the address of the telegram. 11 bits in the standard mode or 29 bits in the extended mode. ACC Access r/w0: CPU does not have right of access. r/w1: CPU has right of access. Access determines the right of access for the CPU. The CPU should not modify this flag after initialization. In operation mode only the BI modifies it and the CPU reads it. RSR r/w0: r/w1: Micronas In the provide mode, RSR signals a send request from outside; in the fetch mode it means that a remote Tg is being sent. It is set by the BI if a remote telegram has been received. It is deleted as soon as the corresponding data telegram has been transmitted. EXF Extended Format r/w0: Standard. r/w1: Extended. In order to send/receive telegrams with extended address format, this flag must be switched on. For standard telegrams it is deleted. DLC Data Length Code r/w: Data length. The DLC defines the number of data bytes transmitted. Only telegrams with 0 to max. 8 data bytes are transmitted. If the DLC of a TxTg contains a value >8, the entered DLC and exactly 8 bytes will be transmitted. In the case of RxTgs the received DLC, and therefore also values > 8 will be entered by BI. TIE Tx Interrupt Enable r/w0: Disable. r/w1: Enable. Masks the Tx interrupt for this com. object. RIE Rx Interrupt Enable r/w0: Disable. r/w1: Enable. Masks the Rx interrupt for this com. object. SR Send Request r0: Successful transmission. r/w1: Send request. With SR, the microprocessor issues a send request. Both the microprocessor and the BI write the SR flag. If the microprocessor writes a one, the telegram is sent. The BI deletes the SR flag after successful transmission. TS Transfer Status r/w0: Ready for Transfer. r/w1: Successful transfer. The TS flag is set by BI after a successful transfer and is deleted by the microprocessor after a com. object has been processed. 25.2.4.2. Data Field The data field consists of 8 Byte. They are filled with telegram data according to the DLC. Unused data bytes (DLC less than 8) can be used by the user. 25.2.4.3. Time Stamp TIMST Time Stamp r: Counter value. The last two bytes in the CO are used for the time stamp. At each SoF (Start of Frame) the free-running 16-bit counter CANxCTIM is loaded into a register. When the Tg has been correctly transmitted, this register is copied to the two time stamp bytes of the corresponding CO. Remote Send Request Remote telegram received. Corresponding data transmitted. 149 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Data 5 Data 6 Data 7 14 Time Stamp low 15 Time Stamp high Fig. 25-4: Time stamp 25.3. Application Notes After reset, a CAN Module is in standby mode (inactive). Prior to entering active mode, proper SW configuration of the U-Ports assigned to function as RX input and TX output has to be made (Table 25-1). The RX port has to be configured Special In and the TX port has to be configured Special Out. Refer to "Ports" for details. For entering active mode of a CAN, set the respective enable bit (Table 25-1). Table 25-1: Module specific settings Module Name CAN0 HW Options Initialization Item Address Item Setting CAN0-RX input multiplexer PM.U20 CAN0-RX U2.1 or U4.3 special in CAN0-TX U2.0 or U4.2 special out CAN1-RX U6.1 special in CAN1-TX U6.0 special out CAN2-RX U8.5 special in CAN2-TX U8.4 special out CAN0-TX output multiplexer CAN1 CAN2 In the initialization phase, a configuration of the CAN node takes place. The mode of operation of the BTL and the bus coupling is set. The communication area is created in the CAN-RAM. The different telegrams are specified in it. The CAN node must be halted (HACK = TRUE) to carry out the initialization. After a reset, the flags HLT and HACK are set and initialization can take place. If initialization is required on-line, the flag HLT must be set. However, the BI must terminate any current transmission before it comes to a halt. For the user this means that he must wait until HACK has been set. If HLT is deleted after initialization, then BI begins to participate in the bus traffic and to scan the CA for tasks. During initialization, the error status register (CANxESTR) and the interrupt index (CANxIDX) should be deleted, otherwise no interrupts can be initiated. If telegrams with different identifiers are to be received in a single CO, the identifier mask register must be initialized. This defines which bit of the ID received must be the same as the ID in the CO. Bit timing registers 1, 2 and 3 and the output control registers 1 and 2 must be initialized in all cases. 150 Enable Bit SR0.CAN0 SR0.CAN1 SR0.CAN2 The CA must be created in the CAN-RAM. The different COs are created one after the other starting at the address 0. It is important at this point that the three MSBs have been set in the first byte after the last CO, i.e. at an address divisible by 16 (CM = End of CA). This is not necessary if the CAN-RAM is completely filled with COs. Communication mode (CM), identifier, data length code, extended format flag (EXF) and remote send request flag must be initialized in each CO. Lock flag (LCK) must be deleted and access flag (ACC) must be set in order that the BI may also view this CO. Transfer status flag (TS) must be deleted so that interrupts are not initiated erroneously. 25.3.2. Handling the COs 25.3.2.1. Principles If the user wishes to access a CO, then he must lock out the BI from access to it. Also the BI reserves access for itself to one CO. In this case the user may not have access. When scanning the CA, the BI ignores inactive or locked COs; i.e. it reads only the first byte and then jumps to the next CO. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 25.3.1. Initialization CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Reservations Procedure If the user would like to access a com. object, then he must first set LCK. Then he must read ACC. If it is TRUE, he has right of access. After the operation he must delete LCK. 25.3.2.3. Transmit Telegram LCK = TRUE; if (ACC == TRUE) { /* CPU has right of access */ } LCK = FALSE; _______________ or _________________ LCK = TRUE; while (ACC == FALSE) { /* wait until BI is ready */ } /* CPU has right of access */ LCK = FALSE; A transmit telegram is used to send data. How many data bytes will be sent is fixed in the DLC. The data is entered directly after the TD. Unused data bytes can be freely used by the user. If after the transmission of this telegram the user would like the next Tx-Tg in the CA to be sent, he deletes the RSC flag. If he sets the RSC, then the transmit search starts again at the beginning of the CA. The RSR flag has to be deleted. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Fig. 25-5: Access to a CO by the user When the BI is accessing a com. object, it first deletes ACC and then reads LCK. If LCK is FALSE, it has right of access. ACC = FALSE; if (LCK == FALSE) { /* BI has right of access */ } ACC = TRUE; Fig. 25-6: Access to a CO by the BI The BI does not wait at a CO until it becomes free. The BI scans the CA from beginning to end. After a TxTg has been transmitted, the next TxTg entered is reported ready to send. It makes sense to enter the COs in the CA in order of their priority. The priority is determined by the ID. The lowest ID has the highest priority. If the first bits of an extended ID are identical with a standard ID, the standard ID has higher priority. The CO with the highest priority is at the beginning of the CA. This ensures that Tx-Tgs with high priority are transmitted first when a rescan is initiated. 25.3.2.2. Configuration A CO may be configured only in the inactive and/or locked mode or when HACK has been set. Otherwise it can lead to access conflicts between the user and BI. The communication mode (CM) is determined in the configuration phase. The identifiers are also entered. The flag EXF must not be overlooked. The flag RSR and DLC determine whether and how many data bytes will be transmitted in the telegram. The interrupts can be permitted. In case of a receive telegram it is necessary under certain circumstances to set the flags MID and OW. In case of a transmit telegram, the flag RSC must be adjusted. CM = Send The set SR flag tells BI that this telegram is to be sent; SR can be likened to a postage stamp. The TS flag must be deleted before the CO is released with the deletion of LCK. If the BI finds a CO whose SR flag has been set, it reserves this (ACC = FALSE) and reports it "ready to send". It will be transmitted as soon as no higher-priority telegrams occupy the bus. After successful transmission, it deletes the flag SR and sets TS. The setting of ACC re-releases the CO. Whether an interrupt will be triggered depends on whether CANxIDX in the GCS contains the value minus one (255) and transmit interrupts are permitted. The user should now reserve the CO, reset the flag TS and delete CANxIDX so that other interrupts can also be reported. Should he wish to send further data, he can now enter this. 25.3.2.4. Receive Telegram CM = Receive With a receive telegram, data is received. If the EXF flag and the unmasked bits of the identifier of a received telegram are the same as those of a receive CO, the telegram will be copied to the CO. ID, DLC and data bytes are overwritten by the received ID, DLC and data. Only as many data bytes as the received DLC specify will be overwritten (max. 8). The DLC actually received will be entered. A permitted receive CO is only used when TS has been deleted or OW has been set. Once a telegram has been received and copied to a CO, the flag TS is set. An interrupt will also be initiated if receive interrupts are permitted and CANxIDX contains the value minus one (255). If the user detects the reception of a telegram (TS set), he must reserve the CO. Then he can read the data and, before releasing the CO again, delete TS. 25.3.2.5. Receive All Telegrams CM = Rx-All If, while searching for an RX-CO, the BI comes across a free Rx-All-CO, the received telegram will be entered here without regard to ID and EXF. Rx-All-COs should be applied at the end of the CA. 25.3.2.6. Fetch Telegram CM = Fetch A fetch CO is used to request data from another node. This is done by sending a telegram with the identifier of the desired data. The remote transmission request flag is set in Micronas 151 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 this Tg. No data is therefore sent with it. If another node has the desired data available, this is transmitted with the same ID as soon as bus traffic allows. If a telegram with a DLC greater than 8 is received, this value will be written into the DLC of the CO, but exactly 8 bytes of data will be copied. In this mode, only the reception of the data telegram can trigger an interrupt. If the DLC of a Tx-CO contains a value greater than 8, this DLC will be transmitted, but only 8 bytes of data. The sequence of a fetch cycle is represented for the user in pseudo-code. 25.3.2.9. Overwrite Mode The BI now transmits the telegram with the RTR flag set. The other node receives the Tg, provides the data and returns the telegram with RTR flag deleted. After the reply telegram has been received, the BI sets the flag TS. The user waits for the data. /* wait for answer */ while (TS == FALSE) {/* do anything else */} LCK = TRUE; /* claim CO */ /* wait until BI released this CO */ while (ACC == FALSE) {/* do anything else */} /* copy data */ TS = FALSE; LCK = FALSE; /* release CO */ Instead of waiting for the answer, it is also possible for notification to be given by a receive interrupt. 25.3.2.7. Provide Telegram CM = Provide A provide CO is used to prepare data for fetching. It is the counterpart of a fetch CO. In a provide CO the RSR flag is cleared. It will be set and deleted by the BI. The data can be prepared in two ways: In the first case, the user does not become active until a remote frame has been received (Rx interrupt or polling from RSR). After the CO has then been reserved, the data is written, the SR flag is set and the CO is released. The BI ensures then that the data is transferred back. In the second case, the data has already been entered, SR has been set and TS deleted before the request. When the remote frame is received, the user does not need to become active. Also, no Rx interrupt will be initiated. The data is simply fetched. In this case the requesting RTR telegram must contain the correct DLC because, with an RTR telegram too, a received DLC overwrites the local DLC. In both cases a Tx interrupt can occur after the data telegram has been transmitted. 25.3.2.8. Data Length Code The data length code is 4 bits long. It can therefore contain values between 0 and 15. In principle, no more than 8 bytes can be transmitted. Empty data telegrams (DLC = 0) are also possible. 152 The BI normally processes a CO only when the transfer status TS has been deleted; i.e. the user has processed the CO since the last transmission. In the case of COs with which telegrams are received, the TS flag can be by-passed. If overwrite (OW) is permitted, the BI may overwrite a previously received telegram. When accessing data therefore, the user always receives the most up-to-date data. 25.3.3. Interrupts All interrupts are enabled or disabled by the global interrupt enable flags, GTIE for Tx interrupts, GRIE for Rx interrupts and EIE for error interrupts in the GCS register. This is the only location for enabling error interrupts. A Tx interrupt can be enabled in the corresponding CO with the Tx interrupt enable flag TIE. An Rx interrupt can be enabled in the corresponding CO with the Rx interrupt enable flag RIE. An interrupt can only be initiated when the interrupt index CANxIDX is empty (minus one). To initiate an interrupt, the BI enters the number (0...253) of the appropriate CO in the CANxIDX. When an error interrupt is involved, the number 254 is entered. The BI attempts to initiate an interrupt immediately after successful transfer. If this does not work (CANxIDX not empty), the interrupt is pending (also error interrupt). The BI permanently scans the CA. If, while doing so, it finds a CO whose interrupt condition is satisfied (e.g. TIE and TS are set), it generates an interrupt. This means that interrupts not yet reported will not be reported in the sequence of their occurrence, but in the sequence in which they are discovered later. The interrupt service routine of the user must read the CANxIDX. The interrupt source is stored here. If CANxIDX points to a CO (0...253), the user must reserve this. After this, he must first delete TS so that this CO does not initiate an interrupt again. Only then he may release CANxIDX (CANxIDX = 255) so that the BI can enter further interrupts. 25.3.4. Rescan The normal transmit strategy searches for the next transmit CO in the CA. If all the transmit COs are ready to send, they are processed one after the other. This is a democratic strategy. If higher-priority TxTgs are reported in the meantime, these are not processed until the complete list has been finished. With rescan, the search for Tx telegrams is started again at the beginning of the CA. By this means the user can force the normal strategy to be interrupted and a search to be made first of all for higher-priority TxTgs. A transmit CO already reported will of course be transmitted first. The rescan requirement can be achieved dynamically, when a transmit CO is reported, by setting the global rescan flag GRSC. It is also possible to configure a rescan strategy statically. Each Tx-CO has the rescan flag RSC. If it is set, the system Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. if (TS == FALSE && SR == FALSE) /* CO is empty */ { LCK = TRUE; /* claim CO */ /* wait until BI released this CO */ while (ACC == FALSE) {/* do anything else */} SR = TRUE; /* send this Tg */ TS = FALSE; LCK = FALSE; /* release CO */ } CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 starts from the beginning with the transmit search after this CO has been processed. It is possible, for instance, to set RSC in the low-priority Tx-COs. Each time a low-priority TxCO has been handled, the search continues for higher-priority objects. If the BI has received an identifier complete, it starts at the beginning of the CA with the search for an appropriate RxCO. If a rescan is initiated, the BI also starts from the beginning with the transmit search. The user must ensure that each Tx-CO is processed. 25.3.7.1. Buffers 25.3.5. Time Stamp The time stamp of a CO shows the user how much time has elapsed since the transmission of the object. For this purpose, he compares the time stamp with the capture timer CANxCTIM. Because the time stamp contains the value of the CANxCTIM at the time of the start of transmission, the difference is proportional to the time which has elapsed. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The time stamp mechanism also enables network-wide synchronization. A master transmits a Tg. All nodes note the transmission time (local time). Then the master transmits its own (global) transmission time. The difference between local and global time shows by how much one's own clock (timer) is wrong. 25.3.6. Errors In the error status register (CANxESTR) error messages and status data are collected which can generate an error interrupt. As long as a flag is set in the CANxESTR, the flag ERS is also set in the status register. This means that the value 254 is written in CANxIDX and an interrupt is generated when EIE has been set. Several successive receive COs may be allocated with the same identifier. The BI stores a received Tg in the first free Rx-CO. Using this mechanism it is possible to construct a receive buffer. If RIE is set in the last CO, the CPU is not informed until the buffer is full. 25.3.7.2. Basic/Full CAN For a Basic CAN application, a single Tx-CO will be used. All outgoing telegrams will be transmitted with this. The user must receive all Rx-Tgs and must himself decide whether he needs it (acceptance filtering). For this case it is possible to use an Rx-All-CO. But it is necessary to ensure that this can be processed before the next Tg arrives. For this reason, it is a good idea to employ 2 or 3 Rx-All-COs as buffers after the Tx-CO. In the case of a FullCAN application, one uses the built-in acceptance filtering and sets up a CO specifically for each desired Rx-Tg and Tx-Tg. If the CAN-RAM is not big enough, mixed strategies are also possible. The acceptance filtering, of course, burdens the CPU with communication tasks. An error interrupt is deleted by first deleting CANxESTR and then releasing CANxIDX. TD: CM=Send Tx-Obj The flag ECNT (error counter level) indicates that an error counter has exceeded a limit value. It is set when the transmit error counter exceeds the values 95, 127 and 255 or the receive error counter exceeds the values 95 and 127. TD: CM= Rec. All Rx-Obj When the BI is in the Bus-Off mode, it no longer actively participates in the bus traffic. Nor does it receive telegrams, but continues to observe the bus. As soon as the BI has detected 128 x 11 successive recessive bits, it reverts from the Bus-Off mode to the error-active mode. At the same time the error counters are cleared. TD: CM= Rec. All Rx-Obj TD:CM = 7 End of Com. Area The 5 flags BIT, STF, CRC, FRM and ACK originate from the protocol manager. The flag GDM (Good Morning) is not an error flag. GDM is set when the BI is aroused from the sleep mode by a dominant bus level. A Bus-Off sequence triggers two interrupts, if the error interrupt is enabled. The first interrupt (ECNT=TRUE) indicates that the transmit error counter has exceeded the value 255. This means that the module is in the Bus-Off mode now (BOFF=TRUE). The receive error counter is used to count the reception of 128 x 11 successive recessive bits in the Bus-Off mode. This is the reason for the second interrupt (ECNT=TRUE), which indicates that the receive error counter has exceeded the value 95 (warning level). The second interrupt can be ignored in Bus-Off mode. The error interrupt can be disabled during Bus-Off mode to avoid this second interrupt. Fig. 25-7: Example: CA of a BasicCAN with 2 Rx-buffers 25.3.7. Layout of the CA The CA contains all COs beginning with the lowest identifier. The three MSBs must be set in the byte after the last CO (End of CA). Micronas 153 CDC32xxG-B V3.0 ADVANCE INFORMATION TD: CM= Receive Rx-Obj TD: CM=Send Tx-Obj TD: CM=Send Tx-Obj TD: CM= Rec. All Rx-Obj TD: CM=Send Tx-Obj TD: CM= Rec. All Rx-Obj TD: CM= Receive Rx-Obj TD: CM= Rec. All Rx-Obj TD: CM= Rec. All Rx-Obj TD: CM= Rec. All Rx-Obj TD: CM= Rec. All Rx-Obj TD:CM = 7 End of Com. Area TD:CM = 7 End of Com. Area Fig. 25-9: Example: CA of a BasicCAN with 4 Rx-buffers Fig. 25-8: Example: CA of a FullCAN with 2 Rx-objects, 2 Tx-objects, and 2 Rx-buffers 25.3.7.3. Bus Monitor With some Rx-All-COs it is possible to construct a userfriendly bus monitor. The CPU has merely to observe whether anything has been received. The contents of the CO must be stored. The transmission time can be calculated from the time stamp. 25.3.7.4. Maximum number of COs The maximum number of COs depends on the size of the CAN-RAM, the baud rate, the system clock, the BI and the CPU accesses to the CAN-RAM. - The BI can handle a maximum of 254 objects. The limiting factor is the 8-bit register CANxIDX in the GCS. CANxIDX can contain 256 different values. The values 255 (empty) and 254 (error) are reserved. The remaining values 0...253 can indicate 254 objects. - The maximum number of COs is, of course, limited to a greater extent by the size of the CAN-RAM. The BI can only access the CAN-RAM. Therefore the CA can only be applied there. 16 bytes are reserved for each CO. One extra byte for coding EoCA after the last CO must not be forgotten. The CAN-RAM area after the EoCA is freely available to the user. No EoCA is necessary if the CAN-RAM is filled completely with COs. There is a maximum number of 32 COs possible in a CAN-RAM of 512 bytes. 154 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 3 DEC 01 ADVANCE INFORMATION CDC32xxG-B V3.0 3 DEC 01 CAN RAM Size Max. Number CO = ----------------------------------------16 - The next limiting factor can be calculated from the baud rate and system clock. After the BI has received an identifier, it must be possible for it to scan the entire CA before the telegram comes to an end. t CA SCAN Max. Number CO = ----------------------t CO SCAN t CO SCAN 9 = ---f0 t CA SCAN = 28 t Bit t Bit = ( 3 + TSEG1 + TSEG2 ) t Q All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. BPR + 1 t Q = -------------------f0 tCA Scan is the time from having received an ID to the end of a minimum telegram (11 bit ID, no data), which is at the BI's disposal to scan the CA. tCO Scan is the worst case time needed by the BI to process an object (A value of 6 I/O cycles is a more realistic size than 9). With an input frequency of 8 MHz and a baud rate (1/tbit) of 1 MBd, the BI could handle 24 COs. Naturally, this value needs to be rounded off. - The value thus calculated is further limited, however, by the CPU accesses to the CAN-RAM. Each I/O cycle required by the CPU to write or read data in the CANRAM is missing from the BI. The BI is halted by CPU accesses. This reduces the time which the BI has to scan the CA. Where there is a reduced CPU clock, in particular, the user should have only limited access to the CANRAM. With the ARM CPU accessing CAN RAM, it is easy to block the BI's CAN-RAM access over a long time. The ARM CPU can make a memory access with each I/O cycle, leaving nearly no I/O cycles to the BI. In the above example (8 MHz, 1 MBd), tCA Scan lasts 224 I/O cycles (28 * 8). The BI needs 144 I/O cycles to scan 16 COs leaving 80 I/O cycles to the CPU to process a telegram. It is not necessary to process more than one telegram during transmission of one telegram. As long as the COs are managed via interrupt, 80 I/O cycles should be more than enough to read or write a CO. In this worst case scenario the BI needs 288 I/O cycles to scan 32 COs. This is possible at an input frequency of 8 MHz and up to baud rate of 500 kBd. In a more realistic estimation (average tCO Scan = 6) the BI needs 192 I/O cycles to scan 32 COs leaving 32 I/O cycles to the CPU to process a telegram. This means 1 MBd is possible even with 32 COs, as long as the COs are managed via interrupt only. Due to this, care has to be taken when using free CANRAM (after EoCA). It is not possible here, to make an assumption about how many accesses a non CAN routine makes to its data storage. 25.4. Bit Timing Logic In the bit timing logic the transmission speed (baud rate) and the sample point within one bit will be configured. By shifting the sample point it is possible to take account of the signal propagation delay in different buses. Furthermore, the nature of the sampling and the bit synchronization can also be defined. 25.4.1. Baud Rate Pre-scaler The baud rate pre-scaler is a 6-bit counter. It divides the system clock down by the factor 1...64. The output is the clock for the bit timing logic. This clock TQCLK defines the time quantum (tQ). The time quantum is the smallest time unit into which a bit is subdivided. 25.4.2. Bit Timing A bit duration consists of a programmable number of TQCLK cycles. The cycles are split up into the segments SYNCSEG, TSEG1 and TSEG2. 25.4.2.1. Bit Timing Definition Sync.Seg. It is expected that a bit will begin in the synchronization segment. If the bit level changes, the resynchronization ensures Micronas that the edge lies inside this segment. The sync.seg is always one time quantum long. Prop.Seg. This part of a bit is necessary to compensate for delay times of the network. It is twice the sum of the signal propagation delay on the bus plus input comparator delay plus output driver delay. Phase Seg. Phase segments 1 and 2 are necessary to compensate phase differences. They can be lengthened or shortened by resynchronization. Sample Point The bus level is read at this point and interpreted as a received bit. TSEG1 The CAN implementation combines propagation delay segment and phase segment 1 to form time segment TSEG1. TSEG2 TSEG2 corresponds to phase segment 2. SJW The synchronization jump width gives the maximum number of time quanta by which a bit may be lengthened or shortened by resynchronization. 155 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 t Bit = t SYNCSEG + t TSEG1 + t TSEG2 BPR + 1 t Q = -------------------f0 t SYNCSEG = 1 t Q t TSEG1 = ( TSEG1 + 1 ) t Q t TSEG2 = ( TSEG2 + 1 ) t Q t SJW = SJW t Q tBit 1 Timequant Prop Seg Phase Seg1 tTSEG1 Phase Seg2 tTSEG2 def. CAN-SPEC impl. CAN Fig. 25-10: Bit Timing Definition The baud rate is then calculated as follows: With a baud rate of 1 MBd a bit should be at least 8 tQ long. In case of a triple sample mode (MSAM = 1), the following boundary condition must also be observed: 1 BR = -------t Bit ( BPR + 1 ) ( 3 + TSEG1 + TSEG2 ) t Bit = ----------------------------------------------------------------------------------------f0 f0 BR = ---------------------------------------------------------------------------------------( BPR + 1 ) ( 3 + TSEG1 + TSEG2 ) 25.4.2.2. Bit Timing Configuration Certain boundary conditions need to be observed when programming the bit timing registers. The correct location of the sample point is especially important with maximum bus length and at high baud rate. t TSEG2 2 t Q = Information Processing Time t TSEG2 t SJW t TSEG1 3 t Q t TSEG1 t PROP + t SJW + 2t Q The triple sample mode offers better immunity to interference signals. In the single sample mode a higher transmission speed is possible. For high baud rates and maximum bus length, neither SYN nor MSAM may be switched on. Bosch advises against both adjustment facilities. When an input filter matched to the baud rate or a bus driver is used, the triple sample mode is not necessary. If SYN is set, synchronization will also be made with the soft edge (dominant to recessive) and this will mean higher demands being imposed on the clock tolerances. 25.4.2.3. Synchronization The BTL carries out synchronization at an edge (change of the bus level) in order to compensate for phase shifts between the oscillators of the different CAN nodes. t TSEG1 t TSEG2 25.4.2.4. Hard Synchronization t TSEG1 t PROP + t SJW Hard synchronization is carried out at the start of a telegram. The BTL ensures that the first negative edge is in the sync. seg. The information processing time is the internal processing time. After reception of a bit (sample point) this time is needed to calculate the next bit for transmission. 156 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Sync Seg tSYNCSEG Sample Point CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 25.4.2.5. Resynchronization Resynchronization takes place during the transmission of a telegram. If the BTL detects an edge outside the sync. seg., it can lengthen or shorten the bit. If it detects the edge during TSEG1, tTSEG1 is lengthened. If it detects the edge during TSEG2, tTSEG2 is shortened. In this way, it ensures that the edges lie in the sync. seg. TSJW is the maximum time a bit can be lengthened or shortened. Two forms of resynchronization are possible. In normal operation, synchronization is carried out only with the negative edge (recessive to dominant). At low transmission speeds, synchronization can also be carried out with the rising edge (SYN = 1). 25.5. Bus Coupling All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Integrated transceivers (Siliconix Si9200, Philips 82C250 etc.) are available for physical coupling in the high-speed range in compliance with ISO/DIS 11898. For a laboratory system a "minimum bus" can be constructed by means of a wire-Or circuit. To utilize the advantages of differential signal transmission, an analogue comparator is necessary. ITX 0 REF0 The output pins are push/pull drivers for TLL levels. The input pins are also designed for TTL levels. Table 25-3: Logical Level Receiving REF1 The bus coupling describes the connection of the internal signals rx (receive line) and tx (transmit line) to the pins to the CAN bus. RxD 0 0 x 1 Don't work 0 1 0 1 Recessive 0 1 1 0 Dominant 1 0 0 0 Dominant 1 0 1 1 Recessive 1 1 x 0 Don't work rx Bus Level Remarks inverted direct tx TxD 1 1 +5V Bus +5V REF1 1 RxD 0 OR CAN rx 0 +5V REF1 1 1 REF0 RxD 0 OR 0 Fig. 25-11: Bus Coupling 1 rx REF0 ITX Table 25-2: Logical Level Transmitting ITX tx TxD Bus Level Remarks 0 0 0 Dominant direct 0 1 1 Recessive 1 0 1 Recessive 1 1 0 Dominant Micronas TxD 0 tx 1 1 Fig. 25-12: Minimum Bus inverted 157 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 158 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 26. DIGITbus System Description 26.1. Bus Signal and Protocol The DIGITbus is a single line serial master-slave-bus that allows clock recovery from the sign stream. Data on the bus are represented by a pulse width modulated signal. There are three different signs: "0": 25% High Time "1": 50% High Time "T": 75% High Time address length is one bit. The minimum data field length is zero bit. Telegrams with more than one data field are allowed too. For instance TTTTAAATDDDDTDDDDDTT is a valid telegram format on the DIGITbus. A telegram consisting of an address only is possible too. The length of the data field is zero in this case. bit time T All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 0 1 A permanent low bus (0% High Time) is interpreted as bus reset or failure indicator. Reasons may be shorts or opens or even a low level forced by a bus node to indicate an internal failure or reset condition. The sign "T" is used to provide a system wide clock for the bus nodes and to separate the address and data fields and consecutive telegrams. A telegram normally consists of an address and a data field separated by one "T". These fields may be as long as necessary. Thus the length of an address or data field may carry information. The end is marked by a "T". The end of a telegram is marked by two T-Signs. T Address Address T T T T T T T A permanent high bus (100% High Time) means the bus is passive high. The bus is active if there are consecutive TSigns, ones or zeros. T T T Data T T T One system implementation may be confined to certain address and/or data field lengths, thus reducing the hardware or software requirements. The transmitter of an address has to guarantee that the address is preceded by four T-Signs at least. An isolated data field is not possible. Each non "T" sequence, which is preceded by two or more consecutive TSigns must be interpreted as an address. An address field is valid after the reception of the following "T". The minimum A data field is preceded by an address field and separated from this by a single "T". It is followed by one T-Sign. After reception of two T-Signs the telegram is finished and valid. In the idle phase (no information exchange) of the bus traffic, only the bus clock is transmitted. T T T T T T T T T T T T After the reception of two consecutive T-Signs all bus nodes have to be prepared to receive a new telegram starting with an address field. They are ready to send an address after the reception of four consecutive T-Signs. The modification of a T-Sign to a zero or one is done by pulling the bus line to low (dominant state) at the right time. This is done by a master sending an address or a data bit or by a slave sending a data bit. In case of reading data from a slave, the master first sends the address. After receiving the address the slave waits one T-Sign and then modifies the following T-Signs to zeros and ones which the master can recognize. Slaves do not have the possibility to become active on the bus if they want to communicate a local event or if they need data from a master. It is a polling bus. Only a master is able to send an address. The master has to scan the slaves for their data. But it is possible to transfer data from one slave directly to another slave. The master has to transmit an address for which one slave is the source and the second slave is the destination. Telegrams on the bus are broadcasted. Each bus node may receive them. 26.2. Other Features There are two possibilities for a slave to signal a local event to the master. They are called wake-up and bus reset. 26.2.1. Wake-up level. This will awake the master who has to store this event in a flag, to start the bus clock and to scan the bus for the source of this event. The minimum low time of the reset pulse is 1/16 of the nominal bit time (1/Baudrate). If the DIGITbus is passive high (permanent high level for more than one bit period) a slave may pull the bus line to low Micronas 159 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 The rising edge of a bit or bus clock is only controlled by the bus node which generates the bus clock (clock master). No other bus node may hold down the bus line at that moment. When the clock master releases the bus line at the end of a bit, he must watch the bus line. If the bus level does not rise after at least 1/2 bit time, this must be interpreted as a protocol violation. Delay of 1/2 of a bit time is the latest moment for a master. He can indicate this protocol violation if the rising edge is delayed 1/8 bit time. Slaves may use this mechanism to signal an exception to the master. They must pull down the bus for at least 2 bit times. After such an event normal communication may be impossible until the PLL of bus nodes have synchronized again. 26.2.3. Phase Correction On a physical bus the signal edges may be delayed by the bus load. An extra delay may be added by different trigger edges. The bus nodes see the edges at different times. This cause them to pull the bus line delayed. To compensate this effect the phase correction mechanism allows the bus node to adjust their internal counters. The master sends a special address to which the slave answers with a single zero. The master measures the time between the rising and the falling edge. With this value he can calculate a phase correction value and transmit it to the slave. The slave may use it to adjust his internal counter. The Phase Correction has to be done for each bus node separately. 26.2.4. Abort Transmission The Abort Transmission feature is an option that allows the implementation of some kind of rip cord with the DIGITbus. On an alarm event, the SW of the sending master bus node may break the current telegram and send another telegram instead. The reception of an address/data field can not be stopped. The transmission of the alarm telegram is delayed until after the end of the reception in this case. Only the actual sending bus node can abort the transmission. 26.3. Standard Functions The following standard functions have to be included in every DIGITbus implementation. a received address it is not sufficient to compare the value. The length of the address must be correct too because of the arbitrary length of the address field. 26.3.1. Send Bus Clock The Bus Clock is the sequence of T-Signs on the DIGITbus. The rising edges of the bus signal are of constant distance. Only one bus node may generate this Bus Clock even in a multi master system. All bus nodes use this stream of TSigns to generate telegrams. The bus clock generator knows two states. "Active Bus" means the transmission of the Bus Clock. "Passive Bus" means permanent high bus level. "Passive Bus" may be a low power mode. 26.3.2. Receive Bus Clock Bus nodes which does not generate the bus clock need an internal clock for their operation. They may use a separate clock source or derive their clock from the bus clock by a PLL. Bus nodes which use own clock sources nevertheless have to synchronize on the bus clock if they want to transmit or receive data. 26.3.3. Send Address The Address is the first bit field in a telegram. Only a master may send this field. The sender must guarantee, that at least two consecutive T-Signs have been visible on the DIGITbus before sending this field. Therefore he has to send four TSigns. If one of those four transmitted T-signs is disturbed, only one of the separated telegrams is corrupted for a receiver. Sending of an address requires synchronization on the bus clock and, in case of a multi master system, collision detection and arbitration capability. 26.3.4. Receive Address 26.3.5. Send Data Each master must be and some slaves are able to send a data field. A data field is preceded by an address or data field and one T-Sign. 26.3.6. Receive Data Each master must be and some slaves are able to receive a data field. A data field is preceded by an address or data field and one T-Sign. It is a good idea to verify the length of a received data field if possible. But variable length data fields are possible too. 26.3.7. Collision Detection Collision detection together with arbitration is necessary in multi master systems. It is necessary to avoid the disturbance of telegrams if two masters try to send a telegram at the same time. As long as both transmit the same sign (one or zero) at the same time, they don't detect a collision. If one master is sending a one and the other is sending a zero, a zero will be seen at the bus. In this case the master whose one was modified to the zero stops immediately sending. He should receive this telegram. The sender has to arbitrate his part of the telegram. Write telegram: TTTTTAAAATDDDDTTTTT Read telegram: TTTTTAAAATDDDDTTTTT The separator (T-Sign) after an address or data field is object of arbitration too. In a single master system arbitration loss has to be managed as a bus error. Each slave and all multi master capable bus nodes must be able to receive an address. For a receiver a valid address field must be preceded by two consecutive T-Signs. To verify 160 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 26.2.2. Bus Reset ADVANCE INFORMATION CDC32xxG-B V3.0 3 DEC 01 26.4. Optional Functions The following optional functions may be designed into a certain DIGITbus implementation. 26.4.1. Abort Transmission A master who is controlling the transmission of a telegram can abort the sending of the address and data field. After four T-Signs after the last bit he can send another, more urgent telegram. If he is receiving a data field from a slave, he must wait until the slave has finished the data field. Then he can insert a new telegram. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 26.4.2. Measure Pulse Width The capability to measure the pulse width of a high pulse at the DIGITbus may be used for a phase correction by some bus nodes. The bus node who generates the bus clock, sends a data read telegram to another bus node. The other bus node answers with a data field which consists of a single zero. The pulse width of this zero is measured by the master. With this value he can calculate a phase correction value and transmit it to this bus member, which may adjust its time slots to the system dependencies. 26.4.3. Correct Phase Bus nodes which does not generate the bus clock may use the above described procedure to adjust their phase. They have to answer to a special address with sending back a zero. Afterwards they will receive with another special address a correction value. With this value they can adjust the point where they pull the bus line to modify a "T" to a one or a zero. 26.4.4. Generate Wake-up If the DIGITbus is passive high (no bus clock, always high level), the clock master may be wake up by pulling the bus level to low (dominant state) for 1/16 bit time at least. All nodes without the clock master may be able to do that. 26.4.5. Receive Wake-up If there is a low pulse of at least 1/64 bit time on a passive high DIGITbus, the clock master must start to transmit the bus clock by sending T-Signs. All Masters with a bus clock generation unit must be able to do so in a system who uses this feature. 26.4.6. Generate Reset During active DIGITbus a slave may be allowed to pull down the bus line longer than up to the end of the actual bit time (2 bit times at least). The rising edge at the end of the bit will be delayed in this case. This will disturb the bus clock for all bus nodes. 26.4.7. Receive Reset The clock master is generating the rising edge at the end of a bit time. He will detect the above described reset condition and set a flag if the rising edge is delayed for at least 1/8 of the bit time. Micronas 161 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 162 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 27. DIGITbus Master Module The DIGITbus is a single line serial master-slave-bus that allows clock recovery from the sign stream. The address and data field are of arbitrary length. - Bus clock generation. The DIGITbus Master module is a HW-Module for connecting a single chip controller to the DIGITbus. It generates the bus clock and manages short telegrams autonomously. Transmission and reception of long telegrams is supported by a FIFO each. The DIGITbus Master may be used in a single or in a multi master bus system. - Transmit FIFO and receive FIFO. - Receive and transmit a telegram with address and data field. - Collision detection and arbitration. - Abort transmission. - Sleep mode. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. - Bus monitor mode. Features - Measure pulse width for phase correction. - Single master in a single master system. - Phase correction. - Clock master in a multi master system. - Receive wake-up and bus reset signal. - Passive master in a multi master system. - Register interface to the CPU. 27.1. Context Apart from reset and clock line, the interface to the CPU consists of registers connected to the internal address and data bus. An output signal may be connected to the interrupt controller. A modified universal port builds the output logic which is connected with its special input and output to the DIGITbus Mas- from clock divider ADB R/W DB Reset Interrupt ter. This provides an easy way for the SW to hold the bus line permanent low or high, or investigate bus level directly, without support of DIGITbus Master HW. An open drain output instead of a push/pull output is necessary for the universal port to build a single line wired and bus. +U Universal Port with Open Drain Output DIGITbus Master rx tx SI SO Port Pin DIGITbus Other Transmitter Fig. 27-1: Context Diagram Micronas 163 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 27.2.1. 3bit-Prescaler 27.2.8. Collision Detection The programmable 3bit-Prescaler supplies the module with clock signals. It scales down the HW option selectable clock by factor 1, 2, 3 to 8 (see Table 27-2 on page 166). The output is 64 times the bus clock. The desired input frequency from the clock divider is hardware programmable. The collision detection logic compares each incoming with the actual outgoing bit. A difference is signaled to the send telegram logic. If the module is transmitting, the send telegram logic is stopped immediately and the transmit FIFO and shift register are flushed. 27.2.2. Internal Clocks 27.2.9. Transmit FIFO In low power mode the clock supply of the whole module with exception of the receive bit logic can be stopped. The receive bit logic needs a clock in low power mode too, because it must filter and watch the bus line for a wake-up signal. The transmit FIFO has five entry addresses. One for the field length of address or data field, one for a address byte, one for a data byte, one for more address bytes and one for more data bytes. The field length has to be written once before the corresponding field is entered into the FIFO unless the field length is not a multiple of 8. 27.2.3. Transmit T An entry into the address register is inserted into the bus clock after the reception of 4 consecutive T-signs. An entry into the data register is inserted into the bus clock after the reception of a non T-sign and one T-sign. Thus it is possible to append a second data field (maybe acknowledge) after the reception of a telegram. The transmit T logic sends a continuous stream of T-signs if active. It outputs a permanent high if it is inactive. 27.2.4. Transmit Bit Depending on the input signals the transmit bit logic modifies the T-signs to ones or zeros. A phase correction can be done by adjusting the start time of a transmit bit sequence. Other bus behavior than sending zeros, ones or T-signs may be forced by the SW using the universal port in normal mode directly. The bus line may be released or pulled low. 27.2.5. Receive Bit The receive bit logic samples the bus level at a frequency of 64 times of the bus clock. It filters the input signal and decodes the input stream to supply the receive telegram logic with the logical bus signals (0, 1 and T) and the receive clock. Additional it measures the pulse width of each non Tsign. It creates a bus reset signal if the active bus is hold down beyond the end of a bit time. It creates a wake-up signal if there is a low level on the passive high bus. The transmit FIFO may be flushed to abort a transmission. It is also flushed if the transmit telegram logic is active and a collision is detected. 27.2.10. Receive FIFO The receive FIFO will be filled from the receive shift register. It has two exit addresses. One for the field length and field type and one for the bit field. The field length has to be read before the corresponding field is taken from the FIFO. The receive FIFO will be frozen if it is full. The receive shift register will be over written. 27.2.11. Interrupt Several flags of the status registers are connected by a logical-or to the interrupt source signal. The interrupt output can be masked by a flag in the control register. 27.2.6. Send Telegram The send telegram logic will be enabled by the transmit FIFO and the receive telegram logic if four consecutive T-signs were received. It supports the transmit bit logic with the transmit bit sequence. If it recognizes the begin of a new field, it waits one bit time (separator T-sign). 27.2.7. Receive Telegram The receive telegram logic traces the bus and indicates the state to the status register and other related modules. The received bit field is written to the receive FIFO. The receive telegram logic is active all the time. Even if the module is transmitting a telegram all bits must be received too in a multi master system, because arbitration may be lost. Reception of own telegrams can be disabled (in a single master system). 164 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 27.2. Functional Description CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 ADB DIGITbus Master Address Decoder R/W run HW option fDB 64 x bus clk 3-Bit-Prescaler Transmit T generate bus clock DIGITbus Interrupt Source Control/Status T-Seq. DB Phase All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Tx Field Length Tx Addr. Field & Tx Data Field Reset Tx More Addr. Field wake-up/bus reset arbitration lost busy Tx More Data Field 0-Seq. 64 x bus clk 1-Seq. full flush TxFIFO Transmit Bit T dat Transmit Telegram tx rise Collision Detection TxSR RxSR rx external only Receive Telegram data lost RxFIFO empty Rx Field Length rxclk txclk T dat Receive Bit rx 64 x bus clk Rx Field Pulse Width Fig. 27-2: Block Diagram Micronas 165 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 27.3. Registers PSC r/w: The register mnemonic prefix "DG" stands for DIGITbus. Prescaler Scaling value Table 27-1: Register Mapping Table 27-2: Clock Prescaler Addr. Offs. Mnem. readable writable 0 DGC0 Control 0 1 DGC1 Control 1 2 DGS0 Status 0 3 DGRTMD 4 DGTL 5 DGS1TA Status 1 Tx Addr. 6 DGTD reserved Tx Data 7 DGRTMA Rx Field Tx More Addr. PSC Rx Length fDB = 5 MHz fDB = 10 MHz 0x0 1 62.5 78.1 156.25 0x1 2 31.25 39.1 78.1 0x2 3 20.8 26.0 52.1 0x3 4 15.6 19.5 39.1 0x4 5 12.5 15.6 31.25 0x5 6 10.4 13.0 26.0 0x6 7 8.9 11.2 22.3 0x7 8 7.8 9.8 19.5 Tx More Data Tx Length Note: With an input clock of 5 MHz, the bus clock frequency of 31.25 kHz and its derivatives (16, 8, 4, 2, 1 kHz) can't be achieved. Thus, with a 5 MHz quartz the DIGITbus should be operated in PLL mode. Control Register 0 7 6 5 4 3 RUN GBC ACT RXO X 0 0 0 0 x 2 1 0 DGC1 PSC 2 to 0 0 0 0 Res r/w Control Register 1 7 6 5 4 INTE ENEM ENOF x 0 0 0 x 3 2 0 0 INTE r/w1: r/w0: Enable Interrupt Enable interrupt Disable interrupt GBC r/w1: r/w0: ENEM r/w1: r/w0: Enable Not Empty Interrupt Enable Disable ENOF r/w1: r/w0: Enable Not Full Interrupt Enable Disable ACT Activate r/w1: Module is active (reception and transmission). r/w0: Module is sleeping (low power mode). Only the receive bit logic is active in low power mode. RXO r/w1: r/w0: Receive External Only Don't receive own telegrams. Receive all. 0 0 0 PHASE RUN Run r/w1: Module clock is active. r/w0: Module is not clocked. The module is absolute inactive if RUN is zero. Other flags are not functional then. Generate Bus Clock Module generates bus clock No bus clock 1 Res PHASE Phase Correction Field r/w: Transmit phase. The start of the transmit frame can be selected in increments of 1/64 of a total bit time related to the rising edge. Values between 0 and 15 are possible, but only the interval from 0 to 9 results in correct behavior. Set PHASE to 2 if the DIGITbus is operated as clock master (GBC = 1). This is necessary to compensate for internal delay of 2 clocks. Refer to section 27.4.9. for further information about phase correction. 166 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. r/w Bus Clock in kHz fDB = 4 MHz An "x" in a writable bit location means that this flag is reserved. The user has to write a zero to this location for further compatibility. An "x" in a readable bit location means that this flag is reserved. A read from this location results in an undefined value. DGC0 Divide by CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Bit time Transmitted RxFIFO 0 16 32 48 0 Received NEM 0 16 32 48 0 Phase delay Interrupt Corrected 4 16 32 48 0 PHASE = Start value of transmit counter. TxFIFO Fig. 27-3: Phase Correction EMPTY NOF All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. DGS0 Status Register 0 7 6 5 4 3 2 1 0 w x x x TGV PV ERR x ARB r RDL NEM NOF x 0 1 0 0 0 x 0 Interrupt Fig. 27-4: Rx- and TxFIFO Timing Res RDL Receive Data Lost r1: Data lost r0: No data lost This flag is set if the receive FIFO is full and the shift register tries to store its contents to the FIFO because a new bit arrives. In this case the FIFO is frozen but the shift register is overwritten. It must be interpreted and cleared by the user. It is cleared by reading an entry from the FIFO. NEM Rx FIFO is Not Empty r1: There is at least one entry to read. r0: Empty. (see Fig. 27-4 on page 167) NOF Tx FIFO is Not Full r1: There is at least one entry free. r0: Full. It generates only an interrupt in the moment when the limit is passed. It doesn't generate interrupts when the FIFO is empty (see Fig. 27-4 on page 167). TGV Telegram Valid r1: Telegram valid r0: Telegram not valid w0: Clear flag This flag will be set if there were received two consecutive Tsigns. It is reset by the HW if a non T-sign is received. It can be cleared by the user if the related telegram is evaluated. ERR Error r1: Fatal error. r0: No error w0: Clear flag The HW sets this flag either if a dominant level is transmitted and a recessive level is detected (collision error), or if there was a wrong edge within a received bit. If a collision error is detected during transmission, the flag ARB will be set too and transmission stops immediately. This flag has to be cleared by the user. ARB Arbitration Lost r1: Arbitration lost. r0: No arbitration loss. w0: Clear flag This flag will be set if a collision is detected during transmission. It must be cleared by the user. The transmit buffer was flushed when ARB is true. It is impossible to write to the transmit FIFO as long as ARB is true. Wait until flag TGV is true before reloading TxFIFO. This is automatically done if ARB is evaluated within the TGV interrupt subroutine only. The Flags RDL, NEM, NOF, TGV, and PV trigger the interrupt source signal (see Section 27.4.7. on page 171). DGS1TA 7 Status 1 & Tx Address Register 6 5 w PV r1: Protocol Violation Wake-up if bus is passive high. Bus reset if bus is active. r0: No trouble w0: Clear flag It must be interpreted and cleared by the user. It is set when the receive bit logic enters or leaves state passive high or when it enters the state passive low. Micronas 4 3 2 1 0 0 0 Transmit Address r STATE 0 PW5 to 0 1 0 0 0 0 Res The first byte of an address field must be written to DGS1TA. 167 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 27-4: LEN usage, Receive and Transmit Length Bus State State of receive bit logic. Table 27-3: Receiver States LEN 210 Valid Bit Numbers 76543210 STATE Bus 1 001 _______x 00 Passive low 2 010 ______xx 01 Passive high 3 011 _____xxx 10 Active low 4 100 ____xxxx 11 Active high 5 101 ___xxxxx 6 110 __xxxxxx 7 111 _xxxxxxx 0 000 xxxxxxxx PW Pulse Width r: Pulse width The pulse width of the most recently non T-sign is stored in this register. It is measured in increments of 1/64 of the bus clock period. DGRTMD 7 Rx Length & Tx More Data Register 6 5 3 2 1 0 Table 27-5: DGRTMD Interpretation Examples EOFLD Transmit More Data LEN w 4 The examples in Table 27-5 illustrate the interpretation of register DGRTMD. They are valid for an address field (FTYP = 1) or a data field (FTYP = 0). More bytes of a data field must be written to DGRTMD. 6 1 The read part of register DGRTMD is associated with the front entry in the receive FIFO (the receive field DGRTMA). It has to be read and interpreted before the corresponding FIFO entry. Last byte of a field. The six right most bits belong to the field. 0 0 A byte of a field. All bits belong to the field. At least one byte follows. 0 1 Last byte of a field. Eight bits belong to the field. 0 0 Impossible. r RDL NEM FTYP EOFLD x 0 0 x x x LEN2 to 0 x x x Res RDL Receive Data Lost r1: Data lost r0: No data lost The flag RDL from the status register DGS0 is mirrored here. It is cleared by a read access to register DGRTMA. NEM Receive FIFO is Not Empty r1: There is at least one entry. r0: Empty The flag NEM from the status register DGS0 is mirrored here. FTYP, EOFLD, LEN and register DGRTMA are not valid if NEM is false. FTYP r1: r0: Field Type Address field Data field EOFLD End of Field r1: Last byte of a field r0: Not last byte of a field If EOFLD is set, the corresponding FIFO entry is the last part of the actual field. The next entry, if there is one, belongs to a new field. LEN Length of Field r: Length of valid data bit The three bit length doesn't limit the overall length of the corresponding field. The length field defines how many bits of the front entry of the receive FIFO carry valid bits. They are right aligned (Table 27-4). The real length of the field is unlimited. The user must count the bytes he fetched from the FIFO to calculate the real field length. 168 DGRTMA 7 Rx Field & Tx More Address Register 6 5 4 3 w Transmit More Address r Receive Field x x x x x 2 1 0 x x x Res More bytes of an address field must be written to DGRTMA. The bytes of a received field must be read from register DGRTMA. The meaning of this field (address or data) is defined by the flag FTYP. Received bytes of a bit field are right aligned. The last byte of a long bit field (with the LSB) may be filled partially. To get the whole bit field right aligned it is necessary to shift all preceding bytes right. A read access to this register takes the top entry of the receive FIFO. Both registers DGRTMA and DGRTMD are overwritten by the next FIFO entry as result of a read access. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. STATE r: CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 DGTL wait until EMPTY or TGV becomes true before rewriting TxFIFO. Setting of FLUSH clears TGV at the same time. Transmit Length Register 7 6 5 4 3 2 1 w x FLUSH x x x x 0 x x x 0 0 0 r BUSY EMPTY x x x x x x 0 1 x x x x x x EMPTY r1: r0: 0 LEN2 to 0 Res Res The Transmit Length Register is associated with the whole field (address or data) which will be written into the transmit FIFO. It has to be written before the first entry of the field. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. BUSY Transmitter is Busy r1: Busy. r0: Idle. This flag is true as long as there is an entry in the TxFIFO or transmission is not completed. It is set with the first entry into the TxFIFO and reset after the transmission of the first T sign after a telegram. FLUSH Flush Tx FIFO w1: Empty Tx FIFO and abort transmission. w0: No action. This flag will be reset by the HW autonomously. After FLUSH Tx FIFO is Empty No transmit telegram in FIFO. Transmit telegram in FIFO. LEN Length of Field w: Length of address or data field. These three bits correspond to the first byte of a bit field. They define how many bits of this byte carry valid information and should be transmitted (see Table 27-4 on page 168). DGTL must be written before the first byte of the actual bit field is written to the FIFO. It has only to be written once for each bit field. The overall length of the bit field is not limited. DGTD 7 Transmit Data Register 6 5 w 4 3 2 1 0 x x x Transmit Data x x x x x Res The first byte of a data field must be written to DGTD. The first byte of a bit field (with the MSB) which is entered into DGS1TA or DGTD, may be partially filled. In the following bytes all bits must contain valid data. 27.4. Principle of Operation 27.4.1. Reset 27.4.2. Initialization The module reset signal resets all registers and internal HW. The same does a standby bit in a standby register. The corresponding port must be configured special out, double pull-down. Setting flag RUN in register DGC0 resets all internal HW and registers with exception of registers DGC0, DGC1, DGS0 and DGS1TA. These registers are accessible all the time, they are not reset by any setting of the DIGITbus Master flags. After reset and after setting flag DGB in standby register SR0, the DIGITbus master is inactive. The global enable flag RUN must be set together with the appropriate prescaler entry PSC, to activate the module. Internal HW are reset to an inactive state (not transmitting, not receiving). Internal counters are reset to zero. FIFOs and shift registers are empty. Internal representations of the bus line are reset to passive bus level (high). Registers C0 C1 reset S1.TSTn reset SR0.DGB C0.RUN R Q R Q reset Internal HW and remaining registers For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 27.4.2.1. Clock Master The flag GBC (generate bus clock) must be set, if the DIGITbus master should generate the bus clock. The module acts now as clock master of the connected DIGITbus system. It outputs a stream of T-signs. 27.4.2.2. Receiver/Transmitter Setting the flag ACT activates the receive and transmit logic. From now on all telegrams are received in the receive FIFO. Writing to the transmit FIFO initiates transmission of a telegram. The bus clock (T-signs) must be activated some time before the first telegram is transmitted. This is necessary, because other modules may use a PLL for generating the internal clock from the bus clock. No telegram shall be transmitted before all modules have locked on the bus clock. Fig. 27-5: Reset Structure Micronas 169 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 27.4.2.3. Single Master System In a single master system (no collision possible), you can suppress reception of transmitted telegrams by setting flag RXO (receive external only). This unburdens the CPU from clearing the receive FIFO of those telegrams. A telegram has been transmitted correctly, if ARB and ERR are false and EMPTY is true. Transmission starts with the first entry in the transmit FIFO. Consecutive fields should be entered before the transmission of the preceding field is finished. Take care about possible interrupts. 27.4.2.4. Multi Master System Table 27-6: Operating modes RUN GBC ACT RXO Remarks 0 x x x Standby mode 1 0 x x Passive master. External bus clock generation is necessary. 1 1 x x Clock master 1 0 0 x Sleep mode 1 x 1 x Active mode 1 x 1 0 Receive all. (Recommended in multi master system) 1 x 1 1 Receive external only. (Recommended in single master system) 27.4.3. Transmission Transmission is initiated by writing a telegram into the transmit FIFO. If the field length is not a multiple of 8 bit, the total field length modulo 8 has to be written to register DGTL. This must be done once for each field and before any entry to registers DGS1TA, DGTD, DGRTMA or DGRTMD. If the total field length is a multiple of 8 it is not necessary to write the field length to register DGTL. The first entry of a field (address or data) has to be written right aligned to register DGS1TA (address) or DGTD (data). Further entries of the same field, if it is longer than 8 bit, have to be written to DGRTMA (more address) or DGRTMD (more data). A telegram is transmitted MSB first, hence fields have to be written to transmit FIFO MSB first. A new address field is transmitted if there were at least 4 consecutive T-signs on the bus. A new data field is transmitted if there was exactly one T-sign. If the last bit of a field was transmitted and there are no more entries in the transmit FIFO, the transmitter stops sending. After reception of two consecutive T-signs the telegram valid flag TGV is set. This is the signal for the SW to evaluate whether transmission was correct or whether an arbitration loss or an error canceled transmission (flags ARB, PV and ERR). In the latter case SW must initiate retransmission. 170 27.4.3.1. Transmit FIFO SW must ascertain that there is an empty entry in the transmit FIFO before writing to it. Flag NOF (not full) indicates that there is at least one entry free. Flag EMPTY indicates complete emptiness of transmit FIFO. After reset, FLUSH or ARB wait until flag TGV is true before rewriting TxFIFO. Short telegrams can completely be buffered in the FIFO. Managing long telegrams is a SW job. The SW must buffer long telegrams and write the parts in time. The transmit FIFO is intended to unburden the CPU from immediately reaction on an NOF interrupt. If an entry becomes free, the SW has time to write, as long as it needs to transmit two FIFO entries and the contents of the transmit shift register. This time must not necessary be the duration for sending 24 bit. May be only one bit of each remaining FIFO entry has to be send. The transmit FIFO is not intended for telegram tracking. Only one transmit telegram at a time shall be entered. 27.4.4. Reception Every non T sign is shifted into the receive shift register. If it is full or if a T sign was received, the shift register is stored into the receive FIFO. This is done until the receive FIFO is full. In this case, the FIFO is frozen, but the shift register continues operation. The flag RDL indicates the latter case. If the shift register is stored to the receive FIFO because a T sign was received, the corresponding flag EOFLD is set, indicating that this is the last entry of a field. The corresponding flag FTYP is modified at the same time. If two or more consecutive T signs were received in front of the actual field, it is set, indicating that this field has to be interpreted as an address field. If only one T sign has been received in front of the actual field, it is cleared, indicating that it has to be interpreted as a data field. The flag TGV is set if two consecutive T-signs were received. This is the moment to read status flags and Receive FIFO. The flags PV and ERR have to be interpreted. Even if an error occurred, the Receive FIFO must be emptied by reading it because every telegram or fragment is stored there. Otherwise reception of the next telegram may overflow the receive FIFO, which is indicated by flag RDL. Every time you want to read DGRTMA, it is ingenious to read DGRTMD first, because DGRTMD and DGRTMA are overwritten with a read access to DGRTMA. 27.4.4.1. Receive FIFO The receive FIFO contains entries as long as flag NEM is true. Short telegrams can be buffered completely in the receive FIFO. SW must buffer long telegrams and read parts of it in time. Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. In a multi master system it is necessary that each transmitted telegram is received too, because arbitration may be lost and then the transmitter becomes a receiver. If arbitration was not lost, the receive FIFO must be read to empty it. The flag RXO has to be cleared in a multi master system. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 27.4.5. Sleep Mode 27.4.9. Correct Phase Only the receive bit logic is active in sleep mode. Neither transmission nor reception of telegrams is possible. The rising edge of the bus signal can be delayed by inner (sampling and filter) or outer (bus load) influences. This delayed rising edge resets a 6 bit transmit counter in the transmit bit logic. The transmit counter pushes the bus line low when it reaches 15 (transmitting 0) or 31 (transmitting 1). It releases the bus line when it reaches 55. A wake-up (passive high to low edge) is signaled by flag PV. The DIGITbus master is not automatically activated by a wake-up. This has to be done by SW. The flag PV can be used to trigger an interrupt. Switching to Sleep Mode while a telegram is transmitted can cause problems. Hence make sure, that bus clock generation is switched off only if bus is idle (T-signs). 27.4.6. Abort Transmission 27.4.10. Error Writing a one to flag FLUSH aborts the transmission of a telegram after completion of the actual transmitted bit, if the DIGITbus master is the transmitter. The transmit FIFO is emptied and another, more urgent telegram can be transmitted. Transmission of the new telegram starts, as soon as 4 consecutive T signs were received after the aborted telegram. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The transmit counter is reset to a value which contains two zeros at the most significant position and the four PHASE bits of the control register DGC1 at the least significant position. This allows an adjustment of the transmitted non T signs between 0 and 15/64 of the whole bit length. The setting of flag ERR may have one of the following causes: - Wrong baud rate of DIGITbus Master or other bus nodes. - Wrong port configuration of DIGITbus Master. - Disturbances on bus line. Flag TGV is cleared with a FLUSH. This is the reason why TGV is set (and interrupt is triggered if enabled) after reception of 2 T signs, even if no telegram was aborted by FLUSH because it happened during transmission of T signs. - HW damaged of DIGITbus Master. Resetting of Flag TGV is the reason why an aborted address field is marked as data field (FTYP = 0) in the RxFIFO. Don't access DIGITbus registers in CPU Slow and Deep Slow mode. This can cause interrupts. It is not possible to abort a telegram or a field which is transmitted by another bus node. If fXTAL is 5 MHz, a bus clock of 31.25 kHz is only in PLL mode possible (Table 27-2). 27.4.11. Precautions 27.4.7. Interrupt Five flags (RDL, NEM, NOF, TGV, PV) are connected to the interrupt source output by an or operation. This output can be enabled globally by flag INTE. The interrupt generation of two flags (NEM, NOF) can be enabled locally by flags ENEM and ENOF. A rising edge of a flag triggers the interrupt source output. INTE RDL ENEM DIGITbus Interrupt Source & NEM ENOF & OR & NOF TGV PV Fig. 27-6: Interrupt Sources 27.4.8. Measure Pulse Width The pulse width (high time) of every non T sign is stored with the falling edge of the bus signal in status register DGS1TA in the field PW. T signs doesn't affect PW. It must be read before the falling edge of the next non T sign. Micronas 171 Tx stream Tx stream Rx stream 172 D Rx stream T D D D T T T T T T T T T T T T T T T T A T T T A A T A T A T A D T T T D D T D T D T D T T T T T T T T T collision Fig. 27-7: Tx Timing Bus Clock T T txa T T TGV NEM ARB collision Fig. 27-8: Rx Timing Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 27.5. Timings Bus Clock T txa T TGV NEM ARB CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 28. Audio Module (AM) The Audio Module AM provides a gong output signal that may be used to drive a speaker circuit. Features The output signal is a square wave signal with selectable gong frequency. - Programmable gong duration - Programmable gong frequency - Programmable initial amplitude The gong signal amplitude is defined by the pulse width of a PWM signal. An internal accumulator is selectable to automatically decrease this pulse width and thus the gong amplitude following an exponential function. - Gong can be stopped and retriggered - Generation of an exponentially decreasing gong amplitude function without CPU interaction 1/ 32 13 13 - + All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Adder '0x1F' Data Bus 13 Write AMAS (Start/Stop gong sound) 13 13 8 5 AMAS LSBs Amplitude - Latch (13 Bit) MSB 13 Read AMAS 8 S Q R COMP Amplitude=0 ? HW Option AC Data Bus (Bit 7) AMA 8 FAMClock AM Clock U 1.3 AM-PWM AMMCA & 8 Bit - PWM 0 VDD & AM Trigger 8-Bit Counter CLK & FPWM Clear Counter Set Prescaler-Register Write AMPRE Data Bus FGong 5-Bit Counter 7-Bit Counter CLK 1/ 2n Clear Counter Set Frequency-Register 8 CLK 1/( n) 2 Clear Counter Set Decrement-Register Data Bus FDecrement 3 7 AMA Write AMF U 1.4 AM-OUT Write AMDEC Data Bus Fig. 28-1: Block diagram of the audio module Micronas 173 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 28.1. Functional Description The Audio Module output frequency is defined by the following formulas: GDF ln 0.5 - ln AMAS 2 t d ------------------------------------------ ----------------F Gong 1 ln 1 - ------ 32 Frequency: F AMTrigger F AMClock F Gong = ---------------------------------- = ------------------------------------------------------------------2 ( AMF + 1 ) 2 ( AMF + 1 ) ( AMPRE + 1 ) Amplitude: ( AMAS + 1 ) Ampl. ---------------------------------( AMPRE + 1 ) where the maximum amplitude is 1 if AMAS is equal to or bigger than AMPRE. In the latter case the amplitude remains constant until the decay mechanism has decreased AMAS below AMPRE. Every 1st..32nd cycle of the gong sound frequency (depending on the Gong Duration Factor (AMDEC.GDF)) a new amplitude value is calculated (FDecrement). The falling edge of the amplitude decrement frequency FDecrement is latching the output of the adder into the amplitude latch (13 Bit) and simultaneously the 8 MSBs into the PWM. During the first low cycle of FGong following the active FDecreedge the PWM is already running with the newly calculated amplitude, but takes effect at the output not until the next high cycle of FGong. FGong is modulating the PWM-output to generate the gong sound frequency, while the decreasing PWM-value generates an exponential decreasing amplitude. Duration: AMF, AMPRE, AMAS and GDF are register values and described later. The initial gong sound amplitude is set by writing the Audio Module Amplitude & Status Register (AMAS), this write also starts the gong sound. An active audio module is indicated by the read only Audio Module Active Bit (AMA) in the AMAS. As soon as the 8 MSBs of the amplitude latch are reaching zero, the AMA will be reset, which deactivates the audio module. The sound is generated by blocks of pulses 2 x AMF x AMPRE -> FGong AMF x AMPRE One block of pulses AMPRE AMAS (PWM) Fig. 28-2: Sound generation 28.1.1. Hardware Settings The AM clock frequency FAMClock is set by HW option AC. For the effect of CPU clock modes on the operation of this module refer to section "CPU and Clock System" (see Table 4-1 on page 36). 28.1.2. Initialization 28.1.3. Start Gong Prior to entering active mode, proper SW initialization of the Ports has to be made. The ports have to be configured Special Out. Refer to "Ports" for details. The gong sound is started by writing the initial amplitude value into AMAS. Simultaneously with the write to AMAS the Flag Audio Module Active (AMA) is set, which enables the FAMClock-input. Three Audio Module Registers have to be set before the gong sound can be started: the gong prescaler (AMPRE), the gong sound frequency (AMF) and the gong duration factor (AMDEC.GDF) register. 28.1.4. Restart Gong It's possible to restart the gong sound simply by writing a new initial amplitude value to AMAS independent of the 174 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ment CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 former initial value or the current value of the register. (Note: The current amplitude value can't be read out). The new gong sound will start immediately with a low cycle of FGong. To stop the gong sound, just write 0x00 into AMAS. The gong sound then will stop immediately with the writing of 0x00 (also indicated by AMA). 28.1.5. Stop Gong A continuous tone will never stop automatically. It has to be stopped by writing 0x00 into AMAS. The gong sound will stop automatically as soon as the amplitude value in AMAS reaches zero. This will reset the AMA, which indicates the inactive audio module. Conditions: (FPWM = 15.625 kHz; FGong = 601 Hz; AMDEC value = 2, FDecrement = 150.25Hz) A 100 % All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. zoomed gong output signal B after 0 s (initial) 50 % after 0.146 s (0.68) FPWM PWM Pulse Duty Factor C 15 % 0 1 2 3 12 13 14 FGong 15 25 26 after 0.398 s (1.87) 4x A 4x C 4x B Gong Output Pin FGong FDecrement start gong new amplitude (n.a.) n.a. n.a. n.a. n.a. time 0.146 s (0.68) 0s 0.398 s (1.87) Fig. 28-3: Example sections of the audio module output signal 28.1.6. Decay of Sound The decay characteristic used for this gong sound is described by the following exponential function: An A0 (1 - 1/32)n with A0 = initial amplitude (AMAS) An = amplitude after n FDecrement cycles n = int (t * FDecrement) = number of decrement cycles Following the above formula, n can be expressed as ln A n - ln A 0 n ------------------------------1 ln 1 - ------ 32 Micronas Each FDecrement cycle the amplitude is decreased by 1/32. FDecrement is determined by the value of GDF in the register AMDEC and by FGong: F GONG F Decrement = ---------------------GDF = 0...5 GDF 2 With GDF settings of 6 and 7 the gong sound amplitude update frequency FDecrement is zero (continuous tone). The time constant of the above exponential function is defined as the time interval within which the amplitude A is decreasing to 36.8%. 175 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Given n 1 0, 368 = 1 - ----- 32 the number n of FDecrement cycles needed to reduce the initial amplitude to 36.8% is n 32 With an initial amplitude of 0xFF the total time t255->0 needed to reach zero amplitude in the 8 Bit - AMAS is n = 193 FDecrement cycles, which is approximately 6. With an initial amplitude lower than 0xFF the gong sound duration is shorter. That means that is correlating with FDecrement. The higher FDecrement, the shorter is . All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. The total time from a start amplitude A0 to an end amplitude An is approximately calculated according to following formula. ln A n - ln A 0 2 GDF t A A ------------------------------- --------------------F GONG 1 0 n ln 1 - ------ 32 To sum up it can be said that the total duration of the gong sound depends on FGong, set with AMF and AMPRE, the setting of the Gong Duration Factor GDF and the setting of the initial amplitude AMAS. 176 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 240 ADVANCE INFORMATION 260 3 DEC 01 . Decay of Sound - Function Micronas AMAS (MSB of amplitude latch) 220 200 180 160 140 120 100 36.8% 80 40 20 13.5% 5.0% 1.8% 8 1/FDecrement 16 24 32 1 40 48 56 64 2 72 80 88 96 104 112 120 128 136 144 152 160 168 176 184 192 200 3 4 5 time 6 177 no. FDecrement-cycles CDC32xxG-B V3.0 60 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 28.2. Registers 7 Audio Module Amplitude and Status Register 6 5 w r 4 3 2 1 0 Note Initial Amplitude AMA x x x x x x x 0 x x x x x x x Res Initial Amplitude A write access to this register starts or stops the gong sound, while the value written is the initial amplitude. Writing the value 0x0 into this register during an active gong sound deactivates the gong sound immediately, while writing a value > 0x0 is restarting the gong sound immediately with the new Initial Amplitude. wnn: (Re-)Start gong sound with initial amplitude. w00: Stop gong sound. AMA Audio Module Active Flag This flag indicates an active Audio Module generating a gong sound. r1: Audio Module is active. r0: Audio Module is not active. AMF 7 w Audio Module Frequency Register 6 5 x - 4 3 2 1 0 Note 0 0 Res Sound Frequency 0 0 0 0 0 With this register the gong sound frequency is programmed. The PWM frequency is divided by twice the register value increased by one. The value which has to be written, resp. the resulting gong sound frequency is calculated with: F AMTrigger AMF = ---------------------------------- - 1 2F GONG It's possible to write a new gong sound frequency during an active audio module (AMA = '1'). GDF Gong sound Duration Factor This register sets the gong sound duration in dependence of FGong. With GDF=0 the amplitude will be decreased every FGong - cycle, values 1 to 5 will result in a amplitude update frequency of FGong / 2 to FGong / 32 according to this equation: F GONG GDF = 0...5 F Decrement = ---------------------GDF 2 A value of 6 or 7 disables decrease of the amplitude, so a continuous tone with the initial amplitude will be generated (FDecrement = 0). To stop the continuous tone write a 0x00 to AMAS or change the gong sound duration factor to let the tone decay. It's possible to change GDF during an active gong sound (AMA = '1'). Table 28-1: Definition of GDF GDF gong sound duration factor 0x0 1 0x1 2 0x2 4 0x3 8 0x4 16 0x5 32 0x6 continuous tone 0x7 AMPRE 7 Audio Module Prescaler 6 5 w AMDEC 7 w AMMCA 0 AMMCA w1: w0: Audio Module Decrement Register 6 5 4 3 x x x x - - - - 2 1 0 0 0 4 3 2 1 0 Note 1 1 1 Res Prescale Value 1 1 1 1 1 Note GDF 0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. AMAS start, stop, frequency, duration) is the same. The tone is started by writing an initial value to AMAS, but this value will only influence the duration of the tone, not its amplitude. Res Audio Module Maximum Constant Amplitude Flag Activate the AMMCA mode. Deactivate the AMMCA mode. AMPRE defines the frequency of the trigger input of the Audio Module. The AM clock input is divided by the Prescale Value plus one to derive the trigger frequency FPWM. F AMClock AMPRE = ------------------------------- - 1 F AMTrigger AMPRE must be greater than zero. With the flag AMMCA the Audio Module Maximum Constant Amplitude mode is selected. If this Flag is set, the gong sound with the maximum, not decreasing amplitude is available at the audio module output pin. The only difference between this tone and a 'normal' gong sound is the constant, not decreasing amplitude. The handling of this tone (i.e. 178 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 29. Hardware Options 29.1. Functional Description Hardware Options are available in several areas to adapt the IC function to the host system requirements: - clock signal selection for most of the peripheral modules from f0 to f0/217 plus some internal signals (see Table 29-4 on page 181) - Special Out signal selection for some U- and H-ports - Rx/Tx polarity selection for SPI and UART modules Hardware Option setting requires two steps: All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 1. selection is done by programming dedicated address locations in the HW Options field (see Section 29.2. on page 180) with the desired options' code (see Section 29.3. on page 181). 2. activation is done by copying the HW Options field to the corresponding HW Options registers (see Section 29.3. on page 181) at least once after each reset. All HW Options except these listed in table 29-1 are SW progammable. Table 29-1: Port, Clock and CM Option Programmability IC Type IC Name Port Opt. Clock Opt. CM.WC M setting EMU CDC3205G-A mask SW set to 0 CDC3205G-B SW SW set to 0 MCM CDC3207G-B SW SW set to 0 Mask ROM Part SW mask mask In mask ROM derivatives the clock options and the Watchdog, Clock and Supply Monitors are hard wired according to the HW Options field of the ROM code hex file. Those options can only be altered by changing a production mask. To ensure compatible option settings in this IC and mask ROM derivatives when run with the same ROM code, it is mandatory to always write the HW Options field to the HW option registers directly after reset. Micronas 179 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 29.2. Listing of Dedicated Addresses of the Hardware Options Field Table 29-2: HW Options Field Offs. Mne. Options 0x00 T0C Timer 0 Clock 0x01 T1C Timer 1 Clock 0x02 T2C Timer 2 Clock 0x03 T3C Timer 3 Clock 0x04 T4C Timer 4 Clock 0x05 CO00C Clock Out 0: Mux0 Pre. & Clock 0x06 CO01C Clock Out 0: Mux1 Clock 0x07 CO02C Clock Out 0: Mux2 Clock 0x08 DMAC DMA Timer Clock 0x09 CO1C Clock Out 1: Pre. & Clock 0x0A C0C CAPCOM Counter 0 Clock 0x0B C1C CAPCOM Counter 1 Clock 0x0C DC DIGITbus Clock 0x0D LC LCD Pre. & Clock 0x0E AC AM Clock 0x0F PF0C PFM 0 Clock Table 29-2: HW Options Field Offs. Mne. Options 0x10 SMC SM, SPI0, SPI1 Pre. & SM Clock 0x11 SP0C SPI0 I/O & F0SPI Clock 0x12 SP1C SPI1 I/O & F1SPI Clock 0x13 SP2C F2SPI Clock 0x14 P9C PWM 8, 9 Clock 0x15 P9P PWM 8, 9 Period 0x16 P11C PWM 10, 11 Clock 0x17 P11P PWM 10, 11 Period 0x18 P1C PWM 0, 1 Clock 0x19 P1P PWM 0, 1 Period 0x1A P3C PWM 2, 3 Clock 0x1B P3P PWM 2, 3 Period 0x1C P5C PWM 4, 5 Clock 0x1D P5P PWM 4, 5 Period 0x1E P7C PWM 6, 7 Clock 0x1F P7P PWM 6, 7 Period 0x29 PM Port Mux 0x2A CM Clock Monitor 0x2C UA0 UART0 I/O 0x2D UA1 UART1 I/O All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Please refer to section "Memory and Boot System" for the dedicated start address of the HW Options field. 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x2B 0x2E 0x2F 180 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 29.3. HW Options Registers and Code The mapping of the HW Options registers corresponds exactly to the HW Options field in the section above. The order of the HW Options registers description in this section does not correspond to the order of the HW Options field. The emulator IC allow SW programming of the whole registers. Future mask ROM derivatives don't allow to write other clock option values as defined in the HW Options field. The clock options may be programmed to values according to table 29-4 on page 181. Some of the clocks may be pre scaled by a programmable value. Refer to table 29-3 for possible values. Table 29-3: Clock Prescaler All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. PRE Prescale Value Table 29-4: Clock Option Selection Code Clock Option Number Clock Signal Selection Code f0 f0 xxx0.0000 f1 f1 xxx0.0001 f2 f1/21 xxx0.0010 f3 f1/22 xxx0.0011 f4 f1/23 xxx0.0100 f5 f1/24 xxx0.0101 f6 f1/25 xxx0.0110 f7 f1/26 xxx0.0111 f8 f1/27 xxx0.1000 1 0 x 0 direct f9 f1/28 xxx0.1001 0 1 1/1.5 f10 f1/29 xxx0.1010 1 1 1/2.5 f11 f1/210 xxx0.1011 f12 f1/211 xxx0.1100 f13 f1/212 xxx0.1101 f14 f1/213 xxx0.1110 f15 f1/214 xxx0.1111 f16 f1/215 xxx1.0000 f17 f1/216 xxx1.0001 f18 VSS xxx1.0010 f19 T0-OUT xxx1.0011 f20 VSS xxx1.0100 f21 fSM xxx1.0101 f22 1) fSM/28 xxx1.0110 f23 fCC0IN xxx1.0111 f24 fCC1IN xxx1.1000 f25, 26, 27 VSS xxx1.1001 ... f28 f1/21 xxx1.1100 f29, 30 VSS xxx1.1101 ... f31 f1/29 xxx1.1111 If the leading "x" in the Clock sampling table are not used for the purpose of coding other options, they must be replaced by zeros. 1) Clock option f22 is only available if the Stepper Motor Module has been enabled by the standby bit. Micronas 181 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 29.3.1. Timers P3C w Timer 0 Clock 7 6 5 4 3 2 1 x x x Clock Options f1 to f31 x x x 0x01 0 w 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 w Timer 1 Clock 4 3 2 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 1 0 w w 3 2 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 1 0 w 6 5 w 3 2 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 x x x Clock Options f0 to f31 (all) x x x 0x08 1 0 w w 3 2 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 1 0 w The high pulse width of the trigger period must be greater than the high pulse width of the clock the PWM is provided with. w PWM 0, 1 Clock 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 w 182 2 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 1 3 w 0 w Res PWM 0, 1 Period 4 3 2 1 0 Res 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x08 4 3 2 1 0 Res PWM 6, 7 Clock 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 4 3 2 1 0 Res PWM 6, 7 Period 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x08 7 6 5 1 x x x Clock Options f0 to f31 (all) x x x 0x08 0 w Res 4 3 2 1 0 Res PWM 8, 9 Clock 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 P9P 2 4 PWM 4, 5 Period P9C 7 P1P 3 0 Res 7 P7P 4 1 Res 29.3.2. PWMs P1C 2 Res Timer 4 Clock 4 3 PWM 4, 5 Clock P7C T4C 4 Res Timer 3 Clock 4 0 Res 7 P5P T3C 1 Res Timer 2 Clock 4 2 PWM 2, 3 Period P5C T2C 3 Res P3P T1C 4 4 3 2 1 0 Res PWM 8, 9 Period 7 6 5 4 3 2 1 x x x Clock Options f0 to f31 (all) x x x 0x08 0 Res Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. T0C PWM 2, 3 Clock CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 29.3.7. Clock Out P11C w PWM 10, 11 Clock 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 P11P w 4 3 2 1 0 CO00C 7 Res PWM 10, 11 Period 4 3 w 6 5 x x x Clock Options f0 to f31 (all) x x x 0x08 2 1 Res CAPCOM Counter 0 Clock All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. w 5 4 3 2 1 x x x Clock Options f0 to f31 (all) x x x 0x0 3 2 x 0x0 0x11 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 1 Prescaler (Table 29-3) Clock Out 0: Mux1 Clock 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 Res 4 3 2 1 x x x Clock Options f0 to f31 (all) x x x 0x0 0 Res Clock Out 1: Pre. & Clock 6 5 4 3 2 1 x PRE Clock Options f0 to f31 (all) x 0x0 0x11 0 Res Prescaler (Table 29-3) 29.3.8. LCD 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 2 1 0 LCD Pre. & Clock 6 5 4 3 2 1 0 Res 29.3.5. DMA x PRE Clock Options f0 to f31 (all) x 0x0 0x03 PRE Res Prescaler (Table 29-3) DMA Timer Clock 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 4 3 2 1 29.3.9. Stepper Motor and SPIs 0 SMC w 29.3.6. PFM PF0C PFM 0 Clock 4 PRE 3 2 SM, SPI0, SPI1 Pre. & SM Clock Res 7 7 6 5 x x x Clock Options f0 to f31 (all) x x x 0x0 Micronas 0 Clock Out 0: Mux2 Clock PRE w w 1 5 7 w 2 Res DIGITbus Clock DMAC 3 6 LC w 4 7 CO1C 29.3.4. DIGITbus 3 Res 0 w 4 0 Res 7 DC 1 Clock Options f0 to f31 (all) 7 w 2 PRE CO02C CAPCOM Counter 1 Clock 4 3 0 w C1C 4 x CO01C w 6 5 0 29.3.3. CAPCOMs 7 6 PRE 7 C0C Clock Out 0: Mux0 Pre. & Clock 1 6 5 4 3 2 1 x PRE Clock Options f0 to f31 (all) x 0x0 0x0 0 Res Prescaler (Table 29-3) The field PRE of register SMC defines the SPI0 and SPI1 prescaler setting too. 0 Res 183 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 7 SPI0 I/O & F0SPI Clock 6 w SPI0OUT SPI0IN 0 0 5 4 3 2 1 x Clock Options f0 to f31 (all) x 0x0 SPI0OUT w1: w0: SPI0 Data Output Inverter Inverted. Direct. SPI0IN w1: w0: SPI0 Data Input Inverter Inverted. Direct. 0 7 SPI1 I/O & F1SPI Clock 6 w SPI1OUT SPI1IN 0 0 5 4 3 2 Clock Options f0 to f31 (all) x 0x0 SPI1 Data Output Inverter Inverted. Direct. SPI1IN w1: w0: SPI1 Data Input Inverter Inverted. Direct. CC4I w1: w0: CAPCOM4-IN Input from P0.0. Input from U5.3. CACO w1: w0: CAPCOM0, 1, 2-IN Input from U4.1, U2.4, U2.2. Input from U3.2, U3.1, U3.0. U06 w1: w0: U-Port 0.6 outputs CC3-OUT. T4-OUT. U20 w1: U-Port 2.0 outputs CAN0-TX on U4.2. CAN0-RX on U4.3. SCL0 on U2.0. SDA0 on U2.1. CAN0-TX on U2.0 and U4.2. CAN0-RX on U2.1. SCL0, SDA0 not usable. w0: 1 x SPI1OUT w1: w0: U-Port 1.5 outputs CO1. CO0Q. Res The clock is pre scaled by SMC.PRE. SP1C U15 w1: w0: 0 Res H7 w1: w0: H-Port 7 outputs PWM9, 8, 6, 4. SME. H0 w1: w0: H-Port 0 outputs PWM7, 5, 3, 1. SMG. PINT w1: w0: Port interrupts Input from P1.2 to 7. Input from U1.7, U1.6, U1.5, U0.7, U0.5, U0.4. The clock is pre scaled by SMC.PRE. 29.3.12. Clock Monitor SP2C 7 w F2SPI Clock 6 5 4 3 2 1 x x x Clock Options f0 to f31 (all) x x x 0x0 0 CM Res w The clock is pre scaled by SMC.PRE. Clock Monitor 7 6 5 4 3 2 1 0 x WCM x x x x x x x 0 x x x x x x WCM w1: 29.3.10. Audio Module Watchdog, Clock and Supply Monitor Clock & Supply: Always active. Watchdog: Always active. Clock & Supply: deactivatable by SW. Watchdog: activatable by SW. w0: AC AM Clock 7 6 5 4 3 2 1 x x x Clock Options f0 to f31 (all) x x x 0x0 Res 0 29.3.13. UARTs w Res UA0 7 6 5 4 3 2 1 0 U0TX U0RX x x x x x x 0 0 x x x x x x 29.3.11. Port Multiplexers w PM w 184 Port Mux 7 6 5 4 3 2 1 0 U15 CC4I CACO U20 U06 H7 H0 PINT 0 0 0 1 0 0 0 0 Res UART0 I/O U0TX w1: w0: UART0 Tx Output Inverted. Direct. U0RX w1: w0: UART0 Rx Input Inverted. Direct. Res Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. SP0C All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION UA1 w Micronas CDC32xxG-B V3.0 3 DEC 01 UART1 I/O 7 6 5 4 3 2 1 0 U1TX U1RX x x x x x x 0 0 x x x x x x U1TX w1: w0: UART1 Tx Output Inverted. Direct. U1RX w1: w0: UART1 Rx Input Inverted. Direct. Res 185 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 186 ADVANCE INFORMATION 3 DEC 01 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 30. Register Cross Reference Table 30.1. 8 Bit I/O Region Table 30-1: Base address 0x00F80000 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Offs. Byte Address 3 Remarks 2 1 0 0xFFC 0x600 0x5FC 0x400 0x3FC 0x200 0x1FC 0x000 5 CAN reserved Module CAN RAM CAN 2 CAN 1 CAN 0 Table 30-2: Base address 0x00F81000 Offs. 0x1FC 0x0C0 0x0BC 0x094 0x090 0x08C 0x088 0x084 0x080 0x07C 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x014 0x010 0x00C 0x008 0x004 0x000 Micronas Byte Address 3 Remarks 2 1 0 5 CAN reserved Module CAN register CAN2 CTIM ICR IDM IDX REC BT3 TEC BT2 CTIM OCR BT1 ESTR STR CTR CAN1 CTIM ICR IDM IDX REC BT3 TEC BT2 CTIM OCR BT1 ESTR STR CTR CAN0 CTIM ICR IDM IDX REC BT3 TEC BT2 CTIM OCR BT1 ESTR STR CTR 187 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 30-3: Base address 0x00F90000 (formerly 1F00) 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0B0 0x0AC 0x0A8 0x0A4 0x0A0 0x09C 0x080 0x07C 0x078 0x074 0x070 0x06C 0x068 0x064 0x060 0x05C 0x058 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 188 Byte Address 3 TST2 TST5 DGRTMA DGRTMD Remarks 2 TST1 DGTD DGS0 1 TST3 TSTAD3 DGS1TA DGC1 0 TST4 TSTAD2 DGTL DGC0 Module Test DIGITBus 64 byte UA0BR1 UA0IF UA0BR0 AD1 UA0CA UA0C ANAA AD0 UA0IM UA0D ADC UART0 32 byte CC3H CC2H CC1H CC0H CC3L CC2L CC1L CC0L SMVSIN TIM4 SMVC TIM3 TIM0H TIM0L CC5H CC4H CC5L CC4L AMDEC IRPM1 AMF IRPM0 CCC0H CC3I CC2I CC1I CC0I CCC0L CC3M CC2M CC1M CC0M CAPCOM0 SMVCMP CSW1 SMVCOS Core Logic Stepper Motor Module VDO TIM2 TIM1 Timer CCC1H CC5I CC4I CCC1L CC5M CC4M AMAS AMPRE CC3 CC2 CC1 CC0 8 byte Timer0 CAPCOM1 CC5 CC4 16 byte Audio Module Port Interrupt 8 byte UA1BR1 SPI1M SR1 SR0 UA1IF UA1BR0 UA1CA UA1C SPI1D SPI0M UA1IM UA1D CO0SEL SPI0D UART1 Core Logic SPI Core Logic ANAU CSW0 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Offs. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 30-4: Base address 0x00F90100 (formerly 1E00) All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Offs. 0x0FC 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x060 0x05C 0x054 0x050 0x04C 0x048 0x044 0x040 0x03C 0x020 0x01C 0x018 0x014 0x010 0x00C 0x008 0x004 0x000 Micronas Byte Address 3 Remarks 2 1 0 16 byte P7P P3P P11P SP2C PF0C C1C CO02C T3C UA1 PM UA0 CM P7C P3C P11C SP1C AC C0C CO01C T2C P5P P1P P9P SP0C LC CO1C CO00C T1C P5C P1C P9C SMC DC DMAC T4C T0C Module HW Options 96 byte PFM PFM0 PWMC PWM11 PWM7 PWM3 PWM PWM10 PWM6 PWM2 PWM9 PWM5 PWM1 PWM8 PWM4 PWM0 32 byte I2C1 I2CM1 I2CRS1 I2CWD11 I2CRD1 I2CWD01 I2CWP11 I2CWS11 I2C I2CWP01 I2CWS01 I2C0 I2CM0 I2CRS0 I2CWD10 I2CRD0 I2CWD00 I2CWP10 I2CWS10 I2CWP00 I2CWS00 189 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 30-5: Base address 0x00F90400 0x0FC 0x0F8 0x0F4 0x0F0 0x0EC 0x0E8 0x0E4 0x0E0 0x0DC 0x0D8 0x0D4 0x0D0 0x0CC 0x0C8 0x0C4 0x0C0 0x0BC 0x0B8 0x0B4 0x0B0 0x0AC 0x090 0x084 0x080 0x074 0x070 0x064 0x060 0x054 0x050 0x044 0x040 0x034 0x030 0x024 0x020 0x014 0x010 0x004 0x000 190 Byte Address 3 Remarks 2 1 HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI HxLVL HxNS HxTRI 0 HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD HxPIN HxD P2IE P1IE P0IE P2PIN P1PIN P0PIN H-Port7 Module H-Ports H-Port6 H-Port5 H-Port4 H-Port3 H-Port2 H-Port1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Offs. H-Port0 P-Ports P2LVL P1LVL P0LVL UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxMODE UxDPM UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxPIN UxNS UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxLVL UxTRI UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD UxSLOW UxD P-Port 2 P-Port1 P-Port 0 reserved U-Ports U-Port 8 U-Port 7 U-Port 6 U-Port 5 U-Port 4 U-Port 3 U-Port 2 U-Port 1 U-Port 0 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION Offs. 0x0FC 0x050 0x04C 0x048 0x044 0x040 0x03C 0x030 0x02C 0x028 0x024 0x020 0x01C 0x014 0x010 0x00C 0x008 0x004 0x000 Micronas Byte Address 3 CDC32xxG-B V3.0 3 DEC 01 Table 30-6: Base address 0x00F90500 Remarks 2 1 0 GC GD WSR IOC 180 Bytes Module reserved reserved GBus reserved Core Logic Clock, PLL, ERM ERMC PLLC reserved LCD ULCDLD reserved for Patch 191 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 30.2. 32 Bit I/O Region Table 30-7: Base address 0x00FFFD00 Offs. 0x0FC 0x004 0x000 Byte Address 3 Remarks 2 1 0 252 bytes reserved CR Module Core Logic Control Register Table 30-8: Base address 0x00FFFE00 0x0FC 0x020 0x018 0x010 0x008 0x004 0x000 Byte Address 3 Remarks 2 1 0 rsvd Channel 4 to 31 DC3M DC2M DC1M DST Module DMA Channel 3 Channel 2 Channel 1 Control DVB Table 30-9: Base address 0x00FFFF00 Offs. 0x0FC 0x0F4 0x0F0 0x0EC 0x0C8 0x0C4 0x0C0 0x0BC 0x040 0x03C 0x028 0x024 : 0x004 0x000 192 Byte Address 3 Remarks 2 1 0 12 bytes reserved VTB PESRC CRF PRF AFP CRI FIQ registers 40 bytes reserved Module IRQ and FIQ Interrupt Controller IRQ registers PEPRIO 128 bytes reserved Interrupt source nodes ISN39 : ISN7 ISN3 ISN38 : ISN6 ISN2 ISN37 : ISN5 ISN1 ISN36 : ISN4 ISN0 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Offs. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 31. Register Quick Reference Table 31-1: Possible Postfixes Due to HW constraints some multi-byte registers must be accessed byte by byte only. Postfixes (_m_n) may be attached to such register mnemonics if necessary, where "m" stands for the access size in bit (m = 8 or 16) and "n" stands for the byte or half word offset (n = 0, 1, 2, 3). The I/O area is organized in little endian format, thus the LSB, independent of the flag CR.ENDIAN setting, is always stored at the low address. Postfix Access Size Byte Offset _8_0 Byte Byte 0 (LSB) _8_1 Byte 1 _8_2 Byte 2 _8_3 Byte 3 (MSB) _16_0 Half word Low half word _16_1 High half word Table 31-2: Analog Section (Base addr. 0xF90000) All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic Register Name Offs. Register Configuration 7 AD0 ADC Register 0 0x0A8 r AD1 ADC Register 1 0x0A9 6 5 4 3 2 1 0 x x x x TEST AN1 AN0 EOC w Section TSAMP REF CHANNEL 0 0 0 0 0 0 0 0 r AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 w x x x x x x x BUF 0 ANAA Analog AVDD Register 0x0AC r/w EP06 0 Micronas P06 WAIT 13.7. x x x x Res Res BVE 0 Res 193 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-3: Analog Input Ports (Base addr. 0xF90400) Mnemonic P0PIN Register Name Port x Pin Register Offs. 0x0B0 P1PIN 0x0B4 P2PIN 0x0B8 P0IE Port x Input Enable Register P1IE Register Configuration r 0x0B1 r/w 0x0B5 Section 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 1 1 1 1 1 1 1 1 I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 12.1. Res Res I P0LVL 0x0B9 Port x Level Register 0x0B3 P1LVL 0x0B7 P2LVL 0x0BB r/w Res Table 31-4: Audio Module (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 AMPRE Audio Module Prescaler 0x02C AMF Audio Module Amplitude & Status Register Audio Module Frequency Register 0x02D w Audio Module Decrement Register 0x02F 2 1 0 28.2. 1 1 1 1 1 1 1 Res AMA x x x x x x x 0 x x x x x x x Res 0 0 Res 0 Res x w AMMCA 0 194 3 Initial Amplitude - AMDEC 4 Prescale Value w r 0x02E 5 w 1 AMAS 6 Section Sound Frequency 0 0 0 0 x x x x - - - - 0 GDF 0 0 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. P2IE CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-5: Capture-Compare-Unit 0 (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 CC0M 0x06C CC1M 0x070 CC2M 0x074 CC3M 0x078 CC0I All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CAPCOM 0 Mode Register CAPCOM 0 Interrupt Register 0x06D CC1I 0x071 CC2I 0x075 CC3I 0x079 CC0L CC1L CAPCOM 0 Capture/ Compare Register low byte 0x06E 0x072 CC2L 0x076 CC3L 0x07A CC0H CC1H CAPCOM 0 Capture/ Compare Register high byte 0x06F 0x073 CC2H 0x077 CC3H 0x07B CCC0L CAPCOM Counter 0 low byte 0x07C r/w r/w CAPCOM Counter 0 high byte 0x07D 4 3 2 1 OAM 0 17.2. MCMP MOFL FOL 0 0 0 0 0 0 0 0 CAP CMP OFL LAC RCR x x x 0 0 0 0 0 0 0 0 Res IAM 1 Res 1 1 Res 0 0 Res 0 0 Res r Read low byte of capture register and lock it. w Write low byte of compare register and lock it. 1 1 1 1 1 1 1 r Read high byte of capture register and unlock it. w Write high byte of compare register and unlock it. 1 1 r 1 1 1 1 Res Read low byte and lock CCC 0 r 0 0 0 0 Read high byte and unlock CCC 0 Micronas 5 MCAP 0 CCC0H 6 Section 0 0 0 0 0 195 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-6: Capture-Compare-Unit 1 (Base addr. 0xF90000) Register Name Offs. Register Configuration 7 CC4M CAPCOM Mode Register CC5M CC4I CC5L r/w 0x044 CAPCOM Interrupt Register CC5I CC4L 0x040 0x041 r/w 0x045 CAPCOM Capture/ Compare Register low byte 0x042 0x046 CC5H CAPCOM Capture/ Compare Register high byte 0x043 0x047 CAPCOM Counter 1 low byte 0x048 CAPCOM Counter 1 high byte 0x049 2 1 OAM 0 17.2. FOL 0 0 0 0 0 0 0 0 CAP CMP OFL LAC RCR x x x 0 0 0 0 0 0 0 0 Res IAM 1 Res 1 1 Res 0 0 Res 0 0 Res r Read low byte of capture register and lock it. w Write low byte of compare register and lock it. 1 1 1 1 1 1 r Read high byte of capture register and unlock it. w Write high byte of compare register and unlock it. 1 r 1 1 1 1 Res Read low byte and lock CCC 0 r 0 0 0 0 Read high byte and unlock CCC 0 196 3 MOFL 0 CCC1H 4 MCMP 1 CCC1L 5 MCAP 1 CC4H 6 Section All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic 0 0 0 0 0 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-7: Controller Area Network Registers (Base addr. 0xF81000) Mnemonic CAN0CTR Control Register Offs. 0x000 CAN1CTR 0x040 CAN2CTR 0x080 CAN0STR Status Register 0x001 CAN1STR 0x041 CAN2STR 0x081 CAN0ESTR All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Register Name Error Status Register 0x002 CAN1ESTR 0x042 CAN2ESTR 0x082 CAN0IDX Interrupt Index Register 0x003 CAN1IDX 0x043 CAN2IDX 0x083 CAN0IDM Identifier Mask Register 0x004 Register Configuration r/w r r/w 7 6 HLT Section 5 4 3 2 1 0 SLP GRSC EIE GRIE GTIE rsvd rsvd 1 0 0 0 0 0 x x HACK BOFF EPAS ERS rsvd rsvd rsvd rsvd 1 0 0 0 x x x x GDM CTOV ECNT BIT STF CRC FRM ACK 0 0 0 0 0 0 0 0 Res 1 1 1 Res r/w 25.2. Res Res Interrupt Index 1 r/w 1 1 1 1 Identifier Mask Bits 4 to 0 x x x 3 CAN1IDM 0x044 r/w Identifier Mask Bits 12 to 5 2 CAN2IDM 0x084 r/w Identifier Mask Bits 20 to 13 1 r/w Identifier Mask Bits 28 to 21 0 CAN0BT1 Bit Timing Register 1 0x008 CAN1BT1 0x048 CAN2BT1 0x088 CAN0BT2 Bit Timing Register 2 0x009 CAN1BT2 0x049 CAN2BT2 0x089 CAN0BT3 Bit Timing Register 3 0x00A CAN1BT3 0x04A CAN2BT3 0x08A CAN0ICR Input Control Register 0x00B CAN1ICR 0x04B CAN2ICR 0x08B Micronas r/w r/w r/w r/w 0 0 MSAM SYN 0 0 rsvd 0 0 0 0 0 0 Res BPR 0 0 0 0 TSEG2 0 0 Res 0 0 Res Res TSEG1 0 0 0 0 0 0 rsvd rsvd rsvd rsvd rsvd x x x x x 0 0 0 rsvd rsvd rsvd rsvd rsvd XREF REF1 REF0 x x x x x 0 0 0 SJW Res 197 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-7: Controller Area Network Registers (Base addr. 0xF81000) Register Name Offs. Register Configuration 7 CAN0OCR Output Control Register 0x00C CAN1OCR 0x04C CAN2OCR 0x08C CAN0TEC Transmit Error Counter 0x00D CAN1TEC 0x04D CAN2TEC 0x08D CAN0REC Receive Error Counter 0x00E CAN1REC 0x04E CAN2REC 0x08E CAN0CTIM Capture Timer 0x00F CAN1CTIM 0x04F CAN2CTIM 0x08F r/w 6 5 4 3 2 1 0 25.2. rsvd rsvd rsvd rsvd rsvd rsvd rsvd ITX x x x x x x x 0 Res 0 0 0 Res 0 0 Res r Counter Bit 7 to 0 0 r Section 0 0 0 x x 0 Counter Bit 6 to 0 0 0 0 0 0 r Timer Bit 15 to 8 1 r Timer Bit 7 to 0 0 0 0 0 0 0 0 0 0 Res Table 31-8: Core Logic 32 Bit (Base addr. 0xFFFD00) Mnemonic CR Register Name Control Register Offs. 0x000 Register Configuration r/w 7 6 5 4 3 2 1 0 x x x x x x x x 3 x x x TSTTOG x PSA 2 TETM EB1 EBW EASY IBOOT IROM r/w STPCLK RESLNG r/w EB2 TFT r/w JTAG ENDIAN MAP Value of memory location 0x20 to 0x23 198 Section MFM IRAM ICPU 6.1. 1 0 Res Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-9: Core Logic 8 Bit (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 CSW0 ANAU Clock, Supply and Watchdog Register 0 Analog UVDD Register 0x000 0x004 w r/w 6 5 4 3 2 1 0 FHR x x x x x x CMA 0 x x x x x x 1 EAL x x x FVE VE 0 0 0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. SR0 Standby Register 0 0x008 Section LS 0 0 Standby Register 1 0x00C I2C1 I2C0 x x x x CAN2 CAN1 3 r/w TIM2 TIM3 TIM4 UART1 x DGB CCC1 x 2 r/w LCD x PSLW UART0 ADC x TIM1 XTAL 1 r/w SM x x x SPI1 CAN0 CCC0 SPI0 0 Res r/w x x x x x x x x 3 r/w x x x x x x x x 2 r/w x PFM0 PWM11 PWM9 PWM7 PWM5 PWM3 PWM1 1 r/w IRQ FIQ x x x CPUM 0 0x00000001 CO0SEL CSW1 Clock Out 0 Selection Clock, Supply and Watchdog Register 1 0x014 0x060 w Res x x x x x x CO01 CO00 x x x x x x 0 0 Res Res w r Micronas Res r/w 0x00000100 SR1 6. Watchdog Time and Trigger Value 1 1 1 1 1 1 1 1 TST x x FHR CLM PIN POR WDRES - - - 0 0 0 0 0 Res 199 Mnemonic PLLC ERMC IOC WSR 200 Register Name PLL Control ERM Control I/O Control Wait State Register Offs. 0x020 0x024 0x028 0x02C Register Configuration r/w r/w r/w w w 7 6 ACT x r/w INPH 5 4 LCK PLLM x x x x r/w x x EOM x x x x 3 x x x x x x x x x x x NWS 0x00 2 0 x 1 PMF 0 0 x x 0 0 0 TSEL x TOL SUP 0x00000000 IOP 0 Res SWS Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-10: Core Logic 8 Bit (Base addr. 0xF90500) Section 0 6. Res 3 2 1 0 Res Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-11: DIGITbus (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 DGC0 DGC1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. DGS0 DGRTMD Control Register 0 Control Register 1 Status Register 0 Rx Length & Tx More Data Register 0x0F0 0x0F1 0x0F2 0x0F3 r/w Tx Length Register 0x0F4 Status 1 & Tx Address Register 0x0F5 RXO X 0 0 0 0 x INTE ENEM ENOF x 0 0 0 x 0 w x x x TGV r RDL NEM NOF x 0 1 0 r/w w w 0x0F6 Rx Field & Tx More Address Register 0x0F7 0 27.3. PSC 2 to 0 0 0 0 Res 0 0 0 Res PV ERR x ARB 0 0 x 0 Res x Res Res PHASE NEM FTYP EOFLD x 0 0 x x x x FLUSH x x x x 0 x x x 0 0 0 BUSY EMPTY x x x x x x 0 1 x x x x x x Res 0 0 0 Res x x x Res x x x Res w LEN2 to 0 x x LEN2 to 0 Transmit Address STATE PW5 to 0 1 0 w 0 0 Transmit Data x x x x w Transmit More Address r Receive Field x Micronas 1 RDL x DGRTMA 2 Transmit More Data 0 Tx Data Register 3 ACT r DGTD 4 GBC r DGS1TA 5 RUN r DGTL 6 Section x x x x 201 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-12: DMA (Base addr. 0xFFFE00) DVB Register Name DMA Vector Base Offs. 0x000 Register Configuration r/w Section 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 r/w A23 to A16 2 r/w A15 to A8 1 r/w A7 0 0 0 0 0 0 0 0x0000 DST DMA Status 0x004 r/w DE x DMA Channel x Mode 0x008 DC2M 0x010 DC3M 0x018 r/w P r/w EN x SRC x 0 TRIG x 0 Res DMAT x 20.2. Res 0x00 DC1M 3 BYP 1 DIR MAS 0 0x0000 Res Table 31-13: FIQ Interrupt Logic (Base addr. 0xFFFF00) Mnemonic PRF CRF Register Name Pending Register FIQ Control Register FIQ Offs. 0x0F0 0x0F1 Register Configuration r/w r/w Section 7 6 5 4 3 2 1 0 x x x x x x x P x x x x x x x 0 Res GE x x x 0 x x x 0 0 Res 10.2. SEL 0 0 Table 31-14: Graphic Bus Interface (Base addr. 0xF90500) Mnemonic Register Name Offs. Register Configuration 7 GD GC Graphic Bus Data Register Graphic Bus Control Register 0x040 0x044 6 5 r/w r/w 4 3 1 0 Data 0 0x00 Res TIM E 0x00 202 2 Section BSY SEQ DTA 21.2. 0 Res Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-15: Hardware Options Registers (Base addr. 0xF90100) Mnemonic T0C T1C Timer 0 Clock Timer 1 to 4 Clock Offs. 0x0C0 0x0C1 T2C 0x0C2 T3C 0x0C3 T4C 0x0C4 CO00C All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Register Name CO01C Clock Out0: Mux0 Pre. & Clock Clock Out0: Mux1 to Mux3 Clock CO02C DMAC CO1C C0C 0x0C5 0x0C6 DMA Timer Clock Clock Out1: Pre. & Clock CAPCOM Counter Clocks 0x0C8 0x0C9 0x0CA DIGITbus Clock 0x0CC LC LCD Pre. & Clock 0x0CD SMC SP0C w w w w w w 0x0CB DC PF0C w 0x0C7 C1C AC Register Configuration AM Clock PFM 0 Clock SM, SPI0, SPI1 Pre. & SM Clock SPI0 I/O & F0SPI Clock 0x0CE 0x0CF 0x0D0 0x0D1 w w w w 7 6 5 x x x Clock Options f1 to f31 x x x 0x01 x x x Clock Options f0 to f31 (all) x x x 0x0 3 2 1 x PRE Clock Options f0 to f31 (all) x 0x0 0x11 x x x Clock Options f0 to f31 (all) x x x 0x0 x x x Clock Options f0 to f31 (all) x x x 0x0 x PRE Clock Options f0 to f31 (all) x 0x0 0x11 x x x Clock Options f0 to f31 (all) x x x 0x0 x PRE Clock Options f0 to f31 (all) x 0x0 0x03 x x x Clock Options f0 to f31 (all) x x x 0x0 x x x Clock Options f0 to f31 (all) x x x 0x0 x PRE Clock Options f0 to f31 (all) x 0x0 0x0 w SPI0OUT SPI0IN 0 Micronas 4 Section 0 x Clock Options f0 to f31 (all) x 0x0 0 29.3. Res Res Res Res Res Res Res Res Res Res Res Res 203 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-15: Hardware Options Registers (Base addr. 0xF90100) Register Name Offs. Register Configuration 7 SP1C SP2C P9C SPI1 I/O & F1SPI Clock F2SPI Clock PWM Clock 0x0D2 0x0D3 0x0D4 P11C 0x0D6 P1C 0x0D8 P3C 0x0DA P5C 0x0DC P7C 0x0DE P9P PWM Period 0x0D5 P11P 0x0D7 P1P 0x0D9 P3P 0x0DB P5P 0x0DD P7P 0x0DF PM CM UA0 UA1 204 Port Multiplexer Clock Monitor UARTs 0x0E9 0x0EA 0x0EC 0x0ED 6 w SPI1OUT SPI1IN w w w w w w w 5 4 3 2 Section 1 x Clock Options f0 to f31 (all) 0 29.3. 0 0 x 0x0 Res x x x Clock Options f0 to f31 (all) x x x 0x0 x x x Clock Options f0 to f31 (all) x x x 0x0 x x x Clock Options f0 to f31 (all) x x x 0x08 U15 CC4I CACO U20 U06 H7 H0 PINT 0 0 0 1 0 0 0 0 x WCM x x x x x x x 0 x x x x x x U0TX U0RX x x x x x x 0 0 x x x x x x U1TX U1RX x x x x x x 0 0 x x x x x x Res Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic Res Res Res Res Res Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-16: High Current Ports (Base addr. 0xF90400) Mnemonic All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. H0D Register Name High Current Port Data Register Offs. 0x0C0 H1D 0x0C8 H2D 0x0D0 H3D 0x0D8 H4D 0x0E0 H5D 0x0E8 H6D 0x0F0 H7D 0x0F8 H0TRI High Current Port Tristate Register 0x0C1 H1TRI 0x0C9 H2TRI 0x0D1 H3TRI 0x0D9 H4TRI 0x0E1 H5TRI 0x0E9 H6TRI 0x0F1 H7TRI 0x0F9 H0NS H1NS High Current Port Normal/Special Register 0x0C2 0x0CA H2NS 0x0D2 H3NS 0x0DA H4NS 0x0E2 H5NS 0x0EA H6NS 0x0F2 H7NS 0x0FA Micronas Register Configuration r/w r/w r/w Section 7 6 5 4 3 2 1 0 x x x x D3 D2 D1 D0 x x x x 0 0 0 0 x x x x T3 T2 T1 T0 x x x x 0 0 0 0 x x x x S3 S2 S1 S0 x x x x 0 0 0 0 12.5. Res Res Res 205 Mnemonic H0LVL H0PIN 206 Register Name High Current Port Level Register High Current Port Pin Register Offs. 0x0C3 H1LVL 0x0CB H2LVL 0x0D3 H3LVL 0x0DB H4LVL 0x0E3 H5LVL 0x0EB H6LVL 0x0F3 H7LVL 0x0FB 0x0C4 H1PIN 0x0CC H2PIN 0x0D4 H3PIN 0x0DC H4PIN 0x0E4 H5PIN 0x0EC H6PIN 0x0F4 H7PIN 0x0FC Register Configuration r/w r 7 6 5 4 3 2 1 0 x x x x A3 A2 A1 A0 x x x x 0 0 0 0 x x x x P3 P2 P1 P0 x x x x 0 0 0 0 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-16: High Current Ports (Base addr. 0xF90400) Section 12.5. Res Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-17: I2C-Bus Master Interfaces (Base addr. 0xF90100) Mnemonic Register Name Offs. Register Configuration 7 I2CWS00 I2C Write Start Register 0 I2CWS01 I2CWS10 I2C Write Start Register 1 I2C Write Data Register 0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. I2C Write Data Register 1 I2C Write Stop Register 0 I2C Write Stop Register 1 I2C Read Data Register I2CM1 Micronas 0x003 0x004 0x005 0x006 I2C Read Status Register 0x007 0x00B 0x01B 24.2. Res 0x00 w Res I2C Data 0x00 w Res I2C Data 0x00 w Res I2C Data 0x00 w Res I2C Data 0x00 r Res I2C Data 0x00 r 0x017 I2C Mode Register 0 I2C Address 0x016 I2CRS1 I2CM0 w 0x015 I2CRD1 I2CRS0 0x002 1 0x00 0x014 I2CWP11 I2CRD0 0x001 2 I2C Address 0x013 I2CWP01 I2CWP10 3 0x012 I2CWD11 I2CWP00 w 4 0x011 I2CWD01 I2CWD10 5 0x010 I2CWS11 I2CWD00 0x000 6 Section w Res x OACK AACK DACK BUSY WFH RFE x 0 0 0 0 0 0 0 0 DGL SPEED 1 0x02 Res Res 207 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-18: Interrupt Controller Unit (Base addr. 0xFFFF00) Register Name Offs. Register Configuration 7 ISN0 Interrupt Source Node Register 0 0x000 : : : ISN39 Interrupt Source Node Register 39 0x027 CRI Control Register IRQ 0x0C0 AFP PEPRIO PESRC VTB Actual and Forced Priority Register Priority Encoder Priority output Priority Encoder Source output Vector Table Base 0x0C1 0x0C2 0x0C3 0x0C4 r/w r/w 6 5 4 M P E x 0 x 0 x 0 0 0 0 GE TE x x x x x x 0 0 x x x x x x Res 0 0 Res 0 0 0 Res 0 0 0 Res r/w r r r/w 2 1 0 9.3. PRIO APRIO 0 0 0 0 x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 Priority 0 Source 0 0 0 Address bit 23 to 16 r/w 0 0 0 0 3 2 Address bit 15 to 9 0 Res FPRIO r/w r/w 3 Section All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic 0 0 0 1 0 0 0x00000000 Res Table 31-19: LCD (Base addr. 0xF90500) Mnemonic Register Name Offs. Register Configuration 7 ULCDLD Universal Port LCD Load Register 0x010 w LCDSLV 0 208 Section 6 5 4 3 2 1 0 x x x x x x x 0 0 0 0 0 0 0 19.2. Res Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-20: Port Interrupts (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 IRPM0 IRPM1 Interrupt Port Mode Register 0 Interrupt Port Mode Register 1 0x02A 0x02B r/w r/w 6 5 4 PIT3 3 PIT2 2 Section 1 PIT1 0 0 0 0 x x x x x x x x 0 11. PIT0 0 0 0 PIT5 0 Res 0 Res PIT4 0 0 0 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Table 31-21: Pulse Frequency Modulator (Base addr. 0xF90100) Mnemonic Register Name Offs. Register Configuration 7 PFM0 Pulse Width and Period Length Register 0x050 w INV 6 5 4 3 2 1 0 x x x x x x x 3 w Pulse Width 2 w Period Length (High Byte) 1 w Period Length (Low Byte) 0 0x00 Micronas Section 16.2. Res 209 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-22: Pulse Width Modulator (Base addr. 0xF90100) Register Name Offs. Register Configuration 7 PWM0 PWM Register 0x040 PWM1 0x041 PWM2 0x042 PWM3 0x043 PWM4 0x044 PWM5 0x045 PWM6 0x046 PWM7 0x047 PWM8 0x048 PWM9 0x049 PWM10 0x04A PWM11 0x04B PWMC PWM Control Register 0x04F 6 5 4 w w 3 2 Section 1 0 15.2. Pulse width value 0 0 0 0 0 0 0 0 x x P1611 P169 P167 P165 P163 P161 x x 0 0 0 0 0 0 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic Res Table 31-23: Serial Synchronous Peripheral Interfaces (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 SPI0D SPI Data Register SPI1D SPI0M SPI1M 210 0x010 0x011 0x013 5 r/w 0x012 SPI Mode Register 6 r/w 4 3 2 Section 1 0 22.2. Bit 7 to 0 of Rx/Tx Data 0 0 BIT8 LEN9 0 0 0 0 0 RXSEL INTERN 0 0 0 0 SCLK 0 0 Res 0 Res CSF 0 0 Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-24: Stepper Motor VDO (Base addr. 0xF90000) Mnemonic SMVC SMVSIN Register Name Stepper Motor VDO, Control Register Stepper Motor VDO, Sine Register Offs. Register Configuration 0x05A w 0x05B r 7 6 x x x x x x 5 4 0 x All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. SMVCMP Stepper Motor VDO, Back-Up Comparator Register 0x05C 0x05D 0 0 x 0 18.2. QUAD 0 0 x 0 0 x x x x BUSY 0 0 0 Res Res 0 w r/w 1 Res 8bit Sine Value 0 Stepper Motor VDO, Cosine Register 2 SEL w SMVCOS 3 Section 0 8bit Cosine Value 0 0 0 0 0 0 0 0 x ACRF ACRD ACRB ACRG ACRE ACRC ACRA x 0 0 0 0 0 0 0 Res Table 31-25: Test Registers (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 TSTAD2 Test Register AD2 0x0F8 TSTAD3 Test Register AD3 0x0F9 TST5 Test Register 5 0x0FB TST4 Test Register 4 0x0FC TST3 Test Register 3 0x0FD TST1 Test Register 1 0x0FE TST2 Test Register 2 0x0FF Micronas 6 5 w 4 3 2 Section 1 0 6.5. For testing purposes only 0 0 0 0 0 0 0 0 Res 211 Mnemonic TIM0L TIM0H 212 Register Name Timer 0 low byte Timer 0 high byte Offs 0x04E 0x04F TIM1 Timer 1 Register 0x054 TIM2 Timer 2 Register 0x055 TIM3 Timer 3 Register 0x056 TIM4 Timer 4 Register 0x057 Register Configuration 7 1 1 0 6 1 1 0 5 1 1 w 0 4 1 1 0 3 1 0 2 1 1 r Latched high byte of down-counter w High byte of reload value 1 r Read low byte of down-counter and latch high byte w Write low byte of reload value and reload down-counter Reload value 1 1 Res 1 1 1 Res 0 0 0 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-26: Timer (Base addr. 0xF90000) Section 0 14. Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-27: Universal Asynchronous Receiver Transmitters (Base addr. 0xF90000) Mnemonic Register Name Offs. Register Configuration 7 UA0D UART Data Register UA1D 0x0A0 0x018 UART Control and Status Register UA1C 0x0A1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. UA1BR0 UA0BR1 Transmit register r RBUSY UART Baudrate Register high byte UART Interrupt Mask Register UA1IF Micronas 0x0A4 w 0x01C UART Compare Address Register UA1CA UA0IF w 0x0A5 UART Interrupt Flag Register 0x0A6 0x01E r 0 23.3. x x x x x x BRKD FRER OVRR PAER EMPTY FULL TBUSY Res x x 0 x 1 0 0 x x x x STPB ODD PAR LEN x x x x 0 0 0 0 Res Res 0 0 0 Res Res Bit 7 to 0 of Baud Rate 0 0 0 0 x x x - - - 0 0 0 0 0 x x x x x ADR BRK RCVD - - - - - 0 0 0 Res Res w 0x01D 1 0 0 0x01B UA1IM UA0CA 0x0A3 2 x w 0x01A UA1BR1 UA0IM 0x0A2 3 w 0x019 UART Baudrate Register low byte 4 Receive register w UA0BR0 5 r x UA0C 6 Section Bit 12 to 8 of Baud Rate Bit 7 to 0 of address 0 0 0 0 0 0 0 0 Test Test Test Test Test ADR BRK RCVD - - - - - x 0 0 Res 213 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-28: Universal Ports (Base addr. 0xF90400) U0D Register Name Universal Port Data/ Segment 0 Register Offs. 0x000 U1D 0x010 U2D 0x020 U3D 0x030 U4D 0x040 U5D 0x050 U6D 0x060 U7D 0x070 U8D 0x080 U0TRI U1TRI Universal Port Tristate/Segment 1 Register 0x001 0x011 U2TRI 0x021 U3TRI 0x031 U4TRI 0x041 U5TRI 0x051 U6TRI 0x061 U7TRI 0x071 U8TRI 0x081 U0NS U1NS Universal Port Normal-Special/Segment 2 Register 0x002 0x012 U2NS 0x022 U3NS 0x032 U4NS 0x042 U5NS 0x052 U6NS 0x062 U7NS 0x072 U8NS 0x082 214 Register Configuration Section 7 6 5 4 3 2 1 0 r/w D7 D6 D5 D4 D3 D2 D1 D0 Port r/w SG7_0 SG6_0 SG5_0 SG4_0 SG3_0 SG2_0 SG1_0 SG0_0 LCD 0 0 0 0 0 0 0 0 Res r/w T7 T6 T5 T4 T3 T2 T1 T0 Port r/w SG7_1 SG6_1 SG5_1 SG4_1 SG3_1 SG2_1 SG1_1 SG0_1 LCD 1 1 1 1 1 1 1 1 Res r/w S7 S6 S5 S4 S3 S2 S1 S0 Port r/w SG7_2 SG6_2 SG5_2 SG4_2 SG3_2 SG2_2 SG1_2 SG0_2 LCD 0 0 0 0 0 0 0 0 Res 12.3. All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Mnemonic Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-28: Universal Ports (Base addr. 0xF90400) Mnemonic U0DPM All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. U1DPM Register Name Universal Port Double Pull-Down Mode/ Segment 3 Register Offs. 0x003 0x013 U2DPM 0x023 U3DPM 0x033 U4DPM 0x043 U5DPM 0x053 U6DPM 0x063 U7DPM 0x073 U8DPM 0x083 U0SLOW Universal Port Slow Mode Register 0x004 U1SLOW 0x014 U2SLOW 0x024 U3SLOW 0x034 U4SLOW 0x044 U5SLOW 0x054 U6SLOW 0x064 U7SLOW 0x074 U8SLOW 0x084 U0LVL Universal Port Level Register 0x005 U1LVL 0x015 U2LVL 0x025 U3LVL 0x035 U4LVL 0x045 U5LVL 0x055 U6LVL 0x065 U7LVL 0x075 U8LVL 0x085 Micronas Register Configuration Section 7 6 5 4 3 2 1 0 r/w D7 D6 D5 D4 D3 D2 D1 D0 Port r/w SG7_3 SG6_3 SG5_3 SG4_3 SG3_3 SG2_3 SG1_3 SG0_3 LCD 0 0 0 0 0 0 0 0 Res S7 S6 S5 S4 S3 S2 S1 S0 0 0 0 0 0 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 r/w r/w 12.3. Res Res 215 Mnemonic U0PIN U0MODE 216 Register Name Universal Port Pin Register Universal Port Mode Register Offs. 0x006 U1PIN 0x016 U2PIN 0x026 U3PIN 0x036 U4PIN 0x046 U5PIN 0x056 U6PIN 0x066 U7PIN 0x076 U8PIN 0x086 0x007 U1MODE 0x017 U2MODE 0x027 U3MODE 0x037 U4MODE 0x047 U5MODE 0x057 U6MODE 0x067 U7MODE 0x077 U8MODE 0x087 Register Configuration r r/w 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 x x x x x x x x L7 L6 L5 L4 L3 L2 L1 L0 0 0 0 0 0 0 0 0 Res All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 31-28: Universal Ports (Base addr. 0xF90400) Section 12.3. Res Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 32. Control Register and Memory Interface 32.1. Control Register CR Emu Bus configured for external Flash memory. Pin signals FBUSQ, BWQ0 to 3 and CE1Q are disabled and pulled low weakly. In CPU SLOW mode pin signal CE0Q activates flash memory only for 1/128th of access cycle. Emu Bus configured for standard external Memory. CE0Q always enables memory for full access cycle. When exiting Reset, the device will start up in a configuration defined by the CR setting. For details on how to set the CR see chapter "Core Logic". A full description of the functionality of all CR bits is given below. Among others, the CR allows to configure the memory interface for connection to a variety of external memories. Control Register 6 5 4 3 2 1 x x x x x x x x 3 x x x TSTTOG x PSA 2 TETM EB1 EBW EASY IBOOT IROM EB2 TFT r/w JTAG ENDIAN MAP MFM IRAM ICPU Value of memory location 0x20 to 0x23 1 0 Res The upper half word of register CR is loaded from location 0x22/0x23 only if flag EBW is at zero. If EBW is at one, the upper half word is initialized to 0xFFFB. STPCLK Stop Clock (Emu parts only) r/w1: Timers are stopped in debug mode. r/w0: Timers are working during debug mode. Timers are stopped with a resolution of 1/f0. RESLNG Reset Pulse Length r/w1: Pulse length is 8/FXTAL r/w0: Pulse length is 2048/FXTAL This bit specifies the length of the reset pulse which is output at pin RESETQ following an internal reset. If pin TEST is 1 the first reset after power on is short. The following resets are as programmed by RESLNG. If pin TEST is 0 all resets are long. TSTTOG TEST2 Pin Toggle (Table 32-8) This bit is used for test purposes only. If TSTTOG is true in IC active mode, pin TEST2 can toggle the Multi Function pins between Bus mode and normal mode. PSA Program Storage Access r/w1: 16bit access. r/w0: 32bit access. This bit allows, in EMU parts, to set the data bus access width to ROM, BootROM and Flash program storage. EB2 r/w1: r/w0: External Bus Flag 2 (Table 32-1) CE0Q and CE1Q select two external chips. OEQ and WEQ select one external chip connected to CE0Q (don't use CE1Q). TFT Trace Bus Full Trace (Emu parts only, Table 32-2) TETM Trace Bus ETM (Emu parts only, Table 32-2) EB1 External Bus Flag 1 (Emu/MCM parts only, Table 32-1) Power saving mode of memory interface. r/w1: Micronas r/w1: r/w0: EASY Emu Bus in Asynchronous Mode (Table 32-1) (Emu/MCM parts only) r/w1: Emu Bus configured for asynchronous external memory. r/w0: Emu Bus configured for synchronous external memory. In synchronous mode the address bus (A) and chip enable (CExQ) latches are transparent. Table 32-1: Emu bus configuration for some commonly used external memories External Memory Type EASY r/w Emu Bus Width (Emu/MCM parts only, Table 32-1) Emu Bus configured for 16bit wide external memory. Bits CR.PSA, CR.STPCLK and CR.RESLNG are forced to one and bit CR.TSTTOG is forced to zero. Emu Bus configured for 32bit wide external memory. Offs EBW All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. r/w STPCLK RESLNG 0 EB1 r/w EBW 7 EB2 CR r/w0: 1 0 0 0 32-Bit sync SRAM (e.g. MT55L256L32F) 0 1 0 1 32-Bit async Flash (e.g. 2 x Am29F400BT) 0 1 1 1 0 0 0 1 0 0 1 1 MFM Program Memory (CE0Q) 16-Bit async. Flash (e.g. Am29F400BT) Data or BOOT Memory (CE1Q) don't use 32-Bit async Flash (e.g. 2 x Am29LV400BT) 16-Bit async. Flash (e.g. Am29LV400BT) don't use Multi Function pin Mode (Tables 32-8) 217 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 JTAG r/w1: r/w0 Application JTAG Interface Enabled if TEST2 pin is high (Fig. 32-2) Disabled ENDIAN Endian setting ARM Core r/w1: Little endian. r/w0: Big endian. Don't change this flag dynamically MAP IBOOT Internal Boot ROM (Tables 32-4, 32-7) IROM Internal ROM (Table 32-5) IRAM Internal RAM (Tables 32-6, 32-7) ICPU r/w1: r/w0: Internal CPU Enable internal CPU. Disable internal CPU Mapping (Table 32-3) ICPU Data Bus CPU IRAM MFM0 MFM1 & 0 Mux 1 Ports 1 Test Bus & predecram IROM predecrom IRAM predecram IROM predecrom IBOOT predecboot predecio & ROM IBOOT predecboot & & & 1 & 1 & external access & Boot Emu only 1 TFT MFM0 MFM1 EMUTRI & EMUTRI Addr. & Ctrl. Mem Ifc TETM ETM TFT Analyzer & 0 Mux 1 Trace Bus Fig. 32-1: Bus Interfaces TEST2 & nTRST 1 Emu only Emu. JTAG interface Table 32-2: TETM and TFT Usage TETM Appl. JTAG interface TFT CR.JTAG Trace Bus Mode 1 1 Disabled (Gnd) (Except for DBGACK, nRESET, FSYS) for external memory access only Off 0 1 Analyzer always Off 1 0 ETM for external memory access only On 0 0 ETM always On Fig. 32-2: Enabling JTAG Interfaces 218 D0 to D31 active ETM Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. MFM0 MFM1 TESTTOG TEST2 Pin RAM CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Mapping Effect Multi Function Pins 1 0 TEST2 Pin MAP Table 32-8: TSTTOG and MFM usage in ROM/Flash parts TSTTOG Table 32-3: MAP usage 0 0 0 x Bus mode 0 1 0 Bus mode 0 1 Port mode 0 x Bus mode 1 1 0 Bus mode 1 1 Port mode 0 x Bus mode 2 1 0 Bus mode 2 1 Port mode x Port mode MFM 1 0 0 0 mirrors RAM base offset 0xC0.0000 to 0 0 1 maps ROM/Flash base offset 0x20.0000 to 0 1 x mirrors Boot ROM base offset 0xF0.0000 to 0 IBOOT 0 MFM selected Boot ROM source 1 0 QFP128 0 0 x external via Multi Function pins in Bus mode x 0 1 1 disable Boot ROM x x internal Boot ROM 1 1 Emu 1 0 ext. via Emu bus 1 1 x IROM Table 32-5: IROM usage selected ROM/Flash source 0 external via Multi Function pins in Bus mode 1 internal ROM/Flash QFP128 Emu external via Emu bus IRAM Table 32-6: IRAM usage MFM selected RAM source 1 0 QFP128 0 0 x external via Multi Function pins in Bus mode x 0 1 1 disable RAM x x internal RAM 1 Emu ext. via Emu bus IBOOT Table 32-7: CE1Q Selections IRAM All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Table 32-4: IBOOT usage CE1Q selects 0 x external internal 1 0 internal external 1 1 No external access Micronas RAM Boot ROM 219 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 32.2. External Memory Interface 32.2.1. Interfacing examples EVDD = 5V is required for the following interfacing examples. 5V CE0Q CE# RESET# OEQ OE# BYTE# WEQ/RWQ WE# RY/BY# Flash-EEPROM 256k x 16 A[17:0] A[18:8], AICU[7:2], AMCS1 DQ[15:0] D[15:0] GND BWQ0 BWQ1 BWQ2 BWQ3 5V CE# WE# WE# WE# WE# OE# A[18:0] OE# A[18:0] I/O[7:0] OE# A[18:0] I/O[7:0] I/O[7:0] asyn. SRAM 512k x 8 CE# asyn. SRAM 512k x 8 CE# asyn. SRAM 512k x 8 CE# OE# A[18:0] I/O[7:0] GND A[20:8], AICU[7:2] D[31:0] asyn. SRAM 512k x 8 CExQ OEQ D[31:24] D[23:16] D[15:8] D[7:0] Fig. 32-4: Asynchronous SRAM (e.g. KM684002B) as emulation program memory 3V3 CE0Q WEQ/RWQ BWQ[3:0] A[19:8], AICU[7:2] D[31:0] 5V to 3V3 Level Shifter FBUSQ CLK CKE CE# MODE R/W# ZZ BW#[d:a] CE2 SSRAM 256k x 32 CE2# SA, SA1,SA0 DQ[d:a] OE# ADV/LD# GND Fig. 32-5: Synchronous SRAM (e.g. MT55L256L32F) as emulation program memory 220 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. Fig. 32-3: Asynchronous Flash EEPROM (e.g. Am29F400B) as program memory CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 3V3 5V to 3V3 Level Shifter FBUSQ CE1Q WEQ/RWQ BWQ[3:0] A[19:8], AICU[7:2] CLK CKE CE# MODE R/W# ZZ BW#[d:a] CE2 SSRAM 256k x 32 CE2# SA, SA1,SA0 OE# DQ[d:a] D[31:0] ADV/LD# GND Fig. 32-6: Synchronous SRAM (e.g. MT55L256L32F) as emulation RAM or boot memory 32.2.2. External Trace Interfacing All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. For a mapping of the IC pins to external trace tools see the Specification of the Evaluation Board Kit (EVB). 32.2.3. Memory Interface Characteristics Table 32-9: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.5V<EVDDn<5.5V, TCASE= 0 to 35 C, CL = 70pF Symbol Parameter Min. DFBUSQ FBUSQ High to Low Ratio 47.5 Typ. Max. Unit Test Conditions 52.5 % PLL mode ns 13ns ADB to Pad, 4ns Pad to DB Synchronous SRAM tsAS sync Address Setup Time 0 tsAH sync Address Hold Time tsCES sync Chip Enable Setup 0 tsDSR sync Data Setup Read Time 25 tsDHR sync Data Hold Read Time tsDSW sync Data Setup Write Time tsDDT sync Data drive Tristate 0 ns 20 ns ns 0 0 ns 15 0 ns ns Asynchronous SRAM taAS async Address Setup Time taAH async Address Hold Time taCES async Chip Enable Setup taOES async Output Enable Setup 0 ns taBWS async Byte Write Setup 0 ns taDSR async Data Setup Read taDHR async Data Hold Read Time Micronas 0 10 0 0 ns 10 25 ns ns ns 0 ns 221 CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 Table 32-9: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 4.5V<EVDDn<5.5V, TCASE= 0 to 35 C, CL = 70pF Symbol Parameter Min. taDSW async Data Setup Write 0 taDDT async Data drive Tristate Typ. Max. Unit 15 ns 0 Test Conditions ns Table 32-10: UVSS=UVSS1=FVSS=HVSSn=EVSSn=AVSS=0V, 3.5V<AVDD=UVDD=UVDD1<5.5V, 3V<EVDDn=FVDD<3.6V, TCASE= -40 to 85 C, CL = 10pF Symbol Parameter Min. Typ. Max. Unit Test Conditions ns 12ns ADB to Pad, 5ns Pad to DB Asynchronous Flash taAS async Address Setup Time 0 nWAIT FBUSQ tsAS A A1 tsAH A2 A3 tsCES tsAH CExQ tsAS tsAH WEQ/RWQ tsAS tsAH BWQ[3:0] tsDSR D[31:0] D1 6) read data 6) read data tsDSW tsDHR D2 D3 6) tsDDT 6) write data Fig. 32-7: Sync SRAM Timing, 0 Wait States 222 Micronas All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. FSYS All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. ADVANCE INFORMATION A A1 D[31:0] A D1 6) write data, no wait state Micronas CDC32xxG-B V3.0 3 DEC 01 FSYS nWAIT FBUSQ tsAS A2 tsAH tsCES CExQ tsAH WEQ/RWQ BWQ[3:0] D1 tsDSR D2 6) read data, no wait state 6) read data, 1 wait state tsAS A1 tsCES tsAS tsAS D[31:0] tsDSW 6) D2 write data, 1 wait state tsDHR 6) write data Fig. 32-8: Sync SRAM Timing, Read with Wait State, followed by a Write Cycle FSYS nWAIT FBUSQ A2 tsAH CExQ tsAH WEQ/RWQ tsAH BWQ[3:0] tsAH tsDDT 6) read data Fig. 32-9: Sync SRAM Timing, Write with Wait State, followed by a Read Cycle 223 taCES taAS A 224 A1 6) A D[31:0] A2 D1 write data 6) read data, no wait state 6) read data A3 taOES taBWS D[31:0] taDSR D2 A1 6) D1 taDHR D3 read data taCES taAS taOES taDSR 6) read data, 1 wait state taDSW 6) D4 Fig. 32-10: Async SRAM/Flash Timing, 0 Wait States FSYS nWAIT FBUSQ taAH CExQ A2 taAH All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 FSYS nWAIT FBUSQ CExQ taAH taAH A4 taAH OEQ BWQ[3:0], WEQ/RWQ taAH taDDT write data 6) OEQ taAH BWQ[3:0], WEQ/RWQ D2 taDHR 6) write data Fig. 32-11: Async SRAM/Flash Timing, Read with Wait State, followed by a Write Cycle Micronas CDC32xxG-B V3.0 ADVANCE INFORMATION 3 DEC 01 FSYS nWAIT FBUSQ taCES taAH CExQ taAS A taAH A2 A1 OEQ taAH taBWS BWQ[3:0], WEQ/RWQ taDSW D[31:0] D1 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Product or development sample availability and delivery are exclusively subject to our order confirmation form. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Micronas GmbH's written consent must be obtained for reprinting. 6) write data, no wait state taDDT D2 6) write data, 1 wait state 6) read data Fig. 32-12: Async SRAM/Flash Timing, Write with Wait State, followed by a Read Cycle 6) During the high level of FBUSQ the previous data bus levels are weakly held. Thus the data bus is defined when the bus drivers are tristate and FBUSQ is high. See section `Electrical Characteristics' for the weak hold currents for pull-down (Ipd) and for pull-up (Ipu). fast mode slow mode FSYSint FBUSQint CE0Q WEQ/RWQ OEQ Fig. 32-13: CE0Q Timing in PLL/FAST and SLOW/DEEP SLOW modes (CR.EB2 set to 0, CR.EB1 and CR.EASY set to 1) CE0Q is used for low power mode. Input data are latched with the rising edge of CE0Q and are weakly held as long as CE0Q stays high. Micronas 225 CDC32XXG-B V3.0 ADVANCE INFORMATION 3 DEC 01 33. Data Sheet History 1. Advance Information: "CEVG-1 V1.0 Automotive Controller Emulator", Oct. 16, 2000, 6251-529-4AI. First release of the advance information. Originally created for HW version CEVG11. 2. Advance Information: "CEVG-2 V0.1 Automotive Controller Emulator", Feb. 13, 2001, 6251-546-1AI. Second release of the advance information. Originally created for HW version CEVG21. 3. Advance Information: "CEVG-2 V1.0 Automotive Controller Emulator", 19 APR 01, 6251-546-2AI. Third release of the advance information. Originally created for HW version CEVG21. 4. Advance Information: "CDC32xxG-B V2.0 Automotive Controller Emulator", 11 JUN 01, 6251-546-3AI. Fourth release of the advance information. Originally created for HW versions CDC3205G-B2 and CDC3207G-B1. 5. Advance Information: "CDC32xxG-B V3.0 Automotive Controller - Family Hardware Manual CDC3205G-B Automotive Controller Specification", 3 DEC 01, 6251-546-4AI. Fifth release of the advance information. Originally created for HW versions CDC3205G-B4 and CDC3207G-B3. Former document V2.0 has been split into two documents, one being the "CDC3207G-B V3.0 Automotive Controller Specification", describing the MCM Flash hardware, and this document "CDC32xxG-B V3.0 Automotive Controller - Family Hardware Manual and CDC3205G-B Automotive Controller Specification", describing the EMU hardware. Chapters only corrected and edited: 5., 17., 20., 21., 22., 23., 25., 29. Chapters changed due to changed functionality: 1., 2., 3., 4., 6., 7., 8., 9., 11., 13., 16., 24., 31., 32. Chapters added: Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-546-4AI 226 All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. 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