MB39A136PFT-G-BND-JNE1 - Spansion

The following document contains information on Cypress products.

FUJITSU SEMICONDUCTOR

DATA SHEET

2013.1

ASSP for Power Management Applications

(General-Purpose DC/DC Converter)

2ch PFM/PWM DC/DC converter IC

with synchronous rectification

MB39A136

■DESCRIPTION

MB39A136 is 2ch step-down DC/DC converter IC of the current mode N-ch/N-ch synchronous rectification

method. It contains the enhanced protection f eatures, and supports the symmetrical-phase method and the

ceramic capacitor. MB39A136 realizes rapid response, high efficiency, and low ripple voltage, and its high-

frequency operation enables the miniaturization of inductors and I/O capacitors.

■FEATURES

• High efficiency

• For frequency setting by external resistor : 100 kHz to 1 MHz

• Error Amp threshold voltage : 0.7 V ± 1.0%

• Minimum output voltage value : 0.7 V

• Wide range of power-supply voltage : 4.5 V to 25 V

• PFM/PWM auto switching mode and fixed PWM mode selectable

• Supports Symmetrical-Phase method

• With built-in over voltage protection function

• With built-in under voltage protection function

• With built-in over current protection function

• With built-in over-temperature protection function

• With built-in soft start/stop circuit without load dependence

• With built-in synchronous rectification type output steps for N-ch MOS FET

• Standby current : 0 [μA] Typ

• Small package : TSSOP-24

■APPLICATION

• Digital TV

• Photocopiers

• Surveillance cameras

• Set-top boxes (STB)

• DVD players, DVD recorders

•Projectors

• IP phones

• Vending machine

• Consoles and other non-portable devices

DS04-27262-4E

MB39A136

2DS04-27262-4E

■PIN ASSIGNMENT

(TOP VIEW)

(FPT-24P-M09)

16 LX2

CB1

DRVH1

LX1

DRVL1

VCC

GND

DRVL2

DRVH2

CB2

MODE

CTL1

CS1

FB1

COMP1

ILIM1

VREF

CTL2

ILIM2

COMP2

FB2

CS2

MB39A136

DS04-27262-4E 3

■PIN DESCRIPTION

Pin No. Symbol I/O Description

1 CTL1 I CH1 control pin.

2 CS1 I CH1 soft-start time setting capacitor connection pin.

3 FB1 I CH1 Error amplifier inverted input pin.

4 COMP1 O CH1 error amplifier output pin.

5 ILIM1 I CH1 over current detection level setting voltage input pin.

6RT⎯Oscillation frequency setting resistor connection pin.

7 VREF O Reference voltage output pin.

8CTL2 I CH2 control pin.

9 ILIM2 I CH2 over current detection level setting voltage input pin.

10 COMP2 O CH2 error amplifier output pin.

11 FB2 I CH2 Error amplifier inverted input pin.

12 CS2 I CH2 soft-start time setting capacitor connection pin.

13 MODE I PFM/PWM switch pin. (CH1 and CH2 commonness) It becomes fixed

PWM operation with the VREF connection, and it becomes PFM/PWM

operation with the GND connection.

14 CB2 ⎯CH2 connection pin for boot strap capacitor.

15 DRVH2 O CH2 output pin for external high-side FET gate drive.

16 LX2 ⎯CH2 inductor and external high-side FET source connection pin.

17 DRVL2 O CH2 output pin for external low-side FET gate drive.

18GND ⎯Ground pin.

19 VB O B ias voltage output pin.

20 VCC ⎯Power supply pin for reference voltage and control circuit.

21 DRVL1 O CH1 output pin for external low-side FET gate drive.

22 LX1 ⎯CH1 inductor and external high-side FET source connection pin.

23 DRVH1 O CH1 output pin for external high-side FET gate drive.

24 CB1 ⎯CH1 connection pin for boot strap capacitor.

MB39A136

4DS04-27262-4E

■BLOCK DIAGRAM

−

+−

−

FB1

COMP1

CS1

CS2

COMP2

FB2

ILIM1

ILIM2

5.5

μA

VREF

<Soft-Start,

Soft-Stop>

/uvlo

ovp_out

<CH1> 13MODE

70 kΩ

ctl1

/uvp_out

/otp_out

intref

ovp1

intref

x 0.7 V

intref

x 1.15 V

uvp1

ovp1

ovp2

<CH2>

uvp1

uvp2

50 μs

delay

512/f

OSC

delay

ovp_out

uvp_out

UVLO

<UVLO>

VREF

UVLO

uvlo

H:UVLO

release

OTP

otp_out

Drive

Logic

Hi-side

Drive

Bias

Reg.

RS-FF

20VCC

SQR

Clock

generator

ch.1 180° out of phase

6RT

ch.2

pfm1 pfm2

2.0 V

CLK VB

Lo-side

Drive Level

Converter

24 CB1

DRVH1

LX1

19 VB

21 DRVL1

CB2

DRVH2

DRVL2

LX2

CTL1

CTL2

intref(3.3 V)

718

ON/OFF

GNDVREF

ctl1, ctl2

The configuration of a control circuit is the same as that of CH1.

MB39A136

DS04-27262-4E 5

■ABSOLUTE MAXIMUM RATINGS

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

Parameter Symbol Conditions Rating Unit

Min Max

Power-supply voltage VVCC VCC pin ⎯27 V

CB pin input voltage VCB CB1, CB2 pins ⎯32 V

LX pin input voltage VLX LX1, LX2 pins ⎯27 V

Voltage between CB and LX VCBLX ⎯⎯7V

Control input voltage VICTL1, CTL2 pins ⎯27 V

Input voltage

VFB FB1, FB2 pins ⎯VVREF + 0.3 V

VILIM ILIM1, ILIM2 pins ⎯VVREF + 0.3 V

VCSx CS1, CS2 pins ⎯VVREF + 0.3 V

VMODE MODE pin ⎯VVB + 0.3 V

Output current IOUT DC DRVL1, DRVL2 pins,

DRVH1, DRVH2 pins ⎯60 mA

Power dissipation PDTa ≤ + 25 °C⎯1644 mW

Storage temperature TSTG ⎯ − 55 + 150 °C

MB39A136

6DS04-27262-4E

■RECOMMENDED OPERATING CONDITIONS

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Parameter Symbol Conditions Value Unit

Min Typ Max

Power supply voltage VVCC ⎯4.5 ⎯25.0 V

CB pin

input voltage VCB ⎯⎯⎯30 V

Reference voltage

output current IVREF ⎯ − 100 ⎯⎯μA

Bias output current IVB ⎯ − 1 ⎯⎯mA

CTL pin input voltage VICTL1, CTL2 pins 0 ⎯25 V

Input voltage

VFB FB1, FB2 pins 0 ⎯VVREF V

VILIM ILIM1, ILIM2 pins 0.3 ⎯1.94 V

VCS CS1, CS2 pins 0 ⎯VVREF V

VMODE MODE pin 0 ⎯VVREF V

Peak output current IOUT DRVH1, DRVH2 pins

DRVL1, DRVL2 pins

Duty ≤ 5% (t = 1/fOSC × Duty) − 1200 ⎯ + 1200 mA

Operation frequency

range fOSC ⎯100 500 1000 kHz

Timing resistor RRT RT pin ⎯47 ⎯kΩ

Soft start capacitor CCS CS1, CS2 pins 0.0075 0.0180⎯μF

CB pin capacitor CCB CB1, CB2 pins ⎯0.1 1.0 μF

Reference voltage

output capacitor CVREF VREF pin ⎯0.1 1.0 μF

Bias voltage output

capacitor CVB VB pin ⎯2.2 10 μF

Operating ambient

temperature Ta ⎯ − 30 + 25 + 85 °C

MB39A136

DS04-27262-4E 7

■ELECTRICAL CHARACTERISTICS

(Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0A)

(Continued)

Parameter Symbol Pin

No. Conditions Value Unit

Min Typ Max

Reference

Voltage

Block

[REF]

Output voltage VVREF 7⎯3.24 3.30 3.36 V

Input stability VREF

LINE 7VCC pin = 4.5 V to 25 V ⎯110mV

Load stability VREF

LOAD 7VREF pin = 0 A to

− 100 μA⎯110mV

Short-circuit out-

put current VREF

IOS 7 VREF pin = 0 V − 14.5 − 10.0 − 7.5 mA

Bias Voltage

Block

[VB Reg.]

Output voltage VVB 19 ⎯4.85 5.00 5.15 V

Input stability VB

LINE 19 VCC pin = 6 V to 25 V ⎯10 100 mV

Load stability VB

LOAD 19 VB pin = 0 A to − 1 mA ⎯10 100 mV

Short-circuit out-

put current VB

IOS 19 VB pin = 0 V − 200 − 140 − 100 mA

Under volt-

age Lockout

Protection

Circuit Block

[UVLO]

Threshold voltage VTLH1 19 VB pin 4.0 4.2 4.4 V

VTHL1 19 VB pin 3.4 3.6 3.8V

Hysteresis width VH1 19 VB pin ⎯0.6* ⎯V

Threshold

voltage VTLH2 7 VREF pin 2.7 2.9 3.1 V

VTHL2 7 VREF pin 2.5 2.7 2.9 V

Hysteresis width VH2 7VREF pin ⎯0.2* ⎯V

Soft-start /

Soft-stop

Block

[Soft-Start,

Soft-Stop]

Charge current I CS 2, 12 CTL1, CTL2 pins = 5 V,

CS1, CS2 pins = 0 V − 7.9 − 5.5 − 4.2 μA

Soft-start

end voltage VCS 2, 12 CTL1, CTL2 pins = 5 V 2.2 2.4 2.6 V

Electrical dis-

charge resistance

at soft-stop RDISCG 2, 12 CTL1, CTL2 pins = 0 V,

CS1, CS2 pins = 0.5 V 49 70 91 kΩ

Soft-stop

end voltage VDISCG 2, 12 CTL1, CTL2 pins = 0 V ⎯0.1* ⎯V

Clock

Generator

Block

[OSC]

Oscillation

frequency fOSC 6RT pin = 47 kΩ450 500 550 kHz

Oscillation

frequency when

under voltage is

detected

fSHORT 6RT pin = 47 kΩ⎯62.5 ⎯kHz

Frequency

Temperature

variation df/dT 6 Ta = − 30 °C to + 85 °C⎯3* ⎯%

MB39A136

8DS04-27262-4E

(Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0 A)

(Continued)

Parameter Symbol Pin

No. Conditions Value Unit

Min Typ Max

Error Amp

Block

[Error Amp1,

Error Amp2]

Threshold

voltage EVTH 3, 11 ⎯0.693 0.700 0.707 V

EVTHT 3, 11 Ta = − 30 °C to + 85 °C0.689* 0.700* 0.711* V

Input current IFB 3, 11 FB1, FB2 pins = 0 V − 0.1 0 + 0.1 μA

Output current

ISOURCE 4, 10 FB1, FB2 pins = 0 V,

COMP1, COMP2 pins =

1 V − 390 − 300 − 210 μA

ISINK 4, 10

FB1, FB2 pins =

VREF pin,

COMP1, COMP2 pins =

1 V

8.4 12.0 16.8mA

Output clamp

voltage VILIM 4, 10 FB1, FB2 pins = 0 V,

ILIM1, ILIM2 pins = 1.5 V 1.35 1.50 1.65 V

ILIM pin

input current IILIM 5, 9 FB1, FB2 pins = 0 V,

ILIM1, ILIM2 pins = 1.5 V − 10 + 1 μA

Over-voltage

Protection

Circuit Block

[OVP Comp.]

Over-voltage

detecting

voltage VOVP 3, 11 FB1, FB2 pins 0.776 0.805 0.835 V

Over-voltage

detection time tOVP 3, 11 ⎯49 70 91 μs

Under-voltage

Protection

Circuit Block

[UVP Comp.]

Under-voltage

detecting

voltage VUVP 3, 11 FB1, FB2 pins 0.450 0.490 0.531 V

Under-voltage

detection time tUVP 3, 11 ⎯⎯

512/

fOSC ⎯s

Over-tempera-

ture Protection

Circuit Block

[OTP]

Detection

temperature

TOTPH ⎯Junction temperature ⎯ + 160* ⎯ °C

TOTPL ⎯Junction temperature ⎯ + 135* ⎯ °C

PFM Control

Circuit Block

(MODE)

Synchronous

rectification stop

voltage VTHLX 22, 16 LX1, LX2 pins ⎯0* ⎯mV

PFM/PWM

mode condition VPFM 13 MODE pin 0 ⎯1.4 V

Fixed PWM

mode

condition VPWM 13 MODE pin 2.2 ⎯VVREF V

MODE pin input

current IMODE 13 MODE pin = 0 V − 10 + 1 μA

MB39A136

DS04-27262-4E 9

(Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0 A)

(Continued)

Parameter Symbol Pin

No. Conditions Value Unit

Min Typ Max

Output Block

[DRV]

High-side

output

on-resistance

RON_MH 23, 15 DRVH1, DRVH2 pins =

− 100 mA ⎯47Ω

RON_ML 23, 15 DRVH1, DRVH2 pins =

100 mA ⎯1.0 3.5 Ω

Low-side

output

on-resistance

RON_SH 21, 17 DRVL1, DRVL2 pins =

− 100 mA ⎯47Ω

RON_SL 21, 17 DRVL1, DRVL2 pins =

100 mA ⎯0.75 1.70 Ω

Output source

current ISOURCE 23, 15,

21, 17

LX1, LX2 pins = 0 V,

CB1, CB2 pins = 5 V

DRVH1, DRVH2 pins,

DRVL1, DRVL2 pins =

2.5 V

Duty ≤ 5%

⎯ − 0.5* ⎯A

Output sink

current ISINK

23, 15

LX1, LX2 pins = 0 V,

CB1, CB2 pins = 5 V

DRVH1, DRVH2 pins =

2.5 V

Duty ≤ 5%

⎯0.9* ⎯A

21, 17

LX1, LX2 pins = 0 V,

CB1, CB2 pins = 5 V

DRVL1, DRVL2 pins =

2.5 V

Duty ≤ 5%

⎯1.2* ⎯A

Minimum on

time tON 23, 15 COMP1, COMP2 pins =

1 V ⎯250* ⎯ns

Maximum

on-duty DMAX 23, 15 FB1, FB2 pins = 0 V 75 80⎯%

Dead time tD23, 21,

15, 17 LX1, LX2 pins = 0 V,

CB1, CB2 pins = 5 V ⎯60 ⎯ns

Level

Converter

Block

[LVCNV]

Maximum

current sense

voltage VRANGE 22, 16 VCC pin − LX1, LX2 pins ⎯220* ⎯mV

Voltage

conversion

gain ALV 22, 16 ⎯5.4 6.88.2 V/V

Offset voltage

at voltage

conversion VIO 22, 16 ⎯⎯300 ⎯mV

Slope

compensation

inclination SLOPE 22, 16 ⎯⎯2* ⎯V/V

LX pin

input current ILX 22, 16 LX1, LX2 pins = VCC pin 320 420 600 μA

MB39A136

10 DS04-27262-4E

(Continued) (Ta = + 25 °C, VCC pin = 15 V, CTL pin = 5 V, VREF pin = 0 A, VB pin = 0 A)

* : This value is not be specified. This should be used as a reference to support designing the circuits.

Parameter Symbol Pin

No. Conditions Value Unit

Min Typ Max

Control Block

[CTL1, CTL2]

ON condition VON 1, 8CTL1, CTL2 pins 2 ⎯25 V

OFF condition VOFF 1, 8CTL1, CTL2 pins 0 ⎯0.8V

Hysteresis

width VH1, 8CTL1, CTL2 pins ⎯0.4* ⎯V

Input current ICTLH 1, 8CTL1, CTL2 pins = 5 V ⎯25 40 μA

ICTLL 1, 8CTL1, CTL2 pins = 0 V ⎯01μA

General

Standby

current ICCS 20 CTL1, CTL2 pins = 0 V ⎯010μA

Power-supply

current ICC 20 LX1, LX2 pins = 0 V,

FB1, FB2 pins = 1.0 V,

MODE pin = VREF pin ⎯3.3 4.7 mA

MB39A136

DS04-27262-4E 11

■TYPICAL CHARACTERISTICS

• Typical data

(Continued)

Power dissipation

Power dissipation vs. Operating ambient temperature

Power dissipation PD (mW)

Operating ambient temperature Ta ( °C)

200

400

600

800

1000

1200

1400

1600

1800

2000

−50 −25 0 +25 +50 +75 +100 +125

1644

VREF bias voltage vs.

Operating ambient temperature Error Amp threshold voltage vs.

Operating ambient temperature

VREF bias voltage VVREF (V)

Error Amp threshold voltage EVTH (V)

Operating ambient temperature Ta ( °C) Operating ambient temperature Ta ( °C)

3.24

3.26

3.28

3.3

3.32

3.34

3.36

-40 -20 0 +20 +40 +60 +80 +100

VCC = 15 V

fosc = 500 kHz

-40 -20 0 +20 +40 +60 +80 +100

0.69

0.695

0.7

0.705

0.71

CH1

CH2

VCC = 15 V

fosc = 500 kHz

MB39A136

12 DS04-27262-4E

(Continued)

Oscillation frequency vs.

Operating ambient temperature Dead time vs.

Operating ambient temperature

Oscillation frequency fOSC (kHz)

Dead time tD (ns)

Operating ambient temperature Ta ( °C) Operating ambient temperature Ta( °C)

tD1 : period from DRVL off to DRVH on

tD2 : period from DRVH off to DRVL on

Oscillation frequency vs. Timing resistor value VB bias voltage vs. VB bias output current

Oscillation frequency fOSC (kHz)

VB bias voltage VVB (V)

Timing resistor value RRT (kΩ) VB bias output current IVB (A)

Maximum duty cycle vs.

Power supply voltage Maximum duty cycle vs.

Operating ambient temperature

Maximum duty cycle DMAX (%)

Power supply voltage VVCC (V) Operating ambient temperature Ta ( °C)

-40 -20 0 +20 +40 +60 +80 +100

475

480

485

490

495

500

505 VCC = 15 V

-40 -20 0 +20 +40 +60 +80 +100

VCC = 15 V

fosc = 500 kHz tD2

tD1

VCC = 15 V

Ta = + 25°C

1000

100 10 100 1000

fosc = 500 kHz

Ta = + 25°C

-0.025 -0.02

VCC = 6 V

VCC = 5 V

VCC = 4.5 V

-0.01-0.015 -0.005 0

5.5

4.5

3.5

2.5

fosc = 500 kHz

Ta = + 25°C

CH2

CH1

75 0102030 -40 -20 0 +20 +40 +60 +80 +100

VCC = 15 V

fosc = 500 kHz

CH2

CH1

MB39A136

DS04-27262-4E 13

■FUNCTION DESCRIPTION

1. Current Mode

It uses the current wa v ef orm from the switching (Q1) as a control wa v ef orm to control the output voltage , as

described below:

1 : The clock (CK) from the internal clock generator (OSC) sets RS-FF and turns on the high-side FET.

2 : Turning on the high-side FET causes the inductor current (IL) rise. Generate Vs that converts this current

into the voltage.

3 : The current comparator (I Comp.) compares this Vs with the output (COMP) from the error amplifier

(Error Amp) that is negative-feedback from the output voltage (Vo).

4 : When I Comp. detects that Vs exceeds COMP, it resets RS-FF and turns off high-side FET.

5 : The clock (CK) from the clock generator (OSC) turns on the high-side FET again.

Thus, switching is repeated.

Operate so that the FB electrical potential ma y become INTREF electrical potential, and stabiliz e the output

voltage as a feedback control.

INTREF

VIN

IL VO

COMP RS-FF

DRVH

DRVL

OSC

Drive

Logic

SQCurrent

Sense

−

COMP

off

OSC(CK)

DRVH

MB39A136

14 DS04-27262-4E

(1) Reference Voltage Block (REF)

The reference voltage circuit (REF) generates a temperature-compensated reference voltage (3.3 [V] Typ)

using the voltage supplied from the VCC pin. The voltage is used as the reference voltage for the IC's internal

circuit. The reference voltage can be used to supply a load current of up to 100 μA to an exter nal device

through the VREF pin.

(2) Bias Voltage Block (VB Reg.)

Bias Voltage Bloc k (VB Reg.) generates the reference voltage used f or IC’ s internal circuit, using the v oltage

supplied from the VCC pin. The ref erence voltage is a temper ature-compensated stable v oltage (5 [V] Typ)

to supply a current of up to 100 mA through the VB pin.

(3) Under Voltage Lockout Protection Circuit Block (UVLO)

The circuit protects against IC malfunction and system destruction/deter ioration in a transitional state or a

momentary drop when a bias voltage (VB) or an internal reference voltage (VREF) starts. It detects a voltage

drop at the VB pin or the VREF pin and stops IC operation. When v oltages at the VB pin and the VREF pin

exceed the threshold voltage of the under voltage lockout protection circuit, the system is restored.

(4) Soft-start/Soft-stop Block (Soft-Start, Soft-Stop)

Soft-start

It protects a rush current or an output voltage (VOx) from overshooting at the output star t. Since the lamp

voltage generated by charging the capacitor connecting to the CSx pin is used for the reference voltage of

the error amplifier (Error Amp), it can set the soft-start time independent of a load of the output (V Ox). When

the IC starts with “H” le v el of the CTLx pin, the capacitor at the CSx pin (CS) starts to be charged at 5.5 μA.

The output voltage (VOx) during the soft-start period rises in proportion to the voltage at the CSx pin generated

by charging the capacitor at the CSx pin.

During the soft-start with 0.8 V > voltage at CS1 and CS2 pins, operations are as follows:

• Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)

• Over-voltage protection function and under-voltage protection function are invalid.

Soft-stop

It discharges electrical charges stored in a smoothing capacitor at output stop. Setting the CTLx pin to “L”

level starts the soft-stop function independent of a load of output (Vox). Since the capacitor connecting to

the CSx pin star ts to discharge through the IC-built-in soft-stop discharging resistance (70 [kΩ] Typ) when

the CTLx pin sets at “L” level enters its lamp voltage into the error amplifier (Error Amp), the soft-stop time

can be set independent of a load of output (VOx). When discharging causes the voltage at the CSx pin to

drop below 100 mV (Typ), the IC shuts down and changes to the stand-by state. In addition, the soft-stop

function operates after the under-voltage protection circuit block (UVP Comp.) is latched or after the over-

temperature protection circuit block (OTP) detects over-temperature.

During the soft-stop with, 0.8 V > voltage at CS1 and CS2 pins, operations are as follows:

• Fixed PWM operation only (fixed PWM even if MODE pin is set to “L”)

• Over-voltage protection function and under-voltage protection function are invalid.

(5) Clock Generator Block (OSC)

The clock generator has the built-in oscillation frequency setting capacitor and generates a clock that

180°phase shifted from each channel by connecting the oscillation frequency setting resistor to the RT pin

(Symmetrical-Phase method).

MB39A136

DS04-27262-4E 15

(6-1) Error Amp Block (Error Amp1, Error Amp2)

The error amplifiers (Error Amp1 and Error Amp2) detect the output voltage from the DC/DC converter and

output to the current comparators (I Comp.1 and I Comp.2). The output voltage setting resistor exter nally

connected to FB1 and FB2 pins allows an arbitrary output voltage to be set.

In addition, since an external resistor and an external capacitor serially connected between COMP1 and

FB1 pins and between COMP2 and FB2 pins allow an arbitrary loop gain to be set, it is possible for the

system to compensate a phase stably.

(6-2) Over Current Detection (Protection) Block (ILIM)

It is the current detection circuit to restrict an output current (IOX). The over current detection block (ILIM)

compares an output waveform of the level converter of each channel (see “(12) Level Converter Block

(LVCNV)”) with the ILIMx pin voltage in ever y cycle. As a load resistance (ROX) drops, a load current (IOX)

increases. Therefore, the output waveform of the level converter exceeds the ILIM pin voltage of each channel.

At this time, the output current can be restricted by turning off FET on the high-side and suppressing a peak

value of the inductor current.

As a result, the output voltage (VOX) should drop.

Fur thermore, if the output voltage drops and the electrical potential at the FBx pin drops below 0.3 V, the

oscillation frequency (fOSC) drops to 1/8.

(7) Over-voltage Protection Circuit Block (OVP Comp.)

The circuit protects a device connecting to the output when the output voltage (VOx) rises.

It compares 1.15 times (Typ) of the internal reference v oltage (INTREF) (0.7 V) that is non-inv erting-entered

into the error amplifier with the feedback voltage that is inver ting-entered into the error amplifier and if it

detects the state where the latter is higher than the former by 50 μs (Typ). It stops the voltage output by

setting the RS latch, setting the DRVHx pin to “L” level, setting the DRVLx pin to “H” level, tur ning off the

high-side FETs, and turning on the low-side FETs.

The conditions below cancel the protection function:

• Setting CTL1 and CTL2 to “L”.

• Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2).

(8) Under-voltage Protection Circuit Block (UVP Comp.)

It protects a device connecting to the output by stopping the output when the output voltage (VOX) drops.

It compares 0.7 times (Typ) of the internal reference voltage (INTREF) (0.7 V) that is non-inve rting-entered

into the error amplifier with the feedback voltage that is inver ting-entered into the error amplifier and if it

detects the state where the latter is lower than the f ormer by 512/f osc [s](Typ), it stops the voltage output f or

both channels by setting the RS latch.

The conditions below cancel the protection function:

• Setting CTL1 and CTL2 to “L”.

• Setting the power supply voltage below the UVLO threshold voltage (VTHL1 and VTHL2).

(9) Over temperature Protection Circuit Block (OTP)

The circuit protects an IC from heat-destruction. If the temperature at the joint par t reaches +160 °C, the

circuit stops the voltage output for both channels by discharging the capacitor connecting to the CSx pin

through the soft-stop discharging resistance (70 [kΩ] Typ) in the IC.

In addition, if the temperature at the joint par t drops to +135 °C, the output restarts again through the soft-

start function.

Make sure to design the DC/DC po wer supply system so that the ov er temperature protection does not start

frequently.

MB39A136

16 DS04-27262-4E

(10) PFM Control Circuit Block (MODE)

It sets the control mode of the IC and makes control at automatic PFM/PWM switching.

Automatic PFM/PWM switching mode operation

It compares the LX1 pin and the LX2 pin voltages with GND electrical potential at Di Comp. In the comparison,

the negativ e voltage at the LX pin causes the lo w-side FET to set on, positiv e v oltage causes it to set off (Di

Comp. method) . As a result, the method restricts the back flow of the inductor current at a light load and

makes the switching of the inductor current discontinuous (DCM) . Such an operation allows the oscillation

frequency to drop, resulting in high efficiency at a light load.

(11) Output Block (DRV)

The output circuit is configured in CMOS type for both of the high-side and the low-side, allowing the external

N-ch MOS FET to drive.

(12) Level Converter Block (LVCNV)

The circuit detects and converts the current when the high-side FET turns on. It converts the voltage waveform

between drain side (VCC pin voltage) and the source side (LX1 and LX2 pin v oltage) on the high-side FET

into the voltage waveform for GND reference.

Note: x : Each channel number

(13) Control Block (CTL1, CTL2)

The circuit controls on/off of the output from the IC.

Control function table

MODE pin connection Control mode Features

“L” (GND) Automatic PFM/PWM

switching Highly-efficient at light load

“H” (VREF) Fixed PWM

Stable oscillation frequency

Stable switching ripple voltage

Excellent in rapid load change characteristic at

heavy load to light load

CTL1 CTL2 DC/DC converter

(VO1) DC/DC con verter

(VO2) Remarks

L L OFF OFF Standby

H L ON OFF ⎯

LHOFFON⎯

H H ON ON ⎯

MB39A136

DS04-27262-4E 17

■PROTECTION FUNCTION TABLE

The following table shows the state of each pin when each protection function operates.

Note: x is the each channel number

Protection Function Detection

condition

Output of each pin after detection DC/DC output

dropping opera-

tion

VREF VB DRVHx DRVLx

Under Voltage Lock Out

Protection

(UVLO)

VB < 3.6 V

VREF < 2.7 V < 2.7 V < 3.6 V L L Self-discharge by

load

Under Voltage Protection

(UVP) FBx < 0.49 V 3.3 V 5 V L L Electrical discharge

by soft-stop func-

tion

Over Voltage Protection

(OVP) FBx > 0.805 V 3.3 V 5 V L H 0 V clamping

Over Current Protection

(ILIM) COMPx > ILIMx 3.3 V 5V switching switching

The output voltage

is dropping to keep

constant output cur-

rent.

Over Temperature

Protection

(OTP) Tj > + 160 °C 3.3 V 5 V L L Electrical discharge

by soft-stop func-

tion

CONTROL

(CTL) CTLx : H→L

(CSx > 0.1 V) 3.3 V 5 V L L

MB39A136

18DS04-27262-4E

■I/O PIN EQUIVALENT CIRCUIT DIAGRAM

(Continued)

VCC

GND

VREF

GND

VCC

GND

CTL1,CTL2

VREF

GND

CS1,CS2

VREF

GND

FB1,FB2

VREF

GND

COMP1,

COMP2

VB pin CS1, CS2 pins

VREF pin CTL1, CTL2 pins

FB1, FB2 pins COMP1, COMP2 pins

ESD protection element

MB39A136

DS04-27262-4E 19

(Continued)

DRVL1,DRVL2

VREF

GND

VREF

GND

LX1,LX2

CB1,CB2

DRVH1,

DRVH2

GND

ILIM1,ILIM2

VREF

GND

MODE

VREF

GND

ILIM1,ILIM2

VREF

GND

VREF

GND

LX1,LX2

CB1,CB2

DRVH1,

DRVH2

MODE pin CB1, CB2, DRVH1, DRVH2, LX1, LX2 pins

ILM1, ILM2 pins RT pin

DRVL1, DRVL2 pins

MB39A136

20 DS04-27262-4E

■EXAMPLE APPLICATION CIRCUIT

VCC

(4.5 V to 25 V) MODE

VREF R21

C13

FB1

COMP1

CS1

613

R23

R8-1

R8-2

MB39A136

<CH1>

ILIM1

R11

R12

CS2

COMP2

FB2

<CH2>

ILIM2

C11 R25

R14-1

R14-2

R15

R17

R18

718

GNDVREF

C15

CB2

DRVH2

DRVL2

LX2

CTL1

CTL2

D2 Q2 L2

Q2 C4-1

C4-2

C4-3

C3-1

C3-2

CB1

DRVH1

DRVL1

LX1

19 VB

D2 Q1 L1

Q1 C2-1

C2-2

C2-3

C14

MB39A136

DS04-27262-4E 21

■PARTS LIST

(Continued)

Compo-

nent Item Specification Vendor Package Parts Name Remark

Q1 N-ch FET VDS = 30 V,

ID = 8 A,

Ron = 21 mΩRENESAS SO-8μPA2755 Dual type

(2 elements)

Q2 N-ch FET VDS = 30 V,

ID = 8 A,

Ron = 21 mΩRENESAS SO-8μPA2755 Dual type

(2 elements)

D2 Diode VF = 0.35 V

at IF = 0.2 A ON Semi SOT-323 BAT54AWT1 Dual type

L1 Inductor 1.5 μH

(6.2 mΩ, 8.9 A) TDK ⎯VLF10040T-1R5N

L2 Inductor 3.3 μH

(9.7 mΩ, 6.9 A) TDK ⎯VLF10045T-3R3N

C1 Ceramic capacitor 22 μF (25 V) TDK 3225 C3225JC1E226M

C2-1

C2-2

C2-3

Ceramic capacitor

22 μF (10 V)

TDK

3216

C3216JB1A226M

3 capacitors

in parallel

C3-1

C3-2 Ceramic capacitor

Ceramic capacitor 22 μF (25 V)

22 μF (25 V) TDK

TDK 3225

3225 C3225JC1E226M

C3225JC1E226M 2 capacitors

in parallel

C4-1

C4-2

C4-3

Ceramic capacitor

22 μF (10 V)

TDK

3216

C3216JB1A226M

3 capacitors

in parallel

C5 Ceramic capacitor 0.1 μF (50 V) TDK 1608C1608JB1H104K

C6 Ceramic capacitor 0.1 μF (50 V) TDK 1608C1608JB1H104K

C7 Ceramic capacitor 0.022 μF (50 V) TDK 1608C1608JB1H223K

C8Ceramic capacitor 0.022 μF (50 V) TDK 1608C1608JB1H223K

C9 Ceramic capacitor 820 pF (50 V) TDK 1608C1608CH1H821J

C11 Ceramic capacitor 1000 pF (50 V) TDK 1608C1608CH1H102J

C13 Ceramic capacitor 0.01 μF (50 V) TDK 1608C1608JB1H103K

C14 Ceramic capacitor 2.2 μF (16 V) TDK 1608C1608JB1C225K

C15 Ceramic capacitor 0.1 μF (50 V) TDK 1608C1608JB1H104K

R8-1

R8-2 Resistor 1.6 kΩ

9.1 kΩSSM

SSM 1608

1608RR0816P162D

RR0816P912D 2 capacitors

in series

R9 Resistor 15 kΩSSM 1608RR0816P153D

R11 Resistor 56 kΩSSM 1608RR0816P563D

R12 Resistor 47 kΩSSM 1608RR0816P473D

R14-1

R14-2 Resistor 1.8 kΩ

39 kΩSSM

SSM 1608

1608RR0816P182D

RR0816P393D 2 capacitors

in series

R15 Resistor 11 kΩSSM 1608RR0816P113D

MB39A136

22 DS04-27262-4E

(Continued)

RENESAS : Renesas Electronics Corporation

ON Semi : ON Semiconductor

TDK : TDK Corporation

SSM : SUSUMU Co.,Ltd.

Compo-

nent Item Specification Vendor Package Parts Name Remark

R17 Resistor 56 kΩSSM 1608RR0816P563D

R18Resistor 56 kΩSSM 1608RR0816P563D

R21 Resistor 82 kΩSSM 1608RR0816P823D

R23 Resistor 22 kΩSSM 1608RR0816P223D

R25 Resistor 56 kΩSSM 1608RR0816P563D

MB39A136

DS04-27262-4E 23

■APPLICATION NOTE

Setting method for PFM/PWM and fixed PWM modes

For the setting method for each mode, see“■ FUNCTION DESCRIPTION (10) PFM Control Circuit Block

(MODE)”.

Cautions at PFM/PWM mode

If a load current drops rapidly because of rapid load change and others, it tends to take a lot of time to restore

overshooting of an output voltage.

As a result, the over-voltage protection may operate.

In this case, solution are possible by the addition of the load resistance of value to be able to restore the

output voltage in the over-voltage detection time.

Setting method of output voltage

Set it by adjusting the output volta ge setting zero-power resistance ratio.

Make sure that the setting does not exceed the maximum on-duty.

Calculate the on-duty by the following formula:

VO = R1 + R2 × 0.7

VO : Output setting voltage [V]

R1, R2 : Output setting resistor value [Ω]

DMAX_Min = VO + RON_Sync × IOMAX

VIN − RON_Main × IOMAX + RON_Sync × IOMAX

DMAX_Min : Minimum value of the maximum on-duty cycle

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

RON_Main : High-side FET ON resistance [Ω]

RON_Sync : Low-side FET ON resistance [Ω]

IOMAX : Maximum load current[A]

FB1

FB2

MB39A136

24 DS04-27262-4E

Oscillation frequency setting method

Set it by adjusting the RT pin resistor value.

The oscillation frequency must set for on-time (tON) to become 300ns or more.

Calculate the on-time by the following formula.

fOSC = 1.09

RRT × 40 × 10 − 12 + 300 × 10 − 9

RRT : RT resistor value [Ω]

fOSC : Oscillation frequency [Hz]

tON = VO

VIN × fOSC

tON : On-time [s]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

MB39A136

DS04-27262-4E 25

Setting method of soft-start time

Calculate the soft-start time by the following formula.

tS = 1.4 × 105 × CCS

Calculate delay time until the soft-start beginning by the following formula.

td1 = 30 × CVB + 290 × CVREF + 1.455 × 104 × CCS

Calculate dela y time for starting while one channel has already started (UVLO released : VB, VREF output

before) by the following formula.

td2 = 1.455 × 104 × CCS

Calculate the discharge time at the soft-stop by the following formula.

tdis = 1.44 × 105 × CCS

In addition, calculate the delay time to the discharge starting by the following formula.

td3 = 7.87 × 104 × CCS

ts : Soft-start time[s] (Time to becoming output 100%)

CCS : CS pin capacitor value [F]

td1 : Delay time including VB voltage and VREF voltage starts [s]

CCS : CS pin capacitor value [F]

CVB : VB pin capacitor value [F]

CVREF : VREF pin capacitor value [F] (0.1 [μF] Typ)

td2 : Delay time for starting while one channel has already started [s]

CCS : CS pin capacitor value [F]

tdis : Discharge time [s]

CCS : CS pin capacitor value [F]

td3 : Delay time until discharge start [s]

CCS : CS pin capacitor value [F]

CTL1

CTL2

dis

MB39A136

26 DS04-27262-4E

• Simultaneous operation of plural channels

Soft-star t/soft-stop operation according to the same timing as two channels can be achieved by even con-

necting it as shown in the figure below at the power supply on/off.

<Connection example 1> When you adjust the soft-start time

Make the CS capacitor common. Connect CTL1 and CTL2.

Note: In this case, the soft-start time (ts), the discharge time (tdis), and the delay time (td1, td2, td3) decrease

in the half value of compared with when CS capacitor is connected to each channel.

CS1

CTL1

MB39A136

CS2

CTL

< DC/DC 2 >

< DC/DC 1 >

1.8 V

1.2 V

CTL2

CTL

DC/DC 2 : Vo = 1.8 V setting

DC/DC 1 : Vo = 1.2 V setting

capacitor

MB39A136

DS04-27262-4E 27

Setting method of over current detection value

It is possible to set o ver-current detection value (ILIM) by adjusting the o ver-current detection setting resistor

value ratio.

Calculate the over current detection setting resistor v alue by the following formula.

200 × 103 ≥ R1 + R2 ≥ 30 × 103

* Since the over current detection value depends on the on-resistance of FET, the over current detection

setting resistor v alue r atio should be adjusted in consideration of the temperature char acteristics of the on-

resistance. When the temperature at the FET joint part rises by + 100 °C, the on-resistance of FET increases

to about 1.5 times.

* If the over current detection function is not used, connect the ILIM pin (ILIM1 and ILIM2) to the VREF pin.

3.3 × R2 − 0.3

ILIM = R1 + R2 + VIN − VO × (200 × 10 − 9

− VO)

6.8 × RON L2 × fOSC × VIN

ILIM : Over current detection value [A]

R1, R2 : ILIM setting resistor value [Ω]*

L : Inductor value [H]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

RON : High-side FET ON resistance [Ω]

VREF

ILIM*

LIM

Inductor current

Time

Over-current

detection value

MB39A136

28DS04-27262-4E

Selection of smoothing inductor

The inductor v alue selects the v a lue that the ripple current peak-to-peak value becomes 50% or less of the

maximum load current as a rough standard. Calculate the inductor value in this case by the following formula.

An inductor ripple current value limited on the principle of operation is necessary for this device. However,

when it uses the high-side FET of the low Ron resistance, the switching r ipple voltage become small, and

the inductor ripple current value ma y become insufficient. This should be solved b y the oscillation frequency

or reducing the inductor value.

Select the one of the inductor value that meets a requirement listed below.

It is necessary to calculate the maximum current value that flows to the inductor to judge whether the electric

current that flows to the inductor is a rated v alue or less. Calculate the maximum current value of the inductor

by the following formula.

L ≥ VIN − VO × VO

LOR × IOMAX VIN × fOSC

L : Inductor value [H]

IOMAX : Maximum load current [A]

LOR : Ripple current peak-to-peak value of Maximum load current ratio (=0.5)

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

L ≤ VIN − VO × VO × RON

ΔVRON VIN × fOSC

L : Inductor value [H]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

ΔVRON : Ripple voltage [V] (20 mV or more is recommended)

RON : High-side FET ON resistance [Ω]

ILMAX ≥ IoMAX + ΔIL , ΔIL = VIN − VO × VO

2LVIN × fOSC

ILMAX : Maximum current value of inductor [A]

IoMAX : Maximum load current [A]

ΔIL : Ripple current peak-to-peak value of inductor [A]

L : Inductor value [H]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

ΔIL

MAX

Inductor current

MB39A136

DS04-27262-4E 29

Selection of SWFET

The switching ripple voltage generated between drain and sources on high-side FET is necessar y for this

device operation. Select the one of the SWFET of on-resistance that satisfies the following formula.

Select FET ratings with a margin enough for the input voltage and the load current. Ratings with the over-

current detection setting value or more are recommended.

Calculate a necessary rated value of high-side FET and low-side FET by the following formula.

VDS > VIN

VGS > VB

Moreover, it is necessary to calculate the loss of SWFET to judge whether a permissible loss of SWFET is

a rated value or less. Calculate the loss on high-side FET by the following formula.

PMainFET = PRON_Main + PSW_Main

RON_Main ≥ ΔVRON_Main , RON_Main ≤ VRONMAX

ΔIL ILIM + ΔIL

RON_Main : High-side FET ON resistance [Ω]

ΔIL : Ripple current peak-to-peak value of inductor [A]

ΔVRON_Main : High-side FET ripple voltage [V] (20mV or more is recommended)

ILIM : Over current detection value [A]

VRONMAX : Maximum current sense voltage [V] (240mV or less is recommended)

ID > IoMAX + ΔIL

ID : Rated drain current [A]

IoMAX : Maximum load current [A]

ΔIL : Ripple current peak-to-peak value of inductor [A]

VDS : Rated voltage between drain and source [V]

VIN : Power supply voltage of switching system [V]

VGS : Rated voltage between gate and source [V]

VB : VB voltage [V]

PMainFET : High-side FET loss [W]

PRON_Main : High-side FET conduction loss [W]

PSW_Main : High-side FET SW loss [W]

MB39A136

30 DS04-27262-4E

High-side FET conduction loss

High-side FET SW loss

Calculate the Ibtm, the Itop, the tr and the tf simply by the following formula.

PRON_Main = IoMAX2 × VO × RON_Main

VIN

PRON_Main : High-side FET conduction loss [W]

IOMAX : Maximum load current [A]

VIN : Power supply voltage of switching system [V]

VO : Output voltage [V]

RON_Main : High-side FET ON resistance [Ω]

PSW_Main = VIN × fOSC × (Ibtm × tr + Itop × tf)

PSW_Main : High-side FET SW loss [W]

VIN : Power supply voltage of switching system [V]

fOSC : Oscillation frequency [Hz]

Ibtm : Ripple current bottom value of inductor [A]

Itop : Ripple current top value of inductor [A]

tr : Turn-on time on high-side FET [s]

tf : Turn-off time on high-side FET[s]

Ibtm = IOMAX − ΔIL

Itop = IOMAX + ΔIL

tr = Qgd × 4 tf = Qgd × 1

5 − Vgs (on) Vgs (on)

IOMAX : Maximum load current [A]

ΔIL : Ripple current peak-to-peak value of inductor [A]

Qgd : Quantity of charge between gate and drain on high-side FET [C]

Vgs (on) : Voltage between gate and source in Qgd on high-side FET [V]

MB39A136

DS04-27262-4E 31

Calculate the loss on low-side FET by the following formula.

* : The transition v oltage of the v o ltage between dr ain and source on low-side FET is generally small, and the

switching loss is omitted here for the small one as it is possible to disregard it.

The gate drive power of SWFET is supplied by LDO in IC, therefore all SWFET allowable maximum total

charge (QgTotalMax) of 2ch is determined by the following formula.

Selection of fly-back diode

When the conversion efficiency is valued, the improved property of the conversion efficiency is possible by

the addition of the fly-back diode. Thought it is usually unnecessary. The effect is achieved in the condition

where the oscillation frequency is high or output voltage is lower. Select schottky barrier diode (SBD) that

the f orward current is as small as possib le . In this DC/DC control IC , the period for the electric current flows

to fly back diode is limited to synchronous rectification period (60 ns × 2) because of using the synchronous

rectification method. Therefore, select the one that the electric current of fly back diode doesn't exceed

ratings of forward current surge peak (IFSM).Calculate the forward current surge peak ratings of fly back

diode by the following formula.

Calculate ratings of the fly-back diode by the following formula:

VR_Fly > VIN

PSyncFET = PRon_Sync* = IoMAX2 × (1 − VO) × Ron_Sync

VIN

PSyncFET : Low-side FET loss [W]

PRon_Sync : Low-side FET conduction loss [W]

IOMAX : Maximum load current [A]

VIN : Power supply voltage of switching system [V]

VO : Output voltage [V]

Ron_Sync : Low-side FET on-resistance [Ω]

QgTotalMax ≤ 0.095

fOSC

QgTotalMax : SWFET allowable maximum total charge [C]

fOSC : Oscillation frequency [Hz]

IFSM ≥ IoMAX + ΔIL

IFSM : Forward current surge peak ratings of fly back diode [A]

IoMAX : Maximum load current [A]

ΔIL : Ripple current peak-to-peak value of inductor [A]

VR_Fly : Reverse voltage of fly-back diode direct current [V]

VIN : Power supply voltage of switching system [V]

MB39A136

32 DS04-27262-4E

Selection of output capacitor

This device suppor ts a small ceramic capacitor of the ESR. The ceramic capacitor that is low ESR is an

ideal to reduce the ripple voltage compared with other capacitor . Use the tantalum capacitor and the polymer

capacitor of the low ESR when a mass capacitor is needed as the ceramic capacitor can not support. To

the output voltage, the ripple voltage by the switching operation of DC/DC is generated. Discuss the lower

bound of output capacitor value according to an allo wab le ripple voltage . Calculate the output ripple voltage

from the following formula.

Notes: • The ripple voltage can be reduced b y raising the oscillation frequency and the inductor v alue besides

capacitor.

• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias char-

acteristic, etc. The effective capacitor value might become extremely small depending on the condition.

Note the effective capacitor value in the condition.

Calculate ratings of the output capacitor by the fo llowing formula:

VCO > VO

Note: Select the capacitor rating with withstand voltage allowing a margin enough for the output voltage.

In addition, use the allowable ripple current with an enough margin, if it has a rating.

Calculate an allowable ripple current of the output capacitor by the following formula:

ΔVO = ( 1 + ESR) × ΔIL

2π × fOSC × CO

ΔVO : Switching ripple voltage [V]

ESR : Series resistance component of output capacitor [Ω]

ΔIL : Ripple current peak-to-peak value of inductor [A]

CO : Output capacitor value [F]

fOSC : Oscillation frequency [Hz]

VCO : Withstand voltage of the output capacitor [V]

VO : Output voltage [V]

Irms ≥ ΔIL

2√3

Irms : Allowable ripple current (effective value) [A]

ΔIL : Ripple current peak-to-peak value of inductor [A]

MB39A136

DS04-27262-4E 33

Selection of input capacitor

Select the input capacitor whose ESR is as small as possible. The ceramic capacitor is an ideal. Use the

tantalum capacitor and the polymer capacitor of the low ESR when a mass capacitor is needed as the

ceramic capacitor can not support. To the power supply voltage, the ripple voltage by the switching operation

of DC/DC is generated. Discuss the low er bound of input capacitor according to an allow able ripple vo ltage.

Calculate the ripple voltage of the power supply from the following formula.

Notes: • The ripple voltage of the power supply can be reduced by raising the oscillation frequency besides

capacitor.

• Capacitor has frequency characteristic, the temperature characteristic, and the electrode bias char-

acteristic, etc. The effective capacitor value might become extremely small depending on the condition.

Note the effective capacitor value in the condition.

Calculate ratings of the input capacitor by the following formula:

VCIN > VIN

Note: Select the capacitor rating with withstand voltage with margin enough for the input voltage.

In addition, use the allowable ripple current with an enough margin, if it has a rating.

Calculate an allowable ripple current by the following formula:

ΔVIN = IOMAX × VO + ESR × (IOMAX + ΔIL )

CIN VIN × fOSC 2

ΔVIN : Switching system power supply ripple voltage peak-to-peak value [V]

IOMAX : Maximum load current value [A]

CIN : Input capacitor value [F]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

ESR : Series resistance component of input capacitor [Ω]

ΔIL : Ripple current peak-to-peak value of inductor [A]

VCIN : Withstand voltage of the input capacitor [V]

VIN : Power supply voltage of switching system [V]

Irms ≥ IOMAX × √VO × (VIN − VO)

VIN

Irms : Allowable ripple current (effective value) [A]

IOMAX : Maximum load current value [A]

VIN : Power supply voltage of switching system [V]

VO : Output voltage [V]

MB39A136

34 DS04-27262-4E

Selection of boot strap diode

Select Schottky barrier diode (SBD), that forward current is as small as possible. The electric current that

drives the gate of high-side FET flows to SBD of the bootstrap circuit. Calculate the mean current by the

following formula. Select it so as not to exceed the electric current ratings.

ID ≥ Qg × fOSC

Calculate ratings of the boot strap diode by the following formula:

VR_BOOT > VIN

Selection of boot strap capacitor

To drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a

minimum v alue as a target is assumed the capacitor which can store electric charge 10 times that of the Qg

on high-side FET. And select the boot strap capacitor.

Calculate ratings of the boot strap capacitor by the following formula:

VCBOOT > VB

ID : Forward current [A]

Qg : Total quantity of charge of gate on high-side FET [C]

fOSC : Oscillation frequency [Hz]

VR_BOOT : Reverse voltage of boot strap diode direct current [V]

VIN : Power supply voltage of switching system [V]

CBOOT ≥ 10 × Qg

CBOOT : Boot strap capacitor [F]

Qg : Amount of gate charge on high-side FET [C]

VB : VB voltage [V]

VCBOOT : Withstand voltage of the boot strap capacitor [V]

VB : VB voltage [V]

MB39A136

DS04-27262-4E 35

Design of phase compensation circuit

Assume the phase compensation circuit of 1pole-1zero to be a standard in this device.

1pole-1zero phase compensation circuit

As f or crossov er frequency (fCO) that shows the band width of the control loop of DC/DC . The higher it is, the

more e xcellent the rapid response becomes, ho we v er , the possibility of causing the oscillation due to phase

margin shor tage increases. Though this crossover frequency (fCO) can be arbitrarily set, make 1/10 of the

oscillation frequencies (fosc) a standard, and set it to the upper limit. Moreover , set the phase margin at least

to 30 °C, and 45 °C or more if possible as a reference.

Set the constants of Rc and Cc of the phase compensation circuit using the following for mula as a target.

RC = (VIN − VO) ALVCNV × RON_Main × fCO × 2π × CO × VO × R1

VIN × fOSC × L × IOMAX

CC = CO × VO

RC × IOMAX

RC : Phase compensation resistor value [Ω]

CC : Phase compensation capacitor value [F]

VIN : Power supply voltage of switching system [V]

VO : Output setting voltage [V]

fOSC : Oscillation frequency [Hz]

IOMAX : Maximum load current value [A]

L : Inductor value [H]

CO : Output capacitor value [F]

RON_Main : High-side FET ON resistance[Ω]

R1 : Output setting resistor value [Ω]

ALVCNV : Level converter voltage gain [V/V]

On-duty ≤ 50%: ALVCNV = 6.8

On-duty > 50%: ALVCNV = 13.6

fCO : Cross-over frequency (arbitrary setting) [Hz]

INTREF

COMP

Rc Cc

Error

Amp

To I Comp.

MB39A136

36 DS04-27262-4E

VB pin capacitor

2.2 μF is assumed to be a standard, and when Qg of SWFET used is large, it is necessar y to adjust it. To

drive the gate of high-side FET, the bootstrap capacitor must have enough stored charge. Therefore, a

minimum value as a target is assumed the capacitor, which can store electr ic charge 100 times that of the

Qg of the SWFET. And select it.

Calculate ratings of the VB pin capacitor by the following formula:

VCVB > VB

CVB ≥ 100 × Qg

CVB : VB pin capacitor value [F]

Qg : Total amount of gate charge of 2 ch respectively: high-side FET and low-side FET

[C]

VB : VB voltage [V]

VCVB : Withstand voltage of the VB pin capacitor [V]

VB : VB voltage [V]

MB39A136

DS04-27262-4E 37

VB regulator

In the condition for which the potential difference between VCC and VB is insufficient, the decrease in the

voltage of VB happens because of power output on-resistance and load current (mean current of all e xternal

FET gate driving current and load current of inter nal IC) of the VB regulator. Stop the switching operation

when the voltage of VB decreases and it reaches threshold voltage (VTHL1) of the under voltage lockout

protection circuit. Therefore, set oscillation frequency or exter nal FET or I/O potential difference of the VB

regulator using the following formula as a target when you use this IC.

VCC ≥ VB (VTHL1) + (Qg × fOSC + ICC) × RVB

If the I/O potential difference is small, the problem can be solved by connecting the VB pin and the VCC pin.

The conditions of the input voltage range are as follows:

Note that if the I/O potential diff erence is not enough when used, use the actual machine to chec k carefully

the operations at the normal operation, start operation, and stop operation. In particular, care is needed

when the input voltage range over 6 V.

VCC : Power supply voltage [V] (VIN)

VB (VTHL1) : Threshold voltage of VB under-voltage lockout protection circuit [V]

(3.8 [V] Max )

Qg : Total amount of gate charge of 2 ch respectively: high-side FET and low-side FET

[C]

fOSC : Oscillation frequency [Hz]

ICC : Power supply current [A] (4.7 × 10−3[A] := Load current of VB (LDO) )

RVB : VB output on-resistance [Ω] (100 Ω (The reference value at VCC = 4.5 V) )

6.0 V

4.5 V25 V

(2)

(3)(1)

(1) For 4.5 V < VIN < 6.0 V

→ Connect VB pin to VCC.

(2) When the input voltage range steps over 6.0 V

→ Normal use (VCC to VB not connected)

(3) For 6.0 V ≤ VIN

→ Normal use (VCC to VB not connected)

VIN input voltage ranges:

MB39A136

38DS04-27262-4E

Power dissipation and the thermal design

As for this IC, considerations of the power dissipation and thermal design are not necessary in most cases

because of its high efficiency. However, they are necessary for the use at the conditions of a high power

supply voltage, a high oscillation frequency, high load, and the high temperature.

Calculate IC internal loss (PIC) by the following formula.

PIC = VCC × (ICC + Qg × fOSC)

Calculate junction temperature (Tj) by the following formula.

Tj = Ta + θja × PIC

Handling of the pins when using a single channel

Although this device is a 2-channel DC/DC conver ter control IC, it is also able to be used as a 1-channel

DC/DC converter by handling the pins of the unused channel as shown in the following diagram.

PIC : IC internal loss [W]

VCC : Power supply voltage (VIN) [V]

ICC : Power supply current [A] (4.7 [mA] Max)

Qg : All SWFET total quantity of charge for ch 2 [C] (Total with Vgs = 5 V)

fOSC : Oscillation frequency[Hz]

Tj : Junction temperature [ °C] (+150 [ °C] Max)

Ta : Ambient temperature [ °C]

θja : TSSOP-24 Package thermal resistance (76 °C/W)

PIC : IC internal loss [W]

FBx

CBx

CSx

LXx

ILIMx

CTLx

DRVHx

COMPx

DRVLx

Note: x is the unused channel number.

“Open”

MB39A136

DS04-27262-4E 39

Board layout

Consider the points listed below and do the layout design.

• Provide the ground plane as much as possible on the IC mounted face. Connect bypass capacitor con-

nected with the VCC and VB pins, and GND pin of the s witching system parts with s witching system GND

(PGND). Connect other GND connection pins with control system GND (AGND), and separate each GND ,

and try not to pass the hea vy current path through the control system GND (A GND) as m uch as possib le.

In that case, connect control system GND (AGND) and switching system GND (PGND) right under IC.

• Connect the s witching system parts as much as possible on the surf ace. A v oid the connection through the

through-hole as much as possible.

• As for GND pins of the switching system parts, provide the through hole at the proximal place, and connect

it with GND of internal layer.

• Pay the most attention to the loop composed of input capacitor (CIN), SWFET, and fly-back diode (SBD).

Consider making the current loop as small as possible.

• Place the boot strap capacitor (CBOOT1, CBOOT2) proximal to CBx and LXx pins of IC as much as possible.

• This device monitors the voltage between drain and source on high-side FET as voltage between VCC

and LX pins. Place the input capacitor (CIN) and the high-side FET of each CH proximally as much as

possible. Draw out the wiring to VCC pin from the proximal place to the input capacitor of CH1 and CH2.

As for the net of the LXx pin, draw it out from the proximal place to the source pin on high-side FET.

Moreover, a large electr ic current flows momentary in the net of the LXx pin. Wire the linewidth of about

0.8mm to be a standard, as short as possible.

• Large electric current flows momentar y in the net of DRVHx and DRVLx pins connected with the gate of

SWFET. Wire the linewidth of about 0.8mm to be a standard, as short as possible.

• By-pass capacitor (CVCC, CVREF, CVB) connected with VREF, VCC , and VB, and the resistor (RRT) connected

with the RT pin should be placed close to the pin as much as possible. Also connect the GND pin of the

by-pass capacitor with GND of internal layer in the proximal through-hole.

• Consider the net connected with RT, FBx, and the COMPx pins to keep away from a Switching system

parts as much as possible because it is sensitive to the noise . Moreover, place the output v oltage setting

resistor and the phase compensation circuit element connected with this net close to the IC as much as

possible, and try to make the net as shor t as possible. In addition, for the inter nal layer right under the

installing part, provide the control system GND (AGND) of fe w ripple and f ew spike noises, or prov ide the

ground plane of the power supply voltage as much as possible.

Switching system parts : Input capacitor (CIN), SWFET, Fly-back diode (SBD), Inductor (L),

Output capacitor (CO)

Note: x : Each channel number

GND

BOOT2

VCC

VREF

1pin C

BOOT1

SBD (option) SBD (option)

PGND

Vo1 Vo2

Layout example of IC Layout example of switching components

Through-hole

AGND and PGND are connected right under IC.

Surface Internal

layer

High-side FET

To the LX1 pin

Low-side FET Low-side

FET

High-side FET

To the VCC pin Through-hole

Output voltage

Vo1 feedback Output voltage

Vo2 feedback

To the LX2

MB39A136

40 DS04-27262-4E

■REFERENCE DATA

(Continued)

CH1 Conversion Efficiency CH2 Conversion Efficiency

Conversion Efficiency vs. Load Current Conversion Efficiency vs. Load Current

Conversion Efficiency η (%)

Conversion Efficiency η(%)

Load Current IO1(A) Load Current IO2 (A)

CH1 Load Regulation CH2 Load Regulation

Output Voltage vs. Load Current Output Voltage vs. Load Current

Output Voltage VO1 (V)

Output Voltage VO2(V)

Load Current IO1(A) Load Current IO2 (A)

0.01 0.1 1 10

100 CH1

= 12 V

1 = 1.2 V

fosc = 300 kHz

Ta = + 25°C

PFM/PWM

Fixed PWM

0.01 0.1 1 10

CH2

= 12 V

2 = 3.3 V

fosc = 300 kHz

Ta = + 25°C

PFM/PWM

100

Fixed PWM

012345

= 12 V

1 = 1.2 V

MODE = VREF

fosc = 300 kHz

Ta = + 25°C

1.10

1.12

1.14

1.16

1.18

1.20

1.22

1.24

1.26

1.28

1.30

012345

= 12 V

2 = 3.3 V

MODE = VREF

fosc = 300 kHz

Ta = + 25°C

3.00

3.10

3.20

3.30

3.40

3.50

3.60

MB39A136

DS04-27262-4E 41

(Continued)

VO1 : 0.5 V/div

CS1 : 2 V/div

LX1 : 10 V/div

IO1 : 10 A/div

500 μs/div

VO1: 1 V/div

1 ms/div

VO2: 1 V/div

CTL1, 2 : 5 V/div

VO1: 1 V/div

1 ms/div

VO2: 1 V/div

CTL1, 2 : 5 V/div

2 A

0 A

2 : 200 mV/div (3.3 V offset)

100 μs/div

2 : 1 A/div

CH1

Load Sudden Change Waveform CH2

Load Sudden Change Waveform

CTL Startup Waveform CTL Stop Waveform

VIN = 12 V, fOSC = 300 kHz, Ta = + 25 °C, Soft-start setting time = 3.0 ms

VO1 = 1.2 V, IO1 = 5 A (0.24 Ω) , VO2 = 3.3 V, IO2 = 5 A (0.66 Ω)

Normal operation → Over current protection → Under voltage protection operation waveform

Normal operation

VIN = 12 V, VO1 = 1.2 V

IO1 = 0←→2 A, fOSC = 300 kHz, Ta = + 25 °CVIN = 12 V, VO2 = 3.3 V

IO2 = 0←→2 A, fOSC = 300 kHz, Ta = + 25 °C

VIN = 12 V

VO1 = 1.2 V

fOSC = 300 kHz

Ta = + 25 °C

Over current

protection operation Under voltage

protection operation

2 A

0 A

VO1 : 200 mV/div (1.2 V offset)

100 μs/div

IO1 : 1 A/div

MB39A136

42 DS04-27262-4E

■USAGE PRECAUTION

1. Do not configure the IC over the maximum ratings.

If the IC is used over the maximum ratings, the LSI may be per manently damaged.

It is preferable for the device to be normally operated within the recommended usage conditions. Usage

outside of these conditions can have an adverse effect on the reliability of the LSI.

2. Use the device within the recommended operating conditions.

The recommended values guarantee the normal LSI operation under the recommended operating conditions.

The electrical ratings are guaranteed when the de vice is used within the recommended operating conditions

and under the conditions stated for each item.

3. Printed circuit board ground lines should be set up with consideration for common

impedance.

4. Take appropriate measures against static electricity.

• Containers for semiconductor materials should have anti-static protection or be made of conductive ma-

terial.

• After mounting, printed circuit boards should be stored and shipped in conductive bags or containers.

• Work platforms, tools, and instruments should be properly grounded.

• Working personnel should be grounded with resistance of 250 kΩ to 1 MΩ in ser ies between body and

ground.

5. Do not apply negative voltages.

The use of negative voltages below − 0.3 V may make the parasitic transistor activated, and can cause

malfunctions.

MB39A136

DS04-27262-4E 43

■ORDERING INFORMATION

■EV BOARD ORDERING INFORMATION

Part number Package Remarks

MB39A136PFT 24-pin plastic TSSOP

(FPT-24P-M09)

Part number EV board version No. Remarks

MB39A136EVB-01 MB39A136EVB-01 Rev2.0 TSSOP-24

MB39A136

44 DS04-27262-4E

■RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION

The LSI products of FUJITSU SEMICONDUCTOR with “E1” are compliant with RoHS Directive, and has

observ ed the standard of lead, cadmium, mercury, He xav alent chromium, polybrominated biphenyls (PBB),

and polybrominated diphenyl ethers (PBDE). A product whose par t number has trailing characters “E1” is

RoHS compliant.

■MARKING FORMAT (Lead Free version)

XXXX

39A136

XXX

INDEX

Lead Free version

MB39A136

DS04-27262-4E 45

■LABELING SAMPLE (Lead free version)

2006/03/01

ASSEMBLED IN JAPAN

QC PASS

(3N) 1MB123456P-789-GE1

1000

(3N)2 1561190005 107210

1,000

PCS

0605 - Z01A

1000

1/1

1561190005

MB123456P - 789 - GE1

Lead-free mark

JEITA logo JEDEC logo

The part number of a lead-free product has

the trailing characters “E1”. “ASSEMBLED IN CHINA” is printed on the label

of a product assembled in China.

MB39A136

46 DS04-27262-4E

■MB39A136PFT

RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL

[FUJITSU SEMICONDUCTOR Recommended Mounting Conditions]

[Mounting Conditions]

(1) IR (infrared reflow)

(2) Manual soldering (partial heating method)

Temperature at the tip of an soldering iron: 400 °C max

Time: Five seconds or below per pin

Item Condition

Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)

Mounting times 2 times

Storage period

Before opening Please use it within two years after

Manufacture.

From opening to the 2nd

reflow Less than 8 days

When the storage period after

opening was exceeded Pl ease process within 8 days

after baking (125 °C, 24h)

Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)

260°C

(e)

(d')

(d)

255°C

170 °C

190 °C

RT (b)

(a)

(c)

Note: Temperature : on the top of the package body

“H” level : 260 °C Max

(a) Temperature increase gradient : Average 1 °C/s to 4 °C/s

(b) Preliminary heating : Temperature 170 °C to 190 °C, 60 s to 180 s

(d) Peak temperature : Temperature 260 °C Max; 255 °C or more, 10 s or less

(d’) Main heating : Temperature 230 °C or more, 40 s or less

Temperature 225 °C or more, 60 s or less

Temperature 220 °C or more, 80 s or less

(e) Cooling : Natural cooling or forced cooling

Main heating

MB39A136

DS04-27262-4E 47

■PACKAGE DIMENSIONS

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

24-pin plastic TSSOP Lead pitch 0.50 mm

Package width

package length

4.40 mm × 6.50 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.20 mm MAX

Weight 0.08 g

24-pin plastic TSSOP

(FPT-24P-M09)

2007-2010 FUJITSU SEMICONDUCTOR LIMITED F24032S-c-2-5

6.50±0.10(.256±.004)

4.40±0.10 6.40±0.20

(.252±.008)

(.173±.004)

0.10±0.05

(Mounting height)

0.10(.004)

0.50(.020)

1 12

24 13

"A"

(Stand off)

0.145±0.045

(.0057±.0018)

0.13(.005)

Details of "A" part

0~8°

(.024±.006)

0.60±0.15

INDEX

(.004±.002)

BTM E-MARK

1.10 +0.10

+.004

–0.15

–.006.043

0.20 +0.07

+.003

–0.02

–.001.008

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) Pins width and pins thickness include plating thickness.

Note 2) Pins width do not include tie bar cutting remainder.

Note 3) #: These dimensions do not include resin protrusion.

MB39A136

48DS04-27262-4E

■MAJOR CHANGES IN THIS EDITION

A change on a page is indicated by a vertical line drawn on the left side of that page.

Page Section Change Results

9■ ELECTRICAL CHARACTERISTICS Revised the minimum value of “Maximum on-duty” in

“Output Block [DRV]”:

72 → 75

MB39A136
DS04-27262-4E 49
■CONTENTS
page
-DESCRIPTION  .................................................................................................................................................... 1
-FEATURES  .......................................................................................................................................................... 1
-APPLICATION  ..................................................................................................................................................... 1
-PIN ASSIGNMENT   ............................................................................................................................................. 2
-PIN DESCRIPTION   ............................................................................................................................................ 3
-BLOCK DIAGRAM  .............................................................................................................................................. 4
-ABSOLUTE MAXIMUM RATINGS  ................................................................................................................... 5
-RECOMMENDED OPERATING CONDITIONS   ............................................................................................ 6
-ELECTRICAL CHARACTERISTICS  ................................................................................................................ 7
-TYPICAL CHARACTERISTICS  ........................................................................................................................ 11
-FUNCTION DESCRIPTION   .............................................................................................................................. 13
-PROTECTION FUNCTION TABLE  .................................................................................................................. 17
-I/O PIN EQUIVALENT CIRCUIT DIAGRAM  ................................................................................................... 18
-EXAMPLE APPLICATION CIRCUIT  ................................................................................................................ 20
-PARTS LIST  ......................................................................................................................................................... 21
-APPLICATION NOTE  ......................................................................................................................................... 23
-REFERENCE DATA  ........................................................................................................................................... 40
-USAGE PRECAUTION  ...................................................................................................................................... 42
-ORDERING INFORMATION  ............................................................................................................................. 43
-EV BOARD ORDERING INFORMATION  ....................................................................................................... 43
-RoHS COMPLIANCE INFORMATION OF LEAD (Pb) FREE VERSION  ................................................... 44
-MARKING FORMAT (Lead Free version)  ....................................................................................................... 44
-LABELING SAMPLE (Lead free version)  ........................................................................................................ 45
-MB39A136PFT RECOMMENDED CONDITIONS OF MOISTURE SENSITIVITY LEVEL  ..................... 46
-PACKAGE DIMENSIONS  .................................................................................................................................. 47
-MAJOR CHANGES IN THIS EDITION  ............................................................................................................ 48

MB39A136

50 DS04-27262-4E

MEMO

MB39A136

DS04-27262-4E 51

MEMO

MB39A136

FUJITSU SEMICONDUCTOR LIMITED

Nomura Fudosan Shin-yokohama Bldg. 10-23, Shin-yokohama 2-Chome,

Kohoku-ku Yokohama Kanagawa 222-0033, Japan

Tel: +81-45-415-5858

http://jp.fujitsu.com/fsl/en/

For further information please contact:

North and South America

FUJITSU SEMICONDUCTOR AMERICA, INC.

1250 E. Arques Avenue, M/S 333

Sunnyvale, CA 94085-5401, U.S.A.

Tel: +1-408-737-5600 Fax: +1-408-737-5999

http://us.fujitsu.com/micro/

Europe

FUJITSU SEMICONDUCTOR EUROPE GmbH

Pittlerstrasse 47, 63225 Langen, Germany

Tel: +49-6103-690-0 Fax: +49-6103-690-122

http://emea.fujitsu.com/semiconductor/

Korea

FUJITSU SEMICONDUCTOR KOREA LTD.

902 Kosmo Tower Building, 1002 Daechi-Dong,

Gangnam-Gu, Seoul 135-280, Republic of Korea

Tel: +82-2-3484-7100 Fax: +82-2-3484-7111

http://kr.fujitsu.com/fsk/

Asia Pacific

FUJITSU SEMICONDUCTOR ASIA PTE. LTD.

151 Lorong Chuan,

#05-08 New Tech Park 556741 Singapore

Tel : +65-6281-0770 Fax : +65-6281-0220

http://sg.fujitsu.com/semiconductor/

FUJITSU SEMICONDUCTOR SHANGHAI CO., LTD.

30F, Kerry Parkside, 1155 Fang Dian Road, Pudong District,

Shanghai 201204, China

Tel : +86-21-6146-3688 Fax : +86-21-6146-3660

http://cn.fujitsu.com/fss/

FUJITSU SEMICONDUCTOR PACIFIC ASIA LTD.

2/F, Green 18 Building, Hong Kong Science Park,

Shatin, N.T., Hong Kong

Tel : +852-2736-3232 Fax : +852-2314-4207

http://cn.fujitsu.com/fsp/

Specifications are subject to change without notice. For further information please contact each office.

The contents of this document are subject to change without notice.

Customers are advised to consult with sales representatives before ordering.

The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose

of reference to show examples of operations and uses of FUJITSU SEMICONDUCTOR device; FUJITSU SEMICONDUCTOR does

not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating

the device based on such information, you must assume any responsibility arising out of such use of the information.

FUJITSU SEMICONDUCTOR assumes no liability for any damages whatsoever arising out of the use of the information.

Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use

or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU SEMICONDUCTOR or any

third party or does FUJITSU SEMICONDUCTOR warrant non-infringement of any third-party's intellectual property right or other right

by using such information. FUJITSU SEMICONDUCTOR assumes no liability for any infringement of the intellectual property rights or

other rights of third parties which would result from the use of information contained herein.

The products described in this document are designed, developed and manufactured as contemplated for general use, including without

limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured

as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect

to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in

nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in

weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).

Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages aris-

ing in connection with above-mentioned uses of the products.

Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-

current levels and other abnormal operating conditions.

Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations

of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.

The company names and brand names herein are the trademarks or registered trademarks of their respective owners.

Edited: Sales Promotion Department

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Spansion Inc.:

MB39A136PFT-G-BND-JNE1 MB39A136PFT-G-JN-ERE1