EFR32MG1 Mighty Gecko SoC with
Integrated Serial Flash Data Sheet
The Mighty Gecko family of SoCs is part of the Wireless Gecko
multi-protocol portfolio.
The EFR32MG1x632 and EFR32MG1x732 Mighty Gecko ICs integrate a 512 kB serial
flash in the package to support over the air updates. This 5x5 QFN32 package is ideal
for space constrained products that need to support ZigBee, Thread, BLE and propriet-
ary networks.
Mighty Gecko applications include:
KEY FEATURES
• 32-bit ARM® Cortex®-M4 core with 40
MHz maximum operating frequency
• Scalable Radio configuration options
available in QFN32 package
• 512 kB co-packaged serial flash for over
the air updates
• 12-channel Peripheral Reflex System
enabling autonomous interaction of MCU
peripherals
• Autonomous Hardware Crypto Accelerator
and Random Number Generator
• Integrated 2.4 GHz balun and PA with up
to 19.5 dBm transmit power
• 125 °C operating temperature ideal for
connected lighting applications
• Connected Home
• Lighting
• Home and Building Automation and Security
Timers and Triggers
Real Time
Counter and
Calendar
Cryotimer
Timer/Counter
Low Energy
Timer
Pulse Counter
Watchdog Timer
Protocol Timer
32-bit bus
Peripheral Reflex System
Serial
Interfaces
I/O Ports Analog I/F
Lowest power mode with peripheral operational:
USART
Low Energy
UARTTM
I2C
External
Interrupts
General
Purpose I/O
Pin Reset
Pin Wakeup
ADC
IDAC
Analog
Comparator
Radio Transceiver
DEMOD
AGC
IFADC
CRC
BUFC
RFSENSE
MOD
FRC
RAC
EM3—StopEM2—Deep SleepEM1—Sleep EM4—Hibernate EM4—ShutoffEM0—Active
PA
I
Q
RF Frontend
LNA
Frequency
Synthesizer
PGA
BALUN
Core / Memory
ARM CortexTM M4 processor
with DSP extensions and FPU
Energy Management
Brown-Out
Detector
DC-DC
Converter
Voltage
Regulator Voltage Monitor
Power-On Reset
Other
CRYPTO
CRC
Clock Management
High Frequency
Crystal
Oscillator
Low Frequency
Crystal
Oscillator
Low Frequency
RC Oscillator
High Frequency
RC Oscillator
Ultra Low
Frequency RC
Oscillator
Auxiliary High
Frequency RC
Oscillator
Serial Flash
Memory
RAM
Memory
Debug
Interface
DMA
Controller
Memory
Protection Unit
Flash
Program
Memory
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1. Feature List
The EFR32MG1 highlighted features are listed below.
•Low Power Wireless System-on-Chip.
•High Performance 32-bit 40 MHz ARM Cortex®-M4 with
DSP instruction and floating-point unit for efficient signal
processing
• 256 kB flash program memory
• 512 kB integrated serial flash memory
• 32 kB RAM data memory
• 2.4 GHz radio operation
• TX power up to 19.5 dBm
•Low Energy Consumption
• 8.7 mA RX current at 2.4 GHz (1 Mbps GFSK)
• 9.8 mA RX current at 2.4 GHz (250 kbps O-QPSK DSSS)
• 8.2 mA TX current @ 0 dBm output power at 2.4 GHz
• 63 μA/MHz in Active Mode (EM0)
• 5.5 μA EM2 DeepSleep current (full RAM retention and
RTCC running from LFXO)
• 5.1 μA EM3 Stop current (State/RAM retention)
• Wake on Radio with signal strength detection, preamble
pattern detection, frame detection and timeout
•High Receiver Performance
• -92.5 dBm sensitivity @ 1 Mbit/s GFSK
• -99 dBm sensitivity @ 250 kbps O-QPSK DSSS
•Supported Modulation Format
• 2-FSK / 4-FSK with fully configurable shaping
• Shaped OQPSK / (G)MSK
•Supported Protocols:
• Bluetooth Smart
•ZigBee®
• Thread
• 2.4 GHz Proprietary Protocols
•Support for Internet Security
• General Purpose CRC
• Random Number Generation
• Hardware Cryptographic Acceleration for AES 128/256,
SHA-1, SHA-2 (SHA-224 and SHA-256) and ECC
•Wide selection of MCU peripherals
• 12-bit 1 Msps SAR Analog to Digital Converter (ADC)
• 2× Analog Comparator (ACMP)
• Digital to Analog Current Converter (IDAC)
• Up to 16 pins connected to analog channels (APORT)
shared between Analog Comparators, ADC, and IDAC
• Up to 16 General Purpose I/O pins with output state reten-
tion and asynchronous interrupts
• 8 Channel DMA Controller
• 12 Channel Peripheral Reflex System (PRS)
• 2×16-bit Timer/Counter
• 3 + 4 Compare/Capture/PWM channels
• 32-bit Real Time Counter and Calendar
• 16-bit Low Energy Timer for waveform generation
• 32-bit Ultra Low Energy Timer/Counter for periodic wake-up
from any Energy Mode
• 16-bit Pulse Counter with asynchronous operation
• Watchdog Timer with dedicated RC oscillator @ 50nA
• Universal Synchronous/Asynchronous Receiver/Transmitter
(UART/SPI/SmartCard (ISO 7816)/IrDA)
•Low Energy UART (LEUART™)
•I2C interface with SMBus support and address recognition
in EM3 Stop
•Wide Operating Range
• 2.3 V to 3.6 V single power supply
• Integrated DC-DC, down to 1.8 V output with up to 200 mA
load current for system
• Standard (-40 °C to 85 °C) and Extended (-40 °C to 125 °C)
temperature grades available
•QFN32 5x5 mm Package
EFR32MG1 Mighty Gecko SoC with Integrated Serial Flash Data Sheet
Feature List
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2. Ordering Information
Ordering Code Protocol Stack Frequency Band
@ Max TX Power
Flash
(kB)
Serial
Flash
(kB)
RAM
(kB)
Temp
Range
EFR32MG1P732F256GM32-C0 • Bluetooth
Smart
• ZigBee
• Thread
• ZigBee RC
• Proprietary
2.4 GHz @ 19.5 dBm 256 512 32 -40 to +85
EFR32MG1P732F256IM32-C0 • Bluetooth
Smart
• ZigBee
• Thread
• ZigBee RC
• Proprietary
2.4 GHz @ 19.5 dBm 256 512 32 -40 to
+125
EFR32MG1P632F256GM32-C0 • Bluetooth
Smart
• ZigBee
• Thread
• ZigBee RC
• Proprietary
2.4 GHz @ 16.5 dBm 256 512 32 -40 to +85
EFR32MG1P632F256IM32-C0 • Bluetooth
Smart
• ZigBee
• Thread
• ZigBee RC
• Proprietary
2.4 GHz @ 16.5 dBm 256 512 32 -40 to
+125
EFR32MG1B732F256GM32-C0 • ZigBee
• Thread
• ZigBee RC
2.4 GHz @ 19.5 dBm 256 512 32 -40 to +85
EFR32MG1B732F256IM32-C0 • ZigBee
• Thread
• ZigBee RC
2.4 GHz @ 19.5 dBm 256 512 32 -40 to
+125
EFR32MG1B632F256GM32-C0 • ZigBee
• Thread
• ZigBee RC
2.4 GHz @ 16.5 dBm 256 512 32 -40 to +85
EFR32MG1B632F256IM32-C0 • ZigBee
• Thread
• ZigBee RC
2.4 GHz @ 16.5 dBm 256 512 32 -40 to
+125
EFR32MG1 Mighty Gecko SoC with Integrated Serial Flash Data Sheet
Ordering Information
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EFR32 –1 P F G C0 R
Tape and Reel (Optional)
Revision
Pin Count
Package – M (QFN), J (CSP)
Flash Memory Size in kB
Memory Type (Flash)
Feature Set Code – r2r1r0
r2: Reserved
r1: RF Type – 3 (TRX), 2 (RX), 1 (TX)
r0: Frequency Band – 1 (Sub-GHz), 2 (2.4 GHz), 3 (Dual-Band)
G
X132 256 M 32
Temperature Grade – G (-40 to +85 °C), -I (-40 to +125 °C)
Performance Grade – P (Performance), B (Basic), V (Value)
Generation
Family – M (Mighty), B (Blue), F (Flex)
Wireless Gecko 32-bit
Gecko
Figure 2.1. OPN Decoder
EFR32MG1 Mighty Gecko SoC with Integrated Serial Flash Data Sheet
Ordering Information
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3. System Overview
3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a highly integrated radio transceiver. This section gives a short intro-
duction to the full radio and MCU system. The detailed functional description can be found in the EFR32 Reference Manual.
A block diagram of the EFR32MG1 family is shown in Figure 3.1 Detailed EFR32MG1 Block Diagram on page 4. The diagram
shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult
Ordering Information.
Analog Peripherals
Clock Management
LFXTAL_P / N LFXO
IDAC
ARM Cortex-M4 Core
Up to 256 kB ISP Flash
Program Memory
Up to 32 kB RAM
A
H
B
Watchdog
Timer
Reset
Management
Unit
Brown Out /
Power-On
Reset
RESETn
Digital Peripherals
Input MUX
Port
Mapper
Port I/O Configuration
I2C
Analog Comparator
12-bit ADC
Temp
Sensor
VREFVDD
VDD
Internal
Reference
TIMER
CRYOTIMER
PCNT
USART
Port A
Drivers
Port B
Drivers
PAn
Port C
Drivers PCn
PBn
Port D
Drivers PDn
LETIMER
RTC / RTCC
IOVDD
AUXHFRCO
HFRCO
ULFRCO
HFXO
Port F
Drivers PFn
Memory Protection Unit
LFRCO
LEUART
CRYPTO
CRC
DMA Controller
+
-
APORT
Floating Point Unit
Energy Management
DC-DC
Converter
DVDD
VREGVDD
VSS
VREGSW
bypass
AVDD
PAVDD
RFVDD
Voltage
Regulator
DECOUPLE
IOVDD
Voltage
Monitor
VREGVSS
RFVSS
PAVSS
Serial Wire Debug /
Programming
Radio Transciever
2G4RF_IOP
2G4RF_ION
RF Frontend
PA
I
Q
LNA
BALUN
RFSENSE
Frequency
Synthesizer
DEMOD
AGC
IFADC
CRC
BUFC
MOD
FRC
RAC
PGA
HFXTAL_P
HFXTAL_N
Co-Packaged Resources
512 kB Serial Flash Memory
A
P
B
Figure 3.1. Detailed EFR32MG1 Block Diagram
3.2 Radio
The Mighty Gecko family features a highly configurable radio transceiver supporting a wide range of wireless protocols.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two pins (2G4RF_IOP and 2G4RF_ION) that interface directly to the on-chip BALUN. The
2G4RF_ION pin should be grounded externally.
The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching
Networks section.
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3.2.2 Fractional-N Frequency Synthesizer
The EFR32MG1 contains a high performance, low phase noise, fully integrated fractional-N frequency synthesizer. The synthesizer is
used in receive mode to generate the LO frequency used by the down-conversion mixer. It is also used in transmit mode to directly
generate the modulated RF carrier.
The fractional-N architecture provides excellent phase noise performance combined with frequency resolution better than 100 Hz, with
low energy consumption. The synthesizer has fast frequency settling which allows very short receiver and transmitter wake up times to
optimize system energy consumption.
3.2.3 Receiver Architecture
The EFR32MG1 uses a low-IF receiver architecture, consisting of a Low-Noise Amplifier (LNA) followed by an I/Q down-conversion
mixer, employing a crystal reference. The I/Q signals are further filtered and amplified before being sampled by the IF analog-to-digital
converter (IFADC).
The IF frequency is configurable from 150 kHz to 1371 kHz. The IF can further be configured for high-side or low-side injection, provid-
ing flexibility with respect to known interferers at the image frequency.
The Automatic Gain Control (AGC) module adjusts the receiver gain to optimize performance and avoid saturation for excellent selec-
tivity and blocking performance. Devices are production-calibrated to improve image rejection performance.
Demodulation is performed in the digital domain. The demodulator performs configurable decimation and channel filtering to allow re-
ceive bandwidths ranging from 0.1 to 2530 kHz. High carrier frequency and baud rate offsets are tolerated by active estimation and
compensation. Advanced features supporting high quality communication under adverse conditions include forward error correction by
block and convolutional coding as well as Direct Sequence Spread Spectrum (DSSS).
A Received Signal Strength Indicator (RSSI) is available for signal quality metrics, for level-based proximity detection, and for RF chan-
nel access by Collision Avoidance (CA) or Listen Before Talk (LBT) algorithms. An RSSI capture value is associated with each received
frame and the dynamic RSSI measurement can be monitored throughout reception.
The EFR32MG1 features integrated support for antenna diversity to improve link budget, using complementary control outputs to an
external switch. Internal configurable hardware controls automatic switching between antennae during RF receive detection operations.
3.2.4 Transmitter Architecture
The EFR32MG1 uses a direct-conversion transmitter architecture. For constant envelope modulation formats, the modulator controls
phase and frequency modulation in the frequency synthesizer. Transmit symbols or chips are optionally shaped by a digital shaping
filter. The shaping filter is fully configurable, including the BT product, and can be used to implement Gaussian or Raised Cosine shap-
ing.
Carrier Sense Multiple Access - Collision Avoidance (CSMA-CA) or Listen Before Talk (LBT) algorithms can be automatically timed by
the EFR32MG1. These algorithms are typically defined by regulatory standards to improve inter-operability in a given bandwidth be-
tween devices that otherwise lack synchronized RF channel access.
3.2.5 Wake on Radio
The Wake on Radio feature allows flexible, autonomous RF sensing, qualification, and demodulation without required MCU activity, us-
ing a subsystem of the EFR32MG1 including the Radio Controller (RAC), Peripheral Reflex System (PRS), and Low Energy peripher-
als.
3.2.6 RFSENSE
The RFSENSE module generates a system wakeup interrupt upon detection of wideband RF energy at the antenna interface, providing
true RF wakeup capabilities from low energy modes including EM2, EM3 and EM4.
RFSENSE triggers on a relatively strong RF signal and is available in the lowest energy modes, allowing exceptionally low energy con-
sumption. RFSENSE does not demodulate or otherwise qualify the received signal, but software may respond to the wakeup event by
enabling normal RF reception.
Various strategies for optimizing power consumption and system response time in presence of false alarms may be employed using
available timer peripherals.
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3.2.7 Flexible Frame Handling
EFR32MG1 has an extensive and flexible frame handling support for easy implementation of even complex communication protocols.
The Frame Controller (FRC) supports all low level and timing critical tasks together with the Radio Controller and Modulator/
Demodulator:
• Highly adjustable preamble length
• Up to 2 simultaneous synchronization words, each up to 32 bits and providing separate interrupts
• Frame disassembly and address matching (filtering) to accept or reject frames
• Automatic ACK frame assembly and transmission
• Fully flexible CRC generation and verification:
• Multiple CRC values can be embedded in a single frame
• 8, 16, 24 or 32-bit CRC value
• Configurable CRC bit and byte ordering
• Selectable bit-ordering (least significant or most significant bit first)
• Optional data whitening
• Optional Forward Error Correction (FEC), including convolutional encoding / decoding and block encoding / decoding
• Half rate convolutional encoder and decoder with constraint lengths from 2 to 7 and optional puncturing
• Optional symbol interleaving, typically used in combination with FEC
• Symbol coding, such as Manchester or DSSS, or biphase space encoding using FEC hardware
• UART encoding over air, with start and stop bit insertion / removal
• Test mode support, such as modulated or unmodulated carrier output
• Received frame timestamping
3.2.8 Packet and State Trace
The EFR32MG1 Frame Controller has a packet and state trace unit that provides valuable information during the development phase. It
features:
• Non-intrusive trace of transmit data, receive data and state information
• Data observability on a single-pin UART data output, or on a two-pin SPI data output
• Configurable data output bitrate / baudrate
• Multiplexed transmitted data, received data and state / meta information in a single serial data stream
3.2.9 Data Buffering
The EFR32MG1 features an advanced Radio Buffer Controller (BUFC) capable of handling up to 4 buffers of adjustable size from 64
bytes to 4096 bytes. Each buffer can be used for RX, TX or both. The buffer data is located in RAM, enabling zero-copy operations.
3.2.10 Radio Controller (RAC)
The Radio Controller controls the top level state of the radio subsystem in the EFR32MG1. It performs the following tasks:
• Precisely-timed control of enabling and disabling of the receiver and transmitter circuitry
• Run-time calibration of receiver, transmitter and frequency synthesizer
• Detailed frame transmission timing, including optional LBT or CSMA-CA
3.2.11 Random Number Generator
The Frame Controller (FRC) implements a random number generator that uses entropy gathered from noise in the RF receive chain.
The data is suitable for use in cryptographic applications.
Output from the random number generator can be used either directly or as a seed or entropy source for software-based random num-
ber generator algorithms such as Fortuna.
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3.3 Power
The EFR32MG1 has an Energy Management Unit (EMU) and efficient integrated regulators to generate internal supply voltages. Only a
single external supply voltage is required, from which all internal voltages are created. An optional integrated DC-DC buck regulator can
be utilized to further reduce the current consumption. The DC-DC regulator requires one external inductor and one external capacitor.
Running from a sufficiently high supply, the device can use the DC-DC to regulate voltage not only for itself, but also for other PCB
components, supplying up to a total of 200 mA.
3.3.1 Energy Management Unit (EMU)
The Energy Management Unit manages transitions of energy modes in the device. Each energy mode defines which peripherals and
features are available and the amount of current the device consumes. The EMU can also be used to turn off the power to unused RAM
blocks, and it contains control registers for the dc-dc regulator and the Voltage Monitor (VMON). The VMON is used to monitor multiple
supply voltages. It has multiple channels which can be programmed individually by the user to determine if a sensed supply has fallen
below a chosen threshold.
3.3.2 DC-DC Converter
The DC-DC buck converter covers a wide range of load currents and provides up to 90% efficiency in energy modes EM0, EM1, EM2
and EM3, and can supply up to 200 mA to the device and surrounding PCB components. Patented RF noise mitigation allows operation
of the DC-DC converter without degrading sensitivity of radio components. Protection features include programmable current limiting,
short-circuit protection, and dead-time protection. The DC-DC converter may also enter bypass mode when the input voltage is too low
for efficient operation. In bypass mode, the DC-DC input supply is internally connected directly to its output through a low resistance
switch. Bypass mode also supports in-rush current limiting to prevent input supply voltage droops due to excessive output current tran-
sients.
3.4 General Purpose Input/Output (GPIO)
EFR32MG1 has up to 16 General Purpose Input/Output pins. Each GPIO pin can be individually configured as either an output or input.
More advanced configurations including open-drain, open-source, and glitch-filtering can be configured for each individual GPIO pin.
The GPIO pins can be overridden by peripheral connections, like SPI communication. Each peripheral connection can be routed to sev-
eral GPIO pins on the device. The input value of a GPIO pin can be routed through the Peripheral Reflex System to other peripherals.
The GPIO subsystem supports asynchronous external pin interrupts.
3.5 Clocking
3.5.1 Clock Management Unit (CMU)
The Clock Management Unit controls oscillators and clocks in the EFR32MG1. Individual enabling and disabling of clocks to all periph-
eral modules is performed by the CMU. The CMU also controls enabling and configuration of the oscillators. A high degree of flexibility
allows software to optimize energy consumption in any specific application by minimizing power dissipation in unused peripherals and
oscillators.
3.5.2 Internal and External Oscillators
The EFR32MG1 supports two crystal oscillators and fully integrates four RC oscillators, listed below.
• A high frequency crystal oscillator (HFXO) with integrated load capacitors, tunable in small steps, provides a precise timing refer-
ence for the MCU. Crystal frequencies in the range from 38 to 40 MHz are supported. An external clock source such as a TCXO can
also be applied to the HFXO input for improved accuracy over temperature.
• A 32.768 kHz crystal oscillator (LFXO) provides an accurate timing reference for low energy modes.
• An integrated high frequency RC oscillator (HFRCO) is available for the MCU system, when crystal accuracy is not required. The
HFRCO employs fast startup at minimal energy consumption combined with a wide frequency range.
• An integrated auxilliary high frequency RC oscillator (AUXHFRCO) is available for timing the general-purpose ADC and the Serial
Wire debug port with a wide frequency range.
• An integrated low frequency 32.768 kHz RC oscillator (LFRCO) can be used as a timing reference in low energy modes, when crys-
tal accuracy is not required.
• An integrated ultra-low frequency 1 kHz RC oscillator (ULFRCO) is available to provide a timing reference at the lowest energy con-
sumption in low energy modes.
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3.6 Counters/Timers and PWM
3.6.1 Timer/Counter (TIMER)
TIMER peripherals keep track of timing, count events, generate PWM outputs and trigger timed actions in other peripherals through the
PRS system. The core of each TIMER is a 16-bit counter with up to 4 compare/capture channels. Each channel is configurable in one
of three modes. In capture mode, the counter state is stored in a buffer at a selected input event. In compare mode, the channel output
reflects the comparison of the counter to a programmed threshold value. In PWM mode, the TIMER supports generation of pulse-width
modulation (PWM) outputs of arbitrary waveforms defined by the sequence of values written to the compare registers, with optional
dead-time insertion available in timer unit TIMER_0 only.
3.6.2 Real Time Counter and Calendar (RTCC)
The Real Time Counter and Calendar (RTCC) is a 32-bit counter providing timekeeping in all energy modes. The RTCC includes a
Binary Coded Decimal (BCD) calendar mode for easy time and date keeping. The RTCC can be clocked by any of the on-board oscilla-
tors with the exception of the AUXHFRCO, and it is capable of providing system wake-up at user defined instances. When receiving
frames, the RTCC value can be used for timestamping. The RTCC includes 128 bytes of general purpose data retention, allowing easy
and convenient data storage in all energy modes.
3.6.3 Low Energy Timer (LETIMER)
The unique LETIMER is a 16-bit timer that is available in energy mode EM2 Deep Sleep in addition to EM1 Sleep and EM0 Active. This
allows it to be used for timing and output generation when most of the device is powered down, allowing simple tasks to be performed
while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of wave-
forms with minimal software intervention. The LETIMER is connected to the Real Time Counter and Calendar (RTCC), and can be con-
figured to start counting on compare matches from the RTCC.
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER)
The CRYOTIMER is a 32-bit counter that is capable of running in all energy modes. It can be clocked by either the 32.768 kHz crystal
oscillator (LFXO), the 32.768 kHz RC oscillator (LFRCO), or the 1 kHz RC oscillator (ULFRCO). It can provide periodic Wakeup events
and PRS signals which can be used to wake up peripherals from any energy mode. The CRYOTIMER provides a wide range of inter-
rupt periods, facilitating flexible ultra-low energy operation.
3.6.5 Pulse Counter (PCNT)
The Pulse Counter (PCNT) peripheral can be used for counting pulses on a single input or to decode quadrature encoded inputs. The
clock for PCNT is selectable from either an external source on pin PCTNn_S0IN or from an internal timing reference, selectable from
among any of the internal oscillators, except the AUXHFRCO. The module may operate in energy mode EM0 Active, EM1 Sleep, EM2
Deep Sleep, and EM3 Stop.
3.6.6 Watchdog Timer (WDOG)
The watchdog timer can act both as an independent watchdog or as a watchdog synchronous with the CPU clock. It has windowed
monitoring capabilities, and can generate a reset or different interrupts depending on the failure mode of the system. The watchdog can
also monitor autonomous systems driven by PRS.
3.7 Communications and Other Digital Peripherals
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
The Universal Synchronous/Asynchronous Receiver/Transmitter is a flexible serial I/O module. It supports full duplex asynchronous
UART communication with hardware flow control as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with devices sup-
porting:
• ISO7816 SmartCards
• IrDA
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)
The unique LEUARTTM provides two-way UART communication on a strict power budget. Only a 32.768 kHz clock is needed to allow
UART communication up to 9600 baud. The LEUART includes all necessary hardware to make asynchronous serial communication
possible with a minimum of software intervention and energy consumption.
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3.7.3 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C bus. It is capable of acting as both a master and a slave and
supports multi-master buses. Standard-mode, fast-mode and fast-mode plus speeds are supported, allowing transmission rates from 10
kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also available, allowing implementation of an SMBus-compliant system. The
interface provided to software by the I2C module allows precise timing control of the transmission process and highly automated trans-
fers. Automatic recognition of slave addresses is provided in active and low energy modes.
3.7.4 Peripheral Reflex System (PRS)
The Peripheral Reflex System provides a communication network between different peripheral modules without software involvement.
Peripheral modules producing Reflex signals are called producers. The PRS routes Reflex signals from producers to consumer periph-
erals which in turn perform actions in response. Edge triggers and other functionality can be applied by the PRS. The PRS allows pe-
ripheral to act autonomously without waking the MCU core, saving power.
3.8 Security Features
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check)
The GPCRC module implements a Cyclic Redundancy Check (CRC) function. It supports both 32-bit and 16-bit polynomials. The sup-
ported 32-bit polynomial is 0x04C11DB7 (IEEE 802.3), while the 16-bit polynomial can be programmed to any value, depending on the
needs of the application.
3.8.2 Crypto Accelerator (CRYPTO)
The Crypto Accelerator is a fast and energy-efficient autonomous hardware encryption and decryption accelerator. EFR32 devices sup-
port various levels of hardware-accelerated encryption, depending on the part number. AES-only devices support AES encryption and
decryption with 128- or 256-bit keys. Full crypto support adds ECC over both GF(P) and GF(2m), SHA-1 and SHA-2 (SHA-224 and
SHA-256).
Supported block cipher modes of operation for AES include: ECB, CTR, CBC, PCBC, CFB, OFB, GCM, CBC-MAC, GMAC and CCM.
Supported ECC NIST recommended curves include P-192, P-224, P-256, K-163, K-233, B-163 and B-233.
The CRYPTO is tightly linked to the Radio Buffer Controller (BUFC) enabling fast and efficient autonomous cipher operations on data
buffer content. It allows fast processing of GCM (AES), ECC and SHA with little CPU intervention. CRYPTO also provides trigger sig-
nals for DMA read and write operations.
3.9 Analog
3.9.1 Analog Port (APORT)
The Analog Port (APORT) is an analog interconnect matrix allowing access to analog modules ADC, ACMP, and IDAC on a flexible
selection of pins. Each APORT bus consists of analog switches connected to a common wire. Since many clients can operate differen-
tially, buses are grouped by X/Y pairs.
3.9.2 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-
er. Inputs are selected from among internal references and external pins. The tradeoff between response time and current consumption
is configurable by software. Two 6-bit reference dividers allow for a wide range of internally-programmable reference sources. The
ACMP can also be used to monitor the supply voltage. An interrupt can be generated when the supply falls below or rises above the
programmable threshold.
3.9.3 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to 1 MSamples/s. The
output sample resolution is configurable and additional resolution is possible using integrated hardware for averaging over multiple
samples. The ADC includes integrated voltage references and an integrated temperature sensor. Inputs are selectable from a wide
range of sources, including pins configurable as either single-ended or differential.
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3.9.4 Digital to Analog Current Converter (IDAC)
The Digital to Analog Current Converter can source or sink a configurable constant current. This current can be driven on an output pin
or routed to the selected ADC input pin for capacitive sensing. The current is programmable between 0.05 µA and 64 µA with several
ranges with various step sizes.
3.10 Reset Management Unit (RMU)
The RMU is responsible for handling reset of the EFR32MG1. A wide range of reset sources are available, including several power
supply monitors, pin reset, software controlled reset, core lockup reset and watchdog reset.
3.11 Core and Memory
3.11.1 Processor Core
The ARM Cortex-M processor includes a 32-bit RISC processor integrating the following features and tasks in the system:
• ARM Cortex-M4 RISC processor achieving 1.25 Dhrystone MIPS/MHz
• Memory Protection Unit (MPU) supporting up to 8 memory segments
• Up to 256 kB flash program memory
• Up to 32 kB RAM data memory
• Configuration and event handling of all modules
• 2-pin Serial-Wire debug interface
3.11.2 Serial Flash
512 kB of high-speed, low-power serial flash is included in the system, accessible via a dedicated serial interface. The serial flash is
internal to the package, requiring no additional area on the PCB. Software libraries enable easy API-level access to this memory space.
3.11.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the microcontroller. The flash memory is readable and writable
from both the Cortex-M and DMA. The flash memory is divided into two blocks; the main block and the information block. Program code
is normally written to the main block, whereas the information block is available for special user data and flash lock bits. There is also a
read-only page in the information block containing system and device calibration data. Read and write operations are supported in en-
ergy modes EM0 Active and EM1 Sleep.
3.11.4 Linked Direct Memory Access Controller (LDMA)
The Linked Direct Memory Access (LDMA) controller features 8 channels capable of performing memory operations independently of
software. This reduces both energy consumption and software workload. The LDMA allows operations to be linked together and stag-
ed, enabling sophisticated operations to be implemented.
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3.12 Memory Map
The EFR32MG1 memory map is shown in the figures below. RAM and flash sizes are for the largest memory configuration.
Figure 3.2. EFR32MG1 Memory Map — Core Peripherals and Code Space
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Figure 3.3. EFR32MG1 Memory Map — Peripherals
3.13 Configuration Summary
The features of the EFR32MG1 are a subset of the feature set described in the device reference manual. The table below describes
device specific implementation of the features. Remaining modules support full configuration.
Table 3.1. Configuration Summary
Module Configuration Pin Connections
USART0 IrDA SmartCard US0_TX, US0_RX, US0_CLK, US0_CS
TIMER0 with DTI TIM0_CC[2:0], TIM0_CDTI[2:0]
TIMER1 TIM1_CC[3:0]
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4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the following conditions, unless stated otherwise:
• Typical values are based on TAMB=25 °C and VDD= 3.3 V, by production test and/or technology characterization.
• Radio performance numbers are measured in conducted mode, based on Silicon Laboratories reference designs using output pow-
er-specific external RF impedance-matching networks for interfacing to a 50 Ω antenna.
• Minimum and maximum values represent the worst conditions across supply voltage, process variation, and operating temperature,
unless stated otherwise.
Refer to Table 4.2 General Operating Conditions on page 15 for more details about operational supply and temperature limits.
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4.1.1 Absolute Maximum Ratings
Stresses above those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of
the devices at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect device reliability. For more information on the available quality and relia-
bility data, see the Quality and Reliability Monitor Report at http://www.silabs.com/support/quality/pages/default.aspx.
Table 4.1. Absolute Maximum Ratings
Parameter Symbol Test Condition Min Typ Max Unit
Storage temperature range TSTG -50 — 150 °C
External main supply voltage VDDMAX 0 — 3.6 V
External main supply voltage
ramp rate
VDDRAMPMAX — — 1 V / μs
Voltage on any 5V tolerant
GPIO pin1
VDIGPIN -0.3 — Min of 5.25
and IOVDD
+2
V
Voltage on non-5V tolerant
GPIO pins
-0.3 — IOVDD+0.3 V
Voltage on HFXO pins VHFXOPIN -0.3 — 1.4 V
Input RF level on pins
2G4RF_IOP and
2G4RF_ION
PRFMAX2G4 — — 10 dBm
Voltage differential between
RF pins (2G4RF_IOP -
2G4RF_ION)
VMAXDIFF2G4 -50 — 50 mV
Absolute Voltage on RF pins
2G4RF_IOP and
2G4RF_ION
VMAX2G4 -0.3 — 3.3 V
Total current into VDD power
lines (source)
IVDDMAX — — 200 mA
Total current into VSS
ground lines (sink)
IVSSMAX — — 200 mA
Current per I/O pin (sink) IIOMAX — — 50 mA
Current per I/O pin (source) — — 50 mA
Current for all I/O pins (sink) IIOALLMAX — — 200 mA
Current for all I/O pins
(source)
— — 200 mA
Voltage difference between
AVDD and VREGVDD
ΔVDD — — 0.3 V
Junction Temperature for -G
grade devices
TJ-40 — 105 °C
Junction Temperature for -I
grade devices
-40 — 125 °C
Note:
1. When a GPIO pin is routed to the analog module through the APORT, the maximum voltage = IOVDD.
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4.1.2 Operating Conditions
When assigning supply sources, the following requirements must be observed:
• VREGVDD must be the highest voltage in the system
• VREGVDD = AVDD
• DVDD ≤ AVDD
• IOVDD ≤ AVDD
• RFVDD ≤ AVDD
• PAVDD ≤ AVDD
4.1.2.1 General Operating Conditions
Table 4.2. General Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Operating temperature range TOP -G temperature grade, Ambient
Temperature
-40 25 85 °C
-I temperature grade, Junction
Temperature
-40 25 125 °C
AVDD Supply voltage1VAVDD 2.3 3.3 3.6 V
VREGVDD Operating supply
voltage1 2
VVREGVDD DCDC in regulation 2.4 3.3 3.6 V
DCDC in bypass 50mA load 2.3 3.3 3.6 V
DCDC not in use. DVDD external-
ly shorted to VREGVDD
2.3 3.3 3.6 V
VREGVDD Current IVREGVDD DCDC in bypass, Tamb ≤ 85 °C — — 200 mA
DCDC in bypass, Tamb > 85 °C — — 100 mA
RFVDD Operating supply
voltage
VRFVDD 1.62 — VVREGVDD V
DVDD Operating supply volt-
age
VDVDD 1.62 — VVREGVDD V
PAVDD Operating supply
voltage
VPAVDD 1.62 — VVREGVDD V
IOVDD Operating supply
voltage
VIOVDD 2.3 — VVREGVDD V
Difference between AVDD
and VREGVDD, ABS(AVDD-
VREGVDD)
dVDD — — 0.1 V
HFCLK frequency fCORE 0 wait-states (MODE = WS0) 3— — 26 MHz
1 wait-states (MODE = WS1) 3— 38.4 40 MHz
Note:
1. VREGVDD must be tied to AVDD. Both VREGVDD and AVDD minimum voltages must be satisfied for the part to operate.
2. The minimum voltage required in bypass mode is calculated using RBYP from the DCDC specification table. Requirements for
other loads can be calculated as VDVDD_min+ILOAD * RBYP_max
3. In MSC_READCTRL register
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4.1.3 Thermal Characteristics
Table 4.3. Thermal Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Thermal Resistance THETAJA QFN32 Package, 2-Layer PCB,
Air velocity = 0 m/s
— 85.2 — °C/W
QFN32 Package, 2-Layer PCB,
Air velocity = 1 m/s
— 67.1 — °C/W
QFN32 Package, 2-Layer PCB,
Air velocity = 2 m/s
— 58.3 — °C/W
QFN32 Package, 4-Layer PCB,
Air velocity = 0 m/s
— 36.9 — °C/W
QFN32 Package, 4-Layer PCB,
Air velocity = 1 m/s
— 32.4 — °C/W
QFN32 Package, 4-Layer PCB,
Air velocity = 2 m/s
— 31 — °C/W
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4.1.4 DC-DC Converter
Test conditions: LDCDC=4.7 µH (Murata LQH3NPN4R7MM0L), CDCDC=1.0 µF (Murata GRM188R71A105KA61D), VDCDC_I=3.3 V,
VDCDC_O=1.8 V, IDCDC_LOAD=50 mA, Heavy Drive configuration, FDCDC_LN=7 MHz, unless otherwise indicated.
Table 4.4. DC-DC Converter
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VDCDC_I Bypass mode, IDCDC_LOAD = 50
mA
2.3 — VVREGVDD_
MAX
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 100 mA, or
Low power (LP) mode, 1.8 V out-
put, IDCDC_LOAD = 10 mA
2.4 — VVREGVDD_
MAX
V
Low noise (LN) mode, 1.8 V out-
put, IDCDC_LOAD = 200 mA
2.6 — VVREGVDD_
MAX
V
Output voltage programma-
ble range1
VDCDC_O 1.8 — VVREGVDD V
Regulation DC Accuracy ACCDC Low noise (LN) mode, 1.8 V target
output
1.7 — 1.9 V
Regulation Window2WINREG Low power (LP) mode,
LPCMPBIAS3 = 0, 1.8 V target
output, IDCDC_LOAD ≤ 75 μA
1.63 — 2.2 V
Low power (LP) mode,
LPCMPBIAS3 = 3, 1.8 V target
output, IDCDC_LOAD ≤ 10 mA
1.63 — 2.1 V
Steady-state output ripple VRRadio disabled. — 3 — mVpp
Output voltage under/over-
shoot
VOV CCM Mode (LNFORCECCM3 =
1), Load changes between 0 mA
and 100 mA
— — 150 mV
DCM Mode (LNFORCECCM3 =
0), Load changes between 0 mA
and 10 mA
— — 150 mV
Overshoot during LP to LN
CCM/DCM mode transitions com-
pared to DC level in LN mode
— 200 — mV
Undershoot during BYP/LP to LN
CCM (LNFORCECCM3 = 1) mode
transitions compared to DC level
in LN mode
— 50 — mV
Undershoot during BYP/LP to LN
DCM (LNFORCECCM3 = 0) mode
transitions compared to DC level
in LN mode
— 125 — mV
DC line regulation VREG Input changes between
VVREGVDD_MAX and 2.4 V
— 0.1 — %
DC load regulation IREG Load changes between 0 mA and
100 mA in CCM mode
— 0.1 — %
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Parameter Symbol Test Condition Min Typ Max Unit
Max load current ILOAD_MAX Low noise (LN) mode, Heavy
Drive4, Tamb ≤ 85 °C
— — 200 mA
Low noise (LN) mode, Heavy
Drive4, Tamb > 85 °C
— — 100 mA
Low noise (LN) mode, Medium
Drive4
— — 100 mA
Low noise (LN) mode, Light
Drive4
— — 50 mA
Low power (LP) mode,
LPCMPBIAS3 = 0
— — 75 μA
Low power (LP) mode,
LPCMPBIAS3 = 3
— — 10 mA
DCDC nominal output ca-
pacitor
CDCDC 25% tolerance 1 1 1 μF
DCDC nominal output induc-
tor
LDCDC 20% tolerance 4.7 4.7 4.7 μH
Resistance in Bypass mode RBYP — 1.2 2.5 Ω
Note:
1. Due to internal dropout, the DC-DC output will never be able to reach its input voltage, VVREGVDD
2. LP mode controller is a hysteretic controller that maintains the output voltage within the specified limits
3. In EMU_DCDCMISCCTRL register
4. Drive levels are defined by configuration of the PFETCNT and NFETCNT registers. Light Drive: PFETCNT=NFETCNT=3; Medi-
um Drive: PFETCNT=NFETCNT=7; Heavy Drive: PFETCNT=NFETCNT=15.
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4.1.5 Current Consumption
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = DVDD = RFVDD = PAVDD = 3.3 V. TOP = 25 °C.
EMU_PWRCFG_PWRCG=NODCDC. EMU_DCDCCTRL_DCDCMODE=BYPASS. Minimum and maximum values in this table repre-
sent the worst conditions across supply voltage and process variation at TOP = 25 °C. See Figure 5.1 EFR32MG1 Typical Application
Circuit: Direct Supply Configuration without DC-DC converter on page 64.
Table 4.5. Current Consumption 3.3V without DC/DC
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
Active mode with all periph-
erals disabled
IACTIVE 38.4 MHz crystal, CPU running
while loop from flash1
— 130 — μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 88 — μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 100 105 μA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 112 — μA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 102 106 μA/MHz
1 MHz HFRCO, CPU running
while loop from flash
— 222 350 μA/MHz
Current consumption in EM1
Sleep mode with all peripher-
als disabled
IEM1 38.4 MHz crystal1— 65 — μA/MHz
38 MHz HFRCO — 35 38 μA/MHz
26 MHz HFRCO — 37 41 μA/MHz
1 MHz HFRCO — 157 275 μA/MHz
Current consumption in EM2
Deep Sleep mode.
IEM2 Full RAM retention and RTCC
running from LFXO, serial flash in
deep power down
— 6.3 — μA
4 kB RAM retention and RTCC
running from LFRCO, serial flash
in deep power down
— 6 9.2 μA
Current consumption in EM3
Stop mode
IEM3 Full RAM retention and CRYO-
TIMER running from ULFRCO,
serial flash in deep power down
— 5.8 9.2 μA
Current consumption in
EM4H Hibernate mode
IEM4 128 byte RAM retention, RTCC
running from LFXO
— 4.1 — μA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
— 3.65 — μA
128 byte RAM retention, no RTCC — 3.65 4.7 μA
Current consumption in
EM4S Shutoff mode
IEM4S no RAM retention, no RTCC — 3.04 3.6 μA
Note:
1. CMU_HFXOCTRL_LOWPOWER=0
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4.1.5.2 Current Consumption 3.3 V using DC-DC Converter
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD = 1.8 V DC-DC
output. TOP = 25 °C. Minimum and maximum values in this table represent the worst conditions across supply voltage and process
variation at TOP = 25 °C. See Figure 5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from
VDCDC) on page 64.
Table 4.6. Current Consumption 3.3V with DC-DC
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in EM0
Active mode with all periph-
erals disabled, DCDC in Low
Noise DCM mode1.
IACTIVE 38.4 MHz crystal, CPU running
while loop from flash2
— 88 — μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 63 — μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 71 — μA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 78 — μA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 76 — μA/MHz
Current consumption in EM0
Active mode with all periph-
erals disabled, DCDC in Low
Noise CCM mode3.
38.4 MHz crystal, CPU running
while loop from flash2
— 98 — μA/MHz
38 MHz HFRCO, CPU running
Prime from flash
— 75 — μA/MHz
38 MHz HFRCO, CPU running
while loop from flash
— 81 — μA/MHz
38 MHz HFRCO, CPU running
CoreMark from flash
— 88 — μA/MHz
26 MHz HFRCO, CPU running
while loop from flash
— 94 — μA/MHz
Current consumption in EM1
Sleep mode with all peripher-
als disabled, DCDC in Low
Noise DCM mode1.
IEM1 38.4 MHz crystal2— 49 — μA/MHz
38 MHz HFRCO — 32 — μA/MHz
26 MHz HFRCO — 38 — μA/MHz
Current consumption in EM1
Sleep mode with all peripher-
als disabled, DCDC in Low
Noise CCM mode3.
38.4 MHz crystal2— 61 — μA/MHz
38 MHz HFRCO — 45 — μA/MHz
26 MHz HFRCO — 58 — μA/MHz
Current consumption in EM2
Deep Sleep mode. DCDC in
Low Power mode4.
IEM2 Full RAM retention and RTCC
running from LFXO, serial flash in
deep power down
— 5.5 — μA
4 kB RAM retention and RTCC
running from LFRCO, serial flash
in deep power down
— 5.2 — μA
Current consumption in EM3
Stop mode
IEM3 Full RAM retention and CRYO-
TIMER running from ULFRCO,
serial flash in deep power down
— 5.1 — μA
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Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in
EM4H Hibernate mode
IEM4 128 byte RAM retention, RTCC
running from LFXO
— 3.86 — μA
128 byte RAM retention, CRYO-
TIMER running from ULFRCO
— 3.58 — μA
128 byte RAM retention, no RTCC — 3.58 — μA
Current consumption in
EM4S Shutoff mode
IEM4S no RAM retention, no RTCC — 3.04 — μA
Note:
1. DCDC Low Noise DCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=3.0 MHz (RCOBAND=0), ANASW=DVDD
2. CMU_HFXOCTRL_LOWPOWER=0
3. DCDC Low Noise CCM Mode = Light Drive (PFETCNT=NFETCNT=3), F=6.4 MHz (RCOBAND=4), ANASW=DVDD
4. DCDC Low Power Mode = Medium Drive (PFETCNT=NFETCNT=7), LPOSCDIV=1, LPBIAS=3, LPCILIMSEL=1, ANASW=DVDD
4.1.5.3 Current Consumption Using Radio
Unless otherwise indicated, typical conditions are: VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. TOP = 25 °C.
Minimum and maximum values in this table represent the worst conditions across supply voltage and process variation at TOP = 25 °C.
See Figure 5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 or
Figure 5.1 EFR32MG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter on page 64.
Table 4.7. Current Consumption Using Radio 3.3 V with DC-DC
Parameter Symbol Test Condition Min Typ Max Unit
Current consumption in re-
ceive mode, active packet
reception (MCU in EM1 @
38.4 MHz, peripheral clocks
disabled)
IRX 1 Mbit/s, 2GFSK, F = 2.4 GHz,
Radio clock prescaled by 4
— 8.7 — mA
802.15.4 receiving frame, F = 2.4
GHz, Radio clock prescaled by 3
— 9.8 — mA
Current consumption in
transmit mode (MCU in EM1
@ 38.4 MHz, peripheral
clocks disabled)
ITX F = 2.4 GHz, CW, 0 dBm output
power, Radio clock prescaled by 3
— 8.2 — mA
F = 2.4 GHz, CW, 3 dBm output
power
— 16.5 — mA
F = 2.4 GHz, CW, 8 dBm output
power
— 23.3 — mA
F = 2.4 GHz, CW, 10.5 dBm out-
put power
— 32.7 — mA
F = 2.4 GHz, CW, 16.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
— 83.9 — mA
F = 2.4 GHz, CW, 19.5 dBm out-
put power, PAVDD connected di-
rectly to external 3.3V supply
— 126.7 — mA
RFSENSE current consump-
tion
IRFSENSE — 51 — nA
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4.1.6 Wake up times
Table 4.8. Wake up times
Parameter Symbol Test Condition Min Typ Max Unit
Wake up from EM2 Deep
Sleep
tEM2_WU Code execution from flash — 10.7 — μs
Code execution from RAM — 3 — μs
Wakeup time from EM1
Sleep
tEM1_WU Executing from flash — 3 — AHB
Clocks
Executing from RAM — 3 — AHB
Clocks
Wake up from EM3 Stop tEM3_WU Executing from flash — 10.7 — μs
Executing from RAM — 3 — μs
Wake up from EM4H Hiber-
nate1
tEM4H_WU Executing from flash — 60 — μs
Wake up from EM4S Shut-
off1
tEM4S_WU — 290 — μs
Note:
1. Time from wakeup request until first instruction is executed. Wakeup results in device reset.
4.1.7 Brown Out Detector
Table 4.9. Brown Out Detector
Parameter Symbol Test Condition Min Typ Max Unit
DVDDBOD threshold VDVDDBOD DVDD rising — — 1.62 V
DVDD falling 1.35 — — V
DVDD BOD hysteresis VDVDDBOD_HYST — 24 — mV
DVDD response time tDVDDBOD_DELAY Supply drops at 0.1V/μs rate — 2.4 — μs
AVDD BOD threshold VAVDDBOD AVDD rising — — 1.85 V
AVDD falling 1.62 — — V
AVDD BOD hysteresis VAVDDBOD_HYST — 21 — mV
AVDD response time tAVDDBOD_DELAY Supply drops at 0.1V/μs rate — 2.4 — μs
EM4 BOD threshold VEM4DBOD AVDD rising — — 1.7 V
AVDD falling 1.45 — — V
EM4 BOD hysteresis VEM4BOD_HYST — 46 — mV
EM4 response time tEM4BOD_DELAY Supply drops at 0.1V/μs rate — 300 — μs
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4.1.8 Frequency Synthesizer Characteristics
Table 4.10. Frequency Synthesizer Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
RF Synthesizer Frequency
range
FRANGE_2400 2.4 GHz frequency range 2400 — 2483.5 MHz
LO tuning frequency resolu-
tion with 38.4 MHz crystal
FRES_2400 2400 - 2483.5 MHz — — 73 Hz
Maximum frequency devia-
tion with 38.4 MHz crystal
ΔFMAX_2400 — — 1677 kHz
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4.1.9 2.4 GHz RF Transceiver Characteristics
4.1.9.1 RF Transmitter General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.45 GHz. Test circuit according to
Figure 5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Fig-
ure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.11. RF Transmitter General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Maximum TX power1POUTMAX 19.5 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply2
— 19.5 — dBm
16.5 dBm-rated part numbers.
PAVDD connected directly to ex-
ternal 3.3V supply
— 16.5 — dBm
Minimum active TX Power POUTMIN CW -30 — dBm
Output power step size POUTSTEP -5 dBm< Output power < 0 dBm — 1 — dB
0 dBm < output power <
POUTMAX
— 0.5 — dB
Output power variation vs
supply at POUTMAX
POUTVAR_V 1.85 V < VVREGVDD < 3.3 V,
PAVDD connected directly to ex-
ternal supply, for output power >
10.5 dBm.
— 4.5 — dB
1.85 V < VVREGVDD < 3.3 V using
DC-DC converter
— 2.2 — dB
Output power variation vs
temperature at POUTMAX
POUTVAR_T From -40 to +85 °C, PAVDD con-
nected to DC-DC output
— 1.5 — dB
From -40 to +125 °C, PAVDD
connected to DC-DC output
— 2.2 — dB
From -40 to +85 °C, PAVDD con-
nected to external supply
— 1.5 — dB
From -40 to +125 °C, PAVDD
connected to external supply
— 3.4 — dB
Output power variation vs RF
frequency at POUTMAX
POUTVAR_F Over RF tuning frequency range — 0.4 — dB
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Note:
1. Supported transmit power levels are determined by the ordering part number (OPN). Transmit power ratings for all devices cov-
ered in this datasheet can be found in the Max TX Power column of 2. Ordering Information
2. For Bluetooth, the Maximum TX power on Channel 2456 is limited to +15 dBm to comply with In-band Spurious emissions.
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4.1.9.2 RF Receiver General Characteristics for the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according
to Figure 5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and
Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.12. RF Receiver General Characteristics for 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
RF tuning frequency range FRANGE 2400 — 2483.5 MHz
Receive mode maximum
spurious emission
SPURRX 30 MHz to 1 GHz — -57 — dBm
1 GHz to 12 GHz — -47 — dBm
Max spurious emissions dur-
ing active receive mode, per
FCC Part 15.109(a)
SPURRX_FCC 216 MHz to 960 MHz, Conducted
Measurement
— -55.2 — dBm
Above 960 MHz, Conducted
Measurement
— -47.2 — dBm
Level above which
RFSENSE will trigger1
RFSENSETRIG CW at 2.45 GHz — -24 — dBm
Level below which
RFSENSE will not trigger1
RFSENSETHRES — -50 — dBm
1% PER Sensitivity SENS2GFSK 2 Mbps 2GFSK signal2— -89.2 — dBm
0.1% BER Sensitivity 250 kbps 2GFSK signal — -99.1 — dBm
Note:
1. RFSENSE performance is only valid from 0 to 85 °C. RFSENSE should be disabled outside this temperature range.
2. Channel at 2420 MHz will have degraded sensitivity. Sensitivity could be as high as -83dBm on this channel.
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4.1.9.3 RF Transmitter Characteristics for Bluetooth Smart in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.44 GHz. Test circuit according to
Figure 5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Fig-
ure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.13. RF Transmitter Characteristics for Bluetooth Smart in the 2.4GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Transmit 6dB bandwidth TXBW — 740 — kHz
Power spectral density limit PSDLIMIT Per FCC part 15.247 at 10 dBm — -6.5 — dBm/
3kHz
Per FCC part 15.247 at 20 dBm — -2.6 — dBm/
3kHz
Per ETSI 300.328 at 10 dBm/1
MHz
— 10 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band
— 1.1 — MHz
In-band spurious emissions
at 10 dBm, with allowed ex-
ceptions1
SPURINB At ±2 MHz — -39.8 — dBm
At ±3 MHz — -42.1 — dBm
In-band spurious emissions
at 20 dBm, with allowed ex-
ceptions1 2
At ±2 MHz — — -20 dBm
At ±3 MHz — — -30 dBm
Emissions of harmonics out-
of-band, per FCC part
15.247
SPURHRM_FCC 2nd,3rd, 5, 6, 8, 9,10 harmonics;
continuous transmission of modu-
lated carrier
— -47 — dBm
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
tured in SPURHARM,FCC. Re-
stricted Bands
SPUROOB_FCC Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier3
— -47 — dBm
Spurious emissions out-of-
band, per FCC part 15.247,
excluding harmonics cap-
tured in SPURHARM,FCC.
Non Restricted Bands
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
— -26 — dBc
Spurious emissions out-of-
band; per ETSI 300.328
SPURETSI328 [2400-BW to 2400] MHz, [2483.5
to 2483.5+BW] MHz
— -16 — dBm
[2400-2BW to 2400-BW] MHz,
[2483.5+BW to 2483.5+2BW]
MHz per ETSI 300.328
— -26 — dBm
Spurious emissions per ETSI
EN300.440
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
— -60 — dBm
25-1000 MHz — -42 — dBm
1-12 GHz — -36 — dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Per Bluetooth Core_4.2, Section 3.2.2, exceptions are allowed in up to three bands of 1 MHz width, centered on a frequency
which is an integer multiple of 1 MHz. These exceptions shall have an absolute value of -20 dBm or less.
2. For 2456 MHz, a maximum output power of 15 dBm is used to achieve this value.
3. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.
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4.1.9.4 RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: TOP = 25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD.
RFVDD and PAVDD path is filtered using ferrites. Crystal frequency=38.4MHz. RF center frequency 2.440 GHz. Test circuit according
to Figure 5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and
Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.14. RF Receiver Characteristics for Bluetooth Smart in the 2.4GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 0.1% BER
SAT Signal is reference signal1. Packet
length is 20 bytes.
— 10 — dBm
Sensitivity, 0.1% BER2SENS Signal is reference signal1. Using
DC-DC converter
— -92.5 — dBm
With non-ideal signals as speci-
fied in RF-PHY.TS.4.2.2, section
4.6.1
— -92 — dBm
Signal to co-channel interfer-
er, 0.1% BER
C/ICC Desired signal 3 dB above refer-
ence sensitivity
— 8.3 — dB
N+1 adjacent channel (1
MHz) selectivity, 0.1% BER,
with allowable exceptions.
Desired is reference signal at
-67 dBm
C/I1+ Interferer is reference signal at +1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -3 — dB
N-1 adjacent channel (1
MHz) selectivity, 0.1% BER,
with allowable exceptions.
Desired is reference signal at
-67 dBm
C/I1- Interferer is reference signal at -1
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -0.5 — dB
Alternate (2 MHz) selectivity,
0.1% BER, with allowable
exceptions. Desired is refer-
ence signal at -67 dBm
C/I2Interferer is reference signal at ± 2
MHz offset. Desired frequency
2402 MHz ≤ Fc ≤ 2480 MHz
— -43 — dB
Alternate (3 MHz) selectivity,
0.1% BER, with allowable
exceptions. Desired is refer-
ence signal at -67 dBm
C/I3Interferer is reference signal at ±3
MHz offset. Desired frequency
2404 MHz ≤ Fc ≤ 2480 MHz
— -46.7 — dB
Selectivity to image frequen-
cy, 0.1% BER. Desired is ref-
erence signal at -67 dBm
C/IIM Interferer is reference signal at im-
age frequency with 1 MHz preci-
sion
— -38.7 — dB
Selectivity to image frequen-
cy +1 MHz, 0.1% BER. De-
sired is reference signal at
-67 dBm
C/IIM+1 Interferer is reference signal at im-
age frequency +1 MHz with 1
MHz precision
— -48.2 — dB
Blocking, 0.1% BER, Desired
is reference signal at -67
dBm. Interferer is CW in
OOB range.
BLOCKOOB Interferer frequency 30 MHz ≤ f ≤
2000 MHz
— -27 — dBm
Interferer frequency 2003 MHz ≤ f
≤ 2399 MHz
— -32 — dBm
Interferer frequency 2484 MHz ≤ f
≤ 2997 MHz
— -32 — dBm
Interferer frequency 3 GHz ≤ f ≤
12.75 GHz
— -27 — dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Intermodulation performance IM Per Core_4.1, Vol 6, Part A, Sec-
tion 4.4 with n = 3
— -25.8 — dBm
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 4 — — dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN — — -101 dBm
RSSI resolution RSSIRES Over RSSIMIN to RSSIMAX — — 0.5 dB
Note:
1. Reference signal is defined 2GFSK at -67 dBm, Modulation index = 0.5, BT = 0.5, Bit rate = 1 Mbps, desired data = PRBS9;
interferer data = PRBS15; frequency accuracy better than 1 ppm
2. Receive sensitivity on Bluetooth Smart channel 26 is -86 dBm
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4.1.9.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD
and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.45 GHz. Test circuit according to Figure
5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure
5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.15. RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Error vector magnitude (off-
set EVM), per
802.15.4-2011, not including
2415 MHz channel1
EVM Average across frequency. Signal
is DSSS-OQPSK reference pack-
et2
— 5.5 — % rms
Power spectral density limit PSDLIMIT Relative, at carrier ±3.5 MHz — -26 — dBc
Absolute, at carrier ±3.5 MHz3— -36 — dBm
Per FCC part 15.247 — -4.2 — dBm/
3kHz
Output power level which meets
10dBm/MHz ETSI 300.328 speci-
fication
— 12 — dBm
Occupied channel bandwidth
per ETSI EN300.328
OCPETSI328 99% BW at highest and lowest
channels in band
— 2.25 — MHz
Spurious emissions of har-
monics in restricted bands
per FCC Part 15.205/15.209,
Emissions taken at
Pout_Max power level of
19.5 dBm, PAVDD connec-
ted to external 3.3 V supply,
Test Frequency is 2450 MHz
SPURHRM_FCC_
R
Continuous transmission of modu-
lated carrier
— -45.8 — dBm
Spurious emissions of har-
monics in harmonics in non-
restricted bands per FCC
Part 15.247/15.35, Emis-
sions taken at Pout_Max
power level of 19.5 dBm,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency is 2450 MHz
SPURHRM_FCC_
NRR
— -26 — dBc
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Parameter Symbol Test Condition Min Typ Max Unit
Spurious emissions out-of-
band in restricted bands
(30-88 MHz), per FCC part
15.205/15.209, Emissions
taken at Pout_Max power
level of 19.5 dBm, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
SPUROOB_FCC_
R
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier4
— -52 — dBm
Spurious emissions out-of-
band in restricted bands
(88-216 MHz), per FCC part
15.205/15.209, Emissions
taken at Pout_Max power
level of 19.5 dBm, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
— -62 — dBm
Spurious emissions out-of-
band in restricted bands
(216-960 MHz), per FCC
part 15.205/15.209, Emis-
sions taken at Pout_Max
power level of 19.5 dBm,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
— -57 — dBm
Spurious emissions out-of-
band in restricted bands
(>960 MHz), per FCC part
15.205/15.209, Emissions
taken at Pout_Max power
level of 19.5 dBm, PAVDD
connected to external 3.3 V
supply, Test Frequency =
2450 MHz
— -48 — dBm
Spurious emissions out-of-
band in non-restricted bands
per FCC Part 15.247, Emis-
sions taken at Pout_Max
power level of 19.5 dBm,
PAVDD connected to exter-
nal 3.3 V supply, Test Fre-
quency = 2450 MHz
SPUROOB_FCC_
NR
Above 2.483 GHz or below 2.4
GHz; continuous transmission of
modulated carrier
— -26 — dBc
Spurious emissions out-of-
band; per ETSI 300.3285
SPURETSI328 [2400-BW to 2400], [2483.5 to
2483.5+BW];
— -16 — dBm
[2400-2BW to 2400-BW],
[2483.5+BW to 2483.5+2BW]; per
ETSI 300.328
— -26 — dBm
Spurious emissions per ETSI
EN300.4405
SPURETSI440 47-74 MHz,87.5-108 MHz,
174-230 MHz, 470-862 MHz
— -60 — dBm
25-1000 MHz, excluding above
frequencies
— -42 — dBm
1G-14G — -36 — dBm
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. Typical EVM for the 2415 MHz channel is 7.9%
2. Reference packet is defined as 20 octet PSDU, modulated according to 802.15.4-2011 DSSS-OQPSK in the 2.4GHz band, with
pseudo-random packet data content
3. For 2415 MHz, a maximum duty cycle of 50% is used to achieve this value.
4. For 2480 MHz, a maximum duty cycle of 20% is used to achieve this value.
5. Specified at maximum power output level of 10 dBm
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4.1.9.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band
Unless otherwise indicated, typical conditions are: T=25 °C,VREGVDD = AVDD = IOVDD = 3.3 V, DVDD = RFVDD = PAVDD. RFVDD
and PAVDD path is filtered using ferrites. Crystal frequency=38.4 MHz. RF center frequency 2.445 GHz. Test circuit according to Figure
5.2 EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC) on page 64 and Figure
5.4 Typical 2.4 GHz RF impedance-matching network circuits on page 65.
Table 4.16. RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
Parameter Symbol Test Condition Min Typ Max Unit
Max usable receiver input
level, 1% PER
SAT Signal is reference signal1. Packet
length is 20 octets.
— 10 — dBm
Sensitivity, 1% PER2SENS Signal is reference signal. Packet
length is 20 octets. Using DC-DC
converter.
— -99 — dBm
Signal is reference signal. Packet
length is 20 octets. Without DC-
DC converter.
— -99 — dBm
Co-channel interferer rejec-
tion, 1% PER
CCR Desired signal 10 dB above sensi-
tivity limit
— -2.6 — dB
High-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level3
ACR+1 Interferer is reference signal at +1
channel-spacing.
— 33.75 — dB
Interferer is filtered reference sig-
nal4 at +1 channel-spacing.
— 52.2 — dB
Interferer is CW at +1 channel-
spacing.5
— 58.6 — dB
Low-side adjacent channel
rejection, 1% PER. Desired
is reference signal at 3dB
above reference sensitivity
level3
ACR-1 Interferer is reference signal at -1
channel-spacing.
— 35 — dB
Interferer is filtered reference sig-
nal4 at -1 channel-spacing.
— 54.7 — dB
Interferer is CW at -1 channel-
spacing.
— 60.1 — dB
Alternate channel rejection,
1% PER. Desired is refer-
ence signal at 3dB above
reference sensitivity level3
ACR2Interferer is reference signal at ±2
channel-spacing
— 45.9 — dB
Interferer is filtered reference sig-
nal4 at ±2 channel-spacing
— 56.8 — dB
Interferer is CW at ±2 channel-
spacing
— 65.5 — dB
Image rejection , 1% PER,
Desired is reference signal at
3dB above reference sensi-
tivity level3
IR Interferer is CW in image band5— 49.3 — dB
Blocking rejection of all other
channels. 1% PER, Desired
is reference signal at 3dB
above reference sensitivity
level3. Interferer is reference
signal.
BLOCK Interferer frequency < Desired fre-
quency - 3 channel-spacing
— 57.2 — dB
Interferer frequency > Desired fre-
quency + 3 channel-spacing
— 57.9 — dB
Blocking rejection of 802.11g
signal centered at +12MHz
or -13MHz
BLOCK80211G Desired is reference signal at 6dB
above reference sensitivity level3
— 51.6 — dB
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Parameter Symbol Test Condition Min Typ Max Unit
Upper limit of input power
range over which RSSI reso-
lution is maintained
RSSIMAX 5 — — dBm
Lower limit of input power
range over which RSSI reso-
lution is maintained
RSSIMIN — — -98 dBm
RSSI resolution RSSIRES over RSSIMIN to RSSIMAX — 0.25 — dB
RSSI accuracy in the linear
region as defined by
802.15.4-2003
RSSILIN — ±1 — dB
Note:
1. Reference signal is defined as O-QPSK DSSS per 802.15.4, Frequency range = 2400-2483.5 MHz, Symbol rate = 62.5 ksym-
bols/s
2. Receive sensitivity on 802.15.4 channel 14 is -98 dBm
3. Reference sensitivity level is -85 dBm
4. Filter is characterized as a symmetric bandpass centered on the adjacent channel having a 3dB bandwidth of 4.6 MHz and stop-
band rejection better than 26 dB beyond 3.15 MHz from the adjacent carrier.
5. Due to low-IF frequency, there is some overlap of adjacent channel and image channel bands. Adjacent channel CW blocker
tests place the Interferer center frequency at the Desired frequency ±5 MHz on the channel raster, whereas the image rejection
test places the CW interferer near the image frequency of the Desired signal carrier, regardless of the channel raster.
4.1.10 Modem Features
Table 4.17. Modem Features
Parameter Symbol Test Condition Min Typ Max Unit
Receive Bandwidth RXBandwidth Configurable range with 38.4 MHz
crystal
0.1 — 2530 kHz
IF Frequency IFFreq Configurable range with 38.4 MHz
crystal. Selected steps available.
150 — 1371 kHz
DSSS symbol length DSSSRange Configurable in steps of 1 chip 2 — 32 chips
DSSS Bits per symbol DSSSBitPerSym Configurable 1 — 4 bits/
symbol
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4.1.11 Oscillators
4.1.11.1 LFXO
Table 4.18. LFXO
Parameter Symbol Test Condition Min Typ Max Unit
Crystal frequency fLFXO — 32.768 — kHz
Supported crystal equivalent
series resistance (ESR)
ESRLFXO — — 70 kΩ
Supported range of crystal
load capacitance 1
CLFXO_CL 6 — 18 pF
On-chip tuning cap range 2CLFXO_T On each of LFXTAL_N and
LFXTAL_P pins
8 — 40 pF
On-chip tuning cap step size SSLFXO — 0.25 — pF
Current consumption after
startup 3
ILFXO ESR = 70 kΩ, CL = 7 pF, GAIN4 =
3, AGC4 = 1
— 273 — nA
Start- up time tLFXO ESR=70 kΩ, CL=7 pF, GAIN4 =2 — 308 — ms
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CLFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
3. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register
4. In CMU_LFXOCTRL register
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4.1.11.2 HFXO
Table 4.19. HFXO
Parameter Symbol Test Condition Min Typ Max Unit
Crystal Frequency fHFXO 38 38.4 40 MHz
Supported crystal equivalent
series resistance (ESR)
ESRHFXO Crystal frequency 38.4 MHz — — 60 Ω
Supported range of crystal
load capacitance 1
CHFXO_CL 6 — 12 pF
On-chip tuning cap range 2CHFXO_T On each of HFXTAL_N and
HFXTAL_P pins
9 20 25 pF
On-chip tuning capacitance
step
SSHFXO — 0.04 — pF
Startup time tHFXO 38.4 MHz, ESR = 50 Ω, CL = 10
pF
— 300 — μs
Frequency Tolerance for the
crystal
FTHFXO 38.4 MHz, ESR = 50 Ω, CL = 10
pF
-40 — 40 ppm
Note:
1. Total load capacitance as seen by the crystal
2. The effective load capacitance seen by the crystal will be CHFXO_T /2. This is because each XTAL pin has a tuning cap and the
two caps will be seen in series by the crystal.
4.1.11.3 LFRCO
Table 4.20. LFRCO
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency fLFRCO ENVREF = 1 in
CMU_LFRCOCTRL, TAMB ≤ 85
°C
30.474 32.768 34.243 kHz
ENVREF = 1 in
CMU_LFRCOCTRL, TAMB > 85
°C
30.474 — 39.7 kHz
ENVREF = 0 in
CMU_LFRCOCTRL
30.474 32.768 33.915 kHz
Startup time tLFRCO — 500 — μs
Current consumption 1ILFRCO ENVREF = 1 in
CMU_LFRCOCTRL
— 342 — nA
ENVREF = 0 in
CMU_LFRCOCTRL
— 494 — nA
Note:
1. Block is supplied by AVDD if ANASW = 0, or DVDD if ANASW=1 in EMU_PWRCTRL register
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4.1.11.4 HFRCO and AUXHFRCO
Table 4.21. HFRCO and AUXHFRCO
Parameter Symbol Test Condition Min Typ Max Unit
Frequency Accuracy fHFRCO Any frequency band, across sup-
ply voltage and temperature
-2.5 — 2.5 %
Start-up time tHFRCO fHFRCO ≥ 19 MHz — 300 — ns
4 < fHFRCO < 19 MHz — 1 — μs
fHFRCO ≤ 4 MHz — 2.5 — μs
Current consumption on all
supplies
IHFRCO fHFRCO = 38 MHz — 204 228 μA
fHFRCO = 32 MHz — 171 190 μA
fHFRCO = 26 MHz — 147 164 μA
fHFRCO = 19 MHz — 126 138 μA
fHFRCO = 16 MHz — 110 120 μA
fHFRCO = 13 MHz — 100 110 μA
fHFRCO = 7 MHz — 81 91 μA
fHFRCO = 4 MHz — 33 35 μA
fHFRCO = 2 MHz — 31 35 μA
fHFRCO = 1 MHz — 30 35 μA
Step size SSHFRCO Coarse (% of period) — 0.8 — %
Fine (% of period) — 0.1 — %
Period Jitter PJHFRCO — 0.2 — % RMS
4.1.11.5 ULFRCO
Table 4.22. ULFRCO
Parameter Symbol Test Condition Min Typ Max Unit
Oscillation frequency fULFRCO 0.95 1 1.07 kHz
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4.1.12 Primary Flash Memory Characteristics
Table 4.23. Primary Flash Memory Characteristics1
Parameter Symbol Test Condition Min Typ Max Unit
Flash erase cycles before
failure
ECFLASH 10000 — — cycles
Flash data retention RETFLASH TAMB ≤ 85 °C 10 — — years
TAMB ≤ 125 °C 10 — — years
Word (32-bit) programming
time
tW_PROG 20 26 40 μs
Page erase time tPERASE 20 27 40 ms
Mass erase time tMERASE 20 27 40 ms
Device erase time2tDERASE TAMB ≤ 85 °C — 60 74 ms
TAMB ≤ 125 °C — 60 78 ms
Page erase current3IERASE — — 3 mA
Mass or Device erase cur-
rent3
— — 5 mA
Write current3IWRITE — — 3 mA
Note:
1. Flash data retention information is published in the Quarterly Quality and Reliability Report.
2. Device erase is issued over the AAP interface and erases all flash, SRAM, the Lock Bit (LB) page, and the User data page Lock
Word (ULW)
3. Measured at 25°C
4.1.13 Serial Flash Memory Characteristics
Table 4.24. Serial Flash Memory Characteristics
Parameter Symbol Test Condition Min Typ Max Unit
Serial flash erase cycles be-
fore failure
ECSFLASH 100000 — — cycles
Serial flash data retention RETSFLASH 20 — — years
Page Program Time tPPROG 1 to 256 Bytes — 0.5 0.8 ms
Erase Time tERASE 4 kByte Sector — 70 300 ms
32 kByte Block — 130 500 ms
64 kByte Block — 200 1000 ms
Full Erase — 1.5 3 s
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4.1.14 GPIO
Table 4.25. GPIO
Parameter Symbol Test Condition Min Typ Max Unit
Input low voltage VIOIL — — IOVDD*0.3 V
Input high voltage VIOIH IOVDD*0.7 — — V
Output high voltage relative
to IOVDD
VIOOH Sourcing 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = WEAK
IOVDD*0.8 — — V
Sourcing 1.2 mA, IOVDD ≥ 2.3 V,
DRIVESTRENGTH1 = WEAK
IOVDD*0.6 — — V
Sourcing 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
IOVDD*0.8 — — V
Sourcing 8 mA, IOVDD ≥ 2.3 V,
DRIVESTRENGTH1 = STRONG
IOVDD*0.6 — — V
Output low voltage relative to
IOVDD
VIOOL Sinking 3 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = WEAK
— — IOVDD*0.2 V
Sinking 1.2 mA, IOVDD ≥ 2.3 V,
DRIVESTRENGTH1 = WEAK
— — IOVDD*0.4 V
Sinking 20 mA, IOVDD ≥ 3 V,
DRIVESTRENGTH1 = STRONG
— — IOVDD*0.2 V
Sinking 8 mA, IOVDD ≥ 2.3 V,
DRIVESTRENGTH1 = STRONG
— — IOVDD*0.4 V
Input leakage current IIOLEAK All GPIO except LFXO pins, GPIO
≤ IOVDD, Tamb ≤ 85 °C
— 0.1 30 nA
LFXO Pins, GPIO ≤ IOVDD, Tamb
≤ 85 °C
— 0.1 50 nA
All GPIO except LFXO pins, GPIO
≤ IOVDD, TAMB > 85 °C
— — 110 nA
LFXO Pins, GPIO ≤ IOVDD, TAMB
> 85 °C
— — 250 nA
Input leakage current on
5VTOL pads above IOVDD
I5VTOLLEAK IOVDD < GPIO ≤ IOVDD + 2 V — 3.3 15 μA
I/O pin pull-up resistor RPU 30 43 65 kΩ
I/O pin pull-down resistor RPD 30 43 65 kΩ
Pulse width of pulses re-
moved by the glitch suppres-
sion filter
tIOGLITCH 20 25 35 ns
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Parameter Symbol Test Condition Min Typ Max Unit
Output fall time, From 70%
to 30% of VIO
tIOOF CL = 50 pF,
DRIVESTRENGTH1 = STRONG,
SLEWRATE1 = 0x6
— 1.8 — ns
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
— 4.5 — ns
Output rise time, From 30%
to 70% of VIO
tIOOR CL = 50 pF,
DRIVESTRENGTH1 = STRONG,
SLEWRATE = 0x61
— 2.2 — ns
CL = 50 pF,
DRIVESTRENGTH1 = WEAK,
SLEWRATE1 = 0x6
— 7.4 — ns
Note:
1. In GPIO_Pn_CTRL register
4.1.15 VMON
Table 4.26. VMON
Parameter Symbol Test Condition Min Typ Max Unit
VMON Supply Current IVMON In EM0 or EM1, 1 supply moni-
tored
— 5.8 8.26 μA
In EM0 or EM1, 4 supplies moni-
tored
— 11.8 16.8 μA
In EM2, EM3 or EM4, 1 supply
monitored
— 62 — nA
In EM2, EM3 or EM4, 4 supplies
monitored
— 99 — nA
VMON Loading of Monitored
Supply
ISENSE In EM0 or EM1 — 2 — μA
In EM2, EM3 or EM4 — 2 — nA
Threshold range VVMON_RANGE 1.62 — 3.4 V
Threshold step size NVMON_STESP Coarse — 200 — mV
Fine — 20 — mV
Response time tVMON_RES Supply drops at 1V/μs rate — 460 — ns
Hysteresis VVMON_HYST — 26 — mV
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4.1.16 ADC
Table 4.27. ADC
Parameter Symbol Test Condition Min Typ Max Unit
Resolution VRESOLUTION 6 — 12 Bits
Input voltage range VADCIN Single ended 0 — 2*VREF V
Differential -VREF — VREF V
Input range of external refer-
ence voltage, single ended
and differential
VADCREFIN_P 1 — VAVDD V
Power supply rejection1PSRRADC At DC — 80 — dB
Analog input common mode
rejection ratio
CMRRADC At DC — 80 — dB
Current from all supplies, us-
ing internal reference buffer.
Continous operation. WAR-
MUPMODE2 = KEEPADC-
WARM
IADC_CONTI-
NOUS_LP
1 Msps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 1
3
— 301 350 μA
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 1 3
— 149 — μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG = 15, GPBIASACC =
1 3
— 91 — μA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE2 = NORMAL
IADC_NORMAL_LP 35 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 1
3
— 51 — μA
5 ksps / 16 MHz ADCCLK
BIASPROG = 0, GPBIASACC = 1
3
— 9 — μA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation.
AWARMUPMODE2 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
IADC_STAND-
BY_LP
125 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 1
3
— 117 — μA
35 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 1
3
— 79 — μA
Current from all supplies, us-
ing internal reference buffer.
Continous operation. WAR-
MUPMODE2 = KEEPADC-
WARM
IADC_CONTI-
NOUS_HP
1 Msps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 0
3
— 345 — μA
250 ksps / 4 MHz ADCCLK, BIA-
SPROG = 6, GPBIASACC = 0 3
— 191 — μA
62.5 ksps / 1 MHz ADCCLK,
BIASPROG = 15, GPBIASACC =
0 3
— 132 — μA
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Parameter Symbol Test Condition Min Typ Max Unit
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation. WAR-
MUPMODE2 = NORMAL
IADC_NORMAL_HP 35 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 0
3
— 102 — μA
5 ksps / 16 MHz ADCCLK
BIASPROG = 0, GPBIASACC = 0
3
— 17 — μA
Current from all supplies, us-
ing internal reference buffer.
Duty-cycled operation.
AWARMUPMODE2 = KEEP-
INSTANDBY or KEEPIN-
SLOWACC
IADC_STAND-
BY_HP
125 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 0
3
— 162 — μA
35 ksps / 16 MHz ADCCLK,
BIASPROG = 0, GPBIASACC = 0
3
— 123 — μA
Current from HFPERCLK IADC_CLK HFPERCLK = 16 MHz — 140 — μA
ADC Clock Frequency fADCCLK — — 16 MHz
Throughput rate fADCRATE — — 1 Msps
Conversion time4tADCCONV 6 bit — 7 — cycles
8 bit — 9 — cycles
12 bit — 13 — cycles
Startup time of reference
generator and ADC core
tADCSTART WARMUPMODE2 = NORMAL — — 5 μs
WARMUPMODE2 = KEEPIN-
STANDBY
— — 2 μs
WARMUPMODE2 = KEEPINSLO-
WACC
— — 1 μs
SNDR at 1Msps and fin =
10kHz
SNDRADC Internal reference, 2.5 V full-scale,
differential (-1.25, 1.25)
58 67 — dB
vrefp_in = 1.25 V direct mode with
2.5 V full-scale, differential
— 68 — dB
Spurious-Free Dynamic
Range (SFDR)
SFDRADC 1 MSamples/s, 10 kHz full-scale
sine wave
— 75 — dB
Input referred ADC noise,
rms
VREF_NOISE Including quantization noise and
distortion
— 380 — μV
Offset Error VADCOFFSETERR -3 0.25 3 LSB
Gain error in ADC VADC_GAIN Using internal reference — -0.2 5 %
Using external reference — -1 — %
Differential non-linearity
(DNL)
DNLADC 12 bit resolution -1 — 2 LSB
Integral non-linearity (INL),
End point method
INLADC 12 bit resolution -6 — 6 LSB
Temperature Sensor Slope VTS_SLOPE — -1.84 — mV/°C
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Parameter Symbol Test Condition Min Typ Max Unit
Note:
1. PSRR is referenced to AVDD when ANASW=0 and to DVDD when ANASW=1 in EMU_PWRCTRL
2. In ADCn_CNTL register
3. In ADCn_BIASPROG register
4. Derived from ADCCLK
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4.1.17 IDAC
Table 4.28. IDAC
Parameter Symbol Test Condition Min Typ Max Unit
Number of Ranges NIDAC_RANGES — 4 — -
Output Current IIDAC_OUT RANGSEL1 = RANGE0 0.05 — 1.6 μA
RANGSEL1 = RANGE1 1.6 — 4.7 μA
RANGSEL1 = RANGE2 0.5 — 16 μA
RANGSEL1 = RANGE3 2 — 64 μA
Linear steps within each
range
NIDAC_STEPS — 32 —
Step size SSIDAC RANGSEL1 = RANGE0 — 50 — nA
RANGSEL1 = RANGE1 — 100 — nA
RANGSEL1 = RANGE2 — 500 — nA
RANGSEL1 = RANGE3 — 2 — μA
Total Accuracy, STEPSEL1 =
0x10
ACCIDAC EM0 or EM1, AVDD=3.3 V, T = 25
°C
-2 — 2 %
EM0 or EM1 -18 — 22 %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE0,
AVDD=3.3 V, T = 25 °C
— -2 — %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE1,
AVDD=3.3 V, T = 25 °C
— -1.7 — %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE2,
AVDD=3.3 V, T = 25 °C
— -0.8 — %
EM2 or EM3, Source mode,
RANGSEL1 = RANGE3,
AVDD=3.3 V, T = 25 °C
— -0.5 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE0, AVDD=3.3 V, T
= 25 °C
— -0.7 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE1, AVDD=3.3 V, T
= 25 °C
— -0.6 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE2, AVDD=3.3 V, T
= 25 °C
— -0.5 — %
EM2 or EM3, Sink mode, RANG-
SEL1 = RANGE3, AVDD=3.3 V, T
= 25 °C
— -0.5 — %
Start up time tIDAC_SU Output within 1% of steady state
value
— 5 — μs
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Parameter Symbol Test Condition Min Typ Max Unit
Settling time, (output settled
within 1% of steady state val-
ue)
tIDAC_SETTLE Range setting is changed — 5 — μs
Step value is changed — 1 — μs
Current consumption in EM0
or EM1 2
IIDAC Source mode, excluding output
current
— 8.9 13 μA
Sink mode, excluding output cur-
rent
— 12 16 μA
Current consumption in EM2
or EM32
Source mode, excluding output
current, duty cycle mode, T = 25
°C
— 1.04 — μA
Sink mode, excluding output cur-
rent, duty cycle mode, T = 25 °C
— 1.08 — μA
Source mode, excluding output
current, duty cycle mode, T ≥ 85
°C
— 8.9 — μA
Sink mode, excluding output cur-
rent, duty cycle mode, T ≥ 85 °C
— 12 — μA
Output voltage compliance in
source mode, source current
change relative to current
sourced at 0 V
ICOMP_SRC RANGESEL1=0, output voltage =
min(VIOVDD, VAVDD2-100 mv)
— 0.04 — %
RANGESEL1=1, output voltage =
min(VIOVDD, VAVDD2-100 mV)
— 0.02 — %
RANGESEL1=2, output voltage =
min(VIOVDD, VAVDD2-150 mV)
— 0.02 — %
RANGESEL1=3, output voltage =
min(VIOVDD, VAVDD2-250 mV)
— 0.02 — %
Output voltage compliance in
sink mode, sink current
change relative to current
sunk at IOVDD
ICOMP_SINK RANGESEL1=0, output voltage =
100 mV
— 0.18 — %
RANGESEL1=1, output voltage =
100 mV
— 0.12 — %
RANGESEL1=2, output voltage =
150 mV
— 0.08 — %
RANGESEL1=3, output voltage =
250 mV
— 0.02 — %
Note:
1. In IDAC_CURPROG register
2. The IDAC is supplied by either AVDD, DVDD, or IOVDD based on the setting of ANASW in the EMU_PWRCTRL register and
PWRSEL in the IDAC_CTRL register. Setting PWRSEL to 1 selects IOVDD. With PWRSEL cleared to 0, ANASW selects be-
tween AVDD (0) and DVDD (1).
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4.1.18 Analog Comparator (ACMP)
Table 4.29. ACMP
Parameter Symbol Test Condition Min Typ Max Unit
Input voltage range VACMPIN ACMPVDD =
ACMPn_CTRL_PWRSEL 1
0 — VACMPVDD V
Supply Voltage VACMPVDD BIASPROG2 ≤ 0x10 or FULL-
BIAS2 = 0
1.85 — VVREGVDD_
MAX
V
0x10 < BIASPROG2 ≤ 0x20 and
FULLBIAS2 = 1
2.1 — VVREGVDD_
MAX
V
Active current not including
voltage reference
IACMP BIASPROG2 = 1, FULLBIAS2 = 0 — 50 — nA
BIASPROG2 = 0x10, FULLBIAS2
= 0
— 306 — nA
BIASPROG2 = 0x20, FULLBIAS2
= 1
— 74 95 μA
Current consumption of inter-
nal voltage reference
IACMPREF VLP selected as input using 2.5 V
Reference / 4 (0.625 V)
— 50 — nA
VLP selected as input using VDD — 20 — nA
VBDIV selected as input using
1.25 V reference / 1
— 4.1 — μA
VADIV selected as input using
VDD/1
— 2.4 — μA
Hysteresis (VCM = 1.25 V,
BIASPROG2 = 0x10, FULL-
BIAS2 = 1)
VACMPHYST HYSTSEL3 = HYST0 -1.75 0 1.75 mV
HYSTSEL3 = HYST1 10 18 26 mV
HYSTSEL3 = HYST2 21 32 46 mV
HYSTSEL3 = HYST3 27 44 63 mV
HYSTSEL3 = HYST4 32 55 80 mV
HYSTSEL3 = HYST5 38 65 100 mV
HYSTSEL3 = HYST6 43 77 121 mV
HYSTSEL3 = HYST7 47 86 148 mV
HYSTSEL3 = HYST8 -4 0 4 mV
HYSTSEL3 = HYST9 -27 -18 -10 mV
HYSTSEL3 = HYST10 -47 -32 -18 mV
HYSTSEL3 = HYST11 -64 -43 -27 mV
HYSTSEL3 = HYST12 -78 -54 -32 mV
HYSTSEL3 = HYST13 -93 -64 -37 mV
HYSTSEL3 = HYST14 -113 -74 -42 mV
HYSTSEL3 = HYST15 -135 -85 -47 mV
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Parameter Symbol Test Condition Min Typ Max Unit
Comparator delay4tACMPDELAY BIASPROG2 = 1, FULLBIAS2 = 0 — 30 — μs
BIASPROG2 = 0x10, FULLBIAS2
= 0
— 3.7 — μs
BIASPROG2 = 0x20, FULLBIAS2
= 1
— 35 — ns
Offset voltage VACMPOFFSET BIASPROG2 =0x10, FULLBIAS2
= 1
-35 — 35 mV
Reference Voltage VACMPREF Internal 1.25 V reference 1 1.25 1.47 V
Internal 2.5 V reference 2 2.5 2.8 V
Capacitive Sense Internal
Resistance
RCSRES CSRESSEL5 = 0 — inf — kΩ
CSRESSEL5 = 1 — 15 — kΩ
CSRESSEL5 = 2 — 27 — kΩ
CSRESSEL5 = 3 — 39 — kΩ
CSRESSEL5 = 4 — 51 — kΩ
CSRESSEL5 = 5 — 102 — kΩ
CSRESSEL5 = 6 — 164 — kΩ
CSRESSEL5 = 7 — 239 — kΩ
Note:
1. ACMPVDD is a supply chosen by the setting in ACMPn_CTRL_PWRSEL and may be IOVDD, AVDD or DVDD
2. In ACMPn_CTRL register
3. In ACMPn_HYSTERESIS register
4. ±100 mV differential drive
5. In ACMPn_INPUTSEL register
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given as:
IACMPTOTAL = IACMP + IACMPREF
IACMPREF is zero if an external voltage reference is used.
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4.1.19 I2C
I2C Standard-mode (Sm)
Table 4.30. I2C Standard-mode (Sm)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 — 100 kHz
SCL clock low time tLOW 4.7 — — μs
SCL clock high time tHIGH 4 — — μs
SDA set-up time tSU,DAT 250 — — ns
SDA hold time3tHD,DAT 100 — 3450 ns
Repeated START condition
set-up time
tSU,STA 4.7 — — μs
(Repeated) START condition
hold time
tHD,STA 4 — — μs
STOP condition set-up time tSU,STO 4 — — μs
Bus free time between a
STOP and START condition
tBUF 4.7 — — μs
Note:
1. For CLHR set to 0 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Standard-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW)
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I2C Fast-mode (Fm)
Table 4.31. I2C Fast-mode (Fm)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 — 400 kHz
SCL clock low time tLOW 1.3 — — μs
SCL clock high time tHIGH 0.6 — — μs
SDA set-up time tSU,DAT 100 — — ns
SDA hold time3tHD,DAT 100 — 900 ns
Repeated START condition
set-up time
tSU,STA 0.6 — — μs
(Repeated) START condition
hold time
tHD,STA 0.6 — — μs
STOP condition set-up time tSU,STO 0.6 — — μs
Bus free time between a
STOP and START condition
tBUF 1.3 — — μs
Note:
1. For CLHR set to 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode, refer to the I2C chapter in the reference manual
3. The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW)
I2C Fast-mode Plus (Fm+)
Table 4.32. I2C Fast-mode Plus (Fm+)1
Parameter Symbol Test Condition Min Typ Max Unit
SCL clock frequency2fSCL 0 — 1000 kHz
SCL clock low time tLOW 0.5 — — μs
SCL clock high time tHIGH 0.26 — — μs
SDA set-up time tSU,DAT 50 — — ns
SDA hold time tHD,DAT 100 — — ns
Repeated START condition
set-up time
tSU,STA 0.26 — — μs
(Repeated) START condition
hold time
tHD,STA 0.26 — — μs
STOP condition set-up time tSU,STO 0.26 — — μs
Bus free time between a
STOP and START condition
tBUF 0.5 — — μs
Note:
1. For CLHR set to 0 or 1 in the I2Cn_CTRL register
2. For the minimum HFPERCLK frequency required in Fast-mode Plus, refer to the I2C chapter in the reference manual
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4.1.20 USART SPI
SPI Master Timing
Table 4.33. SPI Master Timing
Parameter Symbol Test Condition Min Typ Max Unit
SCLK period 1 2tSCLK 2 *
tHFPERCLK
— — ns
CS to MOSI 1 2tCS_MO 0 — 8 ns
SCLK to MOSI 1 2tSCLK_MO 3 — 20 ns
MISO setup time 1 2tSU_MI IOVDD = 2.3 V 56 — — ns
IOVDD = 3.0 V 37 — — ns
MISO hold time 1 2tH_MI 6 — — ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD)
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_MO
tH_MI
tSU_MI
tSCKL_MO
tSCLK
SCLK
CLKPOL = 1
Figure 4.1. SPI Master Timing Diagram
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SPI Slave Timing
Table 4.34. SPI Slave Timing
Parameter Symbol Test Condition Min Typ Max Unit
SCKL period 1 2tSCLK_sl 2 *
tHFPERCLK
— — ns
SCLK high period1 2tSCLK_hi 3 *
tHFPERCLK
— — ns
SCLK low period 1 2tSCLK_lo 3 *
tHFPERCLK
— — ns
CS active to MISO 1 2tCS_ACT_MI 4 — 50 ns
CS disable to MISO 1 2tCS_DIS_MI 4 — 50 ns
MOSI setup time 1 2tSU_MO 4 — — ns
MOSI hold time 1 2tH_MO 3 + 2 *
tHFPERCLK
— — ns
SCLK to MISO 1 2tSCLK_MI 16 +
tHFPERCLK
— 66 + 2 *
tHFPERCLK
ns
Note:
1. Applies for both CLKPHA = 0 and CLKPHA = 1 (figure only shows CLKPHA = 0)
2. Measurement done with 8 pF output loading at 10% and 90% of VDD (figure shows 50% of VDD)
CS
SCLK
CLKPOL = 0
MOSI
MISO
tCS_ACT_MI
tSCLK_HI
tSCLK
tSU_MO
tH_MO
tSCLK_MI
tCS_DIS_MI
tSCLK_LO
SCLK
CLKPOL = 1
Figure 4.2. SPI Slave Timing Diagram
4.2 Typical Performance Curves
Typical performance curves indicate typical characterized performance under the stated conditions.
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4.2.1 Supply Current
Figure 4.3. EM0 Active Mode Typical Supply Current
Figure 4.4. EM1 Sleep Mode Typical Supply Current
Typical supply current for EM2, EM3 and EM4H using standard software libraries from Silicon Laboratories.
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Figure 4.5. EM2, EM3, EM4H and EM4S Typical Supply Current
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4.2.2 DC-DC Converter
Default test conditions: CCM mode, LDCDC = 4.7 μH, CDCDC = 1.0 μF, VDCDC_I = 3.3 V, VDCDC_O = 1.8 V, FDCDC_LN = 7 MHz
Figure 4.6. DC-DC Converter Typical Performance Characteristics
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100μs/div 10μs/div
2V/div
offset:1.8V
50mV/div
offset:1.8V
100mA
1mA
ILOAD
60mV/div
offset:1.8V
VSW
DVDD
DVDD
Load Step Response in LN (CCM) mode
(Heavy Drive)
LN (CCM) and LP mode transition (load: 5mA)
Figure 4.7. DC-DC Converter Transition Waveforms
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4.2.3 Internal Oscillators
Figure 4.8. HFRCO and AUXHFRCO Typical Performance at 38 MHz
Figure 4.9. HFRCO and AUXHFRCO Typical Performance at 32 MHz
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Figure 4.10. HFRCO and AUXHFRCO Typical Performance at 26 MHz
Figure 4.11. HFRCO and AUXHFRCO Typical Performance at 19 MHz
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Figure 4.12. HFRCO and AUXHFRCO Typical Performance at 16 MHz
Figure 4.13. HFRCO and AUXHFRCO Typical Performance at 13 MHz
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Figure 4.14. HFRCO and AUXHFRCO Typical Performance at 7 MHz
Figure 4.15. HFRCO and AUXHFRCO Typical Performance at 4 MHz
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Figure 4.16. HFRCO and AUXHFRCO Typical Performance at 2 MHz
Figure 4.17. HFRCO and AUXHFRCO Typical Performance at 1 MHz
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Figure 4.18. LFRCO Typical Performance at 32.768 kHz
Figure 4.19. ULFRCO Typical Performance at 1 kHz
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4.2.4 2.4 GHz Radio
Figure 4.20. 2.4 GHz RF Transmitter Output Power
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Figure 4.21. 2.4 GHz RF Receiver Sensitivity
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5. Typical Connection Diagrams
5.1 Power
Typical power supply connections for direct supply, without using the internal DC-DC converter, are shown in the following figure.
Main
Supply
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
–
Figure 5.1. EFR32MG1 Typical Application Circuit: Direct Supply Configuration without DC-DC converter
Typical power supply circuits using the internal DC-DC converter are shown below. The MCU operates from the DC-DC converter sup-
ply. For low RF transmit power applications less than 13dBm, the RF PA may be supplied by the DC-DC converter. For OPNs support-
ing high power RF transmission, the RF PA must be directly supplied by VDD for RF transmit power greater than 13 dBm.
Main
Supply
VDCDC
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
–
Figure 5.2. EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDCDC)
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Typical Connection Diagrams
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Main
Supply
VDCDC
VDD
VREGVDD AVDD IOVDD
VREGSW
VREGVSS
DVDD
DECOUPLE
RFVDD PAVDD
HFXTAL_N
HFXTAL_P
LFXTAL_N
LFXTAL_P
+
–
Figure 5.3. EFR32MG1 Typical Application Circuit: Configuration with DC-DC converter (PAVDD from VDD)
5.2 RF Matching Networks
Typical RF matching network circuit diagrams are shown in Figure 5.4 Typical 2.4 GHz RF impedance-matching network circuits on
page 65 for applications in the 2.4GHz band. Application-specific component values can be found in the EFR32 Reference Manual.
For low RF transmit power applications less than 13dBm, the two-element match is recommended. For OPNs supporting high power
RF transmission, the four-element match is recommended for high RF transmit power (> 13dBm).
2-Element Match for 2.4GHz Band 4-Element Match for 2.4GHz Band
L0
C0
50Ω2G4RF_IOP
2G4RF_ION 2G4RF_ION
2G4RF_IOP
L0 L1
C0 C1
50Ω
PAVDD PAVDD
PAVDD PAVDD
Figure 5.4. Typical 2.4 GHz RF impedance-matching network circuits
5.3 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN0002: "Hardware De-
sign Considerations" contains detailed information on these connections. Application Notes can be accessed on the Silicon Labs web-
site (www.silabs.com/32bit-appnotes).
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6. Pin Definitions
6.1 EFR32MG1 QFN32 2.4 GHz Definition
Figure 6.1. EFR32MG1 QFN32 2.4 GHz Pinout
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Pin Definitions
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Table 6.1. QFN32 2.4 GHz Device Pinout
QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#Pin Name Analog Timers Communication Radio Other
0 VSS Ground
1 PF0
BUSAX [ADC0:
APORT1XCH16
ACMP0:
APORT1XCH16
ACMP1:
APORT1XCH16]
BUSBY [ADC0:
APORT2YCH16
ACMP0:
APORT2YCH16
ACMP1:
APORT2YCH16]
TIM0_CC0 #24
TIM0_CC1 #23
TIM0_CC2 #22
TIM0_CDTI0 #21
TIM0_CDTI1 #20
TIM0_CDTI2 #19
TIM1_CC0 #24
TIM1_CC1 #23
TIM1_CC2 #22
TIM1_CC3 #21 LE-
TIM0_OUT0 #24
LETIM0_OUT1 #23
PCNT0_S0IN #24
PCNT0_S1IN #23
US0_TX #24
US0_RX #23
US0_CLK #22
US0_CS #21
US0_CTS #20
US0_RTS #19
LEU0_TX #24
LEU0_RX #23
I2C0_SDA #24
I2C0_SCL #23
FRC_DCLK #24
FRC_DOUT #23
FRC_DFRAME #22
MODEM_DCLK #24
MODEM_DIN #23
MODEM_DOUT #22
MODEM_ANT0 #21
MODEM_ANT1 #20
PRS_CH0 #0
PRS_CH1 #7
PRS_CH2 #6
PRS_CH3 #5
ACMP0_O #24
ACMP1_O #24
DBG_SWCLKTCK
#0
2 PF1
BUSAY [ADC0:
APORT1YCH17
ACMP0:
APORT1YCH17
ACMP1:
APORT1YCH17]
BUSBX [ADC0:
APORT2XCH17
ACMP0:
APORT2XCH17
ACMP1:
APORT2XCH17]
TIM0_CC0 #25
TIM0_CC1 #24
TIM0_CC2 #23
TIM0_CDTI0 #22
TIM0_CDTI1 #21
TIM0_CDTI2 #20
TIM1_CC0 #25
TIM1_CC1 #24
TIM1_CC2 #23
TIM1_CC3 #22 LE-
TIM0_OUT0 #25
LETIM0_OUT1 #24
PCNT0_S0IN #25
PCNT0_S1IN #24
US0_TX #25
US0_RX #24
US0_CLK #23
US0_CS #22
US0_CTS #21
US0_RTS #20
LEU0_TX #25
LEU0_RX #24
I2C0_SDA #25
I2C0_SCL #24
FRC_DCLK #25
FRC_DOUT #24
FRC_DFRAME #23
MODEM_DCLK #25
MODEM_DIN #24
MODEM_DOUT #23
MODEM_ANT0 #22
MODEM_ANT1 #21
PRS_CH0 #1
PRS_CH1 #0
PRS_CH2 #7
PRS_CH3 #6
ACMP0_O #25
ACMP1_O #25
DBG_SWDIOTMS
#0
3 PF2
BUSAX [ADC0:
APORT1XCH18
ACMP0:
APORT1XCH18
ACMP1:
APORT1XCH18]
BUSBY [ADC0:
APORT2YCH18
ACMP0:
APORT2YCH18
ACMP1:
APORT2YCH18]
TIM0_CC0 #26
TIM0_CC1 #25
TIM0_CC2 #24
TIM0_CDTI0 #23
TIM0_CDTI1 #22
TIM0_CDTI2 #21
TIM1_CC0 #26
TIM1_CC1 #25
TIM1_CC2 #24
TIM1_CC3 #23 LE-
TIM0_OUT0 #26
LETIM0_OUT1 #25
PCNT0_S0IN #26
PCNT0_S1IN #25
US0_TX #26
US0_RX #25
US0_CLK #24
US0_CS #23
US0_CTS #22
US0_RTS #21
LEU0_TX #26
LEU0_RX #25
I2C0_SDA #26
I2C0_SCL #25
FRC_DCLK #26
FRC_DOUT #25
FRC_DFRAME #24
MODEM_DCLK #26
MODEM_DIN #25
MODEM_DOUT #24
MODEM_ANT0 #23
MODEM_ANT1 #22
CMU_CLK0 #6
PRS_CH0 #2
PRS_CH1 #1
PRS_CH2 #0
PRS_CH3 #7
ACMP0_O #26
ACMP1_O #26
DBG_TDO #0
DBG_SWO #0
GPIO_EM4WU0
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QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#Pin Name Analog Timers Communication Radio Other
4 PF3
BUSAY [ADC0:
APORT1YCH19
ACMP0:
APORT1YCH19
ACMP1:
APORT1YCH19]
BUSBX [ADC0:
APORT2XCH19
ACMP0:
APORT2XCH19
ACMP1:
APORT2XCH19]
TIM0_CC0 #27
TIM0_CC1 #26
TIM0_CC2 #25
TIM0_CDTI0 #24
TIM0_CDTI1 #23
TIM0_CDTI2 #22
TIM1_CC0 #27
TIM1_CC1 #26
TIM1_CC2 #25
TIM1_CC3 #24 LE-
TIM0_OUT0 #27
LETIM0_OUT1 #26
PCNT0_S0IN #27
PCNT0_S1IN #26
US0_TX #27
US0_RX #26
US0_CLK #25
US0_CS #24
US0_CTS #23
US0_RTS #22
LEU0_TX #27
LEU0_RX #26
I2C0_SDA #27
I2C0_SCL #26
FRC_DCLK #27
FRC_DOUT #26
FRC_DFRAME #25
MODEM_DCLK #27
MODEM_DIN #26
MODEM_DOUT #25
MODEM_ANT0 #24
MODEM_ANT1 #23
CMU_CLK1 #6
PRS_CH0 #3
PRS_CH1 #2
PRS_CH2 #1
PRS_CH3 #0
ACMP0_O #27
ACMP1_O #27
DBG_TDI #0
5 RFVDD Radio power supply
6 HFXTAL_N High Frequency Crystal input pin.
7 HFXTAL_P High Frequency Crystal output pin.
8 RESETn Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low
during reset, and let the internal pull-up ensure that reset is released.
9 RFVSS Radio Ground
10 PAVSS Power Amplifier (PA) voltage regulator VSS
11 2G4RF_ION 2.4 GHz Differential RF input/output, negative path. This pin should be externally grounded.
12 2G4RF_IOP 2.4 GHz Differential RF input/output, positive path.
13 PAVDD Power Amplifier (PA) voltage regulator VDD input
14 PD13
BUSCY [ADC0:
APORT3YCH5
ACMP0:
APORT3YCH5
ACMP1:
APORT3YCH5
IDAC0:
APORT1YCH5]
BUSDX [ADC0:
APORT4XCH5
ACMP0:
APORT4XCH5
ACMP1:
APORT4XCH5]
TIM0_CC0 #21
TIM0_CC1 #20
TIM0_CC2 #19
TIM0_CDTI0 #18
TIM0_CDTI1 #17
TIM0_CDTI2 #16
TIM1_CC0 #21
TIM1_CC1 #20
TIM1_CC2 #19
TIM1_CC3 #18 LE-
TIM0_OUT0 #21
LETIM0_OUT1 #20
PCNT0_S0IN #21
PCNT0_S1IN #20
US0_TX #21
US0_RX #20
US0_CLK #19
US0_CS #18
US0_CTS #17
US0_RTS #16
LEU0_TX #21
LEU0_RX #20
I2C0_SDA #21
I2C0_SCL #20
FRC_DCLK #21
FRC_DOUT #20
FRC_DFRAME #19
MODEM_DCLK #21
MODEM_DIN #20
MODEM_DOUT #19
MODEM_ANT0 #18
MODEM_ANT1 #17
PRS_CH3 #12
PRS_CH4 #4
PRS_CH5 #3
PRS_CH6 #15
ACMP0_O #21
ACMP1_O #21
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QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#Pin Name Analog Timers Communication Radio Other
15 PD14
BUSCX [ADC0:
APORT3XCH6
ACMP0:
APORT3XCH6
ACMP1:
APORT3XCH6
IDAC0:
APORT1XCH6]
BUSDY [ADC0:
APORT4YCH6
ACMP0:
APORT4YCH6
ACMP1:
APORT4YCH6]
TIM0_CC0 #22
TIM0_CC1 #21
TIM0_CC2 #20
TIM0_CDTI0 #19
TIM0_CDTI1 #18
TIM0_CDTI2 #17
TIM1_CC0 #22
TIM1_CC1 #21
TIM1_CC2 #20
TIM1_CC3 #19 LE-
TIM0_OUT0 #22
LETIM0_OUT1 #21
PCNT0_S0IN #22
PCNT0_S1IN #21
US0_TX #22
US0_RX #21
US0_CLK #20
US0_CS #19
US0_CTS #18
US0_RTS #17
LEU0_TX #22
LEU0_RX #21
I2C0_SDA #22
I2C0_SCL #21
FRC_DCLK #22
FRC_DOUT #21
FRC_DFRAME #20
MODEM_DCLK #22
MODEM_DIN #21
MODEM_DOUT #20
MODEM_ANT0 #19
MODEM_ANT1 #18
CMU_CLK0 #5
PRS_CH3 #13
PRS_CH4 #5
PRS_CH5 #4
PRS_CH6 #16
ACMP0_O #22
ACMP1_O #22
GPIO_EM4WU4
16 PD15
BUSCY [ADC0:
APORT3YCH7
ACMP0:
APORT3YCH7
ACMP1:
APORT3YCH7
IDAC0:
APORT1YCH7]
BUSDX [ADC0:
APORT4XCH7
ACMP0:
APORT4XCH7
ACMP1:
APORT4XCH7]
TIM0_CC0 #23
TIM0_CC1 #22
TIM0_CC2 #21
TIM0_CDTI0 #20
TIM0_CDTI1 #19
TIM0_CDTI2 #18
TIM1_CC0 #23
TIM1_CC1 #22
TIM1_CC2 #21
TIM1_CC3 #20 LE-
TIM0_OUT0 #23
LETIM0_OUT1 #22
PCNT0_S0IN #23
PCNT0_S1IN #22
US0_TX #23
US0_RX #22
US0_CLK #21
US0_CS #20
US0_CTS #19
US0_RTS #18
LEU0_TX #23
LEU0_RX #22
I2C0_SDA #23
I2C0_SCL #22
FRC_DCLK #23
FRC_DOUT #22
FRC_DFRAME #21
MODEM_DCLK #23
MODEM_DIN #22
MODEM_DOUT #21
MODEM_ANT0 #20
MODEM_ANT1 #19
CMU_CLK1 #5
PRS_CH3 #14
PRS_CH4 #6
PRS_CH5 #5
PRS_CH6 #17
ACMP0_O #23
ACMP1_O #23
DBG_SWO #2
17 PA0
ADC0_EXTN
BUSCX [ADC0:
APORT3XCH8
ACMP0:
APORT3XCH8
ACMP1:
APORT3XCH8
IDAC0:
APORT1XCH8]
BUSDY [ADC0:
APORT4YCH8
ACMP0:
APORT4YCH8
ACMP1:
APORT4YCH8]
TIM0_CC0 #0
TIM0_CC1 #31
TIM0_CC2 #30
TIM0_CDTI0 #29
TIM0_CDTI1 #28
TIM0_CDTI2 #27
TIM1_CC0 #0
TIM1_CC1 #31
TIM1_CC2 #30
TIM1_CC3 #29 LE-
TIM0_OUT0 #0 LE-
TIM0_OUT1 #31
PCNT0_S0IN #0
PCNT0_S1IN #31
US0_TX #0
US0_RX #31
US0_CLK #30
US0_CS #29
US0_CTS #28
US0_RTS #27
LEU0_TX #0
LEU0_RX #31
I2C0_SDA #0
I2C0_SCL #31
FRC_DCLK #0
FRC_DOUT #31
FRC_DFRAME #30
MODEM_DCLK #0
MODEM_DIN #31
MODEM_DOUT #30
MODEM_ANT0 #29
MODEM_ANT1 #28
CMU_CLK1 #0
PRS_CH6 #0
PRS_CH7 #10
PRS_CH8 #9
PRS_CH9 #8
ACMP0_O #0
ACMP1_O #0
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QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#Pin Name Analog Timers Communication Radio Other
18 PA1
ADC0_EXTP
BUSCY [ADC0:
APORT3YCH9
ACMP0:
APORT3YCH9
ACMP1:
APORT3YCH9
IDAC0:
APORT1YCH9]
BUSDX [ADC0:
APORT4XCH9
ACMP0:
APORT4XCH9
ACMP1:
APORT4XCH9]
TIM0_CC0 #1
TIM0_CC1 #0
TIM0_CC2 #31
TIM0_CDTI0 #30
TIM0_CDTI1 #29
TIM0_CDTI2 #28
TIM1_CC0 #1
TIM1_CC1 #0
TIM1_CC2 #31
TIM1_CC3 #30 LE-
TIM0_OUT0 #1 LE-
TIM0_OUT1 #0
PCNT0_S0IN #1
PCNT0_S1IN #0
US0_TX #1
US0_RX #0
US0_CLK #31
US0_CS #30
US0_CTS #29
US0_RTS #28
LEU0_TX #1
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #0
FRC_DCLK #1
FRC_DOUT #0
FRC_DFRAME #31
MODEM_DCLK #1
MODEM_DIN #0
MODEM_DOUT #31
MODEM_ANT0 #30
MODEM_ANT1 #29
CMU_CLK0 #0
PRS_CH6 #1
PRS_CH7 #0
PRS_CH8 #10
PRS_CH9 #9
ACMP0_O #1
ACMP1_O #1
19 PB11
BUSCY [ADC0:
APORT3YCH27
ACMP0:
APORT3YCH27
ACMP1:
APORT3YCH27
IDAC0:
APORT1YCH27]
BUSDX [ADC0:
APORT4XCH27
ACMP0:
APORT4XCH27
ACMP1:
APORT4XCH27]
TIM0_CC0 #6
TIM0_CC1 #5
TIM0_CC2 #4
TIM0_CDTI0 #3
TIM0_CDTI1 #2
TIM0_CDTI2 #1
TIM1_CC0 #6
TIM1_CC1 #5
TIM1_CC2 #4
TIM1_CC3 #3 LE-
TIM0_OUT0 #6 LE-
TIM0_OUT1 #5
PCNT0_S0IN #6
PCNT0_S1IN #5
US0_TX #6
US0_RX #5
US0_CLK #4
US0_CS #3
US0_CTS #2
US0_RTS #1
LEU0_TX #6
LEU0_RX #5
I2C0_SDA #6
I2C0_SCL #5
FRC_DCLK #6
FRC_DOUT #5
FRC_DFRAME #4
MODEM_DCLK #6
MODEM_DIN #5
MODEM_DOUT #4
MODEM_ANT0 #3
MODEM_ANT1 #2
PRS_CH6 #6
PRS_CH7 #5
PRS_CH8 #4
PRS_CH9 #3
ACMP0_O #6
ACMP1_O #6
20 PB12
BUSCX [ADC0:
APORT3XCH28
ACMP0:
APORT3XCH28
ACMP1:
APORT3XCH28
IDAC0:
APORT1XCH28]
BUSDY [ADC0:
APORT4YCH28
ACMP0:
APORT4YCH28
ACMP1:
APORT4YCH28]
TIM0_CC0 #7
TIM0_CC1 #6
TIM0_CC2 #5
TIM0_CDTI0 #4
TIM0_CDTI1 #3
TIM0_CDTI2 #2
TIM1_CC0 #7
TIM1_CC1 #6
TIM1_CC2 #5
TIM1_CC3 #4 LE-
TIM0_OUT0 #7 LE-
TIM0_OUT1 #6
PCNT0_S0IN #7
PCNT0_S1IN #6
US0_TX #7
US0_RX #6
US0_CLK #5
US0_CS #4
US0_CTS #3
US0_RTS #2
LEU0_TX #7
LEU0_RX #6
I2C0_SDA #7
I2C0_SCL #6
FRC_DCLK #7
FRC_DOUT #6
FRC_DFRAME #5
MODEM_DCLK #7
MODEM_DIN #6
MODEM_DOUT #5
MODEM_ANT0 #4
MODEM_ANT1 #3
PRS_CH6 #7
PRS_CH7 #6
PRS_CH8 #5
PRS_CH9 #4
ACMP0_O #7
ACMP1_O #7
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QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#Pin Name Analog Timers Communication Radio Other
21 PB13
BUSCY [ADC0:
APORT3YCH29
ACMP0:
APORT3YCH29
ACMP1:
APORT3YCH29
IDAC0:
APORT1YCH29]
BUSDX [ADC0:
APORT4XCH29
ACMP0:
APORT4XCH29
ACMP1:
APORT4XCH29]
TIM0_CC0 #8
TIM0_CC1 #7
TIM0_CC2 #6
TIM0_CDTI0 #5
TIM0_CDTI1 #4
TIM0_CDTI2 #3
TIM1_CC0 #8
TIM1_CC1 #7
TIM1_CC2 #6
TIM1_CC3 #5 LE-
TIM0_OUT0 #8 LE-
TIM0_OUT1 #7
PCNT0_S0IN #8
PCNT0_S1IN #7
US0_TX #8
US0_RX #7
US0_CLK #6
US0_CS #5
US0_CTS #4
US0_RTS #3
LEU0_TX #8
LEU0_RX #7
I2C0_SDA #8
I2C0_SCL #7
FRC_DCLK #8
FRC_DOUT #7
FRC_DFRAME #6
MODEM_DCLK #8
MODEM_DIN #7
MODEM_DOUT #6
MODEM_ANT0 #5
MODEM_ANT1 #4
PRS_CH6 #8
PRS_CH7 #7
PRS_CH8 #6
PRS_CH9 #5
ACMP0_O #8
ACMP1_O #8
DBG_SWO #1
GPIO_EM4WU9
22 AVDD Analog power supply.
23 PB14
LFXTAL_N
BUSCX [ADC0:
APORT3XCH30
ACMP0:
APORT3XCH30
ACMP1:
APORT3XCH30
IDAC0:
APORT1XCH30]
BUSDY [ADC0:
APORT4YCH30
ACMP0:
APORT4YCH30
ACMP1:
APORT4YCH30]
TIM0_CC0 #9
TIM0_CC1 #8
TIM0_CC2 #7
TIM0_CDTI0 #6
TIM0_CDTI1 #5
TIM0_CDTI2 #4
TIM1_CC0 #9
TIM1_CC1 #8
TIM1_CC2 #7
TIM1_CC3 #6 LE-
TIM0_OUT0 #9 LE-
TIM0_OUT1 #8
PCNT0_S0IN #9
PCNT0_S1IN #8
US0_TX #9
US0_RX #8
US0_CLK #7
US0_CS #6
US0_CTS #5
US0_RTS #4
LEU0_TX #9
LEU0_RX #8
I2C0_SDA #9
I2C0_SCL #8
FRC_DCLK #9
FRC_DOUT #8
FRC_DFRAME #7
MODEM_DCLK #9
MODEM_DIN #8
MODEM_DOUT #7
MODEM_ANT0 #6
MODEM_ANT1 #5
CMU_CLK1 #1
PRS_CH6 #9
PRS_CH7 #8
PRS_CH8 #7
PRS_CH9 #6
ACMP0_O #9
ACMP1_O #9
24 PB15
LFXTAL_P
BUSCY [ADC0:
APORT3YCH31
ACMP0:
APORT3YCH31
ACMP1:
APORT3YCH31
IDAC0:
APORT1YCH31]
BUSDX [ADC0:
APORT4XCH31
ACMP0:
APORT4XCH31
ACMP1:
APORT4XCH31]
TIM0_CC0 #10
TIM0_CC1 #9
TIM0_CC2 #8
TIM0_CDTI0 #7
TIM0_CDTI1 #6
TIM0_CDTI2 #5
TIM1_CC0 #10
TIM1_CC1 #9
TIM1_CC2 #8
TIM1_CC3 #7 LE-
TIM0_OUT0 #10
LETIM0_OUT1 #9
PCNT0_S0IN #10
PCNT0_S1IN #9
US0_TX #10
US0_RX #9
US0_CLK #8
US0_CS #7
US0_CTS #6
US0_RTS #5
LEU0_TX #10
LEU0_RX #9
I2C0_SDA #10
I2C0_SCL #9
FRC_DCLK #10
FRC_DOUT #9
FRC_DFRAME #8
MODEM_DCLK #10
MODEM_DIN #9
MODEM_DOUT #8
MODEM_ANT0 #7
MODEM_ANT1 #6
CMU_CLK0 #1
PRS_CH6 #10
PRS_CH7 #9
PRS_CH8 #8
PRS_CH9 #7
ACMP0_O #10
ACMP1_O #10
25 VREGVSS Voltage regulator VSS
26 VREGSW DCDC regulator switching node
27 VREGVDD Voltage regulator VDD input
28 DVDD Digital power supply.
29 DECOUPLE Decouple output for on-chip voltage regulator. An external decoupling capacitor is required at this pin.
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Pin Definitions
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QFN32 Pin# and
Name
Pin Alternate Functionality / Description
Pin
#Pin Name Analog Timers Communication Radio Other
30 IOVDD Digital IO power supply.
31 PC10
BUSAX [ADC0:
APORT1XCH10
ACMP0:
APORT1XCH10
ACMP1:
APORT1XCH10]
BUSBY [ADC0:
APORT2YCH10
ACMP0:
APORT2YCH10
ACMP1:
APORT2YCH10]
TIM0_CC0 #15
TIM0_CC1 #14
TIM0_CC2 #13
TIM0_CDTI0 #12
TIM0_CDTI1 #11
TIM0_CDTI2 #10
TIM1_CC0 #15
TIM1_CC1 #14
TIM1_CC2 #13
TIM1_CC3 #12 LE-
TIM0_OUT0 #15
LETIM0_OUT1 #14
PCNT0_S0IN #15
PCNT0_S1IN #14
US0_TX #15
US0_RX #14
US0_CLK #13
US0_CS #12
US0_CTS #11
US0_RTS #10
LEU0_TX #15
LEU0_RX #14
I2C0_SDA #15
I2C0_SCL #14
FRC_DCLK #15
FRC_DOUT #14
FRC_DFRAME #13
MODEM_DCLK #15
MODEM_DIN #14
MODEM_DOUT #13
MODEM_ANT0 #12
MODEM_ANT1 #11
CMU_CLK1 #3
PRS_CH0 #12
PRS_CH9 #15
PRS_CH10 #4
PRS_CH11 #3
ACMP0_O #15
ACMP1_O #15
GPIO_EM4WU12
32 PC11
BUSAY [ADC0:
APORT1YCH11
ACMP0:
APORT1YCH11
ACMP1:
APORT1YCH11]
BUSBX [ADC0:
APORT2XCH11
ACMP0:
APORT2XCH11
ACMP1:
APORT2XCH11]
TIM0_CC0 #16
TIM0_CC1 #15
TIM0_CC2 #14
TIM0_CDTI0 #13
TIM0_CDTI1 #12
TIM0_CDTI2 #11
TIM1_CC0 #16
TIM1_CC1 #15
TIM1_CC2 #14
TIM1_CC3 #13 LE-
TIM0_OUT0 #16
LETIM0_OUT1 #15
PCNT0_S0IN #16
PCNT0_S1IN #15
US0_TX #16
US0_RX #15
US0_CLK #14
US0_CS #13
US0_CTS #12
US0_RTS #11
LEU0_TX #16
LEU0_RX #15
I2C0_SDA #16
I2C0_SCL #15
FRC_DCLK #16
FRC_DOUT #15
FRC_DFRAME #14
MODEM_DCLK #16
MODEM_DIN #15
MODEM_DOUT #14
MODEM_ANT0 #13
MODEM_ANT1 #12
CMU_CLK0 #3
PRS_CH0 #13
PRS_CH9 #16
PRS_CH10 #5
PRS_CH11 #4
ACMP0_O #16
ACMP1_O #16
DBG_SWO #3
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6.1.1 EFR32MG1 QFN32 2.4 GHz GPIO Overview
The GPIO pins are organized as 16-bit ports indicated by letters (A, B, C...), and the individual pins on each port are indicated by a
number from 15 down to 0.
Table 6.2. QFN32 2.4 GHz GPIO Pinout
Port Pin
15
Pin
14
Pin
13
Pin
12
Pin
11
Pin
10
Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0
Port A - - - - - - - - - - - - - - PA1 PA0
Port B PB15 PB14 PB13
(5V)
PB12
(5V)
PB11
(5V) -----------
Port C - - - - PC11
(5V)
PC10
(5V) ----------
Port D PD15
(5V)
PD14
(5V)
PD13
(5V) -------------
Port F - - - - - - - - - - - - PF3
(5V)
PF2
(5V)
PF1
(5V)
PF0
(5V)
Note:
1. GPIO with 5V tolerance are indicated by (5V).
2. The pins PB13, PB12, PB11, PD15, PD14, and PD13 will not be 5V tolerant on all future devices. In order to preserve upgrade
options with full hardware compatibility, do not use these pins with 5V domains.
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6.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. The following table shows the name of the alter-
nate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.
Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout
is shown in the column corresponding to LOCATION 0.
Table 6.3. Alternate functionality overview
Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
ACMP0_O
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Analog comparator
ACMP0, digital out-
put.
ACMP1_O
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Analog comparator
ACMP1, digital out-
put.
ADC0_EXTN
0: PA0 Analog to digital
converter ADC0 ex-
ternal reference in-
put negative pin
ADC0_EXTP
0: PA1 Analog to digital
converter ADC0 ex-
ternal reference in-
put positive pin
CMU_CLK0
0: PA1
1: PB15
3: PC11
5: PD14
6: PF2
Clock Management
Unit, clock output
number 0.
CMU_CLK1
0: PA0
1: PB14
3: PC10
5: PD15
6: PF3
Clock Management
Unit, clock output
number 1.
DBG_SWCLKTCK
0: PF0
Debug-interface
Serial Wire clock
input and JTAG
Test Clock.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull down.
DBG_SWDIOTMS
0: PF1
Debug-interface
Serial Wire data in-
put / output and
JTAG Test Mode
Select.
Note that this func-
tion is enabled to
the pin out of reset,
and has a built-in
pull up.
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
DBG_SWO
0: PF2
1: PB13
2: PD15
3: PC11
Debug-interface
Serial Wire viewer
Output.
Note that this func-
tion is not enabled
after reset, and
must be enabled by
software to be
used.
DBG_TDI
0: PF3
Debug-interface
JTAG Test Data In.
Note that this func-
tion is enabled to
pin out of reset,
and has a built-in
pull up.
DBG_TDO
0: PF2
Debug-interface
JTAG Test Data
Out.
Note that this func-
tion is enabled to
pin out of reset.
FRC_DCLK
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Frame Controller,
Data Sniffer Clock.
FRC_DFRAME
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
13: PC10
14: PC11
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
30: PA0
31: PA1
Frame Controller,
Data Sniffer Frame
active
FRC_DOUT
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
Frame Controller,
Data Sniffer Out-
put.
GPIO_EM4WU0
0: PF2 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU4
0: PD14 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU9
0: PB13 Pin can be used to
wake the system
up from EM4
GPIO_EM4WU12
0: PC10 Pin can be used to
wake the system
up from EM4
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
I2C0_SCL
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
I2C0 Serial Clock
Line input / output.
I2C0_SDA
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
I2C0 Serial Data in-
put / output.
LETIM0_OUT0
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Low Energy Timer
LETIM0, output
channel 0.
LETIM0_OUT1
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
Low Energy Timer
LETIM0, output
channel 1.
LEU0_RX
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
LEUART0 Receive
input.
LEU0_TX
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
LEUART0 Transmit
output. Also used
as receive input in
half duplex commu-
nication.
LFXTAL_N
0: PB14
Low Frequency
Crystal (typically
32.768 kHz) nega-
tive pin. Also used
as an optional ex-
ternal clock input
pin.
LFXTAL_P
0: PB15 Low Frequency
Crystal (typically
32.768 kHz) posi-
tive pin.
MODEM_ANT0
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
12: PC10
13: PC11
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
29: PA0
30: PA1
MODEM antenna
control output 0,
used for antenna
diversity.
MODEM_ANT1 2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
11: PC10
12: PC11
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
28: PA0
29: PA1
MODEM antenna
control output 1,
used for antenna
diversity.
MODEM_DCLK
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
MODEM data clock
out.
MODEM_DIN
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
MODEM data in.
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Pin Definitions
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
MODEM_DOUT
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
13: PC10
14: PC11
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
30: PA0
31: PA1
MODEM data out.
PCNT0_S0IN
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Pulse Counter
PCNT0 input num-
ber 0.
PCNT0_S1IN
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
Pulse Counter
PCNT0 input num-
ber 1.
PRS_CH0
0: PF0
1: PF1
2: PF2
3: PF3
12: PC10
13: PC11 Peripheral Reflex
System PRS, chan-
nel 0.
PRS_CH1
0: PF1
1: PF2
2: PF3
7: PF0
Peripheral Reflex
System PRS, chan-
nel 1.
PRS_CH2
0: PF2
1: PF3
6: PF0
7: PF1
Peripheral Reflex
System PRS, chan-
nel 2.
PRS_CH3
0: PF3
5: PF0
6: PF1
7: PF2
12: PD13
13: PD14
14: PD15
Peripheral Reflex
System PRS, chan-
nel 3.
PRS_CH4
4: PD13
5: PD14
6: PD15
Peripheral Reflex
System PRS, chan-
nel 4.
PRS_CH5
3: PD13
4: PD14
5: PD15 Peripheral Reflex
System PRS, chan-
nel 5.
PRS_CH6
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PD13
16: PD14
17: PD15 Peripheral Reflex
System PRS, chan-
nel 6.
PRS_CH7
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
10: PA0
Peripheral Reflex
System PRS, chan-
nel 7.
PRS_CH8
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
9: PA0
10: PA1
Peripheral Reflex
System PRS, chan-
nel 8.
PRS_CH9
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
8: PA0
9: PA1
15: PC10
16: PC11 Peripheral Reflex
System PRS, chan-
nel 9.
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Pin Definitions
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
PRS_CH10
4: PC10
5: PC11 Peripheral Reflex
System PRS, chan-
nel 10.
PRS_CH11
3: PC10
4: PC11 Peripheral Reflex
System PRS, chan-
nel 11.
TIM0_CC0
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Timer 0 Capture
Compare input /
output channel 0.
TIM0_CC1
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
Timer 0 Capture
Compare input /
output channel 1.
TIM0_CC2
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
13: PC10
14: PC11
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
30: PA0
31: PA1
Timer 0 Capture
Compare input /
output channel 2.
TIM0_CDTI0
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
12: PC10
13: PC11
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
29: PA0
30: PA1
Timer 0 Compli-
mentary Dead Time
Insertion channel 0.
TIM0_CDTI1 2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
11: PC10
12: PC11
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
28: PA0
29: PA1 Timer 0 Compli-
mentary Dead Time
Insertion channel 1.
TIM0_CDTI2 1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
10: PC10
11: PC11
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
27: PA0
28: PA1 Timer 0 Compli-
mentary Dead Time
Insertion channel 2.
TIM1_CC0
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
Timer 1 Capture
Compare input /
output channel 0.
TIM1_CC1
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
Timer 1 Capture
Compare input /
output channel 1.
TIM1_CC2
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
13: PC10
14: PC11
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
30: PA0
31: PA1
Timer 1 Capture
Compare input /
output channel 2.
TIM1_CC3
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
12: PC10
13: PC11
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
29: PA0
30: PA1
Timer 1 Capture
Compare input /
output channel 3.
US0_CLK
4: PB11
5: PB12
6: PB13
7: PB14
8: PB15
13: PC10
14: PC11
19: PD13
20: PD14
21: PD15
22: PF0
23: PF1
24: PF2
25: PF3
30: PA0
31: PA1
USART0 clock in-
put / output.
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Pin Definitions
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Alternate LOCATION
Functionality 0 - 3 4 - 7 8 - 11 12 - 15 16 - 19 20 - 23 24 - 27 28 - 31 Description
US0_CS
3: PB11
4: PB12
5: PB13
6: PB14
7: PB15
12: PC10
13: PC11
18: PD13
19: PD14
20: PD15
21: PF0
22: PF1
23: PF2
24: PF3
29: PA0
30: PA1
USART0 chip se-
lect input / output.
US0_CTS 2: PB11
3: PB12
4: PB13
5: PB14
6: PB15
11: PC10
12: PC11
17: PD13
18: PD14
19: PD15
20: PF0
21: PF1
22: PF2
23: PF3
28: PA0
29: PA1 USART0 Clear To
Send hardware
flow control input.
US0_RTS 1: PB11
2: PB12
3: PB13
4: PB14
5: PB15
10: PC10
11: PC11
16: PD13
17: PD14
18: PD15
19: PF0
20: PF1
21: PF2
22: PF3
27: PA0
28: PA1 USART0 Request
To Send hardware
flow control output.
US0_RX
0: PA1
5: PB11
6: PB12
7: PB13
8: PB14
9: PB15
14: PC10
15: PC11
20: PD13
21: PD14
22: PD15
23: PF0
24: PF1
25: PF2
26: PF3
31: PA0
USART0 Asynchro-
nous Receive.
USART0 Synchro-
nous mode Master
Input / Slave Out-
put (MISO).
US0_TX
0: PA0
1: PA1
6: PB11
7: PB12
8: PB13
9: PB14
10: PB15
15: PC10
16: PC11
21: PD13
22: PD14
23: PD15
24: PF0
25: PF1
26: PF2
27: PF3
USART0 Asynchro-
nous Transmit. Al-
so used as receive
input in half duplex
communication.
USART0 Synchro-
nous mode Master
Output / Slave In-
put (MOSI).
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Pin Definitions
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6.3 Analog Port (APORT)
The Analog Port (APORT) is an infrastructure used to connect chip pins with on-chip analog clients such as analog comparators, ADCs,
and DACs. The APORT consists of wires, switches, and control needed to configurably implement the routes. Please see the device
Reference Manual for a complete description.
PF0 BUSAX
PF2
PC10
BUSBY
PF1 BUSAY
PF3
PC11
BUSBX
PB14 BUSCX
PD14
PA0
PB12
BUSDY
PD13 BUSCY
PD15
PA1
PB11
PB13
PB15
BUSDX
ACMP0
1X 1Y 2X 2Y 3X 3Y 4X 4Y
ACMP1
1X 1Y 2X 2Y 3X 3Y 4X 4Y
ADC0
1X 1Y 2X 2Y 3X 3Y 4X 4Y
IDAC0
1X 1Y
Figure 6.2. EFR32MG1 APORT
Table 6.4. APORT Client Map
Analog Module Analog Module Channel Shared Bus Pin
ACMP0 APORT1XCH10 BUSAX PC10
APORT1XCH16 PF0
APORT1XCH18 PF2
ACMP0 APORT1YCH11 BUSAY PC11
APORT1YCH17 PF1
APORT1YCH19 PF3
ACMP0 APORT2XCH11 BUSBX PC11
APORT2XCH17 PF1
APORT2XCH19 PF3
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Analog Module Analog Module Channel Shared Bus Pin
ACMP0 APORT2YCH10 BUSBY PC10
APORT2YCH16 PF0
APORT2YCH18 PF2
ACMP0 APORT3XCH6 BUSCX PD14
APORT3XCH8 PA0
APORT3XCH28 PB12
APORT3XCH30 PB14
ACMP0 APORT3YCH5 BUSCY PD13
APORT3YCH7 PD15
APORT3YCH9 PA1
APORT3YCH27 PB11
APORT3YCH29 PB13
APORT3YCH31 PB15
ACMP0 APORT4XCH5 BUSDX PD13
APORT4XCH7 PD15
APORT4XCH9 PA1
APORT4XCH27 PB11
APORT4XCH29 PB13
APORT4XCH31 PB15
ACMP0 APORT4YCH6 BUSDY PD14
APORT4YCH8 PA0
APORT4YCH28 PB12
APORT4YCH30 PB14
ACMP1 APORT1XCH10 BUSAX PC10
APORT1XCH16 PF0
APORT1XCH18 PF2
ACMP1 APORT1YCH11 BUSAY PC11
APORT1YCH17 PF1
APORT1YCH19 PF3
ACMP1 APORT2XCH11 BUSBX PC11
APORT2XCH17 PF1
APORT2XCH19 PF3
ACMP1 APORT2YCH10 BUSBY PC10
APORT2YCH16 PF0
APORT2YCH18 PF2
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Analog Module Analog Module Channel Shared Bus Pin
ACMP1 APORT3XCH6 BUSCX PD14
APORT3XCH8 PA0
APORT3XCH28 PB12
APORT3XCH30 PB14
ACMP1 APORT3YCH5 BUSCY PD13
APORT3YCH7 PD15
APORT3YCH9 PA1
APORT3YCH27 PB11
APORT3YCH29 PB13
APORT3YCH31 PB15
ACMP1 APORT4XCH5 BUSDX PD13
APORT4XCH7 PD15
APORT4XCH9 PA1
APORT4XCH27 PB11
APORT4XCH29 PB13
APORT4XCH31 PB15
ACMP1 APORT4YCH6 BUSDY PD14
APORT4YCH8 PA0
APORT4YCH28 PB12
APORT4YCH30 PB14
ADC0 APORT1XCH10 BUSAX PC10
APORT1XCH16 PF0
APORT1XCH18 PF2
ADC0 APORT1YCH11 BUSAY PC11
APORT1YCH17 PF1
APORT1YCH19 PF3
ADC0 APORT2XCH11 BUSBX PC11
APORT2XCH17 PF1
APORT2XCH19 PF3
ADC0 APORT2YCH10 BUSBY PC10
APORT2YCH16 PF0
APORT2YCH18 PF2
ADC0 APORT3XCH6 BUSCX PD14
APORT3XCH8 PA0
APORT3XCH28 PB12
APORT3XCH30 PB14
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Analog Module Analog Module Channel Shared Bus Pin
ADC0 APORT3YCH5 BUSCY PD13
APORT3YCH7 PD15
APORT3YCH9 PA1
APORT3YCH27 PB11
APORT3YCH29 PB13
APORT3YCH31 PB15
ADC0 APORT4XCH5 BUSDX PD13
APORT4XCH7 PD15
APORT4XCH9 PA1
APORT4XCH27 PB11
APORT4XCH29 PB13
APORT4XCH31 PB15
ADC0 APORT4YCH6 BUSDY PD14
APORT4YCH8 PA0
APORT4YCH28 PB12
APORT4YCH30 PB14
IDAC0 APORT1XCH6 BUSCX PD14
APORT1XCH8 PA0
APORT1XCH28 PB12
APORT1XCH30 PB14
IDAC0 APORT1YCH5 BUSCY PD13
APORT1YCH7 PD15
APORT1YCH9 PA1
APORT1YCH27 PB11
APORT1YCH29 PB13
APORT1YCH31 PB15
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7. QFN32 Package Specifications
7.1 QFN32 Package Dimensions
Figure 7.1. QFN32 Package Drawing
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Table 7.1. QFN32 Package Dimensions
Dimension Min Typ Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.20 REF
b 0.18 0.25 0.30
D/E 4.90 5.00 5.10
D2/E2 3.40 3.50 3.60
E 0.50 BSC
L 0.30 0.40 0.50
K 0.20 — —
R 0.09 — 0.14
aaa 0.15
bbb 0.10
ccc 0.10
ddd 0.05
eee 0.08
fff 0.10
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220, Variation VKKD-4.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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7.2 QFN32 PCB Land Pattern
Figure 7.2. QFN32 PCB Land Pattern Drawing
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Table 7.2. QFN32 PCB Land Pattern Dimensions
Dimension Typ
S1 4.01
S 4.01
L1 3.50
W1 3.50
e 0.50
W 0.26
L 0.86
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size can be 1:1 for all perimeter pads.
7. A 3x3 array of 0.85 mm square openings on a 1.00 mm pitch can be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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7.3 QFN32 Package Marking
EFR32
PPPPPPPPP
YYWWTTTTTT
Figure 7.3. QFN32 Package Marking
The package marking consists of:
• PPPPPPPPP – The part number designation.
1. Family Code (B | M | F)
2. G (Gecko)
3. Series (1, 2,...)
4. Performance Grade (P | B | V)
5. Feature Code (1 to 7)
6. TRX Code (3 = TXRX | 2= RX | 1 = TX)
7. Band (1 = Sub-GHz | 2 = 2.4 GHz | 3 = Dual-band)
8. Flash (G = 256K | F = 128K | E = 64K | D = 32K)
9. Temperature Grade (G = -40 to 85 | I = -40 to 125)
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• TTTTTT – A trace or manufacturing code. The first letter is the device revision.
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8. Revision History
8.1 Revision 1.0
2016-Jul-22
• Added -I temperature grade OPN's and associated sections
• Electrical Characteristics: Minimum and maximum value statement changed to cover full operating temperature range.
• Finalized Specification Tables. Tables with condition/min/typ/max or footnote changes include:
• Absolute Maximum Ratings
• General Operating Conditions
• DC-DC Converter
• Current Consumption Using Radio 3.3V with DC-DC
• RF Transmitter General Characteristics for 2.4 GHz Band
• RF Receiver General Characteristics for 2.4 GHz Band
• RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band
• RF Transmitter Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
• RF Receiver Characteristics for 802.15.4 DSSS-OQPSK in the 2.4 GHz Band
• LFRCO
• HFRCO and AUXHFRCO
• Primary Flash Memory Characteristics
• GPIO
• ADC
• IDAC
• Updated Typical Performance Graphs.
• Added external ground note to 2G4RF_ION pin descriptions.
• Added note for 5V tolerance to pinout GPIO Overview sections.
• Updated OPN decoder with latest revision.
• Updated Package Marking text with latest descriptions.
8.2 Revision 0.95
2016-05-12
• All OPNs changed to rev C0. Note the following:
• All OPNs ending in -B0 are Engineering Samples based on an older revision of silicon and are being removed from the OPN
table. These older revisions should be used for evaluation only and will not be supported for production.
• OPNs ending in -C0 are the Current Revision of Silicon and are intended for production.
• Electrical specification tables updated with latest characterization data and production test limits.
8.3 Revision 0.2
2016-03-29
• Initial version.
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Table of Contents
1. Feature List ................................1
2. Ordering Information ............................2
3. System Overview ..............................4
3.1 Introduction...............................4
3.2 Radio.................................4
3.2.1 Antenna Interface ............................4
3.2.2 Fractional-N Frequency Synthesizer......................5
3.2.3 Receiver Architecture...........................5
3.2.4 Transmitter Architecture ..........................5
3.2.5 Wake on Radio .............................5
3.2.6 RFSENSE ..............................5
3.2.7 Flexible Frame Handling..........................6
3.2.8 Packet and State Trace ..........................6
3.2.9 Data Buffering .............................6
3.2.10 Radio Controller (RAC)..........................6
3.2.11 Random Number Generator ........................6
3.3 Power ................................7
3.3.1 Energy Management Unit (EMU) .......................7
3.3.2 DC-DC Converter ............................7
3.4 General Purpose Input/Output (GPIO)......................7
3.5 Clocking ................................7
3.5.1 Clock Management Unit (CMU) .......................7
3.5.2 Internal and External Oscillators .......................7
3.6 Counters/Timers and PWM .........................8
3.6.1 Timer/Counter (TIMER) ..........................8
3.6.2 Real Time Counter and Calendar (RTCC) ....................8
3.6.3 Low Energy Timer (LETIMER)........................8
3.6.4 Ultra Low Power Wake-up Timer (CRYOTIMER) .................8
3.6.5 Pulse Counter (PCNT) ..........................8
3.6.6 Watchdog Timer (WDOG) .........................8
3.7 Communications and Other Digital Peripherals ...................8
3.7.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) ..........8
3.7.2 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) ..........8
3.7.3 Inter-Integrated Circuit Interface (I2C) .....................9
3.7.4 Peripheral Reflex System (PRS) .......................9
3.8 Security Features.............................9
3.8.1 GPCRC (General Purpose Cyclic Redundancy Check) ...............9
3.8.2 Crypto Accelerator (CRYPTO)........................9
3.9 Analog ................................9
3.9.1 Analog Port (APORT) ..........................9
3.9.2 Analog Comparator (ACMP) ........................9
3.9.3 Analog to Digital Converter (ADC) ......................9
3.9.4 Digital to Analog Current Converter (IDAC) ...................10
Table of Contents 90
3.10 Reset Management Unit (RMU) .......................10
3.11 Core and Memory ............................10
3.11.1 Processor Core ............................10
3.11.2 Serial Flash .............................10
3.11.3 Memory System Controller (MSC) ......................10
3.11.4 Linked Direct Memory Access Controller (LDMA) .................10
3.12 Memory Map ..............................11
3.13 Configuration Summary ..........................12
4. Electrical Specifications .......................... 13
4.1 Electrical Characteristics ..........................13
4.1.1 Absolute Maximum Ratings ........................14
4.1.2 Operating Conditions ...........................15
4.1.2.1 General Operating Conditions .......................15
4.1.3 Thermal Characteristics ..........................16
4.1.4 DC-DC Converter ............................17
4.1.5 Current Consumption...........................19
4.1.5.1 Current Consumption 3.3 V without DC-DC Converter ...............19
4.1.5.2 Current Consumption 3.3 V using DC-DC Converter ...............20
4.1.5.3 Current Consumption Using Radio .....................21
4.1.6 Wake up times .............................22
4.1.7 Brown Out Detector ...........................22
4.1.8 Frequency Synthesizer Characteristics .....................23
4.1.9 2.4 GHz RF Transceiver Characteristics ....................24
4.1.9.1 RF Transmitter General Characteristics for the 2.4 GHz Band ............24
4.1.9.2 RF Receiver General Characteristics for the 2.4 GHz Band .............25
4.1.9.3 RF Transmitter Characteristics for Bluetooth Smart in the 2.4 GHz Band .........26
4.1.9.4 RF Receiver Characteristics for Bluetooth Smart in the 2.4 GHz Band..........28
4.1.9.5 RF Transmitter Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band ......30
4.1.9.6 RF Receiver Characteristics for 802.15.4 O-QPSK DSSS in the 2.4 GHz Band.......33
4.1.10 Modem Features ............................34
4.1.11 Oscillators ..............................35
4.1.11.1 LFXO ...............................35
4.1.11.2 HFXO ...............................36
4.1.11.3 LFRCO ..............................36
4.1.11.4 HFRCO and AUXHFRCO ........................37
4.1.11.5 ULFRCO ..............................37
4.1.12 Primary Flash Memory Characteristics ....................38
4.1.13 Serial Flash Memory Characteristics .....................38
4.1.14 GPIO................................39
4.1.15 VMON ...............................40
4.1.16 ADC ................................41
4.1.17 IDAC ................................44
4.1.18 Analog Comparator (ACMP) ........................46
4.1.19 I2C ................................48
4.1.20 USART SPI .............................50
4.2 Typical Performance Curves .........................51
4.2.1 Supply Current .............................52
4.2.2 DC-DC Converter ............................54
Table of Contents 91
4.2.3 Internal Oscillators............................56
4.2.4 2.4 GHz Radio .............................62
5. Typical Connection Diagrams ........................ 64
5.1 Power ................................64
5.2 RF Matching Networks ...........................65
5.3 Other Connections ............................65
6. Pin Definitions .............................. 66
6.1 EFR32MG1 QFN32 2.4 GHz Definition .....................66
6.1.1 EFR32MG1 QFN32 2.4 GHz GPIO Overview ..................73
6.2 Alternate Functionality Pinout ........................74
6.3 Analog Port (APORT) ...........................80
7. QFN32 Package Specifications........................ 84
7.1 QFN32 Package Dimensions.........................84
7.2 QFN32 PCB Land Pattern ..........................86
7.3 QFN32 Package Marking ..........................88
8. Revision History ............................. 89
8.1 Revision 1.0 ..............................89
8.2 Revision 0.95 ..............................89
8.3 Revision 0.2 ..............................89
Table of Contents .............................. 90
Table of Contents 92
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