intel. tel 8087 MATH COPROCESSOR @ Adds Arithmetic, Trigonometric, Exponential, and Logarithmic Instructions to the Standard 8086/8088 and 80186/80188 Instruction Set for All Data Types @ Available in 5 MHz (8087), 8 MHz (8087- 2) and 10 MHz (8087-1): 8 MHz 80186/ 80188 System Operation Supported with the 8087-1 m Adds 8 x 80-Bit Individually m CPU/8087 Supports 7 Data Types: 16-, Addressable Register Stack to the 32-, 64-Bit Integers, 32-, 64-, 80-Bit 8086/8088 and 80186/80188 Floating Point, and 18-Digit BCD Architecture Operands @ 7 Built-In Exception Handling Functions mw Compatible with IEEE Floating Point & MULTIBUS System Compatible Standard 754 Interface The Intel 8087 Math CoProcessor is an extension to the Intel 8086/8088 microprocessor architecture. When combined with the 8086/8088 microprocessor, the 8087 dramatically increases the processing speed of computer applications which utilize mathematical operations such as CAM, numeric controllers, CAD or graph- ics. The 8087 Math CoProcessor adds 68 mnemonics to the 8086 microprocessor instruction set. Specific 8087 math operations include logarithmic, arithmetic, exponential, and trigonometric functions. The 8087 supports integer, floating point and BCD data formats, and fully conforms to the ANSI/IEEE floating point standard. The 8087 is fabricated with HMOS ili technology and packaged in a 40-pin cerdip package. FRACTION pus PROGRAMMABLE SHIFTER INTERFACE MICROCODE ARITHMETIC CONTROL MODULE UNIT aS DATA REGISTER STACK 1 ADDRESSING & BUS TRACKING EXCEPTION POINTERS STATUS AODRESS Le | ne ees _l 205835-1 205835-2 Figure 1. 8087 Block Diagram Figure 2. 8087 Pin <; Configuration October 1989 3-90 Order Number: 205835-007intel 8087 Table 1. 8087 Pin Description Symbol | Type Name and Function AD15-ADO0| I/O | ADDRESS DATA: These lines constitute the time multiplexed memory address (T4) and data (T2, T3, Tw, T4) bus. AO is analogous to the BHE for the lower byte of the data bus, pins D7-D0. It is LOW during T, when a byte is to be transferred on the lower portion of the bus in memory operations. Eight-bit oriented devices tied to the lower half of the bus would normally use AO to condition chip select functions. These lines are active HIGH. They are input/output lines for 8087-driven bus cycles and are inputs which the 8087 monitors when the CPU is in control of the bus. A15~A8 do not require an address latch in an 8088/8087 or 80188/8087. The 8087 will supply an address for the T;-T4 period. A19/S6, \/O0 | ADDRESS MEMORY: During T, these are the four most significant address lines for A18/S5, memory operations. During memory operations, status information is available on these A17/S4, lines during Ta, T3, Tw, and T4. For 8087-controlied bus cycles, $6, S4, and S3 are A16/S3 reserved and currently one (HIGH), while S5 is always LOW. These lines are inputs which the 8087 monitors when the CPU is in control of the bus. BHE/S7 1/0 | BUS HIGH ENABLE: During T, the bus high enable signed (BHE) should be used to enable data onto the most significant half of the data bus, pins D15-D8. Eight-bit- oriented devices tied to the upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T, for read and write cycles when a byte is to be transferred on the high portion of the bus. The $7 status information is available during Ta, T3, Tw, and T,4. The signal is active LOW. S7 is an input which the 8087 monitors during the CPU-controlled bus cycles. 52, S1,50 | 1/O | STATUS: For 8087-driven, these status lines are encoded as follows: $2 S1 50 O(LOW) X X_ Unused 1(HIGH) O O Unused 1 QO 1 Read Memory 1 1 0 Write Memory 1 1 1 Passive Status is driven active during T4, remains vatid during T, and To, and is returned to the passive state (1, 1, 1) during T3 or during Ty when READY is HIGH. This status is used by the 8288 Bus Controller (or the 82188 Integrated Bus Controller with an 80186/ 80188 CPU) to generate all memory access control signals. Any change in S2, ST, or SO during T, is used to indicate the beginning of a bus cycle, and the return to the Passive state in T3 or Ty is used to indicate the end of a bus cycle. These signals are monitored by the 8087 when the CPU is in control of the bus. RQ/GTO 1/0 | REQUEST/GRANT: This request/grant pin is used by the 8087 to gain control of the local bus from the CPU for operand transfers or on behalf of another bus master. it must be connected to one of the two processor request/grant pins. The request/grant sequence on this pin is as follows: 1. A pulse one clock wide is passed to the CPU to indicate a local bus request by either the 8087 or the master connected to the 8087 RQ/GT1 pin. 2. The 8087 waits for the grant pulse and when it is received will either initiate bus transfer activity in the clock cycle following the grant or pass the grant out on the RQ/GT1 pin in this clock if the initial request was for another bus master. 3. The 8087 will generate a release pulse to the CPU one clock cycle after the completion of the last 8087 bus cycle or on receipt of the release pulse from the bus master on RQ/GT1. For 80186/80188 systems the same sequence applies except RQ/GT signals are converted to appropriate HOLD, HLDA signals by the 82188 Integrated Bus Controller. This is to conform with 80186/80188's HOLD, HLDA bus exchange protocol. Refer to the 82188 data sheet for further information. / 3-918087 Table 1. 8087 Pin Description (Continued) Symbol Type a intel. Name and Function RO/GT1 1/0 REQUEST/GRANT: This request/grant pin is used by another iocal bus master to force the 8087 to request the local bus. If the 8087 is not in control of the bus when the request is made the request/grant sequence is passed through the 8087 on the RQ/ GTO pin one cycle later. Subsequent grant and release pulses are aiso passed through the 8087 with a two and one clock delay, respectively, for resynchronization. RO/GT1 has an internal pullup resistor, and so may be left unconnected. If the 8087 has control of the bus the request/grant sequence is as follows: 1. A pulse 1 CLK wide from another local bus master indicates a jocal bus request to the 8087 (pulse 1). 2. During the 8087's next T, or T; a pulse 1 CLK wide from the 8087 to the requesting master (pulse 2) indicates that the 8087 has allowed the local bus to float and that it will enter the RQ/GT acknowledge state at the next CLK. The 8087's control unit is disconnected logically from the local bus during RQ/GT acknowledge. 3. A pulse 1 CLK wide from the requesting master indicates to the 8087 (pulse 3) that the RQ/GT request is about to end and that the 8087 can reciaim the local bus at the next CLK. Each master-master exchange of the local bus is a sequence of 3 pulses. There must be one dead CLK cycle after each bus exchange. Pulses are active LOW. For 80186/80188 system, the RQ/GT1 line may be connected to the 82188 Integrated Bus Controller. In this case, a third processor with a HOLD, HLDA bus exchange system may acquire the bus from the 8087. For this configuration, RQ/GT1 will only be used if the 8087 is the bus master. Refer to 82188 data sheet for further information. QS1, QSO QS1, QS0: QS1 and QSO provide the 8087 with status to allow tracking of the CPU instruction queue. Qsi aso 0 (LOW) 0 No Operation 0 1 First Byte of Op Code from Queue 1 (HIGH) 0 Empty the Queue 1 1 Subsequent Byte from Queue INT INTERRUPT: This line is used to indicate that an unmasked exception has occurred during numeric instruction execution when 8087 interrupts are enabled. This signal is typically routed to an 8259A for 8086/8088 systems and to INTO for 80186/80188 systems. INT is active HIGH. BUSY BUSY: This signal indicates that the 8087 NEU is executing a numeric instruction. It is connected to the CPUs TEST pin to provide synchronization. In the case of an unmasked exception BUSY remains active until the exception is cleared. BUSY is active HIGH. READY READY: READY is the acknowledgement from the addressed memory device that it will complete the data transfer. The RDY signal from memory is synchronized by the 8284A Clock Generator to form READY for 8086 systems. For 80186/80188 systems, RDY is synchronized by the 82188 Integrated Bus Controller to form READY. This signal is active HIGH. RESET RESET: RESET causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. RESET is internally synchronized. CLK CLOCK: The clock provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty cycle to provide optimized internal timing. Voc POWER: Vcc is the +5V power supply pin. GND GROUND: GND are the ground pins. NOTE: For the pin descriptions of the 8086, 8088, 80186 and 80188 CPUs, reference the respective data sheets (8086, 8088, 80186, 80188). 3-92intel. APPLICATION AREAS The 8087 provides functions meant specifically for high performance numeric processing requirements. Trigonometric, logarithmic, and exponential func- tions are built into the coprocessor hardware. These functions are essential in scientific, engineering, navigational, or military applications. The 8087 also has capabilities meant for business or commercial computing. An 8087 can process Binary Coded Decimal (BCD) numbers up to 18 digits with- out roundoff errors. It can also perform arithmetic on integers as large as 64 bits + 1018). PROGRAMMING LANGUAGE SUPPORT Programs for the 8087 can be written in Intels high- level languages for 8086/8088 and 80186/80188 Systems; ASM-86 (the 8086, 8088 assembly lan- guage), PL/M-86, FORTRAN-86, and PASCAL-86. RELATED INFORMATION For 8086, 8088, 80186 or 80188 details, refer to the respective data sheets. For 80186 or 80188 sys- tems, also refer to the 82188 Integrated Bus Con- troller data sheet. FUNCTIONAL DESCRIPTION The 8087 Math CoProcessors architecture is de- signed for high performance numeric computing in conjunction with general purpose processing. 8087 The 8087 is a numeric processor extension that pro- vides arithmetic and logical instruction support for a variety of numeric data types. It also executes nu- merous built-in transcendental functions (e.g., tan- gent and log functions). The 8087 executes instruc- tions as a coprocessor to a maximum mode CPU. It effectively extends the register and instruction set of the system and adds several new data types as well. Figure 3 presents the registers of the CPU + 8087. Table 2 shows the range of data types supported by the 8087. The 8087 is treated as an extension to the CPU, providing register, data types, control, and in- struction capabilities at the hardware tevel. At the programmers level the CPU and the 8087 are viewed as a single unified processor. System Configuration As a coprocessor to an 8086 or 8088, the 8087 is wired in parallel with the CPU as shown in Figure 4. Figure 5 shows the 80186/80188 system configura- tion. The CPU's status (SO-S2) and queue status lines (QSO0-QS1) enable the 8087 to monitor and decode instructions in synchronization with the CPU and without any CPU overhead. For 80186/80188 systems, the queue status signals of the 80186/ 80188 are synchronized to 8087 requirements by the 8288 Integrated Bus Controller. Once started, the 8087 can process in parailel with, and indepen- dent of, the host CPU. For resynchronization, the 8087's BUSY signal informs the CPU that the 8087 is executing an instruction and the CPU WAIT in- struction tests this signal to insure that the 8087 is ready to execute subsequent instructions. The 8087 can interrupt the CPU when it detects an error or exception. The 8087s interrupt request line is typi- cally routed to the CPU through an 8259A Program- mable Interrupt Controller for 8086, 8088 systems and INTO for 80186/80188. 79 SIGN 78 EXPONENT proc nee ---+es 8087 DATA FIELD 64 63 TAG FIELD o o1 SIGNIFICANO 18 CONTAOL REGISTER STATUS REGISTER TAG WORD + INSTRUCTION POINTER 1 DATAPOINTER 205835-3 Figure 3. CPU + 8087 Architecture 3-938087 The 8087 uses one of the request/grant lines of the 8086/8088 architecture (typically RQ/GT0) to ob- tain contro! of the local bus for data transfers. The other request/grant line is available for general sys- tem use (for instance by an I/O processor in LOCAL mode). A bus master can also be connected to the 8087s RQ/GT1 line. In this configuration the 8087 will pass the request/grant handshake signals be- tween the CPU and the attached master when the 8087 is not in control of the bus and will relinquish the bus to the master directly when the 8087 is in control. In this way two additional masters can be configured in an 8086/8088 system; one will share the 8086/8088 bus with the 8087 on a first-come first-served basis, and the second will be guaranteed to be higher in priority than the 8087. For 80186/80188 systems, ROQ/GTO and RQ/GT1 are connected to the corresponding inputs of the 82188 Integrated Bus Controller. Because the 80186/80188 has a HOLD, HLDA bus exchange protocol, an interface is needed which will translate RQ/GT signals to corresponding HOLD, HLDA sig- nals and vice versa. One of the functions of the 82188 IBC is to provide this translation. RQ/GTO is translated to HOLD, HLDA signals which are then directly connected to the 80186/80188. The RQ/ GT1 line is also translated into HOLD, HLDA signals (referred to as SYSHOLD, SYSHLDA signals) by the 82188 IBC. This allows a third processor (using a HOLD, HLDA bus exchange protocol) to gain control of the bus. intel. Unlike an 8086/8087 system, RQ/GT is only used when the 8087 has bus control. If the third processor requests the bus when the current bus master is the 80186/80188, the 82188 IBC will directly pass the request onto the 80186/80188 without going through the 8087. The third processor has the high- est bus priority in the system. !f the 8087 requests the bus while the third processor has bus control, the grant pulse will not be issued until the third proc- essor releases the bus (using SYSHOLD). In this configuration, the third processor has the highest priority, the 8087 has the next highest, and the 80186/80188 has the lowest bus priority. Bus Operation The 8087 bus structure, operation and timing are identical to all other processors in the 8086/8088 series (maximum mode configuration). The address is time multiplexed with the data on the first 16/8 lines of the address/data bus. A16 through A19 are time multiplexed with four status lines S3-S6. S3, S4 and S6 are always one (HIGH) for 8087-driven bus cycles while $5 is always zero (LOW). When the 8087 is monitoring CPU bus cycles (passive mode) S6 is also monitored by the 8087 to differentiate 8086/8088 activity from that of a local I/O: proces- sor or any other local bus master. (The 8086/8088 must be the only processor on the local bus to drive S6 LOW). S7 is multiplexed with and has the same value as BHE for ali 8087 bus cycles. Table 2. 8087 Data Types Data Most Significant Byte Range /Precision Formats 7 07 o7 ol7 o7 ol7 ol7 ol7 oj7 ol7 of Word Integer 104 16 Bits [lis Io| Two's Complement Short Integer 109 32 Bits ils1 Ig} Two's Complement Long Integer 1018 | 64 Bits [ls lol Complement PackedBCD | 1018 | 18 Digits |S| __D47Die ID Dol Short Real 10+38 | 24Bits |SIE7 EglFy _____Faa|Fo Implicit Long Real 10+308| 53 Bits |S|E1o Eol Fi Fso|Fo Implicit Temporary Real] 10+4932) 64 Bits SlE14 Eo|Fo Fea| Integer: | Packed BCD: ( 1)5(D17...D9) Real: ( 1)S(2E Bias) (FgeF 4...) bias = 127 for Short Real 1023 for Long Real 16383 for Temp Real 3-94intel. The first three status lines, SO-S2, are used with an 8288 bus controller or 82188 Integrated Bus Con- troller to determine the type of bus cycle being run: $2 S1 So 0 X X Unused 1 0 0 Unused 1 0 1 Memory Data Read 1 1 0 Memory Data Write 1 1 1 Passive (no bus cycle) Programming Interface The 8087 includes the standard 8086, 8088 instruc- tion set for general data manipulation and program control. It also includes 68 numeric instructions for extended precision integer, floating point, trigono- metric, logarithmic, and exponential functions. Sam- ple execution times for several 8087 functions are shown in Table 3. Overall performance is up to 100 times that of an 8086 processor for numeric instruc- tions. Any instruction executed by the 8087 is the com- bined result of the CPU and 8087 activity. The CPU and the 8087 have specialized functions and regis- ters providing fast concurrent operation. The CPU controls overall program execution while the 8087 uses the coprocessor interface to recognize and perform numeric operations. Table 2 lists the seven data types the 8087 supports and presents the format for each type. Internally, the 8087 holds all numbers in the temporary real format. Load and store instructions automatically convert operands represented in memory as 16-, 32-, or 64- bit integers, 32- or 64-bit fioating point numbers or 18-digit packed BCD numbers into temporary real format and vice versa. The 8087 also provides the capability to control round off, underflow, and over- flow errors in each calculation. Computations in the 8087 use the processor's regis- ter stack. These eight 80-bit registers provide the equivalent capacity of 20 32-bit registers. The 8087 register set can be accessed as a stack, with in- structions operating on the top one or two stack ele- ments, or as a fixed register set, with instructions operating on explicitly designated registers. Table 5 lists the 8087's instructions by class. All ap- pear as ESCAPE instructions to the host. Assembly language programs are written in ASM-86, the 8086, 8088 assembly language. 8087 Table 3. Execution Times for Selected 8086/8087 Numeric Instructions and Corresponding 8086 Emulation Approximate Execution Floating Point Time (18) Instruction 8086/8087 8086 (8 MHz Emulation Clock) Add/Subtract 10.6 1000 Multiply (Single Precision) 11.9 1000 Multiply (Extended Precision) 16.9 1312 Divide 24.4 2000 Compare -5.6 812 Load (Double Precision) -6.3 1062 Store (Double Precision) 13.1 750 Square Root 22.5 12250 Tangent 56.3 8125 Exponentiation 62.5 10687 NUMERIC PROCESSOR EXTENSION ARCHITECTURE As shown in Figure 1, the 8087 is internally divided into two processing elements, the control unit (CU) and the numeric execution unit (NEU). The NEU ex- ecutes all numeric instructions, while the CU re- ceives and decodes instructions, reads and writes memory operands and executes 8087 control in- structions. The two elements are able to operate in- dependently of one another, allowing the CU to maintain synchronization with the CPU while the NEU is busy processing a numeric instruction. Control Unit The CU keeps the 8087 operating in synchronization with its host CPU. 8087 instructions are intermixed with CPU instructions in a single instruction stream. The CPU fetches all instructions from memory; by monitoring the status (S0-S2, S6) emitted by the CPU, the control unit determines when an instruction is being fetched. The CPU monitors the data bus in parallel with the CPU to obtain instructions that per- tain to the 8087. 3-952 eo intel r-c4 INT | NTA 82598 | PIC | cuk eae ld Rovat Be oso QS! TEST | Se oes s08e MULTIMASTER 22 INTERFACE <=> SYSTEM sn Qs0 08) 6USY 38 COMPONENTS clock FG/GTo = GENERATOR CuK T cx 8087 INT Fa/en1 205835-4 Figure 4. 8086/8087, 8088/8087 System Configuration e087 "] RO/GT1 AQ/STo Q81 O80 BUSY INT AG/ET1 RO/GTo ast0 ___I 800) lees Test NTO osu anes a2188 aso O80 INTERFACE tec soveG/20188 COMPONENTS Bs HODA HLOA 3 wou! WOLD sys SVS UDA WOLD T pp |! r 71 j b--- | svsnovo | I AS 3 LH & ol sysiioa I fe * i K | ano IVY Ede 1 PROCESSOR | Li_~_--- al " 3 205835-5 Figure 5. 80186/8087, 80188/8087 System Configuration 3-96a intel. The CU maintains an instruction queue that is identi- cal to the queue in the host CPU. The CU automati- cally determines if the CPU is an 8086/80186 or an 8088/80188 immediately after reset (by monitoring the BHE/S7 line) and matches its queue length ac- cordingly. By monitoring the CPUs queue status lines (QS0, QS1), the CU obtains and decodes in- structions from the queue in synchronization with the CPU. A numeric instruction appears as an ESCAPE in- struction to the CPU. Both the CPU and 8087 de- code and execute the ESCAPE instruction together. The 8087 only recognizes the numeric instructions shown in Table 5. The start of a numeric operation is accomplished when the CPU executes the ESCAPE instruction. The instruction may or may not identify a memory operand. The CPU does, however, distinguish between ESC instructions that reference memory and those that do not. If the instruction refers to a memory operand, the CPU calculates the operands address using any one of its available addressing modes, and then per- forms a dummy read of the word at that location. (Any location within the 1M byte address space is allowed.) This is a normal read cycle except that the CPU ignores the data it receives. If the ESC instruc- tion does not contain a memory reference (e.g. an 8087 stack operation), the CPU simply proceeds to the next instruction. An 8087 instruction can have one of three memory reference options: (1) not reference memory; (2) load an operand word from memory into the 8087; or (3) store an operand word from the 8087 into memo- ry. If no memory reference is required, the 8087 sim- ply executes its instruction. If a memory reference is required, the CU uses a dummy read cycle initiat- ed by the CPU to capture and save the address that the CPU places on the bus. If the instruction is a load, the CU additionally captures the data word - when it becomes available on the local data bus. If data required is longer than one word, the CU imme- diately obtains the bus from the CPU using the request/grant protocol and reads the rest of the in- formation in consecutive bus cycles. In a store oper- ation, the CU captures and saves the store address as in a load, and ignores the data word that follows in the dummy read cycle. When the 8087 is ready to perform the store, the CU obtains the bus from the CPU and writes the operand starting at the spec- ified address. 8087 Numeric Execution Unit The NEU executes all instructions that involve the register stack; these include arithmetic, logical, tran- scendental, constant and data transfer instructions. The data path in the NEU is 84 bits wide (68 frac- tions bits, 15 exponent bits and a sign bit) which allows internal operand transfers to be performed at very high speeds. When the NEU begins executing an instruction, it activates the 8087 BUSY signal. This signal can be used in conjunction with the CPU WAIT instruction to resynchronize both processors when the NEU has completed its current instruction. Register Set The CPU + 8087 ragister set is shown in Figure 3. Each of the eight data registers in the 8087's regis- ter stack is 80 bits and is divided into fields corre- sponding to the 8087s temporary real data type. At a given point in time the TOP field in the control word identifies the current top-of-stack register. A push operation decrements TOP by 1 and loads a value into the new top register. A pop operation stores the value from the current top register and then increments TOP by 1. Like CPU stacks in mem- ory, the 8087 register stack grows down toward lower-addressed registers. Instructions may address the data registers either implicitly or explicitly. Many instructions operate on the register at the top of the stack. These instruc- tions implicitly address the register pointed to by the TOP. Other instructions allow the programmer to ex- plicitly specify the register which is to be used. Ex- plicit register addressing is top-relative. Status Word The status word shown in Figure 6 reflects the over- all state of the 8087; it may be stored in memory and then inspected by CPU code. The status word is a 16-bit register divided into fields as shown in Figure 6. The busy bit (bit 15) indicates whether the NEU is either executing an instruction or has an interrupt request pending (B= 1), or is idle (B=0). Several instructions which store and manipulate the status word are executed exclusively by the CU, and these do not set the busy bit themselves. 3-978087 intel. Pele be felelel lll [|=]"[* EXCEPTION FLAGS (1 = EXCEPTION HAS OCCURRED) INVALID OPERATION DENORMALIZED OPERAND ZEAO DIVIDE OVERFLOW UNDERFLOW PR (RESERVED) INTERRUPT REQUEST CONDITION CODE TOP OF STACK POINTER NEU BUSY NOTES: 2. See Table 3 for condition code interpretation. 3. Top Values: 000 = Register 0 is Top of Stack. 001 = Register 1 is Top of Stack. 111 = Register 7 is Top of Stack. 1. IR is set if any unmasked exception bit is set, cleared otherwise. 205835-6 Figure 6. 8087 Status Word The four numeric condition code bits (Co-Cg) are similar to flags in a CPU: various instructions update these bits to reflect the outcome of the 8087 opera- tions. The effect of these instructions on the condi- tion code bits is summarized in Table 4. Bits 14-12 of the status word point to the 8087 reg- ister that is the current top-of-stack (TOP) as de- scribed above. Bit 7 is the interrupt request bit. This bit is set if any unmasked exception bit is set and cleared other- wise. Bits 5-0 are set to indicate that the NEU has detect- ed an exception while executing an instruction. Tag Word The tag word marks the content of each register as shown in Figure 7. The principal function of the tag word is to optimize the 8087's performance. The tag word can be used, however, to interpret the con- tents of 8087 registers. Instruction and Data Pointers The instruction and data pointers (see Figure 8) are provided for user-written error handlers. Whenever the 8087 executes a math instruction, the CU saves the instruction address, the operand address (if present) and the instruction opcode. 8087 instruc- tions can store this data into memory. 15 0 TAG (7) TAG(6) TAG(5) TAG (4) TAG (3) TAG (2) TAG)(1) TAG (0) TAG VALUES: 00 = VALID 01 = ZERO 10 = SPECIAL 11 = EMPTY Figure 7. 8087 Tag Word 3-98intel 8087 Table 4a. Condition Code Interpretation ree C3 Co Ci Co Interpretation Compare, Test 0 0 x 0 ST > Source or 0 (FTST) 0 0 x 1 ST < Source or 0 (FTST) 1 0 x 0 ST = Source or 0 (FTST) 1 1 xX 1 ST is not comparable Remainder Qy 0 Qo Qo Complete reduction with three low bits of quotient (See Table 4b) U 1 U U Incomplete Reduction Examine 0 0 0 0 Valid, positive unnormalized 0 0 0 1 Invalid, positive, exponent = 0 0 0 1 0 Valid, negative, unnormalized 0 0 1 1 invalid, negative, exponent = 0 0 1 0 0 Valid, positive, normalized 0 1 0 1 Infinity, positive 0 1 1 0 Valid, negative, normalized 0 1 1 1 Infinity, negative a 1 0 0 0 Zero, positive 1 0 0 1 Empty 1 0 1 0 Zero, negative 1 0 1 1 Empty 1 1 0 0 Invalid, positive, exponent = 0 1 1 0 1 Empty 1 1 1 0 Invalid, negative, exponent = 0 1 1 1 1 Empty NOTES: 1. ST = Top of stack 2. X = value is not affected by instruction 3. U = value is undefined following instruction 4. Q, = Quotient bit n Table 4b. Condition Code Interpretation after FPREM Instruction As a MEMORY Function of Divided Vaiue OFFSET 16 0 Dividend Range Q2 Qy Qo CONTROL WORD +0 Dividend < 2 * Modulus C31 Cy! Qo STATUS WORD +2 Dividend < 4 * Modulus Cg! Qy Qo Dividend > 4*Modulus | Qo | Q; | Qo TAG WORD 4 INSTRUCTION POINTER (15-0) +6 NOTE: INSTRUCTION INSTRUCTION 1. Previous value of indicated bit, not affected by FPREM POINTER (19-16) 0 OPCODE (10-0) +8 instruction execution. DATA POINTER (15-0) +10 DATA POINTER (19-16) 0 +12 15 1211 0 Figure 8. 8087 instruction and Data Pointer image in Memory i 3-998087 Control Word The 8087 provides several processing options which are selected by loading a word from memory into the control word. Figure 9 shows the format and encod- ing of the fields in the control word. The low order byte of this control word configures 8087 interrupts and exception masking. Bits 5-0 of the control word contain individual masks for each of the six exceptions that the 8087 recognizes and bit 7 contains a general mask bit for all 8087 interrupts. The high order byte of the control word configures the 8087 operating mode including precision, round- ing, and infinity controls. The precision control bits (bits 9-8) can be used to set the 8087 internal oper- ating precision at less than the default of temporary real precision. This can be useful in providing com- patibility with earlier generation arithmetic proces- sors of smaller precision than the 8087. The round- ing control bits (bits 11-10) provide for directed rounding and true chop as well as the unbiased round to nearest mode specified in the proposed IEEE standard. Control over closure of the number space at infinity is also provided (either affine clo- sure, + , or projective closure, , is treated as unsigned, may be specified). intel. The 8087 detects six different exception conditions that can occur during instruction execution. Any or all exceptions will cause an interrupt if unmasked and interrupts are enabled. Exception Handling if interrupts are disabled the 8087 will simply contin- ue execution regardless of whether the host clears the exception. If a specific exception class is masked and that exception occurs, however, the 8087 will post the exception in the status register and perform an on-chip default exception handling procedure, thereby allowing processing to continue. The exceptions that the 8087 detects are the follow- ing: 1. INVALID OPERATION: Stack overflow, stack un- derflow, indeterminate form (0/0, % , etc.) or the use of a Non-Number (NAN) as an oper- and. An exponent value is reserved and any bit pattern with this value in the exponent field is termed a Non-Number and causes this exception. If this exception is masked, the 8087's default re- sponse is to generate a specific NAN called IN- DEFINITE, or to propagate already existing NANs as the calculation result. foe belle Del) ===>] | EXCEPTION MASKS {1 = EXCEPTION IS MASKED) INVALID OPERATION DENI IZED O1 ZERO DIVIDE OVERFLOW UNDERFLOW PRECISION (RESERVED) INTERRUPT MASK (1 = INTERRUPTS ARE MASKED) aN CONTROL" ROUNDING CONTROL INFINITY CONTROL (0 = PROJECTIVE, 1 = AFFINE) NOTES: 1. Precision Control 00 = 24 bits 2. Rounding Control 10 = 53 bits 10 11 = 64 bits 11 00 = Round to Nearest or Even 01 = Reserved 01 = Round Down (toward ) Round Up (toward + %) Chop (truncate toward zero) (RESERVED) 205835-7 Figure 9. 8087 Control Word 3-100intel. 2. OVERFLOW: The result is too large in magnitude to fit the specified format. The 8087 will generate an encoding for infinity if this exception is masked. 3. ZERO DIVISOR: The divisor is zero while the divi- dend is a non-infinite, non-zero number. Again, the 8087 will generate an encoding for infinity if this exception is masked. 4. UNDERFLOW: The result is non-zero but too small in magnitude to fit in the specified format. If this exception is masked the 8087 will denormal- ABSOLUTE MAXIMUM RATINGS* 8087 ize (shift right) the fraction until the exponent is in range. This process is called gradual! underflow. 5. DENORMALIZED OPERAND: At least one of the operands or the result is denormalized; it has the smallest exponent but a non-zero significand. Normal processing continues if this exception is masked off. 6. INEXACT RESULT: If the true result is not exactly representable in the specified format, the result is rounded according to the rounding mode, and this flag is set. If this exception is masked, processing will simply continue. NOTICE: This is a production data sheet. The specifi- Ambient Temperature Under Bias ...... OC to 70C cations are subject to change without notice. Storage Temperature .......... 65C to + 150C * WARNING: Stressing the device beyond the Absolute Voltage on Any Pin with Maximum Fiatings may cause permanent damage. Respect to Ground.............. 1.0V to +7V These are stress ratings only. Operation beyond the Power Dissipation............0..0..00005 3.0 Watt Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. D.C. CHARACTERISTICS T, = 0C to 70C, Voc = 5V 45% Symbol Parameter Min Max Units Test Conditions Vit Input Low Voltage 0.5 0.8 Vv Vin Input High Voitage 2.0 Voc + 0.5 Vv VoL Output Low Voltage (Note 8) 0.45 Vv lo, = 2.5mA Vou Output High Voltage 2.4 Vv lon = 400 pA loc Power Supply Current 475 mA Ta = 25C to Input Leakage Current +10 pA OV < Vin < Voc ILo Output Leakage Current +10 pA Ta = 25C Voi Clock Input Low Voltage 0.5 0.6 Vv Vou Clock Input High Voltage 3.9 Voc + 1.0 V Cin Capacitance of Inputs 10 pF fc = 1 MHz Cio Capacitance of |/O Buffer 15 pF fe = 1 MHz (ADO-15, AygAyg, BHE, S2-S0, RQ/GT) and CLK Court Capacitance of Outputs 10 pF fe = 1 MHz BUSY INT 3-1018087 A.C. CHARACTERISTICS Ty, = 0C to 70C, Voc = 5V +5% TIMING REQUIREMENTS intel. Symbol Parameter 8087 | 8087-2 (Gee Note 7) | Units| Test Conditions Min| Max] Min|Max} Min | Max TCLOL CLK Cycle Period 200] 5001251500; 100 | 500] ns TCLCH CLK Low Time 118 68 53 ns TCHCL CLK High Time 69 44 39 ns TCH1CH2 | CLK Rise Time 10 10 15 ns_ | From 1.0V to 3.5V TCL2CL2 | CLK Fall Time 10 10 15 ns_ | From 3.V to 1.0V TDVCL Data In Setup Time 30 20 15 ns TCLDX Data In Hold Time 10 10 10 ns TRYHCH | READY Setup Time 118 68 53 ns TCHRYX | READY Hold Time 30 20 5 ns TRYLCL | READY Inactive to CLK (Note 6)| 8 8 10 ns TGVCH =| RQ/GT Setup Time (Note 8) 30 15 15 ns TCHGX =| RQ/GT Hold Time 40 30 20 ns TQVCL QS0-1 Setup Time (Note 8) 30 30 30 ns TCLQX {| QS0-1 Hold Time 10 10 5 ns TSACH | Status Active Setup Time 30 30 30 ns TSNCL | Status Inactive Setup Time 30 30 30 ns TILIH Input Rise Time (Except CLK) 20 20 20 ns_ | From 0.8V to 2.0V TIHIL Input Fall Time (Except CLK) 12 12 15 ns_ | From 2.0V to 0.8V TIMING RESPONSES Symbol Parameter 8087 8087-2 (See Note 7) | Units| Test Conditions Min | Max | Min | Max | Min | Max TCLML |Command Active Delay | 10/0] 35/70| 10/0! 35/70| 10/0 }35/70| ns |Cy = 20-100 pF (Notes 1, 2) for all 8087 Outputs TCLMH | Command Inactive Delay | 10/0| 35/55] 10/0| 35/55| 10/0 |35/70| ns_ | (addition to 8087 (Notes 1, 2) self-load) TRYHSH | Ready Active to Status 110 65 45 ns Passive (Note 5) TCHSV | Status Active Delay 10 | 110 ; 10 60. 10 45 ns TCLSH | Status Inactive Delay 10 | 130 10 70 10 55 ns TCLAV | Address Valid Delay 10 | 110 | 10 60 10 55 ns TCLAX | Address Hold Time 10 10 10 ns 3-102i ntel 8087 A.C. CHARACTERISTICS T, = 0C to 70C, Voc = 5V +5% (Continued) TIMING RESPONSES (Continued) 8087-1 Symbol Parameter 8087 6067-2 (See Note 7) |Units| Test Conditions Min | Max | Min | Max| Min | Max TCLAZ {Address Float Delay TCLAX} 80 |TCLAX| 50 |TCLAX] 45 ns }C_ = 20-100 pF TSVLH [Status Valid to ALE High 15/30 15/30 15/30| ng_|for all 8087 Outputs (Notes 1, 2) (in acaion to 8087 TCLLH [CLK Low to ALE Valid 15/30 15/30 16/30| ns [Sot 1089) (Notes 1, 2) TCHLL |ALE Inactive Delay 15/30 15/30 15/30} ns (Notes 1, 2) TCLDV |Data Valid Delay 10 110 10 60 10 50 ns TCHDX |Status Hold Time 10 10 10 45 ns TCLDOX | Data Hold Time 10 10 10 ns TCVNV {Control Active Delay 5 45 5 45 5 45 ns (Notes 1, 3) TCVNX |Control Inactive Delay 10 45 10 45 10 45 ns (Notes 1, 3) TCHBV |BUSY and INT Valid Delay} 10 150 10 85 10 65 | ns TCHDTL | Direction Control Active 50 50 50 | ns Delay (Notes 1, 3) TCHDTH | Direction Control Inactive 30 30 30 ns Delay (Notes 1, 3) TSVDTV ISTATUS to DT/R Delay 0 30 0 30 0 30 | ns (Notes 1, 4) TCLOTV |DT/R Active Delay 0 55 0 55 0 55 | ns (Notes 1, 4) TCHDNV] DEN Active Delay 0 55 0 55 0 55 | ns (Notes 1, 4) TCHDNX| DEN Inactive Delay 5 55 5 55 5 55 ns (Notes 1, 4) TCLGL |RQ/GT Active Delay 0 85 0 50 0 38 | ns |C_=40 pF (in (Note 8) addition to 8087 TCLGH |RQ/GT Inactive Delay o | 85 | o | 50[ o | 45 | ng |Self-load) TOLOH {Output Rise Time 20 20 15 ns_ |From 0.8V to 2.0V TOHOL |Output Fall Time 12 12 12 | ns {From 2.0V to 0.8V NOTES: 1. Signal at 8284A, 8288, or 82188 shown for reference only. 2. 8288 timing/82188 timing. 3. 8288 timing. 4, 82188 timing. 5. Applies only to Tg and wait states. 6. Applies only to Ta state (8 ns into T3). 7. IMPORTANT SYSTEM CONSIDERATION: Some 8087-1 timing parameters are constrained relative to the corresponding 8086-1 specifications. Therefore, 8086-1 systems incorporating the 8087-1 should be designed with the 8087-1 specifica- tions. 8. Changes since last revision. | 3-1038087 intel . A.C. TESTING INPUT, OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 24 DEVICE UNDER 1.5 <- TEST POINTS +> 1.5 vest J C, = 100 pF 205835-8 . A.C. Testing: Inputs are driven at 2.4V for a Logic 1 and 0.45V for a Logic Oo. 205835-9 Cy Includes Jig Capacitance WAVEFORMS MASTER MODE (with 8288 references) WRITE CYCLE weet NOTES: 205835-10 1. All signals switch between Vo, and Vox unless otherwise specified. 2. READY is sampled near the end of To, Tz and Ty to determine if Tw machine states are to be inserted. 3. The local bus floats only if the 8087 is returning control to the 8086/8088. 4. ALE rises at later of (TSVLH, TCLLH). 5. Status inactive in state just prior to T4. 6. Signals at 8284A or 8288 are shown for reference only. 7. The issuance of 8288 command and control signals (MRDC, (MWTC, AMWC, and DEN) lags the active high 8288 CEN. 8. Alt timing measurements are made at 1.5V unless otherwise noted. 3-104 [i ntel 8087 WAVEFORMS (Continued) MASTER MODE (with 82188 references) VCH CLK wad RX TCLCH 8 ~7l---- $,,8,,8, UL, V/f see NOTE 5) wie eo we TCLav >| ror BHE/S,,A,,/8,-A,/8, J roat TSVLH-4 (SEE MOTE 3) TCLLH - ALE (82188 OUTPUT) (SEE NOTES 4,6) / READY (9087 IN TCHAYX see NOTE n r c TCLAV~ READ CYCLE FELOX AD,,-AO, { FLOAT TsvDTvy * \ _ TCLDTV om (SEE NOTE 9) > TCLML _ Tome | 62188 OUTPUTS AD a (SEE NOTES 6,7) * >] i TCHDNV > TCHDNX GEN x eF WRITE CYCLE TCLAV ToLoV w| | TeLD0x AD AD, Annee DATA OUT ror T ] F NOTE 3) TCHDNV } | t TCHDNX DEN $2188 OUTPUTS ee) gn To wa NOTES: 205835-11 . All signals switch between Vo_ and Vox unless otherwise specified. . READY is sampied near the end of To, Ts and Ty to determine if Tw machine states are to be inserted. . The local bus floats only if the 8087 is returning control to the 80186/80188. . ALE rises at later of (TSVLH, TCLLH). . Status inactive in state just prior to T4. . Signals at 8284A or 82188 are shown for reference only. . The issuance of 8288 command and control signals (MIDS, CEN. 8. All timing measurements are made at 1.5V unless otherwise noted. 9. DT/R becomes valid at the later of (TSVDTV, TCLDTV). [ 3-105 NOAA ON = (MWTC, AMWC, and DEN) lags the active high 82888087 intel : WAVEFORMS (Continued) PASSIVE MODE Tw CLK Qs,,a8, 8,,8,,8, TOVCL TCLOX BHE/S,,A,,/8,-A,,/S, BHE, Ais AD,,-AD, Ayn-Ay TRYLCL DATA IN READY TCHRYX nur) TCHRYX 205835-12 RESET TIMING }e--___ > 50 see _____ Voc }~~____- =20 CLK CYCLES cLK TCLOX TOVCL RESET \ 8087 TRACKS 8067 READY TO >4 CLK CYCLES CPU ACTIVITY EXECUTE INSTRUCTIONS 205835-13 3-106 |i ntel : 8087 WAVEFORMS (Continued) REQUEST/GRANTo TIMING >1 CLK 2=0CLK CYCLE CYCLE sr TGVCH Rav/ato AD,,-AD, A,,/8,-A,,/8, cpu 5,.5, a6 GHE/s7 an 205835-14 NOTE: The CPU provides active pullup of RQ/GTO0, see TCLGH spec. REQUEST/GRANT, TIMING >1CLK cycLte | cLK \ TGVCH-> TCHGX Ravers 2087 GT \nevease AD,,-AD, . oe TCLAZ ms Ay/8,-A,/8, 0087 . ALTERNATE MASTER 0067 aHt/s7 5 (SEE NOTE) 205835-15 NOTE: Alternate master may not drive the buses outside of the region shown without risking bus contention. BUSY AND INTERRUPT TIMING CLK \ \ BUSY, INT TCHBV j<| 1 205835-16 l 3-1078087 i n Table 5. 8087 Extensions to the 86/186 Instructions Sets Optional Clock Count Range 6,16 Bit a2Bit | 32Bit | 64 Bit | 18 Bit Data Transter Displacement Real | integer | Real | Integer FLD = LOAD | ME = 00 0 10 1 Integer/Real Memory to ST(0} [ESCAPE MF 1 | MOD 0 0 0 RM] DISP. | 38-56 52-60 40-60 46-54 soc s SER EA FEA O+EA Long Integer Memory to ST) [ESCAPE 1 1 1 | MOD 1 0 1 __ Disp 60-68 +EA Temporary Real Memoryto [ESCAPE 0 1 1 | MOD 101 AM| DIP | 53-65 +EA Sr 2.2 BISPL BCD Memory to ST(0) [escaPe 1 1 1 [| MoD 1 0 0 RM | ose! 290-310 +A ST(i) to ST(O) ESCAPE 0 0 1 14000 Sty 17-22 FST = STORE woe eee ee ST(0) to Integer/Reai Memory | ESCAPE ME 1 | MOD 0 1 0 nM | DISP | 84-90 82-92 96-104 80-90 aoe eee oe +EA +EA +EA +EA ST(0) to ST(i) | ESCAPE 404 | 11010 sti | 15-22 FSTP = STORE AND POP ool. ST(0) to integer/Real Memory | escape MF 1 | MOD 0 1 1 A | oISP i 86-92 84-94 98-106 82-92 TOI r + EA FEA +EA +EA ST(0) to Long integer Memory | ESCAPE +144 | MOD 1 1 4 Rm | Disp! 94-105 +EA ST(0) to Temporary Real [| ESCAPE o141 | MOD 11 1 RM | DISP i 52-58 +EA Memory nner mh a me $1(0) to BCD Memory [ ESCAPE 144 | MOD 1 1 0 a | oisP 520-540 +EA ST(0) to STH) [ EscaPe 104 | 110104 stii| 17-24 FXCH = Exchange ST(i) and | ESCAPE oo 1 | 11001 st] 40-15 ST(0} Comparison FCOM = Compare eee ee ee Integer/Real Memory to ST(Q) [escare MF 0 I MOD 0 1 0 am | DISP =} 60-70 78-91 65-75 72-86 costs e - +EA +EA +EA +EA ST(i) to ST (0) [escapee 000/11 010 sti | 40-50 FCOMP = Compare and Pop Integer/Real Memory to ST(0) | ESCAPE MF 0 | MOD 0 1 14 RIM DISP | 63-73 80-93 67-77 74-88 Te +EA +EA +EA +EA ST(i) to ST(O} ESCAPE 000/11 011 ST) 45-52 FCOMPP = Compare Sti}to [escaPe 110/11 011001 | 45-55 ST(0) and Pop Twice FTST = Test ST(0) [escaree 001/11 100100 | 38-48 FXAM = Examine ST(0) [escape 0 01[11 100101 | 12-23 205835-17 3-1081. If P = 1 then add 5 clocks. in 8087 Table 5. 8087 Extensions to the 86/186 Instructions Sets (Continued) Optional Clock Count Range 6,16 Bit s2e | s2et | eapit | 16 Bit Constants Displacement Real | Integer | Real | integer MF 00 01 10 "1 FLOZ = LOAD + 0.0intost(n) | ESCAPE 0 0 1 [1 1 110 | N-17 FLD1 = LOAD + 1.0into S70) [ ESCAPE 0 0 1 [1 1 00 0 | 15-21 FLOP! = LOAD 7 intost(o) [ESCAPE 0 0 1 [1 1 011 | 16-22 FLDL2T = LOAD loge 10 into [ ESCAPE 0 0 1 [1 1 oo | 16-22 ST(0) FLOL2E = LOAD iogaeinto [ ESCAPE 0 0 1 [1 1 o1o0 | 15-21 ST(0) FLDLG2 = LOAD 10919 2 into ST(0) [escape 001 [1 1 100 | 18-24 FLDLN2 = LOAD loge? into | ESCAPE 001 [1 1 10 1 | 17-23 ST(0) Arithmetic FADD = Addition / Integer/Real Memory with ST(0) | ESCAPE MF 0 | MoD RIM | DISP | 90-120 108-143 95-125 102-197 Tot +EA +EA +EA +EA ST{i) and ST(0) | ESCAPE apo|[t1 st | 70-100 (Note 1) FSUB = Subtraction Integer/Real Memory with ST(0) [ ESCAPE MF 0 | MOD RM | DISP | 90-120 108-143 95-125 102-137 cote +EA +EA +EA +EA ST(i) and ST(0) [ escare d PO | 14 IM | 70~100 (Note 1} FMUL = Multiplication aoe eee integer/Real Memory with ST(0) | ESCAPE MF 0 | MOD RM | DISP | 110-126 130-144 112-168 124-138 ces +EA +EA +EA +EA ST(i) and ST(0) [escare a po [1 1 | 90-145 (Note 1) FOIV=Division 2 e integer/Real Memory with ST(0) | ESCAPE MF 0 | mop AM | DISP. | 215-225 290-243 220-290 224-238 tore: - +EA +EA +EA +EA ST(i) and ST(0) [ escaPe a Po [1 1 RIM 193-203 (Note 1) FSQAT = Square Root of ST(0) | ESCAPE 0 0 1 | 1 1 010 | 180-186 FSCALE = Scale ST(0) by ST(1) | ESCAPE 0 0 1] 1 1 101 | 92-38 FPREM = Partie Remainder of | ESCAPE 0 0 1 | 1 1 000 | 15=190 ST(0) +ST(1) FRNDINT = Round ST(0)to [ ESCAPE 0 0 1 | 1 1 100 | 16-80 Integer 205835-18 NOTE: 3-1098087 [I n Table 5. 8087 Extensions to the 86/186 Instructions Sets (Continued) Optional Clock Count Range 6,16 Bit Displacement FXTRAGT - Extract [escare oo 1 [11 410100 | 27-55 Components of St(0)} FABS = Absolute Value of [ escaPe 0041 | 11100001 | 10-17 ST(0) FCHS = Change Sign of ST(0) [ ESCAPE 001 [ +1 100000 | 10-17 Transcendental FPTAN = Partial Tangent of [ ESCAPE 601 | t+ 11001 o | 30-540 ST(0) FPATAN = Partial Arctangent [ escape 001 [11 110011 | 250-800 of ST(0) = ST(1) Faxms = 2970) _y | ESCAPE 001 | 1111000 o | 310-630 FYL2X = ST(1}* Logo [escare 0 0 1[11 11000 1 | 900-1100 IST(O)I FYL2XP1 = ST(1)+ Loge [ ESCAPE 001 | 11111004 | 700-1000 {ST(0} +4] Processor Control! FINIT = Initialized 8087 [escaPe o 11/11 100011 | 2-8 FENI = Enable Interrupts [ ESCAPE 014 | 11710000 o | 2-8 FDIS! = Disable Interrupts | ESCAPE O14 [1 1100004 | 2-8 ..s FLDCW = Load Control Word [ ESCAPE 001 [mop 101 RM | ose | 7-14 +EA FSTCW = Store Control Word [escape 0 0 1 | MOD 111 RM | oOISP_ | 12-18 +EA FSTSW = Store Status Word [ ESCAPE 101 | MOD 1 1 1 RIM | pisP | 12-18 + EA FCLEX = ClearExceptions [ escaPE 0 11/1 41 10 001 0 | 2-8 FSTENV = Store Environment [ ESCAPE 0 0 1 [ MOD 110 RM | OISP | 40-50 +EA FLOENV = Load Environment [ESCAPE 0.0 1] MOD 100 AM | oISP | 35-45 +EA FSAVE = Save State [escape 101 | Mop 110 AM | oISP | 197 -207+EA FRSTOR = Restore State oc 107207+6A FINCSTP = Ir Stack Pointer [ escare 00% | 1149094 1 | 6-12 FDECSTP = Decrement Stack ESCAPE 0 0 1 | 111101 1 90 6-12 Pointer 205835-19 3-110*n = number of times CPU examines TEST line before 8087 lowers BUSY. intel 8087 Table 5. 8087 Extensions to the 86/186 instructions Sets (Continued) Clock Count Range FFREE < Free ST(i) | ESCAPE 101 | 41000 STi ] 9-16 ENOP = No Operation EscaPe 001/141 010000 | 10-16 FWAIT = CPU Walt for 8087 10011014 34+5n* 205835-20 NOTES: 1. a eo if mod = 00 then DISP = 0, disp-low and disp-high are absent if mod = 01 then DISP = disp-low sign-extended to 16-bits, disp-high is absent if mod = 10 then DISP = disp-high; disp-low if mod = 11 then r/m is treated as an ST(i) field . if r/m = 000 then EA = (BX) + (SI) + DISP if r/m = 001 then EA = (BX) + (Dl) + DISP if r/m = 010 then EA = (BP) + (S!) + DISP if r/m = 011 then EA = (BP) + (Di) + DISP if r/m = 100 then EA = (SI) + DISP if r/m = 101 then EA = (DI) + DISP if r/m = 110 then EA = (BP) + DISP ifr/m = 111 then EA = (BX) + DISP *except if mod = 000 and r/m = 110 then EA = disp-high; disp-tow. . MF = Memory Format 00-32-bit Real 01-32-bit Integer 10-64-bit Real 11-16-bit Integer ST(0) = Current stack top ST(i) = ith register below stack top . d = Destination ODestination is ST(0) 1Destination is ST(i) P = Pop ONo pop iPop ST(0) . R = Reverse: When d = 1 reverse the sense of R 0Destination (op) Source 1Source (op) Destination . For FSQRT: O < ST(0) < +0 For FSCALE: -215 < ST(1) < +215 and ST(1) integer For F2XM1: 0 < ST(0) < 2-1 For FYL2x: 0 < ST(O) < o0 < ST(1) < +0 For FYL2XP1: 0 < IST(O)I < (2 2)/2 2 < ST(1) < 0 For FPTAN: 0 < ST(O) < 7/4 For FPATAN: 0 < ST(0) < ST(1) < +0 3-111