March 2002 1/23
VIPer100/SP
-VIPer100A/ASP
SMPS PRIMARY I.C.
1
■ ADJUSTABLE SWITCHING FREQUENCY UP
TO 200 kHz
■ CURRENT MODE CONTROL
■ SOFT START AND SHUT DOWN CONTROL
■ AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (<1w TOTAL POWER
CONSUMPTION)
■ INTERNALLY TRIMMED ZENER REFERENCE
■ UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
■ INTEGRATED START-UP SUPPLY
■ AVALANCHE RUGGED
■ OVERTEMPERATURE PROTECTION
■ LOW STAND-BY CURRENT
■ ADJUSTABLE CURRENT LIMITATION
DESCRIPTION
VIPer100/100A, made using VIPower M0
Technology, combines on the same silicon chip a
state-of-the-art PWM circuit together with an
optimized high voltage avalanche rugged Vertical
Power MOSFET (620V or 700V / 3A).
Typical applications cover off line power supplies
with a secondary power capability of 50 W in wide
range condition and 100W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the possibility to operate in stand-by
mode without extra components.
TYPE VDSS InRDS(on)
VIPer100/SP 620V 3 A 2.5 Ω
VIPer100A/ASP 700V 3 A 2.8 Ω
BLOCK DIAGRAM
PENTAWATT HV PENTAWATT HV
1
10
PowerSO-10(022Y)
FC00231
VDD
OSC
COMP
DRAIN
SOURCE
13 V
UVLO
LOGIC
SECURITY
LATCH PWM
LATCH
FF
FF
R/S SQS
R1
R2 R3Q
OSCILLATOR
OVERTEMP.
DETECTOR
ERROR
AMPLIFIER_
+
0.5 V +
_1.7 µ s
DELAY 250 ns
BLANKING CURRENT
AMPLIFIER
ON/OFF
0.5V
1 V/A
_
+
+
_
4.5 V
2/23
VIPer100/SP - VIPer100A/ASP
ABSOLUTE MAXIMUM RATING
THERMAL DATA
(*) When mounted using the minimum recommended pad size on FR-4 board.
CONNECTION DIAGRAMS (Top View)
CURRENT AND VOLTAGE CONVENTIONS
Symbol Parameter Value Unit
VDS
Continuous Drain-Source Voltage (Tj=25 to 125°C)
for VIPer100/SP
for VIPer100A/ASP -0.3 to 620
-0.3 to 700 V
V
IDMaximum Current Internally limited A
VDD SupplyVoltage 0 to 15 V
VOSC Voltage Range Input 0 to VDD V
VCOMP Voltage Range Input 0 to 5 V
ICOMP Maximum Continuous Current ±2mA
V
esd Electrostatic Discharge (R=1.5kΩ; C=100pF) 4000 V
ID(AR)
Avalanche Drain-Source Current, Repetitive or Not Repetitive
(Tc=100°C; Pulse width limited by Tjmax; δ< 1%)
for VIPer100/SP
for VIPer100A/ASP
2
1.4 A
A
Ptot Power Dissipation at Tc=25ºC 82 W
TjJunction Operating Temperature Internally limited °C
Tstg Storage Temperature -65 to 150 °C
Symbol Parameter PENTAWATT HV PowerSO-10(*) Unit
Rthj-case Thermal Resistance Junction-case Max 1.4 1.4 °C/W
Rthj-amb. Thermal Resistance Ambient-case Max 60 50 °C/W
1
PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VCOMP
VOSC
VDD VDS
ICOMP
IOSC
IDD ID
FC00020
VIPer100/SP - VIPer100A/ASP
3/23
ORDERING NUMBERS
PINS FUNCTIONAL DESCRIPTION
DRAIN PIN:
Integrated Power MOSFET drain pin. It provides
internal bias current during start-up via an
integrated high voltage current source which is
switched off during normal operation. The device
is able to handle an unclamped current during its
normal operation, assuring self protection against
voltage surges, PCB stray inductance, and
allowing a snubberless operation for low output
power.
SOURCE Pin:
Power MOSFET source pin. Primary side circuit
common ground connection.
VDD Pin:
This pin provides two functions :
- It corresponds to the low voltage supply of the
control part of the circuit. If VDD goesbelow 8V,
the start-up current source is activated and the
output power MOSFET is switched off until the
VDD voltage reaches 11V. During this phase,
the internal current consumption is reduced,
the VDD pin is sourcing a current of about 2mA
and the COMP pin is shorted to ground. After
that, the current source is shut down, and the
device tries to start up by switching again.
- This pin is also connected to the error amplifier,
in order to allow primary as well as secondary
regulation configurations. In case of primary
regulation, an internal 13V trimmed reference
voltage is used to maintain VDD at 13V. For
secondary regulation, a voltage between 8.5V
and 12.5V will be put on VDD pin by transformer
design, in order to stuck the output of the
transconductance amplifier to the high state.
The COMP pin behaves as a constant current
source, and can easily be connected to the
output of an optocoupler. Note that any
overvoltage due to regulation loop failure is still
detected by the error amplifier through the VDD
voltage, which cannot overpass 13V. The
output voltagewill be somewhat higherthan the
nominal one, but still under control.
COMP PIN:
This pin provides two functions :
- It is the output of the error transconductance
amplifier, and allows for the connection of a
compensation network to provide the desired
transfer function of the regulation loop. Its
bandwidth can be easily adjusted to the
needed value with usual components value. As
stated above, secondary regulation
configurations are also implemented through
the COMP pin.
- When the COMP voltage is going below 0.5V,
the shut-down of the circuit occurs, with a zero
duty cycle for the power MOSFET. This feature
can be used to switch off the converter, and is
automatically activated by the regulation loop
(whatever is the configuration) to provide a
burst mode operation in case of negligible
output power or open load condition.
OSC PIN:
An Rt-Ctnetwork must be connected on that pin to
define the switching frequency. Note that despite
the connection of Rtto VDD, no significant
frequency change occurs for VDD varying from 8V
to 15V. It provides also a synchronisation
capability, when connected to an external
frequency source.
PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10
VIPer100
VIPer100A VIPer100 (022Y)
VIPer100A (022Y) VIPer100SP
VIPer100ASP
1
4/23
VIPer100/SP - VIPer100A/ASP
AVALANCHE CHARACTERISTICS
ELECTRICAL CHARACTERISTICS (Tj=25°C; VDD=13V, unless otherwise specified)
POWER SECTION
(1) On Inductive Load, Clamped.
SUPPLY SECTION
Symbol Parameter Max Value Unit
ID(AR)
Avalanche Current, Repetitive or Not Repetitive
(pulse widht limited by Tjmax; δ< 1%)
for VIPer100/SP
for VIPer100A/ASP (see fig.12)
2
1.4 A
A
E(AR) Single Pulse Avalanche Energy
(starting Tj=25ºC, ID=ID(ar)) (see fig.12) 60 mJ
Symbol Parameter Test Conditions Min Typ Max Unit
BVDSS Drain-Source Voltage ID=1mA; VCOMP=0V
for VIPer100/SP
for VIPer100A/ASP (seefig.5) 620
700 V
V
IDSS Off-State Drain Current VCOMP=0V; Tj=125°C
VDS=620Vfor VIPer100/SP
VDS=700Vfor VIPer100A/ASP 1
1mA
mA
RDS(on) Static Drain-Source
On Resistance
ID=2A
for VIPer100/SP
for VIPer100A/ASP
ID=2A; Tj=100°C
for VIPer100/SP
for VIPer100A/ASP
2.0
2.3 2.5
2.8
4.5
5.0
Ω
Ω
Ω
Ω
tfFall Time ID=0.2A; VIN=300V (1)
(See fig. 3) 100 ns
trRise Time ID=0.4A; VIN=300V (1)
(See fig. 3) 50 ns
Coss Output Capacitance VDS=25V 150 pF
Symbol Parameter Test Conditions Min Typ Max Unit
IDDch Start-Up Charging
Current VDD=5V; VDS=35V
(see fig. 2 and fig. 15) -2 mA
IDD0 Operating Supply Current VDD=12V; FSW=0kHz
(see fig. 2) 12 16 mA
IDD1 Operating Supply Current VDD=12V; Fsw=100kHz 15.5 mA
IDD2 Operating Supply Current VDD=12V; Fsw=200kHz 19 mA
VDDoff UndervoltageShutdown (See fig. 2) 7.5 8 9 V
VDDon Undervoltage Reset (See fig. 2) 11 12 V
VDDhyst Hysteresis Start-up (See fig. 2) 2.4 3 V
VIPer100/SP - VIPer100A/ASP
5/23
ELECTRICAL CHARACTERISTICS (continued)
OSCILLATOR SECTION
ERROR AMPLIFIER SECTION
PWM COMPARATOR SECTION
SHUTDOWN AND OVERTEMPERATURE SECTION
Symbol Parameter Test Conditions Min Typ Max Unit
FSW Oscillator Frequency
Total Variation
RT=8.2KΩ;C
T
=2.4nF
VDD=9 to 15V;
with RT±1%; CT±5%
(see fig. 6 and fig. 9)
90 100 110 kHz
VOSCIH Oscillator Peak Voltage 7.1 V
VOSCIL Oscillator Valley Voltage 3.7 V
Symbol Parameter Test Conditions Min Typ Max Unit
VDDREG VDD Regulation Point ICOMP=0mA (see fig. 1) 12.6 13 13.4 V
∆VDDreg Total Variation Tj=0 to 100°C2%
G
BW Unity Gain Bandwidth From Input =VDD to Output = VCOMP
COMP pin is open (seefig. 10) 150 kHz
AVOL Open Loop Voltage Gain COMP pin is open (seefig. 10) 45 52 dB
GmDC Transconductance VCOMP=2.5V (see fig. 1) 1.1 1.5 1.9 mA/V
VCOMPLO Output Low Level ICOMP=-400µA; VDD=14V 0.2 V
VCOMPHI Output High Level ICOMP=400µA; VDD=12V 4.5 V
ICOMPLO Output Low Current
Capability VCOMP=2.5V; VDD=14V -600 µA
ICOMPHI Output High Current
Capability VCOMP=2.5V; VDD=12V 600 µA
Symbol Parameter Test Conditions Min Typ Max Unit
HID ∆VCOMP /∆IDPEAK VCOMP=1 to 3 V 0.7 1 1.3 V/A
VCOMPoff VCOMP Offset IDPEAK=10mA 0.5 V
IDpeak Peak Current Limitation VDD=12V; COMP pin open 3 4 5.3 A
tdCurrent Sense Delay to
Turn-Off ID=1A 250 ns
tbBlanking Time 250 360 ns
ton(min) Minimum On Time 350 ns
Symbol Parameter Test Conditions Min Typ Max Unit
VCOMPth Restart Threshold (see fig. 4) 0.5 V
tDISsu Disable SetUp Time (see fig. 4) 1.7 5 µs
Ttsd Thermal Shutdown
Temperature (See fig. 8) 140 170 °C
Thyst Thermal Shutdown
Hysteresis (See fig. 8) 40 °C
6/23
VIPer100/SP - VIPer100A/ASP
Figure 3: Transition Time Figure 4: Shut Down Action
Figure 5: Breakdown Voltage Vs. Temperature Figure 6: Typical FrequencyVariation
Figure 1: VDD Regulation Point Figure 2: Undervoltage Lockout
ICOMP
ICOMPHI
ICOMPLO VDDreg
0VDD
Slope =
Gm in mA/V
FC00150
VDDon
IDDch
IDD0
VDD
VDDoff
VDS=35V
Fsw = 0
IDD
VDDhyst
FC00170
ID
VDS
t
t
tf tr
10%Ipeak
10%VD
90%VD
FC00160
VCOMP
VOSC
ID
t
tDISsu
t
t
ENABLE DISABLEENABLE
VCOMPth
FC00060
Temperature (°C)
FC00180
0 20 40 60 80 100 120
0.95
1
1.05
1.1
1.15
BVDSS
(Normalized)
Temperature(°C)
0 20 40 60 80 100 120 140
-5
-4
-3
-2
-1
0
1FC00190
(%)
VIPer100/SP - VIPer100A/ASP
7/23
Figure 7: Start-Up Waveforms
Figure 8: Overtemperature Protection
SC10191
TJ
Ttsd-Thyst
Ttsc
Vdd
Vddon
Vddoff
Id
Vcomp
t
t
t
t
8/23
VIPer100/SP - VIPer100A/ASP
Figure 9: Oscillator
1
Rt
Ct
OSC
VDD
~360Ω
CLK
FC00050
1 2 3 5 10 20 30 50
30
50
100
200
300
500
1,000
Rt(kΩ)
Frequency (kHz)
Oscillator frequency vs Rt and Ct
Ct= 1.5 nF
Ct =2.7 nF
Ct= 4.7nF
Ct= 10 nF
FC00030FC00030
For Rt>1.2KΩ
and
Ct≥ 15nF if FSW ≤ 40KHz
FSW 2.3
RtCt
------------ 1550
Rt150–
----------------------
–
⋅=
C
t
Fsw
40kHz
15nF
22nF
Forbiddenarea
Forbiddenarea
Ct(nF) = Fsw(kHz)
880
VIPer100/SP - VIPer100A/ASP
9/23
Figure 10: Error Amplifier Frequency Response
Figure 11: Error Amplifier Phase Response
1
0.001 0.01 0.1 1 10 100 1,000
(20)
0
20
40
60
Frequency (kHz)
VoltageGain (dB)
RCOMP= +∞
RCOMP= 270k
RCOMP= 82k
RCOMP= 27k
RCOMP= 12k
FC00200
0.001 0.01 0.1 1 10 100 1,000
(50)
0
50
100
150
200
Frequency (kHz)
Phase (°)
RCOMP= +∞
RCOMP= 270k
RCOMP = 82k
RCOMP = 27k
RCOMP = 12k
FC00210
10/23
VIPer100/SP - VIPer100A/ASP
Figure 12: Avalanche Test Circuit
1
FC00195
U1
VIPer100
13V
OSC
COMP SOURCE
DRAINVDD
-
+
23
54
1
R3
100
R2
1k
BT2
12V
C1
47uF
16V
Q1
2 x STHV102FI in parallel
R1
47
L1
1mH
GENERATORINPUT
500us PULSE
BT1
0 to 20V
11/23
VIPer100/SP - VIPer100A/ASP
1
Figure 13: Off Line Power Supply With Auxiliary Supply Feedback
Figure 14: Off Line Power Supply With Optocoupler Feedback
ACIN +Vcc
GND
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9C7
L2
R3
C6
C5
R2
U1
VIPer100
-
+
13V
OSC
COMP SOURCE
DRAINVDD
FC00081
C11
FC00091
AC IN
F1
BR1
D3
R9
C1
R7
C4
C2
TR2
R1
C3
D1
D2
C10
TR1
C9C7
L2 +Vcc
GND
C8
C5
R2
U1
VIPer100
U2
R4
R5
ISO1 R6
R3
C6
-
+
13V
OSC
COMP SOURCE
DRAINVDD
C11
12/23
VIPer100/SP - VIPer100A/ASP
OPERATION DESCRIPTION:
CURRENT MODE TOPOLOGY:
The current mode control method, like the one
integrated in the VIPer100/100A uses two control
loops - an inner current control loop and an outer
loop for voltage control. When the Power
MOSFET output transistor is on, the inductor
current (primary side of the transformer) is
monitored with a SenseFET technique and
converted into a voltage VSproportional to this
current. When VSreaches VCOMP (the amplified
output voltage error) the power switch is switched
off. Thus, the outer voltage control loop defines
the level at which the inner loop regulates peak
current through the power switch and the primary
winding of the transformer.
Excellent open loop D.C. and dynamic line
regulation is ensured due to the inherent input
voltage feedforward characteristic of the current
mode control. This results in an improved line
regulation, instantaneous correction to line
changes and better stability for the voltage
regulation loop.
Current mode topology also ensures good
limitation in the case of short circuit. During a first
phase the output current increases slowly
following the dynamic of the regulation loop. Then
it reaches the maximum limitation current
internally set and finally stops because the power
supply on VDD is no longer correct. For specific
applications the maximum peak current internally
set can be overridden by externally limiting the
voltage excursion on the COMPpin. An integrated
blanking filter inhibits the PWM comparator output
for a short time after the integrated Power
MOSFET is switched on. This function prevents
anomalous or premature termination of the
switching pulse in the case of current spikes
caused by primary side capacitance or secondary
side rectifier reverse recovery time.
STAND-BY MODE
Stand-by operation in nearly open load condition
automatically leads to a burst mode operation
allowing voltage regulation on the secondary side.
The transition from normal operation to burst
mode operation happens for a power PSTBY given
by :
Where:
LPis the primary inductance of the transformer.
FSW is the normal switching frequency.
ISTBY is the minimum controllable current,
corresponding to the minimum on time that the
device is able to provide in normal operation. This
current can becomputed as :
tb+t
dis the sum of the blanking time and of the
propagation time of the internal current sense and
comparator, and represents roughly the minimum
on time of the device. Note that PSTBY may be
affected by the efficiency of the converter at low
load, and must include the power drawn on the
primary auxiliary voltage.
As soon as the power goes below this limit, the
auxiliary secondary voltage starts to increase
above the 13V regulation level forcing the output
voltage of the transconductance amplifier to low
state (VCOMP <V
COMPth). This situation leads to
the shutdown mode where the power switch is
maintained in the off state, resulting in missing
cycles and zero duty cycle. As soon as VDD gets
back to the regulation level and the VCOMPth
threshold is reached, the device operates again.
The above cycle repeats indefinitely, providing a
burst mode of which the effective duty cycle is
much lowerthan the minimum one when in normal
operation. The equivalent switching frequency is
also lower than the normal one, leading to a
reduced consumption on the input mains lines.
This mode of operation allows the VIPer100/100A
to meet the new German ”Blue Angel” Norm with
less than 1W total power consumption for the
system when working in stand-by. The output
voltage remains regulated around the normal
level, with a low frequency ripple corresponding to
the burst mode. The amplitude of this ripple is low,
because of the output capacitors and of the low
output current drawn in such conditions.The
normal operation resumes automatically when the
power get back to higher levels than PSTBY.
HIGH VOLTAGE START-UP CURRENT
SOURCE
An integrated high voltage currentsource provides
a bias current from the DRAIN pin during the start-
up phase. This current is partially absorbed by
internal control circuits which are placed into a
standby mode with reduced consumption and also
provided tothe external capacitor connected to the
VDD pin. As soon as the voltage on this pin
reaches the high voltage threshold VDDon of the
UVLO logic, the device turns into active mode and
starts switching.
PSTBY 1
2
--- LPI2STBYFSW
=
ISTBY tbtd
+()V
IN
LP
--------------------------------
=
13/23
VIPer100/SP - VIPer100A/ASP
The start up current generator is switched off, and
the converter should normally provide the needed
current on the VDD pin through the auxiliary
winding of the transformer, as shown on figure 15.
In case of abnormal condition where the auxiliary
winding is unableto provide the low voltage supply
current to the VDD pin (i.e. short circuit on the
output of the converter), the external capacitor
discharges itself down to the low threshold voltage
VDDoff of the UVLO logic, and the device get back
to the inactive state where the internal circuits are
in standby mode and the start up current sourceis
activated. The converter enters a endless start up
cycle, with a start-up duty cycle defined by the
ratio of charging current towards dischargingwhen
the VIPer100/100A tries to start. This ratio is fixed
by design to 2 to 15, which gives a 12% start up
duty cycle while the power dissipation at start up is
approximately 0.6 W, for a 230 Vrms input voltage.
This low value of start-up duty cycle prevents the
stress of the output rectifiers and of the
transformer when in short circuit.
The external capacitor CVDD on the VDD pin must
be sized according to the time needed by the
converter to start up, when the device starts
switching. This time tSS depends on many
parameters, among which transformer design,
output capacitors, soft start feature and
compensation network implemented on the COMP
pin. Thefollowing formulacan be used for defining
the minimum capacitor needed:
where:
IDD is the consumption current on the VDD pin
when switching. Refer to specified IDD1 and IDD2
values.
tSS is the start up time of the converter when the
device begins to switch. Worst case is generally at
full load.
VDDhyst is the voltage hysteresis of the UVLO
logic. Refer to the minimum specified value.
Soft start feature can be implemented on the
COMP pinthrough a simple capacitor which will be
also used as the compensation network. In this
case, the regulation loop bandwidth is rather low,
because of the large value of this capacitor. In
case a large regulation loop bandwidth is
mandatory, the schematics of figure 16 can be
used. It mixes a high performance compensation
network together with a separate high value soft
start capacitor. Both soft start time and regulation
loop bandwidth can be adjusted separately.
If the device is intentionally shut down by putting
the COMP pin to ground, the device is also
performing start-up cycles, and the VDD voltage is
oscillating between VDDon and VDDoff.
This voltage can be used for supplying external
functions, provided that their consumption doesn’t
exceed 0.5mA. Figure 17 shows a typical
application of this function, with a latched shut
down. Once the ”Shutdown” signal has been
activated, the device remains in the off state until
the input voltage is removed.
CVDD IDDtSS
VDDhyst
--------------------------
>
Figure 15: Behaviour of the high voltage current source at start-up
Ref.
UNDERVOLTAGE
LOCK OUT LOGIC
15 mA1mA
3mA
2mA
15 mA
VDD DRAIN
SOURCE
VIPer100
Auxiliary primary
winding
VDD
t
VDDoff
VDDon
Start up duty cycle ~ 12%
CVDD
FC00100
14/23
VIPer100/SP - VIPer100A/ASP
TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer100/100A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (ICOMP) versuschange in
input voltage (VDD). Thus:
The output impedance ZCOMP at the output of this
amplifier (COMP pin) can be defined as:
This last equation shows that the open loop gain
AVOL can be related to Gmand ZCOMP:
AVOL =G
mxZ
COMP
where Gmvalue for VIPer100/100A is 1.5 mA/V
typically.
Gmis well defined by specification, but ZCOMP and
therefore AVOL are subject to large tolerances. An
impedance Z can be connected between the
COMP pin and ground in order to define more
accurately the transfer function F of the error
amplifier, according to the following equation, very
similar to the one above:
F(S) = Gm x Z(S)
The error amplifier frequency response is reported
in figure 10 for different values of a simple
resistance connected on the COMP pin. The
unloaded transconductance error amplifier shows
an internal ZCOMP of about 330 KΩ. More complex
impedance can be connected on the COMP pin to
achieve different compensation laws. A capacitor
will provide an integrator function, thus eliminating
the DC static error, and a resistance in series
leads to a flat gain at higher frequency, insuring a
correct phase margin. This configuration is
illustrated on figure 18.
As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any high frequency interference.
It can be also interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
EXTERNAL CLOCK SYNCHRONIZATION:
The OSC pin provides a synchronisation
capability, when connected to an external
frequency source. Figure 20 shows one possible
schematic to be adapted depending the specific
needs. If the proposed schematic is used, the
pulse duration must be kept at a lowvalue (500ns
is sufficient) for minimizing consumption. The
optocoupler mustbe able to provide20mA through
the optotransistor.
PRIMARY PEAK CURRENT LIMITATION
The primary IDPEAK current and, as resulting
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuitbased
on Q1, R1and R2clamps the voltage on the
Gm∂ICOMP
∂VDD
------------------------
=
ZCOMP ∂VCOMP
∂ICOMP
--------------------------- 1
m
G
--------- ∂VCOMP
∂VDD
---------------------------
×==
Figure 16: Mixed Soft Start and Compensation Figure 17: Latched Shut Down
AUXILIARY
WINDING
-
+
13V
OSC
COMP SOURCE
DRAINVDD
U1
VIPER100
R1
C1 +C2
D1
R2
R3
D2
D3
+C3
FC00131
C4
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
Shutdown
U1
Q1
Q2
R1
R2R3
R4 D1
FC00110
15/23
VIPer100/SP - VIPer100A/ASP
COMP pin in order to limit the primary peak
current of the device to a value:
where:
The suggested value for R1+R2is in the range of
220KΩ.
OVER-TEMPERATURE PROTECTION:
Over-temperature protection is based on chip
temperature sensing. The minimum junction
temperature at which over-temperature cut-out
occurs is 140ºC while the typical value is 170ºC.
The device is automatically restarted when the
junction temperature decreases to the restart
temperature threshold that is typically 40ºC below
the shutdown value (see figure 8).
IDPEAK VCOMP 0.5–
HID
-------------------------------------
=
VCOMP 0.6 R1R2
+
R2
----------------------
×=
Figure 18: Typical Compensation Network
Figure 20: External Clock Sinchronisation
Figure 19: Slope Compensation
Figure 21: Current Limitation Circuit Example
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
U1
R1
C1
FC00121
C2
FC00141
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
R1R2
Q1
C2
C1 R3
U1
C3
-
+
13V
OSC
COMP SOURCE
DRAINVDD
U1
VIPER100
10 kΩ
FC00220
-
+
13V
OSC
COMP SOURCE
DRAINVDD
VIPER100
U1
R1
R2
Q1
FC00240
16/23
VIPer100/SP - VIPer100A/ASP
Figure 22: Input Voltage Surges Protection
ELECTRICAL OVER STRESS RUGGEDNESS
The VIPer may be submitted to electrical over
stress caused by violent input voltage surges or
lightning. Following the enclosed Layout
Considerations chapter rules is the most of the
time sufficient to prevent catastrophic damages,
however in some cases the voltage surges
coupled through the transformer auxiliary winding
can overpass the VDD pin absolute maximum
rating voltage value. Such events may trigger the
VDD internal protection circuitry which could be
damaged by the strong discharge current of the
VDD bulk capacitor. The simple RC filter shown in
figure 22 can be implemented to improve the
application immunity to such surges.
C1
Bulk capacitor
D1
R1
(Optional)
C2
22nF
Auxilliary winding
13V
OSC
COMPSOURCE
DRAIN
VDD
-
+
VIPerXX0
R2
39R
17/23
VIPer100/SP - VIPer100A/ASP
1
Figure 23: Recommended Layout
LAYOUT CONSIDERATIONS
Some simple rules insure a correct running of
switching power supplies. They may be classified
into two categories:
- Tominimise power loops: the way the switched
power current must be carefully analysed and
the corresponding paths must present the
smallest inner loop area as possible. This
avoids radiated EMC noises, conducted EMC
noises by magnetic coupling, and provides a
better efficiency by eliminating parasitic
inductances, especially on secondary side.
- To usedifferent tracks for low level signals and
power ones. The interferences due to a mixing
of signal and power may result in instabilities
and/or anomalous behaviour of the device in
case of violent power surge (Input overvoltages,
output short circuits...).
In case of VIPer, these rules apply as shown on
figure 23.The loops C1-T1-U1, C5-D2-T1, C7-D1-
T1 must be minimised. C6 must be as close as
possible from T1. The signal components C2,
ISO1, C3 and C4 are using a dedicated track to be
connected directly to the source of the device.
T1
U1
VIPerXX0
13V
OSC
COMP SOURCE
DRAINVDD
-
+
C4
C2
C5
C1
D2
R1
R2
D1
C7
C6
C3
ISO1
)URP LQSXW
GLRGHV EULGJH
7R VHFRQGDU\
ILOWHULQJ DQG ORDG
FC00500
18/23
VIPer100/SP - VIPer100A/ASP
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 3.35 3.65 0.132 0.144
A (*) 3.4 3.6 0.134 0.142
A1 0.00 0.10 0.000 0.004
B 0.40 0.60 0.016 0.024
B (*) 0.37 0.53 0.014 0.021
C 0.35 0.55 0.013 0.022
C (*) 0.23 0.32 0.009 0.0126
D 9.40 9.60 0.370 0.378
D1 7.40 7.60 0.291 0.300
E 9.30 9.50 0.366 0.374
E2 7.20 7.60 0.283 300
E2 (*) 7.30 7.50 0.287 0.295
E4 5.90 6.10 0.232 0.240
E4 (*) 5.90 6.30 0.232 0.248
e 1.27 0.050
F 1.25 1.35 0.049 0.053
F (*) 1.20 1.40 0.047 0.055
H 13.80 14.40 0.543 0.567
H (*) 13.85 14.35 0.545 0.565
h 0.50 0.002
L 1.20 1.80 0.047 0.070
L (*) 0.80 1.10 0.031 0.043
α0º 8º 0º 8º
α (*) 2º 8º 2º 8º
PowerSO-10MECHANICAL DATA
(*) Muar only POA P013P
DETAIL ”A”
PLANE
SEATING
α
L
A1
F
A1
h
A
D
D1
==
==
E4
0.10 A
C
A
B
B
DETAIL ”A”
SEATING
PLANE
E2
10
1
eB
HE
0.25
P095A
19/23
VIPer100/SP - VIPer100A/ASP
11
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.11
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 15.60 17.30 6.14 0.681
L1 14.60 15.22 0.575 0.599
L2 21.20 21.85 0.835 0.860
L3 22.20 22.82 0.874 0.898
L5 2.60 3 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 4.50 5.60 0.177 0.220
R 0.50 0.02
V4 90°(typ)
Diam 3.65 3.85 0.144 0.152
P023H3
PENTAWATT HV MECHANICAL DATA
20/23
VIPer100/SP - VIPer100A/ASP
1
A
C
H2
H3
H1
L5
DIA
L3
L6
L7
F
G1
G2
LL1
D
R
M
M1
EResinbetween
leads
V4
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 4.30 4.80 0.169 0.189
C 1.17 1.37 0.046 0.054
D 2.40 2.80 0.094 0.110
E 0.35 0.55 0.014 0.022
F 0.60 0.80 0.024 0.031
G1 4.91 5.21 0.193 0.205
G2 7.49 7.80 0.295 0.307
H1 9.30 9.70 0.366 0.382
H2 10.40 0.409
H3 10.05 10.40 0.396 0.409
L 16.42 17.42 0.646 0.686
L1 14.60 15.22 0.575 0.599
L3 20.52 21.52 0.808 0.847
L5 2.60 3.00 0.102 0.118
L6 15.10 15.80 0.594 0.622
L7 6.00 6.60 0.236 0.260
M 2.50 3.10 0.098 0.122
M1 5.00 5.70 0.197 0.224
R 0.50 0.020
V4 90°90°
Diam. 3.70 3.90 0.146 0.154
PENTAWATT HV 022Y (VERTICAL HIGH PITCH) MECHANICAL DATA
21/23
VIPer100/SP - VIPer100A/ASP
1
PowerSO-10SUGGESTED PAD LAYOUT
1
TAPE AND REEL SHIPMENT (suffix “13TR”)
REEL DIMENSIONS
All dimensions are in mm.
Base Q.ty 600
Bulk Q.ty 600
A (max) 330
B (min) 1.5
C(±0.2) 13
F20.2
G (+ 2 / -0) 24.4
N (min) 60
T (max) 30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
All dimensions are in mm.
Tape width W 24
Tape Hole Spacing P0 (±0.1) 4
Component Spacing P 24
Hole Diameter D (±0.1/-0) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (±0.05) 11.5
Compartment Depth K (max) 6.5
Hole Spacing P1 (±0.1) 2
Top
cover
tape
End
Start
NocomponentsNocomponents Components
500mm min 500mm min
Emptycomponents pockets
saled withcovertape.
User directionof feed
6.30
10.8- 11
14.6-14.9
9.5
1
2
3
4
51.27
0.67-0.73
0.54-0.6
10
9
8
7
6
B
A
C
All dimensions are in mm.
Base Q.ty Bulk Q.ty Tube length (±0.5) A B C (±0.1)
Casablanca 50 1000 532 10.4 16.4 0.8
Muar 50 1000 532 4.9 17.2 0.8
TUBE SHIPMENT (no suffix)
C
A
B
MUARCASABLANCA
VIPer100/SP - VIPer100A/ASP
22/23
1
PENTAWATT HV TUBE SHIPMENT (no suffix)
All dimensions are in mm.
Base Q.ty 50
Bulk Q.ty 1000
Tube length (±0.5) 532
A18
B33.1
C(±0.1) 1
C
B
A
VIPer100/SP - VIPer100A/ASP
23/23
1
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