PIC12LC672-10/SM - Microchip Technology

 1999 Microchip Technology Inc. DS30561B-page 1

Devices Included in this Data Sheet:

• PIC12C671

• PIC12C672

•PIC12CE673

•PIC12CE674

High-Performance RISC CPU:

• Only 35 single word instructions to learn

• All instru ctions are single cycle (400 ns) excep t for

program branches which are two-cycle

• Operating speed: DC - 10 MHz clock input

DC - 400 ns instruction cycle

• 14-bit wide instructions

• 8-bit wide data path

• Interrupt capability

• Special function hardware registers

• 8-level deep hardware stack

• Direct, indirect and relative addressing modes for

data and instructions

Peripheral Features:

• Four-channel, 8-bit A/D converter

• 8-bit real time clock/counter (TMR0) with 8-bit

prog r am ma ble pres ca ler

• 1,000,000 erase/write cycle EEPROM data

memory

• EEPROM data retention > 40 years

Note: Throughout this data sheet PIC12C67X

refers to the PIC12C671, PIC12C672,

PIC12CE673 and PIC12CE674.

PIC12CE67X refers to PIC12CE673 and

PIC12CE674.

Device

Memory

Program Data

RAM Data

EEPROM

PIC12C671 1024 x 14 128 x 8 —

PIC12C672 2048 x 14 128 x 8 —

PIC12CE673 1024 x 14 128 x 8 16 x 8

PIC12CE674 2048 x 14 128 x 8 16 x 8

Pin Di agrams :

Special Microc ontroller Features:

• In-Ci rcuit Serial Programming (I CSP™)

• Internal 4 MHz osc illator w ith prog ra mmabl e calibr ati on

• Selectable clockout

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Programmable code protection

• Po w er saving SLEEP mode

• Interrupt-on-pin change (GP0, GP1, GP3)

• Internal pull-ups on I/O pins (GP0, GP1, GP3)

• Internal pu ll-up on MCLR pin

• Selectable oscillator options:

- INTRC: Precision internal 4 MHz oscillator

- EXTRC: External low-cost RC oscillat or

- XT: Standard crystal/resonator

- HS: High speed crystal/resonator

- LP: Power saving, low frequency crystal

CMOS Technology:

• Low-power , high-speed CMOS EPROM/EEPROM

technology

• Fully static design

• Wide operating voltage range 2.5V to 5.5V

• Commercial, Industrial and Extended

temperature ranges

• Low power consumption

< 2 mA @ 5V, 4 MHz

15 µA typical @ 3V, 32 kHz

< 1 µA typical standby current

PDIP, SOIC, Windo we d CERDIP

PIC12C671

PIC12C672

VSS

GP0/AN0

GP1/AN1/VREF

GP2/T0CKI/AN2/

INT

PDIP, Windowed CERDIP

PIC12CE673

PIC12CE674

VSS

GP0/AN0

GP1/AN1/VREF

GP2/T0CKI/AN2/

INT

VDD

GP5/OSC1/CLKIN

GP4/OSC2/AN3/

CLKOUT

GP3/MCLR/VPP

VDD

GP5/OSC1/CLKIN

GP4/OSC2/AN3/

CLKOUT

GP3/MCLR/VPP

8-Pin, 8-Bit CMOS Microcontroller with A/D Converter

and EEPROM Data Memory

PIC12C67X

DS30561B-page 2  1999 Mic rochip Technology Inc.

Table of Contents

1.0 General Description ..................... ....... .... .. .. .... .. ....... .. .... .. .... .. .. ....... .... .. .... .. .. ....... .... .. .. .... ............................................................. 3

2.0 PIC1 2 C6 7 X Device Varie ties.............. ...... .......... ....... .......... ....... .......... ...... ........... ...... ................... ........... ...... .......... ....... .......... .. 5

3.0 Architectural Overview.................................................................................................................................................................. 7

4.0 Memory Organization.................................................................................................................................................................. 11

5.0 I /O Po r t...... ...... .......... ....... .......... ........... ...... ........... ..................... .......... ...... ........... ............ ....... .......... ....... .......... ...... ........... ...... 25

6.0 EEPROM Peripheral Operation ................................... .. .... .. .... ....... .. .... .. .... .. ....... .... .. .... .. ....... .................................................... 33

7.0 Timer0 Module............................................................................................................................................................................ 39

8.0 Analog-to-Digital Converter (A/D) Module................................................................................................................................... 45

9.0 Special Features of the CPU....................................................................................................................................................... 53

10.0 Instruction Set Summary ............................................................................................................................................................. 69

11.0 Developm ent Support . ................................................................................................................................................................ 83

12.0 Electrical Specifications .............................................................................................................................................................. 89

13.0 DC and AC Characteristics......................... .... .. ......... .. .... .. .... .. ......... .. .... .. .... ....... .... .. .... .... ....................................................... 109

14.0 Packagi n g In fo rmation....... .......... ....... .......... ...... ........... ...... ........... ...... ........... ......................... .......... ..................... ................. 115

Appendix A:Compatibilit y... ....... ...... ...... ................. ........................... ............................ ..................................................................... 119

Appendix B:Code for Accessing EEPROM Data Memory ................................................ .... .... ......... .... .... .... .................................... 119

Index .................................................................................................................................................................................................. 121

On-Line Support............................................. .... .. .... .... ....... .... .. .... .... ....... .... .... .. .... ....... ..................................................................... 125

Reader Response.............................................................................................................................................................................. 126

PIC12C67X Product Identification System ........................................................ .... ........... ...... .... ....................................................... 127

To Our Valued Customers

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 1999 Microchip Technology Inc. DS30561B-page 3

PIC12C67X

1.0 GENERAL DESCRIPTION

The PIC12C67X devices are low-cost, high-perfor-

mance, CMOS, fully-static, 8-bit microcontrollers with

integrated analog-to-digital (A/D) converter and

EEPROM data memory (EEPROM on PIC12CE67X

versions only).

All PICmicro® microcontrollers employ an advanced

RISC architecture. The PIC12C67X microcontrollers

have enhanced core features, eight-level deep stack,

and multiple internal and external interrupt sources.

The separate instruction and data buses of the Harvard

architecture allow a 14-bit wide instruction word with

the separate 8-bit wide data. The two stage instruction

pipeline allows all instructions to execute in a single

cycle, except for program branches, which require two

cycles. A total of 35 instructions (reduced instruction

set) are a vailab le. Additionally, a large register set gives

some of the architectu ral in nov ation s used to achie v e a

very high performance.

PIC12C67X microcontrollers typically achieve a 2:1

code compression and a 4:1 speed improvement over

other 8-bit microcontrollers in their class.

The PIC12C67X devices have 128 bytes of RAM, 16

by tes of EEPR OM data memory (PIC12CE67X only), 5

I/O pins and 1 input pin. In addition a timer/counter is

available. Also a 4-channel, high-speed, 8-bit A/D is

pro v ide d. T he 8 -bi t res ol ution is i dea lly suited for appli-

cations requiring low-cost analog interface, (i.e.,

thermostat control, pressure sensing, etc.)

The PIC12C67X devices have special features to

reduce external components, thus reducing cost,

enhancing system reliability and reducing power con-

sumption. The Power-On Reset (POR), Power-up

Timer (PWRT), and Oscillator Start-up Timer (OST)

elimin ate the need f or e xternal reset c ircuitry. There a re

five oscillator configurations to choose from, including

INTRC precision internal oscillator mode and the

power-sav ing LP (Low Power) oscillator mode. Power-

saving SLEEP mode, Watchdog Timer and code

protection features improve system cost, power and

reliabil ity. The SLEEP (pow er-do wn) feature provi des a

power-saving mode. The user can wake-up the chip

from SLEEP through several external and internal

interrupts and resets.

A highly reliable Watchdog Timer with its own on-chip

RC oscillator provides protection against software

lock-up.

A UV erasable windowed package version is ideal for

code development, while the cost-effective One-Time-

Programmable (OTP) version is suitable for production

in an y v olume . The cust omer can ta ke f ull ad vantag e of

Microchip’s price leadership in OTP microcontrollers,

while benefiting from the OTP’s flexibility.

1.1 Applications

The PIC12C67X series fits perfectly in applications

ranging from personal care appliances and security

systems to low-power remote transmitters/receivers.

The EPROM technology makes customizing applica-

tion programs (transmitter codes, appliance settings,

receiver frequencies, etc.) extremely fast and conve-

nient, while the EEPROM data memory (PIC12CE67X

only) technology allows for the changing of calibration

factors and security codes. The small footprint pack-

ages, for through hole or surface mounting, make this

microcontroller series perfect for applications with

space limitations. Low-cost, low-power, high perfor-

mance, ease of use and I/O flexibility make the

PIC12C67X series very versatile even in areas where

no microcontroller use has been considered before

(i.e., timer functions, replacement of "glue" logic and

PLD’s in larger systems, coprocessor applications).

1.2 Family and Upward Compatibility

The PIC12C67X products are compatible with other

members of the 14-bit PIC16CXXX families.

1.3 Development Support

The PIC12C67X devices are supported by a full-

featured macro assembler, a software simulator, an in-

circuit emulator, a low-cost development programmer

and a full-featured programmer. A “C” compiler and

fuzzy logic support tools are also available.

PIC12C67X

DS30561B-page 4  1999 Microchip Technology Inc.

TABLE 1-1: PIC12C67X & PIC12CE67X FAMILY OF DEVICES

PIC12C671 PIC12LC671 PIC12C672 PIC12LC672 PIC12CE673 PIC12LCE673 PIC12CE674 PIC12LCE674

Clock

Maximum

Frequency

of Operation

(MHz)

10 10 10 10 10 10 10 10

Memory

EPROM

Program

Memory

1024 x 14 1024 x 14 2048 x 14 2048 x 14 1024 x 14 1024 x 14 2048 x 14 2048 x 14

RAM Data

Memory

(bytes)

128 128 128 128 128 128 128 128

Peripherals

EEPROM

Data Memory

(bytes)

—— —— 16 16 16 16

Timer

Module(s) TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0 TMR0

A/D Con-

verter (8-bit)

Channels

44 44 44 44

Features

Wake-up

from SLEEP

on pin

change

Yes Yes Yes Yes Yes Yes Yes Yes

Interrupt

Sources 44 44 44 44

I/O Pins 5 5 5 5 5 5 5 5

Input Pins 1 1 1 1 1 1 1 1

Internal

Pull-ups Yes Yes Yes Yes Yes Yes Yes Yes

In-Circuit

Serial

Programming

Yes Yes Yes Yes Yes Yes Yes Yes

Number of

Instructions 35 35 35 35 35 35 35 35

Voltage

Range (Volts) 3.0V - 5.5V 2.5V - 5.5V 3.0V - 5.5V 2.5V - 5.5V 3.0V - 5.5V 2.5V - 5.5V 3.0V - 5.5V 2.5V - 5.5V

Packages 8-p in DIP,

JW, SOIC 8-pin DIP,

JW 8-pin DIP,

JW 8-pin DIP ,

All PIC12C67X devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability.

All PIC12C67X de vices use serial programming with data pin GP0 and clock pin GP1.

 1999 Microchip Technology Inc. DS30561B-page 5

PIC12C67X

2.0 PIC12C67X DEVICE VA RIETIES

A variety of frequency ranges and packaging options

are a vai lable . Depending on a pplication an d production

requirem ents, the prop er devi ce option ca n be selected

using the information in the PIC12C67X Product Iden-

tification System section at the end of this data sheet.

When placing orders, please use that page of the data

sheet to specify the correct part number.

F or example , the PIC12C 67X de vice “typ e” is indicated

in the device number:

1. C, as in PIC12C671. These devices have

EPROM type memory and operate over the

standard voltage range.

2. LC, as in PIC12LC671. These devices have

EPROM type memory and operate over an

extend ed voltage range .

3. CE, as in PIC12CE674. These devices have

EPROM type memory, EEPROM data memory

and operate over the standard vol tage range.

4. LCE, as in PIC 12LCE674. These devices have

EPROM type memory, EEPROM data memory

and operate over an extended voltage range.

2.1 UV Er asa ble Devices

The UV erasable version, offered in windowed pack-

age, is optim al f or prot otype de v elopmen t and pil ot pro-

grams.

The UV erasable version can be erased and repro-

grammed to any of the configuration modes.

Microchip's PICSTART Plus and PRO MATE pro-

grammers both support the PIC12C67X. Third party

programmers also are available; refer to the Microchip

Third Party Guide for a list of sources.

2.2 One -Ti me- Programm able (OTP)

Devices

The availability of OTP devices is especially useful for

customers who need the flexibility for frequent code

updates and small volume applications.

The OTP devices, packaged in plastic packages, per-

mit the user to program them once. In addition to the

program memory, the configuration bits must also be

programmed.

Note: Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the internal oscillator.

The calibration value must be saved prior

to erasing the part.

2.3 Quick-Turn-Programming (QTP)

Devices

Microchip offers a QTP Programming Service for fac-

tory production orders. This service is made available

f or users who choose not to program a medium to high

quantity of units and whose code patterns have stabi-

liz ed. The d e vic es are i dentical to the OTP de vice s, b ut

with all EPROM locations and configuration options

already programmed by the factory. Certain code and

prototype ver ification procedures apply before produc-

tion shipments are available. Please contact your local

Microchip Technology sales office for more details.

2.4 Serialized Quick-Turn Programming

(SQTPSM) Devices

Microchip offers a unique programming service where

a few user-defined locations in each device are pro-

grammed with different serial numbers. The serial num-

bers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a

unique number which can serve as an entry-code,

password, or ID number.

PIC12C67X

DS30561B-page 6  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 7

PIC12C67X

3.0 ARCHITECTURAL OVERVIEW

The hig h performance of the PIC 12C67 X f a mily ca n b e

attributed to a number of architectural features com-

monly found in RISC microprocessors. To begin with,

the PIC12C67X uses a Harvard architecture, in which

program and data are accessed from separate memo-

ries using separate buses. This improves bandwidth

ov er tr aditional von Neu mann archi tecture in wh ich pro-

gram and data are fetched from the same memory

using the same bus. Separating program and data

bus es also allow instructions to be siz ed diff erently than

the 8-bit wide data word. Instruction opcodes are 14-

bits wide making it possible to have all single word

instructions. A 14-bit wide program memory access

bus fetches a 14-bit instruction in a single instruction

cycle. A two-stage pipeline overlaps fetch and execu-

tion of instructions (Example 3-1). Consequently, all

instruction s (35) e xecute in a single cycle (400 ns @ 10

MHz) except for program branches.

The table below lists program memory (EPROM), data

memory (RAM), and non-volatile memory (EEPROM)

for each PIC12C67X device.

Device Program

Memory RAM Data

Memory

EEPROM

Data

Memory

PIC12C671 1K x 14 128 x 8 —

PIC12C672 2K x 14 128 x 8 —

PIC12CE673 1K x 14 128 x 8 16x8

PIC12CE674 2K x 14 128 x 8 16x8

The PIC12C67X can directly or indirectly address its

ters, including the program counter, are mapped in the

data memory. The PIC12C67X has an orthogonal

(symmetrical) instruction set that makes it possible to

carry out any operation on any register using any

addressing mode. This symmetrical nature and lack of

‘speci al optimal si tua tions’ m ake progr am mi ng w ith th e

PIC12C67X simple yet efficient. In addition, the learn-

ing curve is reduced significantly.

PIC12C67X devices contain an 8-bit ALU and working

It performs arithmetic and Boolean functions between

the data in the working register and any register file.

The ALU is 8-bits wide and capable of addition, sub-

traction, shift and logical operations. Unless otherwise

mentioned, arithmetic operations are two's comple-

ment in nature. In two-operand instructions, typically

one operand is the working register (W register). The

other operand is a file register or an immediate con-

stant. In single operand instructions, the operand is

either the W register or a file register.

The W register is an 8-bit working register used f or ALU

operations. It is not an addressable registe r.

Depending on the instruction executed, the ALU may

aff ect the values of the Ca rry (C), Digit Carry (DC), an d

Zero ( Z) bits in th e STATUS reg ister . The C and D C bits

operate as a borrow bit and a digit borrow out bit,

respect ively, in subtraction. See th e SUBLW and SUBWF

instructions for examples.

PIC12C67X

DS30561B-page 8  1999 Microchip Technology Inc.

FIGURE 3-1: PIC12C67X BLOCK DIAGRAM

Power-up

Timer

Oscillator

Start- up Tim er

EPROM

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

RAM

File

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

MCLR VDD, VSS

Timer0

GPIO

GP4/OSC2/AN3/CLKOUT

GP3/MCLR/VPP

GP2/T0CKI/AN2/INT

GP1/AN1/VREF

GP0/AN0

GP5/OSC1/CLKIN

8 Level Stack

(13 bit) 128 byt es

Note 1: Higher order bits are from the STATUS Register.

A/D

Watchdog

Timer

Power-on

Reset

4 MHz Clock

Internal

Data

Memory

16x8

EEPROM

SCL

SDA

Device Program Mem ory Data Memory (RAM) Non-Volatile Memory (EEPROM)

PIC12C671 1K x 14 128 x 8 —

PIC12C672 2K x 14 128 x 8 —

PIC12CE673 1K x 14 128 x 8 16 x 8

PIC12CE674 2K x 14 128 x 8 16 x 8

PIC12CE673

PIC12CE674

 1999 Microchip Technology Inc. DS30561B-page 9

PIC12C67X

TABLE 3-1: PIC12C67X PINOUT DESCRIPTION

Name DIP Pin # I/O/P

Type Buffer

Type Description

GP0/AN0 7 I/O TTL/ST Bi-directional I/O port/serial programming data/analog input 0.

Can be software programmed for internal weak pull-up and

interrupt-on-pin change. This buffer is a Schmitt Trigger input

when used in serial programming mode.

GP1/AN1/VREF 6 I/O TTL/ST Bi-dir ec tio nal I/O port/serial programming clo ck/analog input 1/

voltage reference. Can be software programmed for internal

weak pull-up and interrupt-on-pin change. This buffer is a

Schmitt Trigger input when used in serial programming mode.

GP2/T0CKI/AN2/INT 5 I/O ST Bi-directional I/O port/analog input 2. Can be configured as

T0CKI or external interrupt.

GP3/MCLR/VPP 4 I TTL/ST Input port/master clear (reset) input/pro gramming voltage

input. When configured as MCLR, this pin is an active low

reset to the device. Voltage on MCLR/VPP must not exceed

VDD during normal device operation. Can be software pro-

grammed for internal weak pull-up and interrupt-on-pin

ch ange. Weak pull-up always on if configured as MCLR . This

buffer is Schmitt Trigger when in MCLR mode.

GP4/OSC2/AN3/CLKOUT 3 I/O TTL Bi-directional I/O port/oscillator crystal output/analog input 3.

Connections to crystal or resonator in crystal oscillator mode

(HS, XT and LP mod es on ly, GPIO i n othe r modes). In EXTRC

and INTRC modes, the pin output can be configured to CLK-

OUT, which has 1/4 the frequency of OSC1 and denotes the

instruction cycl e rate.

GP5/OSC1/CLKIN 2 I/O TTL/ST Bi-directional IO port/oscillator crystal input/external clock

source input (GPIO in INTRC mode only, OSC1 in all other

oscillator modes). Schmitt trigger input for EXTRC oscillator

mode.

VDD 1P— Positive supply for logic and I/O pins.

VSS 8 P — Ground reference for logic and I/O pins.

Legend: I = input, O = output, I/O = input/output, P = power, — = not used, TTL = TTL input,

ST = Schmitt Trigger input.

PIC12C67X

DS30561B-page 10  1999 Microchip Technology Inc.

FIGURE 3-2: CLOC K/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

OSC2/CLKOUT

(EXTRC and

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (P C+1)

Internal

phase

clock

INTRC modes)

All instructions are single cycle, except for any program branches. These take two cycles since the fetched

instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF GPIO Fetch 2 Execute 2

3. CALL SUB_1 Fetch 3 Execute 3

4. BSF GPIO, BIT3 (Forced NOP) Fetch 4 Flush

5. Instruction @ address SUB_1 Fetch SUB_1 Execute SUB_1

3.1 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by

four to generate four non-overlapping quadrature

cloc ks, namely Q1, Q 2, Q3 and Q4 . Internally, the pro-

gram counter (PC) is incremented every Q1, and the

instruction is fetched from the program memory and

latched into the instruction register in Q4. The instruc-

tion is decoded and executed during the following Q1

through Q4. The clocks and instruction execution flow

is shown in Figure 3-2.

3.2 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute

are pipelined such that fetch takes one instruction

cycle, while decode and execute takes another

instruction cycle. However, due to the pipelining, each

instruction effectively executes in one cycle. If an

instruction causes the program counter to change

(i.e., GOTO), then tw o cycl es are re quired to compl ete

the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is

latched into the “Instruction Register" (IR) in cycle

Q1. This instruction is then decoded and executed

during the Q2, Q3, and Q4 cycles. Data memory is

read during Q2 (op eran d read) a nd written during Q4

(destinati on write).

 1999 Microchip Technology Inc. DS30561B-page 11

PIC12C67X

4.0 MEMORY ORGANIZATIO N

4.1 Program Memory Organization

The P IC12C 6 7X h as a 13-b it p rog ram c ou nte r ca pa b l e

of addressing an 8K x 14 program memory space.

F or the PIC12C671 and the PIC12CE67 3, the first 1K x

14 (0000h-03FFh) is implemented.

For the PIC12C672 and the PIC12CE674, the first 2K

x 14 (00 00h-07 FFh) is impl ement ed. Acc essing a loc a-

tion above the physically implemented address will

cause a wraparound. The reset vector is at 0000h and

the interrupt vector is at 0004h.

FIGURE 4-1: PI C12C6 7X PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h

0005h

07FFh

1FFFh

Stac k Level 1

Stac k Level 8

Reset Vector

Interrupt Vector

On-Chip Program

Memory

CALL, RETURN

RETFIE, RETLW

0800h

0400h

03FFh

Peripheral

(PIC12C672 and

PIC12CE674 only)

4.2 Data Memory Organization

The data memory is par titioned into two banks, which

contain the Gener al Purpose R egisters and t he Special

Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1 → Bank 1

RP0 (STATUS<5>) = 0 → Bank 0

Each Bank extends up to 7Fh (128 bytes). The lower

locations of each Bank are reserved for the Special

Functio n Regist ers . Abo v e the Special Functi on Re gis-

ters are General Purpose Registers implemented as

static RAM. Both Bank 0 and Bank 1 contain Special

Funct i on Re g is t ers. S o me " hig h u s e" S p ec ial Fu n ct i on

Regi ste r s fr om Bank 0 a re mi rr ore d in Ba nk 1 for code

reduction and quicker access.

Also note that F0h through FFh on the PIC12C67X is

mapped into Bank 0 registers 70h-7Fh as common

RAM.

4.2.1 GENERAL PURPOSE REGISTER FILE

The regis ter file c an be ac cess ed eithe r direct ly o r indi-

rectly through the File Select Register FSR

(Section 4.5).

PIC12C67X

DS30561B-page 12  1999 Microchip Technology Inc.

FIGURE 4-2: PIC12C67X REGISTER FILE

MAP

INDF(1)

TMR0

PCL

STATUS

FSR

GPIO

PCLATH

INTCON

PIR1

ADRES

ADCON0

INDF(1)

OPTION

PCL

STATUS

FSR

TRIS

PCLATH

INTCON

PIE1

PCON

ADCON1

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

General

Purpose

General

Purpose

7Fh FFh

Bank 0 Bank 1

File

Address

BFh

C0h

Unimplemented data memory locations, read

as ’0’.

Note 1: Not a physical register.

File

Address

OSCCAL

F0h

EFh

Mapped

in Bank 0

70h

4.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the

desired operation of the device. These registers are

implemented as static RAM.

The Special Function Registers can be classified into

two s ets (c ore a nd peripheral). T hos e re gi ste rs a ss oc i-

ated wi th the “c ore” func tions are d escribed in this sec -

tion, and those related to the operation of the peripheral

features are described in the section of that peripheral

feature.

 1999 Microchip Technology Inc. DS30561B-page 13

PIC12C67X

TABLE 4-1: PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

Value on

all other

Resets(3)

Bank 0

00h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h(1) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h(1) STATUS IRP(4) RP1(4) RP0 TO PD ZDCC0001 1xxx 000q quuu

04h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h GPIO SCL(5) SDA(5) GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

06h —Unimplemented — —

07h —Unimplemented — —

08h —Unimplemented — —

09h —Unimplemented — —

0Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh(1) INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

0Ch PIR1 —ADIF——————-0-- ---- -0-- ----

0Dh —Unimplemented — —

0Eh —Unimplemented — —

0Fh —Unimplemented — —

10h —Unimplemented — —

11h —Unimplemented — —

12h —Unimplemented — —

13h —Unimplemented — —

14h —Unimplemented — —

15h —Unimplemented — —

16h —Unimplemented — —

17h —Unimplemented — —

18h —Unimplemented — —

19h —Unimplemented — —

1Ah —Unimplemented — —

1Bh —Unimplemented — —

1Ch —Unimplemented — —

1Dh —Unimplemented — —

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 reserved CHS1 CHS0 GO/DONE reserved ADON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter .

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.

5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.

PIC12C67X

DS30561B-page 14  1999 Microchip Technology Inc.

Bank 1

80h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h(1) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h(1) STATUS IRP(4) RP1(4) RP0 TO PD ZDCC0001 1xxx 000q quuu

84h(1) FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRIS —— GPIO Data Direction Register --11 1111 --11 1111

86h —Unimplemented — —

87h —Unimplemented — —

88h —Unimplemented — —

89h —Unimplemented — —

8Ah(1,2) PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000

8Bh(1) INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

8Ch PIE1 —ADIE——————-0-- ---- -0-- ----

8Dh —Unimplemented — —

8Eh PCON ——————POR—---- --0- ---- --u-

8Fh OSCCAL CAL3 CAL2 CAL1 CAL0 CALFST CALSLW — — 0111 00-- uuuu uu--

90h —Unimplemented — —

91h —Unimplemented — —

92h —Unimplemented — —

93h —Unimplemented — —

94h —Unimplemented — —

95h —Unimplemented — —

96h —Unimplemented — —

97h —Unimplemented — —

98h —Unimplemented — —

99h —Unimplemented — —

9Ah —Unimplemented — —

9Bh —Unimplemented — —

9Ch —Unimplemented — —

9Dh —Unimplemented — —

9Eh —Unimplemented — —

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

TABLE 4-1: PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

Value on

all other

Resets(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter .

3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.

5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.

 1999 Microchip Technology Inc. DS30561B-page 15

PIC12C67X

4.2.2.1 STATUS REGISTER

The STATUS Register, shown in Regis ter 4-1, c ontain s

the arithmeti c status of th e ALU , the RESET statu s and

the bank select bits for data memory.

The STATUS Register can be the destination for any

instruction, as with any other register. If the STATUS

Regis ter is the dest ination f or an instructio n that aff ect s

the Z, DC or C bits, then the write to these three bits is

disab led . The se bi ts ar e set o r clea red a ccordi ng to the

device logi c. Fur t her more, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS Register as destination may be different than

inte nded .

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STA TUS Register

as 000u u1uu (where u = unchang ed).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS Register, because these instructions do not

affect the Z, C or DC bits from the STATUS Register.

For other instructi ons, not aff e cting any status bi ts, see

the "Instruction Set Summary."

Note 1: Bits IRP and RP1 (STATUS<7:6>) are not

used by the PIC12C67X and should be

maintained clear. Use of these bits as

general purpose R/W bits is NOT recom-

mended, since this may affect upward

compatibility with future products.

2: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

The IRP bit is reserved; always maintain this bit clear.

bit 6-5: RP<1:0>: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

01 = Bank 1 (80h - FFh)

00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes. The RP1 bit is reserved; always maintain this bit clear.

bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred

bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instr ucti on

0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions ) (for borr ow the pol arity is re v er sed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred

0 = No carry-out from the most significant bit of the result occurred

Note: F or b orrow the po larity is re v er sed. A su btrac tion i s e xecuted b y ad ding the tw o’s comp lemen t of th e sec -

ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of

the source register.

PIC12C67X

DS30561B-page 16  1999 Microchip Technology Inc.

4.2.2.2 OPTION REGISTER

The OPTI ON Regi ster is a rea dab le a nd w ritabl e regi s-

ter, which contains var ious control bits to configure the

TMR0/WDT prescaler, the External INT Interrupt,

TMR0 and the weak pull-ups on GPIO.

Note: To ac hieve a 1:1 pres caler assi gnment for

the TMR0 register, assign the prescaler to

the Watchdog Timer by setting bit PSA

(OPTION<3>).

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

GPPU INTE DG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GPPU: W ea k Pull-up En able

1 = Weak pull-ups disabled

0 = Weak pull-ups enabled (GP0, GP1, GP3)

bit 6: INTEDG: Interrupt Edge

1 = Interrupt on rising edge of GP2/T0CKI/AN2/INT pin

0 = Interrupt on falling edge of GP2/T0CKI/AN2/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on GP2/T0CKI/AN2/INT pin

0 = Internal instruction cycle clo ck (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on GP2/T0CKI/AN2/INT pin

0 = Increment on low-to-high transition on GP2/T0CKI/AN2/INT pin

bit 3: PSA: Prescaler Assig nm ent bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS<2:0>: Prescaler Rate Select bits

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 1999 Microchip Technology Inc. DS30561B-page 17

PIC12C67X

4.2.2.3 INTC ON REGISTER

The I NTCON Regi ster i s a rea dab le a nd w ritabl e regi s-

ter, which contains various enable and flag bits for the

TMR0 Register overflow, GPIO port change and exter-

nal GP2/INT pin interrupts.

Note: Interrupt fl ag b its get s et wh en a n in terrupt

conditi on occ urs, regardless of the sta te of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE GPIE T0IF INTF GPIF R = R eada ble bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE: Glob al I nte rrupt Enab l e bit

1 = Enables all un-masked interrupts

0 = Disables all interrupts

bit 6: PEIE: Pe ripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4: INTE: INT External Interrupt Enable bit

1 = Enables the external interrupt on GP2/INT/T0CKI/AN2 pin

0 = Disables the external interrupt on GP2/INT/T0CKI/AN2 pin

bit 3: GPIE: GPIO Interrupt on Change Enable bit

1 = Enables the GPIO Interrupt on Change

0 = Disables the GPIO Interrupt on Change

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in softwa re)

0 = TMR0 register did not overflow

bit 1: INTF: INT External Interrupt Flag bit

1 = The external interrupt on GP2/INT/T0CKI/AN2 pin occurred (must be cleared in software)

0 = The external interrupt on GP2/INT/T0CKI/AN2 pin did not occur

bit 0: GPIF: GPIO Interrupt on Change Flag bit

1 = GP0, GP1 or GP3 pins changed state (must be cleared in software)

0 = Neither GP0, GP1 nor GP3 pins have changed state

PIC12C67X

DS30561B-page 18  1999 Microchip Technology Inc.

4.2.2.4 PIE1 REGISTE R

This register contains the individual enable bits for the

Peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

—ADIE— — — — — — R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ’0’

bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5-0: Unimplemented: Read as ’0’

 1999 Microchip Technology Inc. DS30561B-page 19

PIC12C67X

4.2.2.5 PIR1 REGISTER

This register contains the individual flag bits for the

Peripheral interrupts.

Note: Interrupt fl ag b its get s et wh en a n in terrupt

conditi on occ urs, regardless of the sta te of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

—ADIF— — — — — — R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ’0’

bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed (must be cleared in software)

0 = The A/D conversion i s not complete

bit 5-0: Unimplemented: Read as ’0’

PIC12C67X

DS30561B-page 20  1999 Microchip Technology Inc.

4.2.2.6 PCON REGISTER

The Pow e r Con trol (PC ON ) R eg ister contai ns a fla g b it

to allow differentiation between a Power-on Reset

(POR), an external MCLR Reset and a WDT Reset.

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0

————— —POR— R = Reada ble bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as ’0’

bit 1: POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: Unimplemented: Re ad as ’0’

 1999 Microchip Technology Inc. DS30561B-page 21

PIC12C67X

4.2.2.7 OSCCAL REGISTER

The Oscillator Calibration (OSCCAL) Register is used

to calibr ate the internal 4 MHz oscillator . It contains four

bits for fine calibration and two other bits to either

increase or decrease frequency.

R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 U-0 U-0

CAL3 CAL2 CAL1 CAL0 CALFST CALSLW —— R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-4: CAL< 3:0>: Fine C ali br ati on

bit 3: CALFST: Calibra tion Fast

1 = Increase frequency

0 = No change

bit 2: CALSLW: Calibration Slow

1 = Decrease frequency

0 = No change

bit 1-0: Unimplemented: Read as ’0’

Note: If CALFST = 1 and CALSLW = 1, CALFST has precedence.

PIC12C67X

DS30561B-page 22  1999 Microchip Technology Inc.

4.3 PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low

by te comes from the PCL Register, which is a readabl e

and w rit able re gister. The high byte (PC< 12:8>) is no t

directl y readable or writable and c omes from PCLATH.

On any reset, the PC is cleared. Figure 4-3 shows the

two situations for the loading of the PC. The upper

example in the figure shows how the PC is loaded on a

write to PCL (PCLATH<4:0> → PCH). The lower e xam-

ple in the f igure shows h ow the P C is loa ded du ring a

CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-3: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO

A Computed GOTO is accomplished by adding an off-

set to the program counter (ADDWF PCL). When doing

a table read using a computed GOTO method, care

should be exercis ed i f t he table locat ion c ros se s a PCL

memory boundary (each 256 byte block). Refer to the

application note

“Implementing a Table Read"

(AN556).

PC 12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU result

GOTO, CALL

Opcode < 10:0 >

PC 12 11 10 0

11PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

4.3.2 STACK

The PIC12C67X family has an 8-level deep x 13-bit

wide hardware stack. The stack space is not part of

either program or data space and the stack pointer is

not readable or writable. The PC is PUSHed onto the

stack when a CALL ins tr uc tio n is execute d or an in ter-

rupt ca uses a branch. The stack is POPed in the event

of a RETURN, RETLW or a RETFIE instruction execu-

tion. PCLATH is not affected by a PUSH or POP oper-

ation.

The stac k operates as a circular b uffer . This means that

after the stac k has been PUSHed eigh t times , th e nin th

push overwrites th e value that w as st ored from the firs t

push. The t ent h pus h overwrites the s ec ond pus h (an d

so on).

4.4 Progr am Memory Paging

The PIC12C67X ignores both paging bits

PCLATH<4:3>, which are used to access program

memory when more than one page is available. The

use of PCLATH<4:3> as general purpose read/write

bits for the PIC12C67X is not recommended since this

may affect upward compatibility with future products.

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the

CALL, RETURN, RETLW, and RETFIE

instructions, or the vectoring to an inter-

rupt address.

 1999 Microchip Technology Inc. DS30561B-page 23

PIC12C67X

4.5 Indirect Addressing, INDF and FSR

Registers

The INDF Register is not a physical register. Address-

ing the INDF Register will cause indirect addressing.

Any instruction using the INDF register actually

acces ses the register p ointed to b y the File Sele ct Reg-

ister, FSR. Reading the INDF Register itself indirectly

(FSR = ’0 ’) will read 00h. Writing to the INDF Register

indirec tly resu lts in a no-o pera tio n (althou gh statu s bits

ma y be affected). An eff e ctiv e 9-bit addres s is obta ined

by concaten ating the 8-bit FSR Register and the IRP bit

(STATUS<7>), as shown in Figure 4-4. H owe ver , IRP is

not used in the PIC 12C67X.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 4-1.

EXAMPLE 4-1: INDIR ECT ADDRESSING

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

CONTINUE

: ;yes continue

FIGURE 4-4: DIRECT/INDIRECT ADDRESSING

For register file map detail see Figure 4-2.

Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.

Data

Memory

Indirect AddressingDirect Addressing

bank select location select

RP1 RP0(1) 60

from opcode IRP(1) FSR register

bank select location select

00 01 10 11 180h

1FFh

00h

7Fh Bank 0 Bank 1 Bank 2 Bank 3

not used

PIC12C67X

DS30561B-page 24  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 25

PIC12C67X

5.0 I/O PORT

As with any other register, the I/O register can be

written and read un der prog r am cont rol. How e ver , rea d

instructions (i.e., MOVF GPIO,W) always read the I/O

pins independent of the pin’s input/output modes. On

RESET, all I/O ports are defined as input (inputs are at

hi-impedance), since the I/O control registers are all

set.

5.1 GPIO

GPIO is an 8-bit I/O register. Only the low order 6 bits

are used (GP<5:0>). Bits 6 and 7 (SDA and SCL,

respectively) are used by the EEPROM peripheral on

the PIC12CE673/674. Refer to Section 6.0 and

Appendix B for use of SDA and SCL. Please note that

GP3 is an input only pin. The configuration word can

set several I/O’s to alternate functions. When acting as

alternate functions, the pins will read as ‘0’ during port

read. Pins GP0, GP1 and GP3 can be configured with

weak pull-ups and also with interrupt-on-change. The

inter rupt on c han ge and w e ak pul l-u p fu nc tion s a r e n ot

pin selectable. If pin 4, (GP3), is configured as MCLR,

a weak pull-up is always on. Interrupt-on-change for

this p in is n ot se t and G P3 wil l read as '0' . I nterrupt-o n-

change is enabled by setting bit GPIE, INTCON<3>.

Note that external oscillator use overrides the GPIO

functions on GP4 and GP5.

5.2 TRIS Register

This register controls the data direction for GPIO. A '1'

from a TRIS R egis ter bit p uts the co rrespo nding o utput

driver in a hi-impedance mode. A '0' puts the contents

of the output data latch on the selected pins, enabling

the output buffer. The exceptions are GP3, which is

input only and its TRIS bit will always read as '1', while

GP6 and GP7 TRIS bits will read as ’0’.

Upon reset, the TRIS Register is all '1's, making all

pins inputs.

TRIS for pins GP4 and GP5 is forced to a ’1’ where

appropriate. Writes to TRIS <5:4> will have an effect

in EXTRC and INTRC oscillator modes only. When

GP4 is configured as CLKOUT, changes to TRIS<4>

will have no eff e ct .

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output

driver on a pin is enabled and driven high,

but the external system is holding it low, a

read of th e p o rt wi l l i ndi ca t e t h at t h e pi n i s

low.

5.3 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in

Figure 5-1 through Figure 5-5. All port pins, except

GP3, which is input only, may be used for both input

and output operations. For input operations, these

ports are non-latching. Any input must be present until

read by an input instruction (i.e., MOVF GPIO,W). The

outputs are latched and remain unchanged until the

output latch is rewritten. To use a port pin as output,

the corres po ndi ng d irec ti on c ontrol bit in TRIS m u st b e

cleared (= 0). For use as an input, the corresponding

TRIS bit must be set. Any I/O pin (except GP3) can be

programmed individually as input or output.

Por t pins GP6 (SDA) and GP7 (SCL) are used for the

serial EEPROM interface on the PIC12CE673/674.

These port pins are not available externally on the

package. Users should avoid writing to pins GP6

(SDA) and GP7 (SCL) when not communicating with

the serial EEPROM memor y. Please see Section 6.0,

EEPROM Peripheral Operation, for information on

serial EEPROM communication.

Note: On a Power-on Reset, GP0, GP1, GP2

and GP4 are configured as analog inputs

and read as '0'.

PIC12C67X

DS30561B-page 26  1999 Microchip Technology Inc.

FIGURE 5-1: BLOCK DIA GRAM OF GP0/AN0 AND GP1/AN1/VREF PIN

Data Bus

WR PORT

WR TRIS

RD TRIS

VDD

Data Latch

CK Q

TRIS Latch

VDD

RD PORT

To A/D Converter

Analog

Input

Mode TTL

Input

Buffer

I/O Pin

GPPU

VSS

CK Q

VSS

GP0/INT(1) and GP1/INT(1)

Note 1: Wake-up on pin change interrupts for GP0 and GP1.

 1999 Microchip Technology Inc. DS30561B-page 27

PIC12C67X

FIGURE 5-2: BLOC K DIAGRAM OF GP2/T0CKI/AN2/INT PIN

Data Bus

WR PORT

WR TRIS

RD TRIS

VDD

CK Q

Data Latch

CK Q

TRIS Latch

RD P ORT

To A/D Converter

Analog

Input

Mode Schmitt Trigger

Inp ut Bu ffer

I/O Pin

TMR0 Clock Input

GP2/INT

VSS

VDD

VSS

PIC12C67X

DS30561B-page 28  1999 Microchip Technology Inc.

FIGURE 5-3: BLOCK DIAGRAM OF GP3/MCLR/VPP PIN

GPPU

VDD

RD PORT

Schmitt Trigger

Input Buffer

Input Pin

VSS

MCLREN

RD TRIS

Data Bus

Program Mode HV Detect

MCLR

GP3/INT(1)

Note 1: Wake-up on pin change interrupt for GP 3.

TTL Input

Buffer

VSS

 1999 Microchip Technology Inc. DS30561B-page 29

PIC12C67X

FIGURE 5-4: BLOC K DIAGRAM OF GP4/OSC2/AN3/CLKOUT PIN

Data Bus

WR PORT

WR TRIS

RD TRIS

VDD

CK Q

Data Latch

CK Q

TRIS Latch

RD PORT

To A/D Converter

Analog

Input

Mode TTL

Input Buffer

I/O Pin

VSS

From OSC1 Oscillator

Circuit

INTRC or EXTRC

w/o CLKOUT

INTRC or EXTRC w/ CLKOUT

CLKO UT (FOSC/4)

VDD

VSS

INTRC/

EXTRC

PIC12C67X

DS30561B-page 30  1999 Microchip Technology Inc.

FIGURE 5-5: BLOC K DIAGRAM OF GP5/OSC1/CLKIN PIN

Data Bus

WR PORT

WR TRIS

RD TRIS

VDD

EN Q

Data Latch

EN Q

TRIS Latch

RD PORT

INTRC

TTL

Input Buffer

I/O Pin

VSS VSS

VDD

To OSC2 Oscillator

Circuit

INTRC

 1999 Microchip Technology Inc. DS30561B-page 31

PIC12C67X

TABLE 5-1: SUMMARY OF PORT REGISTERS

5.4 I/O Programming Considerations

5.4.1 BI-DIRECTIONAL I/O PORTS

Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF

instructions, for example, read the register into the

CPU , execute the bit operation and write the result ba ck

to the register. Caution must be used when these

instructions are applied to a port with both inputs and

outputs defined. For example, a BSF operation on bit5

of GPIO will ca use al l eigh t bits of GPIO to be read in to

the CPU. Then the BSF operation takes place on bit5

and GPIO is written to the output latches. If another bit

of GPIO is used as a bi-d irectional I/O pin (i.e ., bit0) and

it is defined as an input at this time, the input signal

present on the pin itself would be read into the CPU and

rewritten to the data latch of this particular pin, ov erwrit-

ing the pre vio us conten t. As long as the pi n sta ys in the

input mode, no problem occurs. However, if bit0 is

s witched t o an outp ut, the co ntent of t he dat a latch ma y

now be unknown.

Reading the port register reads the values of the port

pins. Writing to the port register writes the value to the

port latch. When using read-modify-write instructions

(i.e., BCF, BSF, etc.) on a port, the value of the port

pins is read, the de sired oper ation is done to this va lue,

and this value is then written to the port latch.

Example 5-1 shows the effect of two sequential read-

modify-write instructions on an I/O port.

EXAMPLE 5-1: READ-MODIFY -WRITE

INSTRUCTIONS ON AN

I/O PORT

;Initial GPIO Settings

; GPIO<5:3> Inputs

; GPIO<2:0> Outputs

;

; GPIO latch GPIO pins

; --------- - ----- -----

BCF GPIO, 5 ;--01 -ppp --11 pppp

BCF GPIO, 4 ;--10 -ppp --11 pppp

MOVLW 007h ;

TRIS GPIO ;--10 -ppp --10 pppp

;

;Note that the user may have expected the pin

;values to be --00 pppp. The 2nd BCF caused

;GP5 to be latched as the pin value (High).

A pin actively outputting a Low or High should not be

driven from external devices at the same time in order

to chan ge th e le vel on this pin (“w ired-o r”, “wired -and”).

The resulting high output currents may damage the

chip.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-on

Reset

Value on

all other

Resets

85h TRIS —— GPIO Data Direction Register --11 1111 --11 1111

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

03h STATUS IRP(1) RP1(1) RP0 TO PD ZDCC0001 1xxx 000q quuu

05h GPIO SCL(2) SDA(2) GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

Legend: Shaded cells not used by Port Registers, read as ‘0’, — = unimplemented, read as '0', x = unknown, u = unchanged,

q = see tables in Section 9.4 for possible values.

Note 1: The IRP and RP1 bits are reserved on the PIC12C67X; always maint ain these bits clear.

2: The SCL and SD A bits are unimplemented on the PIC12C671 and PIC12C672.

PIC12C67X

DS30561B-page 32  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 33

PIC12C67X

6.0 EEPROM PERIPHERAL

OPERATION

The PIC12CE673 and PIC12CE674 each have 16

by tes of EEPROM data me mory. The EEPROM mem-

ory has an endurance of 1,000,000 erase/write cycles

and a data retention of greater than 40 years. The

EEPROM data memory supports a bi-directional 2-wire

bus and data transmission protocol. These two-wires

are serial data (SDA) and serial clock (SCL), that are

mapped to bit6 and bit7, respectively, of the GPIO reg-

ister (SFR 06h). Unlike the GP0-GP5 that are con-

nected to the I/O pins, SDA and SCL are only

connected to the internal EEPROM peripheral. For

most applications, all that is required is calls to the

following functions:

; Byte_Write: Byte write routine

; Inputs: EEPROM Address EEADDR

; EEPROM Data EEDATA

; Outputs: Return 01 in W if OK, else

return 00 in W

;

; Read_Current: Read EEPROM at address

currently held by EE device.

; Inputs: NONE

; Outputs: EEPROM Data EEDATA

; Return 01 in W if OK, else

return 00 in W

;

; Read_Random: Read EEPROM byte at supplied

address

; Inputs: EEPROM Address EEADDR

; Outputs: EEPROM Data EEDATA

; Return 01 in W if OK,

else return 00 in W

The code for these functions is available on our web

site (www.microchip.com ). The co de wil l be ac cessed

by either including the source code FL67XINC.ASM or

by linking FLASH67X.ASM. FLASH67X.INC provides

external definition to the calling program.

6.0.1 SERIAL DATA

SDA is a bi-directional pin used to transfer addresses

and data into and data out of the device.

F or normal data transf er, SD A is allow ed to change only

during SCL low. Changes during SCL high are

reserved for indicating the START and STOP condi-

tions.

6.0.2 SERIAL CLOCK

This SCL signal is used to synchronize the data trans-

fer from and to the EEPROM.

6.1 Bus Chara ct eris tics

The following bus protocol is to be used with the

EEPROM data memory. In this section, the term “proces-

sor” is used to denote the portion of the PIC12C67X that

interf a ces to the EEPROM via software .

• Data transfer may be initiated only when the bus

is not busy.

During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data

line whi le the clo c k line is HIGH will be int erpreted as a

START or STOP condition.

Accordingly, the following bus conditions have been

defined (Fig ure 6 -3).

6.1.1 BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

6.1.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the

cloc k (SCL) is HIGH determines a S TART c ondition. Al l

commands must be preceded by a START condition.

6.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

6.1.4 DATA VALID (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one bit of data per

clock pulse.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the available data

EEPROM space.

PIC12C67X

DS30561B-page 34  1999 Microchip Technology Inc.

6.1.5 ACKNOWLEDGE

The EEPROM, when addressed, will generate an

acknowledge after the reception of each byte. The pro-

cessor must generate an extra clock pulse which is

associated with this acknowledge bit.

The device that acknowledges has to pull down the

SDA line during the acknowled ge cl ock pulse in su ch a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. The processor must signal an end of data to

the EEPROM b y no t g ene r atin g a n a cknow le dg e b it o n

the last b yte that has been clocked o ut of the EEPROM.

In this case, the EEPROM must leave the data line

HIGH to enable the processor to generate the STOP

conditi on (Fig ure 6-4).

FIGURE 6-1: BLOCK DIAGRAM OF GPIO6 (SDA LINE)

FIGURE 6-2: BLOCK DIAGRAM OF GPIO7 (SCL LINE)

Note: Acknowledge bits are not generated if an

internal programming cycle is in progress.

Reset

CK Q

Data Bus Write

Output Latch

To EEPROM SDA

Schmitt Trigger

ltchpin

Input Latch

Read

VDD

Pad

GPIO

CK Q

Data Bus Write

To EE PR O M SCL

ltchpin

Read

VDD

Pad

Schmitt Trigger

GPIO

Output Latch

 1999 Microchip Technology Inc. DS30561B-page 35

PIC12C67X

FIGURE 6-3: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 6-4: ACKNOWLEDGE TIMING

6.2 Device Addressing

After generating a START condition, the processor

transmits a control byte consisting of a EEPROM

address and a Read/Write bit that indicates what type

of opera tion is to be perf ormed. The EEPR OM address

consis ts of a 4-bi t de v ice cod e (101 0) f oll ow ed by three

don’t care bits.

The last bi t of the control b yte determines the ope ration

to be perfor med. When set to a one, a read operation

is sele cted, a nd when s et to a z ero, a write oper ation i s

selected (Figure 6-5). The bus is monitored for its cor-

respond ing EEPROM address all t he time. It g enerate s

an acknowledge bit if the EEPROM address was true

and it is not in a programming mode.

FIGURE 6-5: CONTROL BYTE FORMAT

(A) (B) (C) (D) (A)(C)

SCL

SDA

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL 987654321 123

Transmitter must relea se the SDA line at this point

allowing the Receiver to pull the SDA line low to

acknowledge the previous eight bits of data.

Receiver must release the SDA line at this

point so the Transmitter can continue

sending data.

Data from transmitter Data from transmitter

SDA

Acknowledge

Bit

1010XXXSACKR/W

Device Select

Bits Don’t Care

Bits

EEPROM Address

Acknowledge Condition

Star t Condition

Read/Write Bit

PIC12C67X

DS30561B-page 36  1999 Microchip Technology Inc.

6.3 Write Operations

6.3.1 BYTE WRITE

Following the start signal from the processor, the

de vic e code (4 bits), th e don’t care bits (3 bit s), and the

R/W bit (which is a logic low) are placed onto the bus

by the processor. This indicates to the addressed

EEPROM that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore, the next byte transmitted

by the processo r is the word a ddress and wil l be written

into the address pointer. Only the lower four address

bits are used by the device, and the upper four bits are

don’t cares. If the address byte is acknowledged, the

process or w ill th en transmit the dat a word to be w ritten

into the addressed memory location. The memory

acknowledges again and the processor generates a

stop condition. This initiates the internal write cycle,

and duri ng this time will n ot gener ate ac k no wled ge si g-

nals. After a byte write command, the internal address

counter will not be incremented and will point to the

same ad dress locatio n that was jus t written. If a s top bit

sequen ce is transmitted to the de vice at any poi nt in the

write command sequence before the entire sequence

is complete, then the command will abor t and no data

will be written. If more than 8 data bits are transmitted

bef ore the stop bit sequence is sent, then the de vice will

clear the previously loaded byte and begin loading the

data buffer again. If more than one data byte is trans-

mitted to the device and a stop bit is sent before a full

eight data bits have been transmitted, then the write

command will abort and no data will be written. The

EEPROM memory employs a VCC threshold detector

circuit, which disables the internal erase/write logic if

the VCC is be low mini mum VDD. Byte write operations

must be preceded and immediately followed by a bus

not busy bus cycle where both SDA and SCL are held

high. (See Figure 6-7 for Byte Write operation.)

6.4 Acknowledge Polling

Since the EEPROM will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the processor, the device

initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the proces-

sor sending a start condition followed by the control

by te for a write com mand (R/W = 0). If the de vice is stil l

bus y with the w rite cycle , th en no A CK w ill be retu rned.

If no A CK is returned, the n the start bit and control b yte

must be re-sent. If the cycle is complete, then the

device will return the ACK and the processor can then

proceed with the next read or write command. (See

Figure 6-6 for flow diagram.)

FIGURE 6-6: ACKNOWLEDGE POLLING

FLOW

FIGURE 6-7: BYTE WRITE

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did EEPR OM

Acknowledge

(ACK = 0)?

Operation

YES

SDA LINE

CONTROL

BYTE WORD

ADDRESS DATA

10 X10 XXX

X = Don’t Care Bit

XXX

ACTIVITY

 1999 Microchip Technology Inc. DS30561B-page 37

PIC12C67X

6.5 Rea d Operatio ns

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

EEPROM address is set to one. There are three basic

types of read operations; current address read, random

read and sequential read.

6.5.1 CURRENT ADDRESS READ

The EEPRO M contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous read

access w as to address n, the ne xt current address read

oper ation woul d acc ess data fro m addres s n + 1 . Up on

receipt of the EEPR OM address with th e R/W bit set to

one, the EEPROM issues an acknowledge and trans-

mits the 8-bit data word. The processor will not

acknowledge the transfer, but does generate a stop

condition and the EEPROM discontinues transmission

(Figure 6-8).

6.5.2 RANDOM READ

Rando m read oper ations allo w the pr ocessor to a ccess

any memory location in a random manner. To perform

this typ e o f read operati on, firs t the w o rd a ddre ss m u st

be set . This i s done by sending the word addre ss to the

EEPROM as part of a write operation. After the word

address is s ent, the pro ce ss or ge ner ates a s tart condi-

tion following the acknowledge. This terminates the

write operation, but not before the internal address

pointer is set. Then the processor issues the control

byte again, but with the R/W bit set to a one. The

EEPROM will then issue an acknowledge and trans-

mits the 8-bit data word. The processor will not

acknowledge the transfer, but does generate a stop

condition and the EEPROM discontinues transmission

(Figure 6-9). After this command, the internal address

counter will point to the address location following the

one that was just read.

6.5.3 SEQUENTIAL READ

Sequenti al reads are initiated in the same w ay as a r an-

dom read, e xcept that after the device transmits the first

data byte, the processor issues an acknowledge as

opposed to a stop condition in a random read. This

directs the EEPROM to transmit the next sequentially

addressed 8-bit word (Figure 6-10).

To provide seq uentia l reads, the EEPR OM contains an

internal address pointer, which is incremented by one

at the com pleti on of eac h read op erati on. This addres s

pointer allows the entire memory conten ts to be serially

read during one operation.

FIGURE 6-8: CURRENT ADDRESS READ

FIGURE 6-9: RANDOM READ

FIGURE 6-10: SEQUENTIAL READ

SD A LINE P

CONTROL

BYTE

DATA

1100XXX1

X = Don’t Care Bit

ACTIVITY

SDA LINE

CONTROL

BYTE

WORD

ADDRESS (n) CONTROL

BYTE

DATA (n)

XXXX

S1 100XXX0 S1 100XXX1

X = Don’t Care Bit

ACTIVITY

SD A LINE

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

ACTIVITY

PIC12C67X

DS30561B-page 38  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 39

PIC12C67X

7.0 TIMER0 MODULE

The Tim er0 module timer/count er has the f ollo wing f ea-

tures:

• 8-bit timer/counter

• Readable and writable

• 8-bit soft ware programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 7-1 is a simplified block diagram of the Timer0

module.

Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will

increm ent every instructio n c yc le (witho ut p r es ca ler) . If

the TMR0 register is written, the increment is inhibited

for the following two instruction cycles (Figure 7-2 and

Figure 7-3). The user can work around this by writing

an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION<5>). In counter mode, Timer0 will increment

either on every rising or falling edg e of pin RA 4/T0 C KI.

The incrementing edge is determined by the bit T0SE

(OPTION<4>). Clearing bit T0SE selects the rising

edge. Restrictions on the external clock input are dis-

cussed in detail in Section 7.2.

The prescaler is mutually exclusively shared between

the Timer0 module and the W atchdo g Timer . Th e pres-

caler ass ignm ent is co ntroll ed in soft ware b y control b it

PSA (OPTION<3>). Clearing bit PSA will assign the

prescaler to the Timer0 module. The prescaler is not

readab le or w ritable . When the presc aler is ass igned to

the Timer0 module, prescale values of 1:2, 1:4, ...,

1:256 are selectable. Section 7.3 details the operation

of the prescaler.

7.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister ove rflows fr om FFh to 00 h. This overflow set s bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in s oftwa re b y th e Tim er0 mo dule interrupt s er-

vice routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut off during SLEEP. See

Figure 7-4 for Timer0 interrupt timing.

FIGURE 7-1: TIMER0 BLOCK DIAGRAM

FIGURE 7-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: TOCS, TOSE , PSA, PS<2 :0> (OPTION<5:0> ).

2: The prescaler is shared with Watchdog Timer (refer to Figure 7-6 for detailed block diagram).

GP2/TOCKI/

TOSE

AN2/INT

TOCS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks TMR0

(2 TCY delay)

Data Bus

PSA

PS<2:0> Set interru pt

flag bit T0IF

on overflow

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2 T

MOVWF TMR0MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 + 1 Read TMR0

reads NT0 + 2

Instruction

Executed

PIC12C67X

DS30561B-page 40  1999 Microchip Technology Inc.

FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 7-4: TIMER0 INTERRUPT TIMING

PC-1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

(Program

Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0MOVF TMR0,WMOVF TMR0,WMOVF TMR0,WMO VF TMR0,WMOVF TMR0,W

Write TMR0

executed Read TMR0

reads NT0 Read TMR0

reads NT0 Re ad TMR0

reads NT0 + 1

T0+1 NT0

Instruction

Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit

(INTCON<2>)

FEh

GIE bit

(INTCON<7>)

INSTRUCTION

Instruction

fetched

PC PC +1 PC +1 0004h 0005h

Instruction

executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Du mmy cycle

FFh 00h 01h 02h

FLOW

Interru pt Late ncy (2)

Note 1: Interrupt flag bit T0IF is sampled here (ev ery Q1).

2: Interrupt latency = 3TCY where TCY = instruction cycle time.

3: CLKO UT is available only in the INTRC and EXTRC oscillator modes.

 1999 Microchip Technology Inc. DS30561B-page 41

PIC12C67X

7.2 Using Timer0 with an External Clock

When an e xternal clock inp ut is used f or Timer0 , it must

meet certain requirements. The requirements ensure

the e xternal cloc k can b e synchron ized with the internal

phase clock (TOSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

7.2.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is

used as the clock source. The synchronization of

T0CKI with the internal phase clocks is accomplished

by sampling the prescaler output on the Q2 and Q4

cycle s of the internal phas e cloc k s (Figure 7-5 ). There-

fore, it is necessary for T0CKI to be high for at least

2TOSC (and a small RC delay of 20 ns) and low for at

least 2TOSC (and a small RC delay of 20 ns). Refer to

the electrical specification of the desired device.

When a prescaler is used, the external clock input is

divided by the asynchronous ripple-counter type pres-

caler, so that the prescaler output is symmetrical. For

the external clock to meet the sampling requirement,

the ripple-counter must be taken into account. There-

fore, it is necessary for T0CKI to have a period of at

least 4TOSC (and a s mal l R C d el ay of 40 ns) div id ed by

the prescaler value. The only requirement on T0CKI

high and low time is that they do not violate the mini-

mum pu lse width requirem ent of 10 ns. Ref er to par am-

eters 40, 4 1 and 42 in the e le ctrical sp ec ifi cat ion of the

desired device.

7.2.2 TMR0 INCREMENT DELAY

Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the

e xternal cloc k edge o ccurs to the ti me the Tim er0 mod-

ule is a ctually inc remented. F igure 7-5 s hows the dela y

from the external clock edge to the timer incrementing.

FIGURE 7-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or

Prescaler output(2)

External Clock/Prescaler

Output after sampling

Increment Timer0 (Q4)

Timer0 T0 T0 + 1 T0 + 2

Small pulse

misses sampling

(3) (1)

Note 1: Delay from clock input change to Timer0 increment is 3TOSC to 7TOSC. (Duration of Q = TOSC). Therefore, the error

in measuring the interval between two edges on Timer0 input = ±4TOSC max.

2: External clock if no prescaler selected; prescaler output otherwise.

3: The arrows indicate the points in time where sampling occurs.

PIC12C67X

DS30561B-page 42  1999 Microchip Technology Inc.

7.3 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer, respectively (Figure 7-6). For simplicity, this

counter is being referred to as “prescaler” throughout

this data sheet. Note that there is only one prescaler

availab le w hi ch i s m utually exclusively share d between

the Timer0 module and the Watchdog Timer. Thus, a

prescaler assignment for the Timer0 module means

that there is no prescaler for the Watchdog Timer, and

vice-versa.

The PSA and PS<2:0> bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 re giste r (i.e ., CLRF 1, MOVWF 1,

BSF 1,x...., etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the

prescaler along with the Watchdog Timer. The pres-

caler is not readable or writable.

FIGURE 7-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

GP2/T0CKI/

T0SE

AN2/INT

CLKOUT (= FOSC/4)

SYNC

Cycles TMR 0 r e g

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS<2:0>

Note: T0CS, T0SE, PSA, PS<2:0> are (OPTION<5:0>).

PSA

WDT Enable bit

Data Bus

Set flag bit T0IF

on Overflow

PSA

T0CS

 1999 Microchip Technology Inc. DS30561B-page 43

PIC12C67X

7.3.1 SWITCHING PRESCALER ASSIGNMENT

The prescaler assignment is fully under software con-

trol, (i.e ., it can be chang ed “on-the -fly” du ring prog ra m

e x ec ution).

EXAMPLE 7-1: CHANGING PRESCALER

(TIMER0→WDT)

BCF STATUS, RP0 ;Bank 0

CLRF TMR0 ;Clear TMR0 & Prescaler

BSF STATUS, RP0 ;Bank 1

CLRWDT ;Clears WDT

MOVLW b’xxxx1xxx’ ;Select new prescale

MOVWF OPTION_REG ;value & WDT

BCF STATUS, RP0 ;Bank 0

Note: To a v oid an uni ntende d de v ice RESET, the

following instruction sequence (shown in

Example 7-1) must be executed when

changing the prescaler assignment from

Timer0 to the WDT. This sequence must

be followed even if the WDT is disabled.

To change pres caler from the WD T to the Ti mer0 mo d-

ule, use the sequence shown in Example 7-2.

EXAMPLE 7-2: CHANGIN G PRESCALER

(WDT→TIMER0)

CLRWDT ;Clear WDT and

;prescaler

BSF STATUS, RP0 ;Bank 1

MOVLW b’xxxx0xxx’ ;Select TMR0, new

;prescale value and

MOVWF OPTION_REG ;clock source

BCF STATUS, RP0 ;Bank 0

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR

Value on

all other

Resets

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

0Bh/8Bh INTCON GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

85h TRIS — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer 0.

PIC12C67X

DS30561B-page 44  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 45

PIC12C67X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS1 ADCS0 reserved CHS1 CHS0 GO/DONE reserved ADON R =Readable bit

W =Writable bit

U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: ADCS<1:0>: A/D Conversi on Clock Select bits

00 = FOSC/2

01 = FOSC/8

10 = FOSC/32

11 = FRC (clock derived from an RC oscillation)

bit 5: Reserved

bit 4-3: CHS<1:0>: Analog Channel Select bits

00 = channel 0, (GP0/AN0)

01 = channel 1, (GP1/AN1)

10 = channel 2, (GP2/AN2)

11 = channel 3, (GP4/AN3)

bit 2: GO/DONE: A/D C onversion Status bit

If ADON = 1

1 = A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D conv ersion n ot in prog ress (this bit is au tomatically c leared b y hardwa re when th e A/D con versi on

is comp lete )

bit 1: Reserved

bit 0: ADON: A/D on bit

1 = A/D converter module is operating

0 = A/D converter module is shut off and consumes no operating current

8.0 ANALOG-TO-DIGITAL

CONVERTER (A /D) MODULE

The Analog -To-Digit al (A/D ) c onverter module ha s four

analog inp uts.

The A/D allows conversion of an analog input signal to

a corresponding 8-bit digital number (refer to Applica-

tion Note AN546 for use of A/D Converter). The output

of the sample and hold is the input into the conver ter,

which generates the result via successive approxima-

tion. The analog reference voltage is software select-

abl e to eithe r the de vice’s positiv e sup ply v oltage (VDD)

or the v oltag e le v e l on the GP 1/AN1/VREF pin . The A/D

con v erter has a un ique feature of b eing a b le to o per ate

while the device is in SLEEP mode.

The A/D module has three registers. These registers

are: • A/D Result Register (ADRES)

• A/D Control Regis ter 0 (ADCON 0)

• A/D Control Regis ter 1 (ADCON 1)

The ADCON0 Register, shown in Figure 8-1, controls

the operation of the A/D module. The ADCON1 Regis-

ter , shown i n Figure 8-2, c onfigures t he functio ns of the

port pins. The port pins can be configured as analog

inputs (G P1 can al so be a v ol tage reference) or as di g-

ital I/O.

Note 1: If the port pins are configured as analog

inputs (reset condition), reading the port

(MOVF GPIO, W) results in reading '0's.

2: Changing ADCON1 Register can cause

the GPIF and INTF flags to be set in the

INTCON Register. These interrupts

should be disabled prior to modifying

ADCON1.

PIC12C67X

DS30561B-page 46  1999 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0 R =Readable bit

W =Writable bit

U =Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0'

bit 1-0: PCFG<2:0>: A/D Port Configuration Control bits

A = Analog input

D = Digital I/O

Note 1: Value on reset.

2: Any instruction that reads a pin configured as an analog input will read a '0'.

PCFG<2:0> GP4 GP2 GP1 GP0 VREF

000(1) AAAAVDD

001 AAVREF AGP1

010 DAAAV

011 DAVREF AGP1

100 DDAAVDD

101 DDVREF AGP1

110 DDDAVDD

111 DDDDVDD

 1999 Microchip Technology Inc. DS30561B-page 47

PIC12C67X

The ADRES Register contains the result of the A/D

conversion. When the A/D conversion is complete, the

result is loaded into the ADRES register , the GO/DONE

bit (ADCON0<2>) is cleared, and A/D interrupt flag bit

ADIF (PIE1<6>) is set. The block diagrams of the A/D

module are shown in Figure 8-1.

After the A/D module has been configured as desired,

the selected channel must be acquired before the con-

version is started. The analog input channels must

have their corresponding TRIS bits selected as an

input. To dete rmine sampl e time , see Sectio n 8.1. After

this acquisition time has elapsed, the A/D conversion

can be started. The following steps should be followed

for doing an A/D conversion:

1. Configure the A/D module:

• Configure analog pins / voltage reference /

and digital I/O (ADCON1 and TRIS)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Tur n on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wa it the requ ired acqu is itio n tim e .

4. Start conversion:

• Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result Register (ADRES), clear bit

ADIF if required.

7. For the next conversion, go to step 1, step 2 or

step 3 as required. The A/D conversion time per

bit is defined as TAD. A minimum wait of 2TAD is

required before ne xt acq uisition starts.

FIGURE 8-1: A/D BLOCK DIAGRAM

(Input voltage)

VIN

VREF

(Reference

voltage)

VDD

PCFG<2:0>

CHS<1:0>

GP4/AN3

GP0/AN0

GP2/AN2

GP1/AN1/VREF

A/D

Converter

PIC12C67X

DS30561B-page 48  1999 Microchip Technology Inc.

8.1 A/D Sampling Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 8-2. The source

impeda nce (RS) and the internal sampli ng s witch (R SS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD), see

Figure 8-2. The maximum recommended imped-

ance for analog sources is 10 kΩ. After the analog

input channel is selected (changed), this acquisition

must be done before the conversion can be started.

To calculate the minimum acquis ition time, Equation 8-1

may be use d. This equa tion assumes that 1/2 LSb error

is used (5 12 steps f or the A/D ). The 1/2 LSb error is the

maximu m error allo wed f or the A/D to m eet its spec ified

resolution.

EQUATION 8-1: A/D MINIMUM CHARGING

TIME

VHOLD = (VREF - (VREF/512)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))

Tc = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)

Example 8-1 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following system assumptions.

Rs = 10 kΩ

1/2 LSb error

VDD = 5V → Rss = 7 kΩ

Temp (sy stem ma x.) = 50°C

VHOLD = 0 @ t = 0

EXAMPLE 8-1: CALCULATING THE

MINIMUM REQUIRED

SAMPLE TIME

TACQ = Internal Amplifier Settling Time +

Holding Capa citor Cha rging Time +

Temperatu re Coeffi cient

TACQ =5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]

TC =-CHOLD (RIC + RSS + RS) ln(1/512)

-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.00 20)

-51.2 pF (18 kΩ) ln(0.0020)

-0.921 µs (-6.2146)

5.724 µs

TACQ =5 µs + 5.724 µs + [(50 °C - 25°C)(0.05 µs/°C)]

10.724 µs + 1.25 µs

11.974 µs

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels

itself out.

2: The charge holding capacitor (CHOLD) is

not discharged after each conversion.

3: The maximum recommended impedance

for analog sources is 10 kΩ. This is

required to meet the pin leakage specifi-

cation.

4: After a conversion has completed, a

2.0 TAD delay must complete before

acquisition can begin again. During this

time, the holding capacitor is not con-

nected to the selected A/D input channel.

FIGURE 8-2: ANALOG INPUT MODEL

CPIN

Rs RAx

5 pF

VDD

VT = 0.6V

VT = 0.6V I leakage

RIC ≤ 1k

Sampling

Switch

SS Rss

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

( kΩ )

VDD

= 51.2 pF

± 500 nA

Legend: CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

 1999 Microchip Technology Inc. DS30561B-page 49

PIC12C67X

8.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is defined as TAD. The

A/D conversion requires 9.5 TAD per 8-bit conversion.

The source of the A/D conversion clock is software

selected. The four possible options for TAD are:

•2T

OSC

•8TOSC

•32TOSC

• Internal ADC RC oscillator

For c orrect A /D co nversio ns, the A/ D co nve rsio n clock

(TAD) mus t be sele cted to e nsure a mi nimum TAD time

of 1.6 µs. If the minimum TAD time of 1.6 µs can not be

obtained, TAD should be ≤8 µs for preferred operation.

Table 8-1 shows the resultant TAD times derived from

the device operating frequencies and the A/D clock

sour ce se lec ted .

8.3 Configuring Analog Port Pins

The ADCON1 and TRIS Registers control the opera-

tion of the A/D port pins. The port pins that are des ire d

as analog inputs must have their corresponding TRIS

bits set (input). If the TRIS bit is cleared (output), the

digital output level (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS<2:0> bits and the TRIS bits.

Note 1: When reading the port register, all pins

configured as analog input channel will

read as cleared (a low level). Pins config-

ured as digital inputs, will convert an ana-

log input. Analog levels on a digitally

configured input will not affect the conver-

sion accuracy.

2: Analog l e v el s on an y pin t hat is defi ned a s

a digital input (including the AN<3:0>

pins) may cause the input buffer to con-

sume current that is out of the devices

specification.

TABLE 8-1: TAD vs. DEVICE OPERATING FREQUENCIES

AD Clock Source (TAD)Device Frequency

Operation ADCS<1:0> 4 MHz 1.25 MHz 333.33 kHz

2TOSC 00 500 ns(2) 1.6 µs6 µs

8TOSC 01 2.0 µs6.4 µs24 µs(3)

32TOSC 10 8.0 µs25.6 µs(3) 96 µs(3)

Internal ADC RC Osci llator(5) 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1)

Note 1: The RC source has a typical TAD time of 4 µs.

2: These values violate the minimum required TAD time.

3: For faster conversion times, the selection of another clock source is recommended.

4: While in RC mode, with device frequency above 1 MHz, conversion accuracy is out of specification.

5: For extended voltage devices (LC), please refer to Electrical Specifications sect ion.

PIC12C67X

DS30561B-page 50  1999 Microchip Technology Inc.

8.4 A/D Conversions

Exampl e 8-2 shows how to perf orm an A/D co nv ersion.

The GPIO pins are configured as analog inputs. The

analog reference (VREF) is the device VDD. The A/D

interrupt is enabled and the A/D conversion clock is

FRC. The con v ersion is pe rfo rmed on the GP0 channel.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The ADRES register will

NOT be updated with the partially completed A/D con-

version sample. That is, the ADRES register will con-

tinue to contain the value of the last completed

con v ersi on (or the l ast v alue w ritten to the ADRES reg-

ister). After the A/D conversion is aborted, a 2TAD wai t

is required before the next acquisition is star ted. After

this 2TAD w ait, an acquisition is automatically started on

the selected channel.

EXAMPLE 8-2: DOING AN A/D CONVERSION

BSF STATUS, RP0 ; Select Page 1

CLRF ADCON1 ; Configure A/D inputs

BSF PIE1, ADIE ; Enable A/D interrupts

BCF STATUS, RP0 ; Select Page 0

MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected

MOVWF ADCON0 ;

BCF PIR1, ADIF ; Clear A/D interrupt flag bit

BSF INTCON, PEIE ; Enable peripheral interrupts

BSF INTCON, GIE ; Enable all interrupts

;

; Ensure that the required sampling time for the selected input channel has elapsed.

; Then the conversion may be started.

;

BSF ADCON0, GO ; Start A/D Conversion

: ; The ADIF bit will be set and the GO/DONE bit

: ; is cleared upon completion of the A/D Conversion.

 1999 Microchip Technology Inc. DS30561B-page 51

PIC12C67X

8.5 A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS<1:0> = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

sw i tch ing no is e from the c onversion. When th e c onver-

sion is completed, the GO/DONE bit will be cleared,

and the result loaded into the ADRES Register. If the

A/D interrupt is enabled, the device will wake-up from

SLEEP. If the A /D interrupt is n ot enabled , the A/D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clo c k sourc e is another cl oc k optio n (not

RC), a SLEEP in struction w ill cause the pre sent con ver-

sion to be aborted and the A/D mo dule to be turned off ,

though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest

current co nsu mp t io n state.

8.6 A/D Accuracy/Error

The ov er all ac cu ra cy o f t he A/D is le ss t han ± 1 LSb fo r

VDD = 5V ± 10% and th e analog VREF = VDD. This o ve r-

all accuracy includes offset error, full scale error, and

integral error. The A/D converter is monotonic over the

full VDD range. The resolution and accuracy may be

less when either the analo g reference (VDD) is less than

5.0V or when the analog reference (VREF) is less than

VDD.

The maximum pin leakage current is specified in the

Device Data Sheet electrical specification, parameter

#D060.

In systems where the device frequency is low, use of

the A/D RC clock is preferred. At moderate to high fre-

quencies, TAD should be derived from the device oscil-

lator. TAD must not violate the minimum and should be

≤8 µs for preferred operation. This is because TAD,

when derived from TOSC, is kept away from on-chip

phase cl oc k tr an sitio ns . This reduc es, to a l arge extent,

the eff ects of digital s witching noise . This is not possible

with the RC derived clock. The loss of accuracy due to

digital switching noise can be significant if many I/O

pins are active.

In systems where the device will enter SLEEP mode

after the start of the A/D conversion, the RC clock

source selection is required. In this mode, the digital

noise from the modules in SLEEP are stopped. This

method gives high accuracy.

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS<1:0> = 11). To perform an A/D

conversion in SLEEP, the GO/DONE bit

must be set, followed by the SLEEP

instruction.

8.7 Effects of a Reset

A device reset forces all registers to their reset state.

This forces the A/D module to be turned off, and any

conversion is aborted. The value that is in the ADRES

ter will contain unknown data after a Power-on Reset.

8.8 Connection Considerations

If the inp ut v oltage e xce eds the r ail v alues (VSS or VDD)

by great er than 0.2V, then th e accu racy of the conver-

sion is out of specification.

An external RC filter is sometimes added for anti-

aliasing of the input signal. The R componen t should be

selected to ensure that the total source impedance is

kept un der th e 10 k Ω recommended specification. Any

external components connected (via hi-impedance) to

an analog in put pin (capacitor , zene r diode, etc.) should

have very little leakage current at the pin.

8.9 Transfer Function

The ide al transf er func tion of the A/D conv erter is a s fo l-

lows: the first transition occurs when the analog input

voltage (VAIN) is 1 LSb (or Analog VREF / 256)

(Figure 8-3).

FIGURE 8-3: A/D TRANSFER FUNCTION

Note: For the PIC12C67X, care must be taken

when using the GP4 pin in A/D con versions

due to its proximity to the OSC1 pin.

Digital code output

FFh

FEh

04h

03h

02h

01h

00h

0.5 LSb

1 LSb

2 LSb

3 LSb

4 LSb

255 LSb

256 LSb

(full scale)

Analog input voltage

PIC12C67X

DS30561B-page 52  1999 Microchip Technology Inc.

FIGURE 8-4: FLOWCHART OF A/D OPERATION

TABLE 8-2: SUMMARY OF A/D REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

Power-on

Reset

Value on

all other

Resets

0Bh/8Bh INTCON(1) GIE PEIE T0IE INTE GPIE T0IF INTF GPIF 0000 000x 0000 000u

0Ch PIR1 —ADIF — — — — — — -0-- ---- -0-- ----

8Ch PIE1 —ADIE — — — — — — -0-- ---- -0-- ----

1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 reserved CHS1 CHS0 GO/DONE reserved ADON 0000 0000 0000 0000

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

05h GPIO SCL(2) SDA(2) GP5 GP4 GP3 GP2 GP1 GP0 11xx xxxx 11uu uuuu

85h TRIS — — TRIS5 TRIS4 TRIS3 TRIS2 TRIS1 TRIS0 --11 1111 --11 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.

Note 1: These registers can be addressed from either bank.

2: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.

Acquire

ADON = 0

ADON = 0?

GO = 0?

A/D Clock

GO = 0

ADIF = 0

Abort Conversion

SLEEP

Power-down A/D Wait 2 TAD

Wake-up

Yes

Finish Conversion

GO = 0

ADIF = 1

Device in

Yes

Finish Conversion

GO = 0

ADIF = 1

Wait 2 TAD

Stay in Sleep

Selected Channel

= RC? SLEEP

Yes

Instruction?

Start of A/D

Conversion Delayed

1 Instruction Cycle

From Sleep?

Power-down A/D

Yes

Wait 2 TAD

Finish Conversion

GO = 0

ADIF = 1

SLEEP?

 1999 Microchip Technology Inc. DS30561B-page 53

PIC12C67X

9.0 SPECIAL FEATURES OF THE

CPU

What sets a microcontroller apart from other proces-

sors are special circuits to deal with the needs of real-

time ap plication s. The PIC12C67X family has a ho st of

such features intended to maximize system reliability,

minimize cost through elimination of external compo-

nents , pro vide po wer savi ng opera ting mo des and off er

code protection. These are:

• Oscillator selection

• Reset

- Power-on Reset (POR)

- P o wer-up Tim er (PWRT)

- Oscillator Start-up Timer (OST)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming

The PIC12C67X has a Watchdog Timer, which can be

shut off only through configuration bits. It runs off its

own RC oscillator for added reliability. There are two

timers that offer neces sary delays on po w e r-up. One i s

the Oscillator Start-up Timer (OST), intended to keep

the chi p in rese t until th e crystal osci llator is stab le. Th e

other is th e Pow er-u p Tim er (PWRT), which provides a

fixed delay of 72 ms (nominal) on power-up only,

designe d to k ee p the pa rt in reset while the po w er su p-

ply stabilizes. With these two timers on-chip, most

applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current

pow er-down m ode. The user can w ake-up from SLEEP

through external reset, Watchdog Timer Wake-up, or

through an interrupt. Se veral oscill ator opti ons are also

made available to allow the part to fit the application.

The INTRC/EXTRC oscillator option saves system

cost, while the LP cr ystal option saves power. A set of

configuration bits are used to select various options.

9.1 Configuration Bits

The con figur ati on bits c an be progr a mmed (read as '0')

or left unprogrammed (read as '1') to select various

device configurations. These bits are mapped in pro-

gram memory location 2007h.

The user will note that address 2007h is beyond the

user program memory space. In fact, it belongs to the

special test/configuration memory space (2000h-

3FFFh), which can be accessed only during

programming.

CP1 CP0 CP1 CP0 CP1 CP0 MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0 Register: CONFIG

Address 2007h

bit13 bit0

bit 13-8, CP<1:0>: Code Protection bit pairs(1)

6-5: 11 = Code protection off

10 = Locations 400h through 7FEh code protected (do not use for PIC12C671 and PIC12CE673)

01 = Locations 200h through 7FEh code protected

00 = All memory is code protected

bit 7: MCLRE: Master Clear Reset Enable bit

1 = Master Clear Enabled

0 = Master Clear Disabled

bit 4: PWRTE: Power-up Timer Enable bit

1 = PWRT disabled

0 = PWRT enabled

bit 3: WDTE: Wat c hdog Timer Enable bit

1 = WDT enabled

0 = WDT disabled

bit 2-0: FOSC<2:0>: Oscillator Selection bits

111 = EXTRC, Clockout on OSC2

110 = EXTRC, OSC2 is I/O

101 = INTRC, Clockout on OSC2

100 = INTRC, OSC2 is I/O

011 = Invalid Selection

010 = HS Oscillator

001 = XT Oscillator

000 = LP Oscillator

Note 1: All of the CP<1:0> pairs have to be given the same value to enable the code protection scheme listed.

PIC12C67X

DS30561B-page 54  1999 Microchip Technology Inc.

9.2 Oscillator Configurations

9.2.1 OSCILLATOR TYPES

The PIC12C67X can be operated in seven different

oscillator modes. The user can program three

configuration bits (FOSC<2:0>) to select one of these

seven modes:

• LP: Low Power Crystal

• HS: High Speed Crystal/Resonator

• XT: Crystal/Resonator

• INTRC*: Internal 4 MHz Oscillator

• EXTRC*: External Resistor/Capacitor

*Can be configured to support CLKOUT

9.2.2 CRYSTAL OSCILLATOR / CERAMIC

RESONATORS

In XT, HS or LP modes, a crystal or ceramic resonator

is con necte d to the GP 5/OS C1 /C LKIN a nd G P4/O SC2

pins to establish oscillation (Figure 9-1). The

PIC12C67X oscillator design requires the use of a

par allel cut crystal. Use of a se ries cut c rystal may giv e

a frequency out of the crystal manufacturers

specifications. When in XT, HS or LP modes, the

device can have an external clock source drive the

GP5/OSC1/CLKIN pin (Figure 9-2).

FIGURE 9-1: CRYSTAL OPERATION

(OR CERAMIC RESONATOR)

(XT, HS OR LP OSC

CONFIGURATION)

FIGURE 9-2: EXTERN AL CLOCK INPUT

OPERATION (XT, HS OR LP

OSC CONFIGURATION)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS ) may be required for AT

strip cut crystals.

3: RF varies with the oscillator mode selected

(approx. value = 10 MΩ).

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3) SLEEP

To internal

logic

RS(2)

PIC12C67X

Clock from

ext. system OSC1

OSC2 PIC12C67X

Open

TABLE 9-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC12C67X

TABLE 9-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC12C67X

Osc

Type Resonator

Freq Cap. Range

C1 Cap. Range

XT 455 kHz

2.0 MHz

4.0 MHz

22-100 pF

15-68 pF

22-100 pF

15-68 pF

HS 4.0 MHz

8.0 MHz

10.0 MHz

15-68 pF

10-68 pF

10-22 pF

15-68 pF

10-68 pF

10-22 pF

These values are for design guidance only. Since

each resonator has its own characteristics, the user

should consult the resonator manufacturer for

appropriate values of external components.

Osc

Type Resonator

Freq Cap. Range

C1 Cap. Rang e

LP 32 kHz(1)

100 kHz

200 kHz

15 pF

15-30 pF

15 pF

30-47 pF

15-82 pF

XT 100 kHz

200 kHz

455 kHz

1 MHz

2 MHz

4 MHz

15-30 pF

15-47 pF

200-300 pF

100-200 pF

15-100 pF

15-30 pF

15-47 pF

HS 4 MHz

8 MHz

10 MHz

15-30 pF

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is

recommended.

These values are for design guidance only. Rs may

be required in HS mode, as well as XT mode, to

avoid overdriving crystals with low drive level specifi-

cation. Since each crystal has its own characteris-

tics , the user s hould cons ult th e crystal man ufacturer

for appropriate values of external components.

 1999 Microchip Technology Inc. DS30561B-page 55

PIC12C67X

9.2.3 EXTERNAL CRYSTAL OSCILLATOR

CIRCUIT

Either a pre-packaged oscillator or a simple oscillator

circuit with TTL gates can be used as an external

crystal oscillator circuit. Pre-packaged oscillators

provide a wide operating range and better stability. A

well-designed crystal oscillator will provide good

performance with TTL gates. Two types of crystal

oscillator circuits can be used; one with parallel

resonance or one with series resonance.

Figure 9-3 shows implementation of a parallel

resonant oscillator circuit. The circuit is designed to

use the fundamental frequency of the crystal. The

74AS04 inverter performs the 180-degree phase shift

that a parallel oscillator requires. The 4.7 kΩ resistor

provides the negative feedback for stability. The 10 kΩ

potentiometers bias the 74AS04 in the linear region.

This circuit could be used for external oscillator

designs.

FIGURE 9-3: EXTERN AL PARALLEL

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

Figure 9-4 shows a series resonant oscillator circuit.

This circuit is also designed to use the fundamental

frequency of the crystal. The inver ter performs a 180-

degree phase shift in a series resonant oscillator

circuit. The 330 Ω resistors provide the negative

feedback to bias the inverters in their linear region.

FIGURE 9-4: EX TERNAL SERIES

RESONANT CRYSTAL

OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k 4.7k

10k

74AS04

XTAL

10k

74AS04 PIC12C67X

CLKIN

To Other

Devices

330

74AS04 74AS04 PIC12C67X

CLKIN

To Othe r

Devices

XTAL

330

74AS04

0.1 µF

9.2.4 EXTERNAL RC OSCILLATOR

For timing insensitive applications, the RC device

option offers additional cost savings. The RC oscillator

frequency is a function of the supply voltage, the

resistor (REXT) and capacitor (CEXT) values, and the

operating temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal

process parameter variation. Furthermore, the

differen ce in lea d fr am e c ap ac ita nce between package

types will also affect the oscillation frequency,

especially for low CEXT values. The user also needs to

take into account variation due to tolerance of external

R and C components used.

Figure 9-5 shows how the R/C combination is

connected to the PIC12C67X. For REXT values below

2.2 kΩ, the oscillator operation may become unstable

or stop completely. For very high REXT values

(i.e., 1 MΩ), the oscillator becomes sensitive to noise,

humidity and leakage. Thus, we recommend keeping

REXT between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external

capacitor (CEXT = 0 pF), we recommend using values

above 20 pF for noise and stability reasons. With no or

small external capacitance, the oscillation frequency

can vary dramatically due to changes in external

capacitances, such as PCB trace capacitance or

package le ad frame capacitanc e.

The variation is larger for larger R (since leakage

current variation will affect RC frequency more for

large R) and for smaller C (since variation of input

capacitance will affect RC frequency more).

FIGURE 9-5: EXTERNAL RC OSCILLATOR

MODE

VDD

REXT

CEXT

VSS

OSC1 Internal

clock

PIC12C67X

OSC2/CLKOUT

FOSC/4

PIC12C67X

DS30561B-page 56  1999 Microchip Technology Inc.

9.2.5 INTERNAL 4 MHz RC OSCILLATOR

The internal RC oscillator pro vides a fixed 4 MHz (nom-

inal) system clock at VDD = 5V and 25°C. See

Section 13.0 for information on variation over voltage

and temperature.

In addit ion , a calibr a tion in struction is pro gr ammed into

the las t address of the program memory which contain s

the calibration value for the internal RC oscillator. This

value is programmed as a RETLW XX instruction where

XX is the calibration value. In order to retrieve the cali-

bra tion value, iss ue a CALL YY instruction where YY is

the last location in program memory (03FFh for the

PIC12C671 and the PIC12CE673, 07FFh for the

PIC12C672 and the PIC12CE674). Control will be

returned to the user’s program with the calibration

value loaded into the W register. The program should

then perfor m a MOVWF OSCCAL instruction to load the

value into the internal RC oscillator trim register.

OSCCAL, when written to with the calibration v alue, will

“trim” the internal osci llator to remov e pr ocess v ariation

from the o scillator fre quency. Bits <7:4>, C AL<3:0> are

used f or fi ne cali brati on, wh ile bit 3 , CALFST, and bit 2,

CALSL W, are used f or more coarse adjustment. Ad just-

ing CAL<3:0> from 0000 to 1111 yields a higher clock

speed. Set CALFST = 1 for greater increase in fre-

quency or set CALS LW = 1 for g r eat er dec rea se in fre-

quency. Note that bits 1 and 0 of OSCCAL are

unimplemented and should be written as 0 when mod-

ifying OSCCAL for compatibility with future devices.

9.2.6 CLKOUT

The PIC12C67X can be configured to provide a clock

out signal (CLKOUT) on pin 3 when the configuration

word address (2007h) is programmed with FOSC2,

FOSC1, and FOSC0, equal to 101 for INTRC or 111 for

EXTRC. The oscillator frequency, divided by 4, can be

used for test purposes or to synchronize other logic.

Note: Please note that erasing the device will

also erase the pre-programmed internal

calibration value for the internal oscillator.

The calibration value must be saved prior

to erasing the part.

9.3 Reset

The PIC12C67X differentiates between various kinds

of reset:

• Power-on Reset (POR)

•MCLR

Reset during normal operation

•MCLR

Reset during SLEEP

• WDT Reset (normal operation)

Some registers are not affected in any reset condition;

their statu s is unk nown on POR and unchan ged in any

other reset. Most other registers are reset to a “reset

state” on Power-on Reset (POR), MCLR Reset, WDT

Reset, and MCLR Reset du ri ng SLE EP. Th ey are no t

affected by a WDT Wake-up, which is viewed as the

resumption of normal operation. The TO and PD bits

are set or cleared diff erently in diff erent reset situations ,

as indicated in Table 9-5. These bits are used in

software to determine the nature of the reset. See

Table 9-6 for a full description of reset states of all

registers.

A simplifi ed b loc k diag ram of the on-ch ip res et circui t is

shown in Figure 9-6.

The PIC12C67X has a MCLR noise filter in the MCLR

reset path. The filter will detect and ignore small pulses.

It should be noted that a WDT Reset

does not drive

MCLR pin low.

When M CLR i s asserted, the s tate o f the OS C1/CLKIN

and CLKOUT/OSC2 pins are as follows:

TABLE 9-3: CLKIN/CLKOUT PIN STATES

WHEN MCLR ASSERTED

Oscillator Mode OSC1/CLKIN Pin OSC2/CLKout Pin

EXTRC, CLKOUT

on OSC2 OSC1 pin is

tristated and

driven by external

circuit

OSC2 pin is driven

low

EXTRC, OSC2 is

I/O OSC1 pin is

tristated and

driven by external

circuit

OSC2 pin is

tristate input

INTRC, CLKOUT

on OSC2 OSC1 pin is

tristate input OSC2 pin is driven

low

INTRC, OSC2 is

I/O OSC1 pin is

tristate input O S C2 pin is

tristate input

 1999 Microchip Technology Inc. DS30561B-page 57

PIC12C67X

FIGURE 9-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Weak

Pull-up

GP3/MCLR/VPP Pin

VDD

OSC1/

WDT

Module

VDD rise

detect

OST/PWRT

On-chip(1)

RC OSC

WDT Time-out

P ower-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Enable OST

Enable PWRT

SLEEP

See Table 9-4 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

CLKIN

10-bit Ripple-counter

MCLRE

INTER NA L M CLR

PIC12C67X

DS30561B-page 58  1999 Microchip Technology Inc.

9.4 Power-on Rese t (POR), Power-up

Timer (PWRT) and Oscillator Start-up

Timer (OST)

9.4.1 POWER-ON RESET (POR)

The on-chip POR circuit holds the chip in reset until

VDD has reache d a high enough le v el f or proper op er a-

tion. To take advantage of the POR, just tie the MCLR

pin th ro ugh a resi stor to VDD. This will eliminate exter-

nal R C co mp one nts u sua ll y n eeded to cre ate a Power-

on Reset. A maximum rise time for VDD is specified.

See Electrical Spec ifi cat ion s for detail s.

When the device starts normal operation (exits the

reset co ndi tion), device operati ng p arameters (voltage ,

frequency, temperature, ...) must be met to ensure

operation. If these conditions are not met, the device

must be h eld in re set un til the o per ating condi tions a re

met.

For additional information, refer to Application Note

AN607, "

Power-up Trouble Shooting

9.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up only, from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is ke pt in re set a s long as th e PWR T i s act ive. The

PWRT’s time delay allows VDD to rise to an acceptable

level. A configuration bit is provided to enable/disable

the PWRT.

The po wer-up tim e dela y will vary from chip to chip due

to VDD, temperature and process variation. See

Table 11-4.

9.4.3 OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides 1024

oscillator cycle (from OSC1 input) delay after the

PWR T dela y i s ov er . This e nsures that th e crystal osci l-

lator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or wake-up from

SLEEP.

9.4.4 TIME-OUT SEQUENCE

On power-up, the Time-out Sequence is as follows:

first, PWRT time-out is invoked after the POR time

delay has expired; then, OST is activated. The total

time-out will vary, based on osci llator con figur ation an d

the status of th e PWRT. For example, in R C mo de w i th

the PWRT disabled, there will be no time-out at all.

Figure 9-7, Figure 9-8, and Figure 9-9 depict time-out

sequences on power-up.

Since the time-outs occu r from the POR puls e, if MCLR

is k ept lo w lon g enoug h, the time -outs wil l e xpire . The n

bringing MCLR high will begin execution immediately

(Figure 9-9). This is useful for testing purposes or to

synch roniz e mo re than o ne PIC12C 67X device opera t-

ing in parallel.

9.4.5 POWER CONTROL (PCON)/STATUS

The Power Control/Status Register, PCON (address

8Eh), has one bit. See Register 4-6 for register.

Bit1 is POR (P ower- on Reset). It is cleared on a P o wer-

on Reset and is unaffected otherwise. The user sets

this bit following a Power-on Reset. On subsequent

resets, if POR is ‘0’, it will indicate that a Power-on

Reset must have occur red.

TABLE 9-4: TIME-OUT IN VARIOUS SITUATIONS

TABLE 9-5: STATUS/PCON BITS AND THEIR SIGNIFICANCE

Legend: u = unchanged, x = unkn own.

Oscillator Configuration Power-up Wake-up from SLEEP

PWRTE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024TOSC 1024TOSC 1024TOSC

INTRC, EXTRC 72 ms — —

POR TO PD

011Power-on Reset

00xIllegal, TO is set on P OR

0x0Illegal, PD is set on POR

10uWDT Reset

100WDT Wake-up

1uuMCLR Reset during normal operation

110MCLR Reset during SLEEP or interrupt wake-up from SLEEP

 1999 Microchip Technology Inc. DS30561B-page 59

PIC12C67X

TABLE 9-6: RESET CONDITION FOR SPECIAL REGISTERS

TABLE 9-7: INITIALIZATION CON\DITIONS FOR ALL REGISTERS

Condition Program

Counter STATUS

Powe r-on Rese t 000h 0001 1xxx ---- --0-

MCLR Reset during normal operation 000h 000u uuuu ---- --u-

MCLR Reset during SLEEP 000h 0001 0uuu ---- --u-

WDT Reset during normal operation 000h 0000 uuuu ---- --u-

WDT Wake-up from SLEEP PC + 1 uuu0 0uuu ---- --u-

Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --u-

Legend: u = unchanged, x = unknown, - = unimplemented bit read as ’0’.

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

WDT Reset Wake-up via

WDT or Interrupt

Wxxxx xxxx uuuu uuuu uuuu uuuu

INDF 0000 0000 0000 0000 0000 0000

TMR0 xxxx xxxx uuuu uuuu uuuu uuuu

PCL 0000 0000 0000 0000 PC + 1(2)

STATUS 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR xxxx xxxx uuuu uuuu uuuu uuuu

GPIO

PIC12CE67X 11xx xxxx 11uu uuuu 11uu uuuu

GPIO

PIC12C67X --xx xxxx --uu uuuu --uu uuuu

PCLATH ---0 0000 ---0 0000 ---u uuuu

INTCON 0000 000x 0000 000u uuuu uqqq(1)

PIR1 -0-- ---- -0-- ---- -q-- ----(4)

ADCON0 0000 0000 0000 0000 uuuu uquu(5)

OPTION 1111 1111 1111 1111 uuuu uuuu

TRIS --11 1111 --11 1111 --uu uuuu

PIE1 -0-- ---- -0-- ---- -u-- ----

PCON ---- --0- ---- --u- ---- --u-

OSCCAL 0111 00-- uuuu uu-- uuuu uu--

ADCON1 ---- -000 ---- -000 ---- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition.

Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).

3: See Table 9-5 for reset value for specific condition.

4: If wake-up w as due to A/D completing then bit 6 = 1, all other interrupts generating a wake-up will cause bit 6 = u.

5: If wake-up w as due to A/D completing then bit 3 = 0, all other interrupts generating a wake-up will cause bit 3 = u.

PIC12C67X

DS30561B-page 60  1999 Microchip Technology Inc.

FIGURE 9-7: TIME-OUT SEQUENCE ON P OWER-UP (MCLR NO T TI ED TO VDD): CASE 1

FIGURE 9-8: TIME-OUT SEQUENCE ON P OWER-UP (MCLR NO T TIED TO VDD): CASE 2

FIGURE 9-9: TIME-OUT SEQUENCE ON P OWER-UP (MCLR TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OS T TI M E-OU T

INTERNAL RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

 1999 Microchip Technology Inc. DS30561B-page 61

PIC12C67X

FIGURE 9-10: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW

VDD POWER-UP)

Note 1: External P o w er-on Reset circuit is required only

if VDD power-up slope is too slow. The diode D

helps discharge the capacitor quickly when VDD

powers down.

2: R < 40 kΩ is recommended to make sure that

voltage drop across R does not violate the

device’s electrical specification.

3: R1 = 100Ω to 1 kΩ will limit any current flowing

into MCLR from external capacitor C, in the

event of MCLR/VPP pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS).

VDD

MCLR

PIC12C67X

FIGURE 9-11: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 9-12: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: This circuit will activate reset when VDD goes

below (Vz + 0.7V), where Vz = Zener voltage.

2: Resistors should be adjusted for the character-

istics of the transistor.

VDD 33k

10k

4.3k

VDD

MCLR

PIC12C67X

Note 1: This brown-out circuit is less expensive,

albeit less accurate. Transistor Q1 turns off

when VDD is below a certain level such t hat:

2: Resistors should be adjusted for the charac-

terist ics of the transistor.

VDD • R1

R1 + R2 = 0.7V

VDD

R2 4.3k PIC12C67X

VDD

MCLR

PIC12C67X

DS30561B-page 62  1999 Microchip Technology Inc.

9.5 Interrupts

There are four sources of interrupt:

The Interrupt Control Register (INTCON) records indi-

vidual interrupt requests in flag bits. It also has individ-

ual and global int errupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>),

enables (if set) all un-masked interrupts or disables (if

cleared) all interrupts. When bit GIE is enabled and an

interrupt’ s flag bit and mas k bit are set, the interrupt wil l

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt flag bits are set,

regardle ss of the st atus of th eir corres ponding m ask bit

or the GIE bit. The GIE bit is cleared on reset.

Interrupt Sources

TMR0 Overflow Interrupt

External Interrupt GP2/INT pin

GPIO Port Change Interrupts (pins GP0, GP1, GP3)

A/D Interrupt

Note: Indiv idual interrupt fla g bits are set, regard-

less of the status of their corresponding

mask bit or the GIE bit.

The “return-from-interrupt” instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables interrupts.

The GP2/INT, GPIO port change interrupt and the

TMR0 overflow interrupt flags are contained in the

INTCON register.

The peripheral interrupt flag ADIF, is contained in the

Special Function Register PIR1. The corresponding

interrupt enable bit is contained in Special Function

contained in Special Function Register INTCON.

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pu sh ed onto the sta ck and the PC is lo ade d

with 0004h. Once in the interrupt service routine, the

source(s) of the interrupt can be determined by polling

the interrupt flag bits. The interrupt flag bit(s) must be

cleared in software before re-enabling interrupts to

avoid repeated interrupts.

For external interrupt events, such as GPIO change

interrupt, the interrupt latency will be three or four

inst ruction c yc les. The exact latency de pen ds on whe n

the interrupt event occurs (Figure 9-14). The latency is

the same for one or two cycle instructions. Individual

interrupt flag bits are set, regardless of the status of

their corresponding mask bit or the GIE bit.

FIGURE 9-13: INTERRUPT LOGIC

GPIF

GPIE

T0IF

T0IE

GIE

Wake-up

(If in SLEEP mode)

Interrupt to CPU

PEIE

ADIF

ADIE

INTF

INTE

 1999 Microchip Technology Inc. DS30561B-page 63

PIC12C67X

FIGURE 9-14: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT p in

INTF flag

(INTCON<1>)

GIE bi t

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

Interrupt Latency

PC PC+1 PC+1 0004h 0005h

Inst (0004h) Inst (0005h)

Dummy Cycle

Inst (PC) Inst (PC+1)

Inst (PC-1) Inst (0004h)

Dummy Cycle

Inst ( PC)

—

Note 1: INTF flag is sampled here (ev ery Q1).

2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

3: CLKOUT is available only in INTRC and EXTRC oscillator modes.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

PIC12C67X

DS30561B-page 64  1999 Microchip Technology Inc.

9.5.1 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>) (Section 7.0). The flag bit T0IF

(INTCON<2>) will be set, regardless of the state of the

enable bits. If used, this flag must be cleared in software.

9.5.2 INT INTERRUPT

External interrupt on GP2/INT pin is edge triggered;

either rising if bit INTEDG (OPTION<6>) is set, or fall-

ing, if the INTEDG bit is clear. When a valid edge

appears on the GP2/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be clea red in s oftware i n the in terrupt service rou-

tine before re-enabling this interrupt. The INT interrupt

can w ake-up the proces sor from SLEE P, if bit INTE was

set prior to goin g into SLEEP. The status of gl obal inter-

rupt enable bit GIE decides whether or not the proces-

sor b ra nch es t o t he in t errupt vec tor followin g wake-u p.

See Section 9.8 for details on SLEEP mode.

9.5.3 GPIO INTCON CHANGE

An input change on GP3, GP1 or GP0 sets flag bit GPIF

(INTCON<0>). The interrupt can be enabled/disabled by

setting/clearing enable bit GPIE (INTCON<3>)

(Section 5.1) . This flag bit GPIF (INTCON<0>) will be

set, regardless of the state of the enable bits. If used, this

flag must be clea red in softw a re.

9.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on th e stack. Typically, users m a y wi sh to sa v e key re g-

isters during an interrupt (i.e., W register and STATUS

Example 9-1 shows the storing and restoring of the

STATUS and W re gisters . Th e regist er, W_TEMP, must

be defined in both banks and must be defined at the

same offset from the bank base address (i.e., if

W_TEMP is defined at 0x20 in bank 0, it must also be

defined at 0xA0 in bank 1).

Example 9-2 shows the saving and restoring of STA-

TUS and W using RAM locations 0x70 - 0x7F.

W_TEMP is defined at 0x70 and STATUS_TEMP is

defined at 0x71.

The example:

a) Stores the W register.

b) Stores the STATUS register in bank 0.

c) Executes the ISR code.

d) Restores the STATUS register (and bank select

bit).

e) Restores the W register.

f) Returns from interrupt.

EXAMPLE 9-1: SAVING STATUS AND W REGISTERS USING GENERAL PURPOSE RAM

(0x20 - 0x6F)

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero

SWAPF STATUS,W ;Swap status to be saved into W

BCF STATUS,RP0 ;Change to bank zero, regardless of current bank

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

:(ISR)

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

RETFIE ;Return from interrupt

EXAMPLE 9-2: SAVING STATUS AND W REGISTERS USING SHARED RAM (0x70 - 0x7F)

MOVWF W_TEMP ;Copy W to TEMP register (bank independent)

MOVF STATUS,W ;Move STATUS register into W

MOVWF STATUS_TEMP ;Save contents of STATUS register

:(ISR)

MOVF STATUS_TEMP,W ;Retrieve copy of STATUS register

MOVWF STATUS ;Restore pre-isr STATUS register contents

SWAPF W_TEMP,F ;

SWAPF W_TEMP,W ;Restore pre-isr W register contents

RETFIE ;Return from interrupt

 1999 Microchip Technology Inc. DS30561B-page 65

PIC12C67X

9.7 Watchdog Timer (WDT)

The Watchdog Timer is a free running, on-chip RC

oscillator, which does not require any exter nal compo-

nents . T his RC os cilla tor is s epar ate from the R C osci l-

lator of the OSC1/CLKIN pin. That means that the WDT

will run, even if the clock on the OSC1/CLKIN and

OSC2/CLKOUT pins of the device has been stopped,

for example, by execution of a SLEEP instruction. Dur-

ing normal operation, a WDT time-out generates a

device RESET (W atchdog Timer Reset). If the de vice is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation (Watch-

dog Timer Wake-up). The WDT can be permanently

disabled by clearing configuration bit WDTE

(Section 9.1).

9.7.1 WDT PERIOD

The WDT h as a nomina l time-o ut period of 18 ms (wi th

no presca ler). The time- out pe riod s vary with temp er a-

ture, VDD and process variations from part to part (see

DC specs). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT under software control by writing

to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the pos tscaler , if assi gned to the WDT, and pre v ent

it from timing out early and generating a premature

device RESET condition.

The TO bit in the STATUS register will be cleared upon

a Watchd og Timer tim e-ou t.

9.7.2 WDT PROGRAMMING CONSIDERATIONS

It should also be taken into account that under worst

case conditions (VDD = Min., Temperature = Max., and

max. WDT prescaler), it may take several seconds

before a WDT time-out occurs.

See Examp le 7-1 an d Ex am ple 7-2 for changing pres -

caler between WDT and Timer0.

Note: When the prescaler is assigned to the

WDT, alwa ys e xecute a CLRWDT instruction

before changing the prescale value, other-

wise a W DT reset may occur.

FIGURE 9-15: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 9-8: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Config. bits(1) MCLRE CP1 CP0 PWRTE WDTE FOSC2 FOSC1 FOSC0

81h OPTION GPPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer.

Note 1: See Register 9- 1 for operation of these bits. Not all CP0 and CP1 bits are shown.

From TMR0 Clock Source

(Figure 7-5)

To TMR0 (Figure 7-5)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX PS<2:0>

MUX PSA

WDT

Time-out

Note: PSA and PS<2:0> are bits in the OPTION register.

PIC12C67X

DS30561B-page 66  1999 Microchip Technology Inc.

9.8 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

ke eps running , the PD bit (STATUS<3>) is cleared, th e

TO (STATUS<4>) bit is set, and the oscillator driver is

tur ned off. The I/O por ts maint ain the st atus they had,

before the SLEEP instruction was executed (driving

high, low or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down

the A/D, and disable external clocks. Pull all I/O pins

that are hi-impedance inputs, high or low externally, to

avoid switchin g c urre nts ca us ed by floating inp uts. The

T0CKI input, if enabled, should also be at VDD or VSS

for lowest current consumption. The contribution from

on-chip pull-ups on GPIO should be considered.

The MC LR pi n, i f ena bled, must b e at a log ic hig h level

(VIHMC).

9.8.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. Exter nal reset input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. GP2/INT interrupt, interrupt GPIO port change

or some Peripheral Interrupts.

External MCLR Reset will cause a device reset. All

other events are considered a continuation of program

execution and cause a "wake-up". The TO and PD bits

in the STATUS register can be used to determine the

cause of device reset. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred (and caused

wake-up).

The following peripheral interrupt can wake the device

from SLEEP:

1. A/D conversion (when A/D clock source is RC).

Other peripherals can not generate interrupts since

during SLEEP, no on-chip Q clocks are present.

When th e SLEEP inst ruction is being ex ecuted, the ne xt

instruction (PC + 1) is pre-fetched. For the device to

wake-up through an interrupt event, the corresponding

inte rrup t ena ble bit mus t be set (enabled ). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP inst ru ction . If the GIE bi t is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

ru pt ad dress (00 04h ). In ca ses wh ere the execution of

the instruction following SLEEP is not desirable, the

user shoul d have a NOP after the SLEEP instruction.

9.8.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and inte rrupt flag bit se t, one o f the f o llo wing w ill o ccur:

• If the interrupt occurs before the the execution of

a SLEEP instruction, the SLEEP instruc tio n wi ll

complete as a NOP. Theref ore, the WDT an d WDT

pos tscaler will not be clear ed, the TO bit will not

be set and PD bits will not be cleare d.

• If the interrupt occurs during or after the execu-

tion of a SLEEP instruction, the device will im me-

diately wake-up from sleep . The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

pos tscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT in stru c-

tion should be executed before a SLEEP instruction.

 1999 Microchip Technology Inc. DS30561B-page 67

PIC12C67X

FIGURE 9-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

GPIO pin

GPIF flag

(INTCON<0>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 3)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for INTRC and EXTRC osc mode.

3: GIE = ’1’ assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = ’0’, execution will

continue in-line.

4: CLK OUT is not availab le in XT, HS or LP osc modes, but shown here for timing reference.

9.9 Program Verification/Code Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verification purposes.

9.10 ID Locations

F our memory locations (2000h - 200 3h) are designated

as ID locations, where the user can store checksum or

other code-identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during program/verify. It is recom-

mended that only the 4 least significant bits of the ID

location are used.

9.11 In-Circuit Serial Programming

PIC12C67X microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done wit h two lines f or c lock a nd dat a, and thre e

other lines f or po wer , g round and the prog ramming volt-

age. This all ows customers to manuf ac ture boards with

unprogrammed devices, and then program the micro-

controller just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

The device is placed into a program/verify mode by

holding the GP1 and GP0 pins low, while raising the

MCLR (VPP) pin from VIL to VIHH (see programming

specification). GP1 (clock) becomes the programming

clock and GP0 (data) becomes the programming data.

Both GP0 and GP1 are Schmitt Trigger inputs in this

mode.

Note: Microchip does not recommend code pro-

tecting windowed devices.

After reset, and if the device is placed into program-

ming/verify mode, the program counter (PC) is at loca-

tion 00h. A 6-bit command is then supplied to the

device. Depending on the command, 14-bits of pro-

gram data are then supplied to or from the device,

depending if the command was a load or a read. For

complete details of serial programming, please refer to

the PIC12C67X Programming Specifications.

FIGURE 9-17: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING

CONNECTION

External

Connector

Signals

To Normal

Connections

To Normal

Connections

PIC12C67X

VDD

VSS

MCLR/VPP

GP1

GP0

+5V

VPP

CLK

Data I/O

VDD

PIC12C67X

DS30561B-page 68  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 69

PIC12C67X

10.0 INST RUCTION SET SUMMARY

Each PIC12C67X instruction is a 14-bit word divided

into an OPCODE which specifies the instruction type

and one or more operands which further specify the

operation of the instruction. The PIC12C67X instruc-

tion se t summary in Tab le 10-2 li sts byte-oriented, bit-

oriented, a nd literal and control op erations . Table 10-

1 shows the opco de field descriptions.

For byte-oriented instructions, ’f’ represents a file reg-

ister designator and ’d’ represents a destination desig-

nator. The file register designator specifies which file

The desti nation designator specifies where the res ult of

the operation is to be placed. If ’d’ is zero, the result is

placed in the W register . If ’d’ is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, ’b’ represents a bit field

design ator which s el ec ts the n um ber of th e b it aff ected

by the operation, while ’f’ represents the number of the

file in which the bit is located.

For literal and control operations, ’k’ represents an

eight or eleven bit constant or literal value.

TABLE 10-1: OPCODE FIELD

DESCRIPTIONS

Field Description

fRegister file address (0x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon’t care location (= 0 or 1)

The assembler will generat e code with x = 0. I t is t he

recommended form of use for compatibility with all

Microch ip software tools.

dDestination select; d = 0: store result in W,

d = 1: store result in file register f.

Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

PCLATH Program Counter High Latch

GIE Global Interrupt Enable bit

WDT Wat chdog Timer/Counter

TO Time-out bit

PD Power-down bit

dest Destination either the W register or the specified

[ ] Options

( ) Contents

→Assigned to

< > Regis ter bit field

∈In the set of

talics

User defined term (font is courier)

The instruction set is highly orthogonal and is grouped

into three basic categories:

•Byte-oriented ope ra tio ns

•Bit-oriented operations

•Literal and control operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the pro-

gram counter is changed as a result of an instruction.

In this case, the execution takes two instruction cycles

with the second cycle e xecuted as a NOP. One instruc-

tion cycle consists of four oscillator periods. Thus, for

an osci llator frequenc y of 4 MHz, t he normal ins truction

ex ecution time is 1 µs. If a c ondit ional te st is true or the

program counter is changed as a result of an instruc-

tion, the instruction execution time is 2 µs.

Table 10-2 lists the instructions recognized by the

MPASM assembler .

Figure 10-1 shows the three general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGURE 10-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future PIC12C67X products, do not use the

OPTION and TRIS instructio ns.

Byte-oriented file register operations

13 8 7 6 0

d = 0 for dest ination W

OPCODE d f (FIL E #)

d = 1 for dest ination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT # ) f (FIL E #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC12C67X

DS30561B-page 70  1999 Microchip Technology Inc.

10.1 Spe cial Func tion Reg isters as

Source/Destination

The PIC12C67X’s orthogonal instruction set allows

read and write of all file registers, including special

function registers. There are some special situations

the user should be aware of:

10.1.1 STATUS AS DESTINATION

If an instructio n writes to STATUS , the Z, C and DC bit s

may be set or clear ed as a result of the instruction and

overwrite the original data bits written. For example,

executing CLRF STATUS will clear register STATUS,

and then set the Z bit leaving 0000 0100b in the reg-

ister.

10.1.2 TRIS AS DESTINATION

Bit 3 of the TRIS register always reads as a '1' since

GP3 is an input only pin. This f act can aff ect some read-

modify-write operations on the TRIS register.

10.1.3 PCL AS SOURCE OR DESTINATION

Read, write or read-modify-write on PCL may have the

following results:

Read PC: PCL → dest

Write PCL: PCLATH → PCH;

8-bit destination value → PCL

Read-Modify-Write: PCL→ ALU operand

PCLATH → PCH;

8-bit result → PCL

Where PCH = program counter high byte (not an

addressable register), PCLATH = Program counter

high holding latch, dest = destination, WREG or f.

10.1.4 BIT MANIPULATION

All bit manipulation instructions are done by first read-

ing the entire re gister , oper ating on t he selec ted bit an d

writing the result back (read-modify-write). The user

should keep this in mind when operating on special

function registers, such as por ts.

 1999 Microchip Technology Inc. DS30561B-page 71

PIC12C67X

TABLE 10-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Compleme nt f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0000

dfff

lfff

0xx0

dfff

ffff

0011

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if C l ear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move lit eral to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself ( i.e., MOVF PORTB, 1), the value used will be that v alue present

on the pins themselves . For example, if the data latch is ’1’ for a pin configured as input and is driven low by an external

devi ce, the data will be written back with a ’0’.

2: If this instruction is e x ecuted on the T MR0 register (and, where applicable , d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

PIC12C67X

DS30561B-page 72  1999 Microchip Technology Inc.

10.2 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [

label

] ADDLW k

Operands: 0 ≤ k ≤ 255

Operat ion: (W) + k → (W)

Status Affected: C, DC, Z

Encoding: 11 111x kkkk kkkk

Desc ription: The contents of the W regist er are

added to th e eight bit liter al ’ k’ and

the re sul t is placed in the W reg is-

ter.

Words: 1

Cycles: 1

Example ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [

label

] ADDW F f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (dest)

Status Affected: C, DC, Z

Encoding: 00 0111 dfff ffff

Desc ription: Add the contents of the W regis ter

with regis ter ’f’ . If ’d ’ is 0, the res ult

is stored in the W register. If ’d’ is

1, the result is stored back in reg-

ister ’f’.

Words: 1

Cycles: 1

Example ADDWF FSR, 0

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W= 0xD9

FSR = 0xC2

ANDLW And Literal with W

Syntax: [

label

] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Encoding: 11 1001 kkkk kkkk

Description: The contents of W register are

AND’ed with the eig ht bit literal 'k'.

The result is placed in the W reg-

ister.

Words: 1

Cycles: 1

Example ANDLW 0x5F

Before Instruction

W= 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDW F f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (dest)

Status Affected: Z

Encoding: 00 0101 dfff ffff

Description: AND the W register with register

'f'. If 'd' is 0, the result is stored in

the W r egi ster. If 'd' is 1, the result

is stored back in register 'f'.

Words: 1

Cycles: 1

Example ANDWF FSR, 1

Before Instruction

W = 0x17

FSR = 0xC2

After Instruction

W = 0x17

FSR = 0x02

 1999 Microchip Technology Inc. DS30561B-page 73

PIC12C67X

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affected: None

Encoding: 01 00bb bfff ffff

De scription: Bit ’b’ in register ’f’ is cle ared.

Words: 1

Cycles: 1

Example BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affected: None

Encoding: 01 01bb bfff ffff

De scription: Bit ’b’ in register ’f’ is set.

Words: 1

Cycles: 1

Example BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Encoding: 01 10bb bfff ffff

Description: If bit ’b ’ in register ’f’ is ’0’, then the

next instruction is skipped .

If bit ’b’ is ’0’, then the next instruc-

tion fetched during the current

instruction execution is discarded,

and a NOP is executed instead,

making this a 2 cycle in str ucti on.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSC

GOTO

•

FLAG,1

PROCESS_CO

Before Instruction

PC = address HERE

After Instruction

if FLAG <1> = 0,

PC = address TRUE

if FLAG <1>= 1 ,

PC = address FALSE

PIC12C67X

DS30561B-page 74  1999 Microchip Technology Inc.

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Encoding: 01 11bb bfff ffff

De scription: If bit ’b’ in register ’f’ is ’1’, then the

next instruction is skip ped.

If bit ’b’ is ’1’, then the next instruc-

tion fetched during the current

instruction execution, is discarded

and a NOP is executed ins tea d,

making this a 2 cycle instructi on.

Words: 1

Cycles: 1(2)

Example HERE

FALSE

TRUE

BTFSS

GOTO

•

FLAG,1

PROCESS_CO

Before Instruction

PC = address HERE

After Instruction

if FLA G<1> = 0,

PC = address FALSE

if FLA G<1> = 1,

PC = address TRUE

CALL Call Subroutine

Syntax: [

label

] CALL k

Operands: 0 ≤ k ≤ 2047

Operat ion: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Encoding: 10 0kkk kkkk kkkk

Description: Call Subroutine. First, return

address (PC+1) is pushed onto

the stack. The eleven bit immedi-

ate address is loaded into PC bits

<10:0>. The upper bits of the PC

are loaded from PCLATH. CALL is

a two cycle instruction.

Words: 1

Cycles: 2

Example HERE CALL

THER

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE

TOS = Address HERE+1

CLRF Clear f

Syntax: [

label

] CLRF f

Operands: 0 ≤ f ≤ 127

Operat ion: 00h → (f)

1 → Z

Status Affected: Z

Encoding: 00 0001 1fff ffff

Description: The contents of register ’f’ are

cleared and the Z bit is set.

Words: 1

Cycles: 1

Example CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00

Z=1

CLRW Clear W

Syntax: [

label

] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Encoding: 00 0001 0000 0011

Description: W register is cleared. Zero bit (Z)

is se t.

Words: 1

Cycles: 1

Example CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00

Z=1

 1999 Microchip Technology Inc. DS30561B-page 75

PIC12C67X

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0100

Description: CLRWDT instruction resets the

W atchdog Timer . It also resets th e

prescaler of the WDT. Status bits

TO and PD are set.

Words: 1

Cycles: 1

Example CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00

WDT prescaler= 0

TO =1

PD =1

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1001 dfff ffff

Description: The contents of register ’f’ are

complemented. If ’d’ is 0, the

result is stored in W. If ’ d’ is 1, the

result is stored back in register ’f’.

Words: 1

Cycles: 1

Example COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13

W=0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest)

Status Affected: Z

Encoding: 00 0011 dfff ffff

Description: Decrement register ’f’. If ’d’ is 0,

the result is sto red in the W regis -

ter. If ’d’ is 1, the result is stored

back in r egister ’f’.

Words: 1

Cycles: 1

Example DECF CNT, 1

Before Instruction

CNT = 0x01

Z=0

After Instruction

CNT = 0x00

Z=1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (dest); skip if result = 0

Status Affected: None

Encoding: 00 1011 dfff ffff

Description: The contents of register ’f’ are

decremented. If ’d’ is 0, the result

is placed in the W register. If ’d’ is

1, the result is placed back in reg-

ister ’f’.

If the result is 0, the next instruc-

tion, which is already fetched, is

disc arde d. A NOP is executed

instead making it a two cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1

if CNT = 0,

PC = address CONTINUE

if CNT ≠0,

PC = address HERE+1

PIC12C67X

DS30561B-page 76  1999 Microchip Technology Inc.

GOTO Unconditional Branch

Syntax: [

label

] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Encoding: 10 1kkk kkkk kkkk

Description: GOTO is an unconditional branch.

The eleven bi t imm ed iat e value is

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a two

cycle instruction.

Words: 1

Cycles: 2

Example GOTO THERE

After Instruction

PC = Address THERE

INCF I ncrem ent f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest)

Status Affected: Z

Encoding: 00 1010 dfff ffff

Description: The contents of register ’f’ are

incremented. If ’d’ is 0, the result

is placed in the W register. If ’d’ is

1, the result is placed back in reg-

ister ’f’.

Words: 1

Cycles: 1

Example INCF CNT, 1

Before Instruction

CNT = 0xFF

Z=0

After Instruction

CNT = 0x00

Z=1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (dest), skip if result = 0

Status Affected: None

Encoding: 00 1111 dfff ffff

Description: The contents of register ’f’ are

incremented. If ’d’ is 0, the result

is placed in the W register. If ’d’ is

1, the result is placed back in reg-

ister ’f’.

If the result is 0, the next instruc-

tion, which is already fetched, is

disc arde d. A NOP is executed

instead making it a two cycle

instruction.

Words: 1

Cycles: 1(2)

Example HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1

if CNT= 0,

PC = address CONTINUE

if CNT≠0,

PC = address HERE +1

IORLW Inclusive OR Literal with W

Syntax: [

label

] IORLW k

Operands: 0 ≤ k ≤ 255

Operat ion: (W) .OR. k → (W)

Status Affected: Z

Encoding: 11 1000 kkkk kkkk

Description: The conten ts of the W register a re

OR’ed with the eight bit literal 'k'.

The result is placed in the W reg-

ister.

Words: 1

Cycles: 1

Example IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W= 0xBF

Z=1

 1999 Microchip Technology Inc. DS30561B-page 77

PIC12C67X

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (dest)

Status Affected: Z

Encoding: 00 0100 dfff ffff

Description: Inclusive OR the W register with

placed in the W register. If ’d’ is 1,

the resu lt is pla ce d back in regis-

ter ’f’.

Words: 1

Cycles: 1

Example IORWF RESULT, 0

Before Instruction

RESULT = 0x13

W = 0x91

After Instruction

RESULT = 0x13

W = 0x93

Z=1

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Encoding: 11 00xx kkkk kkkk

Description: The eight bit literal ’k’ is loaded

into W register. The don’t cares

will assemble as 0’s.

Words: 1

Cycles: 1

Example MOVLW 0x5A

After Instruction

W = 0x5A

MO VF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 12 7

d ∈ [0,1]

Operation: (f) → (dest)

Status Affected: Z

Encoding: 00 1000 dfff ffff

Description: The contents of register f are

mov ed to a destin ation depen dant

upon the st atus of d . If d = 0, des-

tination is W register. If d = 1, the

destination is file register f itself.

d = 1 is us eful to test a file registe r

since status flag Z is affected.

Words: 1

Cycles: 1

Example MOVF FSR, 0

After Instruction

W = value in FSR register

Z= 1

MOVWF Mo ve W to f

Syntax: [

label

] MOVWF f

Operands: 0 ≤ f ≤ 12 7

Operat ion: (W) → (f)

Status Affected: None

Encoding: 00 0000 1fff ffff

Description: Move data from W register to reg-

ister 'f'.

Words: 1

Cycles: 1

Example MOVWF OPTION

Before Instruction

OPTION = 0xFF

W = 0x4F

After Instruction

OPTION = 0x4F

W = 0x4F

PIC12C67X

DS30561B-page 78  1999 Microchip Technology Inc.

NOP No Operation

Syntax: [

label

] NOP

Operands: None

Operation: No operation

Status Affected: None

Encoding: 00 0000 0xx0 0000

Description: No operation.

Words: 1

Cycles: 1

Example NOP

OPTION Load Option Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION

Status Affected: None

Encoding: 00 0000 0110 0010

Description: The c ont ents of th e W reg is ter are

loaded in the OPTION register.

This instruction is supported for

code compatibility with PIC16C5X

prod uct s . Si nce O PTION is a re ad-

able/writable register, the user can

directly address it.

Words: 1

Cycles: 1

Example To maintain upward compatibility

with future PIC12C67X products,

do not use this instruction.

RETFIE Return from Interrupt

Syntax: [

label

] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affected: None

Encoding: 00 0000 0000 1001

Description: Return from Interrupt. Stack is

POPed and Top of St ack (T OS) i s

loaded in the PC. Interrupts are

enabled by setting Global Inter-

rupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Words: 1

Cycles: 2

Example RETFIE

After Interrupt

PC = TOS

GIE = 1

RETLW Return with Literal in W

Syntax: [

label

] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affected: None

Encoding: 11 01xx kkkk kkkk

Description: The W register is loaded with the

eight bit literal ’k’. The program

counter is loaded from the top of

the stack (the return address).

This is a two cycle instruct ion.

Words: 1

Cycles: 2

Example

TABLE

CALL TABLE;W contains

table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

 1999 Microchip Technology Inc. DS30561B-page 79

PIC12C67X

RETURN Return from Subroutine

Syntax: [

label

] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Encoding: 00 0000 0000 1000

Description: Return from subroutine. The stac k

is POPed an d th e to p of the sta ck

(TOS) is loaded into the program

counter. This is a two cycle

instruction.

Words: 1

Cycles: 2

Example RETURN

After Interrupt

PC = TOS

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1101 dfff ffff

Description: The contents of register ’f’ are

rotated one bit to the left through

the Carry Flag. If ’ d’ is 0, the re sult

is place d in th e W regi ste r. If ’ d’ is

1, the result is stored back in reg-

ister ’f’.

Words: 1

Cycles: 1

Example RLF REG1,0

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 1100 1100

C=1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Encoding: 00 1100 dfff ffff

Description: The contents of register ’f’ are

rotated on e bit to the right throu gh

the Ca rry Flag. If ’ d’ is 0, the resu lt

is placed in the W register. If ’d’ is

1, the result is placed back in reg-

ister ’f’.

Words: 1

Cycles: 1

Example RRF REG1,

Before Instruction

REG1 = 1110 0110

C=0

After Instruction

REG1 = 1110 0110

W= 0111 0011

C=0

SLEEP

Syntax: [

label

]SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affected: TO, PD

Encoding: 00 0000 0110 0011

Description: The po we r-down s tatus bit, PD is

cleared. Time-out status bit, TO

is set. Watchdog Timer and its

prescaler are cleared.

The proc es so r is p ut into SLEEP

mode w ith the o scillator s topped.

Words: 1

Cycles: 1

Example: SLEEP

PIC12C67X

DS30561B-page 80  1999 Microchip Technology Inc.

SUBLW Subtract W from Literal

Syntax: [

label

]SUBLW k

Operands: 0 ≤ k ≤ 255

Operatio n: k - (W) → (W)

Status

Affected: C, D C, Z

Encoding: 11 110x kkkk kkkk

Description: The W register is subtracted (2’s

complem ent me thod) f rom th e eig ht

bit literal 'k'. The result is placed in

the W reg ister.

Words: 1

Cycles: 1

Example 1: SUBLW 0x02

Before Instruction

W= 1

C=?

After Instruction

W= 1

C = 1; result is positi v e

Example 2: Before Instruction

W= 2

C=?

After Instruction

W= 0

C = 1; result is zero

Example 3: Before Instruction

W= 3

C=?

After Instruction

W= 0xFF

C = 0; result is nega-

tive

SUBWF Subtract W from f

Syntax: [

label

]SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (dest)

Status

Affected: C, D C, Z

Encoding: 00 0010 dfff ffff

Description: Subtract (2’ s complement method) W

result is store d in the W re gister. If 'd'

is 1, the res ult is stored ba ck in regis -

ter 'f'.

Words: 1

Cycles: 1

Example 1: SUBWF REG1,1

Before Inst ruction

REG1 = 3

W=2

C=?

After Instruction

REG1 = 1

W=2

C = 1; result is positive

Example 2: Before Instruction

REG1 = 2

W=2

C=?

After Instruction

REG1 = 0

W=2

C = 1; result is zero

Example 3: Before Instruction

REG1 = 1

W=2

C=?

After Instruction

REG1 = 0xFF

W=2

C = 0; result is negative

 1999 Microchip Technology Inc. DS30561B-page 81

PIC12C67X

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3 :0>)

Status Affected: None

Encoding: 00 1110 dfff ffff

Description: The upper and lower nibbles of

0, the result is placed in W regis-

ter. If ’ d’ is 1, the res ult is pl aced in

Words: 1

Cycles: 1

Example SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5

W = 0x5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f;

Status Affected: None

Encoding: 00 0000 0110 0fff

Description: The instruction is supported for

code compatibility with the

PIC16C5X products. Since TRIS

registers are readable and writ-

able, the user can directly address

them.

Words: 1

Cycles: 1

Example To maintain upward compatibility

with future PIC12C67X products,

do not use this instruction.

XORLW Exclusive OR Literal with W

Syntax: [

label

]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Encoding: 11 1010 kkkk kkkk

Description: The contents of the W register

are XOR’ed with the eight bit lit-

era l 'k'. The resu lt is placed in th e

W register.

Words: 1

Cycles: 1

Example: XORLW 0xAF

Before Instruction

W= 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (dest)

Status Affected: Z

Encoding: 00 0110 dfff ffff

Description: Exclusive OR the contents of the

W register with register 'f'. If 'd' is

0, the result is stored in the W

stor ed back in regis ter 'f'.

Words: 1

Cycles: 1

Example XORWF REG 1

Before Instruction

REG = 0xAF

W=0xB5

After Instruction

REG = 0x1A

W=0xB5

PIC12C67X

DS30561B-page 82  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 83

PIC12C67X

11.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a

full r an ge of hardw are and softw are d e velopment to ols:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASM Assembler

- MPLAB-C17 and MPLAB-C18 C Compilers

- MPLINK/MPLIB Linker/Librarian

• Simulators

- MPLAB-SIM Software Simulator

•Emulators

- MPLAB-ICE Real-Time In-Circuit Emulator

- PICMASTER®/PICMASTER-CE In-Circui t

Emulator

-ICEPIC™

• In-Circuit Debugger

- MPLAB-ICD for PIC16F877

• Device Programmers

-PRO MATE

 II Universal Programmer

- PICSTART Plus Entry-Level Prototype

Programmer

• Low-Cost Demonstration Boards

- SIMICE

- PICDEM-1

- PICDEM-2

- PICDEM-3

- PICDEM-17

- SEEVAL

-KEELOQ

11.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8-bit microcon-

troller market. MPLAB is a Windows-based applica-

tion which contains:

• Multiple functionality

-editor

- simulator

- programmer (sold separately)

- emulator (sold separately)

• A full featured editor

• A project manager

• Customizable tool bar and key mapping

• A status bar

• On-line help

MPLAB allows you to:

• Edit your source files (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all

proje ct information)

• Debug using:

- source files

- absolute listing file

- object code

The ability to use MPLAB with Microchip’s simulator,

MPLAB-SIM, allo ws a c on si ste nt pl atform and the abi l-

ity to easily switch from the cost-effective simulator to

the full featured emulator with minimal retraining.

11.2 MPASM Assembler

MPASM is a ful l feat ured univ ersal mac ro assemb ler f or

all PICmicro MCU’s. It can produce absolute code

directly in the form of HEX files for device program-

mers, or it can generate relocatable objects for

MPLINK.

MPASM has a command line interface and a Windows

shell and c an be u sed a s a stand alone appli catio n o n a

Windows 3.x or greater system. MPASM generates

relocatable object files, Intel standard HEX files, MAP

files to detail memory usage and symbol reference, an

absolute LST file which contains so urce lines an d ge n-

erated machine code, and a COD file for MPLAB

debugging.

MPASM fea ture s includ e:

• MPASM and MPLINK are integrated into MPLAB

projects.

• MPASM allows user defined macros to be created

for streamlined assembly.

• MPASM allows conditional assembly for multi pur-

pose source files.

• MPASM directi ve s allo w comple te control ov er the

assem b l y proces s .

11.3 MPL AB-C17 and MPLAB-C18

C Compilers

The MPLAB-C 17 and MPLAB -C18 Code De v elop ment

Systems are complete ANSI ‘C’ compilers and inte-

grated development environments for Microchip’s

PIC17CXXX and PIC18CXXX family of microcontrol-

lers, respectively. These compilers provide powerful

integration capabilities and ease of use not found with

other co mpi le rs .

For easier source level debugging, the compilers pro-

vide symbol information that is compatible with the

MPLAB IDE memory display.

PIC12C67X

DS30561B-page 84  1999 Microchip Technology Inc.

11.4 MPLINK/MPLIB Linker/Librarian

MPLINK is a relocatable linker for MPASM and

MPLAB-C17 and MPLAB-C18. It can link relocatable

objects from assembly or C source files along with pre-

compiled libraries using directives from a linker script.

MPLIB is a librarian for pre-compiled code to be used

with MPLINK. When a routine from a library is called

from another source file , only the modules that contains

that routine will be linked in with the application. This

allows l arg e li brarie s t o b e use d e ffi ci en tl y i n ma ny di f-

ferent applications. MPLIB manages the creation and

modification of library files.

MPLINK features include:

• MPLINK works with MPASM and MPLAB-C17

and MPLAB-C18.

• MPLINK allows all memory areas to be defined as

sections to provide link-time flexibility.

MPLIB features include:

• MPLIB makes linking easier bec au se singl e li brar-

ies can be included instead of many smaller files.

• MPLIB hel ps k ee p code maintai nab l e b y gr oupin g

related modules together.

• MPLIB commands allow libraries to be created

and modules to be added, listed, replaced,

deleted, or extracted.

11.5 MPLAB-SIM Software Simulator

The MPLAB-SIM Software Simulator allows code

development in a PC host environment by simulating

the PICmicro series microcontrollers on an instruction

level. On any given in struct ion, th e data areas ca n be

examined or modified and stimuli can be applied from

a file or user-defined key press to any of the pins. The

e xecution can be perf ormed in single step , ex ecute until

break, or trace mode.

MPLAB-SIM fully supports symbolic debugging using

MPLAB-C17 and MPLAB-C18 and MPASM. The Soft-

ware Simulator offers the flexibility to develop and

deb ug code outside of the laboratory environment ma k-

ing it an excellent multi-project software development

tool.

11.6 MPLAB-ICE High Performance

Universal In-Circuit Emulator with

MPLAB IDE

The MPLAB-ICE Universal In-Circuit Emulator is

inte nded to provi de t he pr oduc t developm ent en gin eer

with a complete microcontroller design tool set for

PICmicro microcontrollers (MCUs). Software control of

MPLAB-ICE is provided by the MPLAB Integrated

Development Environment (IDE), which allows editing,

“make” and download, and source debugging from a

single environment.

Interchangeable processor modules allow the system

to be easily reconfigured for emulation of different pro-

cessors. The universal architecture of the MPLAB-ICE

allows expansion to support new PICmicro microcon-

trollers.

The MPLAB-ICE Emulator System has been designed

as a real-time emulation system with advanced fea-

tures that are generally found on more expensive devel-

opment tools. The PC platf orm and Microsoft® Windows

3.x/95/98 en vironment were chos en to best make th ese

features available to you, the end user.

MPLAB-ICE 2000 is a full-featured emulator system

with enhanced trace, tr igger, and data monitoring fea-

tures. Both systems use the same processor modules

and will operate across the full operating speed range

of the PICmicro MCU.

11.7 PICMASTER/PICMASTER CE

The PICMASTER system from Microchip Technolog y is

a full-featured, professional quality emulator system.

This flexible in-circuit emulator provides a high-quality,

universal platform for emulating Microchip 8-bit

PICmicro microcontrollers (MCUs). PICMASTER sys-

tems are sold worldwide, with a CE compliant model

available for European Union (EU) countries.

11.8 ICEPIC

ICEPIC is a lo w-cost in-circ uit emula tion solution f o r the

Microchip Technology PIC16C5X, PIC16C6X,

PIC16C7X, and PIC16CXXX fam ilies of 8-bit on e-time-

progr amma b le (OTP) microcontrollers. The modula r

system can suppo rt different subsets of PIC16C5X or

PIC16CXXX products through the use of

interchangeab le persona lity modules or daughter

boards. The em ulator is capable of emulating without

target application circuitry being present.

11.9 MPLAB-ICD In-Circuit Debugger

Microc hip’s In-C ircuit Deb ugger , MPLAB-ICD, is a pow-

erful, low-cost run-time development tool. This tool is

based on the flash PIC16F877 and can be used to

develop for this and other PICmicro microcontrollers

from the PIC16CXXX family. MPLAB-ICD utilizes the

In-Circuit Debugging capability built into the

PIC16F8 7X. This f eature, alon g with Microchip’ s In-C ir-

cuit Serial Programming protocol, offers cost-effective

in-circuit flash programming and debugging from the

graphical user interface of the MPLAB Integrated

Development Environment. This enables a designer to

de velop and deb ug so urce c ode b y w atchi ng v aria bl es ,

single-stepping and setting break points. Running at

full speed enables testing hardware in real-time. The

MPLAB-ICD is also a programmer for the flash

PIC16F87X family.

 1999 Microchip Technology Inc. DS30561B-page 85

PIC12C67X

11.10 PRO MATE II Universal Programmer

The PRO MATE II Universal Programmer is a full-fea-

ture d programme r capable of operati ng in stand -alo ne

mode as well as PC-hosted mode. PRO MATE II is CE

compliant.

The PRO MATE II has programmable VDD and VPP

supplies which allows it to verify programmed memory

at VDD min and VDD max for maximum reliability. It has

an LCD display for instructions and error messages,

keys to enter commands and a modular detachable

socket assembly to support various package types. In

stand-al on e m ode the PRO MATE II can read, verify or

program PICmicro devices. It can also set code-protect

bits in this mode.

11.11 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, low-

cost prototype programmer. It connects to the PC via

one of the COM (RS-232) ports. MPLAB Integrated

Development Environment software makes using the

programmer simple and efficient.

PICSTART Plus supp o rts a ll P ICmi cr o device s wit h up

to 40 pins. Larger pin count devices such as the

PIC16C92X, and PIC17C76X may be supported with

an adapter socket. PICSTART Plus is CE compliant.

11.12 SIMICE Entry-Level

Hardware Simulator

SIMICE is an entry-level hardware development sys-

tem designed to operate in a PC-based environment

with Microchip’s simulator MPLAB-SIM. Both SIMICE

and MPLAB-SIM run under Microchip Technology’s

MPLAB Integrated Development Environment (IDE)

software. Specifically, SIMICE provides hardware sim-

ulation for Microchip’s PIC1 2C5XX, PIC 12CE5 XX, an d

PIC16C5X families of PICmicro 8-bit microcontrollers.

SIMICE works in conjunction with MPLAB-SIM to pro-

vide non- real-time I/O port emulation. SIMICE enables

a developer to run simulator code for driving the target

system . In addition, the target system can provi de input

to the simulator code. This capability allows for simple

and interactive debugging without having to manually

generate MPLAB-SIM stimulus files. SIMICE is a valu-

able debugging tool for entry-level system develop-

ment.

11.13 PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates

the capabilities of several of Microchip’s microcontrol-

lers. The microcontrollers supported are: PIC16C5X

(PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X,

PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and

PIC17C44. All necessary hardware and software is

included to run basic demo programs. The users can

program the sample microcontrollers provided with

the PICDEM-1 board, on a PRO MATE II or

PICSTART-Plus programmer, and easily test firm-

ware. The user can also connect the PICDEM-1

board to the MPLAB-ICE emulator and downl o a d t h e

firmware to the emulator for testing. Additional proto-

type area is available for the user to build some addi-

tional hardware and connect it to the microcontroller

socket(s). Some of the features include an RS-232

interface, a potentiometer for simulated analog input,

push-button switches and eight LEDs connected to

PORTB.

11.14 PICDEM-2 Low-Cost PIC16CXX

Demonstration Board

The PICDEM-2 is a simple demonstration board that

supports the PIC16C62, PIC16C64, PIC16C65,

PIC16C73 and PIC16C74 microcontrollers. All the

necessary hardware and software is included to

run the basic demonstration programs. The user

can program the sample microcontrollers provided

with the PICDEM-2 board, on a PRO MATE II pro-

grammer or PICSTAR T- Plus , an d easil y test firmware .

The MPLAB-ICE emulator may also be used with the

PICDEM-2 board to test firmware. Additional prototype

area has been provided to the user for adding addi-

tional ha rdware and connectin g it to the mic rocontroll er

soc ket (s). Some of the f eatures include a RS-232 int er-

face, push-button switches, a potentiometer for simu-

lated analog input, a Serial EEPROM to demonstrate

usage of th e I2C bu s and separ ate hea ders f or connec -

tion to an LCD module and a keypad.

11.15 PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that

supports the PIC16C923 and PIC16C924 in the PLCC

package. It will also support future 44-pin PLCC

microc ont roll ers wi th a LCD Mo dul e . All the ne ces -

sary hardware and software is included to run the

basic demonstration programs. The user can pro-

gram the sample microcontrollers provided with

the PICDE M- 3 boar d, on a PRO MAT E II pr ogram-

mer or PICSTART Plus with an adapter socket, and

easily test firmware. The MPLAB-ICE emulator may

also be used with the PICDEM-3 board to test firm-

ware. Additional protot ype a rea h as bee n provided to

the us er for adding ha rdware and con necti ng it to the

microcontroller sock et(s). Some of the f eatures inc lude

an RS-232 interface, push-button switches, a potenti-

ometer for simulated analog input, a thermistor and

separate headers for connection to an external LCD

module and a k e y pad. Als o pro vide d on th e PICDEM -3

board is an LCD panel, with 4 commons and 12 seg-

ments, that is capable of displaying time, temperature

and day of the week . Th e PICDEM-3 pro vi de s a n add i-

tional RS-232 interface and Windows 3.1 software for

showing the demultiplex ed LCD signals on a PC . A sim-

ple serial interface allows the user to construct a hard-

ware demultiplexer for the LCD signals.

PIC12C67X

DS30561B-page 86  1999 Microchip Technology Inc.

11.16 PICDEM-17

The PICDEM-17 is an evaluation board that demon-

strates the capabilities of several Microchip microcon-

trollers, including PIC17C752, PIC17C756,

PIC17C762, and PIC17C766. All necessary hardware

is incl uded to run bas ic demo prog rams, which are su p-

plied on a 3.5-inch disk. A programmed sample is

includ ed, and the us er ma y eras e it an d prog ram it wi th

the other sample programs using the PRO MATE II or

PICSTART Plus device programmers and easily debug

and test the sample code . In additio n, PICDEM-17 su p-

ports down-loa ding of progr ams to and e xec uting out of

e xt ernal FLASH memory on board. The PICD EM -17 i s

also usab le with th e MPL AB-ICE or PI CMASTER em u-

lator, and all of the sample programs can be run and

modified using either emulator. Additionally, a gener-

ous prototype area is available for user hardware.

11.17 SEEV AL Evaluation and Programming

System

The SEEVAL SEEPROM Designer’s Kit supports all

Microchip 2-wire and 3-wire Serial EEPROMs. The kit

includes everything necessary to read, write, erase or

program special features of any Microchip SEEPROM

product including Smart Serials and secure serials.

The Total Endurance Disk is included to aid in trade-

off analy sis a nd relia bility calc ulatio ns . The tota l kit ca n

significantly reduce time-to-market and result in an

optimized system.

11.18 KEELOQ Evaluation and

Programming Tools

KEELOQ evaluation and programming tools support

Microc hips HCS Secure D ata Product s. The HC S ev al-

uation kit includes an LCD display to show changing

codes, a decoder to decode transmissions, and a pro-

gramming interface to program test transmitters.

 1999 Microchip Technology Inc. DS30561B-page 87

PIC12C67X

TABLE 11-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12CXXX

PIC14000

PIC16C5X

PIC16C6X

PIC16CXXX

PIC16F62X

PIC16C7X

PIC16C7XX

PIC16C8X

PIC16F8XX

PIC16C9XX

PIC17C4X

PIC17C7XX

PIC18CXX2

24CXX/

25CXX/

93CXX

HCSXXX

MCRFXXX

MCP2510

Software Tools

MPLAB® Integrated

Development Environment

MPLAB® C17 Compiler

MPLAB® C18 Compiler

MPASM/MPLINK

Emulators

MPLAB®-ICE

PICMASTER/PICMASTER-CE

ICEPIC Low-Cost

In-Circuit E mulator

Debugger

MPLAB®-ICD In-Circuit

Debugger

Programmers

PICSTARTPlus

Low-Cost Universal Dev. Kit

PRO MATE II

Universal Programmer

Demo Boards and Eval Kits

SIMICE

PICDEM-1

†

PICDEM-2

†

PICDEM-3

PICDEM-14A

PICDEM-17

KEELOQ® Evaluation Kit

KEELOQ Transponder Kit

microID™ Programmer’s Kit

125 kHz microID Developer’s Kit

125 kHz Anticollision microID

Developer’s Kit

13.56 MHz Anticollision microID

Developer’s Kit

MCP2510 CAN Developer’s Kit

* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB®-ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77

** Contact Microchip Technology Inc. for availability date.

†Development tool is available on select devices.

PIC12C67X

DS30561B-page 88  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 89

PIC12C67X

12.0 ELECTRICAL SPECIFICATIONS FO R PIC12C67X

Absolute Maximum Ratings †

Ambient temperature under bias...............................................................................................................–40° to +125°C

Storage temperature............................................................................................................................. –65°C to +150°C

Voltage on any pin with respect to VSS (except VDD and MCLR)................................................... –0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ................................................................................................................ 0 to +7.0V

Voltage on MCLR with respect to VSS (Note 2)..................................................................................................0 to +14V

Total power dissipation (Note 1)...........................................................................................................................700 mW

Maximum current out of VSS pin...........................................................................................................................200 mA

Maximum current i nto VDD pin..............................................................................................................................150 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp current, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximu m out put current sunk by any I/O pin................. ..... ...... ................. ..... ................. ...... ............ .....................25 mA

Maximu m out put current sourc ed b y an y I/O pin ..... ...... ................. ..... ................. ...... ................ ............................25 mA

Maximum current sunk by GPIO pins combined...................................................................................................100 mA

Maximum current sourced by GPIO pins combined..............................................................................................100 mA

Note 1: Powe r dissi pati on is calc ul ate d as follows: Pdi s = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

de vic e. Th is is a s tress r ating o nly and functional oper atio n of the device at thos e or an y other c onditi ons abo v e those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC12C67X

DS30561B-page 90  1999 Microchip Technology Inc.

FIGURE 12-1: PIC12C67X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C <TA ≤ +125°C

FIGURE 12-2: PIC12C67X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz )

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section fo r the maximum rated speed of the parts.

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz )

VDD

(Volts)

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

 1999 Microchip Technology Inc. DS30561B-page 91

PIC12C67X

FIGURE 12-3: PIC12LC67X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C

6.0

2.5

4.0

3.0

3.5

4.5

5.0

5.5

410

Frequency (MHz )

VDD

(Volts)

2.0

Note 1: The shaded region indicates the permissible combinations of voltage and frequency.

2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.

Please reference the Product Identification System section for the maximum rated speed of the parts.

PIC12C67X

DS30561B-page 92  1999 Microchip Technology Inc.

12.1 DC Characteristics: PIC12C671/672 (Commercial, Industrial, Extended)

PIC12CE673/674 (Commercial, Industrial, Extended)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Oper ati ng Tem per a t ure 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Parm

No. Characteristic Sym Min Typ(1) Max Units Conditions

D001 Supply Voltage VDD 3.0 5.5 V

D002 RAM Data Retention

Voltage(2) VDR 1.5* V Device in SLEEP mode

D003 VDD Start Voltage to ensure

Pow e r - on Rese t VPOR VSS V See section on Power-on Reset for details

D004 VDD Rise Rate to ensure

Pow e r - on Rese t SVDD 0.05* V/ms See section on Power-on Reset for details

D010

D010C

D010A

Supply Current(3) IDD —

—

1.2

2.2

2.5

µA

FOSC = 4MHz, VDD = 3.0V

XT and EXTRC mode (Note 4)

FOSC = 4MHz, VDD = 3.0V

INTRC mode (Note 6)

FOSC = 10MHz, VDD = 5.5V

HS mode

FOSC = 32kHz, VDD = 3.0V, WDT disabled

LP mode, Commercial Temperature

FOSC = 32kHz, VDD = 3.0V, WDT disabled

LP mode, Industrial Temperature

FOSC = 32kHz, VDD = 3.0V, WDT disabled

LP mode, Extended Temperature

D020

D021

D021B

Power-down Current(5) IPD —

—

0.25

0.5

0.8

µA

VDD = 3.0V, Commer ci al, WDT dis abled

VDD = 3.0V, Industrial, WDT disabled

VDD = 3.0V, Extended, WDT disabled

VDD = 5.5V, Commercial, WDT disabl ed

VDD = 5.5V, Industrial, WDT disabled

VDD = 5.5V, Extended, WDT disabled

D022 Watchdog Timer Current ∆IWDT —

—

2.2

µA

VDD = 3.0V, Commercial

VDD = 3.0V, Industrial

VDD = 3.0V, Extended

D028 Supply Current(3)

During read/write to

EEPROM peripheral

∆IEE —0.10.2mAFOSC = 4MHz, VDD = 5.5V, SCL = 400kHz

For PIC12CE673/ 674 only

* These parameters are characterized but not tested.

Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is fo r design guidance only and is not

tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as bus loading, oscillator

type, b us rate, internal code execution pattern and temperature also hav e an impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0C K I = V DD,

MCLR = VDD; WDT disabled.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.

4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the

formula:

Ir = VDD/2REXT (mA) with REXT in kOhm.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the

part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.

 1999 Microchip Technology Inc. DS30561B-page 93

PIC12C67X

LP Oscillator Operating

Frequency

INTRC/EXTRC Oscillator

Operating Freque nc y

XT Oscillator Operating

Frequency

HS Oscillator Operating

Frequency

FOSC 0

—

200

4(6)

kHz

MHz

All temperatures

* These parameters are characterized but not tested.

Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is fo r design guidance only and is not

tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as bus loading, oscillator

type, bus rate, inter nal code execution pattern, and temperature also have an impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0C K I = V DD,

MCLR = VDD; WDT disabled.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.

4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the

formula:

Ir = VDD/2REXT (mA) with REXT in kOhm.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the

part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Parm

No. Characteristic Sym Min Typ(1) Max Units Conditions

PIC12C67X

DS30561B-page 94  1999 Microchip Technology Inc.

12.2 DC Characteristics: PIC12LC671/672 (Commercial, Industrial)

PIC12LCE673/674 (Commercial, Industrial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise specified)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

Param

No. Characteristic Sym Min Typ† Max Units Conditions

D001 Supply Voltage VDD 2.5 5.5 V

D002 RAM Data Retention

Voltage(2) VDR 1.5* V Device in SLEEP mode

D003 VDD Start Voltage to

ensure Power-on Reset VPOR VSS V See section on Power-on Reset for details

D004 VDD Rise Rate to ensure

Power- on Reset SVDD 0.05* V/ms See section on Power-on Reset for details

D010

D010C

D010A

Supply Current(3) IDD —

—

0.4

2.1

µA

FOSC = 4MHz, VDD = 2.5V

XT and EXTRC mode (Note 4)

FOSC = 4MHz, VDD = 2.5V

INTRC mo de (Note 6)

FOSC = 32kHz, VDD = 2.5V, WDT disabled

LP mode, Industrial Temperature

D020

D021

D021B

Power-down Current(5) IPD —

—0.2

0.2 5

6µA

µAVDD = 2.5V, Commercial

VDD = 2.5V, Industrial

Watchdog Timer Current ∆IWDT —2.0

2.0 4

6µA

µAVDD = 2.5V, Commercial

VDD = 2.5V, Industrial

LP Oscillator Operating

Frequency

INTRC/EXTRC Oscillator

Operating Freque nc y

XT Oscillator Operating

Frequency

HS Oscillator Operating

Frequency

FOSC 0

—

200

4(6)

kHz

MHz

All temperatures

* These parameters are characterized but not tested.

Note 1: Data in Typical ("Typ") column is based on characterization results at 25°C. This data is fo r design guidance only and is not

tested.

2: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating v oltage and frequency. Other factors such as bus loading, oscillator

type, bus rate, inter nal code execution pattern, and temperature also have an impact on the current consumption.

a) The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to VSS, T0C K I = V DD,

MCLR = VDD; WDT disabled.

b) For standby current measurements, the conditions are the same, except that the device is in SLEEP mode.

4: For EXTRC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the

formula:

Ir = VDD/2REXT (mA) with REXT in kO h m.

5: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the

part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.

6: INTRC calibration value is for 4MHz nominal at 5V, 25°C.

 1999 Microchip Technology Inc. DS30561B-page 95

PIC12C67X

12.3 DC CHARACTERISTICS: PIC12C671/672 (Commercial, Industrial, Extended)

PIC12CE673/674 (Commer cial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating voltage VDD range as des cribed in DC spe c Sect ion 12.1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ† Max Units Conditions

Input Low Voltage

I/O ports VIL

D030 with TTL buffer VSS —0.8V V F or 4.5V ≤ VDD ≤ 5.5V

VSS —0.15VDD V otherwise

D031 with Schmitt Trigger buffe r VSS —0.2VDD V

D032 MCLR, GP2/T0CKI/AN2/INT

(in EXTRC mode) VSS —0.2VDD V

D033 OSC1 (in EXTRC mode) VSS —0.2VDD Note 1

D033 OSC1 (in XT, HS, and LP) VSS —0.3VDD V Note 1

Input High Voltage

I/O ports VIH —

D040 with TTL buffer 2.0V —VDD V4.5V ≤ VDD ≤ 5.5V

D040A 0.25VDD + 0. 8V —VDD V otherwise

D041 with Schmitt Trigger buffe r 0.8VDD —VDD VFor entire VDD ran g e

D042 MCLR, GP2/T0CKI/AN2/INT 0.8VDD —VDD V

D042 A O SC1 ( X T, HS, and LP) 0.7VDD —VDD V Note 1

D043 OSC1 (in EXTRC mode) 0.9VDD —VDD V

Input Leakage Current (Notes 2, 3)

D060 I/O port s IIL ——

+1 µAVSS ≤ VPIN ≤ VDD, Pin at

hi-impedance

D061 GP3/MCLR (Not e 5) +30 µAVSS ≤ VPIN ≤ VDD

D061 A G P3 ( N ot e 6) +5µAVSS ≤ VPIN ≤ VDD

D062 GP2/T0CKI ——

+5 µAV

SS ≤ VPIN ≤ VDD

D063 OSC1 ——

+5 µAVSS ≤ VPIN ≤ VDD, XT, HS, and

LP osc conf ig urati on

D070 GPIO wea k pu ll- up current (N ot e 4) IPUR 50 250 400 µAVDD = 5V, VPIN = VSS

MCLR pull-up current ———

30 µAVDD = 5V, VPIN = VSS

Output Low Voltage

D080 I/O port s VOL ——

0.6 V IOL = 8.5 mA, VDD = 4.5V,

–40°C to +85°C

D080A ——

0.6 V IOL = 7.0 mA, VDD = 4.5V,

–40°C to +125°C

D083 OSC2/CLKOUT — — 0.6 V IOL = 1.6 mA, V DD = 4.5V,

–40°C to +85°C

D083A — — 0.6 V IOL = 1.2 mA, VDD = 4.5V,

–40°C to +125°C

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X

be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

norm al operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

4: Does not include GP3. For GP3 see parameters D061 and D061A.

5: This spec. applies to GP3/MCLR configured as exter nal MCLR and GP3/MCLR configured as input with internal pull-up

enabled.

6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit

is higher than the standard I/O logic.

PIC12C67X

DS30561B-page 96  1999 Microchip Technology Inc.

Output High Voltage

D090 I/O port s (Note 3) VOH VDD - 0.7 —— VIOH = -3.0 mA, VDD = 4.5V,

–40°C to +85°C

D090A VDD - 0.7 —— VIOH = -2.5 mA, VDD = 4.5V,

–40°C to +125°C

D092 OSC2/CLKOUT VDD - 0.7 — — V IOH = 1.3 mA, VDD = 4. 5V,

–40°C to +85°C

D092A VDD - 0.7 — — V IOH = 1.0 mA, VDD = 4.5V,

–40°C to +125°C

Capacitive Loadin g Spe cs on

Output Pins

D100 OSC2 pin COSC2——

15 pF In XT and LP modes when

external clock is used to drive

OSC1.

D101 All I/O pins CIO ——

50 pF

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating temperature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (industrial)

–40°C ≤ TA ≤ +125°C (extended)

Operating voltage VDD range as des cribed in DC spe c Sect ion 12.1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ† Max Units Conditions

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X

be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent

norm al operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

4: Does not include GP3. For GP3 see parameters D061 and D061A.

5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up

enabled.

6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit

is higher than the standard I/O logic.

 1999 Microchip Technology Inc. DS30561B-page 97

PIC12C67X

12.4 DC CHARACTERISTICS: PIC12LC671/672 (Commercial, Industrial)

PIC12LCE673/674 (Commercial, Industrial)

DC CHARACTERISTICS

Standard Opera ting Conditio ns (u nl ess otherwise specified)

Operating t em perature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (indust rial)

Operating voltage VDD rang e as described in DC spec Sect i on 1 2. 1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ† Max Units Conditions

Input Low Voltage

I/O ports VIL

D030 with TTL buffer VSS — 0.8V V For 4.5V ≤ VDD ≤ 5.5V

VSS —0.15VDD Votherwise

D031 with Schmitt Trigger buffer VSS —0.2VDD V

D032 MCLR, GP2/T0CKI/AN2/INT

(in EXTRC mode) VSS —0.2VDD V

D033 OS C1 (in EXTRC mode) VSS —0.2VDD V N ote 1

D033 OSC1 (in XT, HS, and LP) VSS —0.3VDD V N ote 1

Input High Voltage

I/O ports VIH —

D040 with TTL buffer 2.0V — VDD V4.5V ≤ VDD ≤ 5.5V

D040A 0.25VDD + 0. 8V — VDD Votherwise

D041 wit h Schmitt Tr i gger buffer 0.8VDD —VDD VFor entire VDD range

D042 MCLR, GP2/T0CKI/AN2/INT 0.8VDD —VDD V

D042 A OSC1 (XT, HS, and LP) 0.7VDD —VDD V Note 1

D043 OS C1 (in EXTRC mode) 0.9VDD —VDD V

Input Leakage Current (Notes 2, 3)

D060 I/O ports IIL ——+1µAVss ≤ VPIN ≤ VDD, Pin at

hi-impedance

D061 GP3/MCLR (N ot e 5) +30 µAVss ≤ VPIN ≤ VDD

D061 A GP3 (Note 6) +5µAVss ≤ VPIN ≤ VDD

D062 GP2/T0CKI — — +5µAVss ≤ VPIN ≤ VDD

D063 OSC1 — — +5µAVss ≤ VPIN ≤ VDD, XT, HS and

LP osc confi gurati on

D070 GPIO w eak pul l -u p cur r ent (Note 4) IPUR 50 250 400 µAVDD = 5V, VPIN = VSS

MCLR pull-up current — — — 30 µAVDD = 5V, VPIN = VSS

Output Low Vo ltage

D080 I/O ports VOL ——0.6VIOL = 8.5 mA, VDD = 4. 5V,

–40°C to +85°C

D080A — — 0.6 V IOL = 7.0 mA, VDD = 4.5V,

–40°C to +125°C

D083 OSC2/CLKOUT — — 0.6 V IOL = TBD, VDD = 4.5V,

–40°C to +85°C

D083A — — 0.6 V IOL = TBD, VDD = 4.5V,

–40°C to +125°C

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X

be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent nor-

mal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

4: Does not include GP3. For GP3 see parameters D061 and D061A.

5: This spec. applies to GP3/MCLR configured as exter nal MCLR and GP3/MCLR configured as input with internal pull-up

enabled.

6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is

higher than the standard I/O logic.

PIC12C67X

DS30561B-page 98  1999 Microchip Technology Inc.

Output High Voltage

D090 I/O ports (Note 3) VOH VDD - 0.7 —— VIOH = -3.0 mA, VDD = 4.5V,

–40°C to +85°C

D090A VDD - 0.7 — — V IOH = -2.5 mA, VDD = 4.5V,

–40°C to +125°C

D092 OSC2/CLKOUT VDD - 0.7 — — V IOH = TBD, VDD = 4.5V,

–40°C to +85°C

D092A VDD - 0.7 — — V IOH = TBD, VDD = 4.5V,

–40°C to +125°C

Capacitive Loading Specs on

Output Pins

D100 OS C2 pin COSC2 — — 15 pF In XT an d LP modes when

external clock is used to drive

OSC1.

D101 All I/O pins CIO — — 50 pF

DC CHARACTERISTICS

Standard Operating Conditio ns (u nl ess oth er w is e spe ci f ied)

Operating t em perature 0°C ≤ TA ≤ +70°C (commercial)

–40°C ≤ TA ≤ +85°C (indu strial)

Operating voltage VDD rang e as described in DC spec Sect i on 1 2. 1 and

Section 12.2.

Param

No. Characteristic Sym Min Typ† Max Units Conditions

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: In EXTRC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC12C67X

be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent nor-

mal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is defined as coming out of the pin.

4: Does not include GP3. For GP3 see parameters D061 and D061A.

5: This spec. applies to GP3/MCLR configured as external MCLR and GP3/MCLR configured as input with internal pull-up

enabled.

6: This spec. applies when GP3/MCLR is configured as an input with pull-up disabled. The leakage current of the MCLR circuit is

higher than the standard I/O logic.

 1999 Microchip Technology Inc. DS30561B-page 99

PIC12C67X

12.5 Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

FIGURE 12-4: LOAD CONDITIONS

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

TFFrequency TTime

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercas e letters and t heir meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

I2C only

AA output access Hi gh High

BUF Bus free Low Low

TCC:ST (I2C specifications only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition

STA START condition

VDD/2

Pin Pin

VSS VSS

RL=464Ω

CL= 50 pF for all pins except OSC2

15 pF for OSC2 output

Load cond i tion 1 Load condition 2

PIC12C67X

DS30561B-page 100  1999 Microchip Technology Inc.

12.6 Timing Diagrams and Specifications

FIGURE 12-5: EXTERNAL CLOCK TIMING

TABLE 12-1: CLOCK TIMING REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

FOSC External CLKIN Frequency

(Note 1) DC — 4 MHz XT and EXTRC osc mode

DC — 4 M H z HS osc mode (PIC12C E67X-04)

DC — 10 MHz HS osc mode (PIC 12CE67X- 10)

DC — 2 00 kHz LP osc mod e

Oscillator Frequenc y

(Note 1) DC — 4 MHz EXTRC osc mode

.455 — 4 MHz XT osc mode

4 — 4 MHz HS osc mode (PIC12C E67X-04 )

4 — 10 MHz HS osc mode (PIC 12CE67X- 10)

5 — 200 kHz LP osc mod e

OSC External CLKIN Period

(Note 1) 250 — — ns XT and EXTRC osc mode

250 — — ns HS osc m ode (PIC12C E67X-04)

100 — — ns HS osc m ode (PIC12C E67X-10)

5— — µs LP osc mod e

Oscillator Period

(Note 1) 250 — — ns EXTRC osc mode

250 — 10, 000 ns XT osc mode

250 — 250 ns HS osc m ode (PIC12C E67X-04)

100 — 250 ns HS osc m ode (PIC12C E67X-10)

5— — µsLP osc mode

CY Instruction Cycle Time (Note 1) 400 — DC ns TCY = 4/ FOSC

3 TosL,

TosH External Clock in (OSC1) High

or Low Time 50 — — ns XT oscillator

2.5 — — µs LP oscillator

10 — — n s HS oscillator

4TosR,

TosF External Clock in (OSC1) Rise

or Fall Time — — 25 ns XT oscillator

— — 50 ns LP oscillator

— — 15 ns HS osc i llator

† Data in "Typ" column is at 5V, 25°C unless ot her w ise stated. These paramet ers are for design guid ance only and

are not test e d .

Note 1: Instruction cycle period (TCY) equals four times the inpu t osc illa to r time-base period. All specif ied values are ba sed

on characterizat i on dat a for that pa rt ic ular oscillator type under standard operating conditions w i t h th e device exe-

cuting code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than

expected current consum pt i on. Al l devices ar e test ed to operate at "min. " values with an external clock applied to

the OSC1 /CLKIN pin.

When an external clock inpu t is us ed, t he "M ax." cycle tim e l imit is "D C " (n o cl ock) for all devices. OSC2 is discon-

nected (has no loadi ng) for the PIC12C 67X.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

23344

 1999 Microchip Technology Inc. DS30561B-page 101

PIC12C67X

TABLE 12-2: CALIBRATED INTERNAL RC FREQUENCIES -PIC12C671, PIC12C672, PIC12CE673,

PIC12CE674, PIC12LC671,

PIC12LC6 72, PIC1 2LCE 673 ,

PIC12LCE674

AC Characteristics Standard Operating Conditions (unless otherwise specified)

Operating Temperature 0°C ≤ TA ≤ +70°C (commercial),

–40°C ≤ TA ≤ +85°C (industrial),

–40°C ≤ TA ≤ +125°C (extended)

Operating Voltage VDD range is described in Section 10.1

Parameter

No. Sym Characteristic Min* Typ(1) Max* Units Conditions

Internal Calibrated RC Frequency 3.65 4.00 4.28 MHz VDD = 5. 0V

Internal Calibrated RC Frequency 3.55 4.00 4.31 MHz VDD = 2. 5V

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

PIC12C67X

DS30561B-page 102  1999 Microchip Technology Inc.

FIGURE 12-6: CLKOUT AND I/O TIMING

TABLE 12-3: CLKOUT AND I/O TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOU T↓ — 75 200 ns Note 1

11* TosH2ckH OSC1↑ to CLKOU T↑ — 75 200 ns Note 1

12* TckR CLKOUT rise time — 35 100 ns No te 1

13* TckF CLKOUT fall time — 35 100 ns Note 1

14* Tc kL 2ioV CLKOUT ↓ to Po rt out va lid — — 0.5TCY + 20 ns Note 1

15* TioV2ckH Port in val id before CLKOUT ↑ TOSC + 200 — — ns Note 1

16* TckH2ioI Port in hold after CLKOUT ↑ 0——nsNote 1

17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns

18* TosH2ioI OSC1↑ (Q2 cycle) to Port

input invalid (I/O in hold

time)

PIC12C67X 100 — — ns

18A* PIC12LC67X 200 — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup

time) 0——ns

20* TioR Port output rise time PIC12C67X — 10 40 ns

20A* PIC12LC67X — — 80 ns

21* TioF Por t output fall time PIC12C67X — 10 40 ns

21A* PIC12LC67X — — 80 ns

22††* Tinp GP2/INT pin high or low time TCY ——ns

23††* Trbp GP0/GP1/GP3 change INT high or low

time TCY ——ns

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

†† These parameters are asynchrono us events not related to any internal clock edge.

Note 1: Measurements are taken in EXTRC and INTRC modes where CLKOUT output is 4 x TOSC.

Note: Refer to Figure 12-4 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

12 16

old value new v alue

 1999 Microchip Technology Inc. DS30561B-page 103

PIC12C67X

FIGURE 12-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP

TIMER TIMING

TABLE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 ——µsVDD = 5V, –40°C to +125°C

31* Twdt Watchdog Timer Time-out Period

(No Pres cal e r) 71833msVDD = 5V, –40°C to +125°C

32 Tost Os ci lla tio n St art-up Timer Period — 1024TOSC ——TOSC = OSC1 period

33* Tpwrt Power up Timer Period 28 72 132 ms VDD = 5V, –40°C to +125°C

34 TIOZ I/O Hi-impedance from MCLR

Low or Watchd og Ti m er Reset ——2.1µs

* These parameters are characterized but not tested.

† D at a i n "Typ" column is at 5V, 25°C unless ot her w i se sta te d. These parameters are for design gu id anc e only and

are not test e d .

VDD

MCLR

Internal

POR

PWRT

Timeout

OSC

Timeout

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

PIC12C67X

DS30561B-page 104  1999 Microchip Technology Inc.

FIGURE 12-8: TIMER0 CLOCK TIMINGS

TABLE 12-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

TABLE 12-6: GPIO PULL-UP RESISTOR RANGES

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI H igh Pulse Widt h No Pre scaler 0.5TCY + 20 — — ns Must also me et

parameter 42

With Prescaler 10 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet

parameter 42

With Prescaler 10 — — ns

42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns

With Prescaler Greater of:

20 or TCY + 40

— — ns N = prescale

value (2, 4,...,

256)

48 TCKE2tmr1 D elay from external clock edge to timer

increment 2TOSC —7Tos

c—

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless ot her w i se sta te d. These parameters are for design gu id anc e only and are

not tested .

VDD (Vo l ts) Temperature (°C) Min Typ Max Units

GP0/GP1

2.5 –40 38K 42K 63K Ω

25 42K 48K 63K Ω

85 42K 49K 63K Ω

125 50K 55K 63K Ω

5.5 –40 15K 17K 20K Ω

25 18K 20K 23K Ω

85 19K 22K 25K Ω

125 22K 24K 28K Ω

GP3

2.5 –40 285K 346K 417K Ω

25 343K 414K 532K Ω

85 368K 457K 532K Ω

125 431K 504K 593K Ω

5.5 –40 247K 292K 360K Ω

25 288K 341K 437K Ω

85 306K 371K 448K Ω

125 351K 407K 500K Ω

* These parameters are characterized but not tested.

Note: Refer to Figure 12-4 for load conditions.

GP2/T0CKI

TMR0

 1999 Microchip Technology Inc. DS30561B-page 105

PIC12C67X

TABLE 12-7: A/D CONVERTER CHARACTERISTICS:

PIC12C671/672-04/PIC12CE673/674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC12C671/672-10/PIC12CE673/674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED)

PIC12LC671/672-04/PIC12LCE673/674-04 (COMMERCIAL, INDUSTRIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResolution — — 8-bits bit VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A02 EABS Total absolute error — — < ±1LSbVREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A03 EIL Integral l in earity er ro r — — < ±1LSb

VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A04 EDL Differential linearity error — — < ±1LSb

VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A05 EFS Full scal e error — — < ±1LSb

VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A06 EOFF Offset error — — < ±1LSb

VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A10 — Monotonicity — guarante ed

(Note 3) ——

VSS ≤ VAIN ≤ VREF

A20 VREF Reference voltage 2.5V — VDD + 0.3 V

A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V

A30 ZAIN Recommended impedance of

analo g voltage source ——10.0kΩ

A40 IAD A/D c onversion

current (V DD)PIC12C67X — 180 — µA Average current con-

sumpti on w he n A/ D is on.

(Note 1)

PIC12LC67X — 90 — µA

A50 IREF VREF input current (N ot e 2) 10

—

1000

µA

During VAIN acqui si t ion.

Based on differential of

VHOLD to VAIN to charge

CHOLD, see Section 8.1.

During A/D Conversion

cycle

* These parameters are characterized but not tested.

† Data in “Ty p” col um n is at 5V, 25°C un le ss otherwi se s ta te d. These paramet er s ar e for desig n gui dance on ly and

are not test e d .

Note 1: When A/D is off, it will not consume any curr ent ot her than minor leakage current. The power-down current spec

includes any such leakage from th e A/ D mo dule.

2: VREF curren t is f ro m GP 1 pi n or VDD pin, whichever is selected as reference input.

3: The A/D conversion res ul t never decreases w ith an in cr ease in the Input Voltage, and has no miss in g codes.

PIC12C67X

DS30561B-page 106  1999 Microchip Technology Inc.

FIGURE 12-9: A/D CONVERSION TIMING

TABLE 12-8: A/D CONVERSION REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period PIC12C67X 1.6 ——µsTOSC based, VREF ≥ 3.0V

PIC12LC67X 2.0 — — µsT

OSC based, V REF full range

PIC12C67X 2.0 4.0 6.0 µsA/D RC Mode

PIC12LC67X 3.0 6.0 9.0 µsA/D RC Mode

131 TCNV Conversion time ( not in cluding S/H

time) (Not e 1) 11 — 11 TAD

132 TACQ Acquisition time Note 2

—

µs

µs The minimum time is the

amplifier setting time. This

may be used if the "new"

input voltage has not

changed by more than 1 LSb

(i.e ., 20.0 mV @ 5.1 2V) from

the last sa m pl ed voltage (as

stated on CHOLD).

134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is

selected as RC, a time of

TCY is added be fore the A/D

clock star ts. This allows the

SLEEP instruction to be exe-

cuted.

135 TSWC Switching from conver t → s ample time 1.5 § — — TAD

* Thes e paramet ers are characteriz ed but not t ested.

† Data in “Typ” column is at 5V, 25°C unless otherwis e st at ed. These parameters ar e for design gui dance only and

are not tested.

§ This specification ensur ed by desi gn.

Note 1: ADRES register may be read on t he following TCY cycl e.

2: See Sect i on 8.1 f or min. conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

(TOSC/2)(1)

7 6543210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

134

 1999 Microchip Technology Inc. DS30561B-page 107
PIC12C67X
TABLE 12-9: EEPR OM MEMORY BUS TIMING REQUIREMENTS - PIC12CE673/674 ONLY.
AC Characteristics Standard Operating Conditions (unless otherwise specified)
Oper ati ng Temper a ture  0°C ≤ TA ≤ +70°C, Vcc = 3.0V to 5.5V (commercial)
–40°C ≤ TA ≤ +85°C, Vcc = 3.0V to 5.5V (industrial)
–40°C ≤ TA ≤ +125°C, Vcc = 4.5V to 5.5V (extended)
Oper ati ng Voltage  VDD range is described in Section 12.1
Parameter Symbol Min Max Units Conditions
Clock frequency FCLK —
—
—
100
100
400
kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V
4.5V ≤ Vcc ≤ 5.5V 
Clock high time THIGH 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V
Clock low time TLOW 4700
4700
1300
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V
SDA and SCL rise time
(Note 1) TR—
—
—
1000
1000
300
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V 
SDA and SCL fall time TF— 300 ns (Note 1)
START condition hold time T HD:STA 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V 
START condition setup time TSU:STA 4700
4700
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V 
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 250
250
100
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V
STOP condition setup time TSU:STO 4000
4000
600
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V
Output valid  from clock
(Note 2) TAA —
—
—
3500
3500
900
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V
Bus free  time:  Ti me the b us  must 
be free before a new transmis-
sion ca n start
TBUF 4700
4700
1300
—
—
—
ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)
3.0V ≤ Vcc ≤ 4.5V 
4.5V ≤ Vcc ≤ 5.5V
Output fall time from VIH
minimu m to VIL maximum TOF 20+0.1
CB 250 ns (Note 1), CB ≤ 100 pF
Input filter spike suppression
(SDA and SCL pins) TSP — 50 ns (Notes 1, 3)
Wr ite cycle time TWC —4ms
Endurance 1M — cycles 25°C, VCC = 5.0V, Block Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter , the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL and avoid unintended generation of STAR T or ST OP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved 
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific applica-
tion, please consult the Total Endurance Model which can be obtained on Microchip’s website.

PIC12C67X

DS30561B-page 108  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 109

PIC12C67X

13.0 DC AND AC CHARACTERISTICS - PIC12C671/PIC12C672/PIC 12L C671/

PIC12LC672/PIC12CE673/PIC12CE674/PIC12LCE673/PIC12LCE674

The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables

the data pre sented are outs ide spe cifie d oper ating r ange (i. e., ou tside speci fied VDD rang e). This is f or information only

and devices will operate properly only within the specified range.

The data presented in this secti on is a statistical summary of dat a collected on units fr om different lots over a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ)

respectiv e ly, where σ is standard deviation.

FIGURE 13-1: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS.

TEMPERATURE (VDD = 5.0V)

(INTERNAL RC IS

CALIBRATED TO 25°C, 5.0V)

FIGURE 13-2: CALIBRATED INTERNAL RC

FREQUENCY RANGE VS.

TEMPERATURE (VDD = 2.5V)

(INTERNAL RC IS

CALIBRATED TO 25°C, 5.0V)

4.40

4.30

4.20

4.10

4.00

3.90

3.80

3.70

3.60

3.50-40 25 85 125

4.50

Max.

Min.

Frequency (MHz)

Temperature (Deg.C)

4.40

4.30

4.20

4.10

4.00

3.90

3.80

3.70

3.60

3.50-40 25 85 125

4.50

Max.

Min

Frequency (MHz)

Temperature (Deg.C)

PIC12C67X

DS30561B-page 110  1999 Microchip Technology Inc.

TABLE 13-1: DYNAMIC IDD (TYPICAL) - WDT ENABLED, 25°C

FIGURE 13-3: WDT TIMER TIME- OU T

PERIOD vs. VDD FIGURE 13-4: IOH vs. VOH, VDD = 2.5 V

Oscillator Frequency VDD = 2.5V VDD = 5.5V

External RC 4 MHz 400 µA* 900 µA*

Internal RC 4 MHz 400 µA 900 µA

XT 4 MHz 400 µA 900 µA

LP 32 kHz 15 µA 60 µA

*Does not include current through external R&C.

MIn –40°C

Typ +25°C

Max +85°C

Max +125°C

100 2.5 3.5 4.5 5.5 6.5

VDD (Volts)

WDT period (mS)

Max -40°C

Typ +25°C

Min +85°C

Min +125°C

VOH (Volts)

IOH (mA)

.5 1.0 1.5 2.0 2.5

-0

-1

-2

-3

-4

-5

-10 2.251.751.25.75

-6

-7

-8

-9

 1999 Microchip Technology Inc. DS30561B-page 111

PIC12C67X

FIGURE 13-5: IOH vs. VOH, VDD = 3.5 V

FIGURE 13-6: IOH vs. VOH, VDD = 5.5 V

VOH (Volts)

IOH (mA)

1.5 2.0 2.5 3.0 3.5

-5

-10

-15

-20

-25

Mi n + 125°C

Min +85 °C

Typ +25°C

Max -40°C

3.5 4.0 4.5

VOH (Volts)

IOH (mA)

5.0 5.5

-5

-10

-15

-20

-25

-30

Min +125°C

Max –40°C

Typ +25°C

Min +85°C

-35

-40

FIGURE 13-7: IOL vs. VOL, VDD = 2.5 V

FIGURE 13-8: IOL vs. VOL, VDD = 3.5 V

Min +125°C

Min +85°C

Typ +25°C

Max -40°C

0.5 0.75 1.0

VOL (Volts)

IOL (mA)

0.25

Min +125°C

Min +85°C

Typ +25°C

Max -40°C

0.5 0.75 1.0

VOL (Volts)

IOL (mA)

0.25

PIC12C67X

DS30561B-page 112  1999 Microchip Technology Inc.

FIGURE 13-9: IOL vs. VOL, VDD = 5.5 V

Min +125°C

Min +85°C

Typ +25°C

Max -40°C

0.5 0.75 1.0

VOL (Volts)

IOL (mA)

0.25

FIGURE 13-10: VTH (INPUT THRESHOLD

VOLTAGE) OF GPI O PINS

vs. VDD

Typ (25)

Max (-40 to 125)

Min (-40 to 125)

1.6

1.4

1.2

1.0

0.8

0.6

02.5 3.5 4.5 5.5

VDD (Volts)

VTH (Volts)

1.8

 1999 Microchip Technology Inc. DS30561B-page 113

PIC12C67X

FIGURE 13-11 : VIL, VIH OF NMCLR AND T0CKI vs. VDD

3.5

3.0

2.5

2.0

1.5

1.0

0.52.5 3.5 4.5 5.5

VDD (Volts)

VIL, VIH (Volts)

VIH Max (-40 to 125)

VIH Typ (25)

VIH Min (-40 to 125)

VIL Max (-40 to 125)

VIL Typ (25)

VIL Min (-40 to 125)

PIC12C67X

DS30561B-page 114  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 115

PIC12C67X

14.0 PAC K A GING INFORMATION

14.1 Package Marking Information

MMMMMMMM

XXXXXCDE

AABB

8-Lead PDIP (300 mil) Example

8-Lead Windowed Ceramic Side Brazed (300 mil) Example

12CE674

04/PSAZ

9925

CE674

MMMMMM

Legend: MM...M Microch ip part number information

XX...X Customer specific information*

AA Year code (last 2 digits of calendar year)

BB Week code (week of January 1 is week ‘01’)

C Facility code of the plant at which wafer is manufactured

O = Outside Vendor

C = 5” Line

S = 6” Line

H = 8” Line

D Mask revision numbe r

E Assembly code of the plant or country of origin in which

part was assembled

Note: In the e v en t the full Mi crochi p part number canno t be ma rked on one line , it wil l

be carried over to the next line thus limiting the number of available characters

for custom er sp ecific informat ion.

*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask

rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with

your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

MMMMMMM

XXXXXXX

AABBCDE

8-Lead SOIC (208 mil) Example

12C671

04I/SM

9924SAZ

PIC12C67X

DS30561B-page 116  1999 Microchip Technology Inc.

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

Units INCHES* MILLIMETERS

Dime nsion Limits MIN NOM MAX MIN NOM MAX

Number of Pins n88

Pitch p.100 2.54

Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32

Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68

Base to Seating Plane A1 .015 0.38

Shoulder to Shoulder Width E .300 .313 .325 7.6 2 7.94 8.26

Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60

Overall Length D .360 .373 .385 9.14 9.46 9.78

Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43

Lead Thickness c.008 .012 .015 0.20 0.29 0.38

Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78

Lower Lead Width B .014 .018 .022 0.36 0.46 0.56

Overall Row Spacing eB .310 .370 .430 7.87 9.40 10.92

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

*Controlling Para meter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

JEDEC Equivalent: MS-001

Drawing No. C04-018

.010” (0.254mm) per side.

 1999 Microchip Technology Inc. DS30561B-page 117

PIC12C67X

8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC)

F oot Angl e φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.430.36.020.017.014BLead Width 0.250.230.20.010.009.008

Lead Thi ckness

0.760.640.51.030.025.020LFoot Length 5.335.215.13.210.205.202DOverall Length 5.385.285.11.212.208.201

Molded Pac kage Width 8.267.957.62.325.313.300EOverall Width 0.250.130.05.010.005.002A1Standoff 1.98.078A2Molded Package Thickness 2.03.080AOverall Height 1.27.050

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mit s MILLIMETERSINCHES*Units

.070 .075

.069 .074 1.78

1.75 1.97

1.88

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

Drawing No. C04-056

PIC12C67X

DS30561B-page 118  1999 Microchip Technology Inc.

8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil

7.116.866.60.280.270.260ULid Width 11.6811.4311.18.460.450.440TLid Length 4.344.224.09.171.166.161WWindow Diameter 8.237.877.52.324.310.296eBOverall Row Spacing 0.510.460.41.020.018.016BLower Lead Width 1.521.401.27.060.055.050B1Upper Lead Width 0.300.250.20.012.010.008

Lead Thickness 3.813.563.30.150.140.130LTip to Seating Plane 13.4613.2112.95.530.520.510DOverall Length 7.627.377.11.300.290.280E1Package Width 1.140.890.64.045.035.025A1Standoff 3.633.122.62.143.123.103A2Top of Body to Seating Plane 4.704.193.68.185.165.145ATop to Seating Plane 2.54.100

Pitch 88

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

*Controlling Para meter

JEDC Equivalent: MS-015

Drawing No. C04-083

 1999 Microchip Technology Inc. DS30561B-page 119

PIC12C67X

APPENDIX A:COMPATIBILITY

To convert code written for PIC16C5X to PIC12C67X,

the user should take the following steps:

1. Remove any program memory page select

operat ion s (PA2, PA1, PA0 bits) for CALL, GOTO.

2. Revisit any compute d jump operat ions (wr ite to

PC or add to PC, etc.) to make sure page bits

are set properly under the new scheme.

3. Eliminate any data memory page switching.

Redefine data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR

registers since these have changed.

5. Change reset vector to 0000h.

APPENDIX B:CODE FOR

ACCESSING EEPROM

DATA MEMORY

Please refer to our web site at www.microchip.com for

code availability.

PIC12C67X

DS30561B-page 120  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 121
PIC12C67X
INDEX
A
A/D Accuracy/Error............................................................51
ADCON0 Register.......................................................45
ADIF bit........ ...... ........... ..................... ..................... ....47
Analog Input Model Block Diagram.............................48
Analog-to-Digital Converter.........................................45
Configuring Analog Port Pins......................................49
Configuring the Interrupt.............................................47
Configuring the Module...............................................47
Connection Considerations................................... .. .. ..51
Conversi o n  Clo ck...... ...... ........... ...... ..................... ......49
Conversions................................................................50
Converter Characteristics .........................................105
Delays.........................................................................48
Effects of a Reset........................................................51
Equations....................................................................48
Flowchart of A/D Operation.........................................52
GO/DONE bit..............................................................47
Internal Sampling Switch (Rss) Impedence................48
Operation During Sleep..............................................51
Sampling Requirements....................... .... .. .. ....... .. .... ..48
Sampli n g Time........ ..................... ...... .......... ....... ........48
Source Impedence......................... .... .... .... ........... .... ..48
Time Dela ys....... ....... .......... ....... .......... ...... .................48
Transfe r Functio n.................... ..................... ...............51
Absolute Maximum Ratings................................................89
ADDLW Instruction .............................................................72
ADDWF Instruction.............................................................72
ADIE bit...............................................................................18
ADIF bit...... .......... ...... ........... ...... ........... ..................... ...... ..19
ADRES Register.....................................................13, 45, 47
ALU.......................................................................................7
ANDLW Instruction .............................................................72
ANDWF Instruction.............................................................72
Application Notes
AN546.........................................................................45
AN556.........................................................................22
Architecture
Harvard.........................................................................7
Overview.......................................................................7
von Neumann................................................................7
Assembler
MPASM Assembler.....................................................83
B
BCF Instruction...................................................................73
Bit Manipulation ....... ..................... ....... .......... ...... ........... ....70
Block Diagrams
Analog Input Model.....................................................48
On-Chip Reset Circuit.................................................57
Timer0.........................................................................39
Timer0/WDT Prescaler ...............................................42
Watchdog Timer...................... ......... .. .... .. .. ......... .. .. ....65
BSF Instruction ...................................................................73
BTFSC Instruction ...............................................................73
BTFSS Ins truction............. ..................... .......... ...................74
C
C bit ......... .......... ....... .......... ....... .......... ...... ........... ...... ........ 15
CAL0 bit...................... ...... ........... ...... .......... ....... .......... ...... 21
CAL1 bit...................... ...... ........... ...... .......... ....... .......... ...... 21
CAL2 bit...................... ...... ........... ...... .......... ....... .......... ...... 21
CAL3 bit...................... ...... ........... ...... .......... ....... .......... ...... 21
CALFST bit......................................................................... 21
CALL Inst ruction......... .......... ....... .......... ...... ........... ...... ...... 74
CALSLW bit....... ....... .......... ....... .......... ...... ........... ...... ........ 21
Carry bit...................... ...... ........... ...... .......... ....... .......... ....... . 7
Clocking Scheme................................................................ 10
CLRF Instru ction............................ ...... ...... ........... ...... ........ 74
CLRW Instruction................................................................ 74
CLRWDT Instru ction........... ..................... ....... ...... .......... .... 75
Code Examples
Changing Prescaler (Timer0 to WDT)........................ 43
Changing Prescaler (WDT to Timer0) ........................ 43
Indirect Addressing..................................................... 23
Code Protection............................................................ 53, 67
COMF Instruction................................................................ 75
Computed GOTO................................................................ 22
Configuration Bits ............................................................... 53
D
DC and AC Characteristics.......................... ......... .... .... .. .. 109
DC bit .................................................................................. 15
DC Characteristics
PIC12C671/672, PIC12CE673/674............................ 92
PIC12LC671/672, PIC12LCE673/674........................ 94
DECF Instruction ................................................................ 75
DECFSZ Instruction............................................................ 75
Development Support..................................................... 3, 83
Digit Carry bit........................................................................ 7
Direct Add ressing....... ............................... ....... .......... ...... .. 23
E
EEPROM Peripheral Operation............................ ...... .... .... 33
Electrical Characteristics - PIC12C67X.............................. 89
Errata.................................................................................... 2
External Brown-out Protection Circuit................................. 61
External Power-on Reset Circuit......................................... 61
F
Family of Devices ................................................................. 4
Features ............................................................................... 1
FSR Register.......................................................... 13, 14, 23
G
General Description........................... ...... .... ............. .... .... .... 3
GIE bit............ ........... ..................... .......... ....... .......... .......... 62
GOTO Instruction................................................................ 76
GPIF bit .............................................................................. 64
GPIO ............................................................................. 25, 59
GPIO Regis te r........ ...... .......... ....... .......... ....... .......... ...... .... 13
GPPU bit................. ...... .......... ..................... ..................... .. 16

PIC12C67X
DS30561B-page 122  1999 Microchip Technology Inc.
I
I/O Int e rfacing........... .......... ....... .......... ....... .......... ...... .........25
I/O Ports............... ...... ........... ..................... .......... ...... .........25
I/O Programming Considerations ........................................31
ID Locations........................................................................53
INCF Instruction..................................................................76
INCFSZ Instruction..............................................................76
In-Circuit Serial Programming.......................................53, 67
INDF Register ...............................................................14, 23
Indirect Addressing .............................................................23
Initialization Conditions for All Registers.............................59
Instruction Cycle..................................................................10
Instruction Flow/Pipelining ..................................................10
Instruction Format...............................................................69
Instruction Set
ADDLW.......................................................................72
ADDWF.......................................................................72
ANDLW.......................................................................72
ANDWF.......................................................................72
BCF.............................................................................73
BSF.............................................................................73
BTFSC ........................................................................73
BTFSS ........................................................................74
CALL...........................................................................74
CLRF...........................................................................74
CLRW .........................................................................74
CLRWDT.....................................................................75
COMF .........................................................................75
DECF ..........................................................................75
DECFSZ......................................................................75
GOTO .........................................................................76
INCF............................................................................76
INCFSZ.......................................................................76
IORLW ........................................................................76
IORWF........................................................................77
MOVF..........................................................................77
MOVLW ......................................................................77
MOVWF ......................................................................77
NOP............................................................................78
OPTION ......................................................................78
RETFIE .......................................................................78
RETLW .......................................................................78
RETURN.....................................................................79
RLF .............................................................................79
RRF.............................................................................79
SLEEP ........................................................................79
SUBLW .......................................................................80
SUBWF.......................................................................80
SWAPF .......................................................................81
TRIS............................................................................81
XORLW.......................................................................81
XORWF.......................................................................81
Section........................................................................69
INTCON Register................................................................17
INTEDG bit....... ..................... ..................... ..................... ....16
Internal Sampling Switch (Rss) Impedence ........................48
Interrupts.............................................................................53
A/D..............................................................................62
GP2/INT......................................................................62
GPIO Port ...................................................................62
Section........................................................................62
TMR0 ..........................................................................64
TMR0 Overflow...........................................................62
IORLW Instruction...............................................................76
IORWF Instruction........ ...... ........... ...... ..................... ....... ....77
IRP bit ... ...... ........... .......... ....... .......... ..................... ........... ..15
K
KeeLoq Evaluation and Programming Tools . .................. 86
L
Loading of PC........................... .... .. ......... .... .... .. ......... .... .... 22
M
MCLR............................................................................ 56, 59
Memory
Data Memor y.................. ...... ........... ...... ..................... 11
Program Memory........................................................ 11
Register File Map - PIC12C E6 7 X...... ...... ................... 12
MOVF Instruction................................................................ 77
MOVLW Instruction................... ........... ...... .......... ........... .... 77
MOVWF Instruction ............................................................ 77
MPLAB Integrated Development Environment Software.... 83
N
NOP Instruction .................................................................. 78
O
Opcode............................................................................... 69
OPTION Instruction ............................................................ 78
OPTION Register................................................................ 16
Orthogonal............................................................................ 7
OSC selection..................................................................... 53
OSCCAL Register...... ....... ..................... ...... ..................... .. 21
Oscillator
EXTRC ....................................................................... 58
HS............................................................................... 58
INTRC......................................................................... 58
LP ............................................................................... 58
XT............................................................................... 58
Oscillato r Configurat ions.................................... ....... .......... 54
Oscillator Types
EXTRC ....................................................................... 54
HS............................................................................... 54
INTRC......................................................................... 54
LP ............................................................................... 54
XT............................................................................... 54
P
Package Marking Information........................................... 115
Packagi n g  In fo rmation.... .......... ...... ........... ...... ........... ...... 115
Pagin g , Program Mem o ry........... ........... ..................... ........ 22
PCL..................................................................................... 70
PCL Register .......................................................... 13, 14, 22
PCLATH.............................................................................. 59
PCLATH Register................................................... 13, 14, 22
PCON Register............................................................. 20, 58
PD bit............................................................................ 15, 56
PICDEM-1 Low-Cost PICmicro Demo Board . .................... 85
PICDEM-2 Low-Cost PIC16CXX Demo Board................... 85
PICDEM-3 Low-Cost PIC16CXXX Demo Board ................ 85
PICSTART Plus Entry Level Development System......... 85
PIE1 Register...................................................................... 18
Pinout Description - PIC12CE67X........................................ 9
PIR1 Register ..................................................................... 19
POP.................................................................................... 22
POR.................................................................................... 58
Oscillator S tart-up Timer (OST)......... ............. ...... 53, 58
Power Control Register (PCON)................................. 58
Power-on Reset (POR)................................... 53, 58, 59
Power-up Timer (PWRT)...................................... 53, 58
Power-Up-Timer (PWRT) ........................................... 58
Time-out Sequence ........................... .... .. .... ......... .. .... 58
Time-out Sequence on Power-up................ ......... .... .. 60
TO............................................................................... 56
Power.................................................................................. 56

 1999 Microchip Technology Inc. DS30561B-page 123
PIC12C67X
Power-down Mode (SLEEP )...............................................66
Prescaler, Switching Between Timer0 and WDT.......... .... ..43
PRO MA TE  II Universal Programmer ..............................85
Program Branches................................................................7
Program Mem ory
Paging.........................................................................22
Program Verification ...........................................................67
PS0 bit ........... .......... ....... .......... ...... ........... ..................... ....16
PS1 bit ........... .......... ....... .......... ...... ........... ..................... ....16
PS2 bit ........... .......... ....... .......... ...... ........... ..................... ....16
PSA bit................................................................................16
PUSH..................................................................................22
R
RC Oscillator.......................................................................55
Read Modify Write ..............................................................31
Read-Modify-Write..............................................................31
Register File............. ....... .......... ...... ..................... ....... ........11
Registers
Map PIC12C67X.........................................................12
Reset Conditions....... .......................................... ...... ..59
Reset.............................................................................53, 56
Reset Conditions for Special Registers ..............................59
RETFIE Ins truction............ ...... ..................... ...... .................78
RETLW Instruction..............................................................78
RETURN Instruction ...........................................................79
RLF Instru ction....... ....... .......... ...... ........... ...... ........... ...... ....79
RP0 bit..........................................................................11, 15
RP1 bit................................................................................15
RRF Instruction........ ....... .......... ...... ................................ ....79
S
SEEVAL Evaluation and Programming System...............86
Services
One-Time-Programmable (OTP) ..................................5
Quick-Turnaround-Production (QTP)............................5
Serialized Quick-Turnaround Production (SQTP).........5
SFR.....................................................................................70
SFR As Source/Destination................................................70
SLEEP ..........................................................................53, 56
SLEEP In struction................. .......... ........... ..................... ....79
Softwa re Simulator ( MP L AB-SIM) ................. ...... ........... ....84
Special Features of the CPU ..............................................53
Special Function Register
PIC12C67X.................................................................13
Special Function Registers.................................................70
Special Function Registers, Section ...................................12
Stack...................................................................................22
Overflows....................................................................22
Underflow....................................................................22
STATUS Regi ster ...... ........... ...... ........... ...... ........... ...... ......15
SUBLW Ins truction.......................... ..................... ...............80
SUBWF Instruction .............................................................80
SWAPF Ins truction.......................... ....... .......... ...................81
T
T0CS bit.............................................................................. 16
TAD ..................................................................................... 49
Timer0
RTCC.......................................................................... 59
Timers
Timer0
Block Diag ram................. ...... ........... ...... ............ 39
External Clock.................................................... 41
External Clock Timing......................................... 41
Increment Delay................................................. 41
Interrupt.............................................................. 39
Interrupt Timing.................................................. 40
Prescaler ............................................................ 42
Prescaler Block Diagram.................................... 42
Section ............................................................... 39
Switching Prescaler Assignment........................ 43
Synchronization.................................................. 41
T0CKI ................................................................. 41
T0IF.................................................................... 64
Timing................................................................. 39
TMR0 Interrupt ................................................... 64
Timing Diagrams
A/D Conver sion ........ ...... ..................... ....... .......... .... 106
CLKOUT and I/O...................................................... 102
External Clock Timing............................................... 100
Time-out Sequence ............................. ......... .. .... .... .. .. 60
Timer0 ........................................................................ 39
Timer0 Interrupt Timing.............................................. 40
Timer0 with External Clock......................................... 41
Wake-up from Sleep via Interrupt. .............................. 67
TO bit.................................................................................. 15
TOSE bit............................................................................. 16
TRIS Instr u ction............ ...... ........... ...... ........... ...... .......... .... 81
TRIS Register......................................................... 14, 25, 31
Two’s Complem e nt........... ...... ....... ..................... ...... ...... ...... 7
U
UV Erasable Devices ............................................................ 5
W
W Register
ALU............................................................................... 7
Wake-up from SLEEP......................................................... 66
Watchdog Timer (WDT)................... .. .... .. .... ..... 53, 56, 59, 65
WDT ................................................................................... 59
Block Diag ram.. ...... ........... ...... .......... ....... .......... ...... .. 65
Period......................................................................... 65
Programming Consider a tions...... ...... ........... ...... ........ 65
Timeout....................................................................... 59
WWW, On-Line Support....................................................... 2
X
XORLW Instruction............................................................. 81
XORWF Instr u ction.......................... ...... ........... ...... ............ 81
Z
Z bit.............. ...... ........... ...... ........... ..................... ................ 15
Zero bit ........ ...... ........... ...... ........... ..................... .................. 7

PIC12C67X

DS30561B-page 124  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. DS30561B-page 125

PIC12C67X

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip’s development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-786-7302 for the rest of the world.

Trademarks: The Microchip name, logo, PIC, PICmicro,

PICSTART, PICMASTER, PRO MATE and MPLAB are

registered trademarks of Microchip Technology Incorpo-

rated in the U.S.A. and other countries.

Flex

ROM and

fuzzy

LAB are trademarks and SQTP is a service mark of

Microchip in the U.S.A.

All other trademarks mentioned herein are the property of

their respective companies.

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web (WWW) site.

The we b site is used b y Mic rochi p as a mean s to mak e

files and infor mation easily available to customers. To

vie w the site , the user must ha v e access to the Internet

and a web browser, such as Netscape or Microsoft

Explorer. Files are also available for FTP download

from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your

favorite Internet browser to attach to:

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User’s Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for cons ideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

•Device Errata

• Job Posting s

• Microchip C onsultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Conferences for products, Development Sys-

tems, technical information and more

• Listing of seminars and events

981103

PIC12C67X

DS30561B-page 126  1999 Microchip Technology Inc.

READER RESPONSE

It is our i ntention to provide you w ith the bes t d ocu me nta tion poss ible to ensure suc ce ssf ul us e of your Microchi p pro d-

uct. If you wish to provide your comments on organization, clarity, subject matter , and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To: Technical Publications Manager

RE: Reader Response Total Pages Sent

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DS30561B

PIC12C67X

 1999 Microchip Technology Inc. DS30561B-page 127

PIC12C67X

PIC12C67X PRODUCT IDENTIFICATION SYSTEM

* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement

of each oscillator type (including LC devic es).

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-

mended workarounds. To determine if an errata sheet exists for a par t icular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 786-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Pattern: Special Requirements

Package: P = 300 mil PDIP

JW = 300 mil Windowed Ceramic Side Brazed

SM = 208 mil SOIC

Temp erature

Range: -=0

°C to +70°C

I=-40

°C to +85°C

E=-40

°C to +125°C

Frequency

Range: 04 = 4 MHz/200 kHz

10 = 10 MHz

Device PIC12CE673

PIC12CE674

PIC12LCE673

PIC12LCE674

PIC12C671

PIC12C672

PIC12C671T (Tape & reel for SOIC only)

PIC12C672T (Tape & reel for SOIC only)

PIC12LC671

PIC12LC672

PIC12LC671T (Tape & reel for SOIC only)

PIC12LC672T (Tape & reel for SOIC only)

PART NO. -XX X /XX XXX Examples

a) PIC12CE673-04/P

Commercial Temp.,

PDIP Package, 4 MHz,

normal VDD limits

b) PIC12CE673-04I/P

Industrial Temp ., PDIP

package, 4 MHz, normal

VDD limits

c) PIC12CE673-10I/P

Industrial Temp .,

PDIP package, 10 MHz,

normal VDD limits

d) PIC12C671-04/P

Commercial Temp.,

PDIP Package, 4 MHz,

normal VDD limits

e) PIC12C671-04I/SM

Indust rial Temp ., SOIC

package, 4 MHz, normal

VDD limits

f) PIC12C671-04I/P

Industrial Temp .,

PDIP package, 4 MHz,

normal VDD limits

 2002 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

 2002 Microchip Technology Inc.

AMERICAS

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01/18/02

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