MC14093B Quad 2-Input NAND" Schmitt Trigger The MC14093B Schmitt trigger is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14093B may be used in place of the MC14011B quad 2-input NAND gate for enhanced noise immunity or to "square up" slowly changing waveforms. http://onsemi.com MARKING DIAGRAMS * Supply Voltage Range = 3.0 Vdc to 18 Vdc * Capable of Driving Two Low-Power TTL Loads or One Low-Power * * * * 14 PDIP-14 P SUFFIX CASE 646 Schottky TTL Load Over the Rated Temperature Range Triple Diode Protection on All Inputs Pin-for-Pin Compatible with CD4093 Can be Used to Replace MC14011B Independent Schmitt-Trigger at each Input MC14093BCP AWLYYWW 1 14 SOIC-14 D SUFFIX CASE 751A 14093B AWLYWW 1 14 TSSOP-14 DT SUFFIX CASE 948G MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Parameter DC Supply Voltage Range Unit - 0.5 to +18.0 V - 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin 10 mA PD Power Dissipation, per Package (Note 3.) 500 mW TA Ambient Temperature Range - 55 to +125 C Tstg Storage Temperature Range - 65 to +150 C TL Lead Temperature (8-Second Soldering) 260 C Iin, Iout Input or Output Voltage Range (DC or Transient) Value 1 14 SOEIAJ-14 F SUFFIX CASE 965 MC14093B AWLYWW 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: - 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v 14 093B ALYW v Device Package Shipping MC14093BCP PDIP-14 2000/Box MC14093BD SOIC-14 2750/Box MC14093BDR2 SOIC-14 2500/Tape & Reel MC14093BDT TSSOP-14 96/Rail MC14093BDTEL TSSOP-14 2000/Tape & Reel MC14093BDTR2 TSSOP-14 2500/Tape & Reel MC14093BF SOEIAJ-14 See Note 1. MC14093BFEL SOEIAJ-14 See Note 1. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2000 March, 2000 - Rev. 3 1 Publication Order Number: MC14093B/D MC14093B PIN ASSIGNMENT IN 1A 1 14 VDD IN 2A 2 13 IN 2D OUTA 3 12 IN 1D OUTB 4 11 OUTD IN 1B 5 10 OUTC IN 2B 6 9 IN 2C VSS 7 8 IN 1C LOGIC DIAGRAM 1 2 3 5 6 4 8 9 10 12 13 11 VDD = PIN 14 VSS = PIN 7 EQUIVALENT CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN) http://onsemi.com 2 MC14093B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III IIIII IIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III I III III IIII III III III IIIII IIIIIIIII IIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIIIIIIIIII IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III III III IIII III IIII III III IIIIIIIIII IIII III IIIIIIIIIIIIIIIII III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III IIIIIIIIII IIII III III III IIII III IIII III III III ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol - 55_C 25_C 125_C VDD Vdc Min Max Min Typ (4.) Max Min Max Unit "0" Level VOL 5.0 10 15 -- -- -- 0.05 0.05 0.05 -- -- -- 0 0 0 0.05 0.05 0.05 -- -- -- 0.05 0.05 0.05 Vdc "1" Level VOH 5.0 10 15 4.95 9.95 14.95 -- -- -- 4.95 9.95 14.95 5.0 10 15 -- -- -- 4.95 9.95 14.95 -- -- -- Vdc 5.0 5.0 10 15 - 3.0 - 0.64 - 1.6 - 4.2 -- -- -- -- - 2.4 - 0.51 - 1.3 - 3.4 - 4.2 - 0.88 - 2.25 - 8.8 -- -- -- -- - 1.7 - 0.36 - 0.9 - 2.4 -- -- -- -- IOL 5.0 10 15 0.64 1.6 4.2 -- -- -- 0.51 1.3 3.4 0.88 2.25 8.8 -- -- -- 0.36 0.9 2.4 -- -- -- mAdc Input Current Iin 15 -- 0.1 -- 0.00001 0.1 -- 1.0 Adc Input Capacitance (Vin = 0) Cin -- -- -- -- 5.0 7.5 -- -- pF Quiescent Current (Per Package) IDD 5.0 10 15 -- -- -- 0.25 0.5 1.0 -- -- -- 0.0005 0.0010 0.0015 0.25 0.5 1.0 -- -- -- 7.5 15 30 Adc IT 5.0 10 15 Hysteresis Voltage VH 5.0 10 15 0.3 1.2 1.6 2.0 3.4 5.0 0.3 1.2 1.6 1.1 1.7 2.1 2.0 3.4 5.0 0.3 1.2 1.6 2.0 3.4 5.0 Threshold Voltage Positive-Going VT+ 5.0 10 15 2.2 4.6 6.8 3.6 7.1 10.8 2.2 4.6 6.8 2.9 5.9 8.8 3.6 7.1 10.8 2.2 4.6 6.8 3.6 7.1 10.8 VT- 5.0 10 15 0.9 2.5 4.0 2.8 5.2 7.4 0.9 2.5 4.0 1.9 3.9 5.8 2.8 5.2 7.4 0.9 2.5 4.0 2.8 5.2 7.4 Vin = 0 or VDD Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) IOH Source Sink Total Supply Current (5.) (6.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) Negative-Going mAdc IT = (1.2 A/kHz) f + IDD IT = (2.4 A/kHz) f + IDD IT = (3.6 A/kHz) f + IDD Adc Vdc Vdc 4. Data labelled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. 5. The formulas given are for the typical characteristics only at 25_C. 6. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL - 50) Vfk where: IT is in A (per package), CL in pF, V = (VDD - VSS) in volts, f in kHz is input frequency, and k = 0.004. http://onsemi.com 3 Vdc MC14093B IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III IIIIIIIIIIIIIII IIIII IIII IIII IIII IIII III SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C) Characteristic Symbol VDD Vdc Min Typ (7.) Max Unit Output Rise Time tTLH 5.0 10 15 -- -- -- 100 50 40 200 100 80 ns Output Fall Time tTHL 5.0 10 15 -- -- -- 100 50 40 200 100 80 ns tPLH, tPHL 5.0 10 15 -- -- -- 125 50 40 250 100 80 ns Propagation Delay Time 7. Data labeled "Typ" is not to be used for design purposes but is intended as an indication of the IC's potential performance. VDD 20 ns 14 PULSE GENERATOR INPUT OUTPUT 20 ns VDD 90% 50% 10% tPHL INPUT 7 VSS CL tPLH 90% 50% 10% OUTPUT tTHL VSS VOH VOL tTLH Figure 1. Switching Time Test Circuit and Waveforms VH VDD VH Vin VDD Vin VSS VSS VDD VDD Vout Vout VSS VSS (a) Schmitt Triggers will square up (a) inputs with slow rise and fall times. (b) A Schmitt trigger offers maximum (b) noise immunity in gate applications. Figure 2. Typical Schmitt Trigger Applications http://onsemi.com 4 MC14093B 14 14 IOH VGS Vout All unused inputs connected to ground. VGS 10 VGS = - 5.0 Vdc a b b a TA = - 55C TA = + 25C TA = + 125C c - 6.0 - 10 Vdc b c - 8.0 - 10 - 10 IOL , DRAIN CURRENT (mAdc) - 4.0 7 All unused inputs connected to ground. c b - 2.0 - 15 Vdc b a - 8.0 Vout 7 - 6.0 - 4.0 VDS, DRAIN VOLTAGE (Vdc) a b c 15 Vdc a 8.0 VGS = 10 Vdc b c 6.0 a b c 4.0 b a - 2.0 0 0 0 2.0 4.0 6.0 VDS, DRAIN VOLTAGE (Vdc) 8.0 Figure 4. Typical Output Sink Characteristics Test Circuit VDD 0 5.0 Vdc c Figure 3. Typical Output Source Characteristics Test Circuit 0 TA = - 55C TA = + 25C TA = + 125C a 2.0 Vout , OUTPUT VOLTAGE (Vdc) IOH, DRAIN CURRENT (mAdc) 0 IOL VT- VT+ VH Vin, INPUT VOLTAGE (Vdc) Figure 5. Typical Transfer Characteristics http://onsemi.com 5 VDD 10 MC14093B PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE M 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F DIM A B C D F G H J K L M N L N C -T- SEATING PLANE J K H D 14 PL G M 0.13 (0.005) INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 --- 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 --- 10_ 0.38 1.01 M D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- 1 P 7 PL 0.25 (0.010) 7 G B M M R X 45 _ C F -T- SEATING PLANE 0.25 (0.010) M K D 14 PL M T B S A S http://onsemi.com 6 J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC14093B PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 0.25 (0.010) 8 M B -U- L PIN 1 IDENT. F 7 1 0.15 (0.006) T U N S DETAIL E K A -V- CCC EE CCC EE K1 J J1 SECTION N-N -W- C 0.10 (0.004) -T- SEATING PLANE D G H DETAIL E http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ MC14093B PACKAGE DIMENSIONS F SUFFIX PLASTIC EIAJ SOIC PACKAGE CASE 965-01 ISSUE O 14 LE 8 Q1 E HE M_ L 7 1 DETAIL P Z D VIEW P A e c A1 b 0.13 (0.005) M 0.10 (0.004) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX --- 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --- 1.42 INCHES MIN MAX --- 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --- 0.056 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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