KSZ8091MLX
10Base-T/100Base-TX
Physical Layer Transceiver
Revision 1.2
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August
31, 2015
Revision 1.2
General Description
The KSZ8091MLX is a single-supply 10Base-T/100Base-
TX Ethernet physical layer transceiver for transmission
and reception of data over standard CAT-5 unshielded
twisted pair (UTP) cable.
The KSZ809 1MLX is a hi gh l y-inte grat e d, c ompact s olution.
It reduces board cost and simplifies board layout by using
on-chip termination resistors for the differential pairs, by
integrating a low-noise regulator to supply the 1.2V core,
and by offering a flexible 1.8/2.5/3.3V digital I/O interface.
The KSZ8091MLX offers the Media Independent Interface
(MII) for direct connection with MII-compliant Ethernet
MAC processors and switches.
Energy Efficient Ethernet (EEE) provides further power
saving dur ing idle traff ic periods and W ake-on-LAN ( WOL)
provides a mechanism for the KSZ8091 MLX to wake up a
system that is in standby power mode.
The KSZ8091MLX is available in the 48-pin, lead-free
LQFP package (see Ordering Information).
Datasheets and support documentation are available on
website at: www.micrel.com.
Features
• Single-chip 10Bas e-T/100Base-TX IEEE 802.3
compliant Ethernet transceiver
• MII interface support
• Back-to-back mode support for a 100Mbps copper
repeater
• MDC/MDIO management interface for PHY register
configuration
• Programmable interrupt output
• LED outputs for link, activity and speed status indication
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct
straight-through and crossover cable connections with
disable and en able opt ion
• Auto-Negotiation to automatically select the highest link-
up speed (10/100Mbps) and duplex (half/full)
• Energy Efficient Ethernet (EEE) support with low-power
idle (LPI) mode and clock stoppage for 100Base TX and
transmit amplitude reduction with 10Base-Te option
• Wake-On-LAN (WOL) support with either magic packet,
link status change, or robust custom-packet detection
• LinkMD® TDR-based cable diagnostics to identify faulty
copper cabling
Functional Diagram
Micrel, Inc.
KSZ8091MLX
August
31, 2015 2 Revision 1.2
Features (Continued)
• HBM ESD rating (6kV)
• Parametric NAND Tree support for fault detection
between chip I/Os and the board
• Loopback modes for diagnostics
• Power-down and power-saving modes
• Single 3.3V power supply with VDD I/O options for 1.8V,
2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 48-pin (7mm x 7mm) LQFP package
Applications
• Game console
• IP phone
• IP set-top box
• IP TV
• LOM
• Printer
Ordering Information
Orderin g Part
Number Temperature
Range Package Lead
Finish Description
KSZ8091MLXCA 0°C to 70°C 48-Pin LQFP Pb-Free MII, EEE and WoL Support, Commercial
Temperature.
KSZ8091MLXIA(1) −40°C to 85°C 48-Pin LQFP Pb-Free MII, EEE and WoL Support, Industrial
Temperature.
KSZ8081MLX-EVAL KSZ8091 MLX Ev alu ati on B oard
(Mounted with KSZ8091MLX device in
commercial temperature)
Note:
1. Contact factory for lead time.
Micrel, Inc.
KSZ8091MLX
August
31, 2015 3 Revision 1.2
Revision History
Date
Summary of Changes
Revision
1/14/14 New datasheet 1.0
11/25/14 Added silver wire bonding part numbers to Ordering Information.
Updated Ordering Information to include Ordering Part Number and Device Marking. 1.1
08/31/15 Add Max frequency for MDC in MII Management (MIIM) Interface section.
Updated Table 17 and Table 19.
Updated order i ng inf ormation Table.
Updated desc r ipt ion and add an equ ation in Li nkMD section.
Add a note for table 21.
Updated description for Figure 21.
Add a note for Figure 22.
Add HBM ESD rating in Features.
1.2
Micrel, Inc.
KSZ8091MLX
August
31, 2015 4 Revision 1.2
Contents
List of Figures .......................................................................................................................................................................... 6
List of Tables ........................................................................................................................................................................... 7
Pin Configuration ..................................................................................................................................................................... 8
Pin Description ........................................................................................................................................................................ 9
Strapping Options ................................................................................................................................................................. 13
Functional Description: 10Base-T/100Base-TX Transceiver ................................................................................................ 15
100Base-TX Transmit ........................................................................................................................................................ 15
100Base-TX Receive ......................................................................................................................................................... 15
Scrambler/De-Scrambler (100Base-TX Only) ................................................................................................................... 15
10Base-T Transmit ............................................................................................................................................................ 15
10Base-T Receive ............................................................................................................................................................. 16
SQE and Jabber Function (10Base-T Only)...................................................................................................................... 16
PLL Clock Synthesizer ...................................................................................................................................................... 16
Auto-Negotiation ................................................................................................................................................................ 16
MII Data Interface .................................................................................................................................................................. 18
MII Signal Definition ........................................................................................................................................................... 18
Transmit Clock (TXC) .................................................................................................................................................... 18
Transmit Enable (TXEN) ................................................................................................................................................ 18
Transmit Data[3:0] (TXD[3:0]) ........................................................................................................................................ 19
Transmit Error (TXER) ................................................................................................................................................... 19
Receive Clock (RXC) ..................................................................................................................................................... 19
Receive Data Valid (RXDV) ........................................................................................................................................... 19
Receive Data[3:0] (RXD[3:0]) ........................................................................................................................................ 19
Receive Error (RXER) .................................................................................................................................................... 19
Carrier Sense (CRS) ...................................................................................................................................................... 20
Collision (COL) ............................................................................................................................................................... 20
MII Signal Diagram ............................................................................................................................................................ 20
Back-to-Back Mode – 100Mbps Copper Repeater ............................................................................................................... 21
MII Back-to-Back Mode ..................................................................................................................................................... 21
MII Management (MIIM) Interface ......................................................................................................................................... 22
Interrupt (INTRP) ................................................................................................................................................................... 23
HP Auto MDI/MDI-X .............................................................................................................................................................. 23
Straight Cab le .................................................................................................................................................................... 23
Crossover Cable ................................................................................................................................................................ 24
Loopback Mode ..................................................................................................................................................................... 24
Local (Digital) Loopback .................................................................................................................................................... 24
Remote (Analog) Loopback ............................................................................................................................................... 25
LinkMD® Cab le Di agn os tic .................................................................................................................................................... 27
NAND Tree Support .............................................................................................................................................................. 27
NAND Tree I/O Testing ..................................................................................................................................................... 28
Power Manag ement .............................................................................................................................................................. 29
Power-Saving Mode .......................................................................................................................................................... 29
Energy-Detect Power-Down Mode .................................................................................................................................... 29
Power-Down Mode ............................................................................................................................................................ 29
Slow-Oscillator Mode ......................................................................................................................................................... 29
Efficient Ethernet (EEE) ........................................................................................................................................................ 30
Transmit Direction Control (MAC-to-PHY) ........................................................................................................................ 30
Receive Direction Control (PHY-to-MAC) ......................................................................................................................... 31
Register s Ass ociate d w ith EEE ......................................................................................................................................... 31
Micrel, Inc.
KSZ8091MLX
August
31, 2015 5 Revision 1.2
Wake-On-LAN ....................................................................................................................................................................... 32
Magic-Packet Detection ..................................................................................................................................................... 32
Customized-Packet Detection ........................................................................................................................................... 32
Link Status Change Detection ........................................................................................................................................... 33
Reference Circuit for Power and Ground Connections ......................................................................................................... 34
Typical Current/Power Consumption .................................................................................................................................... 35
Transceiver (3.3V), Digital I/Os (3.3V) .............................................................................................................................. 35
Transceiver (3.3V), Digital I/Os (2.5V) .............................................................................................................................. 35
Transceiver (3.3V), Digital I/Os (1.8V) .............................................................................................................................. 36
Register Map ......................................................................................................................................................................... 37
Standar d Reg is ters ............................................................................................................................................................... 39
IEEE-Defined Registers – Descriptions ............................................................................................................................. 39
Vendor-Specific Registers – Descriptions ......................................................................................................................... 44
MMD Registers...................................................................................................................................................................... 49
MMD Registers – Descriptions .......................................................................................................................................... 51
Absolute Maximum Ratings .................................................................................................................................................. 56
Operating Ratings ................................................................................................................................................................. 56
Electrical Characteristics ....................................................................................................................................................... 56
Timing Diagrams ................................................................................................................................................................... 58
MII SQE Timing (10Base-T) .............................................................................................................................................. 58
MII Transmit Timing (10Base-T) ........................................................................................................................................ 59
MII Receive Timing (10Base-T) ......................................................................................................................................... 60
MII Transmit Timing (100Base-TX) ................................................................................................................................... 61
MII Receive Timing (100Base-TX) .................................................................................................................................... 62
Auto-Negotiation Timing .................................................................................................................................................... 63
MDC/MDIO Timing ............................................................................................................................................................ 64
Power-Up/Reset Timing .................................................................................................................................................... 65
Reset Circuit .......................................................................................................................................................................... 66
Reference Circuits – LED S t ra p-In Pins ................................................................................................................................ 67
Reference Clock – Connection and Selection ...................................................................................................................... 68
Magnetic – Connection and Selection .................................................................................................................................. 69
Package Information and Recommended Land Pattern ....................................................................................................... 71
Micrel, Inc.
KSZ8091MLX
August
31, 2015 6 Revision 1.2
List of Figures
Figure 1. Auto-Negotiation Flow Chart ................................................................................................................................ 17
Figure 2. KSZ8091MLX MII Interface ................................................................................................................................ 20
Figure 3. KSZ8091MLX to KSZ8091MLX Back-to-Back Copper Repeater ....................................................................... 21
Figure 4. Typical Straight Cable Connection ..................................................................................................................... 23
Figure 5. Typical Crossover Cable Connection ................................................................................................................. 24
Figure 6. Local (Digital) Loopback ..................................................................................................................................... 25
Figure 7. Remote (Analog) Loopback ................................................................................................................................ 26
Figure 8. LPI Mode (Refresh Transmissions and Quiet Periods) ...................................................................................... 30
Figure 9. LPI Transition – MII (100Mbps) Transmit ........................................................................................................... 31
Figure 10. LPI Transition – MII (100Mbps) Receive ............................................................................................................ 31
Figure 11. KSZ8091MLX Power and Ground Connections ................................................................................................. 34
Figure 12. MII SQE Timing (10Base-T) ............................................................................................................................... 58
Figure 13. MII Transmit Timing (10Base-T) ......................................................................................................................... 59
Figure 14. MII Receive Timing (10Base-T) .......................................................................................................................... 60
Figure 15. MII Transmit Timing (100Base-TX) ..................................................................................................................... 61
Figure 16. MII Receive Timing (100Base-TX) ...................................................................................................................... 62
Figure 17. Auto-Negotiation Fast Link Pulse (FLP) Timing ................................................................................................. 63
Figure 18. MDC/MDIO Timing .............................................................................................................................................. 64
Figure 19. Power-Up/Reset Timing ...................................................................................................................................... 65
Figure 20. Recommended Res et Circ uit .............................................................................................................................. 66
Figure 21. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ..................................................... 66
Figure 22. Reference Circuits for LED Strapping Pins ........................................................................................................ 67
Figure 23. 25MHz Crystal/Oscillator Reference Clock Connection ..................................................................................... 68
Figure 24. Typical Magnetic Interface Circuit ....................................................................................................................... 69
Micrel, Inc.
KSZ8091MLX
August
31, 2015 7 Revision 1.2
List of Tables
Table 1. MII Signal Definition ............................................................................................................................................. 18
Table 2. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater) .......................................... 21
Table 3. MII Management Frame Format for the KSZ8091MLX ....................................................................................... 22
Table 4. MDI/MDI-X Pin Definit ion ..................................................................................................................................... 23
Table 5. NAND Tree Test Pin Order for KSZ8091MLX ..................................................................................................... 28
Table 6. KSZ8091MLX Power Pin Description .................................................................................................................. 34
Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V) .......................................................... 35
Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V) .......................................................... 35
Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) .......................................................... 36
Table 10. Standard Registers Supported by KSZ8091MLX ................................................................................................ 37
Table 11. MMD Registers Supported by KSZ8091MLX ...................................................................................................... 38
Table 12. Portal Registers (Access to Indirect MMD Registers) .......................................................................................... 49
Table 13. MII SQE Timing (10Base-T) Parameters ............................................................................................................. 58
Table 14. MII Transmit Timing (10Base-T) Parameters ...................................................................................................... 59
Table 15. MII Receive Timing (10Base-T) Parameters ....................................................................................................... 60
Table 16. MII Transmit Timing (100Base-TX) Parameters .................................................................................................. 61
Table 17. MII Receive Timing (100Base-TX) Parameters ................................................................................................... 62
Table 18. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters ............................................................................... 63
Table 19. MDC/MDIO Timing Parameters ........................................................................................................................... 64
Table 20. Power-Up/Reset Timing Parameters ................................................................................................................... 65
Table 21. 25MHz Crystal / Reference Clock Selection Criteria ........................................................................................... 68
Table 22. Magnetics Selection Criteria ................................................................................................................................ 70
Table 23. Compatible Single-Port 10/100 Magnetics .......................................................................................................... 70
Micrel, Inc.
KSZ8091MLX
August
31, 2015 8 Revision 1.2
Pin Configuration
48-Pin 7mm × 7mm LQFP
Micrel, Inc.
KSZ8091MLX
August
31, 2015 9 Revision 1.2
Pin Description
Pin Number Pin Name Type
(2)
Pin Function
1 GND GND Ground.
2 GND GND Ground.
3 GND GND Ground.
4 VDD_1.2 P 1.2V core VDD. (Power supplied by KSZ8091MLX.)
Decouple with 2.2µF and 0.1µF capacitors to ground, and join with Pin 31 by power
trace or plane.
5 NC No Connect. This pin is not bonded and can be left floating.
6 NC No Connect. This pin is not bonded and can be left floatin g.
7 VDDA_3.3 P 3.3V analog VDD.
8 NC No Connect. This pin is not bonded and can be left floating.
9 RXM I/O Physical Receive or Transmit S ignal (− differential).
10 RXP I/O Physical Receive or Transmit Signal (+ differential).
11 TXM I/O Physical Transmit or Receiv e Signal (− differential).
12 TXP I/O Physical Transmit or Receiv e Signal (+ differential).
13 GND GND Ground.
14 XO O Crystal Feedback for 25MHz Crystal. This pin is a no connect if an oscillator or
external clock source is used.
15 XI I Crystal / Oscillator / External Clock Input (25MHz ±50ppm).
16 REXT I Set PHY Transmi t Output Current. Connect a 6.49kΩ res istor to ground on this pin.
17 GND GND Ground.
18 MDIO Ipu/Opu Management Interface (MII) Data I/O. This pin has a weak pull-up, is open-drain, and
requires an external 1.0kΩ pull-up resistor.
19 MDC Ipu Management Interface (MII) Clock Input. This clock pin is synchronous to the MDIO
data pin.
20 RXD3/
PHYAD0 Ipu/O MII mode: MII Receive Data Output[3](3).
Config mode: The pull-up/pull-down value is latched as PHYADDR[0] at the
de-assertion of reset. See the Strapping Options section for details.
Notes:
2. P = Power supply.
GND = Ground.
I = Input.
O = Output.
I/O = Bi-directional.
Ipu = Input with internal pull -up (see El ect ric al Characteris t ics for value).
Ipd = Input with internal pull -down (see Electrical Characteristics for value).
Ipu/O = Input with internal pull-up (see Electri cal Characteristics for value) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact eri st ics for
value).
Opd = Output with internal pull-down (see Electri c al Characteri st i cs for value).
3. MII RX Mode: The RXD[3:0] bits are synchronous with RXC. When RXDV is asserted, RXD[3:0] pres ents valid dat a to the MAC.
Micrel, Inc.
KSZ8091MLX
August
31, 2015 10 Revision 1.2
Pin Description (Continued)
Pin Number Pin Name Type
(2)
Pin Function
21 RXD2/
PHYAD1 Ipd/O MII Mode: MII Receive Data Output[2]
(3)
.
Config. Mode: The pull-up/pull-down value is latched as PH YADDR[1] at the
de-assertion of reset. See the Strapping Options s ect ion for detai ls.
22 RXD1/
PHYAD2 Ipd/O MII Mode: MII Receive Data Output[1](3).
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See the Strapping Options sect ion f or detai ls.
23 RXD0/
DUPLEX Ipu/O MII mode: MII Receive Data Output[0](3).
Config. Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion of
reset. See the Strapping Options sect ion for details.
24 GND GND Ground.
25 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD.
26 NC No Connect. This pin is not bonded and can be left floating.
27 RXDV/
CONFIG2 Ipd/O MII Mode: MII Receive Data Valid Output
Config. Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion
of reset. See t he Strapping O ptions section for details.
28 RXC/
B-CAST_OFF Ipd/O MII mode: MII Receive Clock Output
Config mode: The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset. See the Strapping Options section for details.
29 RXER/
ISO Ipd/O MII Mode: MII Receive Error Output
Config. Mode: The pull-up/pull-down value is latched as ISOLATE at the de-asser t ion of
reset. See the Strapping Options sect ion for details.
30 GND GND Ground.
31 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8091MLX). Decouple w ith 0.1µF capac itor t o
ground, and join with Pin 4 by power trace or plane.
32
INTRP/
PME_N2/
NAND_Tree#
Ipu/Opu
Interrupt Output: Programmable interrupt output, with Register 1Bh as the Interrupt
Control/Status register, for programming the interrupt conditions and reading the
interrupt status. Register 1Fh, Bit [9] sets the interrupt output to active low (default) or
active high.
PME_N Output: Programmable PME_N output (pin option 2). When asserted low, this
pin signals that a WOL event has occurred.
Config. Mode: The pull-up/pull-down value is latched as NAND Tree# at the
de-assertion of reset. See the Strapping Options section for details.
This pin has a weak pull-up and is an open-drain.
For Interrupt (when active low) and PME functions, this pin requires an external 1.0kΩ
pull-up resistor to VDDIO (digital VDD).
33 TXC/
PME_EN Opd MII Mode: MII Transmit Clock Output.
Config. Mode: The pull-up/pull-down value is latched as PME_EN at the de-assertion of
reset. See the Strapping Options sect ion for details.
Micrel, Inc.
KSZ8091MLX
August
31, 2015 11 Revision 1.2
Pin Description (Continued)
Pin Number Pin Name Type
(2)
Pin Function
34 TXEN I MII Mode: MII Transmit Enable input
35 TXD0 I MII Mode: MII Transmit Data Input[0]
(
4
)
36 TXD1 I MII Mode: MII Transmit Data Input[1]
(4)
37 GND GND Ground.
38 TXD2 I MII Mode: MII Transmit Data Input[2](4)
39 TXD3 I MII Mode: MII Transmit Data Input[3](4)
40 COL/
CONFIG0 Ipd/O MII Mode: MII Collision Detect output
Config. Mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion
of reset. See t he Strapping O ptions section for details.
41 CRS/
CONFIG1 Ipd/O MII Mode: MII Carrier Sense output
Config. Mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion
of reset. See t he Strapping O ptions section for details.
42
LED0/
PME_N1/
NWAYEN
Ipu/O
LED Output: Programmable LED0 Output.
PME_N Output: Programmable PME_N Output (pin option 1)
In this mode, this pin has a weak pull-up, is an ope n-drain, and requires an external
1.0kΩ pull-up resistor to VDDIO (digital VDD).
Config. Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) at the de-
assertion of reset. See the Strapping Options section for details.
The LED0 pin is programmable using Register 1Fh, Bits [5:4], and is defined as follows.
LED Mode = [00]
Link/Activity Pin State LED Definition
No Link High OFF
Link Low ON
Activity Toggle Blinking
LED Mode = [01]
Link Pin State LED Definition
No Link High OFF
Link Low ON
LED Mode = [10], [11] Reserved
Note:
4. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents vali d data from the MAC.
Micrel, Inc.
KSZ8091MLX
August
31, 2015 12 Revision 1.2
Pin Description (Continued)
Pin Number Pin Name Type
(2)
Pin Function
43 LED1/
SPEED Ipu/O
LED Output: Programmable LED1 output
Config. Mode: Latched as Speed (Register 0h, Bit [13]) at the de-assertion of reset.
See the Strapping Options section for details.
The LED1 pin is programmable using Register 1Fh, Bits [5:4], and is defined as follows.
LED Mode = [00]
Speed Pin State LED Definition
10Base-T High OFF
100Base-TX Low ON
LED Mode = [01]
Activity Pin State LED Definition
No activity High OFF
Activity Toggle Blinking
LED Mode = [10], [11]
Reserved
44 TXER Ipd
MII Mode: MII Transmit Error Input.
For EEE mode, this pin is driven by the EEE-MAC to put the KSZ8091MLX transmit into
the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to
KSZ8091M LX and can be left as a no connect.
45 NC - No Connect. This pin is not bonded and can be left floating.
46 NC - No Connect. This pin is not bonded and can be left floating.
47 RST# Ipu Chip Reset (active low).
48 NC - No Connect. This pin is not bonded and can be left floating.
Micrel, Inc.
KSZ8091MLX
August
31, 2015 13 Revision 1.2
Strapping Options
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY
strap-in pins to ensure that the intended values are strapped-in correctly.
Pin Number Pin Name Type
(5)
Pin Function
22
21
20
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
PHYAD[2:0] is latched at the de-assertion of reset and is configurable to any value from
0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can be
assigned as a unique PHY address after pulling the B-CAST_OFF strapping pin high or
writing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:3] are set to 00 by default.
27
41
40
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
CONFIG[2:0] Mode
000 MII (default)
110 MII back-to-back
001–101, 111 Reserved – not used
33 PME_EN Opd
PME output for Wake-On-LAN:
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 16h, Bit [15].
29 ISO Ipd/O
Isolate Mode:
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].
43 SPEED Ipu/O
Speed Mode:
Pull-up (default) = 100Mbps
Pull-down = 10Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as the
speed select, and also is latched into Register 4h (Auto-Negotiation adverti sement ) as
the speed capability support.
23 DUPLEX Ipu/O
Duplex Mode:
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].
42 NWAYEN Ipu/O
Nway Auto-Negotiation Enable:
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
Note:
5. Ipu/O = Input with internal pull -up (see Electrical Characteristics for value) during power-up/reset; out put pin otherwise.
Ipd/O = Input with internal pull-down (see E l ect ri cal Characteristics for value) during power-up/reset; output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Charact eri st ics f or value) and output with int ernal pull-up (s ee Elect rical Charact erist ic s for
value).
Opd = Output with internal pull-down (see Electrical Characteristics for value).
Micrel, Inc.
KSZ8091MLX
August
31, 2015 14 Revision 1.2
Strapping Options (Continued)
Pin Number Pin Name Type
(
5
)
Pin Function
28 B-CAST_OFF Ipd/O
Broadcast Off (for PHY Address 0):
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
32 NAND_Tree# Ipu/Opu
NAND Tree Mode:
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
Micrel, Inc.
KSZ8091MLX
August
31, 2015 15 Revision 1.2
Functional Description: 10Base-T/100Base-TX Transceiver
The KSZ8091MLX is an integrated single 3.3V supp ly Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3
Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two
differential pairs and by integrating the regulator to supply the 1.2V core.
On the co pper media side, the KSZ809 1MLX sup ports 10B ase-T and 1 00Base-T X for transmiss ion and recepti on of data
over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and
correction for straight-through and crossover cables.
On the M AC pr ocess or si de, th e KSZ 809 1MLX of f ers the Media In depend ent Int er fac e (MII) f or direc t conn e ction with MI I
compliant Ethernet MAC processors and switches, respectively.
The MII management bus option gives the MAC processor complete access to the KSZ8091MLX control and status
registers . Add itiona lly, an interrupt pin eliminates the need for the processor to poll for PHY status change.
100Base-TX Transmit
The 100Base-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The c ircuitry starts with a p arallel-to-serial convers ion, whic h converts the MII data from the MAC into a 125MH z serial bit
stream. The data and c ontr ol s tr eam is then conver t ed into 4 B/5 B coding and f ollowed b y a scr am bler. T he serial i zed dat a
is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is set by
an external 6.49kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10Base-T output is also incorporated into the 100Base-TX
transmitter.
100Base-TX Receive
The 100Base-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The rec eiving side s tarts with the equal ization filter to c ompens ate for inter-s ym bol interferenc e (ISI) over the twisted p air
cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
compar isons of incom ing si gnal str ength a gains t som e k nown cable charac ter istic s, then tunes itself for optim ization. T his
is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit
compensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit
converts MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used
to convert t he NRZI signal to NRZ format. This signal is sent through the de-scram bler, then the 4B/5B decoder. Finally,
the NRZ serial data is converted to MII format and provided as the input data to the MAC.
Scrambler/De-Scramble r ( 100Ba se-TX Only)
The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and
baseline wander. The de-scrambler recovers the scrambled signal.
10Base-T Transmit
The 10Base-T drivers are incorporated with the 100Base-TX drivers to allow for transmission using the same magnetic.
The drivers perform internal wave-s haping and pr e-emphasis , and output 1 0Base-T signals with typical am plitude of 2.5V
peak for standard 10Base-T mode and 1.75V peak for energy-efficient 10Base-Te mode. The 10Base-T/10Base-Te
signals have harmonic contents that are at least 27dB below the fundamental frequency when driven by an all-ones
Manchester-encoded signal.
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10Base-T Receive
On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch c ircuit rejec ts signals with levels less than 4 00mV, or with s hort pulse widths, to prevent
noise at the differential line receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit,
the PLL locks onto the incoming signal and the KSZ8091MLX decodes a data frame. The receive clock is kept active
during idle periods between data receptions.
SQE and Jabber Fu nction (10Base-T Only)
In 10Base-T operat ion , a s hor t pu ls e is put o ut o n th e CO L pi n af ter each frame is transmitted. T his SQ E test is ne ede d to
test the 10Base-T transmit/receive path. If transmit enable (TXEN) is high for more than 20ms (jabbering), the 10Base-T
transmitter is disabled and COL is asserted high. If TXEN is then driven low for more than 250ms, the 10Base-T
transmitter is re-enabled and COL is de-asserted (returns to low).
PLL Clock Synthesizer
The KSZ8 091MLX generat es all interna l clocks and all external cl ocks for s ys tem timing f rom an externa l 25MHz cr ystal,
oscillator, or reference clock.
Auto-Negotiation
The KSZ8091MLX conforms to the auto-neg ot iat ion protoc ol , defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise c apabi lities ac ross the UTP link to each other an d then c om pare their own
capabil ities with those the y received from their link partners . The highest speed a nd duplex setting th at is common to the
two link partners is selected as the mode of operation.
The following list shows the speed and duplex operation mode from highest to lowest priority.
• Priorit y 1: 100Base-TX, full-duplex
• Priority 2 : 100Base-TX, half-duplex
• Priorit y 3: 10Base-T, full-duplex
• Priorit y 4: 10Base-T, half-duplex
If auto-negotiation is not supported or the KSZ8091MLX link partner is forced to bypass auto-negotiation, then the
KSZ8091MLX sets its operating mode by observing the signal at its receiver. This is known as parallel detection, which
allows the KSZ8091MLX to establish a link by listening for a fixed signal protocol in the absence of the auto-negotiation
advertisement protocol.
Auto-negotiation is enabled by either hardware pin strapping (NWAYEN, Pin 42) or software (Register 0h, Bit [12]).
By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled by Register 0 h, Bit [12]. If auto-negotiation is dis ab led , th e s pee d is set b y Register 0h, Bit [13] , and the dup lex is
set by Register 0h, Bit [8].
The auto-negotiation link-up process is shown in Figure 1.
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Figure 1. Auto-Negotiation Flow Chart
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MII Data Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision
indication).
• 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
By default, the KSZ8091MLX is configured to MII mode after it is powered up or hardware reset with the following:
• A 25MHz crystal connected to XI, XO (Pins 15, 14), or an external 25MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (Pins 27, 41, 40) set to 000 (default setting).
MII Signal Definition
Table 1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed inf ormation.
Table 1. MII Signal Definition
MII Signal Name Direction
(with respect to PHY,
KSZ8091MLX signal)
Direction
(with respect to MAC) Description
TXC Output Input Transmit Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmi t Data[3:0]
TXER Input Output, or (not implemented) Transmit Error
(KSZ8091MLX implements only the EEE function for
this pin. See “Transmit Error (TXER)” for details.)
RXC Output Input Receive Clock
(2.5MHz for 10Mbps; 25MHz for 100Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data[3:0]
RXER Output Input, or (not required) Receive Error
CRS Output Input Ca rrier Sense
COL Output Input Collis ion D etection
Transmit Clock (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN, TXD[3:0] and TXER.
TXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Transmit Enable (TXEN)
TXEN indic ates th at th e M AC is pres en tin g ni bb les on TX D[3: 0] f or t ransmiss ion. It is as ser ted synchronously wit h the f ir st
nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII. It is negated
before the first TXC following the final nibble of a frame.
TXEN transitions synchronously with respect to TXC.
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Transmit Data[3:0] (TXD[3:0])
When TXEN is asserted, TXD[3:0] are the data nibbles presented by the MAC and accepted by the PHY for transmission.
W hen TX EN is de-as s erted , t he M AC dr iv es T X D[3: 0] to eit her 00 00 f or the idl e s tate (no n-E EE mode) or 000 1 f or the LPI
state (EEE mode).
TXD[3:0] transitions synchronously with respect to TXC.
Transmit Error (TXER)
TXER is implemented only for the EEE function.
For EEE mode, this pin is driven by the EEE-MAC to put the KSZ8091MLX transmit into the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to KSZ8091MLX and can be left as a no
connect.
TXER transitions synchronously with respect to TXC.
Receive Clock (RXC)
RXC provides the timing reference for RXDV, RXD[3:0] and RXER.
• In 10Mbps m ode, RXC is recovered from the line while the carrier is active. W hen the line is idle or th e link is down,
RXC is derived from the PHY’s reference clock.
• In 100Mbps mode, RXC is recovered continuously from the line. If the link is down, RXC is derived from the PHY’s
reference clock.
RXC is 2.5MHz for 10Mbps operation and 25MHz for 100Mbps operation.
Receive Data Valid (RXDV)
RXDV is driven by the PHY to indicate that the PHY is presenting recovered and decoded nibbles on RXD[3:0].
• In 10Mbps mode, RXDV is asserted with the first nibble of the start-of-frame delimiter (SFD), 5D, and remains
asserted until the end of the frame.
• In 100Mbps mode, RXDV is asserted from the first nibble of the preamble to the last nibble of the frame.
RXDV transitions synchronously with respect to RXC.
Receive Data[3:0] (RXD[3:0])
For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY.
W hen RXD V is de-as ser ted , the PH Y dr i ves RX D[ 3:0 ] to eith er 0000 for the idle s tate ( non-EE E mode) or 0001 f or the LPI
state (EEE mode).
RXD[3:0] transitions synchronously with respect to RXC.
Receive Error (RXER)
When RXDV is asserted, RXER is asserted for o ne or more RXC periods to indicate that a symbol error (for example, a
coding err or that a PHY c an det ect that ma y otherwise be undetec table b y the M AC sub-la yer) is detec ted s omewhere in
the frame that is being transferred from the PHY to the MAC.
In EEE mode only, when RXDV is de-asserted, RXER is driven by the PHY to inform the MAC that the KSZ8091MLX
receive is in the LPI state.
RXER transitions synchronously with respect to RXC.
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Carrier Sense (CRS)
CRS is asserted and de-asserted as follows:
• In 10Mbps mode, CRS assertion is based on the reception of valid preambles. CRS de-assertion is based on the
reception of an end-of-frame (EOF) marker.
• In 100Mbps mode, CRS is asserted when a start-of-stream delimiter or /J/K symbol pair is detected. CRS is de-
asserted w hen a n end-of-stream delim iter or /T /R symbol pair is detec te d. Ad dit io nall y, the PM A layer de-ass erts CR S
if IDLE symbols are received without /T/R.
Collision (COL)
COL is asserted in half-duplex mode whenever the transmitter and receiver are simultaneously active on the line. This
informs the MAC that a collision has occurred during its transmission to the PHY.
COL transitions asynchronously with respect to TXC and RXC.
MII Signal Diagram
The KSZ8091MLX MII pin connections to the MAC are shown in Figure 2.
Figure 2. KSZ8091MLX MII Interface
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Back-to-Back Mode – 100Mbps Copper Repeater
Two KSZ8091MLX devices can be connected back-to-back to form a 100Base-TX copper repeater.
Figure 3. KSZ8091MLX to KSZ8091MLX Back-to-Back Copper Repeater
MII Back-to-Back Mode
In MII back -to-back mode, a K SZ8091MLX int erfaces with another KSZ8091 MLX to pro vide a complete 100Mbps copper
repeater solution.
The KSZ8091MLX devices are configured to MII back-to-back mode after power-up or reset with the following:
• Strapping pin CONFIG[2:0] (Pins 27, 41, 40) set to 110
• A common 25MHz reference clock connected to XI (Pin 15) of both KSZ8091MLX devices
• MII signals connected as shown in Table 2
Table 2. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater)
KSZ8091MLX (100Base-TX copper)
[Device 1] KSZ8091MLX (100Base-TX copper)
[Device 2]
Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type
RXDV 27 Output TXEN 34 Input
RXD3 20 Output TXD3 39 Input
RXD2 21 Output TXD2 38 Input
RXD1 22 Output TXD1 36 Input
RXD0 23 Output TXD0 35 Input
TXEN 34 Input RXDV 27 Output
TXD3 39 Input RXD3 20 Output
TXD2 38 Input RXD2 21 Output
TXD1 36 Input RXD1 22 Output
TXD0 35 Input RXD0 23 Output
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MII Management (MIIM) Interface
The KSZ8091MLX supports the IEEE 802.3 MII management interface, also known as the Management Data
Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and
control the state of the KSZ8091MLX. An external device with MIIM capability is used to read the PHY status and/or
configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3
Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows the external controller
to communicate with one or more PHY devices.
• A 32-regis ter address space f or direct acc ess to IEEE -defined re gisters and v endor-specific registers, and fo r indirect
access to MMD addresses and registers. See the Regist er Map section.
As the default, the KSZ8091MLX supports unique PHY Addresses 1 to 7, and broadcast PHY Address 0. The latter is
defined in the IEEE 802.3 Specification, and can be used to read/write to a single KSZ8091MLX device, or write to
multiple KSZ8091MLX devices simultaneously.
PHY Addr ess 0 can optio nall y be d isabled as t he br oadc ast a ddress b y either hard ware pi n stra pping (B-CAST _OF F, P in
28) or software (Register 16h, Bit [9]), and assigned as a unique PHY address.
The PHYAD[2:0] strapping pins are used to assign a unique PHY address between 0 and 7 to each KSZ8091MLX device.
The MIIM interface can operates up to a maximum clock speed of 10MHz MAC clock.
Table 3 shows the MII management frame format for the KSZ8091MLX.
Table 3. MII Management Frame Format for the KSZ8091MLX
Preamble Start of
Frame Read/Write
OP Code PHY Address
Bits [4:0] REG Address
Bits [4:0] TA Data
Bits [15:0] Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
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Interrupt (INTRP)
INTRP (Pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status
update t o the KSZ8091 MLX PHY Regis ter. Bits [15:8 ] of Register 1Bh are the interr upt control bits t o enable an d disable
the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate which
interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.
Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.
The MII management bus option gives the MAC processor complete access to the KSZ8091MLX control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
HP Auto MDI/MDI-X
HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable
between the KSZ8091MLX and its link partner. This feature allows the KSZ8091MLX to use either type of cable to
connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive
pairs from the link partner and assigns transmit and receive pairs to the KSZ8091MLX accordingly.
HP Auto MD I/MDI-X is ena bled b y def ault. It is d isable d by writin g a ‘1’ to R egiste r 1Fh, Bit [13]. MDI and M DI-X m ode is
selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
Table 4 shows how the IEEE 802.3 Standard defines MDI and MDI-X.
Table 4. MDI/MDI-X Pin Definition
MDI MDI-X
RJ-45 Pin Signal RJ-45 Pin Signal
1 TX+ 1 RX+
2 TX− 2 RX−
3 RX+ 3 TX+
6 RX− 6 TX−
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 4 shows a
typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
Figure 4. Typical Straight Cable Connection
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Crossover C able
A cross over cable conn ects an MDI de vice to anoth er MDI device, or an MDI -X device to an other MDI -X devic e. Figure 5
shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
Figure 5. Typical Crossover Cable Connection
Loopback Mode
The KSZ8091MLX supports the following loopback operations to verify analog and/or digital data paths.
• Local (digital) loopback
• Remote (analog) loopback
Local (Di gital) Loopback
This loopback mode checks the MII transmit and receive data paths between the KSZ8091MLX and the external MAC,
and is supported for both speeds (10/100Mbps) at full-duplex.
The loopback data path is shown in Figure 6.
1. The MII MAC transmits frames to the KSZ8091MLX.
2. Frames are wrapped around inside the KSZ8091MLX.
3. The KSZ8091MLX transmits frames back to the MII MAC.
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Figure 6. Local (Digital) Loopback
The following programming action and register settings are used for local loopback mode:
For 10/100Mbps loopbac k,
Set Register 0h,
Bit [14] = 1 / / Enab le loc al loopbac k mode
Bit [13] = 0/1 // Select 10Mbps/100Mbps speed
Bit [12] = 0 // Disable Auto-Negotiation
Bit [8] = 1 // Select full-duplex mode
Remote (Ana log) Loopback
This loopb ack m ode checks the li ne (diff erenti al pairs , trans form er, RJ-45 c onnector, Eth ernet c able) tr ansmit and rece ive
data paths between the KSZ8091MLX and its link partner, and is supported for 100Base-TX full-duplex mode only.
The loopback data path is shown in Figure 7:
1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8091MLX.
2. Frames are wrapped around inside the KSZ8091MLX.
3. The KSZ8091MLX transmits frames back to the Fast Ethernet (100Base-TX) PHY link partner.
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Figure 7. Remote (Analog) Loopback
The following programming steps and register settings are used for remote loopback mode.
1. Set Register 0h,
Bits [13] = 1 // Select 100Mbps speed
Bit [12] = 0 // Disable Auto-Negotiation
Bit [8] = 1 // Select full-duplex mode
Or just auto-negotiate and link up with the link partner at 100Base-TX full-duplex mode.
2. Set Register 1Fh,
Bit [2] = 1 // Enable remote loopback mode
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LinkMD® Cable Diagnostic
The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.
These include open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape
of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides the
approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as a
numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing Register 1Dh, the LinkMD Cable Diagnostic register, in conjunction with Register 1Fh,
the PHY Control 2 Register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as
the cable differential pair for testing.
Usage
The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:
3. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].
4. Start cable diagnostic test by writing a ‘1’ to Register 1D h, bit [15]. This enable bit is self-clearing.
5. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.
6. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is
not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal
generated or a signal from another source.
7. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38. The
distance to the cable fault can be determined by the following formula:
D (distance to cable fault) = 0.38 x (Register 1Dh, bits [8:0])
D (distance to cable fault) is expressed in meters.
Concatenated value of Registers 1Dh bits [8:0] shou ld be converted to decimal before multiplying by 0.38.
The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation
that varies significantly from the norm.
NAND Tree Support
The KSZ8091MLX provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND
tree is a chain of nested NAND gates in which each KSZ8091MLX digital I/O (NAND tree input) pin is an input to one
NAND gate along the chain. At the end of the chain, the CRS pin provides the output for the nested NAND gates.
The NAND tree test process includes:
• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAN D tree input pin low, sequentially, according to the NAND tree pin order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
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Table 5 lists the NAND tree pin order.
Table 5. NAND Tree Test Pin Order for KSZ8091MLX
Pin Number Pin Name NAND Tree Description
18 MDIO Input
19 MDC Input
20 RXD3 Input
21 RXD2 Input
22 RXD1 Input
23 RXD0 Input
27 RXDV Input
28 RXC Input
29 RXER Input
32 INTRP Input
33 TXC Input
34 TXEN Input
35 TXD0 Input
36 TXD1 Input
38 TXD2 Input
39 TXD3 Input
42 LED0 Input
43 LED1 Input
40 COL Input
41 CRS Output
NAND Tree I/O Testing
Use the following procedure to check for faults on the KSZ8091MLX digital I/O pin connections to the board:
1. Enable NAND tree mode using either hardware (NAND_Tree#, Pin 32) or software (Register 16h, Bit [5]).
2. Use board logic to drive all KSZ8091MLX NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8091MLX NAND tree pin order, as follows:
a. Toggle t he firs t pin (MD IO) fr om high to low, a nd verif y that the CR S pin s witc hes f rom high to lo w to in dicat e that
the first pin is connected properly.
b. Leave the first pin (MDIO) low.
c. Toggle the second pin (MDC) from high to low, and verify that the CRS pin switches from low to high to indicate
that the second pin is connected properly.
d. Leave the first pin (MDIO) and the second pin (MDC) low.
e. Toggle the t hird p in ( RX D3) fr om high to l o w, and ver i fy that the CR S p in s witch es f rom high to lo w to indic ate that
the third pin is connected properly.
f. Continue with this sequence until all KSZ8091MLX NAND tree input pins have been toggled.
Each KSZ8091MLX NAND tree input pin mus t cause the CR S output pin to togg le high-to-low or low-to-high to indicate a
good connection. If the CRS pin fails to toggle when the KSZ8091MLX input pin toggles from high to low, the input pin has
a fault.
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Power Management
The KSZ8091MLX incorporates a number of power-management m odes and features that provide methods to consume
less energy. These are discussed in the following sections.
Power-Saving Mode
Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by
writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when Auto-Negotiation mode is enabled and the cable is
disconnected (no link).
In this mode, the KSZ8091MLX shuts down all transceiver blocks, except for the transmitter, energy detect, and PLL
circuits.
By default, power-saving mode is disabled after power-up.
Energy-Detect Power-Down Mode
Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is
unplugged. It is enab led by writing a ‘ 0’ to Regist er 18h, Bit [11], and is in ef fect when Auto-Ne gotiation m ode is enable d
and the cable is disconnected (no link).
EDPD m ode works with th e PLL off (set by writing a ‘1’ to Regist er 10h, Bit [4] to autom atically turn t he PLL off in EDPD
mode) to turn off all KSZ8091MLX transceiver blocks except the transmitter and energy-detect circuits.
Power can be reduced further by extending the time interval between transmissions of link pulses to check for the
presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ8091MLX and its link
partner, when operating in the same low-power state and with Auto MDI/MDI-X disab led, can wake up when the c able is
connected between them.
By default, EDPD mode is disabled after power-up.
Power-Down Mode
Power-d own mode is used to power do wn the K SZ8091MLX d evice when it is n ot in use aft er power-up. It is enabled b y
writing a ‘1’ to Register 0h, Bit [11] .
In this mode, the KSZ8091MLX disables all internal functions except the MII management interface. The KSZ8091MLX
exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.
Slow-Oscillator Mode
Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 15) and select the on-chip slow
oscillator when the K SZ8091MLX device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h, Bit [5].
Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8091MLX device in the lowest power
state, with all internal functions disabled except the MII management interface. To properly exit this mode and return to
normal PHY operation, use the following programming sequence:
1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].
2. Disable power-do wn m ode b y writing a ‘0’ t o Register 0h, Bit [11] .
3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].
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Efficient Ethernet (EEE)
The KSZ809 1MLX implements Energy Eff icient Ethernet (EEE) f or the Media Independe nt Interfac e (MII) as descr ibed in
IEEE Sta ndard 80 2.3az. The Stan dard is defined around an EE E-compliant M AC on the host s ide and an EEE-compliant
link partner on the line side that support special signaling associated with EEE. EEE saves power by keeping the AC
signal on the copper Ethernet cable at approximately 0V peak-to-peak as often as possible during periods of no traffic
activity, while maintaining the link-up status. This is referred to as low-power idle (LPI) mode or state.
During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation
imm ediately, without block age of tr af f ic or los s of packet. This in volv es exit ing LPI m ode an d r etur n ing t o nor mal 100Mb ps
operating mode. Wake-up time is <30µs for 100Base-TX.
The LPI state is controlled independently for transmit and receive paths, allowing the LPI state to be active (enabled) for:
• Transmit cable path only
• Receive cable path only
• Both transmit and receive cable paths
The KSZ8091MLX has the EEE function disabled as the power-up default setting. To enable the EEE function for
100Mbps mode, use the following programming sequence:
1. Enable 100Mbps EEE mode advertisement by writing a ‘1’ to MMD Address 7h, Register 3Ch, Bit [1].
2. Restart Auto-Negotiation by writing a ‘1’ to standard Register 0h, Bit [9].
For standard (non-EEE) 10Base-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are
used to maintain the link during the idle period when there is no traffic activity. To save more power, the KSZ8091MLX
provides the option to enable 10Base-Te mode, which saves additional power by reducing the transmitted signal
amplitude from 2.5V to 1.75V. To enable 10Base-Te mode, write a ‘1’ to standard Register 13h, Bit [4] and write a ‘0’ to
MMD Address 1Ch, Register 4h, Bit [13].
During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approximately
every 20 to 22 milliseconds, a refresh transmission of 200 to 220 microseconds is sent to the link partner. The refresh
transmissions and quiet periods are shown in Figure 8.
Figure 8. LPI Mode (Refresh Transmissions and Quiet Periods)
Transmit Direction Control (MAC-to-PHY)
The KSZ8091MLX enters LPI mode for the transmit direction when its attached EEE-compliant MII MAC de-asserts
TXEN, asserts TXER, and sets TXD[3:0] to 0001. The KSZ8091MLX remains in the LPI transmit state while the MAC
maintains the states of the se signals. W hen the M AC changes an y of the TXEN, TXER, or T X data s ignals f rom their LPI
state values, the KSZ8091MLX exits the LPI transmit state.
The TXC clock is not stopped, because it is sourced from the PHY and is used by the MAC for MII transmit.
Figure 9 shows the LPI transition for MII (100Mbps) transmit.
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Figure 9. LPI Transition – MII (100Mbps) Transmit
Recei ve Direction Control (PHY-to-MAC)
The KSZ80 91M LX enter s L PI mode f or the rec eive d ir ec tion when it rec ei ves th e /P/ c ode bit p attern (Sleep/Refr es h) fr om
its E EE-compliant link partner. It then de-ass erts RXDV, as serts RXER, and drives RX D[3:0] to 000 1. The KSZ 8091MLX
remains in the LPI recei ve state w hile it cont inues to r eceive the r efres h fr om its link partner , so it will conti nue to m aintain
and drive th e LPI output states for the MII receive signals to inform the attached EEE-compliant MII MAC that it is in the
LPI recei ve state. W hen the KSZ80 91MLX receives a non /P/ code bit pattern (n on-refresh), it exits t he LPI rec eive state
and sets the RXDV, RXER, and RX data signals to set a normal frame or normal idle.
The KSZ809 1MLX stops the RX C clock output to the MAC af ter nine or mor e RXC clock cycles have occ urred in the LPI
receive state, to save more power. By default, RXC clock stoppage is enabled. It is disabled by writing a ‘0’ to MMD
Address 3h, Register 0h, Bit [10].
Figure 10 shows the LPI transition for MII (100Mbps) receive.
Figure 10. LPI Transition – MII (100Mbps) Receive
Registers Associated with EEE
The following registers are provided for EEE configuration and management:
• Standard Register 13h − AFE Control 4 (to enable 10Base-Te mode)
• MMD Address 1h, Register 0h − PMA/PMD Control 1 (to enable LPI)
• MMD Address 1h, Register 1h − PMA/PMD Status 1 (for LPI status)
• MMD Address 3h, Register 0h − EEE PCS Control 1 (to stop RXC clock)
• MMD Address 7h, Register 3Ch − EEE Ad vert is ement
• MMD Address 7h, Register 3Dh − EEE Li nk Partner Advertis ement
• MMD Address 1Ch, Register 4h − DSP 10Base-T/10Base-Te Control
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Wake-On-LAN
Wake-On-LAN (W OL) is normall y a MAC-bas ed func tion to wake up a hos t system (for exam ple, an Etherne t end device,
such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet
(commonly referred to as the “magic packet”) that is sent by the remote link partner. The KSZ8091MLX can perform the
same W OL funct ion if the MAC addr ess of its assoc iated MAC dev ice is entere d into the KSZ 8091MLX PHY Registers for
magic-packet detection. When the KSZ8091MLX detects the magic packet, it wakes up the host by driving its power
management event (PME) output pin low.
By defau lt, the W OL f unction is d isabled. It is ena bled b y setting th e enabl ing b it and conf iguring t he assoc iated reg isters
for the selected PME wake-up detection method.
The KSZ8091MLX provides three methods to trigger a PME wake-up:
1. Magic-packet detection
2. Customized-packet detection
3. Link status change detection
Magic-Packet Detection
The m agic packet’s fram e form at starts with 6 b ytes of 0x FFh and is followed by 16 r epetitions of the MAC address of its
associated MAC device (local MAC device).
When the magic packet is detected from its link partner, the KSZ8091MLX asserts its PME output pin low.
The following MMD Address 1Fh registers are provided for magic-packet detection:
• Magic-packet detection is enab led b y writing a ‘1’ to MMD Addres s 1Fh, Reg ister 0h, Bit [6]
• The MAC address (for the local MAC device) is written to and stored in MMD Address 1Fh, Registers 19h – 1Bh
The KSZ8091MLX does not generate the magic packet. The magic packet must be provided by the external system.
Customized-Packet Detection
The c ustom ized pac ket has ass ociated r egister /bit m asks to s elect which b yte, or bytes, of the firs t 64 b ytes of the p ack et
to use in the CRC calculation. Af ter the KSZ8091 MLX receives th e packet fr om its link partner, the selected bytes for the
received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that was
previously written to and stored in the KSZ8091MLX PHY Registers. If there is a match, the KSZ8091MLX asserts its
PME output pin low.
Four cus tomized pac kets are provided t o suppor t four t ypes of wak e-up scenar ios. A ded icated s et of regis ters is used to
configure and enable each customized packet.
The following MMD Registers are provided for customized-packet detection:
• Each of the four customized packets is enabled via MMD Address 1Fh, Register 0h,
− Bit [2] // For customized packets, type 0
− Bit [3] // For customized packets, type 1
− Bit [4] // For customized packets, type 2
− Bit [5] // For customized packets, type 3
• Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:
− MMD Address 1Fh, Registers 1h – 4h // For customized packets, type 0
− MMD Address 1Fh, Registers 7h – Ah // For customized packets, type 1
− MMD Address 1Fh, Registers Dh – 10h // For customized packets, type 2
− MMD Address 1Fh, Registers 13h – 16h // For customized packets, type 3
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• 32-bit expected CRCs are written to and stored in:
− MMD Address 1Fh, Registers 5h – 6h // For customized packets, type 0
− MMD Address 1Fh, Registers Bh – Ch // For customized packets, type 1
− MMD Address 1Fh, Registers 11h – 12h // For customized packets, type 2
− MMD Address 1Fh, Registers 17h – 18h // For customized packets, type 3
Link Sta tu s Change Detection
If link status c hange d etec t i on is enabled, th e K SZ80 9 1MLX as s ert s its PME out p ut pin low when ev er t here i s a link status
change, using the following MMD Address 1Fh register bits and their enabled (1) or disabled (0) settings:
• MMD Address 1Fh, Register 0h, Bit [0] // For link-up detection
• MMD Address 1Fh, Register 0h, Bit [1] // For link-down detection
The PME output signal is available on either INTRP/PME_N2 (Pin 32) or LED0/PME_N1 (Pin 42), and is enabled using
standard Register 16h, Bit [15]. MMD Address 1Fh, Register 0h, Bits [15:14] defines and selects the output functions for
Pins 32 and 42.
The PME out put is ac tive low and r equires a 1k Ω pull-up to the VDDIO sup pl y. When asserted , the PME o utput is c leared
by disabling the register bit that enabled the PME trigger source (magic packet, customized packet, link status change).
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Reference Circuit for Power and Ground Connections
The KSZ80 91MLX is a sin gle 3.3 V supply device with a built-in reg ulator to sup ply the 1.2V core . The power and gr ound
connections are shown in Figure 11 and Table 6 for 3.3V VDDIO.
Figure 11. KSZ8091MLX Power and Ground Connections
Table 6. KSZ8091MLX Power Pin Description
Power Pin Pin Number Description
VDD_1.2 4 Connect with Pin 31 by power trace or plane. Decouple with 2.2µF and 0.1µF c apa citor s to gr ound .
VDDA_3.3 7 Connect to board’s 3.3V sup pl y through a ferrite bead . Decouple with 22µF and 0.1µF capacitors to
ground.
VDDIO 25 Connect to board’s 3.3V supply for 3.3V VDDIO. Decouple with 22µF and 0.1µF capacitors to
ground.
VDD_1.2 31 Connect with Pin 4 by power trace or plane. Decouple with 0.1µF capacitor to ground.
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Typical Current/Power Consumption
Table 7, Table 8, Table 9 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O
(VDDIO) power pins, as well as typical values for power consumption by the KSZ8091MLX device for the indicated
nominal op erating voltag es. These cur rent and power consum ption values inc lud e the transmit driver c urrent and on-chip
regulator current for the 1.2V core.
Transceiver (3.3V), Digital I/Os (3.3V)
Table 7. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)
Condition 3.3V Transceiver
(VDDA_3.3) 3.3V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffic) 34 12 152
100Base-TX Full -duplex @ 100% utilization 34 13 155
10Base-T Link-up ( no traffic) 14 11 82.5
10Base-T Ful l-duplex @ 100% utilization 30 11 135
EEE 100Mbps Link-up mode
(transmit and receive in LPI state wi th no traffic) 13 10 75.9
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 10 75.9
EDPD mode (Reg. 18h, Bit [11] = 0) 10 10 66.0
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 3.77 1.54 17.5
Software power-down m ode (Reg. 0h, Bit [11] =1) 2.59 1.51 13.5
Software power-down m ode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.36 0.45 5.97
Transceiver (3.3V), Digital I/Os (2.5V)
Table 8. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)
Condition 3.3V Transceiver
(VDDA_3.3) 2.5V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffic) 34 11 140
100Base-TX Full -duplex @ 100% utilization 34 12 142
10Base-T Link-up ( no traffic) 15 10 74.5
10Base-T Ful l-duplex @ 100% utilization 27 10 114
EEE 100Mbps Link-up mode
(transmit and receive in LPI state wi th no traffic) 13 10 67.9
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 10 67.9
EDPD mode (Reg. 18h, Bit [11] = 0) 11 10 61.3
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 3.55 1.35 15.1
Software power-down m ode (Reg. 0h, Bit [11] =1) 2.29 1.34 10.9
Software power-down m ode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.15 0.29 4.52
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Transceiver (3.3V), Digital I/Os (1.8V)
Table 9. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V)
Condition 3.3V Transceiver
(VDDA_3.3) 1 .8 V Digital I/Os
(VDDIO) Total Chip Power
mA mA mW
100Base-TX Link-up (no traffic) 34 11 132
100Base-TX Full -duplex @ 100% utilization 34 12 134
10Base-T Link-up ( no traffic) 15 9.0 65.7
10Base-T Ful l-duplex @ 100% utilization 27 9.0 105
EEE 100Mbps Link-up mode
(transmit and receive in LPI state wi th no traffic) 13 9.0 59.1
Power-saving mode (Reg. 1Fh, Bit [10] = 1) 13 9.0 59.1
EDPD mode (Reg. 18h, Bit [11] = 0) 11 9.0 52.5
EDPD mode (Reg. 18h, Bit [11] = 0) and
PLL off (Reg. 10h, Bit [4] = 1) 4.05 1.21 15.5
Software power-down m ode (Reg. 0h, Bit [11] =1) 2.79 1.21 11.4
Software power-down m ode (Reg. 0h, Bit [11] =1) and
slow-oscillator mode (Reg. 11h, Bit [5] =1) 1.65 0.19 5.79
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Register Map
The register space within the KSZ8091MLX consists of two distinct areas.
• Standard registers // Direct register access
• MDIO manageable device (MMD) registers // Indirect register access
The KSZ8091MLX supports the following standard registers:
Table 10. Standard Registers Supported by KSZ8091MLX
Register Number (Hex)
Description
IEEE-Defined Registers
0h Basic Control
1h Basic Status
2h PHY Identifier 1
3h PHY Identifier 2
4h Auto-Negotiation Advertisement
5h Auto-Negotiation Lin k Part ner A bility
6h Auto-Negotiation Expansion
7h Auto-Negotiation Next Page
8h Auto-Negotiation Link Partner Next Page Ability
9h – Ch Reserved
Dh MMD Access – Control
Eh MMD Access – Register/Data
Fh Reserved
Vendor-Specific Registers
10h Digital Reserved Control
11h AFE Control 1
12h Reserved
13h AFE Control 4
14h Reserved
15h RXER Counter
16h Operation Mode Strap Override
17h Operation Mode Strap Status
18h Expanded Control
19h – 1Ah Reserved
1Bh Interrupt Control/Status
1Ch Reserved
1Dh LinkMD Cable Diagnostic
1Eh PHY Control 1
1Fh PHY Control 2
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The KSZ80 91M LX s upport s the f ollo win g MM D de vice addres s es and the ir as s oci ated r e gist er a ddr es ses , whic h mak e up
the indirect MMD registers:
Table 11. MMD Registers Supported by KSZ8091MLX
Device Address (Hex) Register Address (Hex) Description
1h 0h PMA/P MD Control 1
1h PMA/PMD Status 1
3h 0h EEE PCS Control 1
7h 3Ch EEE Advertisement
3Dh EEE Link Partner Advertisement
1Ch 4h DSP 10Base-T/10Base-Te Control
1Fh
0h Wake-On-LAN – Control
1h Wake-On-LAN – Customized Packet, Type 0, Mask 0
2h Wake-On-LAN – Customized Packet, Type 0, Mask 1
3h Wake-On-LAN – Customized Packet, Type 0, Mask 2
4h Wake-On-LAN – Customized Packet, Type 0, Mask 3
5h Wake-On-LAN – Customized Pack et, Ty pe 0, Expected CRC 0
6h Wake-On-LAN – Customized Packet, Type 0, Expec ted CRC 1
7h Wake-On-LAN – Customized Packet, Type 1, Mask 0
8h Wake-On-LAN – Customized Packet, Type 1, Mask 1
9h Wake-On-LAN – Customized Packet, Type 1, Mask 2
Ah Wake-On-LAN – Customized Packet, Type 1, Mas k 3
Bh Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
Ch Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
Dh Wake-On-LAN – Customized Packet, Type 2, Mask 0
Eh Wake-On-LAN – Customized Packet, Type 2, Mask 1
Fh Wake-On-LAN – Customized Packet, Type 2, Mask 2
10h Wake-On-LAN – Customized Packet, Type 2, Mask 3
11h Wake-On-LAN – Customized Packet, Type 2, Expec ted CRC 0
12h Wake-On-LAN – Customized Packet, Type 2, Expec ted CRC 1
13h Wake-On-LAN – Customized Packet, Type 3, Mask 0
14h Wake-On-LAN – Customized Packet, Type 3, Mask 1
15h Wake-On-LAN – Customized Packet, Type 3, Mask 2
16h Wake-On-LAN – Customized Packet, Type 3, Mask 3
17h Wake-On-LAN – Customized Packet, Type 3, Expec ted CRC 0
18h Wake-On-LAN – Customized Packet, Type 3, Expec ted CRC 1
19h Wake-On-LAN – Magic Packet, MAC-DA-0
1Ah Wake-On-LAN – Magic Packet, MAC-DA-1
1Bh Wake-On-LAN – Magic Packet, MAC-DA-2
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Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the
IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.
IEEE-Defin ed R egist e rs – Descriptions
Address Name Description Mode
(6)
Default
Register 0h – Basic Control
0.15 Reset 1 = Software reset
0 = Normal opera t ion
This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
0.14 Loopback 1 = Loopback mode
0 = Normal operation RW 0
0.13 Speed Select
1 = 100Mbps
0 = 10Mbps
This bit is ignored if Auto-Negotiation is enabled
(Register 0.12 = 1).
RW Set by the SPEED strapping pin.
See the Strapping Options section
for details.
0.12 Auto-
Negotiation
Enable
1 = Enable Auto-Negotiation process
0 = Disable Auto-Negotiation p roce ss
If enabled, the Auto-Negotiation result overrides
the settings in Registers 0.13 and 0.8.
RW
Set by the NWAYEN strapping
pin.
See the Strapping Options section
for details.
0.11 Power-Down
1 = Power-down mode
0 = Normal operation
If software reset (Register 0.15) is used to exit
power-down m ode (Register 0.11 = 1), two
software reset writes (Register 0.15 = 1) are
required. The first write clears power-down
mode; the second write resets the chip and re-
latches the pin strapping pin values.
RW 0
0.10 Isolate 1 = Electrical isol ation of PHY from MII
0 = Normal operation RW Set by the ISO strapping pin.
See the Strapping Options section
for details.
0.9 Restart Auto-
Negotiation
1 = Restart Auto-Negotiation process
0 = Normal operation.
This bit is self-cleared after a ‘1’ is written to it. RW/SC 0
0.8 Duplex Mode 1 = Full-duplex
0 = Half-duplex RW
The inverse of the DUPLEX
strapping pin value.
See the Strapping Options section
for details.
0.7 Collision Test 1 = Enable COL test
0 = Disable COL test RW 0
0.6:0 Reserved Reserved RO 000_0000
Note:
6. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
LH = Latch high.
LL = Latch low.
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IEEE-Defin ed R egist e rs – Descriptions (Continued)
Address Name Description Mode
(6)
Default
Register 1h – Basic Status
1.15 100Base-T4 1 = T4 capable
0 = Not T4 capable RO 0
1.14 100Base-TX
Full-Duplex 1 = Capable of 100Mbps full-duplex
0 = Not capable of 100Mbps full-duplex RO 1
1.13 100Base-TX
Half-Duplex 1 = Capable of 100Mbps half-duplex
0 = Not capable of 100Mbps half-duplex RO 1
1.12 10Base-T
Full-Duplex 1 = Capable of 10Mbps full-duplex
0 = Not capable of 10Mbps full-duplex RO 1
1.11 10Base-T
Half-Duplex 1 = Capable of 10Mbps half-duplex
0 = Not capable of 10Mbps half-duplex RO 1
1.10:7 Reserved Reserved RO 000_0
1.6 No Preamble 1 = Preamble suppression
0 = Normal preamble RO 1
1.5 Auto-
Negotiation
Complete
1 = Auto-negotiation process completed
0 = Auto-negotiation process not completed RO 0
1.4 Remote Fault 1 = Remote fault
0 = No remote fault RO/LH 0
1.3 Auto-
Negotiation
Ability
1 = Can perform auto-negotiation
0 = Cannot perform auto-negotiation RO 1
1.2 Link Status 1 = Link is up
0 = Link is down RO/LL 0
1.1 Jabber Detect 1 = Jabber detected
0 = Jabber not detected (default is low) RO/LH 0
1.0 Extended
Capability 1 = Supports extended capability registers RO 1
Register 2h – PHY Identifier 1
2.15:0 PHY ID
Number
Assigned to the 3rd through 18th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0022h
Register 3h – PHY Identifier 2
3.15:10 PHY ID
Number
Assigned to the 19th through 24th bits of the
Organizationally Unique Identifier (OUI).
KENDIN Communication’s OUI is 0010A1
(hex).
RO 0001_01
3.9:4 Model Number Six-bit manufacturer’s model number RO 01_0110
3.3:0 Revision
Number Four-bit manufacturer’s revision number RO Indicates silicon revision
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IEEE-Defin ed R egist e rs – Descriptions (Continued)
Address Name Description Mode
(6)
Default
Register 4h – Auto-Negotiation Advertisement
4.15 Next Page 1 = Next page capable
0 = No next page capability RW 0
4.14 Reserved Reserved RO 0
4.13 Remote Fault 1 = Remote fault supported
0 = No remote fault RW 0
4.12 Reserved Reserved RO 0
4.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RW 00
4.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
4.8 100Base-TX
Full-Duplex 1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability RW Set by the SPEED strapping pin.
See the Strapping Options section
for details.
4.7 100Base-TX
Half-Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability RW Set by the SPEED strapping pin.
See the Strapping Options section
for details.
4.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability RW 1
4.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RW 1
4.4:0 Selector Field [00001] = IEEE 802.3 RW 0_0001
Register 5h – Auto-Negotiation Link Partner Ability
5.15 Next Page 1 = Next page capable
0 = No next page capability RO 0
5.14 Acknowledge 1 = Link code word received from partner
0 = Link code word not yet received RO 0
5.13 Remote Fault 1 = Remote fault detected
0 = No remote fault RO 0
5.12 Reserved Reserved RO 0
5.11:10 Pause
[00] = No pause
[10] = Asymmetric pause
[01] = Symmetric pause
[11] = Asymmetric and symmetric pause
RO 00
5.9 100Base-T4 1 = T4 capable
0 = No T4 capability RO 0
5.8 100Base-TX
Full-Duplex 1 = 100Mbps full-duplex capable
0 = No 100Mbps full-duplex capability RO 0
5.7 100Base-TX
Half-Duplex 1 = 100Mbps half-duplex capable
0 = No 100Mbps half-duplex capability RO 0
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IEEE-Defin ed R egist e rs – Descriptions (Continued)
Address Name Description Mode
(6)
Default
5.6 10Base-T
Full-Duplex 1 = 10Mbps full-duplex capable
0 = No 10Mbps full-duplex capability RO 0
5.5 10Base-T
Half-Duplex 1 = 10Mbps half-duplex capable
0 = No 10Mbps half-duplex capability RO 0
5.4:0 Selector Field [00001] = IEEE 802.3 RO 0_0001
Register 6h – Auto-Negotiation Expansion
6.15:5 Reserved Reserved RO 0000_0000_000
6.4 Parallel
Detection Fault 1 = Fault detected by parallel detection
0 = No fault detected by parallel detection RO/LH 0
6.3 Link Partner
Next Page
Able
1 = Link partner has next page capability
0 = Link partner does not have next page
capability RO 0
6.2 Next Page
Able
1 = Local device has next page capability
0 = Local device does not have next page
capability RO 1
6.1 Page Received 1 = New page received
0 = New page not received yet RO/LH 0
6.0
Link Partner
Auto-
Negotiation
Able
1 = Link partner has auto-negotiation capability
0 = Link partner does not have auto-negotiation
capability RO 0
Register 7h – Auto-Negotiation Next Page
7.15 Next Page 1 = Additional next pages will follow
0 = Last page RW 0
7.14 Reserved Reserved RO 0
7.13 Message Page 1 = Message page
0 = Unforma t ted pag e RW 1
7.12 Acknowledge2 1 = Will comply with message
0 = Cannot comply with message RW 0
7.11 Toggle
1 = Previous value of the transmitted link code
word equal to logic 0
0 = Previous value of the transmitted link code
word equal to logic 1
RO 0
7.10:0 Mes sage Field 11-bit wide field to enc ode 2048 messages RW 000_0000_0001
Register 8h – Auto-Negotiation Link Partner Next Page Ability
8.15 Next Page 1 = Additional next pages will follow
0 = Last page RO 0
8.14 Acknowledge 1 = Successful receipt of link word
0 = No successful receipt of link word RO 0
8.13 Message Page 1 = Message page
0 = Unforma t ted pag e RO 0
8.12 Acknowledge2 1 = Can act on the informat ion
0 = Cannot act on the information RO 0
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IEEE-Defin ed R egist e rs – Descriptions (Continued)
Address Name Description Mode(6) Default
8.11 Toggle
1 = Previous value of transmitted link code
word equal to logic 0
0 = Previous value of transmitted link code
word equal to logic 1
RO 0
8.10:0 Mes sage Field 11-bit wide field to enc ode 2048 messages RO 000_0000_0000
Registe r Dh – MMD Access – Control
D.15:14 MMD –
Operation
Mode
For the selected MMD Device Address (Bits
[4:0] of this register), these two bits select one
of the following register or data operations and
the usage for MMD Access – Register/Data
(Reg. Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RW 00
D.13:5 Reserved Reserved RW 00_0000_000
D.4:0 MMD –
Device Address These five bits set the MMD device address. RW 0_0000
Register Eh – MMD Access – Register/Data
E.15:0 MMD –
Register/Data
For the selected MMD Device Address (Reg.
Dh, Bits [4:0]),
When Reg. Dh, Bits [15:14] = 00, this register
contains the read/write register address for the
MMD Device Address.
Otherwise, this register contains the read/write
data value for the MMD Device Address and its
selected regi s ter address.
See also Reg. Dh, Bits [15:14], for descriptions
of post increment reads and writes of this
register for data operation.
RW 0000_0000_0000_0000
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Vendor-S pecific Registers – Descriptions
Address Name Description Mode
(7)
Default
Register 10h – Digital Reserved Control
10.15:5 Reserved Reserved RW 0000_0000_000
10.4 PLL Off
1 = Turn PLL off automatically in EDPD mode
0 = Keep PLL on in EDPD mode.
See also Register 18h, Bit [11] for EDPD mode
RW 0
10.3:0 Reserved Reserved RW 0000
Register 11h – AFE Control 1
11.15:6 Reserved Reserved RW 0000_0000_00
11.5 Slow-Oscillator
Mode Enable
Slow-oscillator mode is used to dis connect the
input reference crystal/clock on the XI pin and
select the on-chip slow oscillator when the
KSZ8091M LX device is not in use after power-
up.
1 = Enable
0 = Disable
This bit automatically sets software power-down
to the analog side when enabled.
RW 0
11.4:0 Reserved Reserved RW 0_0000
Register 13h – AFE Control 4
13.15:5 Reserved Reserved RW 0000_0000_000
13.4 10Base-Te
Mode
1 = EEE 10Base-Te (1.75V TX amplitude) and
als o set MMD Address 1Ch, Register 4h,
Bit [13] to ‘0’.
0 = Standard 10Base-T (2.5V TX amplitude)
and also set MMD Address 1Ch,
Register 4h, Bit [13] to ‘1’.
RW 0
13.3:0 Reserved Reserved RW 0000
Register 15h – RXER Counter
15.15:0 RXER Counter Receive error counter for symbol error frames RO/SC 0000h
Register 16h – Operation Mode Strap Override
16.15 PME Enable
PME for Wake-on-LAN
1 = Enable
0 = Disable
This bit works in conjunction with MMD Address
1Fh, Reg. 0h, Bits [15:14] to define the output
for Pins 32 and 42.
RW Set by the PME_EN strapping pin.
See the Strapping Options section
for details.
16.14:11 Reserved Reserved RW 000_0
16.10 Reserved Reserved RO 0
16.9 B-CAST_OFF
Override 1 = Override strap-in for B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RW 0
16.8 Reserved Reserved RW 0
Note:
7. RW = Read/Write.
RO = Read only.
SC = Self-cleared.
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Vendor-S pecific Registers – Descriptions (Continued)
Address Name Description Mode
(7)
Default
16.7 MII B-to-B
Override 1 = Override strap-in for MII back-to-back
mode (also set Bit 0 of this register to ‘1’) RW 0
16.6 Reserved Reserved RW 0
16.5 NAND Tree
Override 1 = Override strap-in for NAND tree mode RW 0
16.4:1 Reserved Reserved RW 0_000
16.0 MII Override 1 = Override strap-in for MII mode RW 1
Register 17h – Operation Mode Strap Status
17.15:13 PHYAD[2:0]
Strap-In Status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
RO
17.12:10 Reserved Reserved RO
17.9 B-CAST_OFF
Strap-In Status 1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-broadcast. RO
17.8 Reserved Reserved RO
17.7 MII B-to-B
Strap-In Status 1 = Strap to MII back-to-back mode. RO
17.6 Reserved Reserved RO
17.5 NAND Tree
Strap-In Status 1 = Strap to NAND tree mode RO
17.4:1 Reserved Reserved RO
17.0 MII Strap-In
Status 1 = Strap to MII mode RO
Register 18h – Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11 EDPD
Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL off.
RW 1
18.10 100Base-TX
Latency
1 = MII output is rand om late n cy
0 = MII output is fixed latency
For both settings, all bytes of received preamble
are passed to the MII output.
RW 0
18.9:7 Reserved Reserved RW 00_0
18.6 10Base-T
Preamble
Restore
1 = Restore received preamble to MII output
0 = Remove all seven bytes of preamble before
sending frame (starting with SFD) to MII
output
RW 0
18.5:0 Reserved Reserved RW 00_0001
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Vendor-S pecific Registers – Descriptions (Continued)
Address Name Description Mode
(7)
Default
Register 1Bh – Interrupt Control/Status
1B.15 Jabber
Interrupt
Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt RW 0
1B.14 Receive Error
Interrupt
Enable
1 = Enable receive error interrupt
0 = Disable receive error interrupt RW 0
1B.13 Page Received
Interrupt
Enable
1 = Enable page received interrupt
0 = Disable page received interrupt RW 0
1B.12 Parallel Detect
Fault Interrupt
Enable
1 = Enable parallel detect fault interrupt
0 = Disable parallel detect fault interrupt RW 0
1B.11
Link Partner
Acknowledge
Interrupt
Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt RW 0
1B.10 Link-Down
Interrupt
Enable
1= Enable link-down interrupt
0 = Disable link-down interrupt RW 0
1B.9 Remote Fault
Interrupt
Enable
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt RW 0
1B.8 Link-Up
Interrupt
Enable
1 = Enable link-up interrupt
0 = Disable link-up interrupt RW 0
1B.7 Jabber
Interrupt 1 = Jabber occurred
0 = Jabber did not occur RO/SC 0
1B.6 Receive Error
Interrupt 1 = Receive error occurred
0 = Receive error did not occur RO/SC 0
1B.5 Page Receive
Interrupt 1 = Page receive occurred
0 = Page receive did not occur RO/SC 0
1B.4 Parallel Detect
Fault Interrupt 1 = Parallel d etect fault occurred
0 = Parallel detect fault did not occur RO/SC 0
1B.3 Link Partner
Acknowledge
Interrupt
1 = Link partner acknowledge occurred
0 = Link partner acknowledge did not occur RO/SC 0
1B.2 Link-Down
Interrupt 1 = Link-down occurred
0 = Link-down did not occur RO/SC 0
1B.1 Remote Fault
Interrupt 1 = Remote fault occurred
0 = Remote fault did not occur RO/SC 0
1B.0 Link-Up
Interrupt 1 = Link-up occurred
0 = Link-up did not occur RO/SC 0
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Vendor-S pecific Registers – Descriptions (Continued)
Address Name Description Mode
(7)
Default
Register 1Dh – LinkMD Cable Diagnostic
1D.15 Cable
Diagnostic
Test Enable
1 = Enable cable diagnostic test. After test has
completed, this bit is self-cleared.
0 = Indicates cable diagnostic test (if enabled)
has completed and the stat us i nfor m atio n is
valid for read.
RW/SC 0
1D.14:13 Cable
Diagnostic
Test Result
[00] = Normal condition
[01] = Open condition has been detected in
cable
[10] = Short condition ha s been detected in
cable
[11] = Cable diagnostic test has failed
RO 00
1D.12 Short Cable
Short Indicator 1 = A short cable (<10 meter) short condition
has been detected by LinkMD RO 0
1D.11:9 Reserved Reserved RW 000
1D.8:0 Cable Fault
Counter Distance to fault RO 0_0000_0000
Register 1Eh – PHY Control 1
1E.15:10 Reserved Reserved RO 0000_00
1E.9 Enable Pause
(Flow Control) 1 = Flow control capable
0 = No flow c ontrol capability RO 0
1E.8 Link Status 1 = Link is up
0 = Link is down RO 0
1E.7 Polarity Status 1 = Polarity is reversed
0 = Polarity is not reversed RO
1E.6 Reserved Reserved RO 0
1E.5 MDI/MDI-X
State 1 = MDI-X
0 = MDI RO
1E.4 Energy Detect 1 = Signal present on receive differential pair
0 = No signal detected on receive differential
pair RO 0
1E.3 PHY Is o l a te 1 = PHY in isolate mode
0 = PHY in normal operation RW 0
1E.2:0 Operation
Mode
Indication
[000] = Still in auto-negotiation
[001] = 10Base-T half-duplex
[010] = 100Base-TX half-duplex
[011] = Reserved
[100] = Reserved
[101] = 10Base-T full-duplex
[110] = 100Base-TX full-duplex
[111] = Reserved
RO 000
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31, 2015 48 Revision 1.2
Vendor-S pecific Registers – Descriptions (Continued)
Address Name Description Mode
(7)
Default
Register 1Fh – PHY Control 2
1F.15 HP_MDIX 1 = HP Auto MDI/MDI-X mode
0 = Micrel Auto MDI/MDI-X mode RW 1
1F.14 MDI/MDI-X
Select
When A uto MDI/MDI-X is disabled,
1 = MDI-X mode:
Transmit on RXP,RXM (pins 10, 9) and
Receive on TXP,TXM (pins 12, 11)
0 = MDI mode:
Transmit on TXP,TXM (pins 12, 11) and
Receive on RXP,RXM (pins 10, 9)
RW 0
1F.13 Pair Swap
Disable 1 = Disable Auto MDI/MDI-X
0 = Enable Auto MDI/MDI-X RW 0
1F.12 Reserved Reserved RW 0
1F.11 Force Lin k
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allows
the transmitter to send a pattern even if there is
no link.
RW 0
1F.10 Power Saving 1 = Enable power saving
0 = Disable power saving RW 0
1F.9 Interrupt Level 1 = Interrupt pin active high
0 = Interrupt pin active low RW 0
1F.8 Enable Jabber 1 = Enable jabber coun ter
0 = Disable jabber counter RW 1
1F.7:6 Reserved Reserved RW 00
1F.5:4 LED Mode
[00] = LED1: Speed
LED0: Link/Activity
[01] = LED1: Activity
LED0: Link
[10], [11] = Reserved
RW 00
1F.3 Disable
Transmitter 1 = Disable transmitter
0 = Enable transmitter RW 0
1F.2 Remote
Loopback 1 = Remote (analog) loopback is enabled
0 = Normal mode RW 0
1F.1 Enable SQE
Test 1 = Enable SQE test
0 = Disable SQE test RW 0
1F.0 Disable Data
Scrambling 1 = Disable scrambler
0 = Enable scrambler RW 0
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MMD Registers
MMD registers provide indirect read/write access to up to 32 MMD Device Addresses with each device supporting up to
65,536 16-b it reg ist ers , as def ined i n C lause 22 of the IEE E 802. 3 Specificatio n. The KSZ8091MLX , ho w ever , us es onl y a
small fraction of the available registers. See the Register Map section for a list of supported MMD device addresses and
their associated register addresses.
The following two standard registers serve as the portal registers to access the indirect MMD registers.
• Standard Register Dh – MMD Access – Control
• Standard Register Eh – MMD Access – Register/Data
Table 12. Portal Registers (Access to Indirect MMD Registers)
Address Name Description Mode Default
Registe r Dh – MMD Access – Control
D.15:14 MMD –
Operation
Mode
For the selected MMD Device Address (Bits
[4:0] of this register), these two bits select one
of the following register or data operations and
the usage for MMD Access – Register/Data
(Reg. Eh).
00 = Register
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
RW 00
D.13:5 Reserved Reserved RW 00_0000_000
D.4:0 MMD –
Device
Address These five bits set the MMD device address. RW 0_0000
Register Eh – MMD Access – Register/Data
E.15:0 MMD –
Register/Data
For the selected MMD Device Address (Reg.
Dh, Bits [4:0]),
When Reg. Dh, Bits [15:14] = 00, this register
contains the read/write register address for the
MMD Device Address.
Otherwise, this register contains the read/write
data value for the MMD Device Address and its
selected regi s ter address.
See also Register Dh, Bits [15:14] descriptions
for post increment reads and writes of this
register for data operation.
RW 0000_0000_0000_0000
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Examples:
MMD Register Write
Write MMD – Device Address 1Fh, Register 0h = 0001h to enable link-up detection to trigger PME for WOL.
1. Write Register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.
2. Write Register Eh with 0000h // Select Register 0h of MMD – Device Address 1Fh.
3. Write Register Dh with 401Fh // Select register data for MMD – Device Address 1Fh, Register 0h.
4. Write Register Eh with 0001h // Write value 0001h to MMD – Device Address 1Fh, Register 0h.
MMD Register Read
Read MMD – Device Address 1Fh, Register 19h – 1Bh for the magic packet’s MAC address
1. Write Register Dh with 001Fh // Set up register address for MMD – Device Address 1Fh.
2. Write Register Eh with 0019h // Select Register 19h of MMD – Device Address 1Fh.
3. Write Register Dh with 801Fh // Select register data for MMD – Device Address 1Fh, Register 19h
// with post increments
4. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 19h.
5. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 1Ah.
6. Read Register Eh // Read data in MMD – Device Address 1Fh, Register 1Bh.
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MMD Registers – Descriptions
Address Name Description Mode
(8)
Default
MMD Address 1h, Register 0h – PMA/PMD Control 1
1.0.15:13 Reserved Reserved RW 000
1.0.12 LPI enable Lower Power Idle enable RW 0
1.0.11:0 Reserved Reserved RW 0000_0000_0000
MMD Address 1h, Register 1h – PMA/PMD Status 1
1.1.15:9 Reserved Reserved RO 0000_000
1.1.8 LPI State
Entered 1 = PMA/PMD has entered LPI state
0 = PMA/PMD has not entered LPI state RO/LH 0
1.1.7:4 Reserved Reserved RO 0000
1.1.3 LPI State
Indication 1 = PMA/PMD is currently in LPI state
0 = PMA/PMD is currently not in LPI state RO 0
1.1.2:0 Reserved Reserved RO 000
MMD Address 3h, Register 0h – EEE PCS Control 1
3.0.15:12 Reserved Reserved RO 0000
3.0.11 Reserved Reserved RW 1
3.0.10 100Base-TX
RXC Clock
Stoppable
During receive lower-power idle mode,
1 = RXC clock is stoppable for 100Base-TX
0 = RXC clock is not stoppable for 100Bas e-TX RW 1
3.0.9:4 Reserved Reserved RW 00_0001
3.0.3:2 Reserved Reserved RO 00
3.0.1:0 Reserved Reserved RW 00
MMD Address 7h, Register 3Ch – EEE Advertisement
7.3C.15:3 Reserved Reserved RO 0000_0000_0000_0
7.3C.2 1000Base-T
EEE Capable 0 = 1000Mbps EEE is not supported RO 0
7.3C.1 100Base-TX
EEE Capable
1 = 100Mbps EEE capable
0 = No 100Mbps EEE capability
This bit is set to ‘0’ as the default after power-up
or reset. Set this bit to ‘1’ to enable 100Mbps
EEE mode.
RW 0
7.3C.0 Reserved Reserved RO 0
Note:
8. RW = Read/Write.
RO = Read only.
LH = Latch high.
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MMD Registers – Descriptions (Continued)
Address Name Description Mode
(8)
Default
MMD Address 7h, Register 3Dh – EEE Link Partner Advertisement
7.3D.15:3 Reserved Reserved RO 0000_0000_0000_0
7.3D.2 1000Base-T
EEE Capable 1 = 1000Mbps EEE capable
0 = No 1000Mbps EEE capability RO 0
7.3D.1 100Base-TX
EEE Capable 1 = 100Mbps EEE capable
0 = No 100Mbps EEE capability RO 0
7.3D.0 Reserved Reserved RO 0
MMD Address 1Ch, Register 4h – DSP 10Base-T/10Base-Te Control
1C.4.15 Reserved Reserved RW 0
1C.4.14 Reserved Reserved RO 0
1C.4.13 DSP 10Base-
T/10Base-Te
Mode Select
1 = Standard 10Base-T (2.5V TX amplitude)
and also set Standard Register 13h, Bit [4]
to ‘0’.
0 = EEE 10Base-Te (1.75 TX amplitude) and
also set Standard Register 13h, Bit [4] to ‘1’.
RW 1
1C.4.12 Reserved Reserved RW 0
1C.4.11:0 Reserved Reserved RO 0000_0000_0000
MMD Address 1Fh, Register 0h – Wake-On-LAN – Control
1F.0.15:14 PME Output
Select
These two bits work in conjunction with Reg.
16h, Bit [15] for PME Enable to define the
output for Pins 32 and 42.
INTRP/PME_N2 (Pin 32):
00 = INTRP output
01 = PME_N2 output
10 = INTRP and PME_N2 output
11 = Reserved
LED0/PME_N1 (Pin 42):
00 = PME_N1 output
01 = LED0 output
10 = LED0 output
11 = PME_N1 output
RW 00
1F.0.13:7 Reserved Reserved RO 00_0000_0
1F.0.6 Magic Packet
Detect Enable 1 = Enable magic-packet detection
0 = Disable magic-packet det ection RW 0
1F.0.5 Custom −
Packet Type 3
Detect Enable
1 = Enable custom-packet, Type 3 detection
0 = Disable custom-packet, Type 3 detection RW 0
1F.0.4 Custom −
Packet Type 2
Detect Enable
1 = Enable custom-packet, Type 2 detection
0 = Disable custom-packet, Type 2 detection RW 0
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MMD Registers – Descriptions (Continued)
Address Name Description Mode
(8)
Default
1F.0.3 Custom −
Packet Type 1
Detect Enable
1 = Enable custom-packet, Type 1 detection
0 = Disable custom-packet, Type 1 detection RW 0
1F.0.2 Custom-
Packet Type 0
Detect Enable
1 = Enable custom-packet, Type 0 detection
0 = Disable custom-packet, Type 0 detection RW 0
1F.0.1 Link-Down
Detect Enable 1 = Enable link-down detection
0 = Disable link-down detection RW 0
1F.0.0 Link-Up Detect
Enable 1 = Enable link-up detection
0 = Disable link-up detection RW 0
MMD Address 1Fh, Register 1h – Wake-On-LAN – Customized Packet, Type 0, Mask 0
MMD Address 1Fh, Register 7h – Wake-On-LAN – Customized Packet, Type 1, Mask 0
MMD Address 1Fh, Register Dh – Wake-On-LAN – Customized Packet, Type 2, Mask 0
MMD Address 1Fh, Register 13h – Wake-On-LAN – Customized Packet, Type 3, Mask 0
1F.1.15:0
1F.7.15:0
1F.D.15:0
1F.13.15:0
Custom Packe
t
Type X Mask 0
This register selects the bytes in the first 16
bytes of the packet (bytes 1 thru 16) that will be
used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-16
… : …
Bit [1] : byte-2
Bit [0] : byte-1
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 2h – Wake-On-LAN – Customized Packet, Type 0, Mask 1
MMD Address 1Fh, Register 8h – Wake-On-LAN – Customized Packet, Type 1, Mask 1
MMD Address 1Fh, Register Eh – Wake-On-LAN – Customized Packet, Type 2, Mask 1
MMD Address 1Fh, Register 14h – Wake-On-LAN – Customized Packet, Type 3, Mask 1
1F.2.15:0
1F.8.15:0
1F.E.15:0
1F.14.15:0
Custom Pac
ket
Type X
Mask 1
This register selects the bytes in the second 16
bytes of the packet (bytes 17 thru 32) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-32
… : …
Bit [1] : byte-18
Bit [0] : byte-17
RW 0000_0000_0000_0000
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MMD Registers – Descriptions (Continued)
Address Name Description Mode
(8)
Default
MMD Address 1Fh, Register 3h – Wake-On-LAN – Customized Packet, Type 0, Mask 2
MMD Address 1Fh, Register 9h – Wake-On-LAN – Customized Packet, Type 1, Mask 2
MMD Address 1Fh, Register Fh – Wake-On-LAN – Customized Packet, Type 2, Mask 2
MMD Address 1Fh, Register 15h – Wake-On-LAN – Customized Packet, Type 3, Mask 2
1F.3.15:0
1F.9.15:0
1F.F.15:0
1F.15.15:0
Custom Packet
Type X
Mask 2
This register selects the bytes in the third 16
bytes of the packet (Bytes 33 thru 48) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-48
… : …
Bit [1] : byte-34
Bit [0] : byte-33
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 4h – Wake-On-LAN – Customized Packet, Type 0, Mask 3
MMD Address 1Fh, Register Ah – Wake-On-LAN – Customized Packet, Type 1, Mask 3
MMD Address 1Fh, Register 10h – Wake-On-LAN – Customized Packet, Type 2, Mask 3
MMD Address 1Fh, Register 16h – Wake-On-LAN – Customized Packet, Type 3, Mask 3
1F.4.15:0
1F.A.15:0
1F.10.15:0
1F.16.15:0
Custom Packet
Type X
Mask 3
This register selects the bytes in the fourth 16
bytes of the packet (bytes 49 thru 64) that will
be used for CRC calculation.
For each bit in this register,
1 = Byte is selected for CRC calculation
0 = Byte is not selected for CRC calculation
The register-bit to packet-byte mapping is as
follows:
Bit [15] : byte-64
… : …
Bit [1] : byte-50
Bit [0] : byte-49
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 5h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 0
MMD Address 1Fh, Register Bh – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 0
MMD Address 1Fh, Register 11h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 0
MMD Address 1Fh, Register 17h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 0
1F.5.15:0
1F.B.15:0
1F.11.15:0
1F.17.15:0
Custom Packet
Type X CRC 0
This register stores the lower two bytes for the
expected CRC.
Bit [15:8] = Byte 2 (CRC [15:8])
Bit [7:0] = Byte 1 (CRC [7:0])
The upper two bytes for the expec ted CRC are
stored in the follow ing reg ist er.
RW 0000_0000_0000_0000
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MMD Registers – Descriptions (Continued)
Address Name Description Mode
(8)
Default
MMD Address 1Fh, Register 6h – Wake-On-LAN – Customized Packet, Type 0, Expected CRC 1
MMD Address 1Fh, Register Ch – Wake-On-LAN – Customized Packet, Type 1, Expected CRC 1
MMD Address 1Fh, Register 12h – Wake-On-LAN – Customized Packet, Type 2, Expected CRC 1
MMD Address 1Fh, Register 18h – Wake-On-LAN – Customized Packet, Type 3, Expected CRC 1
1F.6.15:0
1F.C.15:0
1F.12.15:0
1F.18.15:0
Custom Packet
Type X
CRC 1
This register stores the upper two bytes for the
expected CRC.
Bit [15:8] = Byte 4 (CRC [31:24])
Bit [7:0] = Byte 3 (CRC [23:16])
The lower two bytes for the expected CRC are
stored in the previou s regis ter.
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 19h – Wake-On-LAN – Magic Packet, MAC-DA-0
1F.19.15:0 Magic Packet
MAC-DA-0
This register stores the lower two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 2 (MAC Address [15:8])
Bit [7:0] = Byte 1 (MAC Address [7:0])
The upper four bytes of the des tination MAC
address are store d in the follo wing two
registers.
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 1Ah – Wake-On-LAN – Magic Packet, MAC-DA-1
1F.1A.15:0 Magic Packet
MAC-DA-1
This register stores the middle two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 4 (MAC Address [31:24])
Bit [7:0] = Byte 3 (MAC Address [23:16])
The lower two bytes and upper two bytes of the
destination MAC address are stored in the
previous and following registers, respectively.
RW 0000_0000_0000_0000
MMD Address 1Fh, Register 1Bh – Wake-On-LAN – Magic Packet, MAC-DA-2
1F.1B.15:0 Magic Packet
MAC-DA-2
This register stores the upper two bytes of the
destination MAC address for the magic packet.
Bit [15:8] = Byte 6 (MAC Address [47:40])
Bit [7:0] = Byte 5 (MAC Address [39:32])
The lower four bytes of the destination MAC
address are store d in the previ ous tw o
registers.
RW 0000_0000_0000_0000
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KSZ8091MLX
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Absolute Maximum Ratings(9)
Supply Voltage (VIN)
(VDD_1.2) .................................................. −0.5V to +1.8V
(VDDIO, VDDA_3.3) ...................................... −0.5V to +5.0V
Input Voltage (all inputs) .............................. −0.5V to +5.0V
Output Volta ge (a ll outputs ) ......................... −0.5V to +5.0V
Lead Temperature (soldering, 10s) ............................ 260°C
Storage Temperature (TS) ......................... –55°C to +150°C
Operating Ratings(10)
Suppl y Voltage
(VDDIO_3.3, VDDA_3.3) .......................... +3.135V to +3.465V
(VDDIO_2.5) ........................................ +2.375V to +2.625V
(VDDIO_1.8) ........................................ +1.710V to +1.890V
Ambient Temperature
(TA, Commercial) ...................................... 0°C to +70°C
(TA, Industrial) ....................................... –40°C to +85°C
Maximum Junction Temperature (TJ maximum) ........ 125°C
Thermal Resistance (θJA) ......................................... 76°C/W
Thermal Resistance (θJC) ......................................... 15°C/W
Electrical Characteristics(11)
Symbol Parameter Condition Min. Typ. Max. Units
Supply Current (VDDIO, VDDA_3.3 = 3.3V)(12)
IDD1_3.3V 10Base-T Full-duplex traffic @ 100% utilization 41 mA
IDD2_3.3V 100Base-TX Full-duplex traffic @ 100% utilization 47 mA
IDD3_3.3V EEE (100Mbps) Mode TX and RX paths in LPI state with no traffic 23 mA
IDD4_3.3V EDPD Mode Ethernet cable disconnected (Reg. 18h.11 = 0) 20 mA
IDD5_3.3V Power-Do wn Mode Software power-down (Reg. 0h.11 = 1) 4 mA
CMOS Level Inputs
VIH Input High Voltage
VDDIO = 3.3V 2.0
V VDDIO = 2.5V 1.8
VDDIO = 1.8V 1.3
VIL Input Low Voltag e
VDDIO = 3.3V 0.8
V VDDIO = 2.5V 0.7
VDDIO = 1.8V 0.5
|IIN| Input Current VIN = GND ~ VDDIO 10 µA
CMOS Level Outputs
VOH Output High Voltage
VDDIO = 3.3V 2.4
V VDDIO = 2.5V 2.0
VDDIO = 1.8V 1.5
VOL Output Low Voltage
VDDIO = 3.3V 0.4
V VDDIO = 2.5V 0.4
VDDIO = 1.8V 0.3
|Ioz| Output Tri-State Leakage 10 µA
LED Output
ILED Output Drive Current Each LED pin (LED0, LED1) 8 mA
Notes:
9. Exceeding the absolute maximum ratings may damage the device. Stresses greater than the absolute maximum rating can cause permanent
damage to the device. Operation of the device at these or any other conditions above those specified i n the operating sections of this specification is
not implied. Maximum condit i ons for extended periods may affect reliabil i t y.
10. The device is not guarant eed to function outside its operat i ng ratings.
11. TA = 25°C. Specification for packaged product onl y.
12. Current consumption is for the single 3.3V supply KSZ8091MLX device only, and includes t he transmit driver current and the 1.2V supply voltage
(VDD_1.2) that are suppl i ed by the KSZ8091MLX.
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Electrical Characteristics(11) (Continued)
Symbol Parameter Condition Min. Typ. Max. Units
All Pull-Up/Pull-Down Pins (including Strapping Pins)
pu Internal Pull-Up Resistance
VDDIO = 3.3V 30 45 73
kΩ VDDIO = 2.5V 39 61 102
VDDIO = 1.8V 48 99 178
pd Internal Pull-Down Resistance
VDDIO = 3.3V 26 43 79
kΩ VDDIO = 2.5V 34 59 113
VDDIO = 1.8V 53 99 200
100Base-TX Transmit (measured differentially after 1:1 transformer)
VO Peak Differential Output Voltage 100Ω termination across differential output 0.95 1.05 V
VIMB Output Voltage Imbalance 100Ω termination across differential output 2 %
tr, tf Rise/Fall Time 3 5 ns
Rise/Fall Time Imbalance 0 0.5 ns
Duty Cycle Di stortion ±0.25 ns
Overshoot 5 %
Output Jitter Peak-to-peak 0.7 ns
10Base-T Transmit (measured differentially after 1:1 transformer)
VP Peak Differential Output Voltage 100Ω termination across differential output 2.2 2.8 V
Jitter Added Peak-to-peak 3.5 ns
tr, tf Rise/Fall Time 25 ns
10Base-T Receive
VSQ Squelch Threshold 5MHz square wave 400 mV
Transmitter – Drive Setting
VSET Reference Voltage of ISET R(ISET) = 6.49kΩ 0.65 V
100Mbps Mode – Industr ial Applications Parameters
Clock Phase Delay – XI Input to
MII TXC Output
XI (25MHz clock input) to MII TXC
(25MHz clock output) delay, referenced to
rising edges of both clocks. 15 20 25 ns
tllr Link Loss Reaction (Indication)
Time
Link loss detected at receive differential inputs
to PHY signal indication time for each of the
following:
1. For LED mode 00, Speed LED output
changes from low (100Mbps) to high
(10Mbps, default state for link-down).
2. For LED mode 01, Link LED output changes
from low (link-up) to high (link-down).
3. INTRP pin asserts for link-down status
change.
4.4 µs
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Timing Diagrams
MII SQE Timing (10Base-T)
Figure 12. MII SQE Timing (10Base-T)
Table 13. MII SQE Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSQE COL (SQE) delay after TXEN de-asserted 2.2 µs
tSQEP COL (SQE) pulse duration 1.0 µs
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KSZ8091MLX
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31, 2015 59 Revision 1.2
MII Transmit Timing (10Base-T)
Figure 13. MII Transmit Timing (10Base-T)
Table 14. MII Transmit Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 400 ns
tWL TXC pulse width low 200 ns
tWH TXC pulse width high 200 ns
tSU1 TXD[3:0] setup to rising edg e of T X C 120 ns
tSU2 TXEN setup to rising edge of TXC 120 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 600 ns
tCRS2 TXEN low to CRS de-asserted latency 1.0 µs
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KSZ8091MLX
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31, 2015 60 Revision 1.2
MII Receive Timing (10Base-T)
Figure 14. MII Receive Timing (10Base-T)
Table 15. MII Receive Timing (10Base-T) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 400 ns
tWL RXC pulse width low 200 ns
tWH RXC pulse width high 200 ns
tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC 205 ns
tRLAT CRS to (RXDV, RXD[3:0]) latency 7.2 µs
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KSZ8091MLX
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31, 2015 61 Revision 1.2
MII Transmit Timing (100Base-TX)
Figure 15. MII Transmit Timing (100Base-TX)
Table 16. MII Transmit Timing (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP TXC period 40 ns
tWL TXC pulse width low 20 ns
tWH TXC pulse width high 20 ns
tSU1 TXD[3:0] setup to rising edg e of T X C 10 ns
tSU2 TXEN setup to rising edge of TXC 10 ns
tHD1 TXD[3:0] hold from rising edge of TXC 0 ns
tHD2 TXEN hold from rising edge of TXC 0 ns
tCRS1 TXEN high to CRS asserted latency 72 ns
tCRS2 TXEN low to CRS de-asserted latency 72 ns
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KSZ8091MLX
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31, 2015 62 Revision 1.2
MII Receive Timing (100Base-TX)
Figure 16. MII Receive Timing (100Base-TX)
Table 17. MII Receive Timing (100Base-TX) Parameters
Timing Parameter Description Min. Typ. Max. Unit
tP RXC period 40 ns
tWL RXC pulse width low 20 ns
tWH RXC pulse width high 20 ns
tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC 16 21 25 ns
tRLAT CRS to (RXDV, RXD[3:0]) latency 170 ns
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KSZ8091MLX
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31, 2015 63 Revision 1.2
Auto-Negotiation Timing
Figure 17. Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 18. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters
Timing Parameter Description Min. Typ. Max. Unit
tBTB FLP burst to FLP burst 8 16 24 ms
tFLPW FLP burst width 2 ms
tPW Clock/data pulse width 100 ns
tCTD Clock pulse to data pulse 55.5 64 69.5 µs
tCTC Clock pulse to clock pulse 111 128 139 µs
Number of clock/data pulses per FLP burst 17 33
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KSZ8091MLX
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31, 2015 64 Revision 1.2
MDC/MDIO Timing
Figure 18. MDC/MDIO Timing
Table 19. MDC/MDIO Timing Parameters
Timing Parameter Description Min. Typ. Max. Unit
fc MDC Clock Frequency 2.5 10MHz
tP MDC period 400 ns
tMD1 MDIO (PHY input) setup to rising edge of MDC 10 ns
tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns
tMD3 MDIO (PHY output) delay from rising edge of MDC 5 222 ns
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KSZ8091MLX
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31, 2015 65 Revision 1.2
Power-Up/Reset Timing
The KSZ8091MLX reset timing requirement is summarized in Figure 19 and Table 20.
Figure 19. Power-Up/Reset Timing
Table 20. Power-Up/Reset Timing Parameters
Timing Parameter Description Min. Typ. Max. Unit
tVR Supply voltage (VDDIO, VDDA_3.3) rise tim e 300 µs
tSR Stable supply voltage (VDDIO, VDDA_3.3) to reset high 10 ms
tCS Configurat i on setu p time 5 ns
tCH Configuration hold t ime 5 ns
tRC Reset to strap-in pin output 6 ns
The supply voltage (VDDIO and VDDA_3.3) power-up waveform should be monotonic. The 300µs minimum rise time is from
10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100µs before starting programming on the MIIM (MDC/MDIO) interface.
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Reset Circuit
Figure 20 shows a reset circuit recommended for powering up the KSZ8091MLX if reset is triggered by the power supply.
Figure 20. Recommended Reset Circuit
Figure 21 Shows a reset circuit recomm ended for applications where reset is driven by another device (for example, the
CPU or a n FPG A). T he res et out R ST _OUT _n fr om CPU/FPG A provi des th e war m res et after power up reset. D2 is used
if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other. If
different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, VISHAY’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 c an be remove d to connect both de vices directl y. Usually, Eth ernet device and CP U/FPGA sho uld use same
VDDIO voltag e.
Figure 21. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output
Micrel, Inc.
KSZ8091MLX
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Reference Circuits – LED Strap-In Pins
The pull-up, float, and pull-do wn reference c ircuits f or the LED1/SPEE D and LED0/P ME_N1/NWAYEN strapping pins ar e
shown in Figure 22 for 3.3V and 2.5V VDDIO .
Figure 22. Reference Circ uits for LED Strapping Pins
For 1.8V VDDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the
SPEED an d NWAYEN strapping p ins are functio nal wi th a 4.7kΩ pull-up to 1.8V VDDIO or float for a value of ‘1’, and with
a 1.0kΩ pull-down to ground for a value of ‘0’.
Note: If using RJ 45 Jack s with integrated LEDs and 1.8V VDDIO , a level shif ting is re quired from LED 3.3V to 1.8V. For
example, use a bipolar transistor or a level shift device.
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Reference Clock – Connection and Selection
A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8091MLX.
For the KSZ80 91MLX in all operating modes, the reference clock is 25MHz. T he crystal / reference clock connections to
XI (Pin 15) and XO (Pin 14), and the crystal / reference clock selection criteria, are provided in Fi gure 23 and Table 21.
Figure 23. 25MHz Crystal/Oscillator Reference Clock Connection
Table 21. 25MHz Crystal / Reference Clock Selection Criteria
Characteristics Value Units
Frequency 25 MHz
Frequency tolerance (m aximum)(13) ±50 ppm
Crystal series resistance (typical) 40 Ω
Crystal load capacitance (typical) 16 pF
Note:
13. ±60ppm for overtemperature crystal.
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KSZ8091MLX
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31, 2015 69 Revision 1.2
Magnetic – Connection and Selection
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements.
The KSZ8091MLX design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential
pairs. Therefore, the two transformer center tap pins on the KSZ8091MLX side should not be connected to any power
supply source on the board; instead, the center tap pins should be separated from one another and connected through
separate 0.1µF common-mode capacitors to ground. Separation is required because the common-mode voltage is
different between transmitting and receiving differential pairs.
Figure 24 shows the typical magnetic interface circuit for the KSZ8091MLX.
Figure 24. Typical Magnetic Interface Circuit
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Table 22 lists recommended magnetic characteristics.
Table 22. Magnetics Selection Criteria
Parameter Value Test Condition
Turns ratio 1 CT : 1 CT
Open-circuit inductance (min. ) 350µH 100mV, 100kHz, 8mA
Insertion lo ss (typ.) –1.1dB 100kHz to 100M Hz
HIPOT (min.) 1500Vrms
Table 23 is a l ist of com pati ble si ng le-port magnet ic s w ith sep ar ate d tr ans f ormer center tap p ins on t he PH Y chip s id e th at
can be used with the KSZ8091MLX.
Table 23. Compatible Single-Port 10/100 Magnetics
Manufacturer Part Number Temperature Range Magnetic + RJ-45
Bel Fuse S558-5999-U7 0°C to 70°C No
Bel Fuse SI-46001-F 0°C to 70°C Yes
Bel Fuse SI-50170-F 0°C to 70°C Yes
Delta LF8505 0°C to 70°C No
HALO HFJ11-2450E 0°C to 70°C Yes
HALO TG110-E055N5 –40°C to 85°C No
LANKom LF-H41S-1 0°C to 70°C No
Pulse H1102 0°C to 70°C No
Pulse H1260 0°C to 70°C No
Pulse HX1188 –40°C to 85°C No
Pulse J00-0014 0°C to 70°C Yes
Pulse JX0011D21NL –40°C to 85°C Yes
TDK TLA-6T718A 0°C to 70°C Yes
Transpower HB726 0°C to 70°C No
Wurth/Midcom 000-7090-37R-LF1 –40°C to 85°C No
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
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perform ance linear and po wer, LAN, and tim ing & communications
markets. The Company’s products include advanced mixed
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MEMs-based clock oscillators & crystal-less clock generators, Ethernet switches, and physical layer transceiver ICs.
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customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and comp
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ormation furnished in this data
sheet. This
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me responsibility for its use.
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specifications and descriptions at any time without notice.
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