AIMEL WIRELESS & pc U6815BM Dual Hex DMOS Output Driver with Serial Input Control Description The U6815BM is a fully protected driver interface designed in 0.8-um BCDMOS technology. It is used to control up to 12 different loads by a microcontroller in automotive and industrial applications. Each of the 6 high-side and 6 low-side drivers is capable to drive currents up to 600 mA. The drivers are freely configurable and can be controlled separately from a standard serial data interface. Therefore, all kinds of loads such as bulbs, resistors, capacitors and inductors Features @ Six high-side and six low-side drivers Outputs freely configurable as switch, half bridge or H-bridge Capable to switch all kinds of loads such as DC motors, bulbs, resistors, capacitors and inductors @ ().6 A continuous current per switch @ Low-side: Rpson < 1.5 Q vs. total temperature range @ High-side: Rpson < 2.0 Q vs. total temperature range @ Very low quiescent current Is < 20 wA in standby made Ordering Information Extended Type Number U6815BM-FL = - po Package $028 Power package can be combined. The IC design especially supports the applications of H-bridges to drive DC motors. Protection is guaranteed in terms of short-circuit conditions, overtemperature, under- and overvoltage. Various diagnosis functions and a very low quiescent current in standby-mode open a wide range of applications. Automotive qualification referring to conducted interferences, EMC protection and 2 kV ESD protection gives added value and enhanced quality for the exacting requirements of automotive applications. @ Outputs short-circuit protected Overtemperature prewarning and protection @ Under- and overvoltage protection Various diagnosis functions such as shorted output, open load, overtemperature and power supply fail @ Serial data interface Daisy chaining possible @ Loss of ground protection @ S028 power package Remarks Rev. A3, 19-Mar-01 207 Preliminary InformationU6815BM ATMEL WIRELESS & pC Block Diagram Hs5/ qh Hs6/ 2 28 | ey f - =F | | by KS 5 | || [38 vs ots 4 | gone pr 2s. ey Vs Step "Ose | OV- | CLK 22 Y & yp y protection | | 7 nD in Ae . Wwe. |. Control | uv- | exe Input Register L [es > Ooty t Fe ti protection utput Re i ler L lodi oe) i G logic a @ GND] __| ae wen _ {L) Thermal }> i innZ anh protection; | ., 5 P-ON- ) eM tole Reset | 421 inp << >, tye ~ an 22 ND? ) 1 yl rc uit : b. ult | Fault dat } auult 23 GND te E Ji Je |] Yoo | = Ky 1: 4 18 Vee 16 i . 4 a 8? = ia 1 : tsi] isa\_l) isal_[}- isa Lssl_J s.) Figure |. Block diagram 208 Rev. A3, 19-Mar-01 Preliminary InformationAIMEL wee lh WIRELESS & pC U6815BM Pin Description LS6 DI CLK CS GND GND GND GND VCC DO INH LS! HSI fey f2d_(25|_ (eel foal foe] [an fa) fav [isl i? fiel_iis U6815BM ' Lead frame i Loo ee 6 ~ 2 se 4 2) 13f Gy [sy te) aT [s} [et to) ay 2) pap [aa HSS HS4 L~LS4 VS GND GND GND GND VS_ LS3 HS3 HS2 LS2 Figure 2. Pinning [3 Pin Symbol . Function | LSS Low-side driver output 5; Power-MOS open drain with internal reverse diode: overvoltage protection by | active zenering; short-circuit protection; diagnosis for short and open load 2 HSS High-side driver output 5; Power-MOS open drain with internal reverse diode: overvoltage protection by a _ active zenering; short-circuit protection; diagnosis for short and open load _ | 3. | HS4 __| High-side driver output 4; see Pin 2 _ _ __| _4 | LS4 | Low-side driver output 4; see Pin 1 3. VS. Power supply output stages HS4, HS5, HS6, internal supply; external _connection to Pin 10 necessary _ _6, 7, 8,9 GND | Ground; reference potential; internal connection to Pin 20 - 23; cooling tab _ ____10 | VS Power supply output stages HS1, HS2 and HS3_ . : : ic LS3___Low-side driver output 3; see Pin I _. . a _ _ _12 _HS3 High-side driver output 3: see Pin 2. ; __ 4 on HS2__| High-side driver output 2; see Pin 2 _ oe | 14 LS2__ | Low-side driver output 2;see Pin) _ _ . __15 HS1___ High-side driver output 1; see Pin 2 _ _ _ ; _| ts _ LI | | Low- _Low-side criver output 1; see Pin I _ _ 17 INH Inhibit input; 5-V logic input with internal pull down; Tow = standby, | ee i high = normal operating _ 18 DO Serial data output; 5-V CMOS logic level tristate output for output (status) register data: sends 16-bit sta- | ! tus information to the wC (LSB is transferred first). Output will remain tristated unless device is selected | i | _ by CS = low, therefore, several [Cs can operate on one data output line only. . 19 VCC | Logic supply voltage (5 V) _ . _ 20, 21, GND Ground; see Pin 6 ~9 : 22,23 ee ee . _ | 24 cs Chip select input; 5-V CMOS logic level input with internal pull up; | _ low = serial communication is enabled, high=disabled ee | 25 CLK | Serial clock input; 5-V CMOS logic level input with internal pull down; _ controls serial data input interface and internal shift register (fmax = 2 MHz) 26 ! DI Serial data input; 5-V CMOS logic level input with internal pull down, receives serial data from the con- jo __, trol device; D1 expects a 16-bit control word with LSB being transferred first_ _ __. 27 | LS6 _| Low-side driver output 6; see Pin] . ee | | 28 ~~ HS6 ___ High-side driver output 6; see Pin 2 a Rev. A3, 19-Mar-01 209 Preliminary InformationU6815BM AMET, Functional Description Serial Interface cL r DI | SRR | LS] I HSI | LS2 I Hs2 | LS3 | HS3 | LS4 | uss] LSS | HSs5 LS6 | HS6 | oLp | st | SI | 0 | 2 3 4 5 6 7 8 9 10 ul 12 13 14 is DOY 1 [sisi [sus J sisz [sus2 [suss J sass [sts | ssa [suss | suss [szse J stise | scD | INH | PSF + Figure 3. Data transfer Data transfer starts with the falling edge of the CS signal. When CS is high, Pin DO is in tristate condition. This Data must appear at DI synchronized to CLK and are output is enabled on the falling edge of CS. Output data accepted on the falling edge of the CLK signal. LSB will change their state with the rising edge of CLK and (bit 0, SRR) has to be transferred first. Execution of new __ stay stable until the next rising edge of CLK appears. LSB input data is enabled on the rising edge of the CS signal. (bit 0, TP) is transferred first. Input Data Protocol Bit | Input Register | Function | 0 SRR | Status register reset (high = reset; the bits PSF, SCD and overtemperature shutdown in the a oe QUIT data register are set to low) co _ to. AST _ Controls output LSI (high = switch output LSI on) - _ re 2; ___.__ HS! __ | Cantrols output HSL (high = switch output HS] on) | 4 3 See LS1_ a oe ee a : See HS] a _ a | See LSI a _[See HS} oe ee oe _ i _|See LSI a - - con _ | See HS1 4 See LSI _ _ _ | See HS! ; _ _ {See LSto oe a ae ee See HS1 eee on bo ne a ___! Open load detection (low =on) eens ee moet tne | Programmable time delay for short circuit and overvellage shutdown (short circuit shutdown . . delay high / low = 100 ms / 12.5 ms, overvoltage shutdown delay high / tow = 15 ms / 3.5 ms | 15 SI Software inhibit; low = standby, high = normal operation __ (data transfer is not affected by standby function because the digital part is still powered) _ After power-on reset, the input register has the following status: Btls B14 | Bits | B12 | BATT | Bild | Bro | Bis | Bi7 [ Bas Bits | Bite | Br3 | Bie2 | Bid Biro (SI) (SCT) | (OLD) | (HS6) | (LS6) (HSS) | (LSS) | (HS4) | (LS4) | (HS3) | (LS3) | (HS2) | (L82) | (HS1) | (LSI) (SRR) HOW MOR Rk bk bk kb kb bp 210 Rev. A3, 19-Mar-01 Preliminary InformationATME!. U6815BM Output Data Protocol Bit | Output (Status) Register Function | 0: TP. Temperature prewarning: high = warning (overtemperature shut down see remark below) | j Status LS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = no open load (correct load condition is detected | if the corresponding output is switched off) | | te Status HS1 Normal operation: high = output is on, low = output is off Open-load detection: high = open load, low = na open load (correct load condition is detected . if the corresponding output is switched off) ____Status LS2 __._ Description see LS1 Status HS2 _ Description see HS 1 OL. Status LS3 0 Descriptionsee LST a ee - j 6 Status HS3 __ | Description see HS1 _ oe a, Status S400 , Description see LSt ee oe ee oo 8 i Status HS4 ___| Description see HS1 . _ _ oo | 9 ft Status LSS Description see LS ee ee oo 10 Status HSS iption see HS1 . - . | MH Status LS6 _ Description see LS1 _ _ / ea Status HS6__Descriptionsee HSE. we 13: SCD Short circuit detected: set high, when at least one output is switched off by a short circuit a condition . _ a 14 INH | Inhibit: this bit is controlled by software (bit SE in input register) and hardware inhibit | Co (Pin 17). High = standby, low = normal operation __ we, IS PSF ss; Power supply fail: over- or undervoltage at Pin VS detected 7 - 4 Remark: Bit 0 to 15 = high: overtemperature shutdown Power Supply Fail Overtemperature Protection Incase of over- / undervoltage at pin VS, an internal timer is started. When the overvoltage delay time (tyov) programmed by the SCT Bit, or the undervoltage delay prewarning bit (TP) in the output register is set. When time (tayy) is reached, the power supply fail bit (PSF) in temperature falls below the thermal prewarning threshold the output register is set and all outputs are disabled. Tjpw reset. the bit TP is reset. The TP bit can be read When normal voltage is present again, the outputs are ; enabled immediately. The PSF bit remains high until it is reset by the SRR bit in the Input Register. If the junction temperature exceeds the thermal prewarning threshold, Tjpw se the temperature without transferring a complete 16 bit data word: with CS = high to low, the state of TP appears at Pin DO. After the uC has read this information, CS is set high and the Open-Load Detection data transfer is interrupted without affecting the state of input and output registers. If the open-load detection bit (OLD) is set to low, a pull up current for each high side switch and a pull down _ Ifthe junction temperature exceeds the thermal shutdown current for each low side switch is turned on (open-load threshold T; switch otf the outputs are disabled and all bits detection current Iysj-6 Ixsi-e). If Wvs-Vusi-6 or in the output register are set high. The outputs can be Visi-6 is lower than the open-load detection threshold enabled again when the temperature falls below the (open-load condition) the corresponding bit of the output thermal shutdown threshold, Tj switch on. and when a high in the output register is set to high. Switching on anoutput has been written to the SRR bit in the input register. stage with OLD bit set to low disables the open-load Thermal prewarning and shutdown threshold have function for this output. hysteresis. Rev. A3, 19-Mar-01 211 Preliminary InformationU6815BM ANMEL WIRELESS & pC Short-Circuit Protection The output currents are limited by a current regulator. Current limitation takes place when the overcurrent limitation and shutdown threshold (Iisi-6, ILst-6) are reached. Simultaneously, an internal timer is started. The shorted output is disabled when during a permanent short the delay time (tasu) programmed by the short-circuit timer bit (SCT) is reached. Additionally, the short-circuit detection bit (SCD) is set. If the temperature prewarning bit TP in the output register is set during a short, the shorted ouiput is disabled immediately and SCD bit is set. By writing a high to the SRR bit in the input register, the Absolute Maximum Ratings All values refer to GND pins SCD bit is reset and the disabled outputs are enabled. Inhibit There are two ways to inhibit the U6815BM: 1. Set bit S] in the input register to zero 2. Switch Pin 17 (INH) to 0 V In both cases, all output stages are turned off but the serial interface stays active. The output stages can be activated again by bit SI = 1 or by Pin 17 (INH) switched back to SV. Parameter Symbol Value Unit Supply voltage _ Pins 5, 10 __ Vvs - 0.3 to 40 Vv Supply voltage t<0.5s;Is>-2A Pins 5, 10 Ws | -l1 | vi | Supply voltage difference _ [Vs pins - Vs Pintol_ AVvs _ 150 mV | surely current __ Pins 5, 10 Iys 1.4 A! Supply current t< 200 ms : Pins 5, 10 Ivs 2.6 - A Logic supply voltage Pin 19 Vvcc 0.3 to7 Vv Input voltage __ Pin 17 _ VINH | -03t017 | OV Logic input voltage Pins 24 to 26 Vor, Vcik, Ves -0.3 to Vvec +0.3 Vv. hans output voltage Pin 18 Vpo -0.3 to Vvcc + 0.3 Vv i Input current _ Pins 17, 17, 24 to 26 linn, Ibi, Ici, Ics -10 to +10 mA Output current Pin 18 Ipo -10 to +10 mA | Output current Pins | to 4, 11 to 16, ILs1 to [nse Internal limited, see ; mA 1 Pins 27 and28 ss Iysitoluse . | output specification | Reverse conducting current Pins 2, 3, 12, 13, 15 lyst to lyase 17 A (tpulse = = 150 ys) 28 towards Pins 5, 10 | Junction temperature range . __ T; _ -40 to 150 | | _Storage temperature range _ TstG -55 to 150 C | Operating Range All values refer to GND pins Parameters Test Conditions / Symbol Min. | Typ.) Max. | Unit | Pins Supply voltage Pins 5, 10 _ Vvs Vuv 2 40?) vi Logic supply voltage Pin 19 Vvcc |. 45 5 5 55 | V Logic input voltage _Pin 17, 24 to 26 Vinu, Vor, VeiK, Vcs | -0.3 Vvec Vv | Serial interface clock frequency Pin 25 foLk _ | 2 MHz | | Junction temperature range _ Tj -40 1is0_ | C ') Threshold for undervoltage detection 2) Qutput disabled for Vvs > Voy (threshold for overvoltage detection) 212 Preliminary Information Rev. A3, 19-Mar-01AIMEL ey WIRELESS & pC U6815BM Thermal Resistance All values refer to GND pins Parameters Test Conditions / Pins Symbol Min Typ. Max. Unit | Junction - pin Measured to GND Runsp 25 Kw Pins 6 to 9 and 20 to 23 Junction ambient Rina | _ 65 K/w Noise and Surge Immunity Parameters Test Conditions Value Conducted interferences ISO 7637-1 level 4 ) Interference Suppression VDE 0879 Part 2 level 5 ESD (Human Body Model) MIL-STD-883D Method 3015.7 2kV ESD (Machine Model) | EOS / ESD - $5.2 150 V 1) Test pulse 5: Vsmax = 40 V Electrical Characteristics 7.5 V<Vys <40 V; 4.5 V<Vycec<5.5 V; INH = High; -40C <Tj < 150C; unless otherwise specified, all values refer to GND pins. Parameter | Test Conditions / Pins | Symbol! Min. Typ. | Max. | Unit Current Consumption Quiescent current (VS) Vvys < 16 V, INH or Ivs 40 pA bit SI = low Pins 5, 10 Quiescent current (VCC) 45 V<Vycc <5.5V, Ivec 20 HA /INH or bit SE=low = Pin 19 Supply current (VS) Vvs<1l6V Pins 5, 10 | normal operating all output stages off, Ivs 0.8 1.2 mA : all output stages on, no load Ivs 10 mA Supply current (VCC) 4.5.V<Vvcc <5.5 V, Ivcc | 150 vA normal operating Pin 19 ' Internal Oscillator Frequency Frequency (Time-base for | fosc 19 45 kHz | delay timers) ' ; Over- and Undervoltage Detection, Power-On Reset | Power-on reset threshold Pin 19 Vee | 34 39 44 1 oy ' Power-on reset delay time After switching on Vycc tapor 30 95 160 Us Undervoltage detection Pins 5, 10 Vuv 5.5 7.0 Vv threshold | | Undervoltage detection Pins 5, 10 AVuv 0.4 Vv hysteresis Undervoltage detection delay _ __tguv 7 21 ms Overvoltage detection thresh- Pins 5, 10 | Vov 18 225 i Vv old . Rev. A3, 19-Mar-01 213 Preliminary InformationU6815BM AIMET, WIRELESS & pC Electrical Characterist 75 V<Vvys <40 V; 4.5V<Vvc all values refer to GND pins. ics (continued) c<5.5 V, INH = High; -40C <T; < 150C; unless otherwise specified, | Parameters Test Conditions / Pins Symbol | Min. | Typ. Max. | Unit Overvoltage detection hvste- Pins 5, 10 AVov 1 Vv resis _ a ee . te Overvoltage detection delay Input register tuov 7 21 ms a _._ bit 14 (SCT) = high po - | Overvoltage detection delay Input register taov | 1.75 5.25 ms Co _bitl4(SCT)=low | | Thermal | Prewarning and Shutdown - ; ee - | Thermal prewarning _ 7 | Tjpwset | 125 145 165 CL Thermal prewarning a _ | Tpwreset 105 (125 145 C | : Thermal prewarning ATjpw 20 K chysteresis ae oe ee oo . . ; | : Thermal shutdown _ ee ee Ti switchort 150 170 190, C | Thermal shutdown __ _Tjswitchon 130 150 170 C Thermal shutdown AT} switch 20 ; K -hysteresis_ _ _ | off ee _. Ratio thermal shutdown ; / ther- | Tj switch off) 1.05 1.17 mal prewarning _ _ Tipw ser eee Ratio thermal shutdown , ther- Tj switeh on/ 1.05 1.2 ' _mal prewarning _ _TiPw reset 2 Output Specification (LS1 - 'LS6, HSI - -HS6) 7.5 V<Vys< Vov On resistance Tour = 600 mA : _ Pins 1, 4, 11, 14, 16, 27 j-RpsoaL. 1s On resistance Tour = -600 mA a _____| Pins 2, 3, 12, 13, 15, 28 -Rpsonu |__|. 2.0. Q- Output clamping voltage Ins1-6= 50mA : oo. Pins 1, 4, 11, 14, 16, 27 | Viste | 40 60 Vv Output leakage current Visio= 40 V all output stages off ILsi-6 10 pA _ - Pins 1, 4, 11, 14, 16, 27 - | Output leakage current ! Vusi-6 =0V . all output stages off lys1-6 -10 pA oe _ Pins 2, 3, 12, 13, 15, 28 | Inductive shutdown energy!) Pins 1-4, 11-16, 27, 28 Woutx | | 15 mJ | Output voltage edge steepness Pins 1-4, 11-16, 27, 28 dV, s1-6/dt 50 200 400) | mV/us fo _ a dVys1-6/dt : . wee Overcurrent limitation and Pins 1, 4, 11, 14, 16, 27 ILs1-6 650 | 950 1250 mA Shutdown threshold _ - . _ a | . a Overcurrent limitation and Pins 2,3, 12, 13,15, 28 tus16 -1250 | -950 | -650 mA _Shutdown threshold 1) Only valid for version U6815B M-N. 214 Preliminary Information Rev. A3, 19-Mar-01AIMEL WIRELESS & pC Electrical Characteristics (continued) U6815BM 7.5 V<Vys<40 V. 4.5 V<Vycc<5.5 V; INH = High; -40C < Tj < 150C; unless otherwise specified, all values refer to GND pins. Parameters Test Conditions / Pins | Symbol Min. Typ. Max. Unit | ; Overcurrent shutdown Input register tasd 70 100 140 ms | [delay time | bit 14 (SCT) = high _ 2 | Overcurrent shutdown Input register tasd 8.75 17.5 ms | |delay time bit 14 (SCT) = low _ . | jo Open load detection current | Input register bit 13 (OLD) Ihsi-6 60 200) UWA '=low, output off : | | | | Pins L, 4, 11, 14, 16, 27 . eo st Open load detection current | Input register bit 13 (OLD) Tusi-6 | -150 | -30 WA =low, output off a ___ Pins 2, 3, 12, 13, 15, 28 ; | | ee Open load detection current | Isteay | 12 _Tatio | __lysi-6 - ao ae Open load detection thresh- Taput register bit 13 (OL D). Visio . 0.6 4 | Vv old | slow, output off | | _ __ Pins 1. 4, 11, 14, 16, 27 - _ io Open k load detection thresh- Input register bit 13 (OLD) | Vys- 0.6 4 old slow, output off ~ Vusi-6 | ae ___ Pins 2, 3, 12, 13, 15, 28 | _. - | Output | Switch on 1 on delay 2 2) Riad = ton | 8s ms _ Output Switch offdelay [| Ryoug=1kQ aot toms Anhibit Input a . a Input voltage low level Pin 17 Vir; O3* : Vv threshold ee | Wee | Input voltage high level Pin 17 Vin ij i 0.7 Vv threshold a | | Vvec_ | | Hysteresis of input \ voltage. a a Pinl7 = AW | __ 1000 bo 700, mV Pull-down current . Vinn= Vcc Pin 17 Ipp 10 ' 80 uA Serial Interface - Logic Inputs DI,CLK,CS _ | Input voltage low level i Pins 24-26 ; Vin 03 | | Vv threshold fe aL Wee , Input voltage high level Pins 24-26 | Vin 0.7% 5 Vv threshold ee ee _ _ | ol vee | Hysteresis of input voltage ____Pins 24. 26. AM SO 7 _ 500 I mV a PulJ-down current Pin DI, Vow Vek = Vcc Ippsi | 2 | | 50 uA i CLK __ Ping 25,26 | | - Pull- up current Pin cs a " vese 0 VV _Pin 24 Ipusi -50 ! -2 WA Serial Interface - Logic Output DO - ! Output-voltage low level Nov= =3mA Pin!8 =| Vpon i 05 | Vv Output-voltage high level jlo. =-2mA__PinI8_ | Vpon Wee Leakage current Vos = Vee, Ipo | 10 WA (tristate) 2) Delay time between rising edge of CS after data transmission and switch on output stages to 90% of final level. OV<Vpo<Vvcec Pin tI& | Rev. A3, 19-Mar-01 Preliminary Information 215U6815BM ANMEL a WIRELESS & pC Electrical Characteristics (continued) | Parameters Test Timing | Symbol | Min. ' Max. | Unit Conditions Chart No. | | | Serial Interface - timing : DO enable after CS fallingedge |Cpo=100pF | 1 tenpo _| | 200 | ons _DO disable after CS risingedge [Cpo=100pF | 2 | tpispo 200 ns DO fall time Cpo = 100 pF - tpor | | 100 ns bo rise time Cpo = 100 pF - tpor [ 100 ns _ /DO valid time Cpo = 100 pF 10 tpovat | 2000. ns | LCS setup time L 4 te8Sethl 225 ns 'CS setup time Vpo < 8 tcsseth | 225 ts | 0.2 x Vycc , CS high time Input register 9 tcsh 140 ms Bit 14 (SCT) = _ . ee tap | CS high time Input register 9 tcsh 17.5 : | ms Bit 14 (SCT) = | : 1 low | | / | CLK high time _ _ 5 tcLKh 225 | | ns CLK low time _ 6 teri | 2250 es _] CLK period time _ - tCLKp S00 | ns CLK setup time __ 7 tCLKSethl 225 ; ns CLK setup time 3 tcLKSetlh 225 : ns : DI setup time _ 11 tDtset 40 | ns __| DI oldie teens ao 216 Rev. A3, 19-Mar-01 Preliminary InformationAIMEE. U6815BM WIRELESS & pC CS CLK DI CLK DO Inputs DI, CLK, CS: High level = 0.7 x Vcc, Low level = 0.3 x Vcc Output DO: High level = 0.8 x Vcc, Low level = 0.2 x Vcc Figure 4. Serial interface timing diagram with chart numbers Rev. A3, 19-Mar-01 217 Preliminary InformationU6815BM Application Circuit Vee US021M warcHpod hnabh | J Sa Os AIMEL WIRELESS & pC Trigger. | | | | 7 I i | uc valid | 1 Lo poy Hs2/ wel Hs4 [JS = 2 i | I . Ti a | Vs ry] a q i vs 7 1 ; VBAIT ~ = ao - 1BV t _ =) |__4vs oily oH y aa u k le & _ on Register Control uv = ot it ster i Jogic Veo sv Figure 5. Application circuit Application Notes It is strongly recommended to connect the blocking capacitors at Vcc and Vs as close as possible to the power supply and GND pins. Recommended value for capacitors at Vs: electrolythic capacitor C > 22 uF in parallel with a ceramic capacitor C= 100 nF. Value for electrolytic capacitor depends on external loads, conducted interfer- ences and reverse conducting current Is, (see Absolute Maximum Ratings). Recommended value for capacitors at Vcc: electrolythic capacitor C > 10 uF in parallel with a ceramic capacitor C = 100 nF. To reduce thermal resistance it is recommended to place cooling areas on the PCB as close as possible to GND pins. 218 Rev. A3. 19-Mar-01 Preliminary InformationAIME!. U6815BM Package Information Package $O28 9.15 Dimensions in mm 18.05 8.05 17.80 75 73 ie : i A L i 4 H | 1 : | | UL. lanl TT A | Ty | 1 : | Foal 0.254 | 0.25 F| TF 0.10] 10.50 ~ | 16.51 10.20 28 15 LAA AA fA AAA ALE a HUE odo ea og ee I 14 13033 Rev. A3, 19-Mar-01 219 Preliminary Information