M68020UM/AD REV. 2 MC68020 MC68ECO20 MICROPROCESSORS USER'S MANUALIntroduction Processing States Signal Description On-Chip Cache Memory Bus Operation Exception Processing Coprocessor Interface Description Instruction Execution Timing Applications Information Electrical Characteristics Ordering Information and Mechanical Data Appendix A Index a =z =z za Zz 6 Za Zz 10 Cit Zz aIntroduction Processing States Signal Description On-Chip Cache Memory Bus Operation Exception Processing Coprocessor Interface Description Instruction Execution Timing Applications Information Electrica! Characteristics Ordering Information and Mechanical Data Appendix A Index68K FAX-IT FAX (512) 895-8593 The Motorola High-Performance Microprocessor Technical Publications Department provides a fax number for you to submit any questions and comments about this document. We welcome your suggestions for improving our documentation or any questions concerning our products. Please provide the document number and revision number (located in upper right-hand corner of the cover) and the title of the document. When refe. ring to items in the manual, please reference the page number, paragraph number, figure number, table number, and line number, if necessary. When we receive a fax between the hours of 7:30 a.m. and 5:00 p.m. CST, Monday through Friday, we will respond within two hours. If the fax is received after 5:00 p.m. or on a weekend or holiday, we will respond within two hours on the first working day following receipt of the fax. When sending a fax, please provide your name, company, fax number, and phone number including area code.MOTOROLA MC68020 MC68EC020 MICROPROCESSORS USERS MANUAL First Edition Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. 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Motorola and the @ are tegisiered trademarks of Motorola, Inc, Motorola, Inc. is an Equal Opportunity/Atirmative Action Employer, MOTOROLA INC., 1992PREFACE The M68020 User's Manual describes the capabilities, operation, and programming of the MC68020 32-bit, second-generation, enhanced microprocessor and the MC68EC020 32- bit, second-generation, enhanced embedded microprocessor. Throughout this manual, MC68020/EC020 is used when information applies to both the MC68020 and the MC68EC020. "MC68020" and MC68EC020" are used when information applies only to the MC68020 or MC68EC020, respectively. For detailed information on the MC68020 and MC68EC020 instruction set, refer to M68000PM/AD, M68000 Family Programmer's Reference Manual. This manual consists of the following sections: Section 1 Introduction Section 2 Processing States Section 3 Signal Description Section 4 = On-Chip Cache Memory Section 5 Bus Operation Section 6 Exception Processing Section 7 Coprocessor Interface Description Section 8 Instruction Execution Timing Section 9 Applications Information Section 10 Electrical Characteristics Section 11. Ordering information and Mechanical Data Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol NOTE In this manual, assert and negate are used to specify forcing a Signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voltage level (high or low) that they represent. MOTOROLA M68020 USER'S MANUAL ilDocumentation Feedback FAX 512-895-2693: Documentation Comments Only (no technical questions please) httpv//iwww.mot.com/hpesd/docs_survey.html (documentation comments only) The Technical Communications Department welcomes your suggestions for improving our documentation and encourages you to complete the documentation feedback form at the website listed above. Your help helps us measure how well we are serving your information requirements and how well we are transferring the Knowledge you need to be successful with Motorola preducts. The Technical Communications Department also provides a fax number for you to submit any questions or comments about this document or how to order other documents. Please provide the part number and revision number (located in the upper right hand comer of the cover) and the title of the document. When referring to items in the manual, please reference the page number, paragraph number, figure or table number. Please do not fax technical questions to this number. When sending a fax, please provide your name, company, fax number, and phone number (including area code). For Internet Access: Web Only: http:/Avwww.mot.com/aesop For Hotline Questions: FAX (US or Canada): 1-800-248-8567 iv M68020 USERS MANUAL MOTOROLAMC68020/EC020 ACRONYM LIST BCD Binary-Coded Decimal CAAR Cache Address Register CACR Cache Control Register CCR Condition Code Register CIR Coprocessor Interface Register CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit CQFP Ceramic Quad Flat Pack DDMA Dual-Channe! Direct Memory Access DFC Destination Function Code Register DMA Direct Memory Access DRAM Dynamic Random Access Memory FPCP Floating-Point Coprocessor HCMOS High-Density Complementary Metal Oxide Semiconductor IEEE Institute of Electrical and Electronic Engineers SP Interrupt Stack Pointer LMB Lower Middle Byte LRAR Limited Rate Auto Request LSB Least Significant Byte MMU Memory Management Unit MPU Microprocessor Unit MSB Most Significant Byte MSP Master Stack Pointer NMOS n-Type Metal Oxide Semiconductor PAL Programmable Array Logic PC Program Counter PGA Pin Grid Array PMMU Paged Memory Management Unit PPGA Plastic Pin Grid Array PQFP Plastic Quad Flat Pack RAM Random Access Memory SFC Source Function Code Register SP Stack Pointer SR Status Register SSP Supervisor Stack Pointer SSW Special Status Word UMB Upper Middle Byte USP User Stack Pointer VBR Vector Base Register VLSI Very Large Scale Integration MOTOROLA M68020 USER'S MANUALParagraph Number a saa NOOMO B&D Nm 2.1 2.1.4 2.1.2 2.1.3 2.2 2.3 2.3.1 2.3.2 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.14 MOTOROLA TABLE OF CONTENTS Page Title Number Section 1 Introduction POALUTCS oooosscicesssstersssteesssssseesnnstietesesscissnesiuavistasitieeee 1-2 Programming Model... sees 1-4 Data Types and Addressing Modes Overview oo. occ 1-8 Instruction Set OVerView oo. 1-10 Virtual Memory and Virtual Machine Concepts oo. ccccceeceeeecees.. 1-10 Virtual MeMOry oo... ccecseststittee neritic 1-10 Vital Machine... cesses 1-12 Pipelined Architecture... occ 1-12 CACHE MEMOLY 0... seeetecescccnssestinsetisenentineie 1-13 Section 2 Processing States PriVHEG@ LOVEIS oss. essseccecssesssstusnseesecvsssninvestetissesetiteiesesee 2-2 Supervisor Privilege LeVEl os ceccseececcsesneen 2-2 User Privilege LeV@l i sesecccissssesisinniiin 2-3 Changing Privilege Level... 2-3 Address Space Types oo... cesses 2-4 Exception PROCESSING... seeccccccsceeeisiitiini 2-5 EXCeption VECIOIS 0. oeeeceeseccssessteeinesininntin 2-5 Exception Stack Frame oo. ..cseeeseecn unin 2-6 Section 3 Signal Description SIGMA! INDEX ae cseeecetteensessstsnssensssnvnstinsninesseieseeeeteeeecc 3-2 Function Code Signals (FO2-FCO) one ccc reesecseeseseeee 3-2 Address Bus (A31~A0, MC68020}(A23-A0, MC68EC020) ooo. 3-2 Data Bus (O39-D0) o.oo ccccscseseueeteesienstiianncee 3-2 Transfer Size Signals (SIZ, SIZO) ccc cesses. 3-2 Asynchronous Bus Control SIQMANS oo cece cece tesce estes, 3-4 Interrupt Control SIM AIS ee eee eeecec cessanvenseevtttnieeee 3-5 Bus Arbitration Control! SHQMANS ooo cca tcetentesteeteete 3-6 Bus Exception Control SIQMANS oo cetera eee 3-6 Emulator Support SIQNAD ees cecs ccerest esc epee 3-7 CHOCK (CLK) osc cecc cc enser scent 3-7 M68020 USERS MANUAL vilParagraph Number 3.12 3.13 4.1 4.2 4.3 4.3.1 4.3.2 aqgaaanan sea a aa NOOB Wh 4 5.1 5.2 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.3 5.3.1 5.3.2 .3.3 5.4 5.4.1 5.4.1.4 .4.1.2 5.4.1.3 5.4.2 3.4.3 5.5 5.5.1 vill TABLE OF CONTENTS (Continued) Page Title Number Power Supply Connections 00.0... rece erence eee e ree esen tenet tena 3-7 Signal SUMMALSY 0.0.2... ccc cc cecceceeeneeeetaeee testes ce receesteeeensttenteneeen 3-8 Section 4 On-Chip Cache Memory On-Chip Cache Organization and Operation ........00 eee eee 4-1 Cache Reset ..........cccccccccccceceecececesneeecneseeetnseteceteceeeseaeeecisttersiteeseeieeens 4-3 Cache Control 0... ccc ccecececeeseeneceeeeseneeeeseasesaeeeeeeneeciteeeeeeeniaseeertsvnees 4-3 Gache Control Register (CACR) 000... cee reece ce ctteneeeeeeseteeeeeensaes 4-3 Cache Address Register (CAAR) .............cccccececccccececcepectcrneecenrnsanerees 4-4 Section 5 Bus Operation Bus Transf@r Signals... ccc ccc ccceccccetecceaeeeeeteneeteececesessetentenaseeeeneas 5-1 Bus Controt Signals... ee cece eee cee eeeseteneeereeeecnereseeesceeenneeanes 5-2 Address BuS 2.0.0.0... ccc cccceccee cere eeneecnnaeeeeeeeeeeeeeeeeteepeesesscnnieaeeeeeeeterey 5-3 Address Strobe oo.......o cece ccccceeceneecneeeceeeeeeeeataeeenteaeeeseaeeetetieseenaseseeaes 5-3 Datta BUS oo... cece cence ccecene nese cecncaeeeeceesgnneeeeneeceessaeeeessctsaeeesenenees 5-3 Data Strobe ooo. ceececcceee ee ce ecneeeeeeceeaeeeeeseneenceeesesseensereeentines 5-4 Data Buffer Enable oo... cece ceccnee cece eeccneeeeeeeeteeeeteeecnaeetesseaes 5-4 Bus Cycle Termination Signals ......0..........cc eee seenteceeseererseteenees 5-4 Data Transfer MeChanisMm ..........c ccc enn eecteneeetetaaeeeseatacersseeecteeee ies 5-5 Dynamic Bus SiZing.......... cece ce eeseceeeeeer ence ce eeeeeaneneaeesseaeeeeenicaeees 5-5 Misaligned Operands... ce cceeerecnenreeeee entre eeeeeeeetnaseteeerniieeenenes 5-14 Effects of Dynamic Bus Sizing and Operand Misalignment ................ 5-20 Address, Size, and Data Bus Relationships ..........0... cc ceee ees 5-21 Cache Interactions 2.2.0... ccc cccccccecceeeeeneeeeeeeeeeesesrecteesavassstatesenteeseninees 5-22 BUS ODGration....... cc cecscesscsscsesecseseeereseeeeeveseesecausesasanessaesseeraseseeeeeesrees 5-24 Synchronous Operation with DSACK1/DSACKO............ es 5-24 Data Transfer Cycles 00... c ccc ccccecee cece ete ee entree ces ta eeeeeeeeeeeeeteeeenees 5-25 Read CYCle ooo. cceccscecetscceecccsaseccsecseeneeseeseeeeeesseesetusssencecsnersnaceetened 5-26 Write Cy Cle o.oo. c cece cee cee cere eee e cece cere cbt Os tata ta nana sae aeaeateeeeyenee ees 5-33 Read-Modify-Write Cycle i ccccnceeeeceeneneeeeeeececnneeeeeeeteaeeseeenaes 5-39 CPU Space Cycles ooo cc cette tenses tectaeteprtaceresaeeesnaeeernneeens 5-44 Interrupt Acknowledge Bus Cycles ........0.0.. cee eee centerenreenteeee: 5-45 Interrupt Acknowledge CycleTerminated Normally .........000....00.5 5-45 Autovector Interrupt Acknowledge Cycle... ees 5-48 Spurious Interrupt Cycle 0... ee eeeeteceeeeeceeeeceeeeeeeesneteeseneees 5-48 Breakpoint Acknowledge Cycle... ccc cctcceeeeceeeeerseeeneeentsentenens 5-50 Coprocessor Communication Cycles oc ceeeccsnecetteeeeneen 5-53 Bus Exception Control Cycles oo... ee cece cee rte treenneteetcneey 5-53 BUS Errors... ccccecceeceecteeeceeeeeecteeetsateseseneeeciaeeeceesaeeseceeeseeeenseees 5-55 M68020 USER'S MANUAL MOTOROLAParagraph Number 5.5.2 5.5.3 5.5.4 5.6 5.7 5.7.1 5.7.4.4 5.7.1.2 5.7.1.3 5.7.1.4 5.7.2 5.7.2.1 5.7.2.2 5.7.2.3 5.8 MOTOROLA TABLE OF CONTENTS (Continued) Page Title Number Retry Operation eo ecccccessesssseesssesneetteresviessiesettetteeeec 5-56 Halt Operation... ccecccccccceceesstesieeesietinentce 5-60 Double BUS Fault... cecsseesesssessessessnnttetsttiittiee 5-60 Bus Synchronization .......ccccccscsssssssssnennneieie 5-62 Bus Arbitration... .eeecesceecccceisissetnneesesecieeniiiiiini 5-62 MC68020 Bus Arbitration 0.0... cccccecceeeeeeeeeeec 5-63 Bus Request (MC68020) ooo. ees eccccee ccsesssteeseetetcteeteecseteee 5-66 Bus Grant (MC68020) 00... sesssesescssesesssststttiosnsis 5-66 Bus Grant Acknowledge (MC68020) oon cecccccceeeeeeece. 5-66 Bus Arbitration Control (MC6B020) oo ecccceetee eee. 5-67 MC68EC020 Bus Arbitration... eects 5-70 Bus Request (MC6BEC020) occ ceseesseceretsneeseessseceeesesec 5-71 Bus Grant (MCG6BECO20) ooo ese cccsstecssecnsesetecsseteseeeeee 5-71 Bus Arbitration Control (MC68EC020) oo. ccccecccceeeececc -73 Reset Operation ose ceecscsnssssttttninnsniiis 5-76 Section 6 Exception Processing Exception Processing Sequence..........-ccccsssssssseussessseeeceeee 6-1 Reset Exception .........ececccccunensnnsseneseeciininc 6-4 Bus Error Exception ..........cceccccseessesostsiiiini cc 6-4 Address Error Exception 0... 6-6 Instruction Trap Exception o.oo... oscuro 6-6 Hllegal Instruction and Unimplemented Instruction Exceptions ..........., 6-7 Privilege Violation EXCEPtion oc cescescccnsessesestecsseeeeec 6-8 Trae EXCOHOM .....sssseccetesesccessessseetitinuncnnstiiii 6-9 Format Error Exception... cesses 6-10 Interrupt Exceptions 0.0.00. eseeseecsciueei 6-11 Breakpoint Instruction EXCEPtiON oo ees testeeressessesceeee cece, 6-17 Multiple Exceptions... sssseccsssnsssseseescitntitiic 6-17 Return from Exception 00.0.0... 6-19 Bus Fault RECOVErY 0... sesessccsseitesssestsseeeueeinni 6-21 Special Status Word (SSW) ose cee eesseesateesestesteseteveaseseeeereecce. 6-21 Using Software to Complete the Bus CYCIES occ ceeeceeteseeee, 6-23 Completing the Bus Cycles with RTE o.oo. 6-24 Coprocessor Considerations... eee 6-25 Exception Stack Frame Formats .......2::cccccsccusen 6-25 M68020 USER'S MANUAL ixTABLE OF CONTENTS (Continued) Paragraph Page Number Title Number Section 7 Coprocessor Interface Description 74 IMEFOCMUCTION 20... eceseeteseevevecauseseesetsesererssetntntrsnitestetesseeeessreees 7-4 7.1.1 Interface Features ooo... ccc cccesececetevecsevevsutuuesususscsececaeeeaeeaeerens 7-2 7.1.2 Concurrent Operation Support 000000 cess seseseevevevsnneneees 7-2 7.1.3 Coprocessor instruction Format ..0.......00000.cccc eee ceseresseeeetsnssseveseenees 7-3 7.1.4 Coprocessor System Interface oo... ccc ccc cece sectennnratens 7-4 7.1.4.1 Coprocessor Classification 20.0000... ccc cc ccceseceeeeesssueserstscesevenneneerens 7-4 7.1.4.2 Processor-Coprocessor Interface 0.0.0.0... 0.00 eccceceececececeeveveeseneeeess 7-5 7.1.4.3 Coprocessor Interface Register Selection 20.00... 7-6 7.2 Coprocessor IMStruction TyP@S .......cccccccccccssececccsccecseccensesesecntevesevennans 7-7 7.2.1 Coprocessor General INStructions 0.0.0.0... ccc cece cece cccceceuaeerernraes 7-8 7.2.1.1 FOr at. eee cece eeepc ere cnr te nr P ee ce eeeeeevevcesosessssteeeeteseveveesennenas 7-8 7.2.1.2 8) 0] 0) ce 7-9 7.2.2 Coprocessor Conditional Instructions ......00.....0. cc cecsccsseececeseceeeeeeeees 7-10 7.2.2.1 Branch on Coprocessor Condition Instruction oo... ees 7-12 7.2.2.1.1 FOAL oii cee eeeteeeencaceeecataeeesiseeesssseseeeusatcnceesesreesensaeentnaes 7-12 7.2.2.4.2 Protocol 0... ccc cceceeceecceceeeeeseeseeaeeesecenecsecccetseasutetsiesaveeennntats 7-12 7.2.2.2 Set on Coprocessor Condition Instruction .......000000. ccc cee cseeeeeeeee 7-13 7.2.2.2.1 FOPIMAL ooo. cc cece cece eeneeecccveeesecesceesucseseuessansesevevvavevsuneneeerereaes 7-13 7.2.2.2.2 PROLOCON ce cceccecepecceeepeesettcaeeuseessssueeeressssauescscnecessessenaverss 7-14 7.2.2.3 Test Coprocessor Condition, Decrement, and Branch Instruction... 7-14 7.2.2.3.1 FOPIMAR ec ccc ececececs cece caeaeceseseesesentersustuvanauseveuepeeenercerenes 7-14 7.2.2.3.2 ad 0) (01916) ce 7-15 7.2.2.4 Trap on Coprocessor Condition Instruction 0.0.0.0... ccceceeeseeceseeeeees 7-15 7.2.2.4.4 FOPIMAR oe. ec ee eee ecceereeesecececetenssananseseseueusesusesestcncrsetseteseeaeanentrteres 7-15 7.2.2.4.2 PrOtOCO ooo. ccceece sees ccceeeeesesseeeecscecusceeeccevstaaareveavatenesensnars 7-16 7.2.3 Coprocessor Context Save and Restore Instructions.............c..e 7-16 7.2.3.1 Coprocessor Internal State Frames ..00..00000000.00..ccccccccecscceecececnteeees 7-17 7.2.3.2 Coprocessor Format Words.........ccccccecsccscsssssececserscececstsecesceeneteees 7-18 7.2.3,2.1 Empty/Reset Format Word .0.0.000........cccceccccecccreeseecccsecersutstneeeeeess 7-18 7.2.3.2.2 Not-Ready Format Word ......cccccccccccccccecceceseccsssessssscssecevevevsnneererats 7-19 7.2.3,2.3 Invalid Format Word 0.0.0... cccccccccccccccecseeceneueecrsceeeenneessnaeeetneers 7-19 7.2.3.2.4 Valid Format Wo0ld............ccccccccccscceseseeeceecsesecsessteceesseeececanaeserentae: 7-20 7.2.3.3 Coprocessor Context Save Instruction ..0..00.0000 0 cccccceseseseceeesenees 7-20 7.2.3.3.1 FOrMat ooo... eee cceeccceeeraesesecteceeeeeevesssssueeesscssaeecevecereenessnentneseess 7-20 7.2.3.3.2 PrOtOCOl cece icc cee cece cnteceteeecurruuevereeevteeesttesttstevevereaes 7-21 7.2.3.4 Coprocessor Context Restore Instruction 200000000 eerrere 7-22 7.2.3.4.1 Format 000.00. ee cern reneees cee teeeeeeeteeeecesttncuseeaaeeeeeeess 7-22 7.2.3.4.2 PrOtOCON ice cec ccc eceecceteecceceteverevevvesseseeeseesecyenrsvmrtsrianesess 7-23 7.3 Coprocessor Interface Register Set... ccccereeerreriees 7-24 x M68020 USERS MANUAL MOTOROLAParagraph Number 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 7.3.11 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.45 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.4.12 7.4.13 7.4.14 7.4.15 7.4.16 7.4.17 7.4.18 7.4.19 7.4.20 7.5 7.5.1 7.5.1.4 7.6.1.2 7.5.1.3 7.5.1.4 7.5.1.5 7.5.2 7.5.2.1 7.5.2.2 MOTOROLA TABLE OF CONTENTS (Continued) Page Title Number RESPONSE CIR oi ceeseceeesccseeretneenaresreseciteseeeeteetee ces 7-24 COMtrol CIR oe cee cece eeeeees cesses teeceveeeevene cc ctieeteeteeee ec 7-24 SAVE CUR oc cee cence ecssessetesssterceresevesecsesseesesene verte tees 7-25 Restore CIR once ccseses ess ensseuevs teste veseesess cs cette ieee 7-25 Operation Word CIR ooo ccccccccessceretessteesteveeseettetetec 7-25 COMMANA CIR o.oo cc ccc cccestesseeveesesetereesess cates ceteeteeteeeee cc 7-25 CONdition CIR one cee cc cee cece csssesstnsesrenteacetettenttieeete 7-26 Operand CIR. ce cee csessesceseseveeettn estes ccieivestetetet 7-26 Register Select CIR oo... icc sc uececes testes eteceseettheeee 7-27 Instruction AddrSS CIR o.oo ceccccccccccscestecsccseeesestbteeetee 7-27 Operand Address CIR ooo... cccccccccscccseeeeee cet eeteiteete 7-27 Coprocessor Response Primitives ....0.....00.cccccsccccsccsccsteeceeseeeeeeec 7-27 SCAMPC oo ccc ccc ees csee ss cantesseescessosevaeitetstattssiteteteie sc 7-28 Coprocessor Response Primitive General Format........00.... 0... 7-28 BUSY PriMitive oo. e ccc ccc ccsesserscssessesstssrertetesvereseestesettessetecce 7-30 NUW Primitive cc cesesseesessececsssesnssttscssesetattreiseeteteeccec 7-31 Supervisor Check Primitive... ccccccccccssceescseeeeccscesesseeeteeseseeescc. 7-33 Transfer Operation Word Primitive ....c..c.cccccsecccccccsssssessseseeesescc 7-33 Transfer from instruction Stream Primitive ..0..cccccccccccccccecccc 7-34 Evaluate and Transfer Effective Address Primitive... 7-35 Evaluate Effective Address and Transfer Data Primitive... 7-35 Write to Previously Evaluated Effective Address Primitive... 7-37 Take Address and Transfer Data Primitive...-...eccccccccccccccseees 7-39 Transfer to/from Top of Stack Primitive ..0..00.0ccccccccsccscecceececeeec cc, 7-40 Transfer Single Main Processor Register Primitive o.oo... 7-40 Transfer Main Processor Control Register Primitive... 7-41 Transfer Multiple Main Processor Registers Primitive ................... 7-42 Transfer Multiple Coprocessor Registers Primitive... 7-42 Transfer Status Register and ScanPC Primitive... 7-44 Take Preinstruction Exception Primitive ...0..0..0.0 ccc occccecceecseeeec. 7-45 Take Midinstruction Exception Primitive ......0.cccccccccccecccccece 7-47 Take Postinstruction Exception Primitive 0.0.00. 7-48 EXCOPLIONS 2. cee tess cssecsesesesrensreseettntitestcevtsteeteeteenc 7-49 Coprocessor-Detected Exceptions oo... ceccccccccceccccsececeeeeeee 7-49 Coprocessor-Detected Protocol Violations ........00..cccccc 7-50 Coprocessor-Detected Illegal Command or Condition Words ......... 7-51 Coprecessor Data-Processing-Related Exceptions wo. 7-51 Coprocessor System-Related Exceptions... cccccceseeeeccceee 7-51 Format Errors ooo... ecccccccccstsestestesteeeseeetnt ee coeeteibieeee ee 7-52 Main-Processor-Detected EXCeptions oo ceeeeccccescsereecee, 7-52 Protocol Violations oo... cccececseseseesesstee cscs se cteceteeceeee 7-52 F-Line Emulator Exceptions v0.0.0. cccccccsccceeceececcceeseseeeecee 7-54 M68020 USER'S MANUAL xTABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 7.5.2.3 Privilege ViOlatiONS o.oo. cece cee cseeetesteeecstevevvanssseaetatetevnees 7-55 7.5.2.4 cpTRAPcc Instruction Traps 2.0.0.0. cceeseeeceeeceesceeesecseeseeesies coe 7-55 7.5.2.5 Trace Exceptions 2.0... cece cececeetevevetettetertttteesieieseeenes 7-55 7.5.2.6 INROPPUPtS ooo ccc ces ecceveervesveserescesseravevtatentiecettevittessietteeees 7-56 7.5.2.7 Format Errors oo... ccecceccccccccccesscescecsccececreveaeturesusceessvavevsetitevsaseeaee. 7-57 7.5.2.8 Address and Bus Errors.........cccc0ccccccceseuseutessesecsseveseeeseevsttenasecses 7-57 7.5.3 Coprocessor ReSet occ cccccccccccececccsseeseeeesuassuacecescerevesevcetetaeeneees 7-58 7.6 COPPOCESSOF SUMMALY occ cece cc ccececeseceeseveeuuaeevsssesscrssvnerstevaaeenanes 7-58 Section & Instruction Execution Timing 8.1 Timing Estimation Factors... ccc ccccscsecescccececsescreceuueessetcccssceveeeeeee 8-1 8.1.1 instruction Cache and Prefetch .....000.00cc cece ceccceccvesesersesssesseseeeeee. 8-1 8.1.2 Operand Misalignment ......0.00.0 ccc cccesecarseeecececesecesecsesaersesenevevseesse 8-2 8.1.3 Bus/Sequencer Concurlency .....0...0.00.00ccecsceseescusecsescetaceueevsseececcctieses 8-2 8.1.4 Instruction Execution Overlap... ccceccecccsccssesscceeveeseesssecsevscereees 8-3 8.1.5 Instruction Stream Timing Examples ..........cccccccccesscecccseseescsevevseses 8-4 8.2 Instruction Timing Tables ooo... ccccccetecscccccseespesssvantseevsecsetateaneases 8-9 8.2.1 Fetch Effective Address... cc cccccccccscecesereeersecseecseeeseccesvsseasecaesnes 8-13 8.2.2 Fetch Immediate Effective Address .o.........cccccccecceesecssvesesecseceseesees 8-14 8.2.3 Calculate Effective Address... ccccssseseccecesceseersesenevnsrsees 8-16 8.2.4 Calculate Immediate Effective Address 000.00. icecccceeeeseceeceeceees 8-17 8.2.5 Jump Effective Address... ccc ccc cccceecnrevetusnsseessterseceuraeerusesns 8-19 8.2.6 MOVE Instruction oo... ccc cece cscs scesscscevevereeeensecestecsssevsuveraneavaseses 8-20 8.2.7 Speciai-Purpose MOVE Instruction ....0..0ccccccecceccsceceevcccccccsscececeveceess 8-29 8.2.8 Arithmetic/Logical Instructions ...........cccccccccccceeeeceeceesetecccccreereeevens 8-30 8.2.9 Immediate Arithmetic/Logical Instructions ....0..0..0.. oc ccecccccseeeeeeeees 8-31 8.2.10 Binary-Coded Decimal Operations 2000.00.00... ccc icesecccceccececcccceveceeseceeeseee 8-32 8.2.11 Single-Operand Instructions ..0...00.00.0. oe cceeceecccccceececcsscetsuseseccessevereees 8-33 8.2.12 Shift/Rotate Instructions 00.0.0... ccc cecceeececneeaccsseseecsevseesseaeeievenes 8-34 8.2.13 Bit Manipulation Instructions 0.00.00... cccccecssecececesscccssectecccaccevensevees 8-35 8.2.14 Bit Field Manipulation Instructions ....00...000ccl ccc eccesesceseesteececeee, 8-36 8.2.15 Conditional Branch Instructions ..00...00000.0 ccc ccecceceesesseeeceseeceseeeeeeees 8-37 8.2.16 Control INStructions 0... cccccccsscccceccesscesveeceesvescreessssetssesaececvaveaseeueves, 8-38 8.2.17 Exception-Related Instructions ....00.000000 ccc cece cece ccc cteccccceteeeeeees 8-39 B.2.18 Save and Restore Operations ..0..00.0.0c cc cececeeeeeeereee ceecveeetenees 8-40 Section 9 Applications Information 9.1 Floating-Point Units ooo. ccccceeeececcccececeeesseseeceterrtereteeesosesteeeneyeys 9-1 9.2 Byte Select Logic for the MC68020/ECO020 0 icc cceccece cece. 9-5 9.3 Power and Ground Considerations .......000000.0.cccccceccececcecceececcecetectveee 9-9 xii M68020 USER'S MANUAL MOTOROLATABLE OF CONTENTS (Concluded) Paragraph Page Number Title Number 9.4 CLOCK DEVE eee cece ense tess cess ssssnsestneneseveeseestetuessetesebee sees 9-16 9.5 Memory Interface oo. cece esse eensessettes eset eves. 9-114 9.6 Access Time Calculations oo... ccc ce ceetesetete ces ceseeeceeeeeee 9-12 9.7 Module Support... cece cc esse teentesversnvstitstieteeiteete 9-14 9.7.1 Module Descriptor... oe esses sesteeeetiretettee 9-14 9.7.2 Module Stack Frame... ccc ccccecccsetesesseerteeteseeeveteeseeeeec 9-16 9.8 ACCESS LOVENS ooo cee eeeseensesssssterressesntttettavesaseeeeeeeecec 9-17 9.8.1 Module Calc cece esses ecennaeurvevsetestsvesseaseeteeteiteiteeecee 9-18 9.8.2 Module Return oo oe cececcssecseessisssecerssstesattetterccsteteeeteese 9-19 Section 10 Electrical Characteristics 10.1 Maximum RatingS. 00.0.0... cece cccsessscesseesteenteseeeseesteneee eee 10-1 10.2 Thermal Considerations 2.02.0... coc cccessspestesstesseesecstesseseeeecee 10-1 10.2.1 MC68020 Thermal Characteristics and DC Electrical Characteristics....0..00.00..0ccccccsssessecssssesceeceeeccccccccsc, 10-2 10.2.2 MC68EC020 Thermal Characteristics and DC Electrical Characteristics ..00..0..0..cccccscscstesessccsssseeteseteecee cece, 10-4 10.3 AC Electrical Characteristics 00.00.00... ccc cesesccessesseeescesrseetee 10-5 Section 11 Ordering Information and Mechanical Data W144 Standard Ordering Information 0.00.0... c.cccccecsecssesscecscesteeeeceeece 11-1 11.1.1 Standard MC68020 Ordering Information ....0....ccccccceccceccc 11-1 11.1.2 Standard MC68EC020 Ordering Information 0.0... ceccccccccceecccceee. 11-1 11.2 Pin Assignments and Package DimensionS ......0..c.-cc-cccccccecceeccccs 11-2 11.2.1 MC68020 RC and RP SuffixPin ASSIQNMENE oo... ccececcceseeece. 11-2 14.2.2 MC68020 RC SuffixPackage Dimensions....00..00.0.- ccc. 11-3 11.2.3 MC68020 AP SuffixPackage Dimensions... ccc ccecccccceccce 11-4 11.2.4 MC68020 FC and FE SuffixPin ASSIQNMENE 0... ccccccccceeees 11-5 11.2.5 MC68020 FC SuffixPackage Dimensions ....0.0000000000 11-6 11.2.6 MC68020 FE SuffixPackage Dimensions ...........000000000.. 11-7 11.2.7 MC68EC020 RP SuffixPin ASSIQMMENE oo. cececceretseceseeees 11-8 11.2.8 MC68EC020 AP SuffixPackage Dimensions......................... 11-9 11.2.9 MC68EC020 FG SuffixPin Assignment... ooo ccccccccccccoeecec 11-10 11.2.10 MC68EC020 FG SuffixPackage Dimensions.................0....... 11-11 Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol MOTOROLA M68020 USERS MANUAL xitiFigure Numbe 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-24 5-22 5-23 xiv LIST OF ILLUSTRATIONS Page r Title Number MC68020/EC020 Block Diagram .......00.0cccccccccccccccccevceecutcecevceeersrseetsecenecensees 1-3 User Programming Model .....0...0..cccccccscccccececesseeceescesseecneesesueesssenseeneseunecaeesas 1-5 Supervisor Programming Model Supplement .............0..0ccccceccecececserseseenereeeee 1-6 Status Register (SR) oo... cece cecccsccscesecceceteessseeescsesesteesssatsuacereseseceeeessereeaey 1-7 INStFUCTION Pipe o.oo... ec ccc cccnnecceseeseeesssseecessgecssececvrsreeeeparssevenssaeeentneceeeees 1-13 General Exception Stack Frame ......c..ccccccccccecsecescecesccesccaecesecsecenevnecvareareaesars 2-6 Functional Signal Groups .........ccccccccescccsessecssecsessesessesccsccsscesccseccsavessvaeeensaesate 3-1 MC68020/EC020 On-Chip Cache Organization ...........c0ccccccccceccseesecrsceserernees 4-2 Cache Control Register ........cccccccccccccccesesesescecesseeeneesessesseerscssnsetensusenesnseetesess 4-3 Cache Address Register... ccc ccc cccecccccscceccescsessessseesaueessnsnsssauevaneesaee vas 4-4 Relationship between External and Internal Signals.............000.cccseesesseseereees 5-2 Input Sample Window ooo... ccc ee cceeseceneeecesserersessteersrssecaeeneenesecssenssneceseeseeess 5-2 Internal Operand Representation ............cecccccssceeccccecececescnersesesessneeeaneasneees 5-6 MC68020/EC 020 Interface to Various Port SiZ@S .......cccccesssetcceeeeeeeeeees 5-6 Long-Word Operand Write to Word Port Example........0..0.ccececcceeeeceseseee ees 5-10 Long-Word Operand Write to Word Port TIMINg........ccccccsseeesesesceeeeseeecereee 5-11 Word Operand Write to Byte Port Example oo... ccc cceceeceseesceeesscsceescneees 5-12 Word Operand Write to Byte Port Timing..............0ccccccccccccensevescsaretesnseneassaes 5-13 Misaligned Long-Word Operand Write to Word Port Example .......0000000.... 5-14 Misaligned Long-Word Operand Write to Word Port Timing.......0.0.000..000.0.e 5-15 Misaligned Long-Word Operand Read from Word Port Example ........0000000.... 5-16 Misaligned Word Operand Write to Word Port Example..........0...cccceeeeen 5-16 Misaligned Word Operand Write to Word Port Timing...........0000. ccs eres 5-17 Misaligned Word Operand Read from Word Bus Example...........ccccceeee 5-18 Misaligned Long-Word Operand Write to Long-Word Port Example ............... 5-18 Misaligned Long-Word Operand Write to Long-Word Port Timing ................. 5-19 Misaligned Long-Word Operand Read from Long-Word Port Example........... 5-20 Byte Enable Signal Generation for 16- and 32-Bit Ports......0.00.00000 ee 5-23 Long-Word Read Cycle Flowchart ........ccccccccccceceeceescnececeeesececeevausuvevsevanvavas 5-26 Byte Read Cycle Flowchart ............ccccscccccssccecsscsscsevsecsecsscsussesassescsucsesaueeevaees 5-27 Byte and Word Read Cycles32-Bit Port ....0....0ccccccccccesetecsecseessseensseestenes 5-28 Long-Word ReadB-Bit Port 00.0.0 ccccccccecccccseccccecsccsscecsesevesecauevsavesaeeesaseass 5-29 Long-Word Read-16- and 32-Bit Ports ..0.00..00.000ccccccccecececneecneesseereenreceens 5-30 M68020 USER'S MANUAL MOTOROLALIST OF ILLUSTRATIONS (Continued) Figure Page Number Title Number 5-24 = Write Cycle Flowchart .0000..0ccc ccc cceecececcccsceseecreceseseattesesesensesvtteesenneeteec. 5-33 5-25 Read-Write-Read Cycles32-Bit Port ...0...00.0 ccc ccccessccsceseeesveccecesseseueeeeeces 5-34 5-26 Byte and Word Write Cycles32-Bit Port ..0...0.00..0coccoccececsccccescceceesecesevsevecces 5-35 5-27 Long-Word Operand Write8-Bit Port.....000.00occcocccccccccsecsecesseeeeccuseeveeeurenvens 5-36 5-28 Long-Word Operand Write16-Bit Port... ccccccecececcseeceteeueeseesceesees 5-37 5-29 Read-Modify-Write Cycle Flowchart .....0..0.c0cccccccccceccsecsenscesstevsccsssecsseneseueuneres 5-40 5-30 Byte Read-Modify-Write Cycle32-Bit Port (TAS Instruction) ...0.000.0cc 5-41 5-31 MC68020/EC020 CPU Space Address Encoding oo... cccececcccceseseseeseerees 5-45 5-32 Interrupt Acknowledge Cycle Flowchart .0..0.00...0ccccccccceseeecesesatesveceesesesseseses 5-46 5-33 Interrupt Acknowledge Cycle Timing .........0.c..cccceecesecccaceeseesesuscescececeseeserrseans 5-47 5-34 Autovector Operation TIMING... coe eee ccccesececceseesssevececcsevressrastrsevecseeseees 5-49 5-35 Breakpoint Acknowledge Cycle Flowchart ...0000.00.00..ccccccccecsecsevesesecsscsseseeee, 5-50 5-36 Breakpoint Acknowledge Cycle Timing ........0....0.cccccccessstsecccssscssesescessssserevece. 5-51 5-37 Breakpoint Acknowledge Cycle Timing (Exception Signaled) ...........ccccccececee- 5-52 5-38 Bus Error without DSACK1/DSACKO 0... cece eeecesecseeceecsecessessveuteusenssuey 5-57 5-39 Late Bus Error with DSACK1/DSACKO....o.. occ cccccccecccsceecesecerscesevsseseseseses 5-58 5-40 Late Retry... cece cceserestesusnestesssseseesrsvstevastsausavatsascceseyaseieeneeses 5-59 5-41 Halt Operation Timing 2... cccccceseceseescsccavecsessccecrserssecnssesasvavssecesscsstaseesees 5-61 5-42 MC68020 Bus Arbitration Flowchart for Single Request .........ccccccccccscccesseeseees 5-64 5-43. MC68020 Bus Arbitration Operation Timing for Single Request ..............00000..- 5-65 5-44 MC68020 Bus Arbitration State Diagram oo... 00 ceccesececsececececseeseseesescaveee 5-67 5-45 MC68020 Bus Arbitration Operation Timing---Bus Inactive ........0...cccccccessessees 5-69 5-46 MC68EC020 Bus Arbitration Flowchart for Single Request ...........cccccsseceseeees 5-71 5-47 MC68EC020 Bus Arbitration Operation Timing for Single Request ................. 5-72 5-48 MC68EC020 Bus Arbitration State Diagram o.oo... cece ccceseceecccaccecsceeseseeses 5-73 5-49 MC68EC020 Bus Arbitration Operation TimingBus Inactive .............ccccc. 5-75 5-50 Interface for Three-Wire to Two-Wire Bus Arbitration 000.00 c cc ccccccccesccceees 5-76 5-51 Initial Reset Operation Timing ooo... cece ceececerseseeseessesecssecssesareceecsssusesacacees 5-77 5-52 RESET Instruction Timing 0.0.20. ec ccccccccceccsecscscsevseeseseseatauseecceesvesvecteseeseseees 5-78 6-1 Reset Operation Flowchart... cececccccccccescessesveasesesesscecssteseeeesersseessces 6-5 6-2 Interrupt Pending Procedure o.oo... cceeccccccscccsessesscesenscuaeensecsescsucsecunesevenvaveas 6-12 6-3 Interrupt Recognition Examples ............ccccccccccsccsecsccssesvesessessecsesssserecseeseyegs 6-13 6-4 Assertion of IPEND (MC68020 Only)... ccc cesvesescnsvsecsenaeecereeevessesaess 6-14 6-5 Interrupt Exception Processing FloWChAar .........ccccecccccccsceesseeesseceseeecusecececseeee 6-15 6-6 Breakpoint Instruction Flowchart .....00..000000ccccccccccesecsccsecscevsecsuecsecscceversuaueaneess 8-18 6-7 RTE Instruction for Throwaway Four-Word Frame ..........ccccscccsesccecesseseseseeeees 6-20 6-8 Special Status Word Format ...0.....c.ccccccccescseessessesvsseseceecaeseeesevasvaseeceeseeseatees 6-22 7-1 F-Line Coprocessor Instruction Operation Word .....0..0.0...cccccecsecsceseccesseseenseueees 7-3 7-2 Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage......... 7-5 7-3 MC68020/EC020 CPU Space Address Encodings ............cccccccccscceceecececeeeeeees 7-6 MOTOROLA M680206 USER'S MANUAL xvFigure Numbe 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 7-38 7-39 7-40 7-41 7-42 7-43 7-44 xvi LIST OF ILLUSTRATIONS (Continued) Page r Titie Number Coprocessor Address Map in MC68020/EC020 CPU Space 0.0... ecco. 7-7 Coprocessor Interface Register Set Map o...........cecccececcecccecccececceccccecceseeceeeec. 7-7 Coprocessor General Instruction Format (CAGEN) .......ccccccccccccccecccecececececesee. 7-8 Coprocessor Interface Protocol for General Category instructions.................. 7-10 Coprocessor Interface Protocol for Conditional Category Instructions ............ 7-11 Branch on Coprocessor Condition Instruction Format (cpBce.W)........0. 7-12 Branch on Coprocessor Condition instruction Format (cpBcc.L) oe, 7-12 Set on Coprocessor Condition Instruction Format (cpScc) o.oo. occccccececeeess 7-13 Test Coprocessor Condition, Decrement, and Branch Instruction Format (CPDBCC)....0.... occ cesceeeceseseecseesessvecceveteseesestnereeeeeecee 7-14 Trap on Coprocessor Condition Instruction Format (CPTRAP CC)... a. 7-15 Coprocessor State Frame Format in Memory ooo... cccecccccccesccesceceeeecececeeecceee 7-47 Coprocessor Context Save Instruction Format (CpSAVE) ...-cccccccccccccccsceceesese. 7-20 Coprocessor Context Save Instruction Protocol .....c.ccccccccccccccccccscevececeeeececees. 7-21 Coprocessor Context Restore Instruction Format (CpRESTORE) ...... i. 7-22 Coprocessor Context Restore Instruction Protocol .....0..-ccccccccccescccccseeeseescseeeee 7-23 Control CIR Format 0... ccccccccccsssessevessesesseesestsesesevesetetaverseeseceteteeecesecee. 7-25 Condition CIR Format... cecccceccsssssssscsecsscceetesatsuvaveteecscsscsveveteeteveceseesecee. 7-26 Operand Alignment for Operand CIR ACCESSES oooceccccceccccccccscececececececeeeeeeeeee. 7-26 Coprocessor Response Primitive Format .........cccccccccecscssecsecccccscesereeececececcee, 7-28 Busy Primitive Format... ccccccccccceccscscsesversestsustecsessscesetvececeseseveceseteseescese 7-30 Null Primitive Format... cc ccccccccccsecesscscanscesvscevsenasavatesacsscsvevepestieececeeseese. 7-31 Supervisor Check Primitive Format .....0.0.0ccsccccccesesecesceccesecsecececeecesecceesee. 7-33 Transfer Operation Word Primitive Format ....ccccccccccccccccccescecceccecceccecsessece 7-33 Transfer from Instruction Stream Primitive Format .o.cccccccscccscccececececececeeeceee.. 7-34 Evaluate and Transfer Effective Address Primitive Format.............................. 7-35 Evaluate Effective Address and Transfer Data Primitive Format..................... 7-35 Write to Previously Evaluated Effective Address Primitive Format .................. 7-37 Take Address and Transfer Data Primitive Format ...0....0.00.0-ccccccccccccceccceeceen. 7-39 Transfer to/from Top of Stack Primitive Format .....0.c..cc0 coccccccccceccececseeceecececen. 7-40 Transfer Single Main Processor Register Primitive Format ..............0...0.... 7-40 Transfer Main Processor Control Register Primitive Format.......................... 7-41 Transfer Muitiple Main Processor Registers Primitive Format......................... 7-42 Register Select Mask Format...0......0. 0c ccccccccscsssseetateceeceseeeceeeceseseeesc 7-42 Transfer Multiple Coprocessor Registers Primitive Format................-.0.0... 7-43 Operand Format in Memory for Transfer to -(AN)...cccccccccccccccccsececcecececeseeceeeee, 7-44 Transfer Status Register and ScanPC Primitive Format...................0.......... 7-44 Take Preinstruction Exception Primitive Format ......00.0..00c0cccc0000----ee ce. 7-45 MC68020/EC020 Preinstruction Stack Frame o.......c.ccccccccecccecccccccececccsseseeeceee-. 7-46 Take Midinstruction Exception Primitive Format ......0.0.cccccccccccccccccccceceececceces ee. 7-47 MC68020/EC020 Midinstruction Stack Frame oo... ccoccccccccoseceececeeeeececeseccee. 7-47 Take Postinstruction Exception Primitive Format .........0c0ccccccccccccccceccccececcce. 7-48 M68020 USERS MANUAL MOTOROLALIST OF ILLUSTRATIONS (Concluded) Figure Page Number Title Number 7-45 MC68020/EC020 Postinstruction Stack Frame ....ccccccccccccccceecccccceeeccce. 7-48 8-1 Concurrent instruction Execution ..0.0..0ccccccccsececssestecescecscececeeeeveveeeececccec 8-3 8-2 Instruction Execution for Instruction Timing PUrPOSES 000.0... eeeccccceeeee 8-3 8-3 Processor Activity for Example 1.0.0.0... ccc cccsscsesestetsscseesecevereeeeveeeecececcec 8-5 8-4 Processor Activity for Example 2.0.0... 0.0cccecccccccecsesssceseseseeveeseecceeeceseceeecse 8-6 8-5 Processor Activity for Example 3..0..0.0.ccccccccccccessvesesescccsesevevereseeseceesececececcc. 8-7 8-6 Processor Activity for Example 4..0......ccccccccscccsssesetesescececeseccsteseesevetereececee. 8-8 9-1 32-Bit Data Bus Coprocessor Commectiion ao... ccccccseeceecceccececeeececeeseeeeeececcee. 9-2 9-2 Chip Select Generation PAL ...o..ccccccccceescstsseseresesteseetscseececeeeeeec cc, 9-3 9-3 Chip Select PAL Equations ......0.0.0ccccccscscccscsesessetestecseseetsveteteseeeeeececcee 9-4 9-4 Bus Cycle Timing Diagram oo... cc ccc cesesessesestetsecessscessetetecseeeeeceseccs latteeesaes 9-4 9-5 Example MC68020/EC020 Byte Select PAL System Configuration oo... 9-7 9-6 MC68020/EC020 Byte Select PAL Equations ..0.000..0.cccccccsccccccccscssceceeeececcccecc. 9-8 9-7 High-Resolution Clock Controller ......c.ccccccccscssscessesecesecssestscesecveveeveceeceeecccn. 9-11 9-8 Alternate Clock Solution 2.2... cc cccccccscsesescavsssecstssteteveasavassvevereeseeeeeess cece. 9-11 9-9 Access Time Computation Diagram ......ccccccccccssssssessecesestsecsesvscesespeveececeseeeccecs. 9-12 9-10 Module Descriptor Format...0....c.cccccsscccsscssescscssesteeeeeesescscsveseresseteteteeeesescccc 9-15 9-11 Module Entry Word... cecccccseesescsscessuescecarssneeavanecesssvavutteceseteteeecc 9-15 9-12 Module Call Stack Frame oo... eccccccccescssesssssescsesevstsueevssssscevaeresseceteesececececce. 9-16 9-13 Access Level Control Bus Registers ........ccccccscsesssscscccccseseseseeececeesececeececc. 9-17 10-1 Drive Levels and Test Points for AC Specifications .......c.ccccccccseccecccces. 10-6 10-2 Clock Input Timing Diagram o.oo... cccccscsseeststescscsssesvavsvaveceveveveveseeecccc, 10-7 10-3. Read Cycle Timing Diagram... ccccccscsssveseeceteeesevaveseseeseteeeeeesececee.. 10-11 10-4 Write Cycle Timing Diagram.......cccccccccccccsssessststevsscssscasscssesacececeveteeeeeeccccc. 10-12 10-5 Bus Arbitration Timing Diagram 0.0.0.0... c.cccccscceseesescecccececestecsereveeeecececs 10-13 A-l Bus Arbitration CircuitMC68EC020 (Two-Wire) to DMA (Three-Wire) ......... A-1 MOTOROLA M68020 USERS MANUAL xvilLIST OF TABLES Table Page Number Title Number 1-1 Addressing Mode 220.00... ccecscscccaeeeseesesseeceeceassvsuueusiscesevsateeraeenares 1-9 1-2 INStPUCTION S@t cece cecetee cera steensececcecteycrvevvassesveraeeeseiesettieeerernees 1-11 2-1 Address Space Encodings o.oo. cee ccc eevee cet seseecesecsevesecrevesevasenevesces 2-4 3-1 Signal INGOX ..... cc ee ecc ee eeee eect cee eseeeeeeceeciecateeepssavessecsevsievisevsseveniee: 3-3 3- Signal SUMMALY o.oo cece ceeeeteeteseesscsceecesseeceessecesestuueeveseeauectievsutensases 3-8 5-1 DSACK1/DSACKO Encodings and Result$..........ccccccccc ccc ccceesccecrtevenssetenstseees 5-5 5-2 SIZ1, SIZO Signal Encoding 00.0.0... ccc cece ec crersreneesuesaseesusseetsssererteeesstaees 5-7 5-3 Address Offset Encodings .......0...0.cccccccccsesseesetscsteetensceessevescssecavsrisenecrtsestens 5-7 5-4 Data Bus Requirements for Read Cycles... ccccecccccccececcescessecsseeeeseees 5-8 5-5 MC68020/EC020 Internal to External Data Bus Multiplexer Write Cy Cle oo... cece ctsnsceseesessasssescsescesesersvecsvssarseacuveeieaesreesarers 5-9 5-6 Memory Alignment and Port Size Influence on Read/Write Bus Cycles.......... 5-20 5-7 Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports............. 5-22 5-8 DSACK1/DSACKO, BERR, HALT Assertion Results. ......000.000.00ccceescceeceseeee 5-54 6-1 Exception Vector ASSIQNMONts ..........c.ccccccceccccccssccesecccsesrosevsntecsuccareecssettsteenes 6-3 6-2 Fracing COMPO... cece ccesesnecssecessessessscssteatseuesscseseseereecrscsteersvsascrasersecss 6-9 6-3 Interrupt Levels and Mask Value@S......0.c00 cece cccecececeecesteueueesescassseesertsiseseeees 6-12 6-4 Exception Priority Groups 200.0000. cceceeecnnevennceeseeceeeressesteesuesevuttecenceees 6-18 6-5 Exception Stack Frames ooo... cocci ccceccssccsscsscceseecesseenteeeestevestsscssecpaseneereenes 6-26 7-1 cpTRAPcc Opmode Encodings ...........0. cc cececevencceeeeseesevscesurstevasescusseceen 7-16 7-2 Coprocessor Format Word Encodings ............00..cc:cccccccssesssserecceesseccececrstvevavess 7-18 7-3 Null Coprocessor Response Primitive Encodings ........0.000.000cccccecccceeceeecseees 7-32 7-4 Valid Effective Address Field Codes .....0.0.00.ccccccccccccsecersescuscesssesssesenseeeetens 7-36 7-5 Main Processor Control Register Select Codes oo... coccccccceeeeeereeee 7-41 7-6 Exceptions Related to Primitive Processing ........0...cccccccccccceeesecevsesesvseereecs 7-59 8-1 Examples 14 Instruction Stream Execution Comparison ...........ccccececcc 8-8 B-2 Instruction Timings from Timing Tables ..0000000000.0000c ccc cccceececceeeeseeeceseeevevees 8-11 8-3 Observed Instruction Timings oo... occ cece cece ce ccerteeecesevevereviecesevavensnanens B-11 xviii M68020 USERS MANUAL MOTOROLALIST OF TABLES (Continued) Table Page Number Title Number 9-1 Data Bus Activity for Byte, Word, and Long-Word Ports... 9-6 9-2 Vcc and GND Pin AssignmentsMC68EC020 PPGA (RP Suffix) ooo, 9-10 9-3 Vcc and GND Pin AssignmentsMC68EC020 PQFP (FG Sufffix) oo, 9-10 9-4 Memory Access Time Equations at 16.67 and 25 MHz... 9-13 9-5 Calculated taypy Values for Operation at Frequencies Less Than or Equal to the CPU Maximum Frequency Rating... 9-14 9-6 Access Status Register Codes .........c.0 occ cceecetes este ceseeceeeveeeee 9-18 10-1 QJa vs. Airflow--MC68020 COFP Package.....e-cceccccccceccecccceece 10-3 10-2 Power vs. Rated Frequency (at Ty Maximum = 110C) ooo 10-3 10-3. Temperature Rise of Board vs. Pyp>MC68020 CQFP Package... 10-3 10-4 = Oya vs. AirflowMC68EC020 PQFP PACKAGE... ccc eeeeccsceseeececeeeeceeees 10-4 MOTOROLA M68020 USERS MANUAL xixSECTION 1 INTRODUCTION The MC68020 is the first full 32-bit implementation of the M68000 family of microprocessors from Motorola. Using VLSI technology, the MC68020 is implemented with 32-bit registers and data paths, 32-bit addresses, a rich instruction set, and versatile addressing modes. The MC68020 is object-code compatible with earlier members of the M68000 family and has the added features of new addressing modes in support of high-level languages, an on-chip instruction cache, and a flexible coprocessor interface with full IEEE floating-point support (the MC68881 and MC68882). The internal operations of this microprocessor operate in parallel, allowing multiple instructions to be executed concurrently. The asynchronous bus structure of the MC68020 uses a nonmultiplexed bus with 32 bits of address and 32 bits of data. The processor supports a dynamic bus sizing mechanism that allows the processor to transfer operands to or from external devices while automatically determining device port size on a cycle-by-cycle basis. The dynamic bus interface allows access to devices of differing data bus widths, in addition to eliminating all data alignment restrictions. The MC68EC020 is an economical high-performance embedded microprocessor based on the MC68020 and has been designed specifically to suit the needs of the embedded microprocessor market. The major differences in the MC68EC020 and the MC68020 are that the MC68EC020 has a 24-bit address bus and does not implement the following signals: ECS, OCS, DBEN, IPEND, and BGACK. Also, the available packages and frequencies differ for the MC68020 and MC68EC020 {see Section 11 Ordering Information and Mechanical Data.) Unless otherwise stated, information in this manual applies to both the MC68020 and the MC68EC020. MOTOROLA 68020 USER'S MANUAL 1-11.1 FEATURES 1 The main features of the MC68020/EC020 are as follows: Object-Code Compatible with Earlier M68000 Microprocessors Addressing Mode Extensions for Enhanced Support of High-Level Languages New Bit Field Data Type Accelerates Bit-Oriented Applicationse.g., Video Graphics An On-Chip Instruction Cache for Faster Instruction Execution Coprocessor Interface to Companion 32-Bit Peripheralsthe MC68881 and MC68882 Floating-Point Coprocessors and the MC68851 Paged Memory Management Unit Pipelined Architecture with High Degree of Internal Parallelism Allowing Multiple Instructions To Be Executed Concurrently High-Performance Asynchronous Bus Is Nonmultiplexed and Full 32 Bits Dynamic Bus Sizing Efficiently Supports 8-/16-/32-Bit Memories and Peripherals Full Support of Virtual Memory and Virtual Machine Sixteen 32-Bit General-Purpose Data and Address Registers Two 32-Bit Supervisor Stack Pointers and Five Special-Purpose Contro! Registers Eighteen Addressing Modes and Seven Data Types 4-Gbyte Direct Addressing Range for the MC68020 16-Mbyte Direct Addressing Range for the MC68EC020 Selection of Processor Speeds for the MC68020: 16.67, 20, 25, and 33.33 MHz Selection of Processor Speeds for the MCEC68020: 16.67 and 25 MHz A block diagram of the MC68020/EC020 is shown in Figure 1-1. 1-2 M68020 USER'S MANUAL MOTOROLASEQUENCER AND CONTROL INSTRUCTION PIPE KAT cacHE CONTROL STAGE LUSTAGE | stace | HOLDING STORE D < 8 KY REGISTER UG INTERNAL DATA CONTROL BUS LOGIC INSTRUCTION Sy CACHE 32-BIT DATA DATA BUS ADDRESS INSTRUCTION PADS BUS ADDPESS EXECUTION UNIT BUS *92-BIT 2 ab PROGRAM DATA ADDRESS COUNTER | -f ADDRESS SECTION ae PADS cee SECTION > MULTIPLEXER ADDRESS ign BUS MISALIGNMENT MULTIPLEXER BUS CONTROLLER WRITE PENDING | | PREFETCH PENDING BUFFER BUFFER Mt MICROBUS | CONTROL LOGIC TC BUS CONTROL SIGNALS *24-Bit for MC6BECO20 Figure 1-1. MC68020/EC020 Block Diagram MOTOROLA M68020 USER'S MANUAL1.2 PROGRAMMING MODEL The programming model of the MC68020/EC020 consists of two groups of registers, the user model and the supervisor model, that correspond to the user and supervisor privilege levels, respectively. User programs executing at the user privilege level use the registers of the user model. System software executing at the supervisor level uses the control registers of the supervisor level to perform supervisor functions. As shown in the programming models (see Figures 1-2 and 1-3), the MC68020/EC020 has 16 32-bit general-purpose registers, a 32-bit PC two 32-bit SSPs, a 16-bit SR, a 32-bit VBA, two 3-bit alternate function code registers, and two 32-bit cache handling (address and contro!) registers. The user programming model remains unchanged from earlier M68000 family microprocessors. The supervisor programming model supplements the user programming model and is used exclusively by MC68020/EC020 system programmers who utilize the supervisor privilege level to implement sensitive operating system functions. The supervisor programming model contains all the controls to access and enable the special features of the MC68020/ECO020. All application software, written to run at the nonprivileged user level, migrates to the MC68020/EC020 from any M68000 platform without modification. Registers D7D0 are data registers used for bit and bit field (1 to 32 bits), byte (8 bit), word (16 bit), long-word (32 bit), and quad-word (64 bit) operations. Registers A6-AO and the USP, ISP, and MSP are address registers that may be used as software stack pointers or base address registers. Register A7 (shown as A7 in Figure 1-2 and as A7 and A7 in Figure 1-3) is a register designation that appties to the USP in the user privilege level and to either the ISP or MSP in the supervisor privilege level. In the supervisor privilege level, the active stack pointer (interrupt or master) is called the SSP. In addition, the address registers may be used for word and long-word operations. All of the 16 general-purpose registers (D7-D0, A7-A0) may be used as index registers. The PC contains the address of the next instruction to be executed by the MC68020/EC020. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC. as appropriate. 1-4 M68020 USERS MANUAL MOTOROLA|__ DATA REGISTERS | ADDRESS REGISTERS a 16 15 a USER STACK | ATUSP) TF BoNTER 0 PROGRAM L |Pc | COUNTER 0 Poros ons eee CONDITION CODE I So . :. ee Figure 1-2. User Programming Model MOTOROLA M68020 USERS MANUAL 1-5au 16 15 0 INTERRUPT STACK ar ise) }- POINTER i! 18 15 0 MASTER STACK | | AT (MSP BOINTER 45 87 o | STATUS. | (CCR) sR REGISTER 1 0 VECTOR BASE L | veR REGISTER a4 3 0 ee ee ee ee ' SFC ALTERNATE Poca cnc n nna cone nee nnn nnn ne nn nee een FUNCTION CODE Loe DFC REGISTERS a 0 CACHE CONTROL | CACR | REGISTER H 0 CAAA CACHE ADDRESS REGISTER Figure 1-3. Supervisor Programming Model Supplement 1-6 M68020 USERS MANUAL MOTOROLAThe SR (see Figure 1-4) stores the processor status. It contains the condition codes that reflect the results of a previous operation and can be used for conditional instruction execution in a program. The condition codes are extend (X), negative (N), zero (Z}, overflow (V), and carry (C). The user byte, which contains the condition codes, is the only portion of the SR information available in the user privilege level, and it is referenced as the CCR in user programs. In the supervisor privilege jevel, software can access the entire SR, including the interrupt priority mask (three bits) and control bits that indicate whether the processor fs in: 1. One of two trace modes {T1, TC) 2. Supervisor or user privilege level (S} 3. Master or interrupt mode (M) USEA BYTE SYSTEM BYTE (CONDITION CODE REGISTER} | | [ lI | 15 14 13 12 it 10 9 8 7 6 5 4 4 2 41 Q iu fmls[wl[ofeluluolofolofx[ulz{v fe LH |... [_ CARRY TRACE INTERRUPT ENABLE PRIORITY MASK OVERFLOW ZERO SUPERVISOPVUSER LEVEL NEGATIVE MASTERANTERRLPT MODE -J }__________.______ Ey TEND Figure 1-4. Status Register (SR) The VBR contains the base address of the exception vector table in memory. The displacement of an exception vector is added to the value in this register to access the vector table. The alternate function code registers, SFC and DFC, contain 3-bit function codes. For the MC68020, function codes can be considered extensions of the 32-bit linear address that optionally provide as many as eight 4-Gbyte address spaces; for the MC68EC020, function codes can be considered extensions of the 24-bit linear address that optionally provide as many as eight 16-Mbyte address spaces. Function codes are automatically generated by the processor to select address spaces for data and program at the user and supervisor privilege levels and to select a CPU address space for processor functions {e.g., coprocessor communications). Registers SFC and DFC are used by certain instructions to explicitly specify the function codes for operations. The CACR controls the on-chip instruction cache of the MC68020/ECO20. The CAAR stores an address for cache control functions. MOTOROLA M68020 USER'S MANUAL 1-71.3 DATA TYPES AND ADDRESSING MODES OVERVIEW For detailed information on the data types and addressing modes supported by the MC68020/EC020, refer to M68000PM/AD, M68000 Family Programmer's Reference Manual. The MC68020/EC020 supports seven basic data types: 1. Bits Bit Fields (Fields of consecutive bits, 1-32 bits long) BCD Digits (Packed: 2 digits/byte, Unpacked: 1 digit/byte) Byte integers (8 bits) Word Integers (16 bits) Long-Word Integers (32 bits) Quad-Word Integers (64 bits) NO on & Gt In addition, the MC68020/EC020 instruction set supports operations on other data types such as memory addresses. The coprocessor mechanism allows direct support of floating- point operations with the MC68881 and MC68882 floating-point coprocessors as well as specialized user-defined data types and functions. The 18 addressing modes listed in Table 1-4 include nine basic types: 1. Register Direct Register Indirect Register Indirect with Index Memory Indirect PC Indirect with Displacement PC Indirect with Index PC Memory Indirect Absolute Immediate oO ON aarp oD The register indirect addressing modes have postincrement, predecrement, displacement, and index capabilities. The PC modes have index and offset capabilities. Both modes are extended to provide indirect reference through memory. In addition to these addressing modes, many instructions implicitly specify the use of the CCR, stack pointer, and/or PC. 1-8 M68020 USER'S MANUAL MOTOROLATable 1-1. Addressing Modes Addressing Modes Syntax Register Direct Data On Address An Register Indirect Address (An) Address with Postincrement (An)+ Address with Predecrement (An) Address with Displacement (dig, An) Address Register Indirect with Index 8-Bit Displacement (dg, An, Xn) Base Displacement (bd, An, Xn) Memory Indirect Postindexed ({od, An), Xn, od) Preindexed ([bd. An, Xn], od) PC Indirect with Displacement (dig, PC) PC Indirect with Index 8-Bit Displacement (dg, PC, Xn) Base Displacement (bd, PC, Xn) PC Indirect Pastindexed Preindexed ([bd, PC], Xn, od) (od, PC, Xn], od) Absolute Datla Addressing Short (xxx). W Long Goog.L Immediate # NOTE On = Data Register, D7-DO An = Address Register, A7-AQ da,dig = Atwos complement or sign-extended displacement added as part of the effective address calculation: size is 8 (dg) or 16 (d4) bits: when omitted, assemblers use a value of zero. Xn = Address or data register used as an index register; form is Xn. SIZE*SCALE, where SIZE is .W or .L (indicates index register size} and SCALE is 1, 2. 4, or 8 (index register is multiplied by SCALE); use of SIZE and/or SCALE is optional. bd = Atwos-complement base displacement; when present, size can be 16 of 32 bits. od = Outer displacement added as part of effective address calculation after any memory indirection, use is opbonal with a size of 16 or 32 bits PG = Program Counter = Immediate vaiue of 8, 16, or 32 bits () } MOTOROLA Effectwe Address Use as indirect access to long-word address M68020 USERS MANUAL1.4 INSTRUCTION SET OVERVIEW For detailed information on the MC68020/ECa20 instruction set, refer to M68000PM/AD, M68000 Family Programmer's Reference Manual. sophisticated operating systems. Many instructions Operate on bytes, words, or long words, and most instructions can use any of the 18 addressing modes. 1.5 VIRTUAL MEMORY AND VIRTUAL MACHINE CONCEPTS The full addressing range of the MC68020 is 4 Gbytes (4,294 967,296 bytes) in each of eight address spaces: the full addressing range of the MC68EC020 is 16 Mbytes (16,777,216 bytes) in each of the eight address spaces. Even though most systems implement a smaller physical memory, the system can be made to appear to have a full 4 Gbytes (MC68020) or 16 Mbytes (MC68EC020) of memory available to each user program by using virtual memory techniques. In a virtual memory system, a user program can be written as if it has a large amount of memory avatiabie, although the physical memory actually present is much smaller. Similarly, a system can be designed to allow user programs to access devices that are not physically present in the system, such as tape drives, disk drives, printers, terminals, and So forth. With proper software emulation, a physical system can appear to be any other M68000 computer system to a user program, and the program can be given full access to all of the resources of that emulated system. Such an emulated system is called a virtual machine. 1.5.1 Virtual Memory has completed execution, it returns control to the program that was executing when the error was detected, reruns the faulted bus cycle (when required), and continues the suspended instruction. 1-10 M68020 USER'S MANUAL MOTOROLATable 1-2. Instruction Set Mnemonic Description Mnemonic Description ABCD Add Decimat with Extend MOVE USP Move User Stack Pointer ADD Add MOVEC Mova Control Register AQDDA Add Addrass MOVEM Move Multiple Registers ADD} Add Immediate MOVEP Move Paripheral ADDQ Add Quick MOVEQ Move Quick ADDX Add with Extend MOVES Move Alternata Address Space ANG Logical AND MULS Signed Multiply ANGI Logical AND immediate MULU Unsigned Muttipty ASL, ASR Arithmetic Shitt Lett and Right NBCD Negate Decimal with Extend Bec Branch Conditionally NEG Negale BCHG Test Bit and Change NEGX Negate with Extend BCLR Test Bit and Clear NOP No Operation BFCHG Tes! Bit Field and Change NOT Logical Compiament BFCLR Tast Bit Field and Clear QA Logical Inclusive OR BFEXTS Signed Bit Field Extract ORI Logical Inclusive OR Immediate BFEXTU Unsigned Bit Field Extract ORI CCR Logical Inclusive Or Immediate to Condition Codes BFFFO Bit Field Find First One ORI SA Logical Inclusive OR Immediate to Status Register BFINS Bit Field Insert PACK Pack BCD BFSET Test Bit Field and Set PEA Push Effectiva Address BFTST Test Bit Field RESET Reset Extemal Devices BKPT Breakpoint ROL, AOR Rotate Left and Aight BRA Branch Always ROXL,ROXR Rotate with Extend Left and Right BSET Test Bit and Set RTD Return and Dealtocate BSA Branch to Subroutine ATE Return from Exception BTST Test Bit RTM Return trom Module CALLM Call Module ATA Return and Restore Codes CAS Compare and Swap Operands ATS Return from Subroutine CAS2 Compare and Swap Dual Operands SBCD Subtract Decimat with Extand CHK Check Register Against Bound See Set Conditionally CHK2 Check Register Against Upper and Lower Bound ToP Stop CLA Clear SUB Subtract CMP Compare SUBA Subtract Address CMPA Compare Address SUBI Subtract Immediate CMP! Compare Immediate SUBQ Subtract Quick CMPM Compare Memory to Mamory SUBX Subtract with Extend CMP2 Compare Register Against Upper and Lower Bounds SWAP Swap Register Words DBes Tast Condition, Decrement and Branch TAS Test and Set an Operand OIVS, DIVSL Signed Oivide TRAP Trap DIVU, DIVUL Unsigned Divide TRAPce Trap Conditionally EOR Logical Exclusive OA TRAPY Trap on Overtlow EORI Logical Exclusive Or immediate TST Test Operand EXG Exchange Registers UNLK Uniink EXT, EXT9 Sign Extend UNPK Unpack BCD ILLEGAL Take Illegal Instruction Trap JMP dump COPROCESSOR INSTRUCTIONS JSR Jump to Subroutine Mnemonic Description LEA Load Effective Addrass cpBce Branch Conditlonally LINK Link and Allocate cpDBce Test Coprocessor Condition, Decrement and Branch LSL, LSA Logical Shilt Lait and Right cpGEN Coprocessor General Instruction MOVE Move coRE STORE Restore Internal State of Coprocessor MOVEA Move Address cpSAVE Save Internal State of Coprocessor MOVE CCA Move Condition Coda Register epScc Set Conditionally MOVE SR Move Status Register cpTRAPce Trap Condilionally MOTOROLA M68020 USERS MANUAL1.5.2 Virtual Machine A typical use for a virtual machine system is the development of software, such as an operating system, for a new machine also under development and not yet available for programming use. In a virtual machine system, a governing operating system emulates the hardware of the new machine and allows the new software to be executed and debugged as though it were running on the new hardware. Since the new software is controlied by the governing operating system, it is executed at a lower privilege level than the governing operating system. Thus, any attempts by the new software to use virtual resources that are not physically present (and should be emulated) are trapped to the governing operating system and performed by its software. In the MC68020/EC020 implementation of a virtual machine, the virtual application runs at the user privilege level. The governing operating system executes at the supervisor privilege level and any attempt by the new operating system to access supervisor resources or execute privileged instructions causes a trap to the governing operating system. Instruction continuation is used to support virtual !/O devices in memory-mapped input/output systems. Control and data registers for the virtual device are simulated in the memory map. An access to a virtual register causes a fault, and the function of the register is emulated by software. 1.6 PIPELINED ARCHITECTURE The MC68020/EC020 contains a three-word instruction pipe where instruction opcodes are decoded. As shown in Figure 1-5, instruction words (instruction operation words and all extension words) enter the pipe at stage B and proceed to stages C and D. An instruction word is completely decoded when it reaches stage D of the pipe. Each stage has a status bit that reflects whether the word in the stage was loaded with data from a bus cycle that was terminated abnormally. Stages of the pipe are only filled in response to specific prefetch requests issued by the sequencer. Words are loaded into the instruction pipe from the cache holding register. Although the individual stages of the pipe are only 16 bits wide, the cache holding register is 32 bits wide and contains the entire long word. This long word is obtained from the instruction cache or the external bus in response to a prefetch request from the sequencer. When the sequencer requests an even-word (long-word-aligned) prefetch, the entire long word is accessed from the instruction cache or the external bus and loaded into the cache holding register, and the high-order word is also loaded into stage B of the pipe. The instruction word for the next sequential prefetch can then be accessed directly from the cache holding register, and no external bus cycle or instruction cache access is required. The cache holding register provides instruction words to the pipe regardless of whether the instruction cache is enabled or disabled. 1-12 M68020 USER'S MANUAL MOTOROLAINSTRUCTION PIPE 1 4 ' i ' i ' ' t 1 ' cy a ' ' ' CACHE Stace . STAGE STAGE < HOLDING ' ! REGISTER 1 i ' ' ' i SEQUENCER i f beara enn pe nen n een ed INSTRUCTION CONTROL FLOW FROM UNIT < CACHE AND MEMORY AAAAAI EXECUTION jot UNIT < Figure 1-5. Instruction Pipe The sequencer is either executing microinstructions or awaiting completion of accesses that are necessary to continue executing microcode. The bus controller is responsible for all bus activity. The sequencer controls the bus controller, instruction execution, and internal processor operations such as the calculation of effective addresses and the setting of condition codes. The sequencer initiates instruction word prefetches and controls the validation of instruction words in the instruction pipe. Prefetch requests are simultaneously submitted to the cache holding register, the instruction cache, and the bus controller. Thus, even if the instruction cache is disabled, an instruction prefetch may hit in the cache holding register and cause an external bus cycle to be aborted. 1.7 CACHE MEMORY Due to locality of reference, instructions that are used in a program have a high probability of being reused within a short time. Additionally, instructions that reside in proximity to the instructions currently in use also have a high probability of being utilized within a short period. To exploit these locality characteristics, the MC68020/EC020 contains an on-chip instruction cache. The cache improves the overall performance of the system by reducing the number of bus cycles required by the processor to fetch information from memory and by increasing the bus bandwidth available for other bus masters in the system. MOTOROLA M68020 USER'S MANUAL 1-13SECTION 2 PROCESSING STATES This section describes the processing states of the MC68020/EC020. It describes the functions of the bits in the supervisor portion of the SR and the actions taken by the processor in response to exception conditions. Unless the processor has halted, it is always in either the normal or the exception processing state. Whenever the processor is executing instructions or fetching instructions or operands, it is in the normal processing state. The processor is also in the normal processing state while it is storing instruction results or communicating with a coprocessor. NOTE Exception processing refers specifically to the transition from normal processing of a program to normal processing of system routines, interrupt routines, and other exception handlers. Exception processing includes all stacking operations, the fetch of the exception vector, and the filling of the instruction pipe caused by an exception. Exception processing has completed when execution of the first instruction of the exception handler routine begins. The processor enters the exception Processing state when an interrupt is acknowledged, when an instruction is traced or results in a trap, or when some other exception condition arises. Execution of certain instructions or unusual conditions occurring during the execution of any instruction can cause exceptions. External conditions, such as interrupts, bus errors, and some coprocessor responses, also cause exceptions. Exception processing provides an efficient transfer of contro! to handlers and routines that process the exceptions. A catastrophic system failure occurs whenever the processor receives a bus error or generates an address error while in the exception processing state. This type of failure halts the processor. For example, if during the exception processing of one bus error another bus error occurs, the MC68020/EC020 has not completed the transition to norma! processing and has not completed saving the internal state of the machine; therefore, the processor assumes that the system is not operational and halts. Only an external reset can restart a halted processor. (When the processor executes a STOP instruction, it is ina special type of normal processing stateone without bus cycles. It is stopped, not halted.) MOTOROLA M68020 USER'S MANUAL 2-12.1 PRIVILEGE LEVELS The processor operates at one of two privilege levels: the user level or the supervisor level. The supervisor level has higher privileges than the user level. Not al! processor or coprocessor instructions are permitted to execute at the iower privileged user level, but all are available at the supervisor level. This arrangement allows a separation of supervisor and user so the supervisor can protect system resources from uncontrolled access. The S-bit in the SR is used to select either the user or supervisor privilege level and either the USP or an SSP for stack operations. The processor identifies a bus access (Supervisor or user mode) via the function codes so that differentiation between supervisor level and user level can be maintained. In many systems, the majority of programs execute at the user level. User programs can access only their own code and data areas and can be restricted from accessing other information. The operating system typically executes at the supervisor privilege level. it has access to all resources, performs the averhead tasks for the user-level programs, and coordinates user-level program activities. 2.1.1 Supervisor Privilege Level The supervisor level is the higher privilege level. The privilege level is determined by the S-bit of the SR; if the S-bit is set, the supervisor privilege level applies, and all instructions are executable. The bus cycles for instructions executed at the supervisor level are normally classified as supervisor references, and the values of the FC2-FCo signals refer to supervisor address spaces. In a multitasking operating system, it is more efficient to have a supervisor stack space associated with each user task and a separate stack space for interrupt-associated tasks. The MC68020/EC020 provides two supervisor stacks, master and interrupt; the M bit of the SR selects which of the two is active. When the M-bit is set, references to the SSP implicitly or to address register seven (A7) explicitly, access the MSP. The operating system sets the MSP for each task to point to a task-related area of supervisor data Space. This arrangement separates task-related supervisor activity from asynchronous, /O-related supervisor tasks that may be only coincidental to the currently executing task. The MSP can separately maintain task contro! information for each currently executing user task, and the software updates the MSP when a task switch is performed, providing an efficient means for transferring task-related stack items. The other supervisor stack pointer, the ISP, can be used for interrupt control information and workspace area as interrupt handling routines require. When the M-bit is clear, the MC68020/EC020 is in the interrupt mode of the supervisor privilege level, and operation is the same as supervisor mode in the MC68000, MC68HC001, MC68008, and MC68010. (The processor is in this mode after a reset operation.) All SSP references access the ISP in this mode. 2-2 M68020 USER'S MANUAL MOTOROLAThe value of the M-bit in the SR does not affect execution of priviteged instructions; both master and interrupt modes are at the Supervisor privitege level. Instructions that affect the M-bit are MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, and ATE. Also. the processor automatically saves the M-bit value and clears it in the SR as part of exception processing for interrupts. All exception processing is performed at the Supervisor privilege level. All bus cycles generated during exception processing are supervisor references, and all stack accesses use the active SSP. 2.1.2 User Privilege Level The user level is the lower privilege level. The privilege level is determined by the S-bit of the SR; if the S-bit is clear, the processor executes instructions at the user privilege level, Most instructions execute at either privilege level, but some instructions that have important system effects are privileged and can only be executed at the supervisor level. For instance, user programs are not allowed to execute the STOP instruction or the RESET instruction. To prevent a user program from entering the supervisor privilege level except in a controlled manner, instructions that can alter the S-bit in the SR are privileged. The TRAP #n instruction provides controlled access to operating system services for user programs. The bus cycles for an instruction executed at the user privilege level are classified as user references, and the values of the FC2FCo signals specify user address spaces. While the processor is at the user level, references to the system stack pointer implicitly, or to address register seven (A7) explicitly, refer to the USP. 2.1.3 Changing Privilege Level To change from the user to the supervisor privilege level, one of the conditions that causes the processor to pertorm exception processing must occur. This causes a change from the user level to the supervisor level and can cause a change from the master mode to the interrupt mode. Exception processing saves the current values of the S and M bits of the SR (along with the rest of the SR) on the active supervisor Stack, and then sets the S-bit, forcing the processor into the supervisor privilege level. When the exception being processed is an interrupt and the M-bit is set, the M-bit is cleared, putting the processor into the interrupt mode. Execution of instructions continues at the supervisor level to process the exception condition. To return to the user privilege level, a system routine must execute one of the following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or ATE. These instructions execute at the supervisor privilege level and can modify the S-bit of the SR. After these instructions execute, the instruction pipeline is flushed and is refilled from the appropriate address space. The RTE instruction returns to the Program that was executing when the exception occurred. It restores the exception stack frame saved on the supervisor stack. If the frame MOTOROLA M68020 USER'S MANUAL 2-3on top of the stack was generated by an interrupt, trap, or instruction exception, the RTE instruction restores the SR and PC to the values saved on the supervisor stack. The processor then continues execution at the restored PC address and at the privilege level determined by the S-bit of the restored SR. If the frame on top of the stack was generated by a bus fault (bus error or address error exception), the RTE instruction restores the entire saved processor state from the stack. 2.2 ADDRESS SPACE TYPES The processor specifies a target address space for every bus cycle with the FC2-FCO signals according to the type of access required. In addition to distinguishing between supervisor/user and program/data, the processor can identify special processor cycles, such as the interrupt acknowledge cycle, and the memory management unit can control accesses and translate addresses appropriately. Table 2-1 lists the types of accesses defined for the MC68020/EC020 and the corresponding values of the FC2FC0 signals. Table 2-1. Address Space Encodings FC2 FCI FCO Address Space a 0 Q (Undefined, Reserved)* 0 0 1 User Data Space 0 1 0 User Program Space 0 1 1 (Undefined, Reserved)* 1 0 0 (Undefined, Reserved}* 1 Q 1 Supervisor Data Space t 1 0 Supervisor Program Space 1 1 1 CPU Space * Address space 3 is reserved for user definition; O and 4 are reserved for future use by Motorola. The memory locations of user program and data accesses are not predefined; neither are the locations of supervisor data space. During reset, the first two long words beginning at memory iocation zero in the supervisor program space are used for processor initialization. No other memory locations are explicitly defined by the MC68020/EC020. A function code of $7 selects the CPU address space. This is a special address space that does not contain instructions or operands but is reserved for specia! processor functions. The processor uses accesses in this space to communicate with external devices for special purposes. For example, all M68000 processors use the CPU space for interrupt acknowledge cycles. The MC68020/EC020 also generate CPU space accesses for breakpoint acknowledge and coprocessor operations. Supervisor programs can use the MOVES instruction to access all address spaces, including the user spaces and the CPU address space. Although the MOVES instruction can be used to generate CPU space cycles, this may interfere with proper system operation. Thus, the use of MOVES to access the CPU space should be done with caution. 2-4 M68020 USERS MANUAL MOTOROLA2.3 EXCEPTION PROCESSING An exception is defined as a special condition that preempts normal processing. Both internal and external conditions can Cause exceptions. External conditions that cause exceptions are interrupts from external devices, bus errors, coprocessor-detected errors, and reset. Instructions, address errors, tracing, and breakpoints are internal conditions that Cause exceptions. The TRAP, TRAPcc, TRAPV, cpTRAPce, CHK, CHK2, ATE, BKPT, CALLM, RTM, cp RESTORE, DIVS and DIvU instructions can generate exceptions as part of their normal execution. In addition, illegal instructions, privilege violations, and coprocessor protocol viclations cause exceptions. Exception processing, which is the transition from the normal processing of a program to the processing required for the exception condition, involves the exception vector table and an exception stack frame. The following paragraphs describe the exception vectors and a generalized exception stack frame. Exception processing is discussed in detail in Section 6 Exception Processing. Coprocessor-detected exceptions are discussed in detail in Section 7 Coprocessor Interface Description. 2.3.1 Exception Vectors The VBR contains the base address of the 1024-byte exception vector table, which consists of 256 exception vectors. Exception vectors contain the memory addresses of routines that begin execution at the completion of exception processing. These routines perform a series of operations appropriate for the corresponding exceptions. Because the exception vectors contain memory addresses, each consists of one long word, except for the reset vector. The reset vector consists of two long words: the address used to initialize The address of an exception vector is derived from an 8-bit vector number and the VBR. The vector numbers for some exceptions are obtained from an external device; others are supplied automatically by the processor. The processor multiplies the vector number by four to calculate the vector offset, which it adds to the VBR. The sum is the memory address of the vector. All exception vectors are located in Supervisor data space, except the reset vector, which is located in Supervisor program space. Only the initial reset vector is fixed in the processor's memory map; once initialization is complete, there are no fixed assignments. Since the VBR Provides the base address of the vector table, the vector table can be located anywhere in memory; it can even be dynamically relocated for each task that is executed by an operating system. Details of exception processing are provided in Section 6 Exception Processing, and Table 6-1 lists the exception vector assignments. MOTOROLA M68020 USER'S MANUAL 2-52.3.2 Exception Stack Frame Exception processing saves the most voiatile portion of the current processor context on the top of the supervisor stack. This context is organized in a format called the exception stack frame. This information always includes a copy of the SR, the PC, the vector offset of the vector, and the frame format field. The frame format field identifies the type of stack frame. The RTE instruction uses the value in the format field to properly restore the information stored in the stack frame and to deailocate the stack space. The general form of the exception stack frame is illustrated in Figure 2-1. Refer to Section 6 Exception Processing for a complete list of exception stack frames. SsP STATUS REGISTER PROGRAM COUNTER FORMAT VECTOR OFFSET | ADDITIONAL PROCESSOR STATE INFORMATION | (2, 6, 12, OR 42 WORDS, IF NEEDED} Figure 2-1. General Exception Stack Frame 2-6 M63020 USERS MANUAL MOTOROLASECTION 3 SIGNAL DESCRIPTION This section contains brief descriptions of the input and output Signals in their functional groups, as shown in Figure 3-1. Each signal is explained in a brief paragraph with reference to other sections that contain more detail about the signal and the related operations. NOTE In this section and in the remainder of the Manual, assert and negate are used to specify forcing a signal to a particular state. In particular, assertion and assert refer to a signal that is active or true; negation and negate indicate a signal that is inactive or false. These terms are used independently of the voitage levei (high or low) that they represent. FUNCTION CODES FO2-FCO ba PL <______ ADDAESS BUS *FAGT-AO PL INTERRUPT i -__.._ 1 DATA BUS * PED CONTROL |}_____j- [~ ag 5120 AVEC .____ TRANSFER SIZE sii <___] _ L an _ _<_-._. [ag 70C8 BG BUS ARBITRATION __ }-_ | - FS CONTROL _.____ _ MC68020 - AW J == RESET AMG = a T ASYNCHRONOUS AS bag HALT {_ oe FP TION __] _ BUS CONTROL __ aEAR DS ____ ____] OBEN __._ OSACKO CLK __ a EK DSACKI L Voc EMULATOR SUPPORT ons Leg SND * This signals implomented in the MC68020 and not implemented in ing MCBBECO20 ** A20 AO tor ihe MC6BECO24, Figure 3-1. Functional Signal Groups MOTOROLA M68020 USER'S MANUAL 3-13.1 SIGNAL INDEX The input and output signals for the MC68020/EC020 are listed in Table 3-1. Both the names and mnemonics are shown along with brief signat descriptions. Signals that are implemented in the MC68020, but not in the MC68ECC20, have an asterisk (*} preceding the signal name tn Table 3-1. Also, note that the address bus is 32 bits wide for the MC68020 and 24 bits wide for the MC68ECQO20. For more detalii on each signal, refer to the paragraph in this section named for the signal and the reference in that paragraph toa description of the related operations. Timing specifications for the signals listed in Table 3-1 can be found in Section 10 Electrica) Characteristics. 3.2 FUNCTION CODE SIGNALS (FC2-FC0) These three-state outputs identify the address space of the current bus cycle. Table 2-1 shows the relationships of the function code signals to the privilege levels and the address spaces. Refer to Section 2 Processing States for more information. 3.3 ADDRESS BUS (A31-A0, MC68020){A23-A0, MC68EC020) These three-state outputs provide the address for the current bus cycle, except in the CPU address space. Refer to Section 2 Processing States for more information on the CPU address space. A31 is the most significant address signal for the MC68020; A23 is the most significant address signal for the MC68EC020. The upper eight bits (A31-A24) are used internally by the MC68EC020 to access the internal instruction cache address tag. Refer to Section 5 Bus Operation for information on the address bus and its relationship to bus operation. 3.4 DATA BUS (D31D0) These three-state bidirectional signals provide the general-purpose data path between the MC68020/EC020 and all other devices. The data bus can transfer 8, 16, 24, or 32 bits of data per bus cycle. O31 ts the most significant bit of the data bus. Refer to Section 5 Bus Operation for more information on the data bus and its relationship to bus operation. 3.5 TRANSFER SIZE SIGNALS (SIZ1, SIZ0) These three-state oulputs indicate the number of bytes remaining to be transferred for the current bus cycle. Signats A1, AO, DSACK1, DSACKO, SIZ1, and SIZ0 define the number of bits transferred on the data bus. Refer to Section 5 Bus Qperation for more information on SIZ1 and S{Z0 and their use in dynamic bus sizing. 3-2 M68020 USERS MANUAL MOTOROLATable 3-1, Signal Index Signal Name Mnemonic Function Function Codes FC2-FCo 3-bit function code used to identity the address space of each bus cycle. Address Bus MC68020 A31 AQ 32-bit address bus MC6BEC020 A23--A0 24-bil address bus Data Bus D31-Da 32-bil data bus used to transfer 8, 16, 24, or 32 bits of data per bus cycle. Size S!2t, 31ZO_ | Indicates the number of bytes remaining to be transferred for this cycle. These signals, together with A1 and AO. define the active sections of the data bus *External Cycle Start Ecs Provides an indication that a bus cycle is beginning *Operand Cycle Start ocs Identical operation to that of ECS except that OCS is asserted only during the first bus cycle of an operand transter. Read/Write RAW Defines the bus transfer as a Processor read or write. Read-Modity-Write Cycle AMG Provides an indicator that the current bus cycle is pan of an indivisible read-modify-write operation. Address Strobe AS Indicates that a valid address is on the bus. Data Strobe 6s Indicates that valid data is to be placed on the data bus by an external device or has been placed on the data bus by the MC68020/EC020. *Data Butfer Enable DBEN Provides an enable signal for external data buffers. Data Transfer and Size Acknowledge DSACKT, Bus response signals that indicate the requested data transfer operation DSACKO has completed. tn addition, these two lines indicate the size of the external bus port on a cycle-by-cycle basis and are used for asynchronous transfers. Interrupt Priority Level IPL2-IPLG Provides an encoded interrupt levet to the processor. *Interrupt Pending IPEND Indicates that an interrupt is pending. Autovector AVET Requests an autovector during an interrupt acknowledge cycle. Bus Request BR Indicates that an external device requires bus mastership. Bus Grant BG Indicates that an external device May assume bus mastership. *Bus Grant Acknowledge BGACK Indicates that an external device has assumed bus mastership. Reset RESET System reset. Hait HALT Indicates that the processor should suspend bus activity or that the processor has halted due to a double bus fault. Bus Error BERR Indicates that an erroneous bus operation is being altempted. Cache Disable cbs Staticalty disables the on-chip cache to assist emulator support Clock CLK Clock input to the processor. Power Supply Voc Power supply. Ground GND Ground connection. *This signal is implemented in the MC68020 and not implemented in the MC68ECO20. MOTOROLA M66020 USERS MANUAL 3-33.6 ASYNCHRONOUS BUS CONTROL SIGNALS The following signals control synchronous bus transter operations for the MC68020/EC020. Note that OCS, ECS, and DBEN are implemented in MC68020 and not implemented in the MC68EC020. Operand Cycle Start (OCS, MC68020 only) This output signal indicates the beginning cf the first external bus cycle for an instruction prefetch or a data operand transfer. OCS is not asserted for subsequent cycles that are performed due to dynamic bus sizing or operand misalignment. Refer to Section 5 Bus Operation for information about the relationship of OCS to bus operation. OCS is not implemented in the MC68ECQ20. External Cycle Start (ECS, MC68020 only) This output signal indicates the beginning of a bus cycle of any type. Refer to Section 5 Bus Operation for information about the relationship of ECS to bus operation. ECS is not implemented in the MC68EC020. Read/Write (R/W) This three-state output signal defines the type of bus cycle. A high level indicates a read cycle; a low level indicates a write cycle. Refer to Section 5 Bus Operation for information about the relationship of R/W to bus operation. Read-Modify-Write Cycle (RMC) This three-state output signal identifies the current bus cycle as part of an indivisible read-modify-write operation; it remains asserted during all bus cycles of the read- modify-write operation. Refer to Section 5 Bus Operation for information about the relationship of RMC to bus operation. Address Strobe (AS) This three-state output signal indicates that a valid address is on the address bus. The FC2-FCO, SIZ1, SIZO, and R/W signals are also valid when AS is asserted. Refer to Section 5 Bus Operation for information about the relationship of AS to bus operation. Data Strobe (DS) During a read cycle, this three-state output signal indicates that an external device should place valid data on the data bus. During a write cycle, DS indicates that the MC68020/EC020 has placed valid data on the bus. During two-clock synchronous write cycles, the MC68020/EC020 does not assert DS. Refer to Section 5 Bus Operation for more information about the relationship of DS to bus operation. 3-4 M68020 USER'S MANUAL MOTOROLAData Buffer Enable (OBEN, MC68020 oniy) This output signal is an enable signal for external data buffers. This signal may not be required in all systems. Refer to Section 5 Bus Operation for more information about the relationship of DBEN to bus operation. DBEN is not implemented in the MC68EC020. Data Transfer and Size Acknowledge (DSACK1, DSACKO) These input signals indicate the completion of a requested data transfer operation. In addition, they indicate the size of the external bus port at the completion of each cycie. These signals apply only to asynchronous bus cycles. Refer to Section 5 Bus Operation for more information on these signals and their relationship to dynamic bus sizing. 3.7 INTERRUPT CONTROL SIGNALS The following signals are the interrupt control signals for the MC68020/EC020. Note that IPEND is implemented in the MC68020 and not implemented in the MC68EC020, interrupt Priority Level Signals (IPC2-IPLO) These input signals provide an indication of an interrupt condition and the encoding of the interrupt level from a peripheral or external prioritizing circuitry. IPL2 is the most significant bit of the level number. For exampie, since the IPL2-IPLO signals are active low, IPL2-IPLO equal to $5 corresponds to an interrupt request at interrupt level 2. Refer to Section 6 Exception Processing for information on MC68020/EC020 interrupts. Interrupt Pending (IPEND, MC68020 only) This output signal indicates that an interrupt request exceeding the current interrupt priority mask in the SR has been recognized internally. This output is for use by external devices (coprocessors and other bus masters, for example) to predict processor operation on the following instruction boundaries. Refer to Section 6 Exception Processing for interrupt information. Also, refer to Section 5 Bus Operation for bus information related to interrupts. IPEND is not implemented in the MC68EC020. Autovector (AVEC) This input signal indicates that the MC68020/EC020 should generate an automatic vector during an interrupt acknowledge cycle. Refer to Section 5 Bus Operation for more information about automatic vectors. MOTOROLA M68020 USERS MANUAL 3-53.8 BUS ARBITRATION CONTROL SIGNALS The following signals are the bus arbitration control signals used to determine which device in a system is the bus master. Note that BGACK is implemented in the MC68020 and not implemented in the MC68EC020. Bus Request (BR) This input signal indicates that an external device needs to become the bus master. BR is typicaily a wire-ORed input (but does not need to be constructed from open-collector devices). Refer to Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol for more information on MC68ECQ020 bus arbitration. Bus Grant (BG) This output signal indicates that the MC68020/EC020 will release ownership of the bus when the current processor bus cycle completes. Refer to Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three- Wire Bus Arbitration Protocol for more information on MC68EC020 bus arbitration. Bus Grant Acknowledge (BGACK, MC68020 only) This input signal indicates that an external device has become the bus master. Refer to Section 5 Bus Operation for more information on MC68020 bus arbitration. Refer to Section 5 Bus Operation and Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol for more information on MC68EC020 bus arbitration. BGACK is not implemented in the MC6BECO20. 3.9 BUS EXCEPTION CONTROL SIGNALS The foltowing signals are the bus exception control signals for the MC68020/EC020. Reset (RESET) This bidirectional open-drain signal is used to initiate a system reset. An external reset signal resets the MC68020/EC020 as well as all external devices. A reset signal from the processor (asserted as part of the RESET instruction) resets externa! devices only: the internal state of the processor is not altered. Refer to Section 5 Bus Operation for a description of reset bus operation and Section 6 Exception Processing for information about the reset exception. 3-6 M68020 USER'S MANUAL MOTOROLAHalt (HALT) The assertion of this bidirectional open-drain signal indicates that the processor should suspend bus activity or, when used with BEAR, that the processor should retry the current cycle. Refer to Section 5 Bus Operation for a description of the effects of HALT on dus operations. When the processor has stopped executing instructions due to a double bus fault condition, the HALT fine is asserted by the processor to indicate to external devices that the processor has stopped. Bus Error (BERR) This input signal indicates that an invalid bus operation is being attempted or, when used with HALT, that the processor shouid retry the current cycle. Refer to Section 5 Bus Operation for a description of the effects of BERRA on bus operations. 3.10 EMULATOR SUPPORT SIGNAL The following signal supports emulation by providing a means for an emulator to disable the on-chip cache by supplying internat status information to an emulator. Refer to Section 7 Coprocessor Interface Description for more detailed information on emulation support. Cache Disable (CDI5) This input signal statically disables the on-chip cache to assist emulator support. Refer to Section 4 On-Chip Cache Memory for information about the cache; refer to Section 9 Applications Information for a description of the use of this signal by an emulator. CDIS does not flush the instruction cache; entries remain unaltered and become available again when CDIS is negated. 3.11 CLOCK (CLK) The CLK signal is the clock input to the MC68020/EC020. This TTL-compatible signal should not be gated off at any time while power is applied to the processor. Refer to Section 9 Applications Information for suggestions on clock generation. Refer to Section 10 Electrical Characteristics for electrical characteristics. 3.12 POWER SUPPLY CONNECTIONS The MC68020/EC020 requires connection to a Vcc power supply, positive with respect to ground. The Vcc connections are grouped to supply adequate current for the various sections of the processor. The ground connections are similarly grouped. Section 11 Ordering Information and Mechanica Data describes the groupings of Vcc and ground connections, and Section 9 Applications Information describes a typical power supply interface. MOTOROLA M68020 USER'S MANUAL 3-73.13 SIGNAL SUMMARY Table 3-2 provides a summary of the characteristics of the signals discussed in this section. Signal names preceded by an asterisk (*) are implemented in the MC68020 and not implemented in the MC68EC020. Table 3-2. Signal Summary Signal Function Signal Name Input/Output Active State Three-State Function Codes FG2-FCO Output High Yes Address Bus Output High Yes MC68020 A31-A0 MC68EC020 A23-A0 Data Bus D31-Da inpulOutput High Yes Transfer Size SIZ1, SIZ0 Output High Yes *Operand Cycle Start 6cs Output Low No *External Cycle Start Ecs Output Low No ReadMrite RAV Output High/Low Yes Read-Modity-Write Cycle RMC Output Low Yes Address Strobe AS Output Low Yes Data Strobe DS Output Low Yes Data Buffer Enable DBEN Output Low Yes Data Transfer and Size Acknowledge DSACKT, BSACKO Input Low Interrupt Priority Level IPL2-iPLO input Low *Interrupt Pending iPEND Output Low No Autovector AVEC Input Low Bus Request BR Input Low 8us Grant 8G Output Low No Bus Grant Acknowledge BGACK Input Low Reset RESET Input/Output Low No** Halt HACT Input/Output Low No** Bus Error BEAR Input Low Cache Disable cb Input Low ~ Clock CLK Input Power Supply Vec Input ~ Ground GND Input _ *This signal is implemented in the MC68020 and not implemented in ihe MC66EC020. *Open-drain 3-8 M68020 USER'S MANUAL MOTOROLASECTION 4 ON-CHIP CACHE MEMORY The MC68026/EC020 incorporates an on-chip cache memory as a means of improving performance. The cache is implemented as a CPU instruction cache and is used to store the instruction stream prefetch accesses from the main memory. An increase in instruction throughput results when instruction words required by a program are available in the on-chip cache and the time required to access them on the external bus is eliminated. In systems with more than one bus master (@.g., a processor and a DMA device), reduced external bus activity increases overall performance by increasing the availability of the bus for use by external devices without degrading the performance of the MC68020/EC020. 4.1 ON-CHIP CACHE ORGANIZATION AND OPERATION The MC68020/EC020 on-chip instruction cache is a direct-mapped cache of 64 long-word entries. Each cache entry consists of a tag field (A31-A8 and FC2), one valid bit, and 32 bits (two words) of instruction data. Figure 4-1 shows a block diagram of the on-chip cache organization. Externally, the MC68EC020 does not use the upper eight bits of the address (A31A24), and addresses $FFO00000 and $00000000 from the MC68EC020 appear the same. However, the MC68EC020 does use A31-A24 internally in the instruction cache address tag, and addresses $FFO00000 and $00000000 appear different in the MC68EC020 instruction cache. The MC68020, MC68030/EC030, and MC68040/EC040 use all 32 bits of the address externally. To maintain object-code upgrade compatibility when designing with the MC68EC020, the upper eight bits should be considered part of the address when assigning address spaces in hardware. When enabled, the MC68020/EC020 instruction cache is used to store instruction prefetches (instruction words and extension words) as they are requested by the CPU. Instruction prefetches are normally requested from sequential memory addresses except when a change of program flow occurs (e.g., a branch taken) or when an instruction is executed that can modify the SR. In these cases, the instruction pipe is automatically flushed and refilled. MOTOROLA M68020 USER'S MANUAL 4-1MC68020/ECO20 PREFETCH ADDRESS A AAAAAAAAKRAAAAAAAAAAAAAA A peeer 222111 4 1 $141'49R8 7 654397 FO 1 321069 6 76543210 a i non -OoOn oon WORD | SELECT TAG v WORD WORD 5 * e . . e oe 1 OF e . . 64 SELECT e TAG REPLACE j ; A A REPLACEMENT DATA VALID 10 L_f > INSTRUCTION PATH / ENTRY HIT CACHE COMPARATOA CONTROL UNE HIT Figure 4-1. MC68020/EC020 On-Chip Cache Organization When an instruction fetch occurs, the cache (if enabled) is first checked to determine if the word required is in the cache. This check is achieved by first using the index field (A7-A2) of the access address as an index into the on-chip cache. This index selects one of the 64 entries in the cache. Next, A31-A8 and FC2 are compared to the tag of the selected entry. (Note that in the MC68EC020, A31-A24 are used for internal on-chip cache tag comparison.) If there is a match and the valid bit is set, a cache hit occurs. A1 is then used to select the proper word from the cache entry, and the cycle ends. If there is no match or if the valid dit is clear, a cache miss occurs, and the instruction is fetched from external memory. This new instruction is automatically written into the cache entry, and the valid bit is set unless the F-bit in the CACR is set. Since the processor always prefetches instructions externally with long-word-aligned bus cycles, both words of the entry will be updated, regardless of which word caused the miss. NOTE Data accesses are not cached, regardless of their associated address space. 4-2 M68020 USERS MANUAL MOTOROLA4.2 CACHE RESET During processor reset, the cache is cleared by resetting ail of the valid bits. The E and F bits in the CACR are also cleared. 4.3 CACHE CONTROL Only the MC68020/EC020 cache control circuitry can directly access the cache array, but a supervisor program can set bits in the CACR to exercise control over cache operations. The supervisor level also has access to the CAAR, which contains the address for a cache entry to be cleared. System hardware can assert the CDIS signal to disable the cache. The assertion of GDIS disables the cache, regardless of the state of the E-bit in the CACR. CDIS is primarily intended for use by in-circuit emulators. 4.3.1 Cache Control Register (CACR) The CACR, shown in Figure 4-2, is a 32-bit register than can be written or read by the MOVEC instruction or indirectly modified by a reset. Four of the bits (3-0) control the instruction cache. Bits 314 are reserved for Motorola definition. They are read as zeros and are ignored when written. For future compatibility, writes should not set these bits. [ TET] [e[eel-Te} Figure 4-2. Cache Control Register CClear Cache The C-bit is set to clear all entries in the instruction cache. Operating systems and other software set this bit to clear instructions from the cache prior to a context switch. The processor clears all valid bits in the instruction cache when a MOVEC instruction sets the C-bit. The C-bit is always read as a zero. CEClear Entry In Cache The CE bit is set to clear an entry in the instruction cache. The index field of the CAAR (see Figure 4-3), corresponding to the index and long-word select portion of an address, specifies the entry to be cleared. The processor clears only the specified long word by clearing the valid bit for the entry when a MOVEC instruction sets the CE bit, regardless of the states of the E and F bits. The CE bit is always read as a zero. MOTORCLA M68020 USER'S MANUAL 4-3F--Freeze Cache The F-bit is set to freeze the instruction cache. When the F-bit is set and a cache miss occurs, the entry (or line) is not replaced. When the F-bit is clear, a cache miss causes the entry (or tine) to be filled. A reset operation clears the F-bit. EEnable Cache The E-bit is set to enable the instruction cache. When it is clear, the instruction cache is disabled. A reset operation clears the E-bit. The supervisor normally enables the instruction cache, but it can clear the E-bit for system debugging or emulation, as required. Disabling the instruction cache does not flush the entries. If the cache is reenabied, the previously valid entries remain valid and may be used. 4.3.2 Cache Address Register (CAAR) The format of the 32-bit CAAR is shown in Figure 4-3. 31 a7 24 0 RESERVED | INDEX | RESERVED | Figure 4-3. Cache Address Register Bits 31-8, 1, and 0--Reserved These bits are reserved for use by Motorola. Index Field The index field contains the address for the clear cache entry operations. The bits of this field, which correspond to A7-A2, specify the index anda long word of a cache line. 4-4 M68020 USERS MANUAL MOTOROLASECTION 5 BUS OPERATION This section provides a functional description of the bus, the signals that contra! it, and the bus cycles provided for data transfer operations. It also describes the error and halt conditions, bus arbitration, and reset operation. Operation of the bus is the same whether the processor or an external device is the bus master: the names and descriptions of bus cycles are fram the point of view of the bus master. For exact timing specifications, refer to Section 10 Electrical Characteristics. The MC68020/EC020 architecture supports byte, word, and long-word operands, allowing access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by the DSACK1 and DSACK0O input signals. The MC68020/EC020 allows byte, word, and long-word operands to be located in memory on any byte boundary. For a misaligned transfer, more than one bus cycle may be required to complete the transfer, regardiess of port size. For a port less than 32 bits wide, multiple bus cycles may be required for an operand transfer due to either misalignment or a port width smalier than the operand size. Instruction words and their associated extension words must be aligned on word boundaries. The user should be aware that misalignment of word or long-word operands can cause the MC68020/EC020 to perform multiple bus cycles for the operand transfer; therefore, processor performance is optimized if word and long-word memory operands are aligned on word or long-word boundaries, respectively. 5.1 BUS TRANSFER SIGNALS The bus transfers information between the MC68020/EC020 and an external memory, coprocessor, or peripheral device. External devices can accept or provide 8 bits, 16 bits, or 32 bits in parallel and must follow the handshake protocol described in this section. The maximum number of bits accepted or provided during a bus transfer is defined as the port width. The MC68020/EC020 contains an address bus that specifies the adcress for the transfer and a data bus that transfers the data. Control signals indicate the beginning of the cycle, the address space and size of the transfer, and the type of cycle. The selected device then controls the length of the cycle with the signal(s) used to terminate the cycle. Strobe signals, one for the address bus and another for the data bus, indicate the validity of the address and provide timing information for the data. The bus operates in an asynchronous mode for any port width. The bus and control input signals are internally synchronized to the MC68020/EC020 clock, introducing a delay. This delay is the time period required for the MC6B020/EC020 to sample an input signal. synchronize the input to the internal clocks of the processor, and determine whether the MOTOROLA M68020 USERS MANUAL 5-4input is high or low. Figure 5-1 shows the relationship between the clock signal, a typical inout, and its associated internal signal. Furthermore, for all inputs, the processor latches the level of the input during a sample window around the falling edge of the clock signal. This window is illustrated in Figure 5-2. To ensure that an input signal is recognized on a specific falling edge of the clock, that input must be stable during the sample window. If an input transitions during the window, the level recognized by the processor is not predictable; however, the processor always resolves the latched Jevel to either a logic high or logic low before using it. In addition to meeting input setup and hold times for deterministic operation, all input signals must obey the protocols described in this section. CLK EXT " J p< _--- SYNC DELAY a Figure 5-1. Relationship between External and Internal Signals \sua) CLK EXT Ll SAMPLE WINDOW Figure 5-2. Input Sample Window 5.1.1 Bus Control Signals The MC68020/EC020 initiates a bus cycle by driving the A1AO, SIZ1, SIZO, FC2-FCO, and R/W outputs. However, if the MC68020/EC020 finds the required instruction in the on- chip cache, the processor aborts the cycle before asserting the AS.The assertion of AS ensures that the cycle has not been aborted by these internal conditions. 5-2 M68020 USERS MANUAL MOTOROLAWhen initiating a bus cycle, the MC68020 asserts ECS in addition to A1-A0, SIZ1. SIZ0, FC2-FCO, and R/W. ECS can be used to initiate various timing sequences that are eventually qualified with AS. Qualification with AS may be required since. in the case of an internal cache hit, a bus cycle may be aborted after EGS has been asserted. During the first MC68020 external bus cycle of an operand transfer, OCS is asserted with EGS. When several bus cycles are required to transfer the entire operand, OCS is asserted only at the beginning of the first external bus cycle. With respect to OCS, an operand is any entity required by the execution unit, whether a program or data item. Note that ECS and OCS are not implemented in the MC68ECQ20. The FC2-FCO signals select one of eight address spaces (see Table 2-1) to which the address applies. Five address spaces are presently defined. Of the remaining three, one is reserved for user definition, and two are reserved by Motorola for future use. FC2-FCO are valid while AS is asserted. The SIZ and S!ZO signals indicate the number of bytes remaining to be transferred during an operand cycle (consisting of one or more bus cycles) or during a cache fill operation from a device with a port size that is less than 32 bits. Table 5-2 lists the encoding of SIZ1 and SIZO. S!IZ1 and SIZO are valid while AS is asserted. The R/W signal determines the direction of the transfer during a bus cycle. When required, this signal changes state at the beginning of a bus cycle and is valid while AS is asserted. R/W only transitions when a write cycie is preceded by a read cycle or vice versa. This signal may remain low for two consecutive write cycles. The RMC signal is asserted at the beginning of the first bus cycle of a read-modify-write operation and remains asserted until completion of the final bus cycle of the operation. The RMC signal is guaranteed to be negated before the end of state 0 for a bus cycle following a read-modify-write operation. 5.1.2 Address Bus A31-A0 (for the MC68020) or A23-AG (for the MC68EC020) define the address of the byte (or the most significant byte) to be transferred during a bus cycle. The processor places the address on the bus at the beginning of a bus cycle. The address is vatid while AS is asserted. In the MC68EC020, A31A24 are used internally, but not externally. 5.1.3 Address Strobe AS is a timing signal that indicates the validity of an address on the address bus and of many control signals. It is asserted one-half clock after the beginning of a bus cycle. 5.1.4 Data Bus D31DO comprise a bidirectional, nonmultiplexed parallel bus that contains the data being transferred to or from the processor. A read or write operation may transfer 8, 16, 24, or 32 bits of data (one, two, three, or four bytes) in one bus cycle. During a read cycle, the data is latched by the processor on the last falling edge of the clock for that bus cycle. For MOTOROLA M68020 USER'S MANUAL 5-3a write cycle, all 32 bits of the data bus are driven, regardless of the port width or operand size. The processor places the data on the data bus one-half clock cycle after AS is asserted in a write cycle. 5.1.5 Data Strobe DS is a timing signal that applies to the data bus. For a read cycle, the processor asserts DS to signal the external device to place data on the bus. DS is asserted at the same time as AS during a read cycle. For a write cycle, DS notifies the external device that the data to be written is valid. The processor asserts DS one full clock cycle after the assertion of AS. during a write cycle. 5.1.6 Data Buffer Enable The MC68020 DBEN signal is used to enable external data buffers while data is present on the data bus. During a read operation, DBEN is asserted one clock cycle after the beginning of the bus cycle and is negated as DS is negated. In a write operation, DBEN is asserted at the time AS is asserted and is held active for the duration of the cycle. Note that DBEN is implemented in the MC68020 and is not implemented in the MC68EC020. 5.1.7 Bus Cycle Termination Signals During bus cycles, external devices assert DSACK1/DSACKO as part of the bus protocol. During a read cycle, DSACK1/DSACKO assertion signals the processor to terminate the bus cycle and to latch the data. During a write cycle, the assertion of DSACK1/DSAGKO indicates that the external device has successfully stored the data and that the cycle may terminate. DSACK1/DSACKO also indicate to the processor the size of the port for the bus cycle just completed, as shown in Table 5-1. Refer to 5.3.1 Read Cycle for timing relationships of DSACK1/DSACKO. The BERR signal is also a bus cycle termination indicator and can be used in the absence of DSACK1/DSACKO to indicate a bus error condition. It can also be asserted in conjunction with DSACKt/DSACKO to indicate a bus error condition, provided it meets the appropriate timing described in this section and in Section 10 Electrical Characteristics. Additionally, the BERR and HALT signals can be asserted together to indicate a retry termination. Again, the BERR and HALT JALT signals can be simultaneously asserted in lieu of, or in conjunction with, the DSACKT/DSACKO signals. Finally, the AVEC signal can be used to terminate interrupt acknowledge cycles, indicating that the MC68020/EC020 should generate a vector number to locate an interrupt handler routine. AVEC is ignored during all other bus cycles. 5-4 M68020 USERS MANUAL MOTOROLA5.2 DATA TRANSFER MECHANISM The MC68020/EC020 architecture supports byte, word, and long-word operands allowing access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled by DSACKT/DSACKO. Byte, word, and long-word operands can be located on any byte boundary, but misaligned transfers may require additional bus cycles, regardless of port size. 5.2.1 Dynamic Bus Sizing The MC68020/EC020 dynamically interprets the port size of the addressed device during each bus cycle, allowing operand transfers to or from 8-, 16-, and 32-bit ports. During an operand transfer cycle, the slave device signals its port size (byte, word, or long word) and indicates completion of the bus cycle to the processor with the DSACK1/DSACKO signals. Refer to Table 5-1 for DSACK1/DSACKO encodings and assertion results. Tabie 5-1. DSACKT/DSACKO Encodings and Resuits DSACKT DSACKO Result Negated Negated Insert Wait States in Current Bus Cycle Negated Assented Complete CycleData Bus Port Size is 8 Bits Asserted Negated Complete CycleDala Sus Port Size is 16 Bits Asserted Asserted Complete CycleData Bus Port Size is 32 Bits For example, if the processor is executing an instruction that reads a long-word operand from a long-word-aligned address, it attempts to read 32 bits during the first bus cycle. (Refer to 5.2.2 Misaligned Operands for the case of a word or byte address.) if the port responds that it is 32 bits wide, the MC68020/EC020 latches ail 32 bits of data and continues with the next operation. If the port responds that it is 16 bits wide, the MC68020/EC020 latches the 16 bits of valid data and runs another bus cycle to obtain the other 16 bits. The operation for an 8-bit port is similar, but requires four read cycles. The addressed device uses the DSACK1/DSACKO signais to indicate the port width. For instance, a 32-bit device always returns DSACK1/DSACKO for a 32-bit port, regardless of whether the bus cycle is a byte, word, or long-word operation. Dynamic bus sizing requires that the portion of the data bus used for a transfer to or from a particular port size be fixed, A 32-bit port must reside on D31D0, a 16-bit port must reside on D32-D16, and an 8-bit port must reside on D31-D24. This requirement minimizes the number of bus cycies needed to transfer data to 8- and 16-bit ports and ensures that the MC68020/EC020 correctly transfers valid data. The MC68020/EC020 always attempts to transfer the maximum amount of data on all bus cycles; for a long- word operation, it always assumes that the port is 32 bits wide when beginning the bus cycle. The bytes of operands are designated as shown in Figure 5-3. The most significant byte of a jong-word operand is OPO; the least significant byte is OP3. The two bytes of a word- length operand are OP2 (most significant) and OP3. The single byte of a byte-length operand is OP3. These designations are used in the figures and descriptions that follow. MOTOROLA M68020 USER'S MANUAL 5-53 6 LONG-WORD OPERAND [ OPa OP) OP2 : OP? | 15 i) WORD OPERAND OP2 | OP3 | 7 0 BYTE OPERAND OP3 Figure 5-3. Internal Operand Representation Figure 5-4 shows the required organization of data ports on the MC68020/EC020 bus for 8-, 16-, and 32-bit devices. The four bytes shown in Figure 5-4 are connected through the internal data bus and data multiplexer to the external data bus. This path is the means through which the MC68020/EC020 supports dynamic bus sizing and operand misalignment. Refer to 5.2.2 Misaligned Operands for the definition of misaligned operand. The data multiplexer establishes the necessary connections for different combinations of address and data sizes. OPO opt oP2 ory REGISTER | 0 | { | 2 | 3 | MULTIPLEXER | ROUTING AND DUPLICATION i Lo ~ INTERNAL TO TT a ae mm L On Dea | D23-Di6 | D15-De o7-Do } = EMEC EXTERNAL DATA BUS EXTERNAL BUS ' Neon BYTE 0 | BYTE} BYTE 2 | aYTES | 32-BIT PORT INCREASING MEMORY \ ADDRESSES Oooo BYTE BYTE} 16-BIT PORT 2 BYTE 2 BYTE 3 xxxx0xxO BYTEO 1 BYTE | 8-BIT POAT 2 BYTE2 5 BYTE 3 Figure 5-4. MC68020/EC020 Interface to Various Port Sizes 5-6 M68020 USER'S MANUAL MOTOROLAThe multiplexer takes the four bytes of the 32-bit bus and routes them to their required positions. For example, OPO can be routed to D31-D24, as would be the normal case, or it can be routed to any other byte position to support a misaligned transfer. The same is true for any of the operand bytes. The positioning of bytes is determined by the SlZt, S1Z0, Al, and AO outputs. The $121 and SIZO outputs indicate the remaining number of bytes to be transferred during the current bus cycle, as listed in Table 5-2. Table 5-2. SIZ1, SIZO Signal Encoding $iz1 sizo Size Negated Asserted Byte Asserted Negated Word Asserted Asserted 3 Bytes Negated Negated Long Word The number of bytes transferred during a write or read bus cycle is equal to or iess than the size indicated by the SIZ1 and SIZO outputs, depending on port width and operand alignment. For example, during the first bus cycle of a lang-word transfer to a word port, the SIZ1 and S!ZO outputs indicate that four bytes are to be transferred, aithough only two bytes are moved on that bus cycle. A1A0 also affect operation of the data multiplexer. During an operand transfer, A31A2 (for the MC68020) or A23A2 (for the MC68EC020) indicate the long-word base address of that portion of the operand to be accessed; A1 and AO indicate the byte offset from the base. Table 5-3 lists the encodings of A1 and AO and the corresponding byte offsets from the long-word base. Table 5-3. Address Offset Encodings Al AQ Offset Negated Negated +0 Bytes Negated Asserted +1 Byte Asserted Negated +2 Bytes Asserted Asserted +3 Bytes MOTOROLA M68020 USER'S MANUAL 5-7Table 5-4 lists the bytes required on the data bus for read cycles. The entries shown as OP3, OP2, OP1, and OPO are portions of the requested operand that are read or written during that bus cycle and are defined by SIZ1, SIZO, Al, and AO for the bus cycle. Table 5-4. Data Bus Requirements for Read Cycles Transfer Size Address Exiernai Data Bytes External Dats Bytes ern Required Required Hequived Sizi | sizo} A1_| AO | D31-p24 023-018 D1s-Ds 07-Do | Da1-D24 D23-p1e | Dat-D24 Byte oy 1] oo] o {{ ops | | | J] [9-3 | o}1}o].s ff | ora | | Hf J _op3 || [ors] ofr fa fo lf] fora [|__| [ora | || [ors ofr fafa fp] [ fora J} {ors Tt [oes Word 1] 9 | o F o ff ope | ops | |} | {ore [ops] |] [ore] Popol. tL [ore forsT Jif [or | | or | tyo}lr]o ff | | or2 | ora J {[ ore [ ona |] [ore] i | | | op2 |] [- | op2 [| [op2 3 Bytes 1} 1 |e | || op: [ore [ors Td} [ or: | ore | ot | tt apo fa fh [| op: [ ope | ops ||| jor: Jt [opr] rf 171 ]o qf i | opr [| ore || [ or: [ ope |] [orn] tearya ts fp T | | opr |] [ | op: | LongWord | 0 J o | o | o |[ opo [ opt | ove | of3 |{ [oro | op: }| [ope] oyofots If | oro [ op: [ ove |} [ | oro |] [oro] o;o]s fo fT | opo | opi || [ oro [| ot || [oro] o}fofifta fff | oro |} [ { oro ]| [ope 5-8 M68020 USERS MANUAL MOTOROLAFable 5-5 lists the combinations of $121, SIZ0, At, and AO and the corresponding pattern of the data transfer for write cycles from the internal multiplexer of the MC68020/EC020 to the external data bus. Table 5-5. MC68020/EC020 Internal to External Data Bus MultiplexerWrite Cycles Teste | eg | ncsen Enigma Dai sizi] siza| at | ao | 031-p2423-p16 D15-p8 D7-pa Byle o | 1 | x | |[ ors | ops | opa | ops | Word \ o | x o || op2 | ops | op2 | ops | 1 o | x 1 || ope | ope | ops | op2 | 3 Bytes 1 | 1 | 0 | o [{ ops | op2 | ofa } opot | 1 | 1 | 0 | 1 |] opt | op: | ore | ops | 1 1 1 o || op: | op2 } opt | op2 | 1} 1] 1] 1 | opt [ opt | oper | ort | LongWord | 0 | o | o | o tf oPo | opr | ope | ops | o | o | o | + |[ oro | oro | ort | ore | o | o | 4 o || oro | op: { oro | opt | o | o | 1 [ 1 || oro | opo { opi* f opo | *Due to the current implementation, this byte is output but never used. x = Don't care NOTE: The OP tables on the external data bus refer to a particular byte of the operand that is written on that section of the data bus. MOTOROLA M66020 USERS MANUAL 5-9Figure 5-5 shows the transfer (write) of a long-word operand to a word port. In the first bus cycle, the MC68020/EC020 places the four operand bytes on the external bus. Since the address is iong-word aligned in this example, the multiplexer follows the pattern in the entry of Table 5-5 corresponding to SIZ0, SIZ1, AO, A1 = 0000. The port latches the data on D31D16, asserts DSACK1 (DSACKO remains negated), and the processor terminates the bus cycle. It then starts a new bus cycle with SIZ1, SIZO, A1, AO = 1010 ta transfer the remaining 16 bits. SIZ1 and SIZOQ indicate that a word remains to be transferred; Al and AO indicate that the word corresponds to an offset of two from the base address. The multiplexer follows the pattern corresponding to this configuration of SIZ1, SIZO, A1, and AO and places the two least significant bytes of the long word on the word portion of the bus (D31D16). The bus cycle transfers the remaining bytes to the word-sized port. Figure 5-6 shows the timing of the bus transfer signals for this operation. Hn LONG-WORD OPERAND 0 { OPO OPI | OP2 OP3 031 DATA BUS Dis WORD MEMORY MC6B020/E0020 MEMORY CONTROL MsB LSB sizi 120 Al AQ DSACKI = DSACKO OPO OPI 0 0 0 0 L H oP? oP4 1 a 1 0 L H Figure 5-5. Long-Word Operand Write to Word Port Example 5-10 M68020 USER'S MANUAL MOTOROLADSACK1 DSACKO / ** DBEN \ / \ b31-D24 i a, op? canon (a) mm p< WORD WRI te >< wore WRI - LONG- WORD OPERAND WRITE TO 16-BIT PORT * For the MC68EC020, A23-A2. ** This signal does not apply to the MC6BECO20. Figure 5-6. Long-Word Operand Write to Word Port Timing MOTOROLA M68020 USER'S MANUAL 5-14Figure 5-7 shows a word write to an 8-bit bus example requires two bus cycles. Each bus c for the first cycle specify two bytes: for the se associated bus transfer signal timing. 15 WORD OPERAND 0 | T | OP3 | O31 DATABUS D24 _ BYTE MEMORY MCEBO207EC020 MEMORY CONTROL $i21 5120 AT AO OSACKI OP2 1 6 @ o OPI o 106 41 Figure 5-7. Word Operand Write to Byte Port Example M68020 USERS MANUAL port. Like the preceding example, this ycle transfers a single byte. SIZ1 and SIZO cond cycle, one byte. Figure 5-8 shows the MOTOROLAo [~LPLPLPLe Pr. * AII-A2 x Al AQ FC2-FG SIZ4 X x _/ so \ foo LS VS DSACKI f DSACKO / \ / \ ** DBEN / \ f \ Da1-024 oP2 oP3 023-016 (ors oPa v0 (THR m 070 (aD of Pw BYTE WRITE ->| BYTE WRITE <---_- WORD OPERAND WRITE --| * For the MC69EC020, A23-A2 ** This signal does not apply to the MC6SE C020. Figure 5-8. Word Operand Write to Byte Port Timing MOTOROLA M68020 USERS MANUAL5.2.2 Misaligned Operands Since operands may reside at any byte boundary, they may be misaligned A byte operand is properly aligned at any address: a word operand is misaligned at an add address, a long word is misaligned at an address that is not evenly divisible by four. The MC68000, MC68008, and MC68010 implementations allow long-word transfers on odd- word boundaries but force exceptions if word or long-word operand transfers are attempted at odd-byte addresses. Although the MC68020/EC020 does not enforce any alignment restrictions for data operands (including PC relative data addresses), some performance degradation occurs when additional bus cycles are required for long-word or word operands that are misaligned. For maximum performance, data items should be aligned on their natural boundaries. All instruction words and extension words must reside on word boundaries. Attempting to prefetch an instruction word at an odd address causes an address error exception. Figure 5-9 shows the transfer (write) of a long-word operand to an odd address in word- organized memory, which requires three bus cycles. For the first cycle, SIZ1 and SIZO specify a long-word transfer, and A2-AO = 001. Since the port width is 16 bits, only the first byte of the long word is transferred. The slave device latches the byte and acknowledges the data transfer, indicating that the port is 16 bits wide. When the processor starts the second cycle, SIZ1 and SIZO specify that three bytes remain to be transferred with A2-AO = 010. The next two bytes are transferred during this cycle. The processor then initiates the third cycle, with SIZ? and SIZO indicating one byte remaining to be transferred with A2-AO = 100. The port latches the final byte, and the Operation is complete. Figure 5-10 shows the associated bus transfer signal timing. Figure 5-11 shows the equivalent operation for a data read cycle. af LONG-WORD OPERAND 0 tL OPO OP1 OP2 OP3 | O31 DATA BUS B16 WORD MEMORY, MCSD 20/EC020 MEMORY CONTROL MSB LSB S121 S20 A2 ALA OSACK1 DSACKO OOK OPO Q G Q 0 1 L H OP OP2 1 1 0 1 0 L H OP3 XXX 0 1 1 0 0 L H Figure 5-9. Misaligned Long-Word Operand Write to Word Port Example 5-14 M68020 USER'S MANUAL MOTOROLAAl SIZ1 sIzo PEGS #* OCS AS DS DSACK1 NNN NNN DSACKO + OBEN 7 \ {/_ {\ ona D7-00 (ore Opa -< BYTE WRITE a WORD WRITE he BYTE WRITE ($$ LONG-WORD OPERAND WRITE ---___+ ae 2 aol rae) * For the MC6BEC020, A23-A2_ ** This signal does not apply to the MC68ECO20. Figure 5-10. Misaligned Long-Word Operand Write to Word Port Timing MOTOROLA M68020 USER'S MANUAL 5:15a LONG-WORD OPERAND (REGISTER} o [ OPO OP1 OP? OP | B31 DATA BUS 016 L _| WORD MEMORY MC68020/EC020 MEMORY CONTROL MSB LSB $IZ1 SHO A2 Al AO DSACK DSACKO XXX oro o 0 @ o 1 L H OP! op2 1 1 0 1 0 L H Opa XXX | o 1 1 0 L H Figure 5-11. Misaligned Long-Word Operand Read from Word Port Example Figures 5-12 and 5-13 show a word transfer (write) to an odd address in word-organized memory. This example is similar to the one shown in Figures 5-9 and 5-10 except that the operand is word sized and the transfer requires only two bus cycles. Figure 5-14 shows the equivalent operation for a data read cycle. 16 WORD OPERAND 0 | ope on | Y 031 DATA BUS D16 [ J Y WORD MEMORY MCEB02WECO20 MEMORY CONTROL MSB LSB SIZ1 S20 A2 Al AO BSACKI + OSACKO bee OP2 1 8 @ 0 4 L H ora OL o ft 60 1 9 L H Figure 5-12. Misaligned Word Operand Write to Word Port Example 5-16 M66020 USER'S MANUAL MOTOROLAFC2-CO 3izi _/ Xx _/ so \ fo , AS NS z| D31-D24 OP2 OPI v5.09 (i _) or or om WORD WRITE >< BYTE WRITE-3 WORD OPERAND WRITE TO Al, AC = 01. -m4 For the MC68EC020, A23-A2. ** This signal does not apply to lhe MC68ECO20 Figure 5-13. Misaligned Word Operand Write to Word Port Timing MOTOROLA M68020 USERS MANUAL15 WORD OPERAND (REGISTER) 0 | OP2 OP3 A 031 DATA BUS O16 C = N WORD MEMORY MO68020/EC020 MEMORY CONTROL MSB LSB SIZ1 SIZ0 A2 AT AO OSACK1 DSACKO XXX OP2 1 0 Go oo f L H OP3 XXX | o 1 60 1 6 L H Figure 5-14. Misaligned Word Operand Read from Word Bus Example Figures 5-15 and 5-16 show an example of a long-word transfer (write) to an odd address in long-word-organized memory. In this example, a long-word access is attempted beginning at the least significant byte of a long-word-organized memory. Only one byte can be transferred in the first bus cycle. The second bus cycle then consists of a three- byte access to a long-word boundary. Since the memory is long word organized, no further bus cycles are necessary. Figure 5-17 shows the equivalent operation for a data read cycle. au LONG-WORD OPERAND 0 | OPO oPt OP2 OP3 | Y Dat DATA BUS DO LONG-WORD MEMORY MC68020/E.C020 MEMORY CONTROL MSB UMB LMB LSB SiZ1 SIZO Az Al AG DSACK* DSACKO KXX XX OOK OPO G a 1 L L OP1 OP2 OP3 XXX 1 1 1 oO L L Figure 5-15. Misaligned Long-Word Operand Write to Long-Word Port Example 5-18 M68020 USERS MANUAL MOTOROLASIZ0 Z| _ _ ae \_/ \/ ~\_S #* 005 al DSACKO DSACKI f \ f \ **DBEN / \ f \ Discs OPI OP3 0709 Cm) oF BYTE WRITE ~ p< 3-BYTE WRITE 3 <-___- LONG. WORD OPERAND WRITE * For the MCG8ECO20, Az3-A2 ** This signal does not appiy to the MC68EC020 Figure 5-16. Misaligned Long-Word Operand Write to Long-Word Port Timing MOTOROLA M68020 USERS MANUAL 5-19i LONG-WORD OPERAND (REGISTER) 0 | OPO OPI OP2 | OP3 A ov DATA 8US po LONG- WORD MEMORY MCEB020/ECO20 MEMORY CONTROL MSB UMB LMB LSB Sizt SiZ0 AZ Al AQ DSACK! DSACKO XXX XXX XXX OPO 9 oo Oo f 1 L L OPt oP2 oP3 XXX + 1 4 0 0 L L Figure 5-17. Misaligned Long-Word Operand Read from Long-Word Port Example 5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment The combination of operand size, operand alignment, and port size determine the number of bus cycles required to perform a particular memory access. Table 5-6 lists the number of bus cycles required for different operand sizes to different port sizes with all possible alignment conditions for read/write cyctes. Table 5-6. Memory Alignment and Port Size Influence on Read/Write Bus Cycles Number of Bus Cycles (Data Port Size = 32 Bits:16 Bits:8 Bits) Ai, AO Operand Size 00 01 10 14 Instruction* 1:24 N/A N/A NIA Byte Operand 11 at 1:41 tad Word Operand bb2 1.2.2 W4:2 2:2:2 Long-Word Operand 12.4 234 2:2:4 23:4 *Instruction prefetches are always two words from a long-word boundary Table 5-6 reveals that bus cycle throughput is significantly affected by port size and alignment. The MC68020/EC020 system designer and programmer should be aware of and account for these effects, particularly in time-critical applications. 5-20 M68020 USERS MANUAL MOTOROLATable 5-6 demonstrates that the processor always prefetches instructions by reading a long word from a long-word address (A1, AO = 00), regardless of port size or alignment. When the required instruction begins at an odd-word boundary, the processor attempts to fetch the entire 32 bits and loads both words into the instruction cache, if possible, although the second one is the required word. Even if the instruction access is not cached, the entire 32 bits are latched into an internal cache hoiding register from which the two instructions words can subsequently be referenced. Refer to Section 8 Instruction Execution Timing for a complete description of the cache holding register and pipeline operation. 5.2.4 Address, Size, and Data Bus Relationships The data transfer examples show how the MC68020/EC020 drives data onto or receives data from the correct byte sections of the data bus. Table 5-7 shows the combinations of the SIZ1, SIZO, A1, and AO signats that can be used to generate byte enable signals for each of the four sections of the data bus for read and write cycles if the addressed device requires them. The port size also affects the generation of these enable signals as shown in the table. The four columns on the right correspond to the four byte enable signals. Letters B, W, and L refer to port sizes: B for 8-bit ports, W for 16-bit ports, and L for 32-bit ports. The letters B, W, and L imply that the byte enable signal should be true for that port size. A dash () implies that the byte enable signal does not apply. The MC68020/EC020 always drives all sections of the data bus because, at the beginning of a write cycle, the bus controller does not know the port size. Tabie 5-7 reveals that the MC68020/EC020 transfers the number of bytes specified by SIZ1, SIZO to or from the specified address unless the operand is misaligned or unless the number of bytes is greater than the port width. In these cases, the device transfers the greatest number of bytes possible for the port. For example, if the size is four and Ai, AO = 01, a 32-bit slave can only receive three bytes in the current bus cycle. A 16- or 8-bit slave can only receive one byte. The table defines the byte enables for all port sizes. Byte data strobes can be obtained by combining the enable signals with the DS signal. Devices residing on 8-bit ports can use the data strobe by itself since there is only one valid byte for every transfer. These enable or strobe signals select only the bytes required for write or read cycles. The other bytes are not selected, which prevents incorrect accesses in sensitive areas such as I/O. MOTOROLA M68020 USERS MANUAL 5-21Table 5-7. Data Bus Byte Enable Signals for Byte, Word, and Long-Word Ports Data Bus Active Sections Byte (B), Word (W) , Long-Word (L) Ports Transfer Size Stz1 SIzo Al AO 031-D24 D23-D16 015-08 D7-De Byte 0 1 0 0 BWL 0 1 0 1 B WL : 0 1 1 0 BW - i - 0 t 1 1 B Ww L Ward 1 0 0 0 BWL WL 1 0 0 1 B WL L 1 0 t 0 aw Ww L L 1 0 t 1 B Ww . L 3 Bytes 1 1 0 6 BWL WL L - 1 1 0 j B WL L L 1 1 1 a BW Ww L L 1 1 1 1 B Ww - L Long Word 0 0 Q 0 BWL WL L L 0 0 0 1 B WL L L 0 0 { 0 BW Ww L L 0 0 1 1 B w _ L Figure 5-18 shows a logic diagram of one method for generating byte enable signals for 16- and 32-bit ports from the SIZ1, SIZO, A1, and AO encodings and the R/W signal. 5.2.5 Cache Interactions The organization and requirements of the on-chip instruction cache affect the interpretation of DSACK1 and DSACKO. Since the MC68020/EC020 attempts to load all instructions into the on-chip cache, the bus may operate differently when caching is enabled. Specifically, on read cycles that terminate normally, the A1, AO, SIZ1, and SIZ0 signals do not apply. The cache can also affect the assertion of AS and the operation of a read cycle. The search of the cache by the processor begins when the sequencer requires an instruction. At this time, the bus controller may also initiate an external bus cycle in case the requested item is not resident in the instruction cache. Hf an internal cache hit occurs, the external cycle aborts, and AS is not asserted. For the MC68020, if the bus is not occupied with another read or write cycle, the bus controller asserts the ECS signal (and the OCS signal, if appropriate). It is possible to have ECS asserted on multiple consecutive clock cycles. Note that there is a minimum time specified from the negation of ECS to the next assertion of EGS (refer to Section 10 Electrical Characteristics). instruction prefetches can occur every other clock so that if, after an aborted cycle due to an instruction cache hit, the bus controller asserts ECS on the next clock, this second cycle is for a data fetch. Note that, if the bus controller is executing other cycles, these aborted cycles due to cache hits may nol be seen externally. 5-22 M68020 USER'S MANUAL MOTOROLAUMD LMD LLO Al size UUD UPPER UPPER DATA (32-BIT PORT) UMD = UPPER MIDDLE DATA (32-BIT PORT} LMD = LOWER MIDDLE DATA (32-BIT PORT) LLD = LOWER LOWER DATA (22-BIT POAT} UD UPPEA DATA (16-BIT PORT) LD = LOWER DATA (16-8iT PORT} siZ\ RW NOTE: These select lines can be combined with the address decode circuilry or all can be generated within the same Programmed array logic unil. Figure 5-18. Byte Enable Signal Generation for 16- and 32-Bit Ports MOTOROLA M68020 USER'S MANUAL 9-235.2.6 Bus Operation The MC68020/EC020 bus is used in an asynchronous manner allowing external devices to operate at clock frequencies different from the MC68020/EC020 clock. Bus operation uses the handshake lines (AS, DS, DSACKO, DSACKT, BERR, and HALT) to control data transfers. AS signals the start of a bus cycle, and DS is used as a condition for valid data on a write cycle. Decoding $!Z1, SIZO, A1, and AO provides byte enable signals that select the active portion of the data bus. The slave device (memory or peripheral) then responds by placing the requested data on the correct portion of the data bus for a read cycle or latching the data on a write cycle and by asserting the DSACKO/DSAGK{ combination that corresponds to the port size to terminate the cycle. If no slave responds or the access is invalid, external control logic asserts BERR to abort or BERR and HALT to retry the bus cycle, DSACK1/DSACKO can be asserted before the data from a slave device is valid on a read cycle. The length of time that DSACK1/DSACKG may precede data is given by parameter #31, and it must be met in any asynchronous system to ensure that valid data is latched into the processor. (Refer to Section 10 Electrical Characteristics for timing parameters.) Note that no maximum time is specified from the assertion of AS to the assertion of DSACK1/DSACKO. Although the processor can transfer data in a minimum of three clock cycles when the cycle is terminated with DSACK1/DSACKO, the processor inserts wait cycles in clock period increments until ODSACK1/DSACKO is recognized. The BERR and/or HALT signals can be asserted after DSACK1/DSACKO is asserted. BERR and/or HALT must be asserted within the time given (parameter #48), after DSACK1/DSACKO is asserted in any asynchronous system. If this maximum delay time is violated, the processor may exhibit erratic behavior. 5.2.7 Synchronous Operation with DSACK1/DSACKO Although cycles terminated with DSACK1/DSACKO are classified as asynchronous, cycles terminated with DSACK1/DSACKO can also operate synchronously in that signals are interpreted relative to clock edges. The devices that use these synchronous cycles must synchronize the responses to the MC68020/EC020 clock. Since these devices terminate bus cycles with DSACK1/DSACKO, the dynamic bus sizing capabilities of the MC68020/EC020 are available. In addition, the minimum cycle time for these synchronous cycles is three clocks. To support systems that use the system clock to generate DSACK1/DSACKO and other asynchronous inputs, the asynchronous input setup time (parameter #47A) and the asynchronous input hold time (parameter #47B) are provided in Section 10 Electrical Characteristics. (Note: although a misnomer, these asynchronous parameters are the setup and hold times for synchronous operation.) If the setup and hoid times are met for the assertion or negation of a signal, such as DSACK1/DSACKO, the processor can be guaranteed to recognize that signal level on that specitic falling edge of the system clock. If the assertion of DSACK1/DSACK6O is recognized on a particular falling edge of the clock, valid data is latched into the processor (for a read cycle) on the next falling clock edge provided the data meets the data setup time (parameter #27). In this case, parameter #31 5-24 M68020 USERS MANUAL MOTOROLAfor asynchronous operation can be ignored. All timing parameters referred to are described in Section 10 Electrical Characteristics. If a system asserts DSACK1/DSACKO for the required window around the falling edge of state 2 and obeys the proper bus protocol by maintaining DSACK1/DSACKO (and/or BERA/HALT) unt and throughout the clock edge that negates AS (with the appropriate asynchronous input hold time specified by parameter #47B), no wait states are inserted. The bus cycle runs at its maximum speed of three clocks per cycle for bus cycles terminated with DSACK1/DSACKO. To ensure proper operation in a synchronous system when BERR or BERB/HALT is asserted after DSACK1/DSACKO, BERR (and HALT) must meet the appropriate setup time (parameter #27A) prior to the falling clock edge one clock cycle after DSACKT/DSACKO is recognized. This setup time is critical, and the MC68020/EC020 may exhibit erratic behavior #f it is violated. When operating synchronously, the data-in setup (parameter #27) and hold (parameter #30) times for synchronous cycles may be used instead of the timing requirements for data relative to the DS signal. 5.3 DATA TRANSFER CYCLES The transfer of data between the processor and other devices involves the following signals: * Address Bus (A31A0 for the MC68020) (A23-A0 for the MC68EC020) * Data.Bus (D31-D0) * Control Signals The address and data buses are both parallel, nonmultiplexed buses. The bus master moves data on the bus by issuing control signals, and the bus uses a handshake protocol to ensure correct movement of the data. In all bus cycles, the bus master is responsible for de-skewing all signals it issues at both the start and end of the cycle. In addition, the bus master is responsible for de-skewing DSACK1/DSACKO, D31-D0, BERR, HALT, and, for the MC68020, DBEN from the stave devices. The following paragraphs define read. write, and read-modify-write cycle operations. Each of the bus cycles is defined as a succession of states. These states apply ta the bus operation and are different from the processor states described in Section 2 Processing States. The clock cycles used in the descriptions and timing diagrams of data transfer cycles are independent of the clock frequency. Bus operations are described in terms of external bus states. MOTOROLA M68020 USERS MANUAL 5-255.3.1 Read Cycle During a read cycle, the processor receives data from a memory, coprocessor, or peripheral device. |f the instruction specifies a long-word operation, the MC68020/EC020 attempts to read four bytes at once. For a ward operation, it attempts to read two bytes at once and for a byte operation, one byte. For some operations, the processor requests a three-byte transfer. The processor properly positions each byte internally. The section of the data bus from which each byte is read depends on the operand size, A1A0. and the port size. Refer to 5.2.1 Dynamic Bus Sizing and 5.2.2 Misaligned Operands for more information on dynamic bus sizing and misaligned operands. Figure 5-19 is a flowchart of a long-word read cycle. Figure 5-20 is a flowchart of a byte read cycle. Figures 5-21-5-23 are read cycle timing diagrams in terms of clock periods. Figure 5-21 corresponds to byte and word read cycles from a 32-bit port. Figure 5-22 corresponds to a long-word read cycle from an 8-bit port. Figure 5-23 also applies to a long-word read cycle, but from 16- and 32-bit ports. PROCESSOR EXTERNAL DEVICE ADDRESS DEVICE *1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2) SET RAV TO READ ##4) DRIVE ADDRESS ON A31-A0 4) DRIVE FUNCTION CODE ON FC2-FCO 5) DRIVE SIZ1, SIZO (FOUR BYTES) 6} ASSERT AS 7) ASSERT OS a PRESENT DATA #8) ASSERT OBEN 1) DECODE ADDRESS 2) PLACE DATA ON 031-0 3) ASSERT DSACK1/DSACKO ACQUIRE DATA 1) LATCHDATA 2) NEGATE AS AND 05 *3) NEGATE OBEN > TERMINATE CYCLE y 1) REMOVE DATA FROM 031-Do 2) NEGATE DSACK1/DSACKO START NEXT CYCLE * This step does not apply ta the MC68ECO20. ** For the MC6BECO20, A23-AQ. Figure 5-19. Long-Word Read Cycle Flowchart 5-26 M68020 USER'S MANUAL MOTOROLAPROCESSOR EXTERNAL DEVICE ADDRESS DEVICE #1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2) SET RAV TO READ **3) DRIVE ADDRESS ON A31-A0 4) DRIVE FUNCTION CODE ON FC2-FCO 5} DRIVE SIZ1, SIZo (FOUR BYTES) 6) ASSERT AS 7) ASSEAT OS +8) ASSERT OBEN PRESENT DATA 1) DECODE ADDRESS 2) PLACE DATA ON 031-D24 OR 023-D16 OR DI5-D8 OR 07-00 (BASED ON Al, AO, AND BUS WIDTH) 3) ASSERT DSACKTASACKO ACQUIRE DATA < 1} LATCHDATA 2) NEGATE AS AND 65 *3) NEGATE DREN > TERMINATE CYCLE y 1) REMOVE DATA FROM D31-Do 2) NEGATE DSACKi/DSACKO START NEXT CYCLE * This step does not apply to the MC6BECO29. ** For the MC6BEC020, A23A0, Figure 5-20. Byte Read Cycle Flowchart MOTOROLA M68020 USER'S MANUAL 5-27tastaz OX xX x aN / nN fo Foarco XX Xx Xx sai \ oo WorD / BvIE rw / ams \_/ \/ \_/ os (\_/S VS VS BN SN NY BN SP NY NV a rn A A so Nf Nf NL bex-og "ona nm ~< WORD READ ><_ BYTE READ a BYTE READ >| For the MC68EC020, A23-A2 ** This signal does not apply to the MC6SEC020 Figure 5-21. Byte and Word Read Cycles32-Bit Port 5-28 M68020 USERS MANUAL MOTOROLASo $2 $4 SO ? Sa SO $2 $4 50 S2 $4 sonae TX a x a Al rearoa XX xX Xo x $1Z1 \ f ee LONG WORD BYTE WORD BYTE 3120 **ECS _/ XS os (\_/ AS Os DSACKI NY NI NNN LS NY NNN TN _/ pee NNN TF" SNS NNN F*TO, ** DBEN oa (we) Ca) (ee) w Dea-D16 07-Do \ ~SN 015-8 > oN / BYTE READ >|. BYTE READS, we BYTE READ > Pat LONG-WORD OPERAND READ FROM 16-BIT PORT am * For the MC68EC020, Az3_A2 ** This signal does not apply to tha MC68ECO20. Figure 5-23. Long-Word Read16- and 32-Bit Ports 5-39 M68020 USERS MANUAL MOTOROLAState 0 MC68020The read cycle starts in state 0 (SO). The processor asserts EGS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a read operation, OCS is asserted simultaneously. During SO. the processor places a valid address on A31A0 and valid function codes on FC2FCO. The function codes select the address space for the cycle. The processor drives R/W high for a read cycle and negates DBEN to disable the data buffers. SIZO and SIZ1 become valid, indicating the number of bytes requested to be transferred. MC68EC020The read cycle starts in SO. During SO, the processor places a valid address on A23A0 and valid function codes on FC2-FCO. The function codes select the address space for the cycle. The processor drives R/W high for a read cycle. SIZO and S121 become valid, indicating the number of bytes requested to be transferred. State 1 MC68020 One-half clock later in state 1 (S1}, the processor asserts AS, S, indicating that the address on the address bus is valid. The processor also asserts DS during S1. in addition, the ECS (and OCS, if asserted) signa! is negated during S1. MC68EC020--One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DS during $1. State 2 MC68020During state 2 (S2), the processor asserts DBEN to enable external data buffers. The selected device uses R/W, SIZ1-SIZO, A1A0, and DS to place its information on the data bus. Any or ail of the bytes (D31-D24, D23-D16, D15-D8, and D7-DO) are selected cted by SIZ1-SIZO and A1-A0O. Concurrently, the selected device asserts DSACK1/DSACKO. MC68EC020During S2, the selected device uses R/W, SIZ1S!Z0, A1A0Q, and DS to place its information on the data bus. Any or all of the bytes (D31-D24, D23-D16, D15-D8, and D7-D0) are selected cted by SIZ1-SIZO and A1-A0. Concurrently, the selected device asserts DSACK1/DSACKO. State 3 MC68020/EC020--As long as at least one of the DSACK1/DSACKO signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACK1/DSACKCO is not recognized by the start of state 3 (S3), the processor inserts wait states instead of proceeding to states 4 and 5. To ensure that wait states are inserted, both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACK1/DSACKO signals on the falling edges of the clock until an assertion is recognized. MOTOROLA M68020 USER'S MANUAL 5-31State 4 MC68020/ECO020At the end of state 4 ($4), the processor latches the incoming data. State 5 MC68020The processor negates AS, DS, and DBEN during state 5 ($5). It holds the address valid during S5 to provide address hold time for memory systems. R/W, SIZ1- $120, and FC2-FCO also remain valid throughout S5. The external device keeps its data and DSACKT/DSACKO signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK1/DSACKO within approximately one clock period after sensing the negation of AS or DS. DSACKT/DSACKO signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MC68EC020The processor negates AS and DS during state S5. It holds the address valid during SS to provide address hold time for memory systems. R/W, SIZ1. SIZO, and FC2-FCO also remain valid throughout S5. The external device keeps its data and DSACK1/DSACGKO0 signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK1/DSACKO within approximately one clock period after sensing the negation of AS or DS. DSACKT/DSACKO signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 5-32 M68020 USER'S MANUAL MOTOROLA5.3.2 Write Cycle During a write cycle, the processor transfers data to memory or a periphera! device. Figure 5-24 is a flowchart of a write cycle operation for a long-ward transfer. Figures 5-25- 5-28 are write cycle timing diagrams in terms of clock periods. Figure 5-25 shows two write cycles (between two read cycles with no idle time in between) for a 32-bit port. Figure 5-26 shows byte and word write cycles to a 32-bit port. Figure 5-27 shows a long- word write cycle to an 8-bit port. Figure 5-28 shows a long-word write cycle to a 16-bit port. PROCESSOR EXTERNAL DEVICE ADDRESS DEVICE *1) ASSERT ECS/OCS FOR ONE-HALF CLOCK **2) DRIVE ADDRESS ON A31-A0 3} DRIVE FUNCTION CODES ON FC2-FCO 4) DRIVE Siz1, SIZo (FOUR BYTES) 5) SET RAV TO WRITE ) ASSERT AS *7) ASSERT OBEN 8) DRIVE GATA LINES D31~Do ~~ c 6) ASSERT 65 ACCEPT DATA 1) DECODE ADDRESS 2) STORE DATA FROM 031-Do 3) ASSERT OSACKIMDSACKO TERMINATE OUTPLIT TRANSFER a 1} NEGATE AS AND DS 2) REMOVE DATA FROM D31-Do *3) NEGATE OBEN > TERMINATE CYCLE 7 1) NEGATE DSACKI/DSACKO [ START NEXT CYCLE | * This step does not apply to the MC6SEC020. ** For the MC68EC020, A23A0. Figure 5-24. Write Cycle Flowchart MOTOROLA M66020 USER'S MANUAL 5-33LONG WORD i DSACKI ON Of Kf St DSACKO ee ey A ey A ey A ** DBEN / \ { \ / \ / p89, 0) x: BYTE READ >< write >< WRITE >|<_ READ WITH WAIT STATES >| * For the MC68EC020, A23-A2. ** This signal does not apply to the MC6SEC0O20 Figure 5-25. Read-Write-Read Cycles32-Bit Port 5-34 M68020 USERS MANUAL MOTOROLARi tt ECS (NS \ f "OS NS \S/ NN NL 6 \_/ \ / \ / om ff Nf NN OSAGKO So \ J NTF ** DBEN ~~ \ 08 on sa 07-Do OPI OP? OP) \~<- WORD ALTE eee BYTE WRITE << BYTE WRITE >| * For the MC68ECO20, A23-A2 ** This signal does not apply to the MC68ECO20. Figure 5-26, Byte and Word Write Cycles32-Bit Port MOTOROLA M68020 USER'S MANUAL 5-35ox PLE LP LP LE LSLS LPL Le Lee. sore X me x x \ Al FozFo xX x x st \ / ee LONG WORD 3-BYTE WORD BYTE 3120 \ / \ / t*ocs cs \_S LS \/S VS ial DSACKI DSACKG NN NN mp NNN NLS _/ S\N SNS NY ** OBEN paz | op) Ops OP2 OP3 a4 opi} oPt DiS-De OP2 OP2 OP2 OP3 OP3 OP4 OPI < BYTE wettest BYTE WRITE omfg BYTE WRITE >< BYTE WRITE 4 (<8 LONG-WORD OPERAND WRITE TO 8-BIT PORT -__--- mn b23-D16 9 3 D?7- 1 * For the MC68EC020, A23-A2. ** This signal does not appty to the MC6SECO20. Figure 5-27. Long-Word Operand Write8-Bit Port 5-36 M68020 USER'S MANUAL MOTOROLAAl FC2Co I x = = a on fF" = = \S \Y LONG WORD WORD LONG WORD 5120 *tECS OCS al DSACKI NN NN BN NN So WS NY F*N CSACKO D23-D16 OP1 Opa OPY 015-De OP2 OP2 OP? D?7-Da OP3 OP3 OP3 < >< wor WRITE- - os LenS ORO WRITE > < ~-- LONG WORD OPERAND WRITE TO 16 BIT PORT - _ | " For the MC6B8ECO020, A23--A2. ** This signal does not apply to the MC6BECO20 Figure 5-28. Long-Word Operand Write16-Bit Port MOTOROLA M68020 USER'S MANUAL 5.37State 0 MC68020 - The write cycle starts in SO. The processor negates ECS, indicating the beginning of an external cycle. If the cycle is the first external cycle of a write operation, OCS is asserted simultaneously. During SO, the processor places a valid address on A31--AO and valid function codes on FC2-FCO. The function codes select the address space for the cycle. The processor drives R/W low for a write cycle. SiZ1 SIZO become valid, indicating the number of bytes to be transferred. MC68EC020-The write cycle starts in SQ. During SO, the processor places a valid address on A23--A0 and valid function codes on FC2-FCO. The function codes select the address space for the cycle. The processor drives R/W low for a write cycle. SiZ1, 3IZ0 become valid, indicating the number of bytes to be transferred. State 1 MC68020One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DBEN during $1, which can enable external data buffers. In addition, the ECS (and OCS, if asserted) signal is negated during $1. MC68EC020 One-half clock later in S1, the processor asserts AS, indicating that the address on the address bus is valid. State 2 MC68020/EC020-During S2, the processor places the data to be written onto D31Do. At the end of S2, the processor samples DSACK1/DSACKO. State 3 MC68020/EC020The processor asserts DS during S3, indicating that the data on the data bus is stable. As long as at least one of the DSACKI/DSAGKO signals is recognized by the end of S2 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK1/DSACKO is not recognized by the start of S3, the processor inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of $2. If wait states are added, the processor continues to sample the DSACKT/DSAGKO signals on the falling edges of the clock until one is recognized. The external device uses R/W, DS, SIZ1, SIZ0, A1, and AO to latch data from the appropriate byte(s) of the data bus (D31-D24, D23-D16, D15D8, and D?7-D0). SI71, 5IZO, Ai, and AO select the bytes of the data bus. If it has not already done so, the device asserts DSACK1/DSACKO to signal that it has successfully stored the data. 5-38 M68020 USERS MANUAL MOTOROLAState 4 MC68020/EC020The processor issues no new control signals during S4. State 5 MC68020-The processor negates AS and DS during S5. tt holds the address and data valid during S5 to provide address hold time for memory systems. R/W, SIZ1, SIZO, FC2-FCO, and DBEN also remain valid throughout S5. The external device must keep DSACKt/DSACKO asserted until it detects the negation of AS or DS {whichever it detects first). The device must negate DSACK1/DSACKO within approximately one clock period after sensing the negation of AS or DS. DSACK1/DSACKO signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. MC68EC020The processor negates AS and DS during S5. It holds the address and data valid during S5 to provide address hold time for memory systems. R/W, SiZ1, SIZO, and FG2-FC0 also remain valid throughout S5. The external device must keep DSACK1/DSACKO asserted until it detects the negation of AS or DS (whichever it detects first). The device must negate DSACK1/DSACKO within approximately one clock period after sensing the negation of AS or DS. DSACK1/DSACKO signals that remain asserted beyond this limit may be prematurely detected for the next bus cycle. 5.3.3 Read-Modify-Write Cycle The read-modify-write cycle performs a read, conditionally modifies the data in the arithmetic logic unit, and may write the data out to memory. In the MC68020/EC020, this operation is indivisible, providing semaphore capabilities for multiprocessor systems, During the entire read-modify-write sequence, the MC68020/EC020 asserts RMC to indicate that an indivisible operation is occurring. The MC68020/EC020 does not issue a BG signa! in response to a BR signal during this operation. The TAS, CAS, and CAS2 instructions are the only MC68020/EC020 instructions that utilize read-modify-write operations. Depending on the compare results of the CAS and CAS2 instructions, the write cycle(s) may not occur. Figure 5-29 is a flowchart of the read-modify-write cycle operation. Figure 5-30 is an example timing diagram of a TAS instruction specified in terms of clock periods. MOTOROLA M68020 USERS MANUAL 5-39PROCESSOR LOCK BUS 1) ASSEAT RMC \ ADDRESS DEVICE *1) ASSERT ECS/OCS FOR ONE-HALF CLOCK 2) SET RAW TO READ #43) DRIVE ADDRESS ON A31-A0 4) DRIVE FUNCTION CODES ON FC2-FCO EXTERNAL DEVICE 5) DRIVE siz1, Sizo &} ASSEAT AS 7) ASSERT DS #8) ASSERT OBEN aaa PRESENT DATA 1} DECODE ADDRESS 2) PLACE DATA ON D21-D0 | 3) ASSERT DSACKI/DSACKO START NEXT CYCLE * This step does not apply to the MC68ECoO20. ** For the MC6B8ECO20, A23A0. ACQUIRE DATA 1) LATCH DATA IF CAS2 INSTRUCTION 2) NEGATE AS AND DS AND ONLY ONE OPERAND +3) NEGATE DBEN READ, THEN GO TO (4): 4) START DATA MODIFICATION IF OPERANDS DO NOT > TERMINATE CYCLE MATCH, THEN GO To ; ELSE GO TO 1) REMOVE DATA FROM D31-D0 OH 2) NEGATE DSACKIOSACKO START OUTPUT TRANSFER *1) ASSERT ECS/OCS FOR ONE-HALF CLOCK **2) DRIVE ADDRESS ON A31-A0 (IF DIFFERENT) 3} DRIVE $21, $izo Y 4} SET RAV TO WRITE 5} ASSERT AS +6) ASSERT OBEN 7} PLACE DATA ON D31-Do 8) ASSERT 05 > ACCEPT DATA 1} DECODE ADDRESS 7 2) STORE DATA FROM 031-D0 4) ASSERT DSACK10SACKO @) TERMINATE OUTPUT TRANSFER IF CASZ INSTRUCTION 1) NEGATE AS AND DS AND ONLY ONE OPERAND 2) REMOVE DATA FROM D31-Do WRITTEN, THEN GO TO *3) NEGATE OBEN a TERMINATE CYCLE (0) ELSE GOTO 1) NEGATE DSACK 1/0SACKO > y UNLOCK BUS 1) NEGATE RMC A Y Figure 5-29. Read-Modify-Write Cycle Flowchart 5-40 M68020 USERS MANUAL MOTOROLA4] S2 54 Si S56 SB st0) $i So % re > > g 8 - one fae OBEN __/f \ a {iN 023-016 > Ay OP3 iy h BERR / \ dh h FALT 4 __ W ef WS <--__ INDIVISIBLE CYCLE > be next CYCLE * For the MC68EC020, A?3-A? ** This signal does not apply ta the MC68ECO20 Figure 5-30. Byte Read-Modify-Write Cycle32-Bit Port (TAS instruction) MOTOROLA M68020 USERS MANUAL 5-44State 0 MC68020- The processor asserts ECS and OCS in SO to indicate the beginning of an external operand cycle. The processor also asserts RMG in SO to identify a read- modify-write cycle. The processor places a valid address on A31A0 and valid function codes on FC2-FCO. The function codes select the address space for the operation. SiZ1, SIZO become valid in SO to indicate the operand size. The processor drives R/AW high for the read cycle. MC68EC020The processor asserts RMC in SO to identify a read-modify-write cycle. The processor places a valid address on A23-A0 and valid function codes on FC2 FCO. The function codes select the address space for the operation. $1Z1-SIZ0 become valid in SO to indicate the operand size. The processor drives R/W high for the read cycle. State 1 MC68020One-half clock later in S1, the processor asserts AS to indicate that the address on the address bus is valid. The processor also asserts DS during $1. In addition, the ECS (and OCS, if asserted) signal is negated during S1. MC68EC020One-half clock later in $1, the processor asserts AS to indicate that the address on the address bus is valid. The processor also asserts DS during $1. State 2 MC68020-During S2, the processor asserts DBEN to enable external data bufters. The selected device uses R/W, SIZ1, SIZO, A1, AO, and DS to place information on the data bus. Any or all of the bytes (031-024, D23-D16, D15-D8, and 07~-D0} are selected by SIZ1, SIZO, A1, and AO. Concurrently, the selected device may assert the DSACK1/DSACKO signals. MC68EC020During S2, the selected device uses R/W, SIZ1, SIZO, A1, AO. and DS to place information on the data bus. Any or all of the bytes (031-D24, D23-D16, D15- D8, and D7D0) are selected by SIZ1, StZO, Ai, and AQ. Concurrently, the selected device may assert the DSACK1/DSACKO signals. State 3 MC68020/EC020As long as at least one of the DSACK1/DSACKO signals is reccgnized by the end of S2 (meeting the asynchronous input setup time requirement), data is latched on the next falling edge of the clock, and the cycle terminates. If DSACK1/DSACKO is not recognized by the start of $3, the processor inserts wait states instead of proceeding to S4 and S5. To ensure that wait states are inserted, both DSACKO and DSACK1 must remain negated throughout the asynchronous input setup and hold times around the end of S2. If wait states are added, the processor continues to sample the DSACK1/OSACKO signals on the falling edges of the clock until one is recognized. State 4 MC68020/EC020At the end of S4, the processor latches the incoming data. 5-42 M68020 USERS MANUAL MOTOROLAState 5 MC68020The processor negates AS, DS, and DBEN during S5. tf more than one read cycle is required to read tn the operand(s), SO-S5 are repeated for each read cycle. When the read cycle(s} are complete, the processor holds the address, R/W. and FC2-FCO valid in preparation for the write portion of the cycle. The external device keeps its data and DSACK1/DSACKO signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the dala and negate DSACK1/DSACKO within approximately one clock period after sensing the negation of AS or DS. DSACKT/DSACKO signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation. MC68ECO20The processor negates AS, DS, and DBEN during S5. If more than one read cycle is required to read in the operand(s), SO-S5 are repeated for each read cycle. When the read cycle(s) ts complete, the processor holds the address, R/W, and FC2--FCO vatid in preparation for the write portion of the cycle. The external device keeps its data and DSACK1/DSACKO signals asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove the data and negate DSACK1/DSACKO within approximately one clock period after sensing the negation of AS or DS. DSACK1/DSACKO signals that remain asserted beyond this limit may be prematurely detected for the next portion of the operation. Idle States MC68020/EC020The processor does not assert any new contro! signals during the idle states, but it may internally begin the modify portion of the cycle at this time. S6- 311 are omitted if no write cycle is required. If a write cycle is required, the R/W signal remains in the read mode until S6 to prevent bus conflicts with the preceding read portion of the cycle; the data bus is not driven until S8. State 6 MiC68020The processor asserts ECS and OCS in S6 to indicate that another external cycle is beginning. The processor drives R/W low for a write cycle. Depending on the write operation to be performed, the address lines may change during S6. MC68EC020During S6, the processor drives R/W low for a write cycle. Depending on the write operation to be performed, the address lines may change during S6. State 7 MC68020During $7, the processor asserts AS, indicating that the address on the address bus is valid. The processor also asserts DBEN, which can be used to enable data buffers. tn addition, ECS (and OCS, if asserted) is negated during S7. MC68EC020During S7, the processor asserts AS, indicating that the address on the address bus is valid. State 8 MC68020.EC020During S8. the processor places the data to be written onto the data bus, MOTOROLA M68020 USER'S MANUAL 5-43State 9 MC68020/EC020 The processor asserts DS during S9, indicating that the data on the data bus is stable. As long as at least one of the DSACK1/DSACKO signats is recognized by the end of S8 (meeting the asynchronous input setup time requirement), the cycle terminates one clock later. If DSACK1/DSACKO is not recognized by the start of S9, the processor inserts wait states instead of proceeding to S10 and S11. To ensure that wait states are inserted, both DSACK1 and DSACKO must remain negated throughout the asynchronous input setup and hold times around the end of S8. tf wait states are added, the processor continues to sample DSACK1/DSACKO signals on the falling edges of the clock until one is recognized. The external device uses R/W, DS, SIZ1, SIZO, A1, and AQ to latch data from the appropriate section(s) of the data bus (D31--D24, D23-D16, D15D8, and D7-D0O). S1Z1, SIZ0, Al, and AQ select the data bus sections. If it has not already done so, the device asserts DSACK1/DSACKO when it has successfully stored the data. State 10 5 | MC68020/EC020The processor issues no new control signals during $10. State 11 MC68020/EC020The processor negates AS and DS during S11. It holds the address and data valid during S11 to provide address hold time for memory systems. R/W and FC2--FCO also remain valid throughout $11. if more than one write cycle is required, S6-S11 are repeated for each write cycle. The external device keeps DSACK1/DSACKO asserted until it detects the negation of AS or DS (whichever it detects first). The device must remove its data and negate DSACK1/DSACKO within approximately one clock period after sensing the negation of AS or DS. 5.4 CPU SPACE CYCLES FC2--FCO select user and supervisor program and data areas as listed in Table 2-1. The area selected by FC2-FCO = 111 is classified as the CPU space. The interrupt acknowledge, breakpoint acknowledge, module operations, and coprocessor communication cycles described in the following paragraphs utilize CPU space. The CPU space type is encoded on A19-A16 during a CPU space operation and indicates the function that the processor is performing. On the MC68020/EC020, four of the encodings are implemented as shown in Figure 5-31. All unused values are reserved by Motorola for future use. 5-44 M68020 USERS MANUAL MOTOROLAFUNCTION ADDRESS BUS CODE ; 2 on 24124 20149 16's 54 24 0 BHEAKPOIN I sontmicrce Lt tt] [oe ooo occ 0e asco 0foce 00000000) eel oo | ' ' uM 20119 16115 76 0 ACCESS LEVEL {| | | | | SS LEVEL | 4 1 Cooggd add oO OO Golo aoot!oo OoOGaooOoa! MMU REG I I ky 20119 t645 1342 54 0 COPROCESSOR | | | | Coen T 111 ]{ oo 00 00000000/001 0 CplD coop OOO D8 CP REG l l an 2019 16.15 44 1 0 INTERRUPT acknomeebor L? tt] Ltt ttt tat ttt tf ewe] | CPU SPACE TYPE FIELD Figure 5-31. MC68020/EC020 CPU Space Address Encoding 5.4.1 Interrupt Acknowledge Bus Cycles When a peripheral device signals the processor (with the IPL2-IPLO signals) that the device requires service and when the internally synchronized value on these signals indicates a higher priority than the interrupt mask in the status register (or that a transition has occurred in the case of a level 7 interrupt), the processor makes the interrupt a pending interrupt. Refer to Section 6 Exception Processing for details on the recognition of interrupts. The MC68020/EC020 takes an interrupt exception for a pending interrupt within one instruction boundary (after processing any other pending exception with a higher priority). The following paragraphs describe the various kinds of interrupt acknowledge bus cycles that can be executed as part of interrupt exception processing, 5.4.1.1 INTERRUPT ACKNOWLEDGE CYCLETERMINATED NORMALLY. When the MC68020/EC020 processes an interrupt exception, it performs an interrupt acknowledge cycle to obtain the number of the vector that contains the starting location of the interrupt service routine. Some interrupting devices have programmable vector registers that contain the interrupt vectors for the routines they use. The following paragraphs describe the interrupt acknowledge cycle for these devices. Other interrupting conditions or devices cannot supply a vector number and use the autovector cycle described in 5.4.1.2 Autovector interrupt Acknowledge Cycle. MOTOROLA M68020 USER'S MANUAL 5-45The interrupt acknowledge cycle is a read cycle. It differs from the read cycle described in 5.3.1 Read Cycle in that it accesses the CPU address space. Specifically, the differences are: 1. FC2-FCO are set 111 for CPU address space. 2. A3, A2, and At are set to the interrupt request level (the inverted values of PL2, IPL1, and {PLO, respectively). The CPU space type field (A19-A16) is set to 1111, the interrupt acknowledge code. 4. Other address signais (A31-A20, A15A4, and AO for the MC68020; A23-A20, A15A4, and AO for the MC68EC020) are set to one. The responding device places the vector number on the data bus during the interrupt acknowledge cycle. Beyond this, the cycle is terminated normally with DSACK1/DSACKO. Figure 5-32 is the flowchart of the interrupt acknowledge cycle. Figure 5-33 shows the timing for an interrupt acknowledge cycle terminated with DSACK1/DSACKG. PROCESSOR INTERRUPTING DEVICE ACKNOWLEDGE INTERRUPT <_-_j REQUEST INTERRUPT 1) INTERRUPT PENDING CONDITION (IPEND FOR MC88020) RECOGNIZED BY CURRENT INSTRUC- TION-WAIT FOR INSTRUCTION BOUNDARY. 2} SET RAW TO READ 3) SET FUNCTION CODE TO CPU SPACE 4) PLACE INTERRUPT LEVEL ON Al, A2, AND A3 TYPE FIELD = (ACK 5) SET SIZE TO BYTE #6) NEGATE IPEND 7] ASSERT AS AND OS os PROVIDE VECTOR INFORMATION 1) PLACE VECTOR NUMBER ON LEAST SIGNIFICANT BYTE OF DATA PORT {DEPENDS ON PORT SIZE) 2) ASSERT DSACKI/OSACKO OR ASSERT AVEC FOR AUTOMATIC GENERA- TION OF VECTOR NUMBER ACQUIRE VECTOR NUMBER ail 1} LATCH VECTOR NUMBER 2) NEGATE AS AND OS a RELEASE 1} REMOVE VECTOR NUMBER FROM DATA BUS 2) NEGATE DSACK1/DSACKO | conmiNue INTERRUPT EXCEPTION PROCE ssitic | * This step does nol apply ta the MC6BEGO20 Figure 5-32. Interrupt Acknowledge Cycle Flowchart 5-46 M68020 USER'S MANUAL MOTOROLAow J LILI LI LEU LPL *A31-Ad x / ON AAI x 4 INTERRUPT LEVEL NX XO . FC2-FCo x / sa X . DUM $I20 x / A mo US /~N 7 ~ \ mmm JX 7 * LL 031-D24 ( VECTOR # FROM 8-BIT PORT D23-016 VECTOA s FROM 16-BiT PORT D7-Do ( VECTOR FROM 32-BIT PORT (PLZAL6 \ x dh ** PEND / INTERRUPT x READ CYCLE ele ACKNOWLEDGE > ) Ke d pe __--~___) Ky < Ye A. be | READ CYCLE rd IN * For the MC68ECO20, A23-A20. ** This signal does not apply to the MC68EC020. MOTOROLA BREAKPOINT ACKNOWLEDGE STRUCTION WORD FETCH a FETCHED <- INSTRUCTION EXECUTION Figure 5-36. Breakpoint Acknowledge Cycle Timing M68020 USERS MANUAL 5-5150 S2 Sw Sw Sw S4 50 $2 54 FLELILI LE LU LPL pn A31-A0 FC2+CO $121-S120 = DSACKi DSACKO oe COBEN / ss 031-00 ____ aa Ny BEAR \ / HALT / aepA INTERNAL < READ WITH BERR ASSERTED $$ <5 SE < STACK WRITE For the MCG8EC020, A23-A0 ** This signal does not apply to Ihe MC68ECO20. Figure 5-37. Breakpoint Acknowledge Cycle Timing (Exception Signaled) 5.52 M68020 USERS MANUAL MOTOROLA5.4.3 Coprocessor Communication Cycles The MC68020/EC020 coprocessor interface provides instruction-oriented communication between the processor and as many as eight coprocessors. Coprocessor accesses use the MC6802G6/EC020 bus protocol except that the address bus supplies access information rather than a 32-bit address. The CPU space type field (A19-A16) for a coprocessor operation is 0010. A15-A13 contain the coprocessor identification number {CpID), and A5-A0 specify the coprocessor interface register to be accessed. The memory management unit of an MC68020/EC020 system is always identified by a CpID of zero and has an extended register select field (A7A0) in CPU space 0001 for use by the CALLM and RTM access level checking mechanism. Refer to Section 9 Applications Information for more details. 5.5 BUS EXCEPTION CONTROL CYCLES The MC68020/EC020 bus architecture requires assertion of DSACK1/DSACKO from an external device to signal that a bus cycle is complete. DSACK1/DSACKO or AVEC is not asserted if: * The external device does not respond, No interrupt vector is provided, or Various other application-dependent errors occur. External circuitry can assert BERR when no device responds by asserting DSACK1/DSACKO or AVEC within an appropriate period of time after the processor asserts AS. Assertion of BERR allows the cycle to terminate and the processor to enter exception processing for the error condition. HALT is also used for bus exception control. HALT can be asserted by an external device for debugging purposes to cause single bus cycle operation or can be asserted in combination with BERR to cause a retry of a bus cycle in error. To properly control termination of a bus cycle for a retry or a bus error condition, DSACK1/DSACKO, BERR, and HALT can be asserted and negated with the rising edge of the MC68020/EC020 clock. This procedure ensures that when two signals are asserted simultaneously, the required setup time (#47A) and hold time (#47B) for both of them is met for the same failing edge of the processor clock. (Refer to Section 10 Electrical Characteristics for timing requirements.) This or some equivalent precaution should be designed into the external circuitry that provides these signals. MOTOROLA M68020 USER'S MANUAL 5-53The acceptable bus cycle terminations for asynchronous cycles are summarized in relation to DSACK1/OSACKO assertion as follows (case numbers refer to Table 5-8): Normal Termination: DSACK1/DSACKO is asserted; BERR and HALT remain negated (case 1}. Hait Termination: HALT is asserted at same time or before DSACK1/DSACKO, and BERR remains negated (case 2), Bus Error Termination: BERR is asserted in lieu of, at the same time, or before DSACK1/DSACKO (case 3} or after DSACK1/DSACKO (case 4), and HALT remains negated; BERR is negated at the same time or after DSACK1/DSACKO. Retry Termination: HALT and BERR are asserted in lieu of, at the same time, or before DSACK1/DSACKO (case 5) or after DSACK1/DSACKO (case 6); BERR is negated at the same time or atter DSACK1/DSACKO; HALT may be negated at the same time or after BERA. Table 5-8. DSACK1/BSACKO, BERR, HALT Assertion Results Asserted on Rising Edge of State Case No. Control Signal n n+2 Result 1 BSACKI/DSACKO A s Normal cycle terminate and continue. BERR N N HALT N x 2 DSACKI/DSACKO A Ss Normal cycle terminate and halt. Continue when BERR N N HALT negated. HALT AIS $ 3 DSACKT/DSACKO NiA x Terminate and take bus error exception, possibly BERR A 5 deterred HALT N N 4 DSACKT/DSACKO A x Terminate and take bus error exception, possibly BERR N A deferred HALT N N 5 DSACK 1/DSACKO NIA x Terminate and retry when HALT negated. BERR A s HALT AIS S 6 DSACKT/DSACKS A x Terminate and retry when HALT negated BERA N A HALT N A Legend n The number of current even bus state (e.g $2. S4, etc } A . Signal is asserted in this bus state N Signal is not asserted and/or remains negated in this bus slate X--Don't care S~ Signal was asserted in previous state and remains assested in this stale 5-54 M68020 USER'S MANUAL MOTOROLATable 5-8 lists various combinations of control signal sequences and the resulting bus cycle terminations. To ensure predictable operation, BERR and HALT should be negated according to parameters #28 and #57 in Section 10 Electrical Characteristics. DSACK1/DSACKO, BERR. and HALT may be negated after AS. If DSACK1/DSACKO or BERR remain asserted into S2 of the next bus cycle, that cycle may be terminated prematurely. Example A: A system uses a watchdog timer to terminate accesses to an unpopulated address space. The timer asserts BEAR after timeout (case 3). Example 8: A system uses error detection and correction on RAM contents. The designer may: 1. Delay DSACK1/DSACKO assertion until data is verified and assert BERR and HALT simultaneously to indicate to the processor to automatically retry the error cycle (case 5) or, If data is valid, assert DSACK1/DSACKO (case 1). 2. Delay DSACK1/DSACKO assertion until data is verified and assert BERR with or without DSACK1/DSACKO if data is in error (case 3). This configuration initiates exception processing for software handling of the condition. 3. Assert DSACK1/DSACKO prior to data verification. If data is invalid, BERR is asserted on the next clock cycle (case 4). This configuration initiates exception processing for software handling of the condition. 4. Assert DSACK1/DSACKO prior to data verification; if data is invalid, assert BERR and HALT on the next clock cycle (case 6). The memory controller can then correct the RAM prior to or during the automatic retry. 5.5.1 Bus Errors The BERR signal can be used to abort the bus cycle and the instruction being executed. BERR takes precedence over DSACK1/DSACKO, provided it meets the timing constraints described in Section 10 Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredictable operation of the MC68020/EC020. If BERR remains asserted into the next bus cycte, it may cause incorrect operation of that cycle. When BERR is issued to terminate a bus cycle, the MC6B020/EC020 may enter exception processing immediately following the bus cycle, or it may defer processing the exception. The instruction prefetch mechanism requests instruction words from the bus controller and the instruction cache before it is ready to execute them. If a bus error occurs on an instruction fetch, the processor does not take the exception until it attempts to use that instruction word. Should an intervening instruction cause a branch or should a task switch occur, the bus error exception does not occur. MOTOROLA M68020 USERS MANUAL 5-55BERR is recognized during a bus cycle in any of the following cases: 1. DSACK1/DSACKO and HALT are negated and BERR is asserted. 2. HALT and BERR are negated and DSACK1/DSACKCO is asserted. BERR is then asserted within one clock cycle (HALT remains negated). 3. BERR and HALT are asserted (see 5.5.2 Retry Operation). When the processor recognizes a bus error condition, it terminates the current bus cycle in the normal way. Figure 5-38 shows the timing of a bus error for the case in which DSACK1/DSACKO is not asserted. Figure 5-39 shows the timing for a bus error for the case in which BERR is asserted after DSAGKT/DSACKO. Exceptions are taken in both cases. (Refer to Section 6 Exception Processing for details of bus error exception processing.) When BERR is asserted during a read cycle that supplies an instruction to the on-chip cache, the instruction in the cache is marked invalid. When BERR is asserted after DSACK1/DSACKO, BERR must be asserted within parameter #48 (refer to Section 10 Electrical Characteristics) for purely asynchronous operation, or it must be asserted and remain stable during the Sample window, defined by parameters #27A and #47B, around the next falling edge of the clock after DSACK1/DSACKO is recognized. If BERR is not stable at this time, the processor may exhibit erratic behavior. In this case, data may be present on the bus, but may not be valid. This sequence may be used by systems that have memory error detection and correction logic and by external cache memories. 5.5.2 Retry Operation When BERR and HALT are asserted simultaneously by an external device during a bus cycle, the processor enters the retry sequence. A delayed retry similar to the delayed BERR signal described previously can also occur. The processor terminates the bus cycle, negates the control signals (AS, DS, R/W, SIZ1, $1Z0, RMC, and, for the MC68020 only, ECS and OCS), and does not begin another bus cycle until the BERR and HALT signals have been negated by external logic. After a synchronization delay, the processor retries the previous cycle using the same access information (address, function code, size, etc.) The BERR signal should be negated before S2 of the read cycle to ensure correct operation of the retried cycle. Figure 5-40 shows a late retry operation of a cycle. The processor retries any read or write cycle of a read-modify-write operation separately: RMC remains asserted during the entire retry sequence. Asserting BR along with BERR and HALT provides a relinquish and retry operation. The MC68020/EC020 does not relinquish the bus during a read-modify-write operation. Any device that requires the processor to give up the bus and retry a bus cycle during a read - modify-write cycle must assert BERR and BR only (HALT must not be included). The bus error handler software should examine the read-modify-write bit in the special status word (refer to Section 6 Exception Processing) and take the appropriate action to resolve this type of fault when it occurs. 5-56 M68020 USER'S MANUAL MOTOROLA*AN1-A20 X \ / d T x To TTF7 ( BREAKPOINT ENCODING / Ny AIS-A2 X BREAKPOINT NUMBER k X Mw Al-AD \ , / hy AI -AlG oe, rate YX 7 UTE X sx 7X7. a nai 7 TN ves \_/ \_/ S\_/ ws /\ [NO eT ( /_ [ OSACK1 / \ / \ OSACKO / \ / Ns \ saan ){_} os )__) Co BERR HALT f | BREAKPOINT | EXCEPTION < READ CYCLE 3>;-=& ACKNOWLEDGE >| ' BUS ERROR STACKING FETCH * For the MC68ECO20, AZ3-A20. ** This signa! does nol apply to he MC68EC020 Figure 5-38. Bus Error without DSACK1/DSACKO MOTOROLA M68020 USER'S MANUAL 5-57so 52 Sw Sw 34 50 $2 34 *AdI-AO FC2-FCO 8121-3120 om rs o< Seo eae o< RW X_ x x = BNF so (Y . LS DSACKI / \ / \ DSACKO / \ / N \ * DBEN / \ / \ or > _ ___ Ay iPL2 PLO / BEAR / \ / N _ A. HALT / N Arar INTERNAL /+< WRITE WITH BERR ASSERTED HE STACK WRITE * For the MC68EC020, A23-A0 ** This signal does not apply to the MC6SEC020 Figure 5-39. Late Bus Error with DSACK1/DSAGKO 5-58 68020 USER'S MANUAL MOTOROLACLK *AI1-A0 FC2-+C0 81Z1-SiZo *tOc5 _X _X _X secs ~\S cs \ YS a Bs UNS VS psncrt ff NN \ once ff NS \ << DATA BUS NOT DRIVEN > p31-ba hk BERR HALT / \ / \~- WRITE CYCLE RETRY SIGNALED~2>}<___ HALT le RETRY crciea| * For the MC68EC020, A23-A0. ** This signal does not apply to the MC68E C020 Figure 5-40, Late Retry MOTOROLA M68020 USER'S MANUAL 5-595.5.3 Halt Operation When HALT is asserted and BEAR is not asserted, the MC68020/EC020 halts external bus activity at the next bus cycle boundary. HALT by itself does not terminate a bus cycle. Negating and reasserting HALT in accordance with the correct timing requirements provides a single-step (bus cycle to bus cycle) operation. The HALT signal affects external bus cycles only; thus, a program that resides in the instruction cache and does not require use of the externa! bus may continue executing unatfected by HALT. The single-cycte mode allows the user to proceed through (and debug) external processor operations, one bus cycle at a time. Figure 5-41 shows the timing requirements for a single-cycle operation. Since the occurrence of a bus error while HALT iS asserted causes a retry operation, the user must anticipate retry cycles while debugging in the single-cycle mode. The single-step operation and the software trace Capability allow the system debugger to trace single bus cycles, single instructions, or changes in program flow. These processor capabilities, along with a software debugging package, give complete debugging flexibility. When the processor completes a bus cycle with the HALT signal asserted, the data bus is placed in the high-impedance state, and the bus control signals (AS, DS, and, for the MC68020 only, ECS and OCS) are negated (not placed in the high-impedance state): A31-A0 for the MC68020 or A23-A0 for the MC68EC020, FC2-FCO, SIZ1, S1Z0, and RAW remain in the same state. The halt operation has no effect on bus arbitration (refer to 5.7 Bus Arbitration). When bus arbitration occurs while the MC68020/EC020 is halted, the address and control signals (A31-A0, FC2-FCO, SIZ1, SIZO, RW, AS, DS, and, for the MC68020 only, ECS and OCS) are also placed in the high-impedance state. Once bus mastership is returned to the MC68020/EC020, if HALT is still asserted, A31A0 for the MC68020 or A23-A0 for the MC68EC020, FC2-FCO, $IZ1, SIZO, and R/W are again driven to their previous states. The MC68020/EC020 does not service interrupt requests while it is halted (although the MC68020 may assert the IPEND signal as appropriate). 9.5.4 Double Bus Fault When a bus error or an address error occurs during the exception processing sequence for a previous bus error, a previous address error, Or a reset exception, a doubie bus fault occurs. For example, the processor attempts to stack several words containing information about the state of the machine while processing a bus error exception. If a bus error exception occurs during the stacking operation, the second error is considered a double bus fault. When a double bus fault occurs, the processor halts and asserts HALT. Only an external reset operation can restart a halted processor. However, bus arbitration can still occur (refer to 5.7 Bus Arbitration). A second bus error or address error that occurs after exception processing has completed (during the execution of the exception handler routine or later) does not cause a double bus fault. A bus cycte that is retried does not constitute a bus error or contribute to a double bus fault. The processor continues to retry the same bus cycle as long as the external hardware requests it. 5-60 M68C020 USERS MANUAL MOTOROLACLK *A31-A0 $1Z1-S120 LP LE Lo SLL Le QC DD a a "cs \_/ . \/ os \_/ . \S AS TNF" 68 fF DSACK1 / \ / N [ f Ny DSACKO __ W **DBEN / \ / BERR HALT NS , HALT ao READ Bo (BUS ARBITRATION i PEAMITTED WHILE THE PROCESSOR IS HALTED} For the MCG8ECO20, A23-A0. ** This signal does not apply to the MC68ECO20 Figure 5-41. Halt Operation Timing MOTOROLA M68020 USERS MANUAL READ - 5-615.6 BUS SYNCHRONIZATION The MC68020/EC020 overlaps instruction executionthat is, during bus activity for one instruction, instructions that do not use the external bus can be executed. Due to the independent operation of the on-chip cache retative to the operation of the bus controller, many subsequent instructions can be executed, resulting in Seemingly nonsequential instruction execution. When this is not desired and the system depends on sequential execution following bus activity, the NOP instruction can be used. The NOP instruction forces instruction and bus synchronization by freezing instruction execution until all pending bus cycles have completed. An example of the use of the NOP instruction for this purpose is the case of a write operation of contro! information to an external register in which the external hardware attempts to control program execution based on the data that is written with the conditional assertion of BERR. Since the MC68020/EC020 Cannot process the bus error until the end of the bus cycle, the external hardware has not successfully interrupted program execution. To prevent a subsequent instruction from executing until the external cycle completes, the NOP instruction can be inserted after the instruction Causing the write. In this case, bus error exception processing proceeds immediately after the write and before subsequent instructions are executed. This iS an irregular situation, and the use of the NOP instruction for this purpose is not required by most systems. 5.7 BUS ARBITRATION The bus design of the MC68020/EC020 provides for a single bus master at any one time: either the processor or an external device. One or more of the external devices on the bus can have the capability of becoming bus master. Bus arbitration is the protocol by which an external device becomes bus master; the bus controller in the MC68020/EC020 manages the bus arbitration signals so that the processor has the lowest priority. Bus arbitration differs in the MC68020 and MC68EC020 due to the absence of BGACK in the MC68EC020. Because of this difference, bus arbitration of the MC68020 and MC68EC020 is discussed separately. External devices that need to obtain the bus must assert the bus arbitration signals in the sequences described in 5.7.1 MC68020 Bus Arbitration or 5.7.2 MC68EC020 Bus Arbitration. Systems having several devices that can become bus master require external circuitry to assign priorities to the devices, so that when two or more external devices attempt to become bus master at the same time, the one having the highest priority becomes bus master first. 5-62 M68020 USER'S MANUAL MOTOROLA5.7.1 MC68020 Bus Arbitration The sequence of the MC68020 bus arbitration protocol is as follows: {. An external device asserts the BR signal. 2. The processor asserts the BG signal to indicate that the bus will become available at the end of the current bus cycle. 3. The external device asserts the BGACK signal to indicate that it has assumed bus mastership. BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR; it is usually asserted as soon as BR has been synchronized and recognized, except when the MC68020 has made an internal decision to execute a bus cycle. Then, the assertion of BG is deferred until the bus cycle has begun. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal. When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. The external device asserts BGACK when it assumes bus mastership, and maintains BGACK during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: * The external device must have received BG through the arbitration process. AS must be negated, indicating that no bus cycle is in progress, and the external device must ensure that all appropriate processor signals have been placed in the high-impedance state (by observing specification #7 in Section 10 Electrical Specifications). * The termination signal (DSACK1/DSACKO) for the most recent cycle must have been negated, indicating that external devices are off the bus (optional, refer to 5.7.1.3 Bus Grant Acknowledge (MC68020)). * BGACK must be inactive, indicating that no other bus master has claimed ownership of the bus. Figure 5-42 is a flowchart of MC68020 bus arbitration for a single device. Figure 5-43 is a timing diagram for the same operation. This technique allows processing of bus requests during data transfer cycles. MOTOROLA M68020 USER'S MANUAL 5-63PROCESSOR REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION <___. 1) ASSERT BA t) ASSERT BG ne on ACKNOWLEDGE BUS MASTERSHIP 1) EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TO COMPLETE 4) NEXT BUS MASTER ASSERTS BGACK TO BECOME NEW MASTER 4} BUS MASTER NEGATES BR TERMINATE ARBITRATION 1) NEGATE BG AND WAIT FOR BGACK To BE NEGATED |}... "yet OPERATE AS BUS MASTER 1) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES) Y RELEASE BUS MASTERSHIP RE-ARBITRATE OR RESUME PROCESSOR OPERATION 1) NEGATE BGACK Figure 5-42. MC68020 Bus Arbitration Flowchart for Single Request The timing diagram (see Figure 5-43) shows that BR is negated at the time that BGAGK is asserted. This type of operation applies to a system consisting of the processor and one device capable of bus mastership. In a system having a number of devices capable of bus mastership, the BR line from each device can be wire-ORed to the processor. In such a system, more than one bus request can be asserted simultaneously. The timing diagram in Figure 5-43 shows that BG is negated a few clock cycles after the transition of BGACK. However, if bus requests are still pending after the negation of BG, the processor asserts another BG within a few clock cycies after it was negated. This additional assertion of BG allows external arbitration circuitry to select the next bus master before the current bus master has finished with the bus. The following Paragraphs provide additional information about the three steps in the arbitration process. Bus arbitration requests are recognized during normal processing, RESET assertion, HALT assertion, and when the processor has halted due to a double bus fault. 5-64 M66020 USER'S MANUAL MOTOROLAo Fo LELE LiL LU ULI LIL Le AN-Aa FC2-FCO $1Z1-S1Z0 DSACKI DSACKO DBEN D31-Do _X > _X > f/f NS NS NL Y* se Wi Sf NY NY _/ \_/* <__ , HEFT boss anni BGACK \ PROCESSOA > GMA DEVICE >| ~ PROCESSOR Figure 5-43. MC68020 Bus Arbitration Operation Timing for Single Request MOTOROLA M68020 USERS MANUAL 5-655.7.1.1 BUS REQUEST (MC68020). External devices Capable of becoming bus masters request the bus by asserting BR. BR can be a wire-ORed signal (although it need not be constructed from open-collector devices) that indicates to the processor that some external device requires control of the bus. The processor is at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). If no BGACK is received while BR is asserted, the processor remains bus master once BR is negated. This prevents unnecessary interference with ordinary processing if the arbitration circuitry inadvertently responds to noise or if an external device determines that it no longer requires use of the bus before it has been granted mastership. 5.7.1.2 BUS GRANT (MC68020). The processor asserts BG as soon as possible after receipt of the bus request. BG assertion immediately follows internal synchronization except during a read-modify-write cycle or follows an internal decision to execute a Dus cycle. During a read-modify-write cycle, the processor does not assert BG until the entire operation has completed. RMC is asserted to indicate that the bus is locked. In the case of an internal decision to execute another bus cycle, BG is deferred until the bus cycle has begun. BG may be routed through a daisy-chained network or through a specific priority-encoded network. The processor allows any type of external arbitration that follows the protocol. 5.7.1.3 BUS GRANT ACKNOWLEDGE (MC68020). Upon receiving BG, the requesting device waits until AS, DSACK1/DSACKO, and BGAGK are negated before asserting its own BGACK. The negation of AS indicates that the previous master releases the bus after specification #7 (refer to Section 10 Electrical Characteristics). The negation of DSACK1/DSACKO indicates that the previous slave has completed its cycie with the previous master. Note that in some applications, DSACGK1/DSACKO might not be used in this way. General-purpose devices are connected to be dependent only on AS. When BGACK is asserted, the device is the bus master until it negates BGACK. BGACK should not be negated until all bus cycles required by the alternate bus master have been completed. Bus mastership terminates at the negation of BGACK. The BR from the granted device should be negated after BGACK is asserted. If another BR ig still pending after the assertion of BGACK, another BG is asserted within a few clocks of the negation of the the first BG, as described in 5.7.1.4 Bus Arbitration Control (MC68020). Note that the processor does nol perform any externai bus cycles before it reasserts 8G in this case. 5-66 M68020 USERS MANUAL MOTOROLA5.7.1.4 BUS ARBITRATION CONTROL (MC68020). The bus arbitration contro! unit in the MC68020 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68020 are internally synchronized tn a maximum of two cycles of the processor clock. As shown in Figure 5-44, input signals labeied R and A are internally synchronized versions of the BR and BGACK signals, respectively. The BG output is labeled G, and the internal high-impedance control signal is labeled T. If T is true, the address, data, and contro! buses are placed in the high-impedance state after the next rising edge following the negation of AS and RMC. All signals are shown in positive logic (active high), regardless of their true active voltage level. ABUS REQUEST ABUS GRANT ACKNOWLEDGE GBUS GRANT TTHREE-STATE CONTROL TO BUS CONTROL LOGIC XDONT CARE NOTE: The 8G output will not be asserted while RMC is asserted Figure 5-44. MC68020 Bus Arbitration State Diagram MOTOROLA M68020 USERS MANUAL 5-67State changes occur on the next rising edge of the clock afler the infernal signal is recognized as valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals (controlled by T) are driven by the processor immediately following a state change when bus mastership ts returned to the MC68020. State 0, at the top center of the diagram, in which both G and T are negated, is the state of the bus arbiter while the processor is bus master. Request A and acknowledge A keep the arbiter in state 0 as long as they are both negated. When a request R is received, both grant G and signal T are asserted (in state 1 at the top left). The next clock causes a change to state 2, at the lower left, in which G and T are held. The bus arbiter remains in that state until acknowledge A is asserted or request R is negated. Once either occurs, the arbiter changes to the center state, state 3, and negates grant G. The next clock takes the arbiter to state 4, at the upper right, in which grant G remains negated and signal T remains asserted. With acknowledge A asserted, the arbiter remains in state 4 until A is negated or request R is again asserted. When A is negated, the arbiter returns to the original state, state 0, and negates signal T. This sequence of states follows the narmal sequence of signals for relinquishing the bus to an external bus master. Other states apply to other possible sequences of combinations of R and A. The MC68020 does not allow arbitration of the external bus during the read-modify-write sequence. For the duration of this sequence, the MC68020 ignores the BR input. If mastership of the MC68020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence. The bus arbitration sequence while the bus ts inactive (i.e., executing internal Operations such as a multiply instruction) is shown in Figure 5-45, 5-68 M68020 USER'S MANUAL MOTOROLA34 SO e PLOLOLOLP LLL A31-AQ al FC2-#CO Se al SIZ1-S1ZO AW ECS DSAGKI / DSACKO / DBEN / SN D31-Do BGACK \ f BUS INACTIVE PR (ARBITRATION PERMITTED __+ Ca ALT OCESSOA >< WHILE THE PROCESSOR IS ALTERNATE MASTER PROCESSOR INACTIVE OR HALTED) Figure 5-45. MC68020 Bus Arbitration Operation TimingBus Inactive MOTOROLA M6B020 USER'S MANUAL 5.695.7.2 MC68EC020 Bus Arbitration The sequence of the MC68EC020 bus arbitration protocol is as follows: 1. An external device asserts the BR signal. 2. The processor asserts the BG signal to indicate that the bus will become available at the end of the current bus cycle. 3. The external device asserts the BR signal throughout its bus mastership. BR may be issued any time during a bus cycle or between cycles. BG is asserted in response to BR; it is usually asserted as soon as BR has been synchronized and recognized, except when the MC68020 has made an internal decision to execute a bus cycie. Then, the assertion of BG is deferred untit the bus cycle has begun. Additionally, BG is not asserted until the end of a read-modify-write operation (when RMC is negated) in response to a BR signal. When the requesting device receives BG and more than one external device can be bus master, the requesting device should begin whatever arbitration is required. The external device continues to assert BR when it assumes bus mastership, and maintains BR during the entire bus cycle (or cycles) for which it is bus master. The following conditions must be met for an external device to assume mastership of the bus through the normal bus arbitration procedure: * The external device must have received BG through the arbitration process. AS must be negated, indicating that no bus cycle is in progress, and the external device must ensure that all appropriate processor signals have been placed in the high-impedance state (by observing specification #7 in Section 10 Electrical Specifications). * The termination signal (DSACK1/DSACKO) for the most recent cycle must have been negated, indicating that external devices are off the bus. * No other bus master has claimed ownership of the bus. Figure 5-46 is a flowchart of MC68EC020 bus arbitration for a single device. Figure 5-47 is a timing diagram for the same operation. This technique allows processing of bus requests during data transfer cycles. Bus arbitration requests are recognized during normal processing, RESET assertion, HALT assertion, and when the processor has halted due to a double bus fault. 5-70 M68020 USER'S MANUAL MOTOROLAPROCESSOR REQUESTING DEVICE REQUEST THE BUS GRANT BUS ARBITRATION 1) ASSERT BR 1) ASSERT BG - J J ACKNOWLEOGE BUS MASTERSHIP OPERATE AS BUS MASTER 1} EXTERNAL ARBITRATION DETERMINES NEXT BUS MASTER 2) NEXT BUS MASTER WAITS FOR CURRENT CYCLE TG COMPLETE 3) PERFORM DATA TRANSFERS (READ AND WRITE CYCLES} f RELEASE BUS MASTERSHIP RE-ARBITAATE OR RESUME PROCESSOR OPERATION A 1) NEGATE BR Figure 5-46. MC68EC020 Bus Arbitration Flowchart for Single Request 5.7.2.1 BUS REQUEST (MC68EC020). External devices capable of becoming bus masters request the bus by asserting BR. BR can be a wire-ORed signal (although it need not be constructed from open-collector devices) that indicates to the processor that some external device requires control of the bus. The processor is at a lower bus priority level than the external device and relinquishes the bus after it has completed the current bus cycle (if one has started). BR remains asserted throughout the external devices bus mastership. 5.7.2.2 BUS GRANT (MC68EC020). The processor asserts BG as soon as possible after receipt of the bus request. BG assertion immediately follows internal synchronization except during a read-modify-write cycle or follows an interna! decision to execute a bus cycle. During a read-modify-write cycle, the processor does not assert BG until the entire operation has completed. RMC is asserted to indicate that the bus is locked. In the case of an internal decision to execute another bus cycle, BG is deferred until the bus cycle has begun. BG may be routed through a daisy-chained network or through a specific priority-encoded network. The processor allows any type of external arbitration that follows the protocol. MOTOROLA M68020 USER'S MANUAL 5-71si ro pS p_ Nn SiZ1-SIz0 x s a DSACKT \ / OSACKO \ jf o21-p9 (7) BA \ fo \ BG \ / PROCESSOR >| |< DMA DEVICE > b~< PROCESSOR Figure 5-47. MC68EC020 Bus Arbitration Operation Timing for Single Request 5-72 M68020 USER'S MANUAL MOTOROLA5.7.2.3 BUS ARBITRATION CONTROL (MC68EC020). The bus arbitration control unit in the MC68EC020 is implemented with a finite state machine. As discussed previously, all asynchronous inputs to the MC68EC020 are internally synchronized in a maximum of two cycles of the processor clock. As shown in Figure 5-48, the input signal labeled R is an internally synchronized version of the BR signal. The BG output is labeled G, and the internal high-impedance control signal is labeled T. If T is true, the address, data, and control buses are placed in the high- impedance state after the next rising edge following the negation of AS and RMC. All signals are shown in positive logic (active high), regardless of their true active voltage level. RABUS REQUEST GBUS GRANT TTHREE-STATE CONTROL TO BUS CONTROL LOGIC XDONT CARE Figure 5-48. MC68EC020 Bus Arbitration State Diagram MOTOROLA M68020 USER'S MANUAL 5-73State changes occur on the next rising edge of the clock after the internal signal is recognized as valid. The BG signal transitions on the falling edge of the clock after a state is reached during which G changes. The bus control signals {controled by T) are driven by the processor immediately following a state change when bus mastership is returned to the MC68ECG20. State 0, at the top center of the diagram, in which both G and T are negated, is the state of the bus arbiter while the processor is bus master. Request R keeps the arbiter in state 0 as long as it is negated. When a request R is received, both grant G and signai T are asserted (in state 1 at the top left). The next clock causes a change to state 2, at the lower left, in which G and T are held. The bus arbiter remains in that state until request R is negated. Then the arbiter changes to the center state, state 3, and negates grant G. The next clock takes the arbiter to state 4, at the upper right, in which grant G remains negated and signal T remains asserted. The arbiter returns to the Original state, state 0, and negates signal T. This sequence of states follows the normal sequence of signals for relinquishing the bus to an external bus master. Other states apply to other possible sequences of R. The MC68EC020 does not allow arbitration of the external bus during the read-modify- write sequence. For the duration of this sequence, the MC68EC020 ignores the BR input. If mastership of the MC68EC020 bus is required during a read-modify-write operation, BERR must be used to abort the read-modify-write sequence. The bus arbitration sequence while the bus is inactive (i.e., executing internal operations such as a multiply instruction} is shown in Figure 5-49. 5-74 M68020 USER'S MANUAL MOTOROLAS4 so ea FT LELEPLOLOL La} 4 {_ FC2-FCO > { SI21-SIZ0 > { BA \ / sn ne-yo ti (ARBITRATION PERMITTED ALTERNATE MASTER PROCE WHILE THE PROCESSOR IS PROCESSOR INACTIVE OR HALTED) Bl Figure 5-49. MC68EC020 Bus Arbitration Operation TimingBus inactive The existing three-wire arbitration design (BR, BG, and BGACK) of some peripherals can be converted to the MC68EC020 two-wire arbitration with the addition of an AND gate. Figure 5-50 shows the combination of BR and BGACK for a three-wire arbitration system to BR of the MC68EC020 or BR and BG from an MC68EC020 to BG for a three-wire arbitration system. The speed of the AND gate must be faster than the time between the assertion of BGACK and the negation of BR by the alternate bus master. Figure 5-50 assumes the alternate bus master does not assume bus mastership unti! the MC68EC020 AS is negated and MC68EC020 BG is asserted. MOTOROLA M68020 USER'S MANUAL 5-75An example of MC68ECO20 bus arbitration to a DMA device that supports three-wire bus arbitration is described in Appendix A Interfacing an MC68EC020 to a DMA Device That Supports a Three-Wire Bus Arbitration Protocol. ALTERNATE BUS MASTER MC6BECO20 AS ->_-_1] a5 BG }-___---_-_ a6 BR _. AGACK Figure 5-50. Interface for Three-Wire to Two-Wire Bus Arbitration 5.8 RESET OPERATION RESET is a bidirectional signal with which an external device resets the system or the processor resets external devices. When power is applied to the system, external circuitry should assert RESET for a minimum of 520 clocks after Vcc and clock timing have stabilized and are within specification limits. Figure 5-51 is a timing diagram of the power- up reset operation, showing the relationships between RESET, Vcc, and bus signals. The clock signal is required to be stable by the time Vec reaches the minimum operating specification. During the reset period, the entire bus three-states (except for non-three- statable signals, which are driven to their inactive state). Once RESET negates, all control signals are negated, the data bus is in read mode, and the address bus is driven. After this, the first bus cycle for reset exception processing begins. The external RESET signal resets the processor and the entire system. Except for the initial reset, RESET should be asserted for at least 520 clock periods to ensure that the processor resets. Asserting RESET for 10 clock periods is sufficient for resetting the processor logic, the additional clock periods prevent a RESET instruction from overlapping the external RESET signal. 5-76 M68020 USERS MANUAL MOTOROLASV NG ] Voc 12 520CLOCKS - RESET = < 4 CLOCKS 2m{ [ .. 4 CLOCKS- BUS |e oom CYCLES ENTIRE BUS | ALL CONTROL SIGNALS | ISP THREE- | NEGATED, DATA BUS IN READ STATED READ MODE.AODRESS STARTS XRXXK BUS STATE UNKNOWN 8US DAIVEN Figure 5-51. Initial Reset Operation Timing Resetting the processor causes any bus cycle in Progress to terminate as if DSACK1/DSACKO or BERR had been asserted. In addition, the processor initializes registers appropriately for a reset exception. Exception processing for a reset operation is described in Section 6 Exception Processing. When a RESET instruction is executed, the processor drives the RESET signal for 512 clock cycles, In this case, the processor resets the external devices of the system, and the internal registers of the processor are unaffected. The external devices connected to the RESET signal are reset at the completion of the RESET instruction. An external RESET signal that is asserted to the processor during execution of a RESET instruction must extend beyond the reset period of the instruction by at least eight clock cycles to reset the processor. Figure 5-52 shows the timing information for the RESET instruction. MOTOROLA M68020 USERS MANUAL oT?* 31-00 nN XxX FezFoo nN xX $iz1-SIzo x N x AY ew / ** ECS \ / ** OCS \ f CC OSACKO / \ / ** DBEN / \ / [] N <0 a * For the MC68EC020, AZ3A0. *4 This signal does not apply to the MC68EC020. RESET INTERNA, RESUME NORMAL 512 CLOCKS OPERATION Figure 5-52. RESET Instruction Timing 5-78 M68020 USER'S MANUAL MOTOROLASECTION 6 EXCEPTION PROCESSING Exception processing is defined as the activities performed by the processor in preparing to execute a handler routine for any condition that causes an exception. In particular, exception processing does not include execution of the handler routine itself. An introduction to exception processing, as one of the processing states of the MC68020/EC020, is given in Section 2 Processing States. This section describes exception processing in detail, describing the processing for each type of exception. It describes the return from an exception and bus fault recovery. This section also describes the formats of the exception stack frames. For more detail on protocol violation and coprocessor-related exceptions, refer to Section 7 Coprocessor Interface Description. Also, for more detail on exceptions defined for floating-point coprocessors, refer to MC68881UM/AD, MC68881/MC68882 Floating-Point Coprocessor User's Manual. 6.1 EXCEPTION PROCESSING SEQUENCE Exception processing occurs in four functional steps. However, all individual bus cycles associated with exception processing (vector acquisition, stacking, etc.) are not guaranteed to occur in the order in which they are described in this section. Nonetheless, all addresses and offsets from the stack pointer are guaranteed to be as described. The first step of exception processing involves the SR. The processor makes an internal copy of the SR, then sets the S-bit in the SR, changing to the supervisor privilege level. Next, the processor inhibits tracing of the exception handler by clearing the T1 and TO bits in the SR. For the reset and interrupt exceptions, the processor also updates the interrupt priority mask (bits 10-8 of the SR). In the second step, the processor determines the vector number of the exception. For interrupts, the processor performs an interrupt acknowledge cycle (a read from the CPU address space type 1111; see Figures 5-32 and 5-33) to obtain the vector number. For coprocessor-detected exceptions, the vector number is included in the coprocessor exception primitive response. (Refer to Section 7 Coprocessor Interface Description for a complete discussion of coprocessor exceptions.) For all other exceptions, internal logic provides the vector number. This vector number is used in the last step to calculate the address of the exception vector. Throughout this section, vector numbers are given in decimal notation. MOTOROLA M68020 USER'S MANUAL 6-1For all exceptions other than reset, the third step is to save the current processor context. The processor creates an exception stack frame on the active supervisor stack and fills it with context information appropriate for the type of exception. Other information may also be stacked, depending on which exception is being processed and the state of the processor prior to the exception. If the exception is an interrupt and the M-bit in the SR is set, the processor clears the M-bit and builds a second stack frame on the interrupt stack. The last step initiates execution of the exception handler. The processor multiplies the vector number by four to determine the exception vector offset. The processor then adds the offset to the value stored in the VBR to obtain the memory address of the exception vector. Next, the processor loads the PC (and the !SP for the reset exception) from the exception vector table in memory. After prefetching the first three words to fill the instruction pipe, the processor resumes normal processing at the address in the PC. Table 6-1 contains a description of all the exception vector offsets defined for the MC68020/EC020. As shown in Table 6-1, the first 64 vectors are defined by Motorola, and 192 vectors are reserved for interrupt vectors defined by the user. However, external devices may use vectors reserved for internal purposes at the discretion of the system designer. 6-2 M68020 USERS MANUAL MOTOROLATable 6-1. Exception Vector Assignments Vector Otfset Vector Number Hex Space Assignment 0 000 SP Reset Initial Interrupt Stack Pointer 1 004 SP Reset Initial Program Counter 2 008 sD Bus Error 3 ooc SB Address Error 4 010 SD lltegal Instruction 5 O14 SD zero Divide 6 018 sD CHK, CHK@2 Instruction 7 o1G 3D cpTRAPeco, TRAPco, TRAPY Instructions 3 020 SD Prividege Violation 9 024 SD Trace 10 028 SD Line 1010 Emulator 11 02C SD Line 1111 Emulator 12 030 SD (Unassigned, Reserved} 13 034 so Coprocessor Protocol Violation 14 038 SD Format Error 15 03C sD Uninitialized Interrupt 16-23 040 SD Unassigned, Reserved O5C SD 24 060 $D Spuriaus Interrupt 25 064 SD Level 1 Interrupt Autovector 26 068 SD Level 2 interrupt Autovector 27 o6C $D Level 3 Interrupt Autovector 28 070 SD Level 4 Interrupt Autovector 2g 074 sD Level 5 Interrupt Autovector 30 078 $D Level 6 interrupt Autovector 31 o7C SD Level 7 Interrupt Autovector 32-47 080 SD TRAP #0-15 instruction Vectors oBC 5D 48 oco sD FPCP Branch or Set on Unordered Condition 49 0c4 sD FPCP Inexact Result 50 0cs SD FPCP Divide by Zero 51 oce $B FPCP Underflow 52 0D0 50 FPCP Operand Error 53 oD4 sD FPCP Overflow 54 ops $b FPCP Signaling NAN 55 obc SD Unassigned, Reserved 56 OE $D PMMU Configuration 57 0E4 $D PMMU Illegal Operation 58 OE8 SD PMMU Access Level Violation 59-63 OEC sb Unassigned, Reserved OFC SD 64-255 100 SD User-Defined Vectors (192) 3FC SD SP---Supervisor Pragram Space SOSupervisor Data Space MOTOROLA M68020 USERS MANUAL 6-36.1.1 Reset Exception Assertion of the RESET signal by external hardware causes a reset exception. For details on the requirements for the assertion of RESET, refer to Section 5 Bus Operation. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. When a reset exception is recognized, it aborts any processing in progress and that processing cannot be recovered. Figure 6-1 is a flowchart of the reset exception, which performs the following operations: 1. Clears the T1 and TO bits in the SR to disable tracing. 2. Places the processor in the interrupt mode of the supervisor privilege level by setting the S-bit and clearing the M-bit in the SR. Sets the 12-10 bits in the SR to the highest priority level (level 7). Initializes the VBR to zero ($00000000). Clears the E and F bits in the CACR. Invalidates all entries in the instruction cache. NO nf w Generates a vector number to reference the reset exception vector (two long words) at offset zero in the supervisor program address space. Loads the first long word of the reset exception vector into the interrupt stack pointer. 9. Loads the second long word of the reset exception vector into the PC. After the initial instruction prefetches, program execution begins at the address in the PC. The reset exception does nat save the value of either the PC or the SR. As described in Section 5 Bus Operation, if a bus error or address error occurs during the exception processing sequence for a reset, a double bus fault occurs. The processor halts and asserts the HALT signal to indicate the halted condition, Execution of the RESET instruction does not cause a reset exception, nor does it affect any internal registers, but it does cause the MC68020/EC020 to assert the RESET signal, resetting all external devices. 6.1.2 Bus Error Exception A bus error exception occurs when external logic aborts a bus cycle by asserting the BERR signal. If the aborted bus cycle is a data access, the processor immediately begins exception processing. If the aborted bus cycle is an instruction prefetch, the processor may delay taking the exception until it attempts to use the prefetched information. 6-4 M68020 USERS MANUAL MOTOROLA4 $00000000 CACR 4 $00000000 INSTRUCTION CACHE ENTRIES INVALIDATED FETCH VECTOR #0 OTHERWISE SP (VECTOR #0) BUS ERROR FETCH VECTOR #1 (DOUBLE BUS FAULT) OTHERWISE PC 4 {VECTOR #1) BUS ERROR PREFETCH 3 WORDS (DOUBLE BUS FAULT) Pr OTHERWISE BUS ERROR OR BEGIN INSTRUCTION ADDRESS ERROR EXECUTION {DOUBLE BUS FAULT} EXIT iy Figure 6-1. Reset Operation Flowchart The processor begins exception processing for a bus error by making an internal copy of the current SR. The processor then enters the supervisor privilege level (by setting the S- bit in the SR) and clears the T1 and TO bits in the SR. The processor generates exception vector number 2 for the bus error vector, It saves the vector offset, PC, and the internal copy of the SR on the active supervisor stack. The saved PC value is the logicai address of the instruction that was executing at the time the fault was detected. This is not necessarily the instruction that initiated the bus cycle since the processor overlaps MOTOROLA M68020 USER'S MANUAL 6-5execution of instructions. The processor also saves the contents of some of its internal registers. The information saved on the stack is sufficient to identify the cause of the bus fault and recover from the error. For efficiency, the MC68020/EC020 uses two different bus error stack frame formats. When the bus error exception is taken at an instruction boundary, less information is required to recover from the error, and the processor builds the short bus fault stack frame as shown in Table 6-5. When the exception is taken during the execution of an instruction, the processor must save its entire state for recovery and uses the long bus fault stack frame shown in Table 6-5. The format code in the stack frame distinguishes the two stack frame formats. Stack frame formats are described in detail in 6.4 Exception Stack Frame Formats. lf a bus error occurs during the exception processing for a bus error, address error, or reset or while the processor is loading internal state information from the stack during the execution of an RTE instruction, a double bus fault occurs and the processor enters the halted state. In this case, the processor does not attempt to alter the current state of memory. Only an external RESET can restart a processor halted by a double bus fault. 6.1.3 Address Error Exception An address error exception occurs when the processor attempts to prefetch an instruction from an odd address. This exception is similar to a bus error exception but is internally initiated. A bus cycle is not executed, and the processor begins exception processing immediately. After exception processing commences, the sequence is the same as that for bus error exceptions described in the preceding paragraphs, except that the vector number is 3 and the vector offset in the stack frame refers to the address error vector. Either a short or long bus fault stack frame may be generated. !f an address error occurs during the exception processing for a bus error, address error, or reset, a double bus fault occurs. 6.1.4 Instruction Trap Exception Certain instructions are used to explicitly cause trap exceptions. The TRAP instruction always forces an exception and is useful for implementing system calls in user programs. The TRAPcc, TRAPYV, cpTRAPcc, CHK, and CHK? instructions force exceptions if the user program detects an error, which may be an arithmetic overflow or a subscript value that is out of bounds. The DIVS and DIVU instructions force exceptions if a division Operation is attempted with a divisor of zero. When a trap exception occurs, the processor copies the SR internally, enters the supervisor privilege level (by setting the S-bit in the SR), and clears the T1 and TO bits in the SR. If tracing is enabled for the instruction that caused the trap, a trace exception is taken after the RTE instruction from the trap handler is executed, and the trace corresponds to the trap instruction; the trap handler routine is not traced. The processor generates a vector number according to the instruction being executed: for the TRAP 6-6 M68020 USER'S MANUAL MOTOROLAinstruction, the vector number is 32 plus n. The stack frame saves the trap vector offset, the PC, and the internal copy of the SR on the supervisor stack. The saved value of the PC is the logical address of the instruction following the instruction that caused the trap. For all instruction traps other than TRAP, a pointer to the instruction that caused the trap is also saved. Instruction execution resumes at the address in the exception vector after the required instruction prefetches. 6.1.5 Illegal Instruction and Unimplemented Instruction Exceptions An illegal instruction is an instruction that contains any bit pattern in its first word that does not correspond to the bit pattern of the first word of a valid MC68020/EC020 instruction or a MOVEC instruction with an undefined register specification field in the first extension word. An illegal instruction exception corresponds to vector number 4 and occurs when the processor attempts to execute an illegal instruction. An illegal instruction exception is also taken if a breakpoint acknowledge bus cycle (see Section 5 Bus Operation) is terminated with the assertion of the BEAR signal, This implies that the external circuitry did not supply an instruction word to replace the BKPT instruction word in the instruction pipe. Instruction word patterns with bits 15-12 = 1010 are referred to as unimplemented instructions with A-line opcodes. When the processor attempts to execute an unimplemented instruction with an A-line opcode, an exception is generated with vector number 10. permitting efficient emulation of unimplemented instructions. Instructions that have word patterns with bits 15-12 = 1111, bits 11-9 = 000, and defined word patterns for subsequent words, are legal PMMU instructions. Instructions that have dits 15-12 of the first words = 1111, bits 11-9 = 000, and undefined patterns in the subsequent words, are treated as unimplemented instructions with F-line opcodes when execution is attempted in the supervisor privilege level. When execution of the same instruction is attempted in the user privilege level, a privilege violation exception is taken. The exception vector number for an unimplemented instruction with an E-line opcode is 11. The word patterns with bits 15-12 = 1111 and bits 11-9 000 are used for coprocessor instructions. When the processor identifies a coprocessor instruction, it runs a bus cycle referencing CPU space type $2 (refer to Section 2 Processing States) and addressing one of eight coprocessors (0-7, according to bits 11-9). If the addressed coprocessor is not included in the system and the cycle terminates with the assertion of BERR, the instruction takes an unimplemented instruction (F-line opcode) exception. The system can emulate the functions of the coprocessor with an F-line exception handler. Refer to Section 7 Coprocessor Interface Description for more details. MOTOROLA M68020 USER'S MANUAL 6-7Exception processing for illegal and unimplemented instructions is similar to that for instruction traps. When the processor has identified an illegal or unimplemented instruction, it inittates exception processing instead of attempting to execute the instruction. The processor copies the SR, enters the supervisor privilege level (by setting the S bit in the SR), and clears the T1 and TO bits in the SR, disabling further tracing. The processor generates the vector number, either 4, 10, or 11, according to the exception type. The iflegal or unimplemented instruction vector offset, current PC, and copy of the SR are saved on the supervisor stack, with the saved value of the PC being the address of the illegal or unimplemented instruction. Instruction execution resumes at the address contained in the exception vector. It is the responsibility of the handling routine to adjust the stacked PC if the instruction is emulated in software or is to be skipped on return from the handler. 6.1.6 Privilege Violation Exception To provide system security, the following instructions are privileged: ANDI ta SR EORI to SR cpRESTORE CpSAVE MOVE from SR MOVE to SR MOVE USP MOVEC MOVES ORI to SR RESET RTE STOP An attempt to execute one of the privileged instructions while at the user privilege level Causes a priviege violation exception. Also, a privilege violation exception occurs if a coprocessor requests a privilege check and the processor is at the user level. Exception processing for privilege violations is similar to that for illegal instructions. When the processor identifies a privilege violation, it begins exception processing before executing the instruction. The processor copies the SR, enters the supervisor privilege level by setting the S-bit in the SR, and clears the T1 and TO bits in the SR. The processor generates vector number 8, the privilege violation exception vector, and saves the privilege violation vector offset, the current PC value, and the internal copy of the SR on the supervisor stack. The saved value of the PC is the logical address of the first word of the instruction that caused the privilege violation. Instruction execution resumes after the required prefetches from the address in the privilege violation exception vector. 6-8 M68020 USERS MANUAL MOTOROLA6.1.7 Trace Exception To aid in program development, the M68000 processors include an instruction-by- instruction tracing capability. The MC68020/ECO20 can be programmed to trace all instructions or only instructions that change program flow. In the trace mode, an instruction generates a trace exception after it completes execution, allowing a debugger program to monitor execution of a program. The T1 and TO bits in the supervisor portion of the SR control tracing. The state of these bits when an instruction begins execution determines whether the instruction generates a trace exception after the instruction completes. Clearing both the T1 and TO bits disables tracing, and instruction execution proceeds normally. Clearing the T1 bit and setting the TO bit causes an instruction that forces a change of flow to take a trace exception. Instructions that increment the PC normally do not take the trace exception. Instructions that are traced in this mode include all branches, jumps, instruction traps, returns, and coprocessor instructions that modify the PC flow. This mode also includes SR manipulations because the processor must re-prefetch instruction words to fill the pipe again any time an instruction that can modify the SR is executed. The execution of the BKPT instruction causes a change of flow if the opcode replacing the BKPT is an instruction that causes a change of flow (i.e., a jump, branch, etc.). Setting the T1 bit and clearing the TO bit causes the execution of all instructions to force trace exceptions. Table 6-2 shows the trace mode selected by each combination of T1 and TO. Table 6-2. Tracing Control Ti TO Tracing Function 0 Q | No Tracing 0 1 Trace on Change of Fiow (BRA, JMP, etc.) 1 0 Trace on Instruction Execution (Any Instruction) 1 1 Undefined, Reserved In general terms, a trace exception is an extension to the function of any traced instructioni.e., the execution of a traced instruction is not complete until completion of trace exception processing. If an instruction does not complete due to a bus error or address error exception, trace exception processing is deferred until after the execution of the suspended instruction is resumed, and the instruction execution completes normally. If an interrupt is pending at the comptetion of an instruction, the trace exception processing occurs before the interrupt exception Processing starts. If an instruction forces an exception as part of its normal execution, the forced exception processing occurs before the trace exception is processed. See 6.1.11 Multiple Exceptions for a more complete discussion of exception priorities. When tracing is enabled and the processor attempts to execute an illegal or unimplemented instruction, that instruction does not cause a trace exception since it is not executed. This is of particular importance to an instruction emulation routine that performs the instruction function, adjusts the stacked PC to skip the untmplemented instruction, and returns. Before returning, the T1 and TO bits of the SR on the stack should be checked. If MOTOROLA M68020 USERS MANUAL 6-9tracing is enabled, the trace exception processing should also be emulated for the trace exception handler to account for the emulated instruction. The exception processing for a trace starts at the end of normal processing for the traced instruction and before the start of the next instruction. The processor makes an internal copy of the SR and enters the supervisor privilege level (by setting the S-bit in the SA). It also clears the T0 and 71 bits of the SR, disabling further tracing. The processor supplies vector number 9 for the trace exception and saves the trace exception vector offset, PC value, and the copy of the SR on the supervisor stack. The saved value of the PC is the logical address of the next instruction to be executed. Instruction execution resumes after the required prefetches from the address in the trace exception vector. The STOP instruction does not perform its function when it is traced. A STOP instruction that begins execution with T1, TO = 10 forces a trace exception after it loads the SR. Upon return from the trace handler routine, execution continues with the instruction following the STOP instruction, and the processor never enters the stopped condition. 6.1.8 Format Error Exception Just as the processor checks that prefetched instructions are valid, the processor (with the aid of a coprocessor, if needed) also performs some checks of data values for control operations, including the type and option fields of the descriptor for CALLM, the coprocessor state frame format word for a cpRESTORE instruction, and the stack frame format for an RTE or an ATM instruction. The RTE instruction checks the validity of the stack format code. For long bus fault format frames, the RTE instruction also compares the internal version number of the processor to that contained in the frame at memory location SP + 54 (SP + $36). This check ensures that the processor can correctly interpret internal state information from the stack frame. The CALLM and RTM both check the values in the option and type fields in the module descriptor and module stack frame, respectively. If these fields do not contain proper values or if an illegal access rights change request is detected by an external memory management unit, then an illegal call or return is being requested and is not executed. Refer to Section 9 Applications Information for more information on the module call/return mechanism. The cpRESTORE instruction passes the format word of the coprocessor state frame to the coprocessor for validation. { the coprocessor does not recognize the format value, it signals the MC68020/EC020 to take a format error exception. Refer to Section 7 Coprocessor interface Description for details of coprocessor-related exceptions. If any of the checks previously described determine that the format of the stacked data is improper, the instruction generates a format error exception. This exception saves a short bus fault stack frame, generates exception vector number 14, and continues execution at the address in the format exception vector. The stacked PC value is the logical address of the instruction that detected the format error. 6-10 M68020 USERS MANUAL MOTOROLA6.1.9 Interrupt Exceptions When a peripheral device requires the services of the MC68020/EC020 or is ready to send information that the processor requires, it may signal the processor to take an interrupt exception. The interrupt exception transfers control to a routine that responds appropriately, The periphera! device uses the IPL2IPLO signals to signal an interrupt condition to the processor and to specify the priority of that condition. These three signals encode a value of zero through seven (IPLO is the least significant bit). When IPL2-IPLO are all negated, the interrupt request level is zero. IPL2-IPLO values t-7 specify one of seven fevels of prioritized interrupts; level 7 has the highest priority. External circuitry can chain or otherwise merge signals from devices at each level, allowing an unlimited number of devices to interrupt the processor. The IPL2-IPLO signals must maintain the interrupt request level until the MC68020/EC020 acknowledges the interrupt to guarantee that the interrupt is recognized. The MC68020/EC020 continuously samples the IPL2-IPLO signals on consecutive falling edges of the processor clock to synchronize and debounce these signals. An interrupt request that is the same for two consecutive falling clock edges is considered a valid input. Although the protocol requires that the request remain until the processor runs an interrupt acknowledge cycle for that interrupt value, an interrupt request that is held for as short a period as two clock cycles could be recognized. The |2-10 bits in the SR specify the interrupt priority mask. The value in the interrupt mask is the highest priority level that the processor ignores. When an interrupt request has a priority higher than the value in the mask, the processor makes the request a pending interrupt. Figure 6-2 is a flowchart of the procedure for making an interrupt pending. When several devices are connected to the same interrupt level, each device should hold its interrupt priority level constant until its corresponding interrupt acknowledge cycle to ensure that all requests are processed. Tabie 6-3 lists the interrupt levels, the states of IPL2-IPLO that define each level, and the mask value that aflows an interrupt at each level. MOTOROLA M68020 USER'S MANUAL 6-116.1.9 Interrupt Excepti When a peripheral device send information that the interrupt exception. The in appropriately, The peripheral device uses processor and to specify th. of zero through seven (IPL the interrupt request level i prioritized interrupts; level otherwise merge signals fi devices to interrupt the proc The IPL2IPLO signals mus acknowledges the interr MC68020/EC020 continuc edges of the processor clc request that is the same fi input. Although the protaco interrupt acknowledge cycle short a period as two clock: The f2--I0 bits in the SR spe is the highest priority level priority higher than the vai interrupt. Figure 6-2 is a flov Wiheg. several deve SES.( RESET } 5 SAMPLE AND SYNCH (PL2-IPLO ~ (COMPARE INTERRUPT LEVEL WITH STATUS REGISTER MASK} OTHERWISE INTERRUPT LEVEL > 12-40, OR TRANSITION ON LEVEL 7 INTERRUPT PENDING (MC68020 ASSERTS (PEND *) | (PEND is not implemented in the MC6BECO20. Figure 6-2. Interrupt Pending Procedure Table 6-3. Interrupt Levels and Mask Values Control Line Status Requested Interrupt Mask Value Interrupt Levet IPL? IPLT IPLO Required for Recognition o* N N N NIA* 1 N N A 0 2 N A N 10 3 N A A 2-0 4 A Ni N 3-0 5 A N A 4-0 6 A A N 5-0 7 A A A 70 *indicales tha! no interrupt is requested. A Asserted N---Negated Priority level 7, the nonmaskable interrupt, is a special case, Level 7 interrupts cannot be masked by the interrupt priority mask, and they are transition sensitive. The processor recognizes an interrupt request each time the external interrupt request level changes from some lower level to level 7, regardless of the value in the mask. Figure 6-3 shows two examples of interrupt recognitions, one for level 6 and one for level 7. When the MC68020/EC020 processes a level 6 interrupt, the interrupt priority mask is automatically updated with a value of 6 before entering the handler routine so that subsequent level 6 interrupts are masked. Provided no instruction that lowers the mask value is executed, the external request can be lowered to level 3 and then raised back to level 6, and a second 6-12 M68020 USER'S MANUAL MOTOROLAlevel 6 interrupt is not processed. However, if the MC68020/EC020 is handling a level 7 interrupt (12-I0 in the SR set to 111) and the external request is lowered to level 3 and then raised back to level 7, a second level 7 interrupt is processed. The second level 7 interrupt is processed because the level 7 interrupt is transition sensitive. A level 7 interrupt is also generated by a level comparison if the request level and mask level are at 7 and the priority mask is then set to a lower level (with the MOVE to SR or RTE instruction, for example). As shown in Figure 6-3 for leve! 6 interrupt request level and mask level, this is the case for all interrupt levels. Note that a mask value of 6 and a mask value of 7 both inhibit request levels of 1-6 from being recognized. In addition, neither masks a transition to an interrupt request level of 7. The only difference between mask values of 6 and 7 occurs when the interrupt request level is 7 and the mask value is 7. lf the mask value is lowered to 6, a second level 7 interrupt is recognized. EXTERNAL iPL2-IPLO INTERRUPT PRIORITY MASK (I2-I IN SR} ACTION LEVEL 6 EXAMPLE | 100 ($3) 401 ($5) INITIAL CONDITIONS Y | IF 001 ($6) THEN 110 ($6) AND LEVEL 6 INTERRUPT (LEVEL COMPARISON) [ IF 100 ($3) AND STILL 410 ($6} THEN -NO ACTION | Y Zz iF 001 ($6) AND STILL 110 ($6) THEN = NO ACTION Y IF STILL 001 ($6) ANDATESO THAT 104 ($5) THEN LEVEL 6INTERAUPT | {LEVEL COMPARISON} LEVEL 7 EXAMPLE f 100 ($3) 101 ($5) | INITIAL CONDITIONS Y IF 000 ($7) THEN 141487) AND LEVEL 7 INTERRUPT | {TRANSITION} Y IF 100 ($3) AND STILL 111 ($7) THEN NO ACTION Y IF 000 ($7) AND STILL 111 ($7) THEN NO ACTION | (TRANSITION) y IF STILL 900 {$7} AND RIESOTHAT = 191 ($5) THEN LEVEL 7 INTERRUPT {LEVEL COMPARISON) Figure 6-3. Interrupt Recognition Examples MOTOROLA M68020 USER'S MANUAL 8-13The MC68020 asserts IPEND (note that iPEND is not implemented in the MC68EC020) when it makes an interrupt request pending. Figure 6-4 shows the assertion of PEND relative to the assertion of an interrupt level on IPL2-IPLO. IPEND signals to external devices that an interrupt exception will be taken at an upcoming instruction boundary (following any higher priority exception). The state of the [PEND signal is internally checked by the processor once per instruction, independently of bus operation. In addition, it is checked during the second instruction prefetch associated with exception processing. Figure 6-5 is a flowchart of the interrupt recognition and associated exception processing sequence. ~ TLL. IPL24PL6 RECOGNIZED ~ + ASSERT IPEND TPL2-IPLO SYNCHRONIZED >| COMPARE REQUEST WITH MASK IN SRO < Figure 6-4. Assertion of IPEND (MC68020 Only) 6-14 M68020 USERS MANUAL MOTOROLAONCE PER INSTRUCTION () ATINSTRUCTION BOUNDARY OTHERWISE EXIT *IPEND ASSERTED * NEGATE IPEND EXECUTE INTERRUPT ACKNOWLEDGE CYCLE TEMP # SR $41 Ti,To4@ 9 UPDATE 120 - (SP) 4 TEMP ~ (SP) 4 PC - isp FORMAT WORD - (SP) 4 OTHER EXCEPTION DEPENDENT INFORMATION THESE INDIVIDUAL BUS CYCLES MAY OCCUR M=1 IN ANY ORDER M=0 PC 4 VECTOR TABLE ENTRY TEMP 4 SA Mo PREFETCH 4 WORDS SEGIN EXECUTION OF THE INTERRUPT Eee TE INTERRUPT N } HANDLER ROUTINE OR PROCESS A ( ) HIGHER PRIORITY EXCEPTION * Does not apply to the MC68ECO020 Figure 6-5. Interrupt Exception Processing Flowchart MOTOROLA M68020 USERS MANUAL 6-15For the MC68020, if no higher priority interrupt has been synchronized, the IPEND signal is negated during state 0 (SO) of an interrupt acknowledge cycle, and the (PL2-iPLOo signals for the interrupt being acknowledged can be negated at this time. For the MC6BEC020, if no higher priority interrupt has been synchronized, the IPL2-IPLO signais for the interrupt being acknowledged can be negated at this time. Refer to Section 5 Bus Operation {for more information on interrupt acknowledge cycles. When processing an interrupt exception, the MC68020/EC020 first makes an internal copy of the SR, sets the privilege level to supervisor, suppresses tracing, and sets the processor interrupt mask level to the level of the interrupt being serviced. The processor attempts to obtain a vector number from the interrupting device using an interrupt acknowledge bus cycie with the interrupt level number output on pins A3Ai of the address bus. For a device that cannot supply an interrupt vector, the AVEC signal can be asserted, and the MC68020/EC020 uses an internally generated autovector, which is one of vector numbers 31-25, that corresponds to the interrupt level number. If external logic indicates a bus error during the interrupt acknowledge cycle, the interrupt is considered Spurious, and the processor generates the spurious interrupt vector number (24). Refer to Section 5 Bus Operation for complete interrupt bus cycle information. Once the vector number is obtained, the processor saves the exception vector offset, PC value, and the internal copy of the SR on the active supervisor stack. The saved value of the PC is the logical address of the instruction that would have been executed had the interrupt not occurred. If the interrupt was acknowledged during the execution of a coprocessor instruction, further internal information is saved on the stack so that the MC68020/EC020 can continue executing the coprocessor instruction when the interrupt handler completes execution. if the M-bit in the SR is set, the processor clears the M-bit and creates a throwaway exception stack frame on top of the interrupt stack as part of interrupt exception processing. This second frame contains the same PC value and vector offset as the frame created on top of the master stack, but has a format number of 1 instead of 0 or 9. The copy of the SR saved on the throwaway frame is exactly the same as that placed on the master stack except that the S-bit is set in the version placed on the interrupt stack. (It may or may not be set in the copy saved on the master stack.) The resulting SR (after exception processing) has the S-bit set and the M-bit cleared. The processor loads the address in the exception vector into the PC. and normal instruction execution resumes after the required prefetches for the interrupt handler routine. Most M68000 family peripherals use programmable interrupt vector numbers as part of the interrupt request/acknowledge mechanism of the system. If this vector number is not initialized after reset and the peripheral must acknowledge an interrupt request, the peripheral usually returns the uninitialized interrupt vector number (15). 6-16 M68020 USER'S MANUAL MOTOROLA6.1.10 Breakpoint Instruction Exception To use the MC68020/EC020 in a hardware emulator, it must provide a means of inserting breakpoints in the emulator code and of performing appropriate operations at each breakpoint. For the MC68000 and MC68008, this can be done by inserting an illegal instruction at the breakpoint and detecting the illegal instruction exception from its vector location. However, since the VBR on M68000 family processors MC68010 and later allows arbitrary relocation of exception vectors, the exception address cannot reliably identify a breakpoint. The MC68020/EC020 processor provides a breakpoint capability with a set of breakpoint instructions, $4848-$484F, for eight unique breakpoints. The breakpoint facility also allows external hardware to monitor the execution of a program residing in the on-chip instruction cache without severe performance degradation. When the MC68020/EC020 executes a breakpoint instruction, it performs a breakpoint acknowledge cycle (read cycle) from CPU space type $0 with address lines A4-A2 corresponding to the breakpoint number. Refer to Section 5 Bus Operation for a description of the breakpoint acknowledge cycle. The external hardware can return either BERR or DSACK1/DSACKO with an instruction word on the data bus. !f the bus cycle terminates with BERR, the processor performs iflegal instruction exception processing. If the bus cycle terminates with DSACK1/DSACKO, the processor uses the data returned to replace the breakpoint instruction in the internal instruction pipe and begins execution of that instruction. The remainder of the pipe remains unaltered. In addition, no stacking or vector fetching is involved with the execution of the instruction. Figure 6-6 is a flowchart of the breakpoint instruction execution. 6.1.11 Multiple Exceptions When several exceptions occur simultaneously, they are processed according to a fixed priority. Table 6-4 lists the exceptions grouped by characteristics. Each group has a priority from 4O. Priority 0 has the highest priority. As soon as the MC68020/EC020 has completed exception processing for a condition when another exception is pending, it begins exception processing for the pending exception instead of executing the exception handier for the original exception condition. Also, whenever a bus error or address error occurs, its exception processing takes precedence over lower priority exceptions and occurs immediately. For example, if a bus error occurs during the exception processing for a trace condition, the system processes the bus error and executes its handier before completing the trace exception processing. However, most exceptions cannot occur during exception processing, and very few combinations of the exceptions shown in Table 6-4 can be pending simultaneously. MOTOROLA M68020 USERS MANUAL 6-17( ENTRY ) AIS-A16 4 $0 A4-A2 BREAKPOINT NUMBEA INITIATE READ BUS CYCLE CYCLE TERMINATED WITH DSACK1/DSACKO PIPE STAGE D # INSTRUCTICN WORD ON DATA BUS EXECUTE INSTRUCTION WORD EXIT CYCLE TERMINATED WITH BEAR TAKE ILLEGAL INSTRUCTION EXCEPTION Figure 6-6. Breakpoint Instruction Flowchart Table 6-4. Exception Priority Groups Group/ Priority Exception and Relative Priority Characteristic 0 0.0Reset Aborts ai! processing (instruction or exception) and does not save old context. 1.0Address Errar 1.1Bus Error Suspends processing (instruction or exception) and saves internal context. 4.1Trace 4.2Interrupt 2 2.0BKPT, CALLM, CHK, CHK2, Exception processing is part af instruction execution. cp Midinstruction, cp Protocal Violation, epTRAPcc, Divide by Zero, RTE, ATM, TRAP. TRAPcc, TRAPV 3 3.6tHegat instruction, Line A, Unimplemented Exception processing begins before instruction is Line F, Privilege Violation, cp Preinstruction| executed. 4 4.0cp Postinstruction Exception processing begins when current instruction OF previous exception processing has completed. NOTE 0.0 1s the highest priority; 4.2 is the towest, M68020 USER'S MANUAL MOTOROLAThe priority scheme is very important in determining the order in which exception handlers execute when several exceptions occur at the same time. As a general rule, the lower the priority of an exception, the sooner the handler routine for that exception executes. For example, if simultaneous trap, trace, and interrupt exceptions are pending, the exception processing for the trap occurs first, followed immediately by exception processing for the trace, and then for the interrupt. When the processor resumes normal instruction execution, it is in the interrupt handler, which returns to the trace handler, which returns to the trap exception handler. This rule does not apply to the reset exception: its handler is executed first even though il has the highest priority because the reset operation clears all other exceptions. 6.1.12 Return from Exception After the MC68020/EC020 has completed exception processing for all pending exceptions, it resumes normal instruction execution at the address in the vector for the last exception processed. Once the exception handler has completed execution, the processor must return to the system context prior to the exception (if possible). The RTE instruction returns from the handler to the previous system context for any exception. When the processor executes an RTE instruction, it examines the stack frame on top of the active supervisor stack to determine if it is a valid frame and what type of context restoration it requires. The following paragraphs describe the processing for each of the stack frame types; refer to 6.3 Coprocessor Considerations for a description of the stack frame type formats. For a normal four-word frame, the processor updates the SR and PC with the data read from the stack, increments the stack pointer by eight, and resumes normal instruction execution. For the throwaway four-word frame, the processor reads the SR value from the frame, increments the active stack pointer by eight, updates the SR with the value read from the Stack, and then begins RTE processing again, as shown in Figure 6-7. The processor reads a new format word from the stack frame on top of the active stack (which may or may not be the same stack used for the previous operation) and performs the proper operations corresponding to that format. In most cases, the throwaway frame is on the interrupt stack and when the SR value is read from the stack, the S and M bits are set. In that case, there is a normal four-word frame or a ten-word coprocessor midinstruction frame on the master stack. However, the second frame may be any format (even another throwaway frame) and may reside on any of the three system stacks. For the six-word stack frame, the processor restores the SR and PC values from the stack, increments the active supervisor stack pointer by 12, and resumes normal instruction execution. MOTOROLA M68020 USER'S MANUAL 6-19TEMP @ {SP} + READ FORMAT WORD SR4 TEMP SP 4SP +6 OTHERWISE INVALID FORMAT WORD FORMAT CODE $1 (THROWAWAY FRAME) OTHERWISE FORMAT CODE = $0 (FOUR-WORD FRAME} OTHERWISE ~~ OTHER FORMATS PC (SP) SP q@SP+6 SR 4 TEMP EXIT Figure 6-7. RTE instruction for Throwaway Four-Word Frame TAKE FORMAT ERROR EXCEPTION / For the coprocessor midinstruction stack frame, the processor reads the SR, PC, instruction address, internal register values, and the evaluated effective address from the Stack, restores these values to the corresponding internal registers, and increments the stack pointer by 20. The processor then reads from the response register of the coprocessor that initiated the exception to determine the next Operation to be performed. Refer to Section 7 Coprocessor Interface Description for details of coprocessor-related exceptions. For both the short and long bus fault stack frames, the processor first checks the format value on the stack for validity. In addition, for the long stack frame, the processor compares the version number in the stack with its own version number. The version number is located in the most significant nibble (bits 15-12) of the word at location SP + $36 in the long stack frame. This validity check is required in a multiprocessor system to ensure that the data is properly interpreted by the RTE instruction. The RTE instruction also reads from both ends of the stack frame to make sure it is accessible. If the frame is invalid or inaccessible, the processor takes a format error or a bus error exception, respectively. Otherwise, the processor reads the entire frame into the proper internal registers, deallocates the stack, and resumes normal processing. Once the processor begins to load the frame to restore its interna! state, the assertion of the BERRA signal 6-20 M68020 USERS MANUAL MOTOROLAcauses the processor to enter the halted state. Refer to 6.2 Bus Fault Recovery for a description of the processing that occurs after the frame is read into the internal registers. If a format error or bus error exception occurs during the frame validation sequence of the RTE instruction, either due to any of the errors previously described or due to an illegal format code, the processor creates a normal four-word or a bus fault stack frame below the frame that it was attempting to use. In this way, the faulty stack frame remains intact. The exception handler can examine or repair the faully frame. In a multiprocessor system, the faulty frame can be left to be used by another processor of a different type (e.g., an MC68010 or a future M68000 family processor) when appropriate. 6.2 BUS FAULT RECOVERY An address error exception or a bus error exception indicates a bus fault. The saving of the processor state for a bus error or address error is described in 6.1.2 Bus Error Exception, and the restoring of the processor state by an ATE instruction is described in 6.1.12 Return from Exception. Processor accesses of either data items or the instruction stream can result in bus errors. When a bus error exception occurs while accessing a data item, the exception is taken immediately after the bus cycle terminates. The processor may never access an instruction that is part of the instruction stream. In this case, the bus error would not be processed. For instruction faults, when the short bus fault stack frame applies, the address of the pipe stage B word is the value in the PC plus four, and the address of the stage C word is the value in the PC plus two. For the long format, the long word at SP + $24 contains the address of the stage B word; the address of the stage C word is the address of the stage B word minus two. Address error faults occur only for instruction stream accesses, and the exceptions are taken before the bus cycles are attempted. 6.2.1 Special Status Word (SSW) The internal SSW (see Figure 6-8) is one of several registers saved as part of the bus fault exception stack frame. Both the short bus fault format and the long bus fault format include this word at offset $A. The bus cycle fault stack frame formats are described in detail in 6.4 Exception Stack Frame Formats. The SSW information indicates whether the fault was caused by an access to the instruction stream, data stream, or both. The high-order half of the SSW contains two status bits each for the B and C stages of the instruction pipe. If an address error exception occurs, the fault bits written to the stack frame are not set (they are only set due to a bus error, as previously described), and the rerun bits alone show the cause of the exception. Depending on the state of the pipeline, either RB and RC are set, or only RC is set. To correct the pipeline contents and continue execution of the suspended instruction, software must place the correct instruction stream data in the stage C and/or stage B images requested by the rerun bits and must clear the rerun bits. The least significant half of the SSW applies to data cycles only. Data and instruction stream faults may be pending simultaneously; the fault handler should be able to recognize any combination of the FC, FB, AC, RB, and DF bits. MOTOROLA M68020 USERS MANUAL 6-2118 14 13 2 " 10 9 7 6 5 4 3 2 a [rc [re] rc [re] o [ o | o | oF | am | aw | SIZE | o | FC2--CO | Figure 6-8. Special Status Word Format FCFault on Stage C When the FC bit is set, the processor attempted to use stage C and found it to be marked invalid due to a bus error on the prefetch for that stage. FC can be used by a bus error handler to determine the cause(s) of a bus error exception. FBFault on Stage B When the FB bit is set, the processor attempted to use Stage B and found it to be marked invalid due to a bus error on the prefetch for that Stage. FB can be used by a bus error handler to determine the cause(s) of a bus error exception. RCRerun Ftag for Stage C The RC bit is set to indicate that a fault occurred during a prefetch for stage C. The RC bit is always set when the FC bit is set. The RC bit indicates that the word in Stage C of the instruction pipe is invalid, and the state of the bit can be used by a handler to repair the values in the pipe after an address error or a bus error, if necessary. lf the RC bit is set when the processor executes an RTE instruction, the processor may execute a bus cycle to prefetch the instruction word for stage C of the pipe (if it is required). If the RC and FC bits are set, the RTE instruction automatically reruns the prefetch cycle for stage C. The address space for the bus cycle is the program space for the privilege level indicated in the copy of the SR on the stack. If the RC bit is clear, the words on the stack for stage C of the pipe are accepted as valid: the processor assumes that there is no prefetch pending for stage C and that software has repaired or filled the image of stage C, if necessary. 1 = Rerun faulted bus cycle or run pending prefetch 0 = Do not rerun bus cycle RBRerun Flag for Stage B The RB bit is set to indicate that a fault occurred during a prefetch for stage B. The RB bit is always set when the FB bit is set. The RB bit indicates that the word in stage B of the instruction pipe is invalid, and the state of the bit can be used by a handler to repair the values in the pipe after an address error or a bus error, if necessary. If the RB bit is set when the processor executes an RTE instruction, the processor may execute a bus cycle to prefetch the instruction word for stage B of the pipe (if it is required). If the RB and FB bits are set, the RTE instruction automatically reruns the prefetch cycle for stage B. The address space for the bus cycle is the program space for the privilege tevel indicated in the copy of the SR on the stack. !f the RB bit is clear, the words on the 6-22 M68020 USER'S MANUAL MOTOROLAstack for stage B of the pipe are accepted as valid; the processor assumes that there is no prefetch pending for stage B and that software has repaired or filled the image of stage B, if necessary. 1 = Rerun faulted bus cycle or run pending prefetch 0 = Do not rerun bus cycle Bits 11-9Reserved by Motorola DFFault/Rerun Flag If the DF bit is set, a data fault has occurred and caused the exception. If the DF bit is set when the processor reads the stack frame, it reruns the faulted data access; otherwise, it assumes that the data input buffer value on the stack is valid for a read or that the data has been correctly written to memory for a write (or that no data fault occurred). 1 = Rerun faulted bus cycle or run pending prefetch 0 = Do not rerun bus cycle RM-Read-Modify-Write 1 = Read-modify-write operation on data cycle 0 = Not a read-modify-write operation RWRead/Write 1 = Read on data cycle 0 = Write on data cycle SIZESize Code The SIZE field indicates the size of the operand access for the data cycle. Bit 3Reserved by Motorola FC2-FCOSpecifies the address space for data cycle 6.2.2 Using Software to Complete the Bus Cycles One method of completing a faulted bus cycle is to use a software handler to emulate the cycle. This is the only methed for correcting address errors. The handler should emulate the faulted bus cycle in a manner that is transparent to the instruction that caused the fauit. For instruction stream faults, the handler may need to run bus cycles for both the B and C stages of the instruction pipe. The RB and RC bits of the SSW identify the stages that may require a bus cycle; the FB and FC bits of the SSW indicate that a stage was invalid when an attempt was made to use its contents. Those stages must be repaired, For each faulted stage, the software handler should copy the instruction word from the proper address space as indicated by the S-bit of the copy of the SR saved on the stack to the image of the appropriate stage in the stack frame. In addition, the handler must clear the AB or RC bit associated with the stage that it has corrected. The handler should not change the FB and FC bits. MOTOROLA M68020 USERS MANUAL 8-23To repair data faults (indicated by DF = 1), the software should first examine the RM bit in the SSW to determine if the fault was generated during a read-modify-write operation. If RM = 0, the handler should then check the RW bit of the SSW to determine if the fault was caused by a read or a write cycle. For data write faults, the handler must transfer the properly sized data from the data output buffer on the stack frame to the location indicated by the data fault address in the address space defined by the SSW. (Both the data output buffer and the data fault address are part of the stack frame at SP + $18 and SP + $19, respectively.) Data read faults only generate the long bus fault frame, and the handler must transfer properly sized data from the location indicated by the fault address and address space to the image of the data input buffer at location SP + $2C of the long format stack frame. Byte, word, and 3-byte operands are right justified in the 4-byte data buffers. In addition, the software handler must clear the DF bit of the SSW to indicate that the fauited bus cycle has been corrected. To emulate a read-modify-write cycle, the exception handler must first read the operation word at the PC address (SP + 2 of the stack frame). This word identifies the CAS, CAS2, or TAS instruction that caused the fault. Then the handler must emulate this entire instruction (which may consist of up to four long-word transfers) and update the CCR portion of the SR appropriately, because the ATE instruction expects the entire operation to have been completed if the RM bit is set and the DF bit is cleared. This is true even if the fault occurred on the first read cycle. To emulate the entire instruction, the handler must save the data and address registers for the instruction (with a MOVEM instruction, for example). Next, the handler reads and modifies (if necessary) the memory location. It clears the DF bit in the SSW of the stack frame and modifies the condition codes in the SR copy and the copies of any data or address registers required for the CAS and CAS2 instructions. Last, the handler restores the registers that it saved at the beginning of the emulation. Except for the data input buffer, the copy of the SR, and the SSW, the handler should not modify a bus fault stack frame. The only bits in the SSW that may be modified are DF, RB, and RC: all other bits, including those defined for internal use, must remain unchanged. Address error faults must be repaired in software. Address error faults can be distinguished from bus error faults by the value in the vector offset field of the format word. 6.2.3 Completing the Bus Cycles with RTE Another method of completing a faulted bus cycle is to allow the processor to rerun the bus cycles during execution of the ATE instruction that terminates the exception handler. This method cannot be used to recover from address errors. The RTE instruction is always executed. Unless the handler routine has corrected the error and cleared the fault (and cleared the RB/RC and DF bits of the SSW), the RTE instruction cannot complete the bus cycle(s). If the DF bit is still set at the time of the RTE execution, the faulted data cycle is rerun by the RTE instruction. If the FB or FC bit is set and the corresponding rerun bit (RB or RC) was not cleared by the software, the ATE reruns the associated instruction prefetch. The fault occurs again unless the cause of the fault, such as a nonresident page in a virtual memory system, has been corrected. If the RB or RC bit is set and the 6-24 M68020 USERS MANUAL MOTOROLAcorresponding fault bit (FB or FC) is cleared, the associated prefetch cycle may or may not be run by the RTE instruction (depending on whether the stage is required). If a fault occurs when the RTE instruction attempts to rerun the bus cycle(s), the processor creates a new stack frame on the supervisor stack after deallocating the previous frame, and address error or bus error exception processing starts in the normal manner. The read-modify-write operations of the MC68020/EC020 can also be completed by the RTE instruction that terminates the handler routine. The rerun operation, executed by the ATE instruction with the DF bit of the SSW set, reruns the entire instruction. If the cause of the error has been corrected, the handler dces not need to emulate the instruction but can leave the DF bit set and execute the ATE instruction. 6.3 COPROCESSOR CONSIDERATIONS Exception handler programmers should consider carefully whether to save and restore the context of a coprocessor at the beginning and end of handler routines for exceptions that can occur during the execution of a coprocessor instruction {i.e., bus errors, interrupts, and coprocessor-related exceptions). The nature of the coprocessor and the exception handler routine determines whether or not saving the state of one or more coprocessors with the cpSAVE and cpRESTORE instructions is required. If the coprocessor allows multiple coprocessor instructions to be executed concurrently, it may require its state to be saved and restored for all coprocessor-generated exceptions, regardless of whether or not the coprocessor is accessed during the handler routine. The MC68882 fioating-point coprocessor is an example of this type of coprocessor. On the other hand, the MC68881 floating-point coprocessor requires FSAVE and FRESTORE instructions within an exception handler routine only if the exception handler itself uses the coprocessor. 6.4 EXCEPTION STACK FRAME FORMATS The MC68020/EC020 provides six different stack frames for exception processing. The set of frames includes the normal four- and stx-word stack frames, the four-word throwaway stack frarne, the coprocessor midinstruction stack frame, and the short and long bus fault stack frames. When the MC68020/EC020 writes or reads a stack frame, it uses long-word operand transfers wherever possible. Using a long-word-aligned stack pointer with memory that is on a 32-bit port greatly enhances exception processing performance. The processor does not necessarily read or write the stack frame data in sequential order. The system software should not depend on a particular exception generating a particular stack frame. For compatibility with future devices. the software should be able to handle any type of stack frame for any type of exception. Table 6-5 summarizes the stack frames defined for the MC68020/ECQ20. MOTOROLA M68020 USER'S MANUAL 6-25Table 6-5. Exception Stack Frames Stack Frames Exception Types (Stacked PC Polnts fo) 15 o Interrupt [Next instruction] SP STATUS REGISTER @ Format Error [RTE or cpRESTORE instruction] $02 PROGRAM COUNTER TRAP [NEXT instruction] @ Illegal Instruction {Illegal instruction] soe Jao oof VECTOR OFFSET @ A-Line Instruction [A-line instruction] @ F-Line Instruction [F-line instruction} FOUR-WORD STACK FRAME -~ FORMAT $0 @ Privilege Violation [First word of instruction causing Privilege Violation] @ Coprocessor [Opword of instuction that Preinstruction returned the take preinstruction primitive] us 8 Created on [Next instruction - same as on SP STATUS REGISTER Interrupt Stack master stack] +$02 PROGRAM COUNTER during interrupt / exception processing +$06 | 0001] VECTOR OFFSET when transition from master state to THROWAWAY FQUR-WORD i STACK FRAME FORMAT $1 interrupt state occurs 15 6 CHK {Next instruction for all these SP STATUS REGISTER CHK2 exceptions] +$02 @ cpTRAPcc PROGRAM COUNTER @ TRAPco INSTRUCTION ADDRESS +$06} 0010] VECTOR OF FSET e TRAPY is the address of the instructian 8 that caused the exception 78) STRUCTION ADDRESS _| Trace p @ Zero Divide @ MMU Configuration SIX-WORD Coprocessor STACK FRAME FORMAT $2 . eects truction 15 6 Coprocessor [Next word to be fetched from SP ~~ STATUS REGISTEA Midinstruction instruction stream for ali these +802 PROGRAM COUNTER Main-Detected exceptions) Proteco! Violation +$06{1001] VECTOR OFFSET @ Interrupt Detected INSTRUCTION ADDRESS During Coprocessor __ is the address of the instruction +$08 INSTRUCTION ADDRESS __J neatea thal caused the exception iC ith null +s INTERNAL REGISTERS, (supported with nu 4 WORDS come again with +$12 interrupts allowed COPROCESSOR MIDINSTRUCTION STACK FRAME (10 WORDS) FORMAT 9 primitive} 6-26 M68020 USERS MANUAL MOTOROLATable 6-5. Exception Stack Frames (Continued) Stack Frames Exception Types (Stacked PC Points to) 16 0 sP > STATUS REGISTER e Address Error or [Next instruction] +$02 Bus Error PROGRAM COUNTER Execution Unit +$06 [1010] VECTOR OFFSET at Instruction +508 WTERNAL REGISTER Boundary +$0A SPECIAL STATUS REGISTER +300 INSTRUCTION PIPE STAGE +$06 INSTRUCTION PIPE STAGE B +$50 | oATAGYCLE FAULT ADDRESS +312 +$14 INTERNAL REGISTER +$16 INTERNAL REGISTER +$18 CATA OUTPUT BUFFER +$hA +$1C INTERNAL REGISTER 4S INTERNAL REGISTER SHORT 8US FAULT STACK FRAME (16 WORDS) FORMAT $A 15 0 SP pe STATUS REGISTER @ Address Error or [Address of instruction in +$02 PROGRA NTER Bus Error excution when fault occurred M COU Instruction may not be the instruction that *$06)1011 I VECTOR OFFSET Execution in generated the faulted bus cycle] +$08 INTERNAL REGISTER Progress +$0A SPECIAL STATUS REGISTER +$0C. INSTRUCTION PIPE STAGE C +$08 INSTRUCTION PIPE STAGE B S0 t DATA CYCLE FAULT ADORESS - +$i4 INTERNAL REGISTER +916 INTERNAL REGISTER $18 * DATA OUTPUT BUFFER-- +$1A 4$ic INTERNAL REGISTER, 4 WORDS 4$22 4 +82 STAGE 8 ADDRESS +926 INTERNAL REGISTERS, +$24 2 WORDS +820 DATA INPUT BUFFER +30 INTERNAL REGISTERS, 3. WORDS +$36 +338 | VERSION | INTERNAL INFORMATION INTERNAL REGISTERS, +8 WORDS 435A i ONG BUS FAULT STACK FRAME {46 WORDS) FORMAT $B MOTOROLA M68020 USERS MANUAL 6-27SECTION 7 COPROCESSOR INTERFACE DESCRIPTION The M68000 family of general-purpose microprocessors provides a level of performance that satisfies a wide range of computer applications. Special-purpose hardware, however, can often provide a higher level of performance for a specific application. The coprocessor concept allows the capabilities and performance of a general-purpose processor to be enhanced for a particular application without encumbering the main processor architecture. A coprocessor can efficiently meet specific capability requirements that must typically be implemented in software by a general-purpose processor. With a general- purpose main processor and the appropriate coprocessor(s), the processing capabilities of a system can be tailored to a specific application. The MC68020/EC020 supports the M68000 coprocessor interface described in this section. This section is intended for designers who are implementing coprocessors to interface with the MC68020/EC020. The designer of a system that uses one or more Motorola coprocessors (the MC68881 or MC68882 floating-point coprocessor, for example) does not require a detailed knowledge of the M68000 coprocessor interface. Motorola coprocessors conform to the interface described in this section. Typically, they implement a subset of the interface, and that subset is described in the coprocessor user's manual. These coprocessors execute Motorola-defined instructions that are described in the user's manual for each coprocessor. 7.1 INTRODUCTION The distinction between standard peripheral hardware and an M68000 coprocessor is impertant from a programming model perspective. The programming model of the main processor consists of the instruction set, register set, and memory map. An M68s000 coprocessor is a device or set of devices that communicates with the main processor through the protocol defined as the M68000 coprocessor interface. The programming model for a coprocessor is different than that for a peripheral device. A coprocessor adds additional instructions and generally additional registers and data types to the programming mode! that are not directly supported by the main processor architecture. The additional instructions are dedicated coprocessor instructions that utilize the coprocessor capabilities. The necessary interactions between the main processor and the coprocessor that provide a given service are transparent to the programmer. That is, the programmer does not need to know the specific communication protocol between the main processor and the coprocessor because this protocol is implemented in hardware. Thus, the coprocessor can provide capabilities to the user without appearing separate from the main processor. MOTOROLA M68020 USERS MANUAL 7-1In contrast, standard peripheral hardware is generally accessed through interface registers mapped into the memory space of the main processor. To use the services provided by the peripheraf, the programmer accesses the peripheral registers with standard processor instructions. While a peripheral could conceivably provide capabilities equivalent to a coprocessor for many applications, the programmer must implement the communication protocol between the main processor and the peripheral necessary to use the peripheral hardware. The communication protocol detined for the M68000 coprocessor interface is described in 7.2 Coprocessor Instruction Types. The algorithms that implement the M68000 coprocessor interface are provided in the microcode of the MC68020/EC020 and are completely transparent to the MC68020/EC020 programming model. For example, floating-point operations are not implemented in the MC68020/EC020 hardware. In a system utilizing both the MC68020/EC020 and the MC68881 or MC68882 floating-point coprocessor, a programmer can use any of the instructions defined for the coprocessor without knowing that the actual computation is performed by the MC68881 or MC68882 hardware, 7.1.1 Interface Features The M68000 coprocessor interface design incorporates a number of flexible capabilities. The physical coprocessor interface uses the main Processor external bus, which simplifies the interface since no special-purpose signals are involved, With the MC68020/EC020, a coprocessor uses the asynchronous bus transfer Protocol. Since standard bus cycles transfer information between the main processor and the coprocessor, the coprocessor can be implemented in whatever technology is available to the coprocessor designer. A coprocessor can be implemented as a VLSI device, as a Sparate system board, or even as a Separate computer system. Since the main processor and a M68000 coprocessor can communicate using the asynchronous bus, they can operate at different clock frequencies. The system designer can choose the speeds of a main processor and coprocessor that provide the optimum performance for a given system. Both the MC68881 and MC68882 floating-point coprocessors use the asynchronous bus handshake protocol. The M68000 coprocessor interface also facilitates the design of coprocessors. The coprocessor designer must only conform to the coprocessor interface and does not need an extensive knowledge of the architecture of the Main processor. Also, the main Processor can operate with a coprocessor without having explicit provisions made in the main processor for the capabilities of that coprocessor. This type of interface provides a great deal of freedom in the implementation of a given coprocessor. 7.1.2 Concurrent Operation Support The programming model for the M68000 family of microprocessors is based on sequential, nonconcurrent instruction execution, which implies that the instructions in a given sequence must appear to be executed in the order in which they occur. To maintain a uniform programming model, any coprocessor extensions should also maintain the 7-2 M68020 USER'S MANUAL MOTOROLAmodel of sequential, nonconcurrent instruction execution at the user levei. Consequently, the programmer can assume that the images of registers and memory affected by a given instruction have been updated when the next instruction in the sequence accessing these registers or memory locations is executed. The M68000 coprocessor interface provides full support of ail operations necessary for nonconcurrent operation of the main processor and its associated coprocessors. Although the M68000 coprocessor interface allows concurrency in coprocessor execution, the coprocessor designer is responsible for implementing this concurrency while maintaining a programming mode! based on sequential nonconcurrent instruction execution. For example, if the coprocessor determines that instruction B does not use or alter resources to be altered or used by instruction A, instruction B can be executed concurrently (if the execution hardware is also available). Thus, the required instruction interdependencies and sequences of the program are always respected. The MC688&2 coprocessor offers concurrent instruction execution; whereas, the MC68881 coprocessor does not. However, the MC68020/EC020 can execute instructions concurrently with coprocessor instruction execution in the MC68881. 7.1.3 Coprocessor Instruction Format The instruction set for a given coprocessor is defined by the design of that coprocessor. When a coprocessor instruction is encountered in the main processor instruction stream, the MC68020/EC020 hardware initiates communication with the coprocessor and coordinates any interaction necessary to execute the instruction with the coprocessor. A programmer needs to know only the instruction set and register set defined by the coprocessor to use the functions provided by the coprocessor hardware. The instruction set of an M68000 coprocessor uses a subset of the F-line operation words in the M68000 instruction set. The operation word is the first word of any M68000 family instruction, The F-line operation word contains ones in bits 15-12 (refer to Figure 7-1), the remaining bits are coprocessor and instruction dependent. The F-line operation word may be followed by as many extension words as are required to provide additional information necessary for the execution of the coprocessor instruction. is 449 9 8 6 5 0 [1 [3 | 1 | 1 Cpld TYPE | TYPE DEPENDENT | Figure 7-1. F-Line Coprocessor Instruction Operation Word As shown in Figure 7-1, bits 11-9 of the F-line operation word encode the coprocessor identification (CpID) field. The MC68020/EC020 uses the CpID field to indicate the coprocessor to which the instruction applies. F-line operation words, in which the CpiD is zero, are not coprocessor instructions for the MC68020/EC020. Instructions with a CpID of zero and a nonzero type field are unimplemented instructions that cause the MOTOROLA M68020 USER'S MANUAL 7-3MC68020/EC020 to begin exception processing. The MC68020/EC020 never generates coprocessor interface bus cycles with the CpID equal to zero (except via the MOVES instruction) CplD codes of 000-101 are reserved for current and future Motorola coprocessors, and CplD codes of 110-111 are reserved for user-defined coprocessors, The Motorola CplD code of 001 designates the MC68881 or MC68882 floating-point coprocessor. By defautt, Motorola assemblers will use a CpID code of 001 when generating the instruction The encoding of bits 8-0 of the coprocessor instruction operation word is dependent on the particular instruction being implemented (refer to 7.2 Coprocessor Instruction Types). 7.1.4 Coprocessor System Interface The communication protocol between the main processor and coprocessor necessary to execute a coprocessor instruction uses a group of interface registers, CIRs, resident within the coprocessor. By accessing one of the CIRs, the MC68020/EC020 hardware initiates coprocessor instructions. The coprocessor uses a set of response primitive codes and format codes defined for the M68000 coprocessor interface to communicate status and service requests to the main processor through these registers. The CIRs are also used to pass operands between the main Processor and the coprocessor. The CIR set, response primitives, and format codes are discussed in 7.3 Coprocessor Interface Register Set and 7.4 Coprocessor Response Primitives. 7.1.4.1 COPROCESSOR CLASSIFICATION. M6s8000 coprocessors can be classified into two categories depending on their bus interface capabilities. The first category, non-DMA coprocessors, consists of coprocessors that always Operate as bus slaves. The second category, DMA coprocessors, consists of coprocessors that operate as bus slaves while communicating with the main processor across the coprocessor interface. These coprocessors also have the abilty to operate as bus masters, directly controlling the system bus. 'f the operation of a coprocessor does not require a large portion of the available bus bandwidth or has special requirements not directly satisfied by the main processor, that coprocessor can be efficiently implemented as a non-DMA coprocessor. Since non-DMA coprocessors always operate as bus slaves. all external bus-related functions that the coprocessor requires are performed by the main processor. The main processor transfers operands from the coprocessor by reading the operand from the appropriate CIR and then Space} and then writing that operand to the appropriate CIR using the coprocessor interface. The bus interface circuitry of a coprocessor operating as a bus slave is not as complex as that of a device Operating as a bus master. 7-4 M68020 USER'S MANUAL MOTOROLATo improve the efficiency of operand transfers between memory and the coprocessor, a coprocessor that requires a relatively high amount of bus bandwidth or has special bus requirements can be implemented as a DMA coprocessor. The DMA coprocessor provides all control, address. and data signals necessary to request and obtain the bus and then performs DMA transfers using the bus. DMA coprocessors, however, must still act as bus slaves when they require information or services of the main processor using the M68000 coprocessor interface protocol. 7.1.4.2 PROCESSOR-COPROCESSOR INTERFACE. Figure 7-2 is a block diagram of the signals involved in an asynchronous non-DMA M68000 coprocessor interface. Since the CpID on signals A15-A13 of the address bus is used with other address signals to select the coprocessor, the system designer can use several coprocessors of the same type and assign a unique CpID to each one. FC2 FCO Co COE CS] coprocessoa r MOA LOGIC AS MAIN PROCESSOR [__ > mceao20Eco20 | DS RAV | ASYNCHRONOUS | INTERFACE BSAGKA | DSACKO RF. , BSACKI / DSACKO TERA AGA , D31-D0 > FC2-FCO = 111 ) CPU SPACE CYCLE AIZ-A16 = 0010 COPROCESSOR ACCESS IN CPU SPACE AIS-AI3 = xa. COPROCESSOR IDENTIFICATION Ad-Al =m COPROCESSOR INFERFACE REGISTER SELECTOR Chip select logic may be integrated into the coprocessor. Address lines not specified above are O during coprocessor access. Figure 7-2. Asynchronous Non-DMA M68000 Coprocessor Interface Signal Usage The MC68020/EC020 accesses the registers in the CIR set using standard asynchronous bus cycles. Thus, the bus interface implemented by a coprocessor for its interface register set must satisfy the MC68020/EC020 address, data, and contral signal timing. The MC68020/EC020 bus operation is described in detail in Section 5 Bus Operation. MOTOROLA M68020 USERS MANUAL 7-5During coprocessor instruction execution, the MC68020/EC020 executes CPU space bus cycles to access the CIR set. The MC68020/ECO20 asserts FC2-FCo, identifying a CPU space bus cycle. The CIR set is mapped into CPU space in the same manner that a peripheral interface register set is generally mapped into data Space. The information encoded on FC2-FCO and the address bus of the MC68020/EC020 during a coprocessor access IS used to generate the chip select signal for the coprocessor being accessed. Other address lines select a register within the interface set. The information encoded on the function code and address lines of the MC68020/EC020 during a coprocessor access is illustrated in Figure 7-3. FUNCTION ADDRESS CODE BUS 0 ED] 20 19 16 15 13 12 5 4 a 2 Lifts} [goo ccc cco ee ofaet ol ow lov ovens an | CPU SPACE TYPE FIELD Figure 7-3. MC68020/EC020 CPU Space Address Encodings Signals A19-A16 of the MC68020/ECo20 address bus specify the CPU Space cycle type for a CPU space bus cycle. The types of CPU space cycles currently defined for the MC68020/EC020 are interrupt acknowledge, breakpoint acknowledge, module support operations, and coprocessor access cycles. CPU space type $2 (A19-A16 = 0010) Specifies a coprocessor access cycle. A15-A13 specify the CpID code for the coprocessor being accessed. This code is transferred from bits 11-9 of the coprocessor instruction operation word (refer to Figure 7-1) to the address bus dur a given coprocessor. The FC2-FCO and A19-A16 signals indicate a coprocessor access: A15-A13 indicate which of the possible eight coprocessors (000-111) is being accessed. Bits A31-A20 and A12-A5 of the MC68020 address bus and bits A23-A20 and A12-A5 of the MC68EC020 address bus are always zero during a coprocessor access. 7.1.4.3 COPROCESSOR INTERFACE REGISTER SELECTION. Figure 7-4 shows that the value on the MC68020/ECQ20 address bus during a coprocessor access addresses a unique region of the main processor's CPU address space. Signals A4AO of the MC68020/EC020 address bus select the CIR being accessed. The register map for the M68000 coprocessor interface is shown in Figure 7-5. The individual registers are described in detail in 7.3 Coprocessor Interface Register Set. 7-6 M68020 USER'S MANUAL MOTOROLACPU SPACE ADDRESS. $20000 INTERFACE REGISTER SET $2001F ADDRESS SPACE FOR COPROCESSOR WITH RESERVED ; CplD~0 $22000 J INTERFACE REGISTER SET $2201F ADDRESS SPACE FOR COPROCESSOR WITH RESERVED Cpl = 1 $24000 s 4 a e $2&000 INTERFACE REGISTER SET $2EO1F ADDRESS SPACE FOR ~ COPROCESSOR WITH RESEAVED Cpl = 7 Figure 7-4. Coprocessor Address Map in MC68020/EC020 CPU Space a 6 15 0 $00 RESPONSE CONTROL $04 SAVE RESTORE $08 OPERATION WORD COMMAND $oc (RESERVED) CONDITION $10 OPERAND $14 REGISTER SELECT (RESERVED) $18 INSTRUCTION ADDRESS sic OPERAND ADDRESS Figure 7-5. Coprocessor interface Register Set Map 7.2 COPROCESSOR INSTRUCTION TYPES The M68000 coprocessor interface supports four categories of coprocessor instructions: general, conditional, context save, and context restore. The category name indicates the type of operations provided by the coprocessor instructions in the category. The instruction category also determines the CIR accessed by the MC68020/EC020 to initiate instruction and communication protocols between the main processor and the coprocessor necessary for instruction execution. During the execution of instructions in the general or conditional categories, the coprocessor uses the set of coprocessor response primitive codes defined for the M68000 coprocessor interface to request services from and indicate status to the main processor. During the execution of the instructions in the context save and context MOTOROLA M68020 USER'S MANUAL 7-7restore categories, the coprocessor uses the set of coprocessor format codes defined for the M68000 coprocessor interface to indicate its status to the main processor 7.2.1 Coprocessor General Instructions The coprocessor general instruction category contains data processing instructions and other general-purpose instructions for a given coprocessor. 7.2.1.1 FORMAT. Figure 7-6 shows the format of a coprocessor general instruction. 9 8 ? 6 5 O 1 i 1 1 | i | Cpld | 9 | a | 0 EFFECTIVE ADDRESS | COPROCESSOR COMMAND OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR.DEFINED EXTENSION WORDS Figure 7-6. Coprocessor General Instruction Format (cpGEN) The mnemonic cpGEN is a generic mnemonic used in this discussion for all general instructions. The mnemonic of a specific general instruction usually suggests the type of operation it performs and the coprocessor to which it applies. The actual mnemonic and syntax used to represent a coprocessor instruction is determined by the syntax of the assembler or compiler that generates the object code. A coprocessor general instruction consists of at least two words. The first word of the instruction is an F-line operation code (bits 15-12 = 1111). The CpID field of the F-line operation code is used during the coprocessor access to indicate which coprocessor in the system executes the instruction. During accesses to the CIRs (refer to 7.1.4.2 Processor-Coprocessor Interface), the processor places the CpID on address lines A15A13. Bits 8-6 = 000 of the first word of an instruction indicate that the instruction is in the general instruction category. Bits 5O of the F-line operation code sometimes encode a standard M68000 effective address specifier (refer to M68000PM/AD, M68cC00 Family Programmer's Reference Manual). During the execution of a cpGEN instruction, the coprocessor can use a coprocessor response primitive to request that the MC68020/EC020 perform an effective address calculation necessary for that instruction. Using the effective address specifier field of the F-line operation code, the processor then determines the effective addressing mode. If a coprocessor never requests effective address calculation, bits 5~O can have any value (don't cares). The second word of the general type instruction is the coprocessor command word. The main processor writes this command word to the command CIR to initiate execution of the instruction by the coprocessor. An instruction in the coprocessor general instruction category optionally includes a number of extension words following the coprocessor command word. These words can provide additional information required for the coprocessor instruction. For example, if 7-8 M68020 USER'S MANUAL MOTOROLAthe coprocessor requests that the MC68020/EC020 calculate an effective address during coprocessor instruction execution, information required for the calculation must be included in the instruction format as effective address extension words. 7.2.1.2 PROTOCOL. The execution of a cpGEN instruction follows the protocol shown in Figure 7-7. The main processor initiates communication with the coprocessor by writing the instruction command word to the command CIR. The coprocessor decodes the command word to begin processing the cpGEN instruction. Coprocessor design determines the interpretation of the coprocessor command word: the MC68020/EC020 does not attempt to decode it. While the coprocessor is executing an instruction, it requests any required services from and communicates status to the main processor by placing coprocessor response primitive codes in the response CIR. After writing to the command CIR, the main processor reads the response CIR and responds appropriately. When the coprocessor has completed the execution of an instruction or no longer needs the services of the main processor to execute the instruction, it provides a response to release the main processor. The main processor can then execute the next instruction in the instruction stream. However, if a trace exception is pending, the MC68020/EC020 does not terminate communication with the coprocessor until the coprocessor indicates that it has completed all processing associated with the cpGEN instruction (refer to 7.5.2.5 Trace Exceptions). The coprocessor interface protocol shown in Figure 7-7 allows the coprocessor to define the operation of each coprocessor general type instruction. That is, the main processor initiates the instruction execution by writing the instruction command word to the command CIR and by reading the response CIR to determine its next action. The execution of the coprocessor instruction is then defined by the internal operation of the coprocessor and by its use of response primitives to request services from the main processor. This instruction protocol allows a wide range of operations to be implemented in the general instruction category. MOTOROLA M68020 USER'S MANUAL 79MAIN PROCESSOR COPROCESSOR M1 RECOGNIZE COPROCESSOR INSTRUCTION F-LINE OPERATION WORD M2 WAITE COPROCESSOR COMMAND WORD TO COMMAND CIR 2 C1 DECODE COMMAND WORD AND INITIATE COMMAND EXECUTION C2 WHILE (MAIN PROCESSOR SERVICE 1S REQUIRED} DO STEPS 1) AND 2) BELOW Ma READ COPROCESSOR RESPONSE PRIMITIVE CODE <_> 1) REQUEST SERVICE BY PLACING APPROPRIATE FROM RESPONSE CiR RESPONSE PRIMITIVE CODE IN RESPONSE CIR 1} PERFORM SERVICE REQUESTED BY RESPONSE 2} RECEIVE SERVICE FROM MAIN PROCESSOR PRIMITIVE 2) IF (COPROCESSOR RESPONSE PRIMITIVE C2 REFLECT NO COME AGAIN" IN RESPONSE CIR INDICATES "COME AGAIN") GO TO M3 (SEE NOTE 1) C4 COMPLETE COMMAND EXECUTION M4 PROCEED WITH EXECUTION OF NEXT INSTRUCTION C5 REFLECT "PROCESSING FINISHED* STATUS IN (SEE NOTE 2) RESPONSE CIA NOTES: 1. "Come Again indicates that further service of the main processor is being requested by the caprocessor 2. The next instruction should be the operation word pointed to by the ScanPC at this point. The operation of the MC68020/EC020 ScanPC is discussed in 7.4.1 ScanPC Figure 7-7. Coprocessor Interface Protocol for General Category Instructions 7.2.2 Coprocessor Conditional Instructions The conditional instruction category provides program control based on the operations of the coprocessor. The coprocessor evaluates a condition and returns a true/false indicator to the main processor. The main processor compietes the execution of the instruction based on this true/false condition indicator. The implementation of instructions in the conditional category promotes efficient use of both the main processor and the coprocessor hardware. The condition specified for the instruction is related to the coprocessor operation and ig therefore evaluated by the coprocessor. However, the instruction completion following the condition evaluation is directly related to the operation of the main processor. The main processor performs the change of flow, the setting of a byte, or the TRAP operation, since its architecture explicitly implements these operations for its instruction set. Figure 7-8 shows the protocol for a conditional category coprocessor instruction. The main processor tnitiates execution of an instruction in this calegory by writing a condition selector to the condition CIR. The coprocessor decodes the condition selector to determine the condition to evaluate. The coprocessor can use response primitives to request that the main processor provide services required for the condition evaluation. 7-10 M68020 USER'S MANUAL MOTOROLAAfter evalualing the condition, the coprocessor returns a true/false indicator to the main processor by placing a null primitive (refer to 7.4.4 Null Primitive) in the response CIR. The main processor completes the coprocessor instruction execution when it receives the condition indicator from the coprocessor. M1 M2 Ma M4 MAIN PROCESSOR RECOGNIZE COPROCESSOR INSTRUCTION F-LINE OPERATION WORD WRITE COPROCESSOR CONDITION SELECTOR TO CONDITION CIR me Cl C2 READ COPROCESSOR RESPONSE PRIMITIVE CODE <> FROM RESPONSE CIR 1) PERFORM SERVICE REQUESTED BY RESPONSE PRIMITIVE 2) IF (COPROCESSOR RESPONSE PRIMITIVE C3 INDICATES "COME AGAIN) GO TO M3 (SEE NOTE) C4 COMPLETE EXECUTION OF INSTRUCTION BASED ON THE TRUE/FALSE CONDITION INDICATOR RETURNED IN THE RESPONSE CIR COPROCESSOR DECODE COMMAND WORD AND INITIATE COMMAND EXECUTION WHILE (MAIN PROCESSOR SERVICE IS REQUIRED} CO STEPS 1) AND 2} BELOW 1) REQUEST SERVICE BY PLACING APPROPRIATE RESPONSE PRIMITIVE CODE IN RESPONSE CIR 2} RECEIVE SERVICE FROM MAIN PROCESSOR COMPLETE CONDITION EVALUATION REFLECT "NO COME AGAIN" STATUS WITH TRUEFALSE CONDITION INDICATOR IN RESPONSE CIR NOTE: All coprocessot response primitives, except the Null primitive, that allow the "Come Again primitive attribute must Indicate Come Again when used during the execution of a conditional category instruction. If a "Come Again" attribute is not indicated in one of these primitives, the main processor will initiate protocol violation MOTOROLA exception processing (see 7.5.2.1 Pratecol Violations). Figure 7-8. Coprocessor Interface Protocol for Conditional Category Instructions M68020 USERS MANUAL 7-147.2.2.1 BRANCH ON COPROCESSOR CONDITION INSTRUCTION. The conditional instruction category includes two formats of the M68000 family branch instruction. These instructions branch on conditions related to the coprocessor operation. They execute similarly to the conditional branch instructions provided in the M68000 family instruction set. 7.2.2.1.1 Format. Figure 7-9 shows the format of the branch on coprocessor condition instruction that provides a word-length displacement. Figure 7-10 shows the format of this instruction that includes a long-word displacement. 18 14 13 12 i" 9 8 ? 6 5 tfa fafa Cplp Lotro] CONDITION SELECTOR OPTIONAL COPROCESSOR DEFINED EXTENSION WORDS . DISPLACEMENT | Figure 7-9. Branch on Coprocessor Condition Instruction Format (cpBcc.W) 9 8 7 6 5 0 1 fords La | CplD to [1 fa | CONDITION SELECTOR OPTIONAL COPROCESSOR. DEFINED EXTENSION WORDS DISPLACEMENT HIGH DISPLACEMENT LOW Figure 7-10. Branch on Coprocessor Condition Instruction Format (cpBec.L) The first word of the branch on coprocessor condition instruction is the F-line operation word. Bits 15-12 = 4111 and bits 11-9 contain the CpID code of the coprocessor that is to evaluate the condition. The value in bits 8-6 identifies either the word or the long-word displacement format of the branch instruction, which is specified by the cpBcc.W or cpBcc.L mnemonic, respectively. Bits 5-0 of the F-line Operation word contain the coprocessor condition selector field. The MC68020/EC020 writes the entire operation word to the condition CIR to initiate execution of the branch instruction by the coprocessor. The coprocessor uses bits 50 to determine which condition to evaluate. If the coprocessor requires additional information to evaluate the condition, the branch instruction format can include this information in extension words. Following the F-line operation word, the number of extension words is determined by the coprocessor design. The final word(s) of the cpBee instruction format contains the displacement used by the main processor to calculate the destination address when the branch is taken, 7.2.2.1.2 Protocol. Figure 7-8 shows the Protocol for the cpBec.L and cp8cc.W instructions. The main processor initiates the instruction by writing the F-line operation word to the condition CIR to transfer the condition Selector to the coprocessor. The main processor then reads the response CIR to determine its next action, The coprocessor can 7-12 M68020 USER'S MANUAL MOTOROLAreturn a response primilive to request services necessary to evaluate the conditton. if the coprocessor returns the false condition indicator, the main processor executes the next instruction in the instruction stream, If the coprocessor returns the true condition indicator, the main processor adds the displacement to the MC68020/EC020 scanPC (refer to 7.4.1 ScanPC) to determine the address of the next instruction for the main processor to execute. The scanPC must be pointing to the location of the first word of the displacement in the instruction stream when the address is calculated. The displacement is a twos- complement integer that can be either a 16-bit word or a 32-bit long word. The main processor sign-extends the 16-bit displacement to a long-word value for the destination address calculation, 7.2.2.2 SET ON COPROCESSOR CONDITION INSTRUCTION. The set on coprocessor condition instruction sets or resets a flag (a data alterable byte) according to a condition evaluated by the coprocessor. The operation of this instruction type is similar to the operation of the Sec instruction in the M68000 family instruction set. Although the Sce instruction and the cpScc instruction do not explicitly cause a change of program flow, they are often used to set flags that control program flow. 7.2.2.2.1 Format. Figure 7-11 shows the format of the set on coprocessor condition instruction, denoted by the epScc mnemonic. 15 141311 9 8 7 6&6 5 0 str fr]fa | CalD Fo fo | 3 EFFECTIVE ADDRESS RESERVED CONDITION SELECTOR OPTIONAL COPROCESSOR.DEFINED EXTENSION WORDS OPTIONAL EFFECTIVE ADDRESS EXTENSION WORDS (0-5 WORDS) Figure 7-11. Set on Coprocessor Condition Instruction Format (cpScc) The first word of the cpScc instruction, the F-line operation word, contains the CpID field in bits 11-9 and 001 in bits 8-6 to identify the cpScc instruction. Bits 5-0 of the F-line operation word are used to encode an M68000 family effective addressing mode (reter to M68000PM/AD, M68000 Family Programmer's Reference Manual). The second word of the cpScc instruction format contains the coprocessor condition selector field in bits 5-0. Bits 15-6 of this word are reserved by Motorola and should be zero to ensure compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpScc instruction. If the coprocessor requires additional information to evaluate the condition, the instruction can include extension words to provide this information. The number of these extension words, which follow the word containing the coprocessor condition selector fleld, is determined by the coprocessor design. MOTOROLA M68020 USER'S MANUAL 7-13The final portion of the cpSce instruction format contains zero to five effective address extension words. These words contain any additional information required to calculate the effective address specified by bits 50 of the F-line operation word. 7.2.2.2.2 Protocol. Figure 7-8 shows the protocol for the cpScc instruction. The MC68020/EC020 transfers the condition selector to the coprocessor by writing the word following the F-line operation word to the condition CIR. The main processor then reads the response CIR to determine its next action. The coprocessor can return a response primitive to request services necessary to evaluate the condition. The Operation of the cpScc instruction depends on the condition evaluation indicator returned to the main processor by the coprocessor. When the coprocessor returns.the false condition indicator, the main processor evaluates the effective address specified by bits 5-0 of the F-line operation word and sets the byte at that effective address to FALSE (all bits cleared). When the coprocessor returns the true condition indicator, the main processor sets the byte at the effective address to TRUE (all bits set to one). 7.2.2.3 TEST COPROCESSOR CONDITION, DECREMENT, AND BRANCH INSTRUCTION. The operation of the test coprocessor condition, decrement, and branch instruction is similar to that of the DBcc instruction provided in the M68000 family instruction set. This operation uses a coprocessor-evaluated condition and a loop counter in the main processor. It is useful for implementing DO UNTIL constructs used in many high-level languages. 7.2.2.3.1 Format. Figure 7-12 shows the format of the test coprocessor condition, decrement, and branch instruction, denoted by the cpDBcc mnemonic. 16 18 8k @ 7 6 5 4&4 3 3 ttrfata CplD jofof o{o |: | recster RESERVED CONDITION SELECTOR OPTIONAL COPROCESSOR. DEFINED EXTENSION WORDS DISPLACEMENT Figure 7-12. Test Coprocessor Condition, Decrement, and Branch Instruction Format (cpDBcc) The first word of the cpDBcc instruction, F-line operation word, contains the CpID field in bits 11-9 and 001001 in bits 8-3 to identify the cpDBcc instruction. Bits 2-0 of this operation word specify the main processor data register used as the loop counter during the execution of the instruction, The second word of the cpDBcc instruction format contains the coprocessor condition selector field tn bits 5-0 and shoutd contain zeros in bits 156 (reserved by Motorola) to maintain compatibility with future M6B000 products. This word is written to the condition CIR to initiate execution of the cpDBcc instruction. 7-14 M68020 USER'S MANUAL MOTOROLAif the coprocessor requires additional information to evaluate the condition, the cpDBcc instruction can include this information in extension words. These extension words follaw the word containing the coprocessor condition selector field in the cpDBcc instruction format. The last word of the instruction contains the displacement for the coDBcc instruction. This displacement is a twos-complement 16-bit value that is sign-extended to long-word size when it is used in a destination address calculation. 7.2.2.3.2 Protocol. Figure 7-8 shows the protocol for the cpDBcc instructions. The MC68020/EC020 transfers the condition selector to the coprocessor by writing the word folowing the operation word to the condition CIR. The main processor then reads the response CIR to determine its next action. The coprocessor can use a response primitive to request any services necessary {o evaluate the condition. lf the coprocessor returns the true condition indicator, the main processor executes the next instruction in the instruction stream. If the coprocessor returns the false condition indicator, the main processor decrements the low-order word of the register specified by bits 2-0 of the F-line operation word. If this register contains minus one {1) after being decremented, the main processor executes the next instruction in the instruction stream. If the register does not contain minus one (1) after being decremented, the main processor branches to the destination address to continue instruction execution. The MC68020/EC020 adds the displacement to the scanPC (refer to 7.4.1 ScanPC) to determine the address of the next instruction. The scanPC must point to the 16-bit displacement in the instruction stream when the destination address is calculated. 7.2.2.4 TRAP ON COPROCESSOR CONDITION INSTRUCTION. The trap on coprocessor condition instruction allows the programmer to initiate exception processing based on conditions related to the coprocessor operation. 7.2.2.4.1 Format. Figure 7-13 shows the format of the trap on coprocessor condition instruction, denoted by the cpoTRAPcc mnemonic. ee 9 6 7 6 5 4 & 2? 0 rfafafa cpio folef1]1]1]1 [ opmone RESERVED CONDITION SELECTOR OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS OPTIONAL WORD OR LONG-WORD OPERAND Figure 7-13. Trap on Coprocessor Condition Instruction Format (cpTRAPcc) The first word of the cpTRAPcc instruction, the F-line operation word contains the CpiID field in bits 11-9 and 001111 in bits 8--3 to identify the cpTRAPcc instruction. Bits 2-0 of the cpTRAPcc F-line operation word specify the opmode, which selects the instruction format. The instruction format can include zero, one, or two operand words. MOTOROLA M68020 USER'S MANUAL 7-15The second word of the cpTRAPcc instruction format contains the coprocessor condition selector in bits 5-0 and should contain zeros in bits 15-6 (these bits are reserved by Motorola) to maintain compatibility with future M68000 products. This word is written to the condition CIR to initiate execution of the cpTRAPcc instruction. lf the coprocessor requires additional information to evaluate a condition, the instruction can include this information in extension words. These extension words follow the word containing the coprocessor condition selector field in the cpTRAPcc instruction format. The operand words of the cpTRAPcc F-line operation word follow the coprocessor-defined extension words. These operand words are not explicitly used by the MC68020/EC020, but can be used to contain information referenced by the cpTRAPcc exception handling routines. The valid encodings for bits 2-0 of the F-line Operation word and the corresponding numbers of operand words are listed in Table 7-1. Other encodings of these bits are invalid for the coTRAPcc instruction. Table 7-1. cpTRAPcc Opmode Encodings Opmode Operand Words in Instruction Format o10 One Olt Two 700 zero 7.2.2.4.2 Protocol. Figure 7-8 shows the protocol for the cpTRAPcc instructions. The MC68020/EC020 transfers the condition selector to the coprocessor by writing the word following the operation word to the condition CIR. The main processor then reads the response CIR to determine its next action. The coprocessor can return a response primitive to request any services necessary to evaluate the condition. If the coprocessor returns the true condition indicator, the main processor initiates exception processing for the cpTRAPcc exception (refer to 7.5.2.4 cpTRAPcc Instruction Traps). If the coprocessor returns the false condition indicator, the main processor executes the next instruction in the instruction stream. 7.2.3 Coprocessor Context Save and Restore Instructions The coprocessor context save and context restore instruction categories in the M68000 coprocessor interface support multitasking programming environments. In a multitasking environment, the context of a coprocessor may need to be changed asynchronously with respect to the operation of that coprocessor. That is, the coprocessor may be interrupted at any point in the execution of an instruction in the general or conditional category to begin context change operations. In contrast to the general and conditional instruction categories, the context save and context restore instruction categories do not use the coprocessor response primitives. A set of format codes defined by the M68000 coprocessor interface communicates status 7-16 M68020 USER'S MANUAL MOTOROLAinformation to the main processor during the execution of these instructions. These coprocessor farmat codes are discussed in detail in 7.2.3.2 Coprocessor Format Words. 7.2.3.1 COPROCESSOR INTERNAL STATE FRAMES. The context save (cpSAVE) and context restore (cpDRESTORE) instructions transfer an internal coprocessor state frame between memory and a coprocessor. This internal coprocessor state frame represents the state of coprocessor operations. Using the cpSAVE and cpRESTORE instructions, it is possible to interrupt coprocessor operation, save the context associated with the current operation, and initiate coprocessor operations with a new context. A cpSAVE instruction stores a coprocessor internal state frame as a sequence of long- word entries in memory. Figure 7-14 shows the format of a coprocessor state frame. The format and length fields of the coprocessor state frame format comprise the format word. During execution of the cpSAVE instruction, the MC68020/EC020 calculates the state frame effective address from information in the operation word of the instruction and stores a format word at this effective address. The processor writes the long words that form the coprocessor state frame to descending memory addresses, beginning with the address specified by the sum of the effective address and the length field multiplied by four. During execution of the coRESTORE instruction, the MC68020/EC020 reads the state frame from ascending addresses beginning with the effective address specified in the instruction operation word. SAVE RESTORE ORDER ORDER v 24 23 16 15 0 0 0 FORMAT LENGTH | UNUSED, RESERVED a 1 COPROCESSOR-DEPENDENT INFORMATION ml 2 m2 3 Figure 7-14. Coprocessor State Frame Format in Memory The processor stores the coprocessor format word at the lowest address of the state frame in memory, and this word is the first word transferred for both the cpSAVE and cpRESTORE instructions. The word following the format ward does not contain information relevant to the coprocessor state frame, but serves to keep the information in the state frame a multiple of four bytes in size. The number of entries following the format word (at higher addresses) is determined by the format word length for a given coprocessor state. MOTOROLA M68020 USERS MANUAL 7-17The information in a coprocessor state frame describes a context of operation for that coprocessor. This description of a coprocessor context includes the program invisible State information and, optionally, the program visible state information. The program invisible state information consists of any internal registers or status information that cannot be accessed by the program but is necessary for the coprocessor to continue its operation at the point of suspension. Program visible state information includes the contents of all registers that appear in the coprocessor programming model and that can be directly accessed using the coprocessor instruction set. The information Saved by the cpSAVE instruction must include the program invisible state information. If coGEN instructions are provided to save the program visible state of the coprocessor, the CpSAVE and cpRESTORE instructions should only transfer the program invisible state information to minimize interrupt latency during a save or restore operation. 7.2.3.2 COPROCESSOR FORMAT WORDS. The coprocessor communicates status information to the main processor during the execution of cpoSAVE and cpRESTORE instructions using coprocessor format words. The format words defined for the M68000 coprocessor interface are listed in Table 7-2, Table 7-2. Coprocessor Format Word Encodings Format Code Length Meaning $00 $xx Empty/Reset $01 $xx Not Ready, Come Again $02 Sxx invalid Format $03 -SOF $xx Undefined, Reserved $10-SFF Length | Valid Format, Coprocessor Defined xx Don't care The upper byte of the coprocessor format word contains the code used to communicate coprocessor status information to the main processor. The MC68020/EC020 recognizes four types of format words: empty/reset, not ready, invalid format, and valid format. The MC68020/EC020 interprets the reserved format codes ($03-$0F) as invalid format words. The lower byte of the coprocessor format word specifies the size in bytes (which must be a muttiple of four) of the coprocessor state frame. This value is only relevant when the code byte contains the valid format code (refer to 7.2.3.2.4 Valid Format Word) 7.2.3.2.1 Empty/Reset Format Word. The coprocessor returns the empty/reset format code during a cpSAVE instruction to indicate that the coprecessor contains no user- specific information. That is, no coprocessor instructions have been executed since either a previous coORESTORE of an empty/reset format code or the previous hardware reset. (f the main processor reads the empty/reset format word from the save CIR during the initiation of a cpSAVE instruction, it stores the format word at the effective address specified in the cpSAVE instruction and executes the next instruction, 7-18 M68020 USER'S MANUAL MOTOROLAWhen the main processor reads the empty/reset format word from memory during the execution of the coRESTORE instruction, it writes the format word to the restore CIR. The main processor then reads the restore CIR and, if the coprocessor returns the empty/reset format word, executes the next instruction. The main processor can then initialize the coprocessor by writing the empty/reset format code to restore the CIR. When the coprocessor receives the empty/reset format code, it terminates any current operations and waits for the main processor to initiate the next coprocessor instruction. In particular, after the coRESTORE of the empty/reset format word, the execution of a CpSAVE should cause the empty/reset format word to be returned when a cpSAVE instruction is executed before any other coprocessor instructions. Thus, an empty/reset state frame consists only of the format word and the following reserved word in memory (refer to Figure 7-14) 7.2,3.2.2 Not-Ready Format Word. When the main processor initiates a CpSAVE instruction by reading the save CIR, the coprocessor can delay the save operation by returning a not-ready format word. The main processor then services any pending interrupts and reads the save CIR again. The not-ready format word delays the save operation until the coprocessor is ready to save its internal state. The cpSAVE instruction can suspend execution of a general or conditional coprocessor instruction; the coprocessor can resume execution of the suspended instruction when the appropriate State is restored with a cpRESTORE. If no further main processor services are required to complete coprocessor instruction execution, it may be more efficient to complete the instruction and thus reduce the size of the saved state. The coprocessor designer should consider the efficiency of completing the instruction or of Suspending and later resuming the instruction when the main processor executes a cpSAVE instruction, When the main processor initiates a coRESTORE instruction by writing a format word to the restore CIR, the coprocessor should usually terminate any current operations and restore the state frame supplied by the main processor. Thus, the not-ready format word should usually not be returned by the coprocessor during the execution of a cpRESTORE instruction. If the coprocessor must delay the coRESTORE operation for any reason, it can return the not-ready format word when the main processor reads the restore CIR. If the main processor reads the not-ready format word from the restore CIR during the cpRESTORE instruction, it reads the restore CIR again without servicing any pending interrupts. 7.2.3.2.3 Invalid Format Word. When the format word placed in the restore CIR to initiate a cpRESTORE instruction does not describe a valid coprocessor state frame. the coprocessor returns the invalid format word in the restore CIR. When the main processor reads this format word during the coRESTORE instruction, it sets the abort bit in the control CiR and initiates format error exception processing. A coprocessor usually should not place an invalid format word in the save CIR when the main processor initiates a coSAVE instruction. A coprocessor. however, may not be able to support the tnitratron of a cpSAVE instruction while it is executing a previously initiated cpSAVE or cpRESTORE instruction. In this situation. the coprocessor can return the invalid format word when the main processor reads the save CIR to initiate the CpSAVE instruction white either another cpSAVE or cpRESTORE instruction is executing. If the MOTOROLA M68020 USERS MANUAL 7-19main processor reads an invalid format word from the save CIR, it writes the abort mask to the control CIR and initiates format error exception processing (refer to 7.5.1.5 Format Errors). 7.2.3.2.4 Valid Format Word. When the main processor reads a valid format word from the save CIR during the cpSAVE instruction, it uses the length field to determine the size of the coprocessor state frame to save. The length field in the lower eight bits of a format word is relevant only in a valid format word. During the cpRESTORE instruction, the main processor uses the length field in the format word read from the effective address in the instruction to determine the size of the coprocessor state frame to restore. The length field of a valid format word, representing the size of the coprocessor state frame, must contain a multiple of four. If the main processor detects a value that is not a multiple of four in a length field during the execution of a cpSAVE or cpRESTORE instruction, the main processor writes the abort mask {refer to 7.2.3.2.3 Invalid Format Word) to the control CIR and initiates format error exception processing. 7.2.3.3 COPROCESSOR CONTEXT SAVE INSTRUCTION. The M68000 coprocessor context save instruction category consists of one instruction. The coprocessor context save instruction, denoted by the cpSAVE mnemonic, saves the context of a coprocessor dynamically without relation to the execution of coprocessor instructions in the general or conditional instruction categories. During the execution of a cpSAVE instruction, the coprocessor communicates status information to the main processor by using the coprocessor format codes. 7.2.3.3.1 Format. Figure 7-15 shows the format of the cpSAVE instruction. The first word of the instruction, the F-line operation word, contains the Cp!D code in bits 11-9 and an M68000 effective address code in bits 5-0. The effective address encoded in the cpSAVE instruction is the address at which the state frame associated with the current context of the coprocessor is saved in memory. 16 14 132 9 8 7 6 0 [4 \ | | Cpt \ | 0 | 0 EFFECTIVE ADDRESS EFFECTIVE ADDRESS EXTENSION WORDS (0-5 WORDS} Figure 7-15. Coprocessor Context Save Instruction Format (cpSAVE) The control alterable and predecrement addressing modes are valid for the cpSAVE instruction. Other addressing modes cause the MC68020/EC020 to initiate F-line emulator exception processing as described in 7.5.2.2 F-Line Emulator Exceptions. The instruction can include as many as five effective address extension words following the F-line operation word. These words contain any additional information required to calculate the effective address specified by bits 5-0 of the F-line operation word. 7-20 M68020 USERS MANUAL MOTOROLA7.2.3.3.2 Protocol. Figure 7-16 shows the protocol for the coprocessor context save instruction. The main processor initiates execution of the cpSAVE instruction by reading the save CIA. Thus, the cpSAVE instruction is the only coprocessor instruction that begins by reading from a CIR. Ail other coprocessor instructions write to a CIR to initiate execution of the instruction by the coprocessor. The coprocessor communicates status information associated with the context save operation to the main processor by placing coprocessor format codes in the save CIR. MAIN PROCESSOR COPROCESSOR Mi RECOGNIZE COPROCESSOR INSTRUCTION F-LINE OPERATION WORD M2 READ SAVE CIA TO INITIATE THE cpSAVE INSTRUCTION C1 IF (NOT READY TO BEGIN CONTEXT SAVE OPERATION) DO STEPS 1) AND 2) BELOW M3 iF (FORMAT = NOT READY} 00 STEPS +) AND 2)BELOW -< 1} PLACE NOT READY FORMAT CODE IN SAVE CIR 1) SERVICE PENDING INTERRUPTS 2} SUSPEND OR COMPLETE CURRENT OPERATIONS 2) GO TO M2 C2 PLACE APPROPAIATE FORMAT WORD IN SAVE CIR Ma EVALUATE EFFECTIVE ADDRESS SPECIFIED IN F-LINE OPWORD AND STORE FORMAT WORD AT C3 TRANSFER NUMBER OF BYTES INDICATED IN FORMAT EFFECTIVE ADDRESS WORD THROUGH OPERAND CIR M5 IF (FORMAT = EMPTY) GO TO M; ELSE, TRANSFER NUMBER OF BYTES INDICATED iN FORMAT WORD FROM OPERAND CIR TO EFFECTIVE ADDRESS M PROCEED WITH EXECUTION OF NEXT INSTRUCTION Figure 7-16. Coprocessor Context Save Instruction Protocol If the coprocessor is not ready to suspend its current operation when the main processor reads the save CIR, it returns a not-ready format code. The main processor services any pending interrupts and then reads the save CIR again. After placing the not-ready format code in the save CIR, the coprocessor should either suspend or complete the instruction it is currently executing. Once the coprocessor has suspended or completed the instruction it is executing, it places a format code representing the internal coprocessor state in the save CIR. When the main processor reads the save CIR, it transfers the format word to the effective address specified in the cpSAVE instruction. The lower byte of the coprocessor format word specifies the number of bytes of state information, not including the format word and associated null word, to be transferred from the coprocessor to the effective address specified. If the state information is mot a multiple of four bytes in size, the MC68020/EC020 initiates format error exception processing (refer to 7.5.1.5 Format Errors). The coprocessor and main processor coordinate the transfer of the internal state of the coprocessor using the operand CIR. The MC68020/ECO20 completes the coprocessor context save by repeatedly reading the operand CIR and writing the MOTOROLA M68020 USER'S MANUAL 7-21information obtained into memory until ail the bytes specified in the coprocessor format word have been transferred. Following a cpSAVE instruction, the coprocessor should be in an idle statethal is, not executing any coprocessor instructions. The cpSAVE instruction is a privileged instruction. When the MC68020/EC020 identifies a cpSAVE instruction, it checks the S-bit in the SR to determine whether it is operating at the supervisor privilege level. If the MC68020/EC020 attempts to execute a cpSAVE instruction while at the user privilege level (S-bit in the SR is clear}, it initiates privilege violation exception processing withoul accessing any of the CIRs (refer to 7.5.2.3 Privilege Violations). The MC68020/EC020 initiates format error exception processing if it reads an invalid format word (or a valid format word whose length fieid is not a multiple of four bytes) from the save CIR during the execution of a cpSAVE instruction (refer to 7.2.3.2.3 Invalid Format Word}. The MC68020/EC020 writes an abort mask (refer to 7.2.3.2.3 Invalid Format Word) to the control CIR to abort the coprocessor instruction prior to beginning exception processing. Figure 7-16 does not include this case since a coprocessor usually returns either a not-ready or a valid format code in the context of the cpSAVE instruction. The coprocessor can return the invalid format word, however, if a cpSAVE is initiated while the coprocessor is executing a cpSAVE or cpRESTORE instruction and the coprocessor is unable to support the suspension of these two instructions. 7.2.3.4 COPROCESSOR CONTEXT RESTORE INSTRUCTION. The M68000 coprocessor context restore instruction category includes one instruction. The coprocessor context restore instruction, denoted by the cpRESTORE mnemonic, forces a coprocessor to terminate any current operations and to restore a former state. During execution of a cpRESTORE instruction, the coprocessor can communicate status information to the main processor by placing format codes in the restore CIR. 7.2.3.4.1 Format. Figure 7-17 shows the format of the cpRESTORE instruction. 16 14 iF 12 tt 9 8 7 6 1 | 1 | { | 1 | cold | 1 0 1 EFFECTIVE ADDRESS EFFECTIVE ADDRESS EXTENSION WORDS (0-5 WORDS) Figure 7-17. Coprocessor Context Restore Instruction Format (cpRESTORE) The first word of the instruction, the F-line operation word, contains the CpID code in bits 11-9 and an M68000 effective addressing code in bits 5-0. The effective address encoded in the cpRESTORE instruction is the starting address in memory where the coprocessor context is stored. The effective address is that of the coprocessor format word that applies to the context to be restored to the coprocessor. 7-22 M68020 USER'S MANUAL MOTOROLAThe instruction can include as many as five effective address extension words following the F-iin operation word in the cpRESTORE instruction format. These words contain any additional information required to calculate the effective address specified by bits 5-0 of the F-line operation word. All memory addressing modes except the predecrement addressing mode are valid. Invalid effective address encodings cause the MC68020/EC020 to initiate F-line emulator exception processing (refer to 7.5.2.2 F-Line Emulator Exceptions). 7.2.3.4.2 Protocol. Figure 7-18 shows the protocol for the coprocessor context restore instruction. When the main processor executes a copRESTORE instruction, it first reads the coprocessor format word from the effective address in the instruction. This format word contains a format code and a length field. During cpoRESTORE operation, the main processor retains a copy of the tength field to determine the number of bytes to be transferred to the coprocessor during the coRESTORE operation and writes the format word to the restore CIR to initiate the coprocessor context restore. MAIN PROCESSOR COPROCESSOR Mi RECOGNIZE COPROCESSOR INSTRUCTION F-LINE OPERATION WORD M2 READ COPROCESSOR FORMAT CODE FROM EFFECTIVE ADDRESS SPECIFIED IN OPERATION WORD M3 WRITE COPROCESSOR FORMAT WORD TO RESTORE CIR 3e C1 TERMINATE CURRENT OPERATIONS AND EVALUATE FORMAT WORD M4 READ RESTORE CIR <> C2_sIF (INVAUD FORMAT) PLACE INVALID FORMAT CODE IN THE RESTORE CIR MSIF (FORMAT = INVALID FORMAT} WRITE $0001 ABORT CODE TO CONTROL CIR AND INITIATE FORMAT ERROR EXCEPTION PROCESSING (SEE NOTE 1) C3 IF (VALID FORMAT) RECEIVE NUMBER OF BYTES INDICATEC IN FORMAT WORD THROUGH OPERAND CIR M6 IF (FORMAT = EMPTY/RESET} GO TO M7; ELSE, TRANSFER NUMBER OF BYTES SPECIFIED BY FORMAT WORD TO OPERAND CIR (SEE NOTE 2) M7 PROCEED WITH EXECUTION OF NEXT INSTRUCTION NOTES: 1. Sea 7.6.1.5 Format Error. 2. Tha MC68020/EC020 uses the length field in the format word read during M2 to determine the number of byles to read from memory and write to the operand CIR Figure 7-18. Coprocessor Context Restore Instruction Protocol When the coprocessor receives the format word in the restore CIR, it must terminate any current operations and evaluate the format word. If the format word represents a valid coprocessor context as determined by the coprocessor design, the coprocessor returns the format word to the main processor through the restore CIR and prepares to receive the number of bytes specified in the format word through its operand CIA. MOTOROLA M68020 USER'S MANUAL 7-23After writing the format word to the restore CiR, the main processor continues cpRESTORE dialog by reading that same register. If the coprocessor returns a valid format word, the main processor transfers the number of bytes specified by the format word at the effective address to the operand CIR. If the format word written to the restore CIR does not represent a valid coprocessor state frame, the coprocessor places an invalid format word in the restore CIR and terminates any current operations. The main processor receives the invalid format code. writes an abort mask (refer to 7.2.3.2.3 invalid Format Word) to the control CIR, and initiates format error exception processing (refer to 7.5.1.5 Format Errors). The cpRESTORE instruction is a privileged instruction. When the MC68020/EC020 accesses a cpRESTORE instruction, it checks the S-bit in the SR. If the MC68020/EC020 attempts to execute a coRESTORE instruction while at the user privilege level {S-bit in the SR is clear), it initiates privilege violation exception processing without accessing any of the CIRs (refer to 7.5.2.3 Privilege Violations). 7.3 COPROCESSOR INTERFACE REGISTER SET The instructions of the M68000 coprocessor interface use registers of the CIR set to communicate with the coprocessor. These CIRs are not directly related to the coprocessor programming model. Figure 7-4 is a memory map of the CIR set. The response, control, save, restore, command, condition, and operand registers must be included in a coprocessor interface that implements all four coprocessor instruction categories. The complete register mode! must be implemented if the system uses all coprocessor response primitives defined for the M680C00 coprocessor interface. The following paragraphs contain detailed descriptions of the registers. 7.3.1 Response CIR The coprocessor uses the 16-bit response CIR to communicate all service requests (coprocessor response primitives) to the main processor. The main processor reads the response CIA to recetve the coprocessor response primitives during the execution of instructions in the general and conditional instruction categories. The offset from the base address of the CIR set for the response CIR is $00. Refer to 7.4 Coprocessor Response Primitives for additional information. 7.3.2 Control CIR The main processor writes to the 2-bit control CIR to acknowledge coprocessor-requested exception processing or to abort the execution of a coprocessor instruction. The offset from the base address of the CIR set tor the control CIR is $02. The control CIR occupies the two least significant bits of the word at that offset. The 14 most significant bits of the word are undefined and reserved by Motorola. Figure 7-19 shows the format of this register 7-24 M68020 USER'S MANUAL MOTOROLA[ |] Figure 7-19. Control CIR Format When the MC68020/EC020 receives one of the three take exception coprocessor response primitives, it acknowledges the primitive by setting the exception acknowledge bit (XA) in the control CIR. The MC68020/EC020 sets the abort bit (AB) in the contro! CIR to abort any coprocessor instruction in progress. (The 14 most significant bits of both masks are undefined.) The MC68020/EC020 aborts a coprocessor instruction when it detects one of the following exception conditions: + An F-line emulator exception condition after reading a response primitive > A privilege violation exception as it performs a supervisor check in response to a supervisor check primitive * A format error exception when it receives an invalid format word or a valid format word that contains an invalid length 7.3.3 Save CIR The coprocessor uses the 16-bit save CIR to communicate status and state frame format information to the main processor while executing a cpSAVE instruction. The main processor reads the save CIR to initiate execution of the cpSAVE instruction by the coprocessor. The offset from the base address of the CIR set for the save CIR is $04. Refer to 7.2.3.2 Coprocessor Format Words for more information on the save CIR. 7.3.4 Restore CIR The main processor initiates the coRESTORE instruction by writing a coprocessor format word to the 16-bit restore register. During the execution of the copRESTORE instruction, the coprocessor communicates status and state frame format information to the main processor through the restore CIR. The offset from the base address of the CIR set for the restore CIR is $06. Refer to 7.2.3.2 Coprocessor Format Words for more information on the restore CIR. 7.3.5 Operation Word CIR The main processor writes the F-line operation word of the instruction in progress to the 16-bit operation word CIR in response to a transfer operation word coprocessor response primitive (refer to 7.4.6 Transfer Operation Word Primitive). The offset from the base address of the CIR set for the operation ward CIR is $08. 7.3.6 Command CIR The main processor initiates a coprocessor general category instruction by writing the instruction command word, which follows the instruction F-line operation word in the instruction stream, to the 16-bit command CIR. The offset from the base address of the CIR set for the command CIR is $0A. MOTOROLA M68020 USER'S MANUAL 7-257.3.7 Condition CIR The main processor initiates a conditional category instruction by writing the condition selector to bits 5-0 of the 16-bit condition CIR. Bits 15-6 are undefined and reserved by Motorola. The offset from the base address of the CIR set for the condition CIR is $0E. Figure 7-20 shows the format of the condition CIA. 15 6 0 | UNDEFINED, RESERVED | CONDITION SELECTOR | Figure 7-20. Condition CIR Format 7.3.8 Operand CIR When the coprocessor requests the transfer of an operand, the main processor performs the transfer by reading from or writing to the 32-bit operand CIR. The offset from the base address of the CIR set for the operand CIR is $10. The MC68020/EC020 aligns all operands transferred to and from the operand CIR to the most significant byte of this CIR. The processor performs a sequence of long-word transfers to read or write any operand larger than four bytes. If the operand size is not a multipte of four bytes, the portion remaining after the initial long-word transfer is aligned to the most significant byte of the operand CIR. Figure 7-21 shows the operand alignment used by the MC68020/EC020 when accessing the operand CIR. a1 24 23 16 15 87 0 | BYTE OPERAND | NO TRANSFER ] | WORD OPERAND NO TRANSFER | | THREE-BYTE OPERAND NO TRANSFER | LONG.WORD OPERAND | TEN: BYTE- OPERAND NO TRANSFER Figure 7-21, Operand Alignment for Operand CIR Accesses 7-26 M68020 USER'S MANUAL MOTOROLA7.3.9 Register Select CIR When the coprocessor requests the transfer of one or more main processor registers or a group of coprocessor registers, the main processor reads the 16-bit register select CIR to identify the number or type of registers to be transferred. The offset from the base address of the CIR set for the register select CIR is $14. The format of this register depends on the primitive that is currently using it (refer to 7.4 Coprocessor Response Primitives). 7.3.10 Instruction Address CIR When the coprocessor requests the address of the instruction it is currently executing, the main processor transfers this address to the 32-bit instruction address CIR. Any transfer of the scanPC is aiso performed through the instruction address CIR (refer to 7.4.17 Transfer Status Register and ScanPC Primitive). The offset from the base address of the CIR set for the instruction address CIR is $18. 7.3.11 Operand Address CIR When a coprocessor requests an operand address transfer between the main processor and the coprocessor, the address is transferred through the 32-bit operand address CIR. The offset from the base address of the CIR set for the operand address CIR is $1C. 7.4 COPROCESSOR RESPONSE PRIMITIVES The response primitives are primitive instructions that the coprocessor issues to the main processor during the execution of a coprocessor instruction. The coprocessor uses response primitives to communicate status information and service requests to the main processor. In response to an instruction command word written to the command CIR or a condition selector in the condition CIR, the coprocessor returns a response primitive in the response CIR. Within the general and conditional instruction categories, individual instructions are distinguished by the operation of the coprocessor hardware and by services specified by coprocessor response primitives and provided by the main processor. Subsequent paragraphs, beginning with 7.4.2 Coprocessor Response Primitive General Format, consist of detailed descriptions of the M68000 coprocessor response primitives supported by the MC68020/EC020. Any response primitive that the MC68020/ECO20 does not recognize causes it to initiate protocol violation exception processing (refer to 7.5.2.1 Protocol Violations). This processing of undefined primitives supports emulation of extensions to the M68000 coprocessor response primitive set by the protocol violation exception handler. Exception processing related to the coprocessor interface is discussed in 7.5 Exceptions. MOTOROLA M68020 USER'S MANUAL 7277.4.1 ScanPC Severat of the response primitives involve the scanPC, and many of them require the main processor to use it while performing services requested. These Paragraphs describe the scanPC and tts operation. During the execution of a coprocessor instruction, the PC in the MC68020/EC020 contains the address of the F-line operation word of that instruction. A second register, called the scanPC, sequentially addresses the remaining words of the instruction. If the main processor requires extension words to calculate an effective address or destination address of a branch operation, it uses the scanPC to address these extension words in the instruction stream. Aliso, if a coprocessor requests the transfer of extension words, the scanPC addresses the extension words during the transfer. As the processor references each word, it increments the scanPC to point to the next word in the instruction stream. When an instruction has compieted, the processor transfers the value in the scanPC to the PC to address the operation word of the next instruction. The value in the scanPC when the main processor reads the first response primitive after beginning to execute an instruction depends on the instruction being executed. For a cpGEN instruction, the scanPC paints to the word following the coprocessor command word. For the cpBec instructions, the scanPC points to the word following the instruction F-line operation word. For the coScc, cpTRAPcc, and cpDBcc instructions, the scanPC points to the word following the coprocessor condition specifier word. if a coprocessor implementation uses optional instruction extension words with a general or conditional instruction, the coprocessor must use these words consistently so that the scanPC is updated accordingly during the instruction execution. Specifically, during the execution of general category instructions, when the coprocessor terminates the instruction protocol, the MC68020/EC020 assumes that the scanPC is pointing to the operation word of the next instruction to be executed. During the execution of conditional category instructions, when the coprocessor terminates the instruction protocol, the MC68020/EC020 assumes that the scanPC is pointing to the word following the last of any coprocessor-defined extension words in the instruction format. 7.4.2 Coprocessor Response Primitive General Format The M68000 coprocessor response primitives are encoded in a 16-bit word that is transferred to the main processor through the response CIR. Figure 7-22 shows the format of the coprocessor response primitives. 15 14 3 12 8 ? 0 | CA | PC | 0A FUNCTION | PARAMETER | Figure 7-22. Coprocessor Response Primitive Format 7-28 M68020 USER'S MANUAL MOTOROLAThe encoding of bits 12-0 of a coprocessor response primitive depends on the individual primitive. Bits 15-13, however, specify optional additional operations that apply to most of the primitives defined for the M68000 coprocessor interface. The CA bit specifies the come-again operation of the main processor. When the main processor reads a response primitive from the response CIR with the CA bit set, it performs the service indicated by the primitive and then reads the response CIR again, Using the CA bit, a coprocessor can transfer several response primitives to the main processor during the execution of a single coprocessor instruction. The PC bit specifies the pass program counter operation. When the main processor reads a primitive with the PC bit set from the response CIR, the main processor immediately passes the current value in its program counter to the instruction address CIR as the first operation in servicing the primitive request. The value in the program counter is the address of the F-line operation word of the coprocessor instruction currently executing. The PC bit is implemented in all coprocessor response primitives currently defined for the M68000 coprocessor interface. When an undefined primitive or a primitive that requests an illegal operation is passed to the main processor, the main processor initiates exception processing for either an F-line emulator or a protocol violation exception (refer to 7.5.2 Main-Processor-Detected Exceptions). If the PC bit is set in one of these response primitives, however, the main processor passes the program counter to the instruction address CIR before it initiates exception processing. When the main processor initiates a cpGEN instruction that can be executed concurrently with main processor instructions, the PC bit is usually set in the first primitive returned by the coprocessor. Since the main processor proceeds with instruction stream execution once the coprocessor releases it, the coprocessor must record the instruction address to support any possible exception processing related to the instruction. Exception processing related to concurrent coprocessor instruction execution is discussed in 7.5.1 Coprocessor-Detected Exceptions. The DR bit 1s the direction bit. It applies to operand transfers between the main processor and the coprocessor. If the OR bit is clear, the direction of transfer is fram the main processor to the coprocessor (main processor write). If the DR bit is set, the direction of transfer is from the coprocessor to the main processor (main processor read). If the operation indicated by a given response primitive does not involve an explicit operand transfer, the value of this bit depends on the particular primitive encoding. MOTOROLA M68020 USER'S MANUAL 7-297.4.3 Busy Primitive The busy response primitive causes the main processor to retnitiate a coprocessor instruction. This primitive applies to instructions in the general and conditional categories. Figure 7-23 shows the format of the busy primitive. 15 14 13 12 i 1 6 7 Otel bop pelepepafep pep Tepe] Figure 7-23. Busy Primitive Format The busy primitive uses the PC bit as described in 7.4.2 Coprocessor Response Primitive General Format. Coprocessors that can operate concurrently with the main processor but cannot buffer write operations to their command or condition CIR use the busy primitive. A coprocessor may execute a cpGEN instruction concurrently with an instruction in the main processor. If the main processor attempts to initiate an instruction in the general or conditional instruction category while the coprocessor is executing a CpGEN instruction, the coprocessor can place the busy primitive in the response CIR. When the main processor reads this primitive, it services pending interrupts using a preinstruction exception stack frame (refer to Figure 7-41). The processor then restarts the general or conditional coprocessor instruction that it had attempted to initiate earlier. The busy primitive should only be used in response to a write to the command or condition CIR. It should be the first primitive returned after the main processor attempts to initiate a general or conditional category instruction. In particular, the busy primitive should not be issued after program-visible resources have been altered by the instruction. (Program- visible resources include coprocessor and main processor program-visible registers and operands in memory, but not the scanPC.) The restart of an instruction after it has altered program-visible resources causes those resources to have inconsistent values when the processor reinitiates the instruction. The MC68020/EC020 responds to the busy primitive differently in a special case that can occur during a breakpoint operation (refer to Section 6 Exception Processing). This special case occurs when a breakpoint acknowledge cycle initiates a coprocessor F-line instruction, the coprocessor returns the busy primitive in response to the instruction initiation, and an interrupt is pending. When these three conditions are met, the processor reexecutes the breakpoint acknowledge cycle after completion of interrupt exception processing. A design that uses a breakpoint to monitor the number of passes through a loop by incrementing or decrementing a counter may not work correctly under these conditions. This special case may cause several breakpoint acknowledge cycles to be executed during a single pass through a loop. 7-30 M68020 USER'S MANUAL MOTOROLA7.4.4 Null Primitive The null caprocessar respo ise primitive communicates coprocessor status information to the main processor. This primitive applies to instructions in the general and conditional categories. Figure 7-24 shows the format of the null primitive. rate fo[e[+ pele [apap] ole le ]e]ee) Figure 7-24. Null Primitive Format The null primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response Primitive General Format. The IA bit specifies the interrupts allowed optional operation. This bit determines whether the MC68020/EC020 services pending interrupts prior to rereading the response CIR after receiving a null primitive. interrupts are allowed when the JA bit is set. The PF bit shows the processing-finished status of the coprocessor. That is, PF = 1 indicates that the coprocessor has completed all processing associated with an instruction. The TF bit indicates the true/false condition during execution of a conditional category instruction. TF = 1 is the true condition specifier; TF = 0 is the false condition specifier. The TF bit is only relevant for null primitives with CA = 0 that are used by the coprocessor during the execution of a conditional instruction. The MC68020/EC020 processes a null primitive with CA = 1 in the same manner whether executing a general or conditional category coprocessor instruction. If the coprocessor sets CA and IA in the aull primitive, the main processor services pending interrupts using a midinstruction stack frame (refer to Figure 7-43) and reads the response CIR again. If the coprocessor sets CA and clears IA in the null primitive, the main processor reacs the response CIR again without servicing any pending interrupts. A null primitive with CA = 0 provides a condition evaluation indicator to the main processor during the execution of a conditional instruction and ends the diafogue between the main processor and coprocessor for that instruction. The main processor completes the execution of a conditional category coprocessor instruction when it receives the primitive, The PF bit is not relevant during conditional instruction execution since the primitive itself implies completion of processing. Usually, when the main processor reads any primitive that does not have CA = 1 while executing a general category instruction, it terminates the dialogue between the main processor and coprocessor. If a trace exception is pending, however, the main processor does not terminate the instruction dialogue until it reads a null primitive with CA = 0 and PF = 1 from the response CIR (refer to 7.5.2.5 Trace Exceptions), Thus, the main processor continues to read the response CiR until it receives a null primitive with CA = 0 MOTOROLA M68020 USER'S MANUAL 7-34and PF = 1, and then performs trace exception processing. When IA = 1. the main processor services pending interrupts before reading the response CIR again. A coprocessor can be designed to execute a cpGEN instruction concurrently with the execution of main processor instructions and, also, buffer one write operation to either its command or condition CIR. This type of coprocessor issues a null primitive with CA = 1 when it is concurrently executing a coGEN instruction, and the main processor initiates another general or conditional coprocessor instruction. This primitive indicates that the coprocessor is busy and the main processor should read the response CIR again without reinitiating the instruction. The IA bit of this null primitive usually should be set to minimize interrupt latency while the main processor is waiting for the coprocessor to complete the general category instruction. Table 7-3 summarizes the encodings of the null primitive. Table 7-3. Null Coprocessor Response Primitive Encodings CA | PC} IA | PFI TF Genera! Instructions Conditional Instructions x 1 x x x | Pass Program Counter to Instruction Same as General Category Address CIR, Clear PC Bit, and Proceed with Operation Specified by CA, IA, PF, and TF Bits 1 0 0 x x | Reread Response CtR, Do Not Service Same as General Category Pending Interrupts 1 0 1 X x | Service Pending Interrupts and Reread the Same as General Category Response CIR 0 0 o 0 lf (Trace Pending) Reread Response CIR: Main Processor Completes Instruction Else, Execute Next Instruction Execution Based on TF ac 0 0 1 0 c [If (Trace Pending) Service Pending Main Processor Completes tnstruction Interrupts and Reread Response CIR; Execution Based on TF =c Else, Execute Nex! Instruction 0 0 x 1 c | Coprocesser Instruction Completed: Main Processor Completes Instruction Service Pending Exceptions or Execute Executian Based on TF = c. Next Instruction x = Don't Care c = 1 or 0 Depending on Coprocessor Candition Evaluation M68020 USER'S MANUAL MOTOROLA7.4.5 Supervisor Check Primitive The supervisor check primitive verifies that the main processor is operating in the supervisor privilege level while executing a coprocessor instruction. This primitive applies to instructions in the general and conditional coprocessor instruction categories. Figure 7-25 shows the format of the supervisor check primitive. 15 14 13 12 it 10 9 8 7 Go Stef feleD [eleL] Le] spolepey | Figure 7-25. Supervisor Check Primitive Format The supervisor check primitive uses the PC bit as described in 7.4.2 Coprocessor Response Primitive General Format. Bit 15 is shown as one, but during execution of a general category instruction, this primitive performs the same operations, regardless of the value of bit 15. However, if this primitive is issued with bit 15 = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. When the MC68020/EC020 reads the supervisor check primitive from the response CIR, it checks the value of the S-bit in the SR. If S = 0 (main processor operating at user privilege level}, the main processor aborts the coprocessor instruction by writing an abort mask to the control CiR (refer to 7.3.2 Control CIR). The main processor then initiates privilege violation exception processing (refer to 7.5.2.3 Privilege Violations). !f the main processor is at the supervisor privilege level when it receives this primitive, it reads the response CIR again. The supervisor check primitive allows privileged instructions to be defined in the coprocessor general and conditional instruction categories. This primitive should be the first one issued by the coprocessor during the dialog for an instruction that is implemented as privileged. 7.4.6 Transfer Operation Word Primitive The transfer operation word primitive requests a copy of the coprocessor instruction operation word for the coprocessor. This primitive applies to general and conditional category instructions. Figure 7-26 shows the format of the transfer operation word primitive. 15 14 13 12 W 10 9 8 7 6 5 4 3 2 1 fatefefefe[ [ifs pep etep ]opote] Figure 7-26. Transfer Operation Word Primitive Format MOTOROLA M68020 USER'S MANUAL 7-33The transfer operation word primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response Primitive General Format. If this primitive is issued with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. When the main processor reads this primitive from the response CIR, it transfers the F-lin operation word of the currently executing coprocessor instruction to the operation word CIR. The value of the scanPC is not affected by this primitive. 7.4.7 Transfer from Instruction Stream Primitive The transfer from instruction stream primitive initiates transfers of operands fram the instruction stream to the coprocessor. This primitive applies to general and conditional category instructions. Figure 7-27 shows the format of the transfer from instruction stream primitive, 1 14 13 12 11 10 9 8 7 0 peatecfofof+fifi]|s | LENGTH Figure 7-27. Transfer from Instruction Stream Primitive Format The transfer from instruction stream primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response Primitive General Format. If this primitive is issued with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. The length field of this primitive specifies the length, in bytes, of the operand to be transferred from the instruction stream to the coprocessor. The length must be an even number of bytes. If an odd length is specified, the main processor initiates protocol violation exception processing (refer to 7.5.2.1 Protocol Violations) This primitive transfers coprocessor-defined extension words to the coprocessor. When the main processor reads this primitive from the response CIR, it copies the number of bytes indicated by the length field from the instruction stream to the operand CIR. The first word or long word transferred is at the location pointed to by the scanPC when the primitive is read by the main processor. The scanPC is incremented after each word or long word is transferred. When execution of the primitive has completed, the scanPC has been incremented by the total number of bytes transferred and points to the word following the last word transferred. The main processor transfers the operands from the instruction stream, using a sequence of long-word writes, to the operand CIR. If the length freld ts not an even multiple of four bytes, the last two bytes from the instruction stream are transferred using a word write to the operand CIR. 7-34 M68020 USERS MANUAL MOTOROLA7.4.8 Evaluate and Transfer Effective Address Primitive The evaluate and transfer effective address primitive evaluates the effective address specified in the coprocessor instruction operation word and transfers the result to the coprocessor. This primitive applies to general category instructions. If this primitive is issued by the coprocessor during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 7-28 shows the format of the evaluate and transfer effective address primitive. CaleloTe[ [Te] Te]elelepelepe pepe] Figure 7-28. Evaluate and Transfer Effective Address Primitive Format The evaluate and transfer effective address primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response Primitive General Format. When the main processor reads this primitive while executing a general category instruction, it evaluates the effective address specified in the instruction. At this point, the scanPC contains the address of the first of any required effective address extension words. The main processor increments the scanPC by two after it references each of these extension words. After the effective address is calculated, the resulting 32-bit value is written to the operand address CIR. The MC68020/EG020 only calculates effective addresses for control alterable addressing modes in response to this primitive. tf the addressing mode in the operation word is not a control alterable mode, the main processor aborts the instruction by writing a $0001 to the control CIR and initiates F-line emulation exception processing (refer to 7.5.2.2 F-Line Emulator Exceptions). 7.4.9 Evaluate Effective Address and Transfer Data Primitive The evaluate effective address and transfer data primitive transfers an operand between the coprocessor and the effective address specified in the coprocessor instruction operation word. This primitive applies to general category instructions. If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 7-29 shows the format of the evaluate effective address and transfer data primitive. 15 14 13 l2 11 10 8 ? 0 | calrc[or[ 1] o | VALID EA LENGTH | Figure 7-29. Evaluate Effective Address and Transfer Data Primitive Format This primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. MOTOROLA M68020 USER'S MANUAL 7-35The valid EA fletd of the primitive format specifies the valid effective address categories for this primitive. If the effective address specified in the instruction operation word is not a member of the class specified by the valid EA field, the main processor aborts the coprocessor instruction by writing an abort mask to the control CIR (refer to 7.3.2 Controi CIR) and by initiating F-line emulation exception processing. Table 7-4 lists the valid effective address field encodings. Table 7-4. Valid Effective Address Field Codes Field Category 000 Control Alterable 001 Data Alterable 010 Memory Alterable O11 Alterable 100 Control 101 Data 110 Memory 111 Any Effective Address (No Restriction} Even when the valid EA fields specified in the primitive and in the instruction operation word match, the MC68020/EC020 initiates protocol violation exception processing if the primitive requests a write to an unalterable effective address. The length in bytes of the operand to be transferred is specified by the length field of the primitive format. Several restrictions apply to operand lengths for certain effective addressing modes. If the effective address is a main processor register (register direct mode), only operand lengths of one, two, or four bytes are valid; all other lengths cause the main processor to initiate protocoi violation exception processing. Operand Sengths of 0-255 bytes are valid for the memory addressing modes. The length of 0-255 bytes does not apply to an immediate operand. The length of an immediate operand must be one byte or an even number of bytes (less than 256), and the direction of transfer must be to the coprocessor; otherwise, the main processor initiates protocol violation exception processing. When the main processor receives the evaluate effective address and transfer data primitive during the execution of a general category instruction, it verifies that the effective address encoded in the instruction operation word is in the category specified by the primitive. If so, the processor calculates the effective address using the appropriate effective address extension words at the current scanPC address and increments the scanPC by two for each word referenced. Using long-word transfers whenever possible, the main processor then transfers the number of bytes specified in the primitive between the cperand CIR and the effective address. Refer to 7.3.8 Operand CIR for information concerning operand alignment for transfers involving the operand CIR. 7-36 M68020 USERS MANUAL MOTOROLAThe DR bit specifies the direction of the operand transfer. DR = 0 requests a transfer from the main processor to the coprocessor, and DR = 1 specifies a transfer from the coprocessor to the main processor. If the effective addressing mode specifies the predecrement mode, the address register used is decremented by the size of the operand before the transfer. The bytes within the operand are then transferred to or from ascending addresses beginning with the location specified by the decremented address register. In this mode, if A7 is used as the address register and the operand length ts one byte, A7 is decremented by two to maintain a word- aligned stack. For the postincrement effective addressing mode, the address register used is incremented by the size of the operand after the transfer. The bytes within the operand are transferred to or from ascending addresses beginning with the location specified by the address register. In this mode, if A7 is used as the address register and the operand length is one byte, A7 is incremented by two after the transfer to maintain a word-aligned stack. Transferring odd length operands longer than one byte using the (A7) or (A7)+ addressing modes can result in a stack pointer that is not word aligned. The processor repeats the effective address calculation each time this primitive is issued during the execution of a given instruction. The calculation uses the current contents of any required address and data registers. The instruction must include a set of effective address extension words for each repetition of a calculation that requires them. The processor locates these words at the current scanPC location and increments the scanPC by two for each word referenced in the instruction stream. The MC68020/EC020 sign-extends a byte or word-sized operand to a long-word value when it is transferred to an address register (A7-A0) using this primitive with the register direct effective addressing mode. A byte or word-sized operand transferred to a data register (D7DO) only overwrites the lower byte or word of the data register. 7.4.10 Write to Previously Evaluated Effective Address Primitive The write to previously evaluated effective address primitive transfers an operand from the coprocessor to a previously evaluated effective address. This primitive applies to general category instructions. If the coprocessor uses this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 7-30 shows the format of the write to previously evaluated effective address primitive. 15 44 13 12 +B] 19 q 6 7 | cafec| 1 ]ofofofolo | LENGTH Figure 7-30. Write to Previously Evaluated Effective Address Primitive Format MOTOROLA M68020 USER'S MANUAL 7-37The write to previously evaluated effective address primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response Primitive General Format. The length field of the primitive format specifies the length of the operand in bytes. The MC68020/EC020 transfers operands of 0-255 bytes in length. When the main processor receives this primitive during the execution of a general category instruction, it transfers an operand from the operand CIR to an effective address specified by a temporary register within the MC68020/EC020. When a previous primitive for the Current instruction has evaluated the effective address, this temporary register contains the evaluated effective address. Primitives that store an evaluated effective address in a temporary register of the main processor are the evaluate and transter effective address, evaluate effective address and transfer data, and transfer multiple coprocessor registers primitive. If this primitive is used during an instruction in which the effective address specified in the instruction operation word has not been calculated, the effective address used for the write is undefined. Also, if the previously evaluated effective address was register direct, the address written to in response to this primitive is undefined. The function code value during the write operation indicates either supervisor or user cata space, depending on the value of the S-bit in the MC68020/EC020 SR when the processor reads this primitive. While a coprocessor should request writes to only alterable effective addressing modes, the MC68020/EC020 does not check the type of effective address used with this primitive. For exampie, if the previously evaluated effective address was PC relative and the MC68020/EC020 is at the user privilege level (S = 0 in SR), the MC68020/EC020 writes to user data space at the previously catculated program relative address (the 32-bit value in the temporary internal register of the processor} Operands longer than four bytes are transferred in increments of four bytes (operand parts) when possible. The main processor reads a long-word operand part from the operand CiR and transfers this part to the current effective address. The transfers continue in this manner using ascending memory locations until all of the long-word operand parts are transferred, and any remaining operand part is then transferred using a one-, two-, or three-byte transfer as required. The operand parts are stored in memory using ascending addresses beginning with the address in the MC68020/EC020 temporary register, which is internal to the processor and not for user use. The execution of this primitive does not modify any of the registers in the MC68020/EC020 programming model, even if the previously evaluated effective address mode is the predecrement or postincrement mode. If the previously evaluated effective adcressing mode used any of the MC68020/EC020 internal address or data registers, the effective address value used is the final value from the preceding primitive. That is, this primitive uses the value from an evaluate and transfer effective address, evaluate effective address and transfer data, or transfer mu'tiple coprocessor registers primitive without modification 7-38 M68020 USER'S MANUAL MOTOROLAThe take address and transfer data primitive described in 7.4.11 Take Address and Transfer Data Primitive does not replace the effective address value that has been calculated by the MC68020/EC020. The address that the main processor obtains in response to the take address and transfer data primitive is no! available to the write to previously evaluated effective address primitive. A coprocessor can issue an evaluate effective address and transfer data primitive followed by this primitive to perform a read-modify-write operation that is not indivisible. The bus cycles for this operation are normal bus cycles that can be interrupted, and the bus can be arbitrated between the cycles. 7.4.11 Take Address and Transfer Data Primitive The take address and transfer data primitive transfers an operand between the coprocessor and an address supplied by the coprocessor. This primitive applies to general and conditional category instructions. Figure 7-31 shows the format of the take address and transfer data primitive. ee Se 0 [cal pc} or{ of| o [+ ]o |]: | LENGTH | Figure 7-31. Take Address and Transfer Data Primitive Format The take address and transfer data primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this primitive with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. The length field of the primitive format specifies the operand length, which can be from 0~255 bytes. The main processor reads a 32-bit address from the operand address CIR. Using a series of long-word transfers, the processor transfers the operand between this address and the operand CIR. The DR bit determines the direction of the transfer. The processor reads or writes the operand parts to ascending addresses, starting at the address from the operand address CIR. If the operand length ts not a multiple of four bytes, the final operand part is transferred using a one-, two-, or three-byte transfer as required. The function code used with the address read from the operand address CIR indicates either supervisor or user data space according to the value of the S-bit in the MC68020/EC020 SR. MOTOROLA M68020 USERS MANUAL 7-397.4.12 Transfer to/from Top of Stack Primitive The transfer to/from top of stack primitive transfers an operand between the coprocessor and the top of the active system stack of the main processor. This primitive applies to general and conditional category instructions. Figure 7-32 shows the format of the transfer to/from top of stack primitive. 1 4 12 12 tf 1 9 9g 7 0 Lea{rcj{o][o]f:]s1]fifo] LENGTH | Figure 7-32. Transfer to/from Top of Stack Primitive Format The transfer to/from top of stack primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this primitive with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. The fength field of the primitive format specifies the length in bytes of the operand to be transferred. The operand may be one, two, or four bytes in length; other length values cause the main processor to initiate protocol violation exception processing. lf DR = 0, the main processor transfers the operand from the active system stack to the operand CIR. The implied effective address mode used for the transfer is the (A7)+ addressing mode. A one-byte operand causes the stack pointer to be incremented by two after the transfer to maintain word alignment of the stack. If DR = 1, the main processor transfers the operand from the operand CIR to the active system stack. The implied effective address mode used for the transfer is the ~(A7) addressing mode. A one-byte operand causes the stack pointer to be decremented by two before the transfer to maintain word alignment of the stack. 7.4.13 Transfer Single Main Processor Register Primitive The transfer single main processor register primitive transfers an operand between one of the main processor's data or address registers and the coprocessor. This primitive applies to general and conditional category instructions. Figure 7-33 shows the format of the transfer single main processor register primitive. 1 14 18 2 BGG Gl 0 Lcafector} of: [i fofofofo fol] o | onl REGISTER | Figure 7-33. Transfer Single Main Processor Register Primitive Format The transfer single main processor register primitive uses the CA. PC, and DA bits as described in 7.4.2 Coprocessor Response Primitive General Format. lf the coprocessor issues this primitive with CA = 0 during a conditional category instruction, the main processor tnitiates protocol violation exception processing. 7-40 M68020 USER'S MANUAL MOTOROLAThe D/A bit specifies whether the primitive transfers an address or data register. D/A = 0 indicates a data register, and D/A = 1 indicates an address register. The register field contains the register number. if DR = 0, the main processor writes the long-word operand in the specified register to the operand CIR. If DR = 1, the main processor reads a long-word operand from the operand CIR and transfers it to the specified data or address register. 7.4.14 Transfer Main Processor Control Register Primitive The transfer main processor control register primitive transfers a long-word operand between one of its control registers and the coprocessor. This primitive applies to general and conditional category instructions. Figure 7-34 shows the format of the transfer main processor control register primitive. 1 4 3 12 1 9 8 F 6 & 3 2 41 4g Lcafecfor{o]sfsfof[ifofo]fo]foflelofofo] Figure 7-34. Transfer Main Processor Control Register Primitive Format The transfer main processor control register primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this primitive with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. When the main processor receives this primitive, it reads a control register select code from the register select CIR. This code determines which main processor contro! register is transferred. Table 7-5 lists the valid control register select codes. If the control register select code is not valid, the MC68020/EC020 initiates protocol violation exception processing (refer to 7.5.2.1 Protocol Violations). Table 7-5. Main Processor Control Register Select Codes Select Code Control Register $x000 SFC $x001 DFC $x002 CACR $x800 USP $x801 VBR $x802 CAAR $x803 MSP $x804 ISP All other codes cause a protocol violation exception. MOTOROLA M68020 USERS MANUAL 7-41After reading a valid code from the register select CIA, if DR = 0, the main processor writes the long-word operand from the specified control register to the operand CIR. If DR = 1, the main processor reads a long-word operand from the operand CIR and places it in the specified control register. 7.4.15 Transfer Multiple Main Processor Registers Primitive The transfer multiple main processor registers primitive transfers long-word operands between one or more of its data or address registers and the coprocessor. This primitive applies to general and conditional category instructions. Figure 7-35 shows the format of the transfer multiple main processor registers primitive. CTebePele[e] opel Tr] 5 4 #19 2 O49 [ ca} ec | on | o | o | 1 Figure 7-35. Transfer Multiple Main Processor Registers Primitive Format The transfer multiple main processor registers primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues this primitive with CA = 0 during a conditional category instruction, the main processor initiates protocol violation exception processing. When the main processor receives this primitive, it reads a 16-bit register select mask from the register select CIR. The format of the register select mask is shown in Figure 7-36. A register is transferred if the bit corresponding to the register in the register select mask is set. The selected registers are transferred in the order D7DO and then A7-A0. CE A La Las [as [oe [os |e Pa] [ov] os [os [oe [os | ce] ov] oo | Figure 7-36. Register Select Mask Format If DR = 0, the main processor writes the contents of each register indicated in the register select mask to the operand CIR using a sequence of long-word transfers. If DR = 1, the main processor reads a long-word operand from the operand CIR into each register indicated in the register select mask. The registers are transferred in the same order, regardless of the direction of transfer indicated by the DR bit. 7.4.16 Transfer Multiple Coprocessor Registers Primitive The transfer multiple coprocessor registers primitive transfers trom 0-16 operands between the effective address specified in the coprocessor instruction and the coprocessor. This primitive applies to general category instructions. If the coprocessor issues thts primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception processing. Figure 7-37 shows the format of the transfer multiple coprocessor registers primitive. 7-42 M68020 USER'S MANUAL MOTOROLA15 14 13 12 4 10 7 0 alre[o[efepfofe]r] LENGTH | Figure 7-37. Transfer Multiple Coprocessor Registers Primitive Format The transfer multiple coprocessor registers primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format. The length field of the primitive format indicates the length in bytes of each operand transferred. The operand length must be an even number of bytes; odd length operands cause the MC68020/EC020 to initiate protocol violation exception processing (refer to 7.5.2.1 Protocol Violations). When the main processor reads this primitive, it calculates the effective address specified in the coprocessor instruction. The scanPC should be pointing to the first of any necessary effective address extension words when this primitive is read from the respanse CIR; the scanPC is incremented by two for each extension word referenced during the effective address calculation. For transfers from the effective address to the coprocessor (DR = 0), the control addressing modes and the postincrement addressing mode are valid. For transfers from the coprocessor to the effective address (DR = 1), the control alterable and predecrement addressing modes are valid. Invalid addressing modes cause the MC68020/EC020 to abort the instruction by writing an abort mask to the cantro!l CiR (refer to 7.3.2 Control CIR) and to initiate F-line emulator exception processing (refer to 7.5.2.2 F-Line Emulator Exceptions). After performing the effective address calculation, the MC68020/EC020 reads a 16-bit register select mask from the register select CIR. The coprocessor uses the register select mask to specify the number of operands to transfer; the MC68020/EC020 counts the number of ones in the register select mask to determine the number of operands. The order of the ones in the register select mask is not relevant to the operation of the main processor. As many as 16 operands can be transferred by the main processor in response to this primitive. The total number of bytes transferred is the product of the number of operands transferred and the length of each operand specified in the length field of the primitive format. if DR = 1, the main processor reads the number of operands specified tn the register select mask from the operand CIR and writes these operands to the effective address specified in the instruction using long-word transfers whenever possible. If DR = 0, the main processor reads the number of operands specified in the register select mask from the effective address and writes them to the operand CIR. For the control addressing modes, the operands are transferred to or from memory using ascending addresses. For the postincrement addressing mode, the operands are read from memory with ascending addresses also, and the address register used is incremented by the size of an operand after each operand is transferred. The address register used with the (An)+ addressing mode is incremented by the total number of bytes transferred during the primitive execution. MOTOROLA M68020 USER'S MANUAL 7-43For the predecrement addressing mode, the operands are written to memory with descending addresses, but the bytes within each operand are written to memory with ascending addresses. As an example, Figure 7-38 shows the format in long-word- oriented memory for two 12-byte operands transferred from the coprocessor to the effective address using the -{An) addressing mode. The processor decrements the address register by the size of an operand before the operand is transferred. It writes the bytes of the operand to ascending memory addresses, When the transfer is complete, the address register has been decremented by the total number of bytes transferred. The MC68020/EC020 transfers the data using long-word transfers whenever possible. xh 2424 16 15 8 7 0 An-2*LENGTH ' : } ~~ 4 > OP1, BYTE (0 ' : = FINAL An eh t ' t 1 ' d 1 ! i: t \ An -LENGTH m4 OPO, BYTE (0) ( ' OP1, BYTE (L- 1} ' i i 1 i 1 1 ! ! ' , 4 I i I T T T 4 ' 1 ! OPO, BYTE (L- 1} INITIAL An 1 NOTE: OPO, Byte (0) is the first byte written to memory OPO, Byte (L-1) is the fast byte of the first operand written to memory OP1, Byte {0} is the first byte of the second operand wiitten to memory OP 1, Byte (L1) is the last byte written to memory Figure 7-38. Operand Format in Memory for Transfer to ~(An) 7.4.17 Transfer Status Register and ScanPC Primitive The transfer status register and the scanPC primitive transfers values between the coprocessor and the MC68020/EC020 SR. On an optional basis, the scanPC also makes transfers. This primitive applies to general category instructions. If the coprocessor issues this primitive during the execution of a conditional category instruction, the main processor initiates protocol violation exception Processing. Figure 7-39 shows the format of the transfer status register and scanPC primitive. fe DeTe le Pete Delete Dey eye Figure 7-39. Transfer Status Register and ScanPC Primitive Format The transfer status register and scanPC Primitive uses the CA, PC, and DR bits as described in 7.4.2 Coprocessor Response Primitive General Format The SP bit selects the scanPC option, If SP = 1, the primitive transfers both the scanPC and SR. If SP = 0, only the SR is transferred 7-44 M68020 USER'S MANUAL MOTOROLA{{ SP = 0 and DR = 0, the main processor writes the 16-bit SR value to the operand CIR. If SP = 0 and DR = 1, the main processor reads a 16-bit value from the operand CIR into the main processor SR. If SP = 1 and DR = QO, the main processor writes the long-word value in the scanPC to the instruction address C!R and then writes the SR value to the operand CIR. lf SP = 1 and DR = 1, the main processor reads a 16-bit value from the operand CIR into the SR and then reads a long-word value from the instruction address CIR into the scanPC. With this primitive, a general category instruction can change the main processor program flow by placing a new value in the SR, in the scanPC, or new values in both the SR and the scanPC. By accessing the SR, the coprocessor can determine and manipulate the main processor condition codes, supervisor status, trace modes, selection of the active stack, and interrupt mask level. The MC68020/EC020 discards any instruction words that have been prefetched beyond the current scanPC location when this primitive is issued with DR = 1 (transfer to main processor). The MC6B8020/EC020 then refills the instruction pipe from the scanPC address in the address space indicated by the S-bit of the SR. If the MC68020/EC020 is operating in the trace on change of flow made (T1, TO in the SR = O01) when the coprocessor instruction begins to execute and if this primitive is issued with DR = 1 (from coprocessor to main processor), the MC68020/EC020 prepares to take a trace exception. The trace exception occurs when the coprocessor signals that it has completed all processing associated with the instruction. Changes in the trace modes due to the transfer of the SR to the main processor take effect on execution of the next instruction. 7.4.18 Take Preinstruction Exception Primitive The take preinstruction exception primitive initiates exception processing using a coprocessor-supplied exception vector number and the preinstruction exception stack frame format. This primitive applies to general and conditional category instructions. Figure 7-40 shows the format of the take preinstruction exception primitive. 15 4 3 12 W 40 9 8 7 Q [fo fec{olsjif{i1]o | o | VECTOR NUMBER Figure 7-40. Take Preinstruction Exception Primitive Format The take preinstruction exception primitive uses the PC bit as described in 7.4.2 Coprocessor Response Primitive General Format. The vector number field contains the exception vector number used by the main processor to initiate exception processing. When the main processor receives this primitive, it acknowledges the coprocessor exception request by writing an exception acknowledge mask to the control CIR (refer to 7.3.2 Control CIR). The MC68020/EC020 then proceeds with exception processing as MOTOROLA M68020 USER'S MANUAL 7-45described in Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the four-word stack frame format shown in Figure 7-41. 15 12 14 . i) SP STATUS REGISTER +02 PROGRAM COUNTER --_____ 610 0 O 9 | VECTOR NUMBER Figure 7-41. MC68020/EC020 Preinstruction Stack Frame The value of the PC saved in this stack frame is the F-line operation word address of the coprocessor instruction during which the primitive was received. Thus, if the exception handler routine does not modify the stack frame, an RTE instruction causes the MC68020/EC020 to return and reinitiate execution of the coprocessor instruction. The take preinstruction exception primitive can be used when the coprocessor does not recognize a value written to either its command CIR or condition CIR to initiate a coprocessor instruction. This primitive can also be used if an exception occurs in the coprocessor instruction before any program-visible resources are modified by the instruction operation. This primitive should not be used during a coprocessor instruction if program-visible resources have been modified by that instruction. Otherwise, since the MC68020/EC020 reinitiates the instruction when it returns from exception processing, the restarted instruction receives the previously modified resources in an inconsistent state. One of the most important uses of the take preinstruction exception primitive is to signal an exception condition in a cpGEN instruction that was executing concurrently with the main processor's instruction execution. If the coprocessor no ionger requires the services of the main processor to complete a cpGEN instruction and if the concurrent instruction completion is transparent to the Programming model, the coprocessor can release the main processor by issuing a primitive with CA = 0. The main processor usually executes the next instruction in the instruction stream, and the coprocessor completes its operations concurrently with the main processor operation. If an exception occurs while the coprocessor is executing an instruction concurrently, the exception is not processed until the main processor attempts to initiate the next general or conditional instruction, After the main processor writes to the command or condition CIR to initiate a general or conditional instruction, it then reads the response CIR. At this time, the coprocessor can return the take preinstruction exception primitive. This protocol allows the main processor to proceed with exception processing related to the previous concurrently executing coprocessor instruction and then return and reinitiate the coprocessor instruction during which the exception was signaled. The coprocessor should record the addresses of all general category instructions that can be executed concurrently with the main processor and that support exception recovery. Since the exception is not reported until the next coprocessor instruction is initiated. the processor usually requires the instruction address to determine 7-46 M68020 USER'S MANUAL MOTOROLAwhich instruction the coprocessor was executing when the exception occurred. A coprocessor can record the instruction address by setting PC = 1 in one of the primitives it uses before reteasing the main processor. 7.4.19 Take Midinstruction Exception Primitive The take midinstruction exception primitive initiates exception processing using a coprocessor-supplied exception vector number and the midinstruction exception stack frame format. This primitive applies to general and conditional category instructions. Figure 7-42 shows the format of the take midinstruction exception primitive. 1 14 13 12 tt 10 9 8 fi 0 pe fecfof ifr ]fs fo fi] VECTOR NUMBER Figure 7-42. Take Midinstruction Exception Primitive Format The take midinstruction exception primitive uses the PC bit as described in 7.4.2 Coprocessor Response Primitive General Format. The vector number field contains the exception vector number used by the main processor to initiate exception processing. When the main processor receives this primitive, it acknowledges the coprocessor exception request by writing an exception acknowledge mask (refer to 7.3.2 Control CIR) to the control CIR. The MC68020/EC020 then performs exception processing as described in Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the 10-word stack frame format shown in Figure 7-43. 15 12 11 0 SP STATUS REGISTER +02 SCAN PC +671 0 0 + VECTOR NUMBER +08 PROGRAM COUNTER +00 INTERNAL REGISTER +0E OPERATION WORD 410 [ps EFFECTIVE ADDRESS Figure 7-43. MC68020/EC020 Midinstruction Stack Frame MOTOROLA M68020 USER'S MANUAL 7-47The PC value saved in this stack frame is the operation word address of the coprocessor instruction during which the primitive is received. The scanPC field contains the value of the MC68020/EC020 scanPC when the primitive is received. If the current instruction does not evaluate an effective address prior to the exception request primitive, the value of the effective address field in the stack frame is undefined. The coprocessor uses this primitive to request exception processing for an exception during the instruction dialog with the main processor. If the exception handler does not modify the stack frame, the MC68020/EC020 returns from the exception handler and reads the response CIR. Thus, the main processor attempts to continue executing the suspended instruction by reading the response CIR and processing the primitive it receives. 7.4.20 Take Postinstruction Exception Primitive The take postinstruction exception primitive initiates exception processing using a coprocessor-supplied exception vector number and the postinstruction exception stack frame format. This primitive applies to general and conditional category instructions. Figure 7-44 shows the format of the take postinstruction exception primitive. 184 19120 "| Lojecjo]s ji] Figure 7-44. Take Postinstruction Exception Primitive Format 9 8 7 1 | 0 | VECTOR NUMBER | The take postinstruction exception primitive uses the PC bit as described in 7.4.2 Coprocessor Response Primitive General Format. The vector number field contains the exception vector number used by the main processor to initiate exception processing. When the main processor receives this primitive, it acknowledges the coprocessor exception request by writing an exception acknowledge mask to the control CIR (refer to 7.3.2 Control CIR). The MC68020/ECO20 then performs exception processing as described in Section 6 Exception Processing. The vector number for the exception is taken from the vector number field of the primitive, and the MC68020/EC020 uses the Six- word stack frame format shown in Figure 7-45. 15 12 14 0 seo STATUS REGISTER +02 SCAN PC 6/0 O Ff OO VECTOR NUMBER +08 PROGRAM COUNTER _ Figure 7-45. MC68020/EC020 Postinstruction Stack Frame 7-48 M68020 USER'S MANUAL MOTOROLAThe value in the main processor scanPC at the time this primitive is received is saved in the scanPC field of the postinstruction exception stack frame. The value of the PC saved is the F-line operation word address of the coprocessor instruction during which the primitive is received. When the MC68020/EC020 receives the take postinstruction exception primitive, it assumes that the coprocessor either completed or aborted the instruction with an exception. If the exception handler does not modify the stack frame, the MC68020/ECO20 returns from the exception handler to begin execution at the location specified by the scanPC field of the stack frame. This location should be the address of the next instruction to be executed. The coprocessor uses this primitive to request exception processing when it completes or aborts an instruction while the main processor is awaiting a normal response. For a general category instruction, the response is a release: for a conditional! category instruction, it is an evaluated true/false condition indicator. Thus, the operation of the MC68020/EC020 in response to this primitive is compatible with standard M6800G family instruction related exception processing (for example, the divide-by-zero exception). 7.5 EXCEPTIONS Various exception conditions related to the execution of coprocessor instructions may occur. Whether an exception is detected by the main processor or by the coprocessor, the main processor coordinates and performs exception processing. Servicing these coprocessor-related exceptions is an extension of the protocol used to service standard M68000 family exceptions. That is, when either the main processor detects an exception or is signaled by the coprocessor that an exception condition has occurred, the main processor proceeds with exception processing as described in Section 6 Exception Processing. 7.5.1 Coprocessor-Detected Exceptions Coprocessor interface exceptions that the coprocessor detects, as well as those that the main processor detects, are usually classified as coprocessor-detected exceptions. Coprocessor-detected exceptions can occur during M68000 coprocessor interface operations, internal operations, or other system-related operations of the coprocessor. Most coprocessor-detected exceptions are signaled to the main processor through the use of one of the three take exception primitives defined for the M68000 coprocessor interface. The main processor responds to these primitives as described in 7.4.18 Take Preinstruction Exception Primitive, 7.4.19 Take Midinstruction Exception Primitive, and 7.4.20 Take Postinstruction Exception Primitive. However, not ali coprocessor- detected exceptions are signaled by response primitives. Coprocessor-detected format errors during the cpSAVE or cpRESTORE instruction are signaled to the main processor using the invalid format word described in 7.2.3.2.3 Invalid Format Words. MOTOROLA M68020 USER'S MANUAL 7-497.5.1.1 COPROCESSOR-DETECTED PROTOCOL VIOLATIONS. Protocol violation exceptions are communication failures between the main processor and coprocessor across the M68000 coprocessor interface. Coprocessor-detected protocol violations occur when the main processor accesses entries in the CIR set in an unexpected sequence. The sequence of operations that the main processor performs for a given coprocessor instruction or coprocessor response primitive has been described previously in this section. A coprocessor can detect protocol violations in various ways. According to the M68000 coprocessor interface protocol, the main processor always accesses the operation word, operand, register select, instruction address, or operand address CIRs synchronously with respect to the operation of the coprocessor. That is, the main processor accesses these five registers in a certain sequence, and the coprocessor expects them to be accessed in that sequence. As a minimum, all M68000 coprocessors should detect a protocol violation if the main processor accesses any of these five registers when the coprocessor is expecting an access to either the command or condition CIR. Likewise, if the coprocessor is expecting an access to the command or condition CIR and the main processor accesses one of these five registers, the coprocessor should detect and signal a protocol violation. According to the M68000 coprocessor interface protocol, the main processor can perform a read of either the save CIR or response CIR or a write of either the restore CIR or control CIR asynchronously with respect to the operation of the coprocessor. That is, an access to one of these registers without the coprocessor explicitly expecting that access at that point can be a valid access. Although the coprocessor can anticipate certain accesses to the restore, response, and control CIRs, these registers can be accessed at other times also. The coprocessor cannot signal a protocol violation to the main processor during execution of a cpSAVE or cpRESTORE instruction. If a coprocessor detects a protocol violation during execution of the cpSAVE or cpRESTORE instruction, it should signal the exception to the main processor when the next coprocessor instruction is initiated. The main philosophy of the coprocessor-detected protocol violation is that the coprocessor should always acknowledge an access to one of its interface registers. If the coprocessor determines that the access is not valid, it should assert DSACK1/DSACKO to the main processor and signal a protocol violation when the main processor next reads the response CIR. If the coprocessor fails to assert DSACK1/DSACKO, the main processor waits for the assertion of that signal (or some other bus termination signal) indefinitely. The protocol previously described ensures that the coprocessor cannot halt the main processor. The coprocessor can signal a protocol violation to the main processor with the take midinstrustion exception primitive. To maintain consistency, the vector number should be 13, as ft is for a protocol violation detected by the main processor. When the main processor reads this primitive, it proceeds as described in 7.4.19 Take Midinstruction Exception Primitive. If the exception handler does not modify the stack frame. the MC68020/EC020 returns from the exception handler and reads the response CIR. 7-50 M68020 USER'S MANUAL MOTOROLA7.5.1.2 COPROCESSOR-DETECTED ILLEGAL COMMAND OR CONDITION WORDS. Ittegal coprocessor command or condition words are values written to the command CIR or condition CIR that the coprocessor does not recognize. If a value written to either of these registers is not valid, the coprocessor should return the take preinstruction exception primitive in the response CIR. When it receives this primitive, the main processor takes a preinstruction exception as described in 7.4.18 Take Preinstruction Exception Primitive. If the exception handler does not modify the main processor stack frame, an RTE instruction causes the MC68020/EC020 to reinitiate the instruction that took the exception. The coprocessor designer should ensure that the state of the coprocessor is not irrecoverably altered by an illegal command or condition exception if the system supports emulation of the unrecognized command or condition word. All M68000 coprocessors signal illegal command and condition words by returning the take preinstruction exception primitive with the F-line emulator exception vector number 11, 7.5.1.3 COPROCESSOR DATA-PROCESSING-RELATED EXCEPTIONS. Exceptions related to the internal operation of a coprocessor are classified as data-processing-related exceptions. These exceptions are analogous to the divide-by-zero exception defined by M6B8000 microprocessors and should be signaled to the main processor using one of the three take exception primitives containing an appropriate exception vector number. Which of these three primitives is used to signal the exception is usually determined by the point in the instruction operation where the main processor should continue the program flow after exception processing. Refer to 7.4.18 Take Preinstruction Exception Primitives, 7.4.19 Take Midinstruction Exception Primitive, and 7.4.20 Take Postinstruction Exception Primitive. 7.5.1.4 COPROCESSOR SYSTEM-RELATED EXCEPTIONS. System-reiated exceptions detected by a DMA coprocessor include those associated with bus activity and any other exceptions (interrupts, for example) occurring external to the coprocessor. The actions taken by the coprocessor and the main processor depend on the type of exception that occurs. When an address or bus error is detected by a DMA coprocessor, the coprocessor should Store any information necessary for the main processor exception handling routines in system-accessible registers. The coprocessor should place one of the three take exception primitives encoded with an appropriate exception vector number in the response CIR. Which of the three primitives is used depends upon the point in the coprocessor instruction at which the exception was detected and the point in the instruction execution at which the main processor should continue after exception processing. Refer to 7.4.18 Take Preinstruction Exception Primitives, 7.4.19 Take Midinstruction Exception Primitive, and 7.4.20 Take Postinstruction Exception Primitive. MOTOROLA M68020 USER'S MANUAL 7-517.5.1.5 FORMAT ERRORS. Format errors are the only coprocessor-detected exceptions that are not signaled to the main processor with a response primitive. When the main processor writes 4 format word to the restore CIR during the execution of a coRESTORE instruction, the coprocessor decodes this word to determine if it is valid (refer to 7.2.3.3 Coprocessor Context Save Instruction). If the format word is not valid, the coprocessor places the invalid format code in the restore CIR. When the main processor reads the invalid format code, it aborts the coprocessor instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR). The main processor then performs exception processing using a four-word preinstruction stack frame and the format error exception vector number 14. Thus, if the exception handler does not modify the stack frame, the MC68020/EC020 restarts the cpRESTORE instruction when the RTE instruction in the handler is executed. If the coprocessor returns the invalid format code when the main processor reads the save CIR to initiate a cpSAVE instruction, the main processor performs format error exception processing as outlined for the coRESTORE instruction. 7.5.2 Main-Processor-Detected Exceptions A number of exceptions related to coprocessor instruction execution are detected and serviced by the main processor instead of the coprocessor. These exceptions can be related to the execution of coprocessor response primitives, communication across the M68000 coprocessor interface, or completion of conditional coprocessor instructions by the main processor. 7.5.2.1 PROTOCOL VIOLATIONS. The main processor detects a protoco! violation when it reads a primitive from the response CIR that is not a valid primitive. The protocol violations that can occur in response to the primitives defined for the M68000 coprocessor interface are summarized in Table 7-6. 7-52 M68020 USERS MANUAL MOTOROLATable 7-6. Exceptions Related to Primitive Processing Primitive Protocol F-Line Other Busy Null Supervisory Chack* Other. Privilege Violation if S-Bit in the SR = 0 Transter Operation Word* Transfer from Instruction Stream Protocol. If Length Field Is Odd (Zero Length Legal) Evaluate and Transfer Effective Address Protocol: If Used with Conditional Instruction F-Line: If EA in Opword Is NOT Control Alterable Evaluate Effective Address and Transfer Data Protocol: 1. If Used with Conditiona? Instructions 2. Length !s Not 1, 2, or 4 and EA = Register Direct 3. If EA = Immediate and Length Odd and Greater Than 1 4, Attempt to Write to Unalterable Address Even if Address Declared Legal in Primitive F-Line: Valid EA Field Does Not Match EA in Qpword Write to Previously Evaluated Effective Address Protocol: If Used with Conditional Instruction Take Address and Transfer Data* Transfer to/from Top of Stack Protocol: Length Field Other Than 1, 2, or 4 Transfer Single Main Processor Register* Transfer Main Processor Controd Register Protocol: Invalid Control Register Select Code Transfer Multiple Main Processor Registers* Transfer Multiple Coprocessor Registers Protocol: 1. Hf Used with Conditional Instructions 2. Odd Length Value F-Line: 1. EA Not Control Alterable or (An}+ for CP to Memory Transter 2, EA Not Control Alterable or (An) for Memory to CP Transfer Transfer Status and ScanPC Protocei: ff Used with Conditional Instruction Other: Flow Mode and DR = 4 2. Address ErrorIf Odd Value Written to ScanPC 1 TraceTrace Made Pending if MC68020/EC020 in Trace on Change of Take Preinstruction, Midinstruction, or Postinstruction Exception Exception Oepends on Vector Supplies in Primitive *Use of this primitive with CA = 0 will cause protocol violation on conditional instructions. Abbreviations: EAEffective Address CP ..Coprocessor MOTOROLA M68020 USER'S MANUAL 7-33When the MC68020/EC020 detects a protocol violation, it does not automatically notify the coprocessor of the resulting exception by writing to the control CIR. However, the exception handling routine may use the MOVES instruction to read the response CIR and thus determine the primitive that caused the MC68020/EC020 to initiate protocol violation exception processing. The main processor initiates exception processing using the midinstruction stack frame (refer to Figure 7-43) and the coprocessor protocol violation exception vector number 13. If the exception handler does not modify the stack frame, the main processor reads the response CIR again following the execution of an RTE instruction to return from the exception handler. This protocol allows extensions to the M68000 coprocessor interface to be emulated in software by a main processor that does not provide hardware support for these extensions. Thus, the protocol violation is transparent to the coprocessor if the primitive execution can be emulated in software by the main processor. 7.5.2.2 F-LINE EMULATOR EXCEPTIONS. The F-line emulator exceptions detected by the MC68020/EC020 are either explicitly or implicitly related to the encodings of F-line operation words in the instruction stream. !f the main processor determines that an F-line operation word is not valid, it initiates F-line emulator exception processing. Any F-line operation word with bits 8-6 = 110 or 111 causes the MC68020/ECO020 to initiate exception processing without initiating any communication with the coprocessor for that instruction. Also, an operation word with bits 8-6 = 000-101 that does not map to one of the valid coprocessor instructions in the instruction set causes the MC68020/EC020 to initiate F-line emulator exception processing. If the F-line emulator exception is either of these two situations, the main processor does not write to the control CIR prior to initiating exception processing. F-line exceptions can also occur if the operations requested by a coprocessor response primitive are not compattble with the effective address type in bits 5-0 of the coprocessor instruction operation word. The F-line emulator exceptions that can result from the use of the M68000 coprocessor response primitives are summarized in Table 7-6. If the exception is caused by receiving an invalid primitive, the main processor aborts the coprocessor instruction in progress by writing an abort mask (refer to 7.3.2 Control CIR) to the control CIR prior to Fine emulator exception processing. Another type of F-line emulator exception occurs when a bus error occurs during the CIR access that initiates a coprocessor instruction. The main processor assumes that the coprocessor ts not present and takes the exception. When the main processor initiates F-tine emulator exception processing, it uses the four- word preinstruction exception stack frame (refer to Figure 7-41) and the F-line emulator exception vector number 11. Thus, if the exception handler does not modify the stack frame, the main processor attempts to restart the instruction that caused the exception after it executes an RTE instruction to return from the exception handler. If the cause of the F-line exception can be emulated in software, the handler stores the results of the emulation in the appropriate registers of the programming model and in the status register field of the saved stack frame. The exception handler adjusts the program 7-54 M68020 USER'S MANUAL MOTOROLAcounter field of the saved stack frame to point to the next instruction operation word and executes the ATE instruction. The MC68020/EC020 then executes the instruction following the instruction that was emulated. The exception handler should also check the copy of the SR on the stack to determine whether tracing is enabled. ff tracing is enabled, the trace exception processing should also be emulated. Refer to Section 6 Exception Processing for additional information. 7.5.2.3 PRIVILEGE VIOLATIONS. Privilege violations can result from the cpSAVE and cpRESTORE instructions and from the supervisor check coprocessor response primitive. The MC68020/EC020 initiates privilege violation exception processing if it attempts to execute either the coSAVE or cpRESTORE instruction when it is in the user state (S = 0 in the SR). The main processor initiates this exception processing prior to any communication with the coprocessor associated with the CpSAVE or cpRESTORE instructions. if the main processor is executing a coprocessor instruction in the user State when it reads the supervisor check primitive, it aborts the coprocessor instruction in progress by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR). The main processor then performs privilege violation exception processing. if a privilege violation occurs, the main processor initiates exception processing using the four-word preinstruction stack frame (refer to Figure 7-41) and the privilege violation exception vector number 8. Thus, if the exception handler does not modify the stack frame, the main processor attempts to restart the instruction during which the exception occurred after it executes an RTE to return from the handler. 7.5.2.4 cpTRAPcc INSTRUCTION TRAPS. If, during the execution of a cpTRAPcc instruction, the coprocessor returns the TRUE condition indicator to the main processor with a null primitive, the main processor initiates trap exception processing. The main processor uses the six-word postinstruction exception stack frame (refer to Figure 7-45) and the trap exception vector number 7. The scanPC field of this stack frame contains the address of the instruction following the coTRAPcc instruction. The processing associated with the cpTRAPcc instruction can then proceed, and the exception handler can locate any immediate operand words encoded in the cpTRAPcc instruction using the information contained in the six-word stack frame. If the exception handler does not modify the stack frame, the main processor executes the instruction following the cpTRAPcc instruction after it executes an RTE instruction to exit from the handler. 7.5.2.5 TRACE EXCEPTIONS. The MC68020/EC020 supports two modes of instruction tracing, as discussed in Section 6 Exception Processing. In the trace on instruction execution mode, the MC68020/EC020 takes a trace exception after completing each instruction. In the trace on change of flow mode. the MC68020/EC020 takes a trace exception after each instruction that alters the SR or places an address other than the address of the next instruction in the PC. MOTORCLA M68020 USERS MANUAL 7-55The protocol used to execute coprocessor cpSAVE, cpRESTORE, or conditional category instructions does not change when a trace exception is pending in the main processor. The main processor performs a pending trace on instruction execution exception after compieting the execution of that instruction. If the main processor is in the trace on change of flow mode and an instruction places an address other than that of the next instruction in the PC, the processor takes a trace exception after it executes the instruction. lf a trace exception is not pending during a general category instruction, the main processor terminates communication with the coprocessor after reading any primitive with CA = 0. Thus, the coprocesser can complete a cpGEN instruction concurrently with the execution of instructions by the main processor. When a trace exception is pending, however, the main processor must ensure that all processing associated with a cpGEN instruction has been completed before it takes the trace exception. In this case, the main processor continues to read the response CIR and to service the primitives until it receives either a null primitive with CA = 0 and PF = 1 or until exception processing caused by a take postinstruction exception primitive has completed. The coprocessor should return the null primitive with CA = 0 and PF = 0 while it is completing the execution of the coGEN instruction. The main processor may service pending interrupts between reads of the response CIR if !A = 1 in these primitives (refer to Table 7-3). This protocol ensures that a trace exception is not taken until all processing associated with a cpGEN instruction has completed. If T1, TO = 01 in the MC68020/EC020 SR (trace on change of flow mode) when a general category instruction is initiated, a trace exception is taken for the instruction only when the coprocessor issues a transfer status register and scanPC primitive with DR = 1 during the execution of that instruction. In this case, it is possible that the coprocessor is still executing the coGEN instruction concurrently when the main processor begins execution of the trace exception handler. A cpSAVE instruction executed during the trace on change of flow exception handler could thus suspend the execution of a concurrently operating cpGEN instruction. 7.5.2.6 INTERRUPTS. Interrupt processing, discussed in Section 6 Exception Processing, can occur at any instruction boundary. Interrupts are also serviced during the execution of a general or conditional category instruction under either of two conditions. {f the main processor reads a null primitive with CA = 1 and IA = 1, it services any pending interrupts prior to reading the response CIR. Similarly, if a trace exception is pending during cpGEN instruction execution and the main processor reads a null primitive with CA - 0, IA = 1, and PF = 0 (refer to 7.5.2.5 Trace Exceptions), the main processor services pending interrupts prior to reading the response CIR again. The MC68020/EC020 uses the 10-word midinstruction stack frame (see Figure 7-43) when it services interrupts during the execution of a general or conditional category coprocessor instruction. Since it uses this stack frame, the main processor can perform all necessary processing and then return to read ihe response CIR. Thus, it can continue execution of the coprocessor instruction during which the interrupt exception occurred. 7-56 M68020 USERS MANUAL MOTOROLAThe MC68020/EC020 also services interrupts if it reads the not-ready format word from the save CIR during a cpSAVE instruction. The MC68020/EC020 uses the narmal four. word preinstruction stack frame (see Figure 7-41) when it services interrupts after reading the not-ready format word. Thus, the processor can service any pending interrupts and execute an RTE to return and reinitiate the cpSAVE instruction by reading the save CIR. 7.5.2.7 FORMAT ERRORS. The MC68020/EC020 can detect a format error while executing a cpSAVE or cpRESTORE instruction if the length field of a valid format word is not a multiple of four bytes. If the MC68020/EC020 reads a format word with an invalid length field from the save CIR during the cpSAVE instruction, it aborts the coprocessor instruction by writing an abort mask to the control CiR (refer to 7.3.2 Control CIR) and initiates format error exception processing. If the MC68020/EC020 reads a format word with an invalid length field from the effective address specified in the cPpRESTORE instruction, the MC68020/EC020 writes that format word to the restore CIR and then reads the coprocessor response from the restore CIR. The MC68020/EC020 then aborts the cpRESTORE instruction by writing an abort mask to the control CIR (refer to 7.3.2 Control CIR) and initiates format error exception processing. The MC68020/EC020 uses the four-word preinstruction stack frame (see Figure 7-41) and the format error vector number 14 when it initiates format error exception processing. Thus, if the exception handler does not modify the stack frame, the main processor, after it executes an RTE to return from the handler, attempts to restart the instruction during which the exception occurred. 7.5.2.8 ADDRESS AND BUS ERRORS. Coprocessor-instruction-related bus faults can occur during main processor bus cycles to CPU space to communicate with a coprocessor or during memory cycles run as part of the coprocessor instruction execution. If a bus error occurs during the CIR access that is used to initiate a coprocessor instruction, the main processor assumes that the coprocessor is not present and takes an E-line emulator exception as described in 7.5.2.2 F-Line Emulator Exceptions. That is, the processor takes an F-line emulator exception when a bus error occurs during the initial access to a CIR by a coprocessor instruction. If a bus error occurs on any other coprocessor access or on a memory access made during the execution of a coprocessor instruction, the main processor performs bus error exception processing as described in Section 6 Exception Processing. After the exception handler has corrected the cause of the bus error, the main processor can return to the point in the coprocessor instruction at which the fault occurred. An address error occurs if the MC68020/EC020 attempts to prefetch an instruction fram an odd address. This can occur if the calculated destination address of a cpBcc or cpDBcc instruction is odd or if an odd value is transferred to the scanPC with the transfer status register and the scanPC response primitive. If an address error occurs, the MC68020/EC020 performs exception processing for a bus fault as described in Section 6 Exception Processing. MOTOROLA M68020 USER'S MANUAL 7-577.5.3 Coprocessor Reset Fither an external reset signal or a RESET instruction can reset the external devices of a system. The system designer can design a coprocessor to be reset and initialized by both reset types or by external reset signals only. To be consistent with the MC68020/EC020 design, the coprocessor should be affected by external reset signals only and not by RESET instructions, because the coprocessor is an extension to the main processor programming model and to the internal state of the MC68020/EC020. 7.6 COPROCESSOR SUMMARY Coprocessor instruction formats are included with the instruction formats in the M68000PM/AD, M68000 Family Programmer's Reference Manual. The M68000 coprocessor response primitive formats are shown in this section. Any response primitive with bits 13-8 = $00 or $3F causes a protocol violation exception. Response primitives with bits 13-8 = $0B, $18-$1B, $1F, $28-$2B, and $38-3B currently cause protocol violation exceptions; they are undefined and reserved for future use by Motorola. 7-58 M68020 USERS MANUAL MOTOROLABusy 15 14 13 12 "i 1G 9 [ 1 | PC 1 | 0 | 0 1 | 9 | Transfer Multiple Coprocessor Registers 15 14 13 12 an] 19 9 8 7 9 Lcafecloa[of[o]ofof: | LENGTH | Transfer Status Register and ScanPC 15 14 13 12 WW 10 9 [ca[rc[or[ o]o fof. | ofofefo] o eo }__| oS a -_ g o | | | | | | | 1__J Supervisor Check 15 14 13 12 W 10 9 8 7 6 5 4 3 2 1 0 [1frc]ofofol:fa of ofofofo]o|o | Take Address and Transfer Data 16 14 13 42 44 10 9 4 ? 0 Lca]ecfor[ of[of[s fof: | LENGTH | Transfer Multiple Main Processor Registers 15. 14 13 12 1 10 9 8 ? 6 5 4 3 2 | 0 LeatecTo[ofe]ifiyololefof[ofofolo] |] Transfer Operation Word 1S 14 13 | 2 WW 0 6 9)lB Lefecto/ofofits[ilofofo[ejfofo]e]. Null 15 14 9 4 -F 6 858 #4 9 2 1 0 [ape lefop>:[efole] o a o ao o a 7 ou 3 Fvaluate and Transfer Effective Address MOTOROLA M68020 USERS MANUAL 7-59Transfer Single Main Processor Register 5 {4 13 5 4 3 2 Ce[e pepe prt: pepe 0 Po fo [oa] recsten | Transter Main Processor Control Register 15 t4 13 12 i 1 ralelo[e]: frets] Transfer to/from Top of Stack Q [Tete] o o o Ls 15 14 13 12 WY 10 4 8 7 0 Lcafector]| of] 1] 1/1 | o | LENGTH | Transfer from Instruction Stream 45 14 13 12 1t 10 9 8 7 0 CA | PC | 0 0 | { | 1 | ' 1 | LENGTH Evaluate Effective Address and Transfer Data 15 14 13 12 YW 10 8 7 0 CA PC | DA | 1 0 | VALID EA LENGTH | Take Preinstruction Exception 15 14 43 12 i1 10 9 8 ? 0 jo lecfofs1i1 [a | o | o VECTOR NUMBER | Take Midinstruction Exception 15 14 13 12 af] 10 9 8 7 6 | 0 | PC | 0 | 1 | 1 | 1 | o | 1 | VECTOR NUMBER Take Postinstruction Exception 15 14 13 12 an} 10 9 8 ? 6 0 PC 0 | \ | 1 | | 1 | 0 | VECTOR NUMBER Write to Previously Evaluated Effective Address 18 14 13 12 11 49 9 8 7 0 Lcafec; 1 ]ofofojolfo | LENGTH M68020 USERS MANUAL MOTOROLASECTION 8 INSTRUCTION EXECUTION TIMING This section describes the instruction execution and operations (table searches, etc.) of the MC68020/EC020 in terms of external clock cycles. It provides accurate execution and operation timing guidelines but not exact timings for every possible circumstance. This approach is used since exact execution time for an instruction or operation is highly dependent on memory speeds and other variables. The timing numbers presented in this section allow the assembly language programmer or compiler writer to predict timings needed to evaluate the performance of the MC68020/EC020. In this section, instruction and operation times are shown in clock cycles, which eliminates clock frequency dependencies. 8.1 TIMING ESTIMATION FACTORS The advanced architecture of the MC68020/EC020 makes exact instruction timing calculations difficult due to the effects of: 1. An On-Chip Instruction Cache and Instruction Prefetch 2. Operand Misalignment 3. Bus Controlier/Sequence Concurrency 4. Instruction Execution Overlap These factors make MC68020/EC020 instruction set timing difficult to calculate on a single instruction basis since instructions vary in execution time from one context to another. A detailed explanation of each of these factors follows. 8.1.1 Instruction Cache and Prefetch The on-chip cache of the MC68020/EC020 is an instruction-only cache. Its purpose is to increase execution efficiency by providing a quick store for instructions. Instruction prefetches that hit in the cache will occur with no deiay in instruction execution. Instruction prefetches that miss in the cache will cause an externa! memory cycle to be performed, which may overlap with internal instruction execution. Thus, while the execution unit of the microprocessor is busy, the bus controller prefetches the next instruction from external memory. Both cases are illustrated in later examples. MOTOROLA M68020 USER'S MANUAL 8-1When prefetching instructions from external memory, the microprocessor will utilize: lore word read cycles. When the read is aligned on a long-word address boundary, the processor reads two words, which may load two instructions at once or two words of a multiword instruction. The subsequent instruction prefetch will find the second word is aiready available, and there is no need to run an external bus cycle (read). The MC68020/EC020 always prefetches long words. When an instruction prefetch falls on an odd-word boundary (e.g., due to a branch to an odd-word location), the MC68020/EC020 will read the even word associated with the long-word base address at the same time as (32-bit memory) or before (8- or 16-bit memory) the odd word is read. When an instruction prefetch falls on an even-word boundary (as would be the normal case), the MC68020/EC020 reads both words at the long-word address, thus effectively prefetching the next two words. 8.1.2 Operand Misalignment Another significant factor affecting instruction timing is operand misalignment. Operand misalignment has impact on performance when the microprocessor is reading or writing external memory. In this case, the address of a word operand falls across a long-word boundary, or a long-word operand fails on a byte or word address that is not a long-word boundary. Although the MC68020/EC020 will automatically handle all occurrences of operand misalignment, it must use multiple bus cycles to complete such transfers. 8.1.3 Bus/Sequencer Concurrency The bus controller is responsible for all bus activity. The sequencer controls the bus controller, instruction execution, and internal processor operation, such as calculation of effective addresses and setting of condition codes. The bus controller and sequencer can operate on an instruction concurrently. The bus controller can perform a read or write while the sequencer controls an effective address calculation or sets the condition codes. The sequencer may also request a bus cycie that the bus controller cannot immediately perform. In this case, the bus cycle is queued and the bus controller runs the cycle when the current cycle is complete. 8-2 M68020 USER'S MANUAL MOTOROLA8.1.4 Instruction Execution Overlap Overlap is the time, measured in clocks, when two instructions execute concurrently. In Figure 8-1, instructions A and B execute concurrently, and the overlapped portion of instruction B is absorbed in the instruction execution time of A (the previous instruction). The overlap time is deducted from the execution time of instruction B. Similarly, there is an overlap period between instruction B and instruction C, which reduces the attributed execution time for C. ------- INSTRUCTION A -___ ------- INSTRUCTION B _| ------- INSTRUCTION C __ OVERLAP OVERLAP Figure 8-1. Concurrent Instruction Execution The execution time attributed to instructions A, B, and C (after considering the overlap) is depicted in Figure 8-2. [+ instruction a ~__ [- INsTRUCTION B }- InstRUCTIONG | bt Lt OVERLAP OVERLAP PERIOD PERIOD (ABSORBED BY (ABSORBED BY INSTRUCTION A} INSTRUCTION B) Figure 8-2. Instruction Execution for Instruction Timing Purposes It is possible that the execution time of an instruction will be absorbed by the overlap with a previous instruction for a net execution time of zero ciocks. Because of this overlap, a NOP is required between a write to a peripheral to clear an interrupt request and a subsequent MOVE to SR instruction to lower the interrupt mask level. Otherwise, the MOVE to SR instruction may complete before the write is accomplished, and a new interrupt exception will be generated for an old interrupt request. MOTOROLA M68020 USER'S MANUAL 8-38.1.5 Instruction Stream Timing Examples A programming example allows a more detailed examination of these effects. The effect of instruction execution overlap on instruction timing is illustrated by the following example instruction stream, Instruction #1)MOVE.L D4 (A1)+ 42) ADDL D405 #3) MOVE.L (At), -(A2) #4) ADDL DS,D6 Example 1 For the first example, the assumptions are: 1. The data bus is 32 bits, 2. The first instruction is prefetched from an odd-word address, 3. Memory access occurs with no wait states, and 4. The instruction cache is disabled. For example 1, the instruction stream is positioned in 32-bit memory as follows: Address n one MOVE #1 n+4 ADD #2 MOVE #3 n+8 ADD #4 aus Figure 8-3 shows processor activity on the first example instruction stream. It shows the activity of the externai bus, the bus controller, the sequencer, and the attributed instruction execution time. 8-4 M68020 USER'S MANUAL MOTOROLA1 ? j 4 45 6 ? & 9 10 i te 13 14 1 16 {7 ao TUPLE LLU ULL LL Lk BUS oF P X 4 ACTIVITY K PREFETCH xX WRITE x READ x REFETCH WAITE BUS PREFETCH =] err sn PREFET CONTROLLER | ~ gyTes nya |. WRITE TOUIe | READFROMIAT) | QTECETCH, | WRITE TO4A2) Ce pos CALCULATE PERFORM PERFORM | CALCULATE |r cri ATION PERFORM SEQUENCER | omoveat fIPLEY Appaz | SOURCE EA EA IDLE MOVE #9 MOVE #3 INSTRUCTION : ~ EXECUTION TIME MOVE.L Dd,(Al}+ . MOVE L {A1}{A2) clock | | | COUNT | (6) | 9) t wn LEGEND: Tr] 1) MOVE.L D4 (At}e 2} ADD.L.D4,05 [__] 3) MOvE.L (at).1a2} BOs] 4) ADD.L D5,06 Figure 8-3. Processor Activity for Example 1 For the first three clocks of this example, the bus controller and sequencer are both performing tasks associated with the MOVE #1 instruction. The next three clocks (clocks 4, 5, and 6) demonstrate instruction overlap. The bus controller is performing a write to memory as part of the MOVE #1 instruction. The sequencer, on the other hand, is performing the ADD #2 instruction for two clocks (clocks 4 and 5) and beginning source effective address (EA) calculations for the MOVE #3 instruction. The bus controller activity completely overlaps the execution of the ADD #2 instruction, causing the ADD #2 attributed execution time to be zero clocks. The overlap also shortens the effective execution time of the MOVE #3 instruction by one clock because the bus controller completes the MOVE #1 write operation while the sequencer begins the MOVE #3 EA calculation. The sequencer continues the source EA calculation for one more clock period (clock 7) while the bus controller begins a read for MOVE #3. When counting instruction execution time in bus clocks, the MOVE #1 completes at the end of clock 6, and the execution of MOVE #3 begins on clock 7. Both the sequencer and bus controller continue with MOVE 43 untit the end of clock 14, when the sequencer begins to perform ADD #4. Timing for MOVE #3 continues because the bus controller is still performing the write to the destination of MOVE #3. The bus activity for MOVE #3 completes at the end of clock 15. The effective execution time for MOVE #3 is nine clocks. The one clock cycle (clock 15) when the sequencer is performing ADD #4 and the bus controller is writing to the destination of MOVE #3 is absorbed by the execution time of MOVE #3. This overlap shortens the effective execution time of ADD #4 by one clock, giving it an attributed execution time of one clock MOTOROLA M68020 USER'S MANUAL 8-5Example 2 Using the same instruction stream, the second example demonstrates the different effects of instruction execution overlap on instruction timing when the same instructions are positioned slightly differently in 32-bit memory: Address n MOVE #1 ADD #2 n+4 MOVE #3 AOD #4 n+8 ove sue The assumptions for example 2 (see Figure 8-4) are: 1. The data bus is 32 bits, 2. The first instruction is prefetched from an even-word address, 3. Memory access occurs with no wait states, and 4. The cache is disabled. BUS } K ACTIVITY WRITE x PREFETCH x READ XK WRITE _ prerercn 1 controler | MAE} Oi | EREFETCH | ReaD FROM(At) | WRITE TO-(A2) CALCULATE SESE CALCULATE SEQUENCER PERFORM | SOURCE EA | IDLE INATIONT pug | AERFORM MOVE #4 2 EAS MOVE #3 EXECUTION Ty 4 - ADD.L D405 MOVE.L (A1},-{A2) CLOCK ; | COUNTER f (4) (3} | (6) e LEGEND: SE ty) MOVELL D4 (At)+ 2} ADD D4,D5 [7] 3) Move. (At) 492) 4) ADD.L 05,06 Figure 8-4. Processor Activity for Example 2 Although the total execution time of the instruction segment does not change in this example, the individual instruction times are significantly different. This example demonstrates that the effects of overlap are not only instruction-sequence dependent but are also dependent upon the alignment of the instruction stream in memory. 8-6 M68020 USER'S MANUAL MOTOROLAExample 3 Both Figures 8-3 and 8-4 show instruction execution without benefit of the MC68020/EC020 instruction cache. Figure 8-5 shows a third example for the same instruction stream executing in the cache. Note that once the instructions are in the cache, the original location in external memory is no longer a factor in timing. The assumptions for Example 3 are: 1. The data bus is 32 bits, 2. The cache is enabled and instructions are in the cache, and 3. Memory access occurs with no wait states. 1 2 3 4 5 6 7 6 9 10 W 12 13 BUS tX- x Tl ACTIVITY WRITE }-4 READ WRITE }- | BUS fied weet iam : CONTROLLER | OLE | WRITE TO[AN)+ | IDLE | READ FROM{AI) | WRITE TO +A2) CALCULATE |. CALCULATE SEQUENCER Pena | SOURCE EA DESTINATION FERFORM MOVERS | thy INSTRUCTION EXECUTION TIME MOVE.L (At) (A2) ctock | | | a COUNTER | {4} i) 1) LEGEND: [2] 1) Move D4,Atys 2) ADD.LB4,D5 3) MOVE. {A1) 4A2) Figure 8-5. Processor Activity for Example 3 Figure 8-5 illustrates the benefits of the instruction cache. The total number of clock cycles is reduced from 16 to 12 clocks. Since the instructions are resident in the cache, the instruction prefetch activity does not require the bus controller to perform external bus cycles. Since prefetch occurs with no delay, the bus controller is idle more often. Example 4 idle clock cycles, such as those shown in example 3, are useful in MC68020/EC020 systems thal require wait states when accessing external memory. This fact is itustrated in example 4 (see Figure 8-6) with the following assumptions: 1. The data bus ts 32 bits, 2. The cache is enabled and instructions are in the cache, and 3. Memory access occurs with one wait state. MOTOROLA M68020 USERS MANUAL 8-7{ 2 3 Ki 6 7 ae TLE LLP LLL L$ BUS ACTIVITY BUS CONTROLLER SEQUENCER INSTRUCTION EXECUTION TIME CLOCK COUNTER 4 5 8 9 19 Wl 12 14 4) ADD.LD5,06 Figure 8-6, Processor Activity for Example 4 t-K WRITE x READ x WAITE Y WRITE 10 (At}e READ FROM (At) WRITE 10 (A2) CALCULATE PERFORM sounCe DESTINATION | j] PERFORM ADD #2 | SOURCE E EA MOVE #4 MOVE #3 MOVE.L (At),-(A2) + (5) (8 as LEGEND: [=] 1) Move L 04,(A1}+ [J 2 avo. 4,05 [] 3) Move. (a1),-1a2) Figure 8-6 shows the same instruction stream executing with four clocks for every read and write. The idle bus cycles coincide with the wait states of the memory access; therefore, the total execution time is only 13 clocks. Examples 1-4 demonstrate the complexity of instruction timing calculation for the MC68020/EC020. It is impossible to anticipate individual instruction timing as an absolute number of clock cycles due to the dependency of overlap on the instruction sequence and alignment as well as the number of wait states in memory. This can be seen by comparing individual and composite time for Figures 8-3 through 8-6. These instruction timings are compared in Table 8-1, where timing varies for each instruction as the context varies. Table 8-1. Examples 1-4 Instruction Stream Execution Comparison 8-8 Example 4 Example 1 Example 2 Example 3 (Cache with instruction (Odd Alignment) (Even Alignment) (Cache) Wait States) #1) MOVE.L D4 fAlj+ 6 4 4 5 #2) ADD.L D4.D5 Qo 3 0 o #3) MOVE.L (At), -(A2) 9 6 7 8 44) ADDL D5.06 1 3 1 a Total Clock Cycles 16 16 12 13 M68020 USERS MANUAL MOTOROLA8.2 INSTRUCTION TIMING TABLES The instruction times given in the following illustration include the following assumptions about the MC68020/EC020 system: 1. All operands are long-word aligned as is the stack, 2. The data bus is 32 bits, and 3. Memory access occurs with no wait states (three-cycle read/write). There are three values given for each instruction and addressing mode: 1. The best case (BC), which reflects the time (in clacks) when the instruction is in the cache and benefits from maximum overlap due to other instructions, 2. The cache-only case (CC) when the instruction is in the cache but has no overlap, and 3. The worst case (WC) when the instruction is not in the cache or the cache is disabled and there is no instruction overlap. The only instances for which the size of the operand has any effect are the instructions with immediate operands. Unless specified otherwise, immediate byte and word operands have identical execution times. Within each set or column of instruction timings are four sets of numbers, three of which are enclosed in parentheses. The bolded outer number is the total number of clocks for the instruction. The first number inside the parentheses is the number of operand read cycles performed by the instruction. The second value inside parentheses is the number of instruction accesses performed by the instruction, including all prefetches to keep the instruction pipe filled. The third value within parentheses is the number of write cycles performed by the instruction. One example from the instruction timing tabte is: 24 (2/370 TOTAL NUMBER OF CLOCKS NUMBER OF READ CYCLES NUMBER OF INSTRUCTION ACCESS CYCLES . NUMBER OF WRITE CYCLES The total number of bus-activity clocks for the previous example is derived in the following way: (2 Reads * 3 Clocks/Read) + (3 Instruction Accesses * 3 Clocks/Access) + (O Writes * 3 Clocks/Write) = 15 Clocks of Bus Activity 24 Total Clocks - 15 Clocks (Bus Activity) = 9 Internal Clocks The example used here was taken from a worst-case fetch effective address time. The addressing mode was ([d32,.B].!,dg2). The same addressing mode under the best-case MOTOROLA M68020 USERS MANUAL 8-9entry is 17 (2/0/0). For the best case. there are no instruction accesses because the cache is enabled and the sequencer does not have to go to external memory for the instruction words. The first tables deal exclusively with fetching and calculating effective addresses and immediate operands. The tables are arranged in this manner because some instructions do not require effective address calculation or fetching. For example, the instruction CLR (found in the table under 8.2.11 Single Operand Instructions) only needs to have a calculated effective address time added to its table entry because no fetch of an operand is required. This instruction only writes to memory or a register. Some instructions use specific addressing modes which exciude timing for calculation or fetching of an operand. When these instances arise, they are footnoted to indicate which other tables are needed in the timing calculation. Many two-word instructions (e.g., MULULL, DIV.L, BFSET, etc.) include the fetch immediate effective address time or the calculate immediate effective address time in the execution time calculation. The timing for immediate data of word length (#.W) is used for these calculations. If the instruction has a source and a destination, the source effective address is used for the table lookup. If the instruction is single operand, the effective address of that operand is used. The following example includes multiword instructions that refer to the fetch immediate effective address and calculate immediate effective address tables in 8.2 Instruction Timing Tables. Instruction #1)MULU.L 07,01:D2 #2) BFCLR = $6000{0:8} #3) DIVS.L = #$10000,03:D4 cc 1.MULU.L (07),01:D2 #.W.Dn 2 MUL.L EA.Dn 43 2.BFCLR $6000{0:8} #edata>.WSXXX.W 5 BFCLR Mem (<5 bytes) 16 3.DIVS._L #$10000,D3:D4 #.W # L 6 DIVS.L EA, Dn 90 Execution time =24+434+541646+90 = 102 clock periods 8-40 M68020 USERS MANUAL MOTOROLANOTE This CC time is a maximum since the times given for the MULU.L and DIVS.L are maximums. The MOVE instruction timing tables include all necessary timing for extension word fetch, address calculation, and operand fetch. The instruction timing tables are used to calculate a best-case and worst-case bounds for some target instruction stream. Calculating exact timing from the timing tables is impossible because the tables cannot anticipate how the combination of factors will influence every particular sequence of instructions. This is illustrated by comparing the observed instruction timing from the prior four examples with instruction timing derived from the instruction timing tables. Table 8-2 lists the original instruction stream and the corresponding clock timing from the appropriate timing tables for the best case, cache-only case, and worst case. Table 8-2. Instruction Timings from Timing Tables Instruction Best Case | Cache Case | Worst Case #1) MOVE.L D4,(A1}+ 40 4 6 #2) ADD.L D4,D5 0 2 3 #3) MOVE.L (A1),-(A2) 6 7 9 #4) ADD.L 05,06 0 2 3 Total 10 15 21 Table 8-3 summarizes the observed instruction timings for the same instruction stream as executed according to the assumptions of the four examples. For each example, Table 8- 3 shows which entry (BC/CC/WC) from the timing tables corresponds to the observed timing for each of the four instructions. Some of the observed instruction timings cannot be found in the timing tables and appear in Table 8-3 within parentheses in the most appropriate column. These timings occur when instruction execution overlap dynamically alters what would otherwise be a BC, CC, or WC timing. Table 8-3. Observed Instruction Timings Example 1 Exampie 2 Example 3 Example 4 Instruction pe cc wc; sc cc welspe cc we| BOC cc we #1) MOVE.L D4,(A1)4+ 6 4 4 (5) #2) ADD.L D405 0 3 0 0 #3) MOVE.L (At),-(A2) 3 6 7 (8) #4) ADD.L D5.D6 (1) 3 (1) 0 Total (16) {16) (12) (13) MOTOROLA M68020 USER'S MANUAL 8-11Comparing Tables 8-2 and 8-3 demonstrates that calculation of instruction timing cannot be a simple lookup of only BC or only WC timings. Even when the assumptions are known and fixed, as in the four examples summarized in Table 8-3, the microprocessor can sometimes achieve best-case timings under worst-case assumptions. Looking across the four examples in Table 8-3 for an individual instruction, it is difficult to predict which timing table entry is used, since the influence of instruction overlap may or may not improve the BC, WC, or CC timings. When looking at the observed instruction timings for one example, it is also difficult to determine which combination of BC/CC/WC timing is required. Just how the instruction stream will fit and run with the cache enabled, how instructions are positioned in memory, and the degree of instruction overlap are factors that are impossible to account for in all combinations of the timing tables. Although the timing tables cannot accurately predict the instruction timing that would be observed when executing an instruction stream on the MC68020/EC020, the tables can be used to calculate best-case and worst-case bounds for instruction timing. Absolute instruction timing must be measured by using the microprocessor itself to execute the target instruction stream. 8-12 M68020 USERS MANUAL MOTOROLA