MicroConverter®, Small Package
12-Bit ADC with Embedded Flash MCU
ADuC814
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
FEATURES
ANALOG I/O
6-channel 247 kSPS ADC
12-bit resolution
ADC high speed data capture mode
Programmable reference via on-chip DAC for low
level inputs, ADC performance specified to VREF = 1 V
Dual voltage output DACs
12-bit resolution, 15 µs settling time
Memory
8 kbytes on-chip Flash/EE program memory
640 bytes on-chip Flash/EE data memory
Flash/EE, 100 year retention, 100 kcycle endurance
3 levels of Flash/EE program memory security
In-circuit serial downlaod (no external hardware)
256 bytes on-chip data RAM
8051 based core
8051 compatible instruction set
32 kHz external crystal,
on-chip programmable PLL (16.78 MHz max)
Three 16-bit timer/counters
11 programmable I/O lines
11 interrupt sources, 2 priority levels
Power
Specified for 3 V and 5 V operation
Normal: 3 mA @ 3 V (core CLK = 2.1 MHz)
Power-down: 15 µA (32 kHz oscillator running)
On-chip peripherals
Power-on reset circuit (no need for external POR device)
Temperature monitor (±1.5°C accuracy)
Precision voltage reference
Time interval counter (wake-up/RTC timer)
UART serial I/O
SPI®/I2C® compatible serial I/O
Watchdog timer (WDT), power supply monitor (PSM)
Package and temperature range
28-lead TSSOP 4.4 mm × 9.7 mm package
Fully specified for −40°C to +125°C operation
APPLICATIONS
Optical networking—laser power control
Base station systems—power amplifier bias control
Precision instruments, smart sensors
Battery-powered systems, precision system monitors
FUNCTIONAL BLOCK DIAGRAM
ADuC814
PROG.
CLOCK
DIVIDER
XTAL2XTAL1
T/H
AIN
MUX
TEMP
MONITOR
INTERNAL
BAND GAP
V
REF
AIN0
V
REF
C
REF
AIN5
OSC
AND
PLL
DAC1
DAC0
BUF
BUF DAC0
DAC1
DAC
CONTROL
LOGIC
12-BIT
ADC ADC
CONTROL
LOGIC
BUF
POWER-
ON
RESET 8 KBYTES FLASH/EE PROGRAM MEMORY
640 BYTES FLASH/EE DATA MEMORY
256 BYTES USER RAM
3× 16-BIT
TIMER/COUNTERS
1× WAKE-UP/RTC
TIMER
10 × DIGITAL
I/O PINS
8051-BASED MCU WITH ADDITIONAL
PERIPHERALS
ON-CHIP MONITORS
POWER SUPPLY
MONITOR
WATCHDOG TIMER
UART AND SPI
SERIAL I/O
02748-A-001
Figure 1.
GENERAL DESCRIPTION
The ADuC814 is a fully integrated 247 kSPS, 12-bit data acquisi-
tion system incorporating a high performance multichannel
ADC, an 8-bit MCU, and program/data Flash/EE memory on a
single chip.
This low power device operates from a 32 kHz crystal with an
on-chip PLL generating a high frequency clock of 16.78 MHz.
This clock is, in turn, routed through a programmable clock
divider from which the MCU core clock operating frequency is
generated.
The microcontroller core is an 8052 and is compatible with an
8051 instruction. 8 kBytes of nonvolatile Flash/EE program
memory are provided on-chip. 640 bytes of nonvolatile Flash/EE
data memory and 256 bytes RAM are also integrated on-chip.
The ADuC814 also incorporates additional analog functionality
with dual 12-bit DACs, a power supply monitor, and a band gap
reference. On-chip digital peripherals include a watchdog timer,
time interval counter, three timer/counters, and two serial I/O
ports (SPI and UART).
On-chip factory firmware supports in-circuit serial download
and debug modes (via UART), as well as single-pin emulation
mode via the DLOAD pin. The ADuC814 is supported by a
QuickStart™ Development System.
The part operates from a single 3 V or 5 V supply over the
extended temperature range −40°C to +125°C. When operating
from 3 V supplies, the power dissipation for the part is below
10 mW. The ADuC814 is housed in a 28-lead TSSOP package.
ADuC814
Rev. A | Page 2 of 72
TABLE OF CONTENTS
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Description ............................ 10
Terminology .................................................................................... 12
ADC Specifications .................................................................... 12
DAC Specifications..................................................................... 12
Typical Performance Curves ......................................................... 13
ADuC814 Architecture, Main Features ....................................... 16
Memory Organization ............................................................... 17
Overview of MCU-Related SFRs.............................................. 18
Accumulator SFR ................................................................... 18
B SFR........................................................................................ 18
Stack Pointer SFR ................................................................... 18
Data Pointer ............................................................................ 18
Program Status Word SFR..................................................... 18
Power Control SFR................................................................. 19
Special Function Registers ........................................................ 20
ADC Circuit Information.............................................................. 21
General Overview....................................................................... 21
ADC Transfer Function............................................................. 21
ADC Data Output Format .................................................... 21
SFR Interface to ADC Block ..................................................... 22
ADCCON1 (ADC Control SFR 1) .......................................... 22
ADCCON2 (ADC Control SFR 2) .......................................... 23
ADCCON3 (ADC Control SFR 3) .......................................... 24
Driving the ADC............................................................................. 25
Voltage Reference Connections................................................ 26
Configuring the ADC ................................................................ 26
Initiating ADC Conversions ..................................................... 27
ADC High Speed Data Capture Mode .................................... 27
ADC Offset and Gain Calibration Overview ......................... 28
ADC Offset and Gain Calibration Coefficients ..................... 28
Calibrating the ADC .................................................................. 29
Initiating Calibration in Code .................................................. 29
Nonvolitile Flash/EE Memory ...................................................... 30
Flash/EE Memory Overview .................................................... 30
Flash/EE Memory and the ADuC814...................................... 30
ADuC814 Flash/EE Memory Reliability................................. 30
Using Flash/EE Program Memory........................................... 31
Serial Downloading (In-Circuit Programming)................ 31
Parallel Programming............................................................ 31
Flash/EE Program Memory Security....................................... 31
Lock Mode .............................................................................. 31
Secure Mode ........................................................................... 31
Serial Safe Mode ..................................................................... 31
Using Flash/EE Data Memory.................................................. 32
ECON—Flash/EE Memory Control SFR ........................... 32
Flash/EE Memory Timing ........................................................ 33
Using the Flash/EE Memory Interface ................................ 33
Programming a Byte.............................................................. 33
User Interface to Other On-Chip ADuC814 Peripherals.......... 34
DACs............................................................................................ 34
Using the DACs ...................................................................... 35
On-Chip PLL .............................................................................. 37
Time Interval Counter (TIC).................................................... 38
Watchdog Timer......................................................................... 41
Power Supply Monitor............................................................... 42
ADuC814 Configuration Register (CFG814) ........................ 43
Serial Peripheral Interface..................................................... 43
External Clock ........................................................................ 43
ADuC814
Rev. A | Page 3 of 72
Serial Peripheral Interface..........................................................44
MISO (Master In, Slave Out Data I/O Pin) .........................44
MOSI (Master Out, Slave In Pin)..........................................44
SCLOCK (Serial Clock I/O Pin) ...........................................44
SS (Slave Select Input Pin) .....................................................44
Using the SPI Interface...........................................................45
SPI Interface—Master Mode .................................................45
SPI Interface—Slave Mode ....................................................45
I2C Compatible Interface............................................................46
8051 Compatible On-Chip Peripherals....................................47
Parallel I/O Ports 1 and 3.......................................................47
Additional Digital Outputs Pins ...........................................47
Timers/Counters .........................................................................48
Timer/Counter 0 and 1 Data Registers................................49
Timer/Counter 0 and 1 Operating Modes...............................50
Mode 0 (13-Bit Timer/Counter)...........................................50
Mode 1 (16-Bit Timer/Counter)...........................................50
Mode 2 (8-Bit Timer/Counter with Autoreload)................50
Mode 3 (Two 8-Bit Timer/Counters)...................................50
Timer/Counter 2 Data Registers...........................................51
Timer/Counter 2 Operating Modes .........................................52
16-Bit Autoreload Mode.........................................................52
16-Bit Capture Mode..............................................................52
UART Serial Interface.................................................................53
SBUF.........................................................................................53
Mode 0: 8-Bit Shift Register Mode .......................................54
Mode 1: 8-Bit UART, Variable Baud Rate ............................54
Mode 2: 9-Bit UART with Fixed Baud Rate ........................55
Mode 3: 9-Bit UART with Variable Baud Rate....................55
UART Serial Port Baud Rate Generation ............................55
Timer 2 Generated Baud Rates .............................................56
Interrupt System..........................................................................57
Interrupt Priority ....................................................................59
Interrupt Vectors.....................................................................59
ADuC814 Hardware Design Considerations..............................60
Clock Oscillator...........................................................................60
Power Supplies.............................................................................60
Power Consumption...................................................................60
Power-Saving Modes..............................................................61
Power-On Reset ......................................................................61
Grounding and Board Layout Recommendations.............61
Other Hardware Considerations...............................................62
In-Circuit Serial Download Access ......................................62
Embedded Serial Port Debugger ..........................................62
Single-Pin Emulation Mode..................................................63
Timing Specifications .....................................................................64
Outline Dimensions........................................................................70
Ordering Guide ...........................................................................71
REVISION HISTORY
12/03 – Data Sheet Changed from REV. 0 to REV. A
Added detailed description of product ........................... Universal
Changes to Specifications.................................................................4
Updated Outline Dimensions........................................................70
Changes to Ordering Guide...........................................................71
ADuC814
Rev. A | Page 4 of 72
SPECIFICATIONS
Table 1. AVDD = DVDD = 2.7 V to 3.3 V or 4.5 V to 5.5 V, VREF = 2.5 V internal reference, XTAL1/XTAL2 = 32.768 kHz crystal. All
specifications TMIN to TMAX, unless otherwise specified1
Parameter VDD = 5 V VDD = 3 V Unit Test Conditions
ADC CHANNEL SPECIFICATIONS
A GRADE
DC ACCURACY2,3 fSAMPLE = 147 kHz
Resolution 12 12 Bits
Integral Nonlinearity 2 2 LSB max 2.5 V internal reference
1 1 LSB typ
2.5 2.5 LSB typ 1.0 V external reference
Differential Nonlinearity 4 4 LSB max 2.5 V internal reference
2 2 LSB typ
5 5 LSB typ 1.0 V external reference
CALIBRATED ENDPOINT ERRORS4, 5
Offset Error 5 5 LSB max
Offset Error Match 1 1 LSB typ
Gain Error 5 5 LSB max
Gain Error Match 1 1 LSB typ
DYNAMIC PERFORMANCE6 fIN = 10 kHz sine wave
f
SAMPLE = 147 kHz
Signal to Noise Ratio (SNR)7 62.5 62.5 dB typ
Total Harmonic Distortion (THD) –65 –65 dB typ
Peak Harmonic or Spurious Noise –65 –65 dB typ
Channel-to-Channel Crosstalk8 –80 –80 dB typ
B GRADE
DC ACCURACY2, 3 f
SAMPLE = 147 kHz
Resolution 12 12 Bits
Integral Nonlinearity 1 1 LSB max 2.5 V internal reference
0.3 0.3 LSB typ
1.5 1.5 LSB max 1.0 V external reference11
Differential Nonlinearity 0.9 0.9 LSB max 2.5 V internal reference
0.25 0.25 LSB typ
+1.5/–0.9 1.5/–0.9 LSB max 1.0 V external reference11
Code Distribution 1 1 LSB typ ADC input is a dc voltage
CALIBRATED ENDPOINT ERRORS4, 5
Offset Error 2 3 LSB max
Offset Error Match 1 1 LSB typ
Gain Error 2 3 LSB max
Gain Error Match 1 1 LSB typ
DYNAMIC PERFORMANCE6 fIN = 10 kHz sine wave
f
SAMPLE = 147 kHz
Signal to Noise Ratio (SNR)7 71 71 dB typ
Total Harmonic Distortion (THD) –85 –85 dB typ
Peak Harmonic or Spurious Noise –85 –85 dB typ
Channel-to-Channel Crosstalk8 –80 –80 dB typ
ANALOG INPUT
Input Voltage Ranges 0 to VREF 0 to VREF V
Leakage Current 1 1 µA max
Input Capacitance 32 32 pF typ
ADuC814
Rev. A | Page 5 of 72
Parameter VDD = 5 V VDD = 3 V Unit Test Conditions
TEMPERATURE MONITOR9
Voltage Output at 25ºC 650 650 mV typ
Voltage TC –2 –2 mV/ºC typ
Accuracy 3 3 ºC typ 2.5 V internal reference
Accuracy 1.5 1.5 ºC typ 2.5 V external reference
DAC CHANNEL SPECIFICATIONS DAC Load to AGND RL = 10 kΩ, CL = 100 pF
DC ACCURACY10
Resolution 12 12 Bits
Relative Accuracy +3 +3 LSB typ
Differential Nonlinearity11 –1 –1 LSB max Guaranteed montonic
1/2 1/2 LSB typ
Offset Error 50 50 mV max VREF range
Gain Error 1 1 % max VREF range
1 1 % typ AVDD range
Gain Error Mismatch 0.5 0.5 % typ Of full scale on DAC1
ANALOG OUTPUTS
Voltage Range_0 0 to VREF Volts DAC VREF = 2.5 V
Voltage Range_1 0 to VDD Volts DAC VREF = VDD
Output Impedance 0.5 0.5 Ω typ
ISINK 50 50 µA typ
DAC AC Specifications
Voltage Output Settling Time 15 15 µs typ Full-scale settling time to within ½ LSB of final
value
Digital-to-Analog Glitch Energy 10 10 nVs typ 1 LSB change at major carry
REFERENCE INPUT/OUTPUT
REFERENCE OUTPUT
Output Voltage (VREF) 2.5 2.5 V
Accuracy 2.5 2.5 % max Of VREF measured at the CREF pin
Power Supply Rejection 47 57 dB typ
Reference Tempco 100 100 ppm/ºC typ
Internal VREF Power-On Time12 80 80 ms typ
EXTERNAL REFERENCE INPUT13 Internal band gap reference deselected via
ADCCON2.6
Voltage Range (VREF)14 1.0 1.0 V min
V
DD VDD V max
Input Impedance 20 20 kΩ typ
Input Leakage 10 10 µA max
POWER SUPPLY MONITOR (PSM)
VDD Trip Point Selection Range 2.63 2.63 V
2.93 2.93 V Four trip points selectable in this range
3.08 3.08 V programmed via TP1–0 in PSMCON
4.63 V
VDD Power Supply Trip Point Accuracy 3.5 3.5 % max
WATCH DOG TIMER (WDT)14
Timeout Period 0 0 ms min Nine time-out periods selectable in this range
2000 2000 ms max programmed via PRE3–0 in WDCON
LOGIC INPUTS
INPUT VOLTAGES14
All Inputs except SCLOCK, RESET, and
XTAL1
VINL, Input Low Voltage 0.8 0.4 V max
VINH, Input High Voltage 2.0 2.0 V min
ADuC814
Rev. A | Page 6 of 72
Parameter VDD = 5 V VDD = 3 V Unit Test Conditions
SCLOCK and RESET Only14
(Schmitt-Triggered Inputs)
VT+ 1.3 0.95 V min
3.0 2.5 V max
VT– 0.8 0.4 V min
1.4 1.1 V max
VT+ – VT– 0.3 0.3 V min
0.85 0.85 V max
INPUT CURRENTS
P1.2–P1.7, DLOAD ±10 ±10 µA max VIN = 0 V or VDD
SCLOCK15 –10 –3 µA min VIN = 0 V, internal pull-up
–40 –15 µA max VIN = 0 V, internal pull-up
±10 ±10 µA max VIN = VDD
RESET ±10 ±10 µA max VIN = 0 V
20 10 µA min VIN = 5 V, 3 V internal pull-down
105 35 µA max VIN = 5 V, 3 V internal pull-down
P1.0, P1.1, Port 315 ±10 ±10 µA max VIN = 5 V, 3 V
(includes MISO, MOSI/SDATA and SS) 1 1 µA typ
–180 –70 µA min VIN = 2 V, VDD = 5 V, 3 V
–660 –200 µA max
–360 –100 µA typ
–20 –5 µA min VIN = 450 mV, VDD = 5 V, 3 V
–75 –25 µA max
–38 –12 µA typ
INPUT CAPACITANCE 5 5 pF typ All digital inputs
CRYSTAL OSCILLATOR
(XTAL1 AND XTAL2)
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage 0.8 0.4 V typ
VINH, Input High Voltage 3.5 2.5 V typ
XTAL1 Input Capacitance 18 18 pF typ
XTAL2 Output Capacitance 18 18 pF typ
DIGITAL OUTPUTS
Output High Voltage (VOH) 2.4 2.4 V min ISOURCE = 80 mA
Output Low Voltage (VOL)
Port 1.0 and Port 1.1 0.4 0.4 V max ISINK = 10 mA, TMAX = 85°C
Port 1.0 and Port 1.1 0.4 0.4 V max ISINK = 10 mA, TMAX = 125°C
SCLOCK, MISO/MOSI 0.4 0.4 V max ISINK = 4 mA
All Other Outputs 0.4 0.4 V max ISINK = 1.6 mA
MCU CORE CLOCK
MCU Clock Rate 131.1 131.1 kHz min Clock rate generated via on-chip PLL,
programmable via CD2-0 in PLLCON
16.78 16.78 MHz max
START UP TIME
At Power-On 500 500 ms typ
From Idle Mode 100 100 µs typ
From Power-Down Mode
Oscillator Running OSC_PD = 0 in PLLCON SFR
Wake-Up with INT0 Interrupt 100 100 µs typ
Wake-Up with SPI/I2C Interrupt 100 100 µs typ
Wake-Up with TIC Interrupt 100 100 µs typ
Wake-Up with External RESET 3 3 ms typ
ADuC814
Rev. A | Page 7 of 72
Parameter VDD = 5 V VDD = 3 V Unit Test Conditions
Oscillator Powered Down16 OSC_PD = 1 in PLLCON SFR
Wake-Up with INT0 Interrupt 150 400 ms typ
Wake-Up with SPI/I2C Interrupt 150 400 ms typ
Wake-Up with External RESET 150 400 ms typ
After External RESET in Normal Mode 3 3 ms typ
After WDT Reset in Normal Mode 3 3 ms typ Controlled via WDCON SFR
FLASH/EE MEMORY RELIABILITY
CHARACTERISTICS17
Endurance18 100,000 100,000 Cycles min
Data Retention19 100 100 Years min
POWER REQUIREMENTS20, 21
Power Supply Voltages
AVDD/DVDD – AGND 2.7 V min AVDD/DVDD = 3 V nom
3.3 V max
4.5 V min AVDD/DVDD = 5 V nom
5.5 V max
Power Supply Currents, Normal Mode
DVDD Current14 5 2.5 mA max Core CLK = 2.097 MHz
4 2 mA typ (CD bits in PLLCON = 3)
AVDD Current14 1.7 1.7 mA max
DVDD Current 20 10 mA max Core CLK = 16.78MHz (max)
16 8 mA typ (CD bits in PLLCON = 0)
AVDD Current 1.7 1.7 mA max
DVDD Current14 3.5 1.5 mA max Core CLK = 131.2 kHz (min)
2.8 1.2 mA typ (CD bits in PLLCON = 7)
AVDD Current 1.7 1.7 mA max
Power Supply Currents, Idle Mode
DVDD Current14 1.7 1.2 mA max Core CLK = 2.097 MHz
1.5 1 mA typ (CD Bits in PLLCON = 3)
AVDD Current14 0.15 0.15 mA max
DVDD Current14 6 3 mA max Core CLK = 16.78 MHz (max)
4 2.5 mA typ (CD bits in PLLCON = 0)
AVDD Current14 0.15 0.15 mA max
DVDD Current14 1.25 1 mA max Core CLK = 131 kHz (min)
1.1 0.7 mA typ (CD bits in PLLCON = 7)
AVDD Current14 0.15 0.15 mA max
Power Supply Currents, Power-Down
Mode
Core CLK = 2.097 MHz or 16.78 MHz (CD bits in
PLLCON = 3 or 0)
DVDD Current14 20 µA max Oscillator on
40 14 µA typ
AVDD Current 1 1 µA typ
DVDD Current 15 µA max Oscillator off
20 10 µA typ
AVDD Current 1 1 µA typ
Typical Additional Power Supply
Currents
Core CLK = 2.097 MHz, (CD bits in PLLCON = 3)
AVDD = DVDD = 5 V
PSM Peripheral 50 µA typ
ADC 1.5 mA typ
DAC 150 µA typ
ADuC814
Rev. A | Page 8 of 72
1Temperature range –40ºC to +125ºC.
2ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also
guaranteed during normal MicroConverter core operation.
3ADC LSB size = VREF /212, i.e., for internal VREF = 2.5 V, 1 LSB = 610 µV, and for external VREF = 1 V, 1 LSB = 244 µV.
4Offset and gain error and offset and gain error match are measured after factory calibration.
5Based on external ADC system components the user may need to execute a system calibration to remove additional external channel errors
and achieve these specifications.
6Measured with coherent sampling system using external 16.77 MHz clock via P3.5 (Pin 22).
7SNR calculation includes distortion and noise components.
8Channel-to-channel crosstalk is measured on adjacent channels.
9The temperature monitor gives a measure of the die temperature directly; air temperature can be inferred from this result.
10DAC linearity is calculated using a reduced code range of 48 to 4095, 0 V to VREF range; a reduced code range of 48 to 3950, 0 V to VDD range. DAC output load = 10 kΩ
and 100 pF.
11DAC differential nonlinearity specified on 0 V to VREF and 0 to VDD ranges.
12Measured with VREF and CREF pins decoupled with 0.1 µF capacitors to ground. Power-up time for the internal reference is determined by the value of the decoupling
capacitor chosen for both the VREF and CREF pins.
13When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the VREF and CREF pins
need to be shorted together for correct operation.
14These numbers are not production tested but are guaranteed by design and/or characterization data on production release.
15Pins configured in I2C compatible mode or SPI mode; pins configured as digital inputs during this test.
16These typical specifications assume no loading on the XTAL2 pin. Any additional loading on the XTAL2 pin increases the power-on times.
17Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory.
18Endurance is qualified to 100 kcycles as per JEDEC Std. 22, Method A117 and measured at –40ºC, +25°C, and +125°C; typical endurance at +25°C is 700 kcycles.
19Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature as shown in Figure 33 in the Flash/EE memory description section.
20Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions:
Normal Mode: Reset and all digital I/O pins = open circuit, core Clk changed via CD bits in PLLCON, core executing internal software loop.
Idle Mode: Reset and all digital I/O pins = open circuit, core Clk changed via CD bits in PLLCON, PCON.0 = 1, core execution suspended in idle mode.
Power-Down Mode: Reset and all P1.2–P1.7 pins = 0.4 V; all other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1,
Core execution suspended in power-down mode, OSC turned on or off via OSC_PD bit (PLLCON.7) in PLLCON SFR.
21DVDD power supply current increases typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle.
ADuC814
Rev. A | Page 9 of 72
ABSOLUTE MAXIMUM RATINGS
Table 2. Temperature = 25°C, unless otherwise noted
Parameter Rating
AVDD to AGND –0.3 V to +7 V
DVDD to AGND –0.3 V to +7 V
AVDD to DVDD –0.3 V to +0.3 V
AGND to DGND1 –0.3 V to +0.3 V
Analog Input Voltage to AGND2 –0.3 V to AVDD + 0.3 V
Reference Input Voltage to AGND –0.3 V to AVDD + 0.3 V
Analog Input Current (Indefinite) 30 mA
Reference Input Current (Indefinite) 30 mA
Digital Input Voltage to DGND –0.3 V to DVDD + 0.3 V
Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 97.9°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
1 AGND and DGND are shorted internally on the ADuC814.
2 Applies to Pins P1.2 to P1.7 operating in analog or digital input mode.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADuC814
Rev. A | Page 10 of 72
PIN CONFIGURATION AND FUNCTION DESCRIPTION
ADuC814
TOP VIEW
(Not to Scale)
DGND
1
DLOAD
2
P3.0/RxD
3
P3.1/TxD
4
P3.2/INT0
5
DV
DD
XTAL2
XTAL1
SCLOCK
P3.7/SDATA/MOSI
28
27
26
25
24
P3.3/INT1
6
P3.4/T0/CONVST
7
P1.0/T2
8
P1.1/T2EX
9
P3.6/MISO
P3.5/T1/SS/EXTCLK
P1.7/ADC5/DAC1
P1.6/ADC4/DAC0
23
22
21
20
RESET
10
P1.5/ADC3
19
P1.2/ADC0
11
P1.3/ADC1
12
AV
DD 13
AGND
14
P1.4/ADC2
C
REF
V
REF
AGND
18
17
16
15
02748-A-009
Figure 2. Pin Configuration
Table 3. Pin Descriptions
Pin No. Mnemonic Type Function
1 DGND S Digital Ground. Ground reference point for the digital circuitry.
2 DLOAD I Debug/Serial Download Mode. Enables when pulled high through a resistor on power-on or RESET. In
this mode, DLOAD may also be used as an external emulation I/O pin, therefore the voltage level at
this pin must not be changed during this mode of operation because it may cause an emulation
interrupt that halts code execution. User code is executed when this pin is pulled low on power-on or
RESET.
3–7 P3.0 – P3.4 I/O Bidirectional Port Pins with Internal Pull-Up Resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs,
with Port 3 pins being pulled low externally, they source current because of the internal pull-up
resistors. When driving a 0-to-1 output transition, a strong pull-up is active during S1 of the
instruction cycle. Port 3 pins also have various secondary functions which are described next.
3 P3.0/RxD I/O Receiver Data Input (asynchronous) or Data Input/Output (synchronous) in Serial (UART) Mode.
4 P3.1/TxD I/O Transmitter Data Output (asynchronous) or Clock Output (synchronous) in Serial (UART) Mode.
5 P3.2/INT0 I/O Interrupt 0, programmable edge or level-triggered interrupt input, which can be programmed to one
of two priority levels. This pin can also be used as agate control input to Timer 0.
6 P3.3/INT1 I/O Interrupt 1, programmable edge or level-triggered interrupt input, which can be programmed to one
of two priority levels. This pin can also be used as agate control input to Timer 1.
7 P3.4/T0/
CONVST
I/O Timer/Counter 0 Input and External Trigger Input for ADC Conversion Start.
8–9 P1.0–P1.1 I/O
Bidirectional Port Pins with Internal Pull-Up Resistors. Port 1 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs
,with Port 1 pins being pulled low externally, they source current because of the internal pull-up
resistors When driving a 0-to-1 output transition a strong pull-up is active during S1 of the instruction
cycle. Port 1 pins also have various secondary functions which are described as follows.
8 P1.0/T2 I/O
Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response
to a 1 to 0 transition of the T2 input.
9 P1.1/T2EX I/O Digital Input. Capture/Reload trigger for Counter 2.
10 RESET I Reset Input. A high level on this pin while the oscillator is running resets the device. There is an
internal weak pull-down and a Schmitt-trigger input stage on this pin.
11–12 P1.2–P1.3 I Port 1.2 to P1.3. These pins have no digital output drivers, i.e., they can only function as digital inputs,
for which 0 must be written to the port bit. These port pins also have the following analog functionality:
11 P1.2/ADC0 I ADC Input Channel 0. Selected via ADCCON2 SFR.
12 P1.3/ADC1 I ADC Input Channel 1. Selected via ADCCON2 SFR.
13 AVDD S Analog Positive Supply Voltage, 3 V or 5 V.
14–15 AGND G Analog Ground. Ground reference point for the analog circuitry.
16 VREF I/O
Reference Input/Output. This pin is connected to the internal reference through a switch and is the
reference source for the analog to digital converter. The nominal internal reference voltage is 2.5 V
and this appears at the pin. This pin can be used to connect an external reference to the analog to
digital converter by setting ADCCON1.6 to 1. Connect 0.1 µF between this pin and AGND.
ADuC814
Rev. A | Page 11 of 72
Pin No. Mnemonic Type Function
17 CREF I Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND.
18–21 P1.4–P1.7 I Port 1.4 to P1.7. These pins have no digital output drivers, i.e., they can only function as digital inputs,
for which 0 must be written to the port bit. These port pins also have the following analog functionality:
18 P1.4/ADC2 I ADC Input Channel 2. Selected via ADCCON2 SFR.
19 P1.5/ADC3 I ADC Input Channel 2. Selected via ADCCON2 SFR.
20 P1.6/ADC4/
DAC0
I/O ADC Input Channel 4. Selected via ADCCON2 SFR. The voltage DAC Channel 0 can also be configured
to appear on P1.6.
21 P1.7/
ADC5/DAC1
I/O ADC Input Channel 5, selected via ADCCON2 SFR. The voltage DAC Channel 1 can also be configured
to appear on P1.7.
22–24 P3.5–P3.7 I/O Bidirectional Port Pins with Internal Pull-Up Resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs
,with Port 3 pins being pulled low externally, they source current because of the internal pull-up
resistors. When driving a 0-to-1 output transition a strong pull-up is active during S1 of the instruction
cycle. Port 3 pins also have various secondary functions which are described as follows.
22 P3.5/T1 I/O Timer/Counter 1 Input. P3.5–P3.7 pins also have SPI interface functions. To enable these functions,
Bit 0 of the CFG814 SFR must be set to 1.
22 P3.5/SS
/EXTCLK
I/O This pin also functions as the Slave Select input for the SPI interface when the device is operated in
slave mode. P3.5 can also function as an input for an external clock. This clock effectively bypasses the
PLL. This function is enabled by setting Bit 1 of the CFG814 SFR.
23 P3.6/MISO I/O SPI Master Input/Slave Output Data Input/Output Pin.
24 P3.7/SDATA/
MOSI
I/O SPI Master Output/Slave Input Data Input/Output Pin.
25 SCLOCK I/O Serial Clock Pin for SPI Serial Interface Clock.
26 XTAL1 I Input to the Crystal Oscillator Inverter.
27 XTAL2 O Output from the Crystal Oscillator Inverter.
28 DVDD S Analog Positive Supply Voltage, 3 V or 5 V.
I = Input, O = Output, S = Supply, G - Ground.
The following notes apply to the entire data sheet:
• In bit designation tables, set implies a Logic 1 state, and cleared implies a Logic 0 state, unless otherwise stated.
• Set and cleared also imply that the bit is set or cleared by the ADuC814 hardware, unless otherwise stated.
• User software should not write to reserved or unimplemented bits as they may be used in future products.
ADuC814
Rev. A | Page 12 of 72
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a
point1/2 LSB below the first code transition and full scale, a
point 1/2 LSB above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000 … 000) to
(0000 … 001) from the ideal, i.e., +1/2 LSB.
Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN voltage (full-scale error has been adjusted out).
Signal-to-(Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at
the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal-to-(noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by
Signal-to =- (Noise + Distortion) = (6.02N + 1.76)
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of the
harmonics to the fundamental.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and including dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
the noise peak.
DAC SPECIFICATIONS
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error.
Voltage Output Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-sec.
ADuC814
Rev. A | Page 13 of 72
TYPICAL PERFORMANCE CURVES
The typical performance plots presented in this section
illustrate typical performance of the ADuC814 under various
operating conditions. Note that all typical plots in this section
were generated using the ADuC814BRU, i.e., the B-grade part.
Figure 3 and Figure 4 show typical ADC integral nonlinearity
(INL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V
supplies, respectively. The ADC is using its internal reference
(2.5 V) and operating at a sampling rate of 152 kHz. The typical
worst-case errors in both plots are just less than 0.3 LSBs.
ADC CODES
LSBs
0
–0.4
–0.3
–0.2
–0.1
0
0.1
0.4
0.3
0.2
1023511 35833071255920471535 4095
02748-A-010
AV
DD
/DV
DD
= 5V
f
S
= 152kHz
Figure 3. Typical INL Error, VDD = 5 V
ADC CODES
LSBs
0
–0.4
–0.3
–0.2
–0.1
0
0.1
0.4
0.3
0.2
1023511 35833071255920471535 4095
02748-A-011
AV
DD
/DV
DD
= 3V
f
S
= 152kHz
Figure 4. Typical INL Error, VDD = 3 V
Figure 5 and Figure 6 show the variation in worst-case positive
(WCP) INL and worst-case negative (WCN) INL versus
external reference input voltage.
EXTERNAL REFERENCE (V)
1.2
WCP–INL (LSBs)
0.8
0.4
0
–0.4
–0.6
1.0
0.6
0.2
–0.2
AVDD/DV
DD = 5V
fS = 152kHz
0.5 1.0 1.5 2.0 2.5 5.0
0.6
0.4
0
–0.4
–0.6
0.2
–0.2
WCN–INL (LSBs)
WCN INL
WCP INL
02748-A-012
Figure 5. Typical Worst-Case INL Error vs. VREF, VDD = 5 V
EXTERNAL REFERENCE (V)
WCP–INL (LSBs)
0.8
0.4
0
–0.4
–0.8
0.6
0.2
–0.2
AV
DD
/DV
DD
= 3V
f
S
= 152kHz
0.5 1.5 2.5
WCN–INL (LSBs)
–0.6
0.8
0.4
0
–0.4
–0.8
0.6
0.2
–0.2
–0.6
3.02.01.0
WCN INL
WCP INL
02748-A-013
Figure 6. Typical Worst-Case INL Error vs. VREF, VDD = 3 V
Figure 7 and Figure 8 show typical ADC differential nonlinearity
(DNL) errors from ADC Code 0 to Code 4095 at 5 V and 3 V
supplies, respectively. The ADC is using its internal reference
(2.5 V) and operating at a sampling rate of 152 kHz. The typical
worst-case errors in both plots are just less than 0.2 LSBs.
ADuC814
Rev. A | Page 14 of 72
ADC CODES
LSBs
0
–0.25
–0.20
–0.15
–0.10
–0.50
0
0.05
0.10
0.30
0.25
0.20
0.15
1023511 35833071255920471535 4095
02748-A-014
AV
DD
/DV
DD
= 5V
f
S
= 152kHz
Figure 7. Typical DNL Error, VDD = 5 V
ADC CODES
LSBs
0
–0.25
–0.20
–0.15
–0.10
–0.50
0
0.05
0.10
0.30
0.25
0.20
0.15
1023511 35833071255920471535 4095
02748-A-015
AV
DD
/DV
DD
= 3V
f
S
= 152kHz
Figure 8. Typical DNL Error, VDD = 3 V
Figure 9 and Figure 10 show the variation in worst-case positive
(WCP) DNL and worst-case negative (WCN) DNL versus
external reference input voltage.
EXTERNAL REFERENCE (V)
–0.6 0.5
WCP–DNL (LSBs)
1.0 2.0 2.5 5.0
–0.4
1.5
–0.2
0
0.2
0.4
0.6
WCN–DNL (LSBs)
–0.4
–0.6
–0.2
0
0.2
0.4
0.6
AV
DD
/DV
DD
= 5V
f
S
= 152kHz
WCP DNL
WCN DNL
02748-A-016
Figure 9. Typical Worst-Case DNL Error vs. VREF, VDD = 5 V
EXTERNAL REFERENCE (V)
WCP–DNL (LS Bs)
0.7
0.5
0.1
–0.5
–0.7
0.3
–0.3
AV
DD
/DV
DD
= 3V
f
S
= 152kHz
0.5 1.0 1.5 2.0 2.5 3.0
WCN–DNL (LS Bs)
WCP DNL
WCN DNL
–0.1
0.7
0.5
0.1
–0.5
–0.7
0.3
–0.3
–0.1
02748-A-017
Figure 10. Typical Worst-Case DNL Error vs. VREF, VDD = 3 V
Figure 11 shows a histogram plot of 10,000 ADC conversion
results on a dc input with VDD = 5 V. The plot illustrates an
excellent code distribution pointing to the low noise
performance of the on-chip precision ADC.
CODE
817 818 819 820 821
10000
OCCURRENCE
8000
6000
4000
2000
0
02748-A-018
Figure 11. Code Histogram plot, VDD = 5 V
Figure 12 shows a histogram plot of 10,000 ADC conversion
results on a dc input for VDD = 3 V. The plot again illustrates a
very tight code distribution of 1 LSB with the majority of codes
appearing in one output bin.
CODE
10000
817 818 819 820 821
OCCURRENCE
8000
6000
4000
2000
0
9000
7000
5000
3000
1000
02748-A-019
Figure 12. Code Histogram Plot, VDD = 3 V
ADuC814
Rev. A | Page 15 of 72
Figure 13 and Figure 14 show typical FFT plots for the ADuC814.
These plots were generated using an external clock input via
P3.5 to achieve coherent sampling. The ADC is using its internal
reference (2.5 V) sampling a full-scale, 10 kHz sine wave test
tone input at a sampling rate of 149.79 kHz. The resultant FFTs
shown at 5 V and 3 V supplies illustrate an excellent 100 dB
noise floor, a 71 dB signal-to-noise ratio (SNR), and a THD
greater than −80 dB.
20
0
–20
–40
–60
–80
–100
–120
–140
–160
dBs
20 FREQUENCY (kHz)
1007060504030
02748-A-020
AV
DD
/DV
DD
= 5V
f
S
= 149.79kHz
f
IN
= 9.910kHz
SNR = 71.3dB
THD = –88.0dB
ENOB = 11.6
Figure 13. ADuC814 Dynamic Performance at VDD = 5 V
20
0
–20
–40
–60
–80
–100
–120
–140
–160
dBs
20 FREQUENCY (kHz)
1007060504030
02748-A-021
AV
DD
/DV
DD
= 3V
f
S
= 149.79kHz
f
IN
= 9.910kHz
SNR = 71.3dB
THD = –88.0dB
ENOB = 11.6
Figure 14. ADuC814 Dynamic Performance at VDD = 3 V
Figure 15 and Figure 16 show typical dynamic performance
versus external reference voltages. Again excellent ac performance
can be observed in both plots with some roll-off being observed
as VREF falls below 1 V.
EXTERNAL REFERENCE (V)
50 0.5
SNR (dBs)
1.0 2.0 2.5 5.0
55
1.5
60
65
70
75
80
THD (dBs)
–100
–95
–90
–85
–80
–75
–70
AV
DD
/DV
DD
= 5V
f
S
= 152kHz
SNR
THD
02748-A-022
Figure 15. Typical Dynamic Performance vs. VREF, VDD = 5 V
EXTERNAL REFERENCE (V)
SNR (dBs)
80
75
65
50
70
55
AVDD/DVDD = 3V
fS = 152kHz
0.5 1.5 2.5
THD (dBs)
SNR
THD
60
–70
–75
–85
–100
–80
–95
–90
1.0 2.0 3.0
02748-A-023
Figure 16. Typical Dynamic Performance vs. VREF, VDD = 3 V
ADuC814
Rev. A | Page 16 of 72
ADuC814 ARCHITECTURE, MAIN FEATURES
The ADuC814 is a fully integrated 247 kSPS 12-bit data
acquisition system incorporating a high performance multi-
channel ADC, an 8-bit MCU, and program/data Flash/EE
memory on a single chip.
This low power device operates from a 32 kHz crystal with an
on-chip PLL generating a high frequency clock of 16.78 MHz.
This clock is, in turn, routed through a programmable clock
divider from which the MCU core clock operating frequency is
generated.
The microcontroller core is an 8052, and therefore 8051,
instruction set compatible. The microcontroller core machine
cycle consists of 12 core clock periods of the selected core
operating frequency. Eight kbytes of nonvolatile Flash/EE
program memory are provided on-chip. 640 bytes of nonvolatile
Flash/EE data memory and 256 bytes RAM are also integrated
on-chip.
The ADuC814 also incorporates additional analog functionality
with dual 12-bit DACs, a power supply monitor, and a band gap
reference. On-chip digital peripherals include a watchdog timer,
time interval counter, three timer/counters, and three serial I/O
ports (SPI, UART, I2C).
On-chip factory firmware supports in-circuit serial download
and debug modes (via UART), as well as single-pin emulation
mode via the DLOAD pin. A detailed functional block diagram
of the ADuC814 is shown in Figure 17.
The ADuC814 is supported by a QuickStart Development
System. This is a full-featured, low cost system, consisting of
PC-based (Windows compatible) hardware and software
development tools.
The part operates from a single 3 V or 5 V supply. When
operating from 3 V supplies, the power dissipation for the part
is below 10 mW. The ADuC814 is housed in a 28-lead TSSOP
package and is specified for operation over an extended
temperature range −40°C to +125°C.
DGND
SCLOCK/D0
ADuC814
BUF
P1.0 (T2)
P1.1 (T2EX)
P1.2 (AIN0)
P1.4 (AIN2)
P1.5 (AIN3)
P1.6 (AIN4/DAC0)
P1.7 (AIN5/DAC1)
P3.0 (RXD)
P3.1 (TXD)
P3.2 (INT0)
P1.3 (AIN1)
BUF
T0
T1
T2EX
T2
DAC1
DAC0
MOSI/D1
POR
P3.3 (INT1)
P3.4 (T0)
P3.5 (SS/EXTCLK)
P3.6 (MISO)
P3.7 (MOSI/D1)
DAC1
DAC0 BUF
INT0
INT1
XTAL1
XTAL2
MISO
SS
DLOAD
TxD
RxD
RESET
DV
DD
AGND
AV
DD
AGND
8052
MCU
CORE
C
REF
V
REF
TEMP MONITOR
DAC0
DAC1
V
REF
AGND
BAND GAP
REFERENCE
640 × 8
DATA
FLASH/EE
256 × 8
USER RAM
WATCHDOG
TIMER
16-BIT
COUNTER
TIMERS
TIME
INTERVAL
COUNTER
PROG.
CLOCK
DIVIDER
OSC
AND
PLL
SPI SERIAL
INTERFACE
DOWNLOADER
DEBUGGER
SINGLE-PIN
EMULATOR
ASYNCHRONOUS
SERIAL PORT
(UART)
POWER SUPPLY
MONITOR
8k × 8
PROGRAM
FLASH/EE
12-BIT
ADC
ADC
CONTROL
AND
CAL
LOGIC
DAC
CONTROL
LOGIC
AIN
MUX T/H
ADC5
ADC0
D0
D1
11
21
16
17
02748-A-024
Figure 17. ADuC814 Block Diagram
ADuC814
Rev. A | Page 17 of 72
MEMORY ORGANIZATION
The ADuC814 does not have Port 0 and Port 2 pins and
therefore does not support external program or data memory
interfaces. The device executes code from the internal 8-kByte
Flash/EE program memory. This internal code space can be
programmed via the UART serial port interface while the device
is in-circuit. The program memory space of the ADuC814 is
shown in Figure 18.
1FFFH
0000H
INTERNAL
8 kBYTE
FLASH/EE
PROGRAM
MEMORY
PROGRAM MEMORY SPACE
READ-ONLY
02748-A-025
Figure 18. Program Memory Map
The data memory address space consists of internal memory
only. The internal memory space is divided into four physically
separate and distinct blocks, namely the lower 128 bytes of
RAM, the upper 128 bytes of RAM, the 128 bytes of special
function register (SFR) area, and a 640-byte Flash/EE data
memory. While the upper 128 bytes of RAM and the SFR area
share the same address locations, they are accessed through
different addressing modes.
The lower 128 bytes of data memory can be accessed through
direct or indirect addressing, the upper 128 bytes of RAM can
be accessed through indirect addressing, and the SFR area is
accessed through direct addressing.
Also, as shown in Figure 19, an additional 640 bytes of Flash/EE
data memory are available to the user and can be accessed
indirectly via a group of control registers mapped into the SFR
area. Access to the Flash/EE data memory is discussed in detail
later as part of the Flash/EE Memory section.
SPECIAL
FUNCTION
REGISTERS
ACCESSIBLE
BY DIRECT
ADDRESSING
ONLY
640 BYTES
FLASH/EE DATA
MEMORY
ACCESSED
INDIRECTLY
VIA SFR
CONTROL REGISTERS
INTERNAL
DATA MEMORY
SPACE
ACCESSIBLE
BY
INDIRECT
ADDRESSING
ONLY
ACCESSIBLE
BY
DIRECT
AND INDIRECT
ADDRESSING
FFH
80H
7FH
00H
UPPER
128
LOWER
128
FFH
80H
DATA MEMORY SPACE
READ/WRITE
(PAGE 159)
(PAGE 0)
00H
9FH
02748-A-026
Figure 19. Data Memory Map
The lower 128 bytes of internal data memory are mapped as
shown in Figure 20. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 to R7. The next 16 bytes
(128 bits), locations 20H to 2FH above the register banks, form
a block of directly addressable bit locations at bit addresses 00H
through 7FH. The stack can be located anywhere in the internal
memory address space, and the stack depth can be expanded up
to 256 bytes.
11
10
01
00 07H
0FH
17H
1FH
2FH
7FH
00H
08H
10H
18H
20H
RESET VALUE OF
STACK POINTER
30H
FOUR BANKS OF EIGHT
REGISTERS
R0 R7
BIT-ADDRESSABLE
BIT ADDRESSES
GENERAL-PURPOSE
AREA
BANKS
SELECTED
VIA
BITS IN PSW
02748-A-027
Figure 20. Lower 128 Bytes of Internal Data Memory
RESET initializes the stack pointer to location 07H and incre-
ments it once to start from location 08H, which is also the first
register (R0) of Register Bank 1. If more than one register bank
is being used, the stack pointer should be initialized to an area
of RAM not used for data storage.
ADuC814
Rev. A | Page 18 of 72
The SFR space is mapped to the upper 128 bytes of internal
data memory space and is accessed by direct addressing only. It
provides an interface between the CPU and all on-chip periph-
erals. A block diagram showing the programming model of the
ADuC814 via the SFR area is shown in Figure 21. A complete
SFR map is shown in Figure 22.
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
MONITOR
DUAL 12-BIT DAC
SERIAL I/O
WDT
PSM
TIC
PLL
6-CHANNEL
12-BIT SAR ADC
02748-A-028
640-BYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
8-kBYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
8051
COMPATIBLE
CORE
256 BYTES
RAM
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
Figure 21. Programming Model
OVERVIEW OF MCU-RELATED SFRS
Accumulator SFR
ACC is the accumulator register and is used for math operations
including addition, subtraction, integer multiplication and
division, and Boolean bit manipulations. The mnemonics for
accumulator-specific instructions refer to the accumulator as A.
B SFR
The B register is used with the ACC for multiplication and
division operations. For other instructions it can be treated as a
general-purpose scratchpad register.
Stack Pointer SFR
The SP register is the stack pointer and is used to hold an internal
RAM address called the top of the stack. The SP register is
incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in on-chip
RAM, the SP register is initialized to 07H after a reset. This
causes the stack to begin at location 08H.
Data Pointer
The data pointer is made up of two 8-bit registers, named DPH
(high byte) and DPL (low byte). These registers provide memory
addresses for internal code access. The pointer may be manipu-
lated as a 16-bit register (DPTR = DPH, DPL), or as two inde-
pendent 8-bit registers (DPH, DPL).
Program Status Word SFR
The program status word (PSW) register is the program status word that contains several bits reflecting the current status of the CPU as
detailed in Table 4.
SFR Address D0H
Power-On Default 00H
Bit Addressable Yes
CY AC F0 RS1 RS0 OV F1 P
Table 4. PSW SFR Bit Designations
Bit No. Name Description
7 CY Carry Flag.
6 AC Auxiliary Carry Flag.
5 F0 General-Purpose Flag.
4 RS1 Register Bank Select Bits.
3 RS0 RS1 RS0 Selected Bank
0 0 0
0 1 1
1 0 2
1 1 3
2 OV Overflow Flag.
1 F1 General-Purpose Flag.
0 P Parity Bit.
ADuC814
Rev. A | Page 19 of 72
Power Control SFR
The power control (PCON) register contains bits for power-saving options and general-purpose status flags as shown in Table 5.
SFR Address 87H
Power-On Default 00H
Bit Addressable No
SMOD SERIPD INT0PD --- GF1 GF0 PD IDL
Table 5. PCON SFR Bit Designations
Bit No. Name Description
7 SMOD Double UART Baud Rate.
6 SERIPD SPI Power-Down Interrupt Enable.
5 INT0PD
INT0 Power-Down Interrupt Enable.
4 RSVD Reserved.
3 GF1 General-Purpose Flag Bit.
2 GF0 General-Purpose Flag Bit.
1 PD Power-Down Mode Enable.
0 IDL Idle Mode Enable.
ADuC814
Rev. A | Page 20 of 72
SPECIAL FUNCTION REGISTERS
All registers, except the program counter and the four general-
purpose register banks, reside in the SFR area. The SFR registers
include control, configuration, and data registers that provide an
interface between the CPU and all on-chip peripherals.
Figure 22 shows a full SFR memory map and SFR contents on
RESET; NOT USED indicates unoccupied SFR locations.
Unoccupied locations in the SFR address space are not
implemented, i.e., no register exists at this location. If an
unoccupied location is read, an unspecified value is returned.
SFR locations reserved for future use are shaded (RESERVED)
and should not be accessed by the user software.
RESERVEDRESERVED
NOT USED RESERVED
RESERVEDRESERVED RESERVED RESERVED RESERVED RESERVED
RESERVED
NOT USED NOT USED
NOT USED
NOT USED
RESERVED
SPICON
1
F8H
04H
DAC0L
F9H 00H
DAC0H
FAH 00H
DAC1L
FBH 00H
DAC1H
FCH 00H
DACCON
FDH 04H RESERVED
B
1
F0H 00H
ADCOFSL
F1H 00H
ADCOFSH
F2H 20H
ADCGAINL
F3H 00H
ADCGAINH
F4H 00H
ADCCON3
F5H 00H RESERVED
DCON
1
E8H 00H RESERVED
ACC
1
E0H 00H RESERVED
ADCCON2
1
D8H 00H
ADCDATAL
D9H 00H
ADCDATAH
DAH 00H RESERVED
PSW
1
D0H 00H RESERVED
T2CON
1
C8H 00H
RCAP2L
CAH 00H
RCAP2H
CBH 00H
TL2
CCH 00H
TH2
CDH 00H RESERVED
WDCON
1
C0H 10H
CHIPID
C2H 0XH
IP
1
B8H 00H
ECON
B9H 00H
EDATA1
BCH 00H
ETIM2
BBH 00H
ETIM1
BAH 00H
EDATA2
BDH 00H
IE
1
A8H 00H
IEIP2
A9H A0H
SCON
1
98H 00H
I2CDAT
9AH 00H
I2CADD
9BH 55H
SBUF
99H 00H NOT USEDNOT USED
P1
1,2
90H FFH NOT USED
TCON
1
88H 00H
TMOD
89H 00H
TL0
8AH 00H
TL1
8BH 00H
TH0
8CH 00H
TH1
8DH 00H
SP
81H 07H
DPL
82H 00H
DPH
83H 00H
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVED
RESERVEDRESERVEDRESERVED
RESERVED
RESERVED
NOT USED
P3
1
B0H FFH
NOT USEDNOT USEDNOT USEDNOT USEDNOT USED
SPIDAT
F7H 00H
ADCCON1
EFH 00H
RESERVED
PSMCON
DFH DEH
EDARL
C6H 00H
EDATA3
BEH 00H
EDATA4
BFH 00H
NOT USED
PCON
87H 00H
ISPI
FFH
0
WCOL
FEH 0
SPE
FDH 0
SPIM
FCH 0
CPOL
FBH 0
CPHA
FAH
SPR1
F9H 0
SPR0
5
F8H
0
BITS
F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H F1H 0 F0H 0
BITS
D1
EFH
0
EEH 0
D0
EDH 0 ECH 0 EBH 0 EAH E9H 0 E8H 0
BITS
E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H E1H 0 E0H 0
BITS
ADCI
DFH
0
ADCSPI
DEH 0
CCONV
DDH 0
SCONV
DCH 0
CS3
DBH 0
CS2
DAH
CS1
D9H 0
CS0
D8H
0
BITS
CY
D7H 0
AC
D6H 0
F0
D5H 0
RS1
D4H 0
RS0
D3H 0
OV
D2H
FI
D1H 0
P
D0H 0
BITS
TF2
CFH 0
EXF2
CEH 0
RCLK
CDH 0
TCLK
CCH 0
EXEN2
CBH 0
TR2
CAH
CNT2
C9H 0
CAP2
C8H 0
BITS
PRE3
C7H 0
PRE2
C6H 0
PRE1
C5H 0 C4H 1
WDIR
C3H 0
WDS
C2H
WD
C1H 0
WDWR
C0H 0
BITS
PSI
BFH 0
PADC
BEH 0
PT2
BDH 0
PS
BCH 0
PT1
BBH 0
PX1
BAH
PT0
B9H 0
PX0
B8H 0
BITS
RD
B7H 1
WR
B6H 1
T1
B5H 1
T0
B4H 1
INT1
B3H 1
INT0
B2H
TxD
B1H 1
RxD
B0H 1
BITS
EA
AFH
EADC
AEH
ET2
ADH
ES
ACH 0
ET1
ABH 0
EX1
AAH
ET0
A9H 0
EX0
A8H 0
BITS
SM0
9FH 0
SM1
9EH 0
SM2
9DH 0
REN
9CH 0
TB8
9BH 0
RB8
9AH
TI
99H 0
RI
98H 0
BITS
97H 1 96H 1 95H 1 94H 1 93H 1 92H
T2EX
91H 1
T2
90H 1
BITS
TF1
8FH 0
TR1
8EH 0
TF0
8DH 0
TR0
8CH 0
IE1
8BH 0
IT1
8AH
IE0
89H 0
IT0
88H 0
BITS
1
0
1
0
IE0
89H 0
IT0
88H 0
TCON
88H 00H
MNEMONIC
SFR ADDRESS
DEFAULT VALUE
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
THESE BITS ARE CONTAINED IN THIS BYTE.
SFR MAP KEY:
1
RESERVEDRESERVED
RESERVED
0
0
0
0
0
0
0
0
0
000
TIMECON HTHSEC SEC MIN HOUR INTVAL
A1H A2H A3H A4H A5H A6H
00H 00H 00H 00H 00H 00H
RESERVED RESERVED RESERVED RESERVED RESERVED
RESERVED RESERVED
CFG814
9CH 04H
RESERVED RESERVED
D1EN D0EN
RESERVED
PRE0
PLLCON
D7H 53H
02748-0-029
Figure 22. Special Function Register Locations and Reset Values
Note the following about SFRs:
• SFRs whose address ends in 0H or 8H are bit addressable.
• Only P1.0 and P1.1 can operate as digital I/O pins. P1.2–P1.7 can be configured as analog inputs (ADC inputs) or as digital inputs.
• The CHIPID SFR contains the silicon revision ID byte and may change for future silicon revisions.
• These registers are reconfigured at power-on with factory calculated calibration coefficients that can be overwritten by user code. See
the calibration options in ADCCON3 SFR.
• When the SPIM bit in the SPICON SFR is cleared, the SPR0 bit reflects the level on the SS pin (Pin 22).
ADuC814
Rev. A | Page 21 of 72
ADC CIRCUIT INFORMATION
GENERAL OVERVIEW
The ADC block incorporates a 4.05 msec, 6-channel, 12-bit
resolution, single-supply ADC. This block provides the user
with a multichannel multiplexer, track-and-hold amplifier, on-
chip reference, offset calibration features and ADC. All compo-
nents in this block are easily configured via a 3-register SFR
interface.
The ADC consists of a conventional successive-approximation
converter based around a capacitor DAC. The converter accepts
an analog input range of 0 V to VREF. A precision, factory cali-
brated 2.5 V reference is provided on-chip. An external reference
may also be used via the external VREF pin. This external refer-
ence can be in the range 1.0 V to AVDD.
Single or continuous conversion modes can be initiated in
software. In hardware, a convert signal can be applied to an
external pin (CONVST), or alternatively Timer 2 can be config-
ured to generate a repetitive trigger for ADC conversions.
The ADuC814 has a high speed ADC to SPI interface data
capture logic implemented on-chip. Once configured, this logic
transfers the ADC data to the SPI interface without the need for
CPU intervention.
The ADC has six external input channels. Two of the ADC
channels are multiplexed with the DAC outputs, ADC4 with
DAC0, and ADC5 with DAC1. When the DAC outputs are in
use, any ADC conversion on these channels represents the DAC
output voltage. Due care must be taken to ensure that no
external signal is trying to drive these ADC/DAC channels
while the DAC outputs are enabled.
In addition to the six external channels of the ADC, five internal
signals are also routed through the front end multiplexer. These
signals include a temperature m