W9725G6KB
4M 4 BANKS 16 BIT DDR2 SDRAM
Publication Release Date: Feb. 07, 2017
Revision: A04
- 1 -
Table of Contents-
1. GENERAL DESCRIPTION ................................................................................................................... 4
2. FEATURES ........................................................................................................................................... 4
3. ORDER INFORMATION ....................................................................................................................... 5
4. KEY PARAMETERS ............................................................................................................................. 5
5. BALL CONFIGURATION ...................................................................................................................... 6
6. BALL DESCRIPTION ............................................................................................................................ 7
7. BLOCK DIAGRAM ................................................................................................................................ 8
8. FUNCTIONAL DESCRIPTION .............................................................................................................. 9
8.1 Power-up and Initialization Sequence ................................................................................................... 9
8.2 Mode Register and Extended Mode Registers Operation ................................................................... 10
8.2.1 Mode Register Set Command (MRS)............................................................................... 10
8.2.2 Extend Mode Register Set Commands (EMRS) .............................................................. 11
8.2.2.1 Extend Mode Register Set Command (1), EMR (1) ................................................ 11
8.2.2.2 DLL Enable/Disable ................................................................................................ 12
8.2.2.3 Extend Mode Register Set Command (2), EMR (2) ................................................ 13
8.2.2.4 Extend Mode Register Set Command (3), EMR (3) ................................................ 14
8.2.3 Off-Chip Driver (OCD) Impedance Adjustment ................................................................ 15
8.2.3.1 Extended Mode Register for OCD Impedance Adjustment .................................... 16
8.2.3.2 OCD Impedance Adjust .......................................................................................... 16
8.2.3.3 Drive Mode ............................................................................................................. 17
8.2.4 On-Die Termination (ODT) ............................................................................................... 18
8.2.5 ODT related timings ......................................................................................................... 18
8.2.5.1 MRS command to ODT update delay ..................................................................... 18
8.3 Command Function ............................................................................................................................. 20
8.3.1 Bank Activate Command .................................................................................................. 20
8.3.2 Read Command ............................................................................................................... 20
8.3.3 Write Command ............................................................................................................... 21
8.3.4 Burst Read with Auto-precharge Command ..................................................................... 21
8.3.5 Burst Write with Auto-precharge Command ..................................................................... 21
8.3.6 Precharge All Command .................................................................................................. 21
8.3.7 Self Refresh Entry Command .......................................................................................... 21
8.3.8 Self Refresh Exit Command ............................................................................................. 22
8.3.9 Refresh Command ........................................................................................................... 22
8.3.10 No-Operation Command .................................................................................................. 23
8.3.11 Device Deselect Command .............................................................................................. 23
8.4 Read and Write access modes ........................................................................................................... 23
8.4.1 Posted
CAS
................................................................................................................... 23
8.4.1.1 Examples of posted
CAS
operation ..................................................................... 23
8.4.2 Burst mode operation ....................................................................................................... 24
8.4.3 Burst read mode operation ............................................................................................... 25
8.4.4 Burst write mode operation .............................................................................................. 25
8.4.5 Write data mask ............................................................................................................... 26
8.5 Burst Interrupt ..................................................................................................................................... 26
8.6 Precharge operation ............................................................................................................................ 27
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 2 -
8.6.1 Burst read operation followed by precharge ..................................................................... 27
8.6.2 Burst write operation followed by precharge .................................................................... 27
8.7 Auto-precharge operation ................................................................................................................... 27
8.7.1 Burst read with Auto-precharge ....................................................................................... 28
8.7.2 Burst write with Auto-precharge ....................................................................................... 28
8.8 Refresh Operation ............................................................................................................................... 29
8.9 Power Down Mode .............................................................................................................................. 29
8.9.1 Power Down Entry ........................................................................................................... 30
8.9.2 Power Down Exit .............................................................................................................. 30
8.10 Input clock frequency change during precharge power down ............................................................. 30
9. OPERATION MODE ........................................................................................................................... 31
9.1 Command Truth Table ........................................................................................................................ 31
9.2 Clock Enable (CKE) Truth Table for Synchronous Transitions ........................................................... 32
9.3 Data Mask (DM) Truth Table ............................................................................................................... 32
9.4 Function Truth Table ........................................................................................................................... 33
9.5 Simplified Stated Diagram ................................................................................................................... 36
10. ELECTRICAL CHARACTERISTICS ................................................................................................... 37
10.1 Absolute Maximum Ratings ................................................................................................................ 37
10.2 Operating Temperature Condition ....................................................................................................... 37
10.3 Recommended DC Operating Conditions ........................................................................................... 37
10.4 ODT DC Electrical Characteristics ...................................................................................................... 38
10.5 Input DC Logic Level ........................................................................................................................... 38
10.6 Input AC Logic Level ........................................................................................................................... 38
10.7 Capacitance ........................................................................................................................................ 39
10.8 Leakage and Output Buffer Characteristics ........................................................................................ 39
10.9 DC Characteristics .............................................................................................................................. 40
10.10 IDD Measurement Test Parameters .......................................................................................... 42
10.11 AC Characteristics ..................................................................................................................... 43
10.11.1 AC Characteristics and Operating Condition for -18 speed grade ................................... 43
10.11.2 AC Characteristics and Operating Condition for -25/25I/-3 speed grade ......................... 45
10.12 AC Input Test Conditions ........................................................................................................... 66
10.13 Differential Input/Output AC Logic Levels .................................................................................. 66
10.14 AC Overshoot / Undershoot Specification ................................................................................. 67
10.14.1 AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 67
10.14.2 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: .......... 67
11. TIMING WAVEFORMS ....................................................................................................................... 68
11.1 Command Input Timing ....................................................................................................................... 68
11.2 ODT Timing for Active/Standby Mode ................................................................................................. 69
11.3 ODT Timing for Power Down Mode .................................................................................................... 69
11.4 ODT Timing mode switch at entering power down mode .................................................................... 70
11.5 ODT Timing mode switch at exiting power down mode ...................................................................... 71
11.6 Data output (read) timing .................................................................................................................... 72
11.7 Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................ 72
11.8 Data input (write) timing ...................................................................................................................... 73
11.9 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) .................................................................... 73
11.10 Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ...................................... 74
11.11 Seamless burst write operation: RL = 5 ( WL = 4, BL = 4) ......................................................... 74
11.12 Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) ............................................................. 75
11.13 Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) .................................................. 75
11.14 Write operation with Data Mask: WL=3, AL=0, BL=4) ............................................................... 76
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 3 -
11.15 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP 2clks) ............ 77
11.16 Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP 2clks) ............ 77
11.17 Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP 2clks) ............ 78
11.18 Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP 2clks) ............ 78
11.19 Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............ 79
11.20 Burst write operation followed by precharge: WL = (RL-1) = 3 .................................................. 79
11.21 Burst write operation followed by precharge: WL = (RL-1) = 4 .................................................. 80
11.22 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP 2clks) ............... 80
11.23 Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ............... 81
11.24 Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP 2clks) ....................................................................................... 81
11.25 Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP 2clks) ....................................................................................... 82
11.26 Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 ................................. 82
11.27 Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 ....................... 83
11.28 Self Refresh Timing ................................................................................................................... 83
11.29 Basic Power Down Entry and Exit Timing.................................................................................. 84
11.30 Precharged Power Down Entry and Exit Timing ........................................................................ 84
11.31 Clock frequency change in precharge Power Down mode ........................................................ 85
12. PACKAGE SPECIFICATION .............................................................................................................. 86
13. REVISION HISTORY .......................................................................................................................... 87
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 4 -
1. GENERAL DESCRIPTION
The W9725G6KB is a 256M bits DDR2 SDRAM, organized as 4,194,304 words 4 banks 16 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for general
applications. W9725G6KB is sorted into the following speed grades: -18, -25, 25I and -3. The -18
grade parts is compliant to the DDR2-1066 (7-7-7) specification. The -25 and 25I grade parts are
compliant to the DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade parts
which is guaranteed to support -40°C TCASE 95°C). The -3 grade parts is compliant to the DDR2-
667 (5-5-5) specification.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and
CLK
falling). All
I/Os are synchronized with a single ended DQS or differential DQS-
DQS
pair in a source
synchronous fashion.
2. FEATURES
Power Supply: VDD, VDDQ = 1.8 V ± 0.1V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and
DQS
) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and
CLK
)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted
CAS
programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8x12.5 mm2), using Lead free materials with RoHS compliant
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 5 -
3. ORDER INFORMATION
PART NUMBER
SPEED GRADE
OPERATING TEMPERATURE
W9725G6KB-18
DDR2-1066 (7-7-7)
C TCASE 85°C
W9725G6KB-25
DDR2-800 (5-5-5) or DDR2-800 (6-6-6)
C TCASE 85°C
W9725G6KB25I
DDR2-800 (5-5-5) or DDR2-800 (6-6-6)
-40°C TCASE 95°C
W9725G6KB-3
DDR2-667 (5-5-5)
C TCASE 85°C
4. KEY PARAMETERS
SYM.
DDR2-1066
DDR2-800
DDR2-667
7-7-7
5-5-5/6-6-6
5-5-5
-18
-25/25I
-3
tCK(avg)
Average clock period
@CL = 7
Min.
1.875 nS
Max.
7.5 nS
@CL = 6
Min.
2.5 nS
2.5 nS
Max.
7.5 nS
8 nS
@CL = 5
Min.
3 nS
2.5 nS
3 nS
Max.
7.5 nS
8 nS
8 nS
@CL = 4
Min.
3.75 nS
3.75 nS
3.75 nS
Max.
7.5 nS
8 nS
8 nS
@CL = 3
Min.
5 nS
5 nS
Max.
8 nS
8 nS
tRCD
Active to Read/Write Command Delay Time
Min.
13.125 nS
12.5 nS
15 nS
tRP
Precharge to Active Command Period
Min.
13.125 nS
12.5 nS
15 nS
tRC
Active to Ref/Active Command Period
Min.
58.125 nS
57.5 nS
60 nS
tRAS
Active to Precharge Command Period
Min.
45 nS
45 nS
45 nS
IDD0
Operating current
Max.
70 mA
60 mA
55 mA
IDD1
Operation current (Single bank)
Max.
80 mA
70 mA
65 mA
IDD4R
Operating burst read current
Max.
125 mA
105 mA
95 mA
IDD4W
Operating burst write current
Max.
130 mA
110 mA
100 mA
IDD5B
Burst refresh current
Max.
75 mA
70 mA
65 mA
IDD6
Self refresh current (TCASE 85°C)
Max.
6 mA
6 mA
6 mA
IDD7
Operating bank interleave read current
Max.
160 mA
135 mA
115 mA
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 6 -
5. BALL CONFIGURATION
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
VSSQ
UDQS
VDDQ
LDQS
VDDQ
CAS
A2
A6
UDQS
VSSQ
DQ8
VSSQ
DQ0
CLK
A0
A4
CLK
CS
VDDQ
VDDQ
DQ7
VDD
ODT
VDD
DQ14
VDDQ
DQ12
NC
VDDL
NC
VSSQ
DQ9
VSSQ
A3
CKE
BA0BA1
WE
DQ3
LDM
VSS
DQ11
VDDQ
VSS
UDM
VDD
DQ6
VDDQ
DQ4
VSS
VDD A12 NC NCNC
A11 A8A9A7
A5
A1
A10/AP
VSSVREF
DQ1
VSSQ
VDDQ
VSSQ
NC VSSQ LDQS
VSSQDQ10
DQ15
DQ13
VDDQ
VDDQ
DQ5
VDD
VSS
M
N
P
R
VSSQDQ2
VSSDL
RAS
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 7 -
6. BALL DESCRIPTION
BALL NUMBER
SYMBOL
FUNCTION
DESCRIPTION
M8,M3,M7,N2,N8,N3
,N7,P2,P8,P3,M2,P7
,R2
A0A12
Address
Provide the row address for active commands, and the column address
and Auto-precharge bit for Read/Write commands to select one
location out of the memory array in the respective bank.
Row address: A0−A12.
Column address: A0−A8. (A10 is used for Auto-precharge)
L2,L3
BA0BA1
Bank Select
BA0BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
G8,G2,H7,H3,H1,H9
,F1,F9,C8,C2,D7,D3,
D1,D9,B1,B9
DQ0DQ15
Data Input
/ Output
Bi-directional data bus.
K9
ODT
On Die
Termination
Control
ODT (registered HIGH) enables termination resistance internal to the
DDR2 SDRAM.
F7,E8
LDQS,
LDQS
LOW Data Strobe
Data Strobe for Lower Byte: Output with read data, input with write data
for source synchronous operation. Edge-aligned with read data, center-
aligned with write data. LDQS corresponds to the data on DQ0DQ7.
LDQS
is only used when differential data strobe mode is enabled via
the control bit at EMR (1)[A10 EMRS command].
B7,A8
UDQS,
UDQS
UP Data Strobe
Data Strobe for Upper Byte: Output with read data, input with write data
for source synchronous operation. Edge-aligned with read data, center-
aligned with write data. UDQS corresponds to the data on DQ8DQ15.
UDQS
is only used when differential data strobe mode is enabled via
the control bit at EMR (1)[A10 EMRS command].
L8
CS
Chip Select
All commands are masked when
CS
is registered HIGH.
CS
provides for external rank selection on systems with multiple ranks.
CS
is considered part of the command code.
K7,L7,K3
RAS
,
CAS
,
WE
Command Inputs
RAS
,
CAS
and
WE
(along with
CS
) define the command being
entered.
B3,F3
UDM, LDM
Input Data Mask
DM is an input mask signal for write data. Input data is masked when
DM is sampled high coincident with that input data during a Write
access. DM is sampled on both edges of DQS. Although DM pins are
input only, the DM loading matches the DQ and DQS loading.
J8,K8
CLK,
CLK
Differential Clock
Inputs
CLK and
CLK
are differential clock inputs. All address and control
input signals are sampled on the crossing of the positive edge of CLK
and negative edge of
CLK
. Output (read) data is referenced to the
crossings of CLK and
CLK
(both directions of crossing).
K2
CKE
Clock Enable
CKE (registered HIGH) activates and CKE (registered LOW)
deactivates clocking circuitry on the DDR2 SDRAM.
J2
VREF
Reference Voltage
VREF is reference voltage for inputs.
A1,E1,J9,M9,R1
VDD
Power Supply
Power Supply: 1.8V ± 0.1V.
A3,E3,J3,N1,P9
VSS
Ground
Ground.
A9,C1,C3,C7,C9,E9,
G1,G3,G7,G9
VDDQ
DQ Power Supply
DQ Power Supply: 1.8V ± 0.1V.
A7,B2,B8,D2,D8,E7,
F2,F8,H2,H8
VSSQ
DQ Ground
DQ Ground. Isolated on the device for improved noise immunity.
A2,E2,L1,R3,R7,R8
NC
No Connection
No connection.
J7
VSSDL
DLL Ground
DLL Ground.
J1
VDDL
DLL Power Supply
DLL Power Supply: 1.8V ± 0.1V.
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 8 -
7. BLOCK DIAGRAM
CKE
A10
DLL
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE: The cell array configuration is 8192 * 512 * 16
ROW DECODER ROW DECODER
ROW DECODERROW DECODER
A0
A9
A11
A12
BA0
BA1
CS
RAS
CAS
WE
CLK
CLK
PREFETCH REGISTER
ODT
CONTROL
DQ0
|
DQ15
LDQS
LDQS
UDQS
UDQS
LDM
UDM
ODT
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 9 -
8. FUNCTIONAL DESCRIPTION
8.1 Power-up and Initialization Sequence
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures
other than those specified may result in undefined operation. The following sequence is required for
Power-up and Initialization.
1. Apply power and attempt to maintain CKE below 0.2 × VDDQ and ODT*1 at a LOW state (all other
inputs may be undefined.) Either one of the following sequence is required for Power-up.
A. The VDD voltage ramp time must be no greater than 200 mS from when VDD ramps from 300
mV to VDD min; and during the VDD voltage ramp, |VDD -VDDQ| 0.3 volts.
VDD, VDDL and VDDQ are driven from a single power converter output
VTT is limited to 0.95V max
VREF*2 tracks VDDQ/2
VDDQ VREF must be met at all times
B. Voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid
DRAM latch-up. During the ramping of the supply voltages, VDD VDDL VDDQ must be
maintained and is applicable to both AC and DC levels until the ramping of the supply voltages
is complete.
Apply VDD/VDDL*3 before or at the same time as VDDQ
Apply VDDQ*4 before or at the same time as VTT
VREF*2 tracks VDDQ/2
VDDQ VREF must be met at all times
Apply VTT
The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is
achieved on VTT must be no greater than 500 mS
2. Start Clock and maintain stable condition for 200 µS (min.).
3. After stable power and clock (CLK,
CLK
), apply NOP or Deselect and take CKE HIGH.
4. Wait minimum of 400 nS then issue precharge all command. NOP or Deselect applied during 400
nS period.
5. Issue an EMRS command to EMR (2). (To issue EMRS command to EMR (2), provide LOW to
BA0, HIGH to BA1.)
6. Issue an EMRS command to EMR (3). (To issue EMRS command to EMR (3), provide HIGH to
BA0 and BA1.)
7. Issue an EMRS command to EMR (1) to enable DLL. (To issue DLL Enable command, provide
LOW to A0, HIGH to BA0 and LOW to BA1. And A9=A8=A7=LOW must be used when issuing this
command.)
8. Issue a Mode Register Set command for DLL reset. (To issue DLL Reset command, provide HIGH
to A8 and LOW to BA0 and BA1.)
9. Issue a precharge all command.
10. Issue 2 or more Auto Refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating
parameters without resetting the DLL.)
12. At least 200 clocks after step 8, execute OCD Calibration (Off Chip Driver impedance adjustment).
If OCD calibration is not used, EMRS to EMR (1) to set OCD Calibration Default
(A9=A8=A7=HIGH) followed by EMRS to EMR (1) to exit OCD Calibration Mode
(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 SDRAM is now ready for normal operation.
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 10 -
Notes:
1. To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
2. VREF must be within ± 300 mV with respect to VDDQ/2 during supply ramp time.
3. VDD/VDDL voltage ramp time must be no greater than 200 mS from when VDD ramps from 300 mV to VDD min.
4. The VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no
greater than 500 mS
tCH tCL
tIS
tIS
400nS
NOP PRE
ALL EMRS MRS PRE
ALL REF MRSREF EMRS EMRS ANY
CMD
tRP tMRD tMRD
tRP tRFC tRFC tOIT
Follow OCD
Flow chart OCD
CAL. Mode
Exit
OCD
Default
min 200 Cycle
DLL
Reset
DLL
Enable
CLK
CLK
CKE
Command
ODT
tMRD
Figure 1 Initialization sequence after power-up
8.2 Mode Register and Extended Mode Registers Operation
For application flexibility, burst length, burst type, CAS Latency, DLL reset function, write recovery
time (WR) are user defined variables and must be programmed with a Mode Register Set (MRS)
command. Additionally, DLL disable function, driver impedance, additive CAS Latency, ODT (On Die
Termination), single-ended strobe and OCD (off chip driver impedance adjustment) are also user
defined variables and must be programmed with an Extended Mode Register Set (EMRS) command.
Contents of the Mode Register (MR) or Extended Mode Registers EMR (1), EMR (2) and EMR (3) can
be altered by re-executing the MRS or EMRS Commands. Even if the user chooses to modify only a
subset of the MR or EMR (1), EMR (2) and EMR (3) variables, all variables within the addressed
register must be redefined when the MRS or EMRS commands are issued.
MRS, EMRS and Reset DLL do not affect array contents, which mean re-initialization including those
can be executed at any time after power-up without affecting array contents.
8.2.1 Mode Register Set Command (MRS)
(
CS
= "L",
RAS
= "L",
CAS
= "L",
WE
= "L", BA0 = "L", BA1 = "L", A0 to A12 = Register Data)
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It
programs CAS Latency, burst length, burst sequence, test mode, DLL reset, Write Recovery (WR) and
various vendor specific options to make DDR2 SDRAM useful for various applications. The default
value in the Mode Register after power-up is not defined, therefore the Mode Register must be
programmed during initialization for proper operation.
The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into
the mode register. The mode register set command cycle time (tMRD) is required to complete the write
operation to the mode register. The mode register contents can be changed using the same command
and clock cycle requirements during normal operation as long as all banks are in the precharge state.
W9725G6KB
Publication Release Date: Feb. 07, 2017
Revision: A04
- 11 -
The mode register is divided into various fields depending on functionality. Burst length is defined by
A[2:0] with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR
SDRAM. Burst address sequence type is defined by A3, CAS Latency is defined by A[6:4]. The DDR2
does not support half clock latency mode. A7 is used for test mode. A8 is used for DLL reset. A7 must
be set to LOW for normal MRS operation. Write recovery time WR is defined by A[11:9]. Refer to the
table for specific codes.
BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
PD WR DLL BTCAS Latency Burst LengthTM
A8
0
1
DLL Reset
No
Yes
BA1 BA0
0 0
0 1
1 0
1 1
MRS mode
MR
EMR (1)
EMR (2)
EMR (3)
A12
1
0Active power down exit time
Fast exit (use tXARD)
Slow exit (use tXARDS)
Burst Length
Address Field
Mode Register
Write recovery for Auto-precharge CAS Latency
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
1
0
Latency
Reserved
3
4
5
7
6
Reserved
Reserved
A2
0
0
A1
1
1
A0
0
1
BL
4
8
A11
0
0
0
0
1
1
1
1
A10
0
0
1
1
0
0
1
1
A9
0
1
0
1
0
1
1
0
WR *
Reserved
2
3
4
5
6
8
7
A7
0
1
Mode
Normal
Test
A3
0
1
Burst Type
Sequential
Interleave
0
DDR2-667
DDR2-800
DDR2-1066
DDR2-800
DDR2-1066
DDR2-667
BA1
0
Note:
1. WR (write recovery for Auto-precharge) min is determined by tCK(avg) max and WR max is determined by tCK(avg) min.
WR[cycles] = RU{ tWR[nS] / tCK(avg)[nS] }, where RU stands for round up. The mode register must be programmed to this
value. This is also used with tRP to determine tDAL.
Figure 2 Mode Register Set (MRS)
8.2.2 Extend Mode Register Set Commands (EMRS)
8.2.2.1 Extend Mode Register Set Command (1), EMR (1)
(
CS
= "L",
RAS
= "L",
CAS
= "L",
WE
= "L", BA0 = "H", BA1 = "L", A0 to A12 = Register data)
The extended mode register (1) stores the data for enabling or disabling the DLL, output driver
strength, additive latency, ODT,
DQS
disable, OCD program. The default value of the extended
mode register (1) is not defined, therefore the extended mode register (1) must be programmed during
initialization for proper operation. The DDR2 SDRAM should be in all bank precharge with CKE
already high prior to writing into the extended mode register (1). The mode register set command
cycle time (tMRD) must be satisfied to complete the write operation to the extended mode register (1).
Extended mode register (1) contents can be changed using the same command and clock cycle
requirements during normal operation as long as all banks are in the precharge state. A0 is used for
DLL enable or disable. A1 is used for enabling a reduced strength output driver. A[5:3] determines the
additive latency, A[9:7] are used for OCD control, A10 is used for
DQS
disable. A2 and A6 are used
for ODT setting.
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8.2.2.2 DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power-up initialization,
and upon returning to normal operation after having the DLL disabled. The DLL is automatically
disabled when entering Self Refresh operation and is automatically re-enabled and reset upon exit of
Self Refresh operation. Any time the DLL is enabled (and subsequently reset), 200 clock cycles must
occur before a Read command can be issued to allow time for the internal clock to be synchronized
with the external clock. Failing to wait for synchronization to occur may result in a violation of the tAC
or tDQSCK parameters.
BA1BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 OCD program BTRtt
Address Field
Extended Mode Register (1)
BA1BA0 MRS mode
0 0
00
1
1
1 1
MR
EMR (1)
EMR (2)
EMR (3)
A6 A2
0 0
00
1
1
1 1
WRAdditive Latency
Qoff 0*1DQS Rtt D.I.C DLL
Rtt (nominal)
ODT Disabled
75 ohm
150 ohm
50 ohm*2
0
A0
1
DLL Enable
Enable
Disable
OCD Calibration Program
OCD calibration mode exit; matain setting
Adjust mode*3
OCD Calibration default*4
Drive (1)
Drive (0)
A9 A8 A7
1
0 0 0
1 1
1110 0
0
0
0
0
Driver impedance adjustment
A12
1
0 Output buffer enabled
Qoff (Optional)*5
Output buffer disabled
A10
1
0DQS
Enable
Disable A10
(DQS Enable)
0 (Enable)
1 (Disable)
Strobe Function Matrix
DQS
DQS
DQS
DQS
DQS
Hi-z
Output driver
impedance control
Reduced
Normal
A1
0
1
A5
0
0
0
0
1
1
1
1
A4
0
0
1
1
0
0
1
1
A3
0
1
0
1
0
1
1
0
Latency
0
3
4
Reserved
1
2
Output Driver Impedance Control
Driver
size
100%
60%
Additive Latency
5
6
DDR2-/667/800
DDR2-1066
Notes:
1. A11 default is 0 RDQS disabled.
2. Optional for DDR2-667, mandatory for DDR2-800 and DDR2-1066.
3. When Adjust mode is issued, AL from previously set value must be applied.
4. After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to the section 8.2.3 for
detailed information.
5. Output disabled - DQs, LDQS,
LDQS
, UDQS,
UDQS
. This feature is used in conjunction with DIMM IDD measurements
when IDDQ is not desired to be included. Figure 3 EMR (1)
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8.2.2.3 Extend Mode Register Set Command (2), EMR (2)
(
CS
= "L",
RAS
= "L",
CAS
= "L",
WE
= "L", BA0 = "L", BA1 = "H", A0 to A12 = Register data)
The extended mode register (2) controls refresh related features. The default value of the extended
mode register (2) is not defined, therefore the extended mode register (2) must be programmed during
initialization for proper operation.
The DDR2 SDRAM should be in all bank precharge state with CKE already high prior to writing into
the extended mode register (2). The mode register set command cycle time (tMRD) must be satisfied to
complete the write operation to the extended mode register (2). Mode register contents can be
changed using the same command and clock cycle requirements during normal operation as long as
all banks are in the precharge state.
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 SELF
0*1
Address Field
Extended Mode Register (2)
0*1
A7
1
0Disable
High Temperature Self Refresh Rate Enable
Enable*2
BA0
1
BA1BA0MRS mode
0 0
00
1
1
1 1
MRS
EMR (1)
EMR (2)
EMR (3)
BA1
Notes:
1. The rest bits in EMR (2) is reserved for future use and all bits in EMR (2) except A7, BA0 and BA1 must be programmed to
0 when setting the extended mode register (2) during initialization.
2. When DRAM is operated at 85°C < TCASE 95°C the extended Self Refresh rate must be enabled by setting bit A7 to “1”
before the Self Refresh mode can be entered. Figure 4 EMR (2)
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8.2.2.4 Extend Mode Register Set Command (3), EMR (3)
(
CS
= "L",
RAS
= "L",
CAS
= "L",
WE
= "L", BA0 = "H", BA1 = "H", A0 to A12 = Register data)
No function is defined in extended mode register (3). The default value of the EMR (3) is not defined,
therefore the EMR (3) must be programmed during initialization for proper operation.
BA1BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1
Address Field
Extended Mode Register (3)
0*1
Note:
1. All bits in EMR (3) except BA0 and BA1 are reserved for future use and must be set to 0 when programming the EMR (3).
Figure 5 EMR (3)
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8.2.3 Off-Chip Driver (OCD) Impedance Adjustment
DDR2 SDRAM supports driver calibration feature and the flow chart in Figure 6 is an example of the
sequence. Every calibration mode command should be followed by “OCD calibration mode exit”
before any other command being issued. MRS should be set before entering OCD impedance
adjustment and On Die Termination (ODT) should be carefully controlled depending on system
environment.
Start
ALL OK
All MR shoud be programmed before entering OCD impedance adjustment and ODT should
be carefully controlled depending on system environment
EMRS: Drive(0)
DQ &DQS Low; DQS High
EMRS: OCD calibration mode exit
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec or NOP
EMRS: OCD calibration mode exit
ALL OK
EMRS: Drive(1)
DQ &DQS High; DQS Low
Test
Need Calibration
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
BL=4 code input to all DQs
Inc, Dec or NOP
EMRS: OCD calibration mode exit
EMRS: OCD calibration mode exit
End
Figure 6 OCD Impedance Adjustment Flow Chart
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8.2.3.1 Extended Mode Register for OCD Impedance Adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs
are driven out by DDR2 SDRAM. In Drive (1) mode, all DQ, DQS signals are driven HIGH and all
DQS
signals are driven LOW. In Drive (0) mode, all DQ, DQS signals are driven LOW and all
DQS
signals are driven HIGH. In adjust mode, BL = 4 of operation code data must be used. In case of OCD
calibration default, output driver characteristics have a nominal impedance value of 18 Ohms during
nominal temperature and voltage conditions. OCD applies only to normal full strength output drive
setting defined by EMR (1) and if reduced strength is set, OCD default driver characteristics are not
applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are
not applicable. After OCD calibration is completed or driver strength is set to default, subsequent
EMRS commands not intended to adjust OCD characteristics must specify A[9:7] as ’000’ in order to
maintain the default or calibrated value.
Table 1 OCD Drive Mode Program
A9
A8
A7
Operation
0
0
0
OCD calibration mode exit
0
0
1
Drive (1) DQ, DQS HIGH and
DQS
LOW
0
1
0
Drive (0) DQ, DQS LOW and
DQS
HIGH
1
0
0
Adjust mode
1
1
1
OCD calibration default
8.2.3.2 OCD Impedance Adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a
4 bit burst code to DDR2 SDRAM as in table 2. For this operation, Burst Length has to be set to BL =
4 via MRS command before activating OCD and controllers must drive the burst code to all DQs at the
same time. DT0 in table 2 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver
output impedance is adjusted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all
DQs and DQS’s of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The
maximum step count for adjustment is 16 and when the limit is reached, further increment or
decrement code has no effect. The default setting may be any step within the 16 step range. When
Adjust mode command is issued, AL from previously set value must be applied.
Table 2 OCD Adjust Mode Program
4 bit burst code inputs to all DQs
Operation
DT0
DT1
DT2
DT3
Pull-up driver strength
Pull-down driver strength
0
0
0
0
NOP (No operation)
NOP (No operation)
0
0
0
1
Increase by 1 step
NOP
0
0
1
0
Decrease by 1 step
NOP
0
1
0
0
NOP
Increase by 1 step
1
0
0
0
NOP
Decrease by 1 step
0
1
0
1
Increase by 1 step
Increase by 1 step
0
1
1
0
Decrease by 1 step
Increase by 1 step
1
0
0
1
Increase by 1 step
Decrease by 1 step
1
0
1
0
Decrease by 1 step
Decrease by 1 step
Other Combinations
Reserved
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For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as
shown in Figure 7. For input data pattern for adjustment, DT0 - DT3 is a fixed order and is not affected
by burst type (i.e., sequential or interleave).
OCD adjust mode OCD calibration mode exit
WR
WL DQS
tDS tDH
DT0
CLK
DQS_in
CMD
DQ_in
DM
NOP
EMRSNOP
NOP
NOP
NOP
NOP
NOPEMRS
CLK
DT1 DT2 DT3
Figure 7 OCD Adjust Mode
8.2.3.3 Drive Mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure DDR2 SDRAM Driver
impedance. In this mode, all outputs are driven out tOIT after enter drive mode” command and all
output drivers are turned-off tOIT after “OCD calibration mode exit” command as shown in Figure 8.
Enter Drive mode OCD calibration mode exit
EMRSEMRS NOP NOP NOP NOP NOPNOP NOP
CLK
DQS
DQS
CMD
DQ
tOIT tOIT
DQs high for Drive (1)
DQs low for Drive (0)
DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0)
CLK
HI-Z
Figure 8 OCD Drive Mode
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8.2.4 On-Die Termination (ODT)
On-Die Termination (ODT) is a new feature on DDR2 components that allows a DRAM to turn on/off
termination resistance for each DQ, UDQS/
UDQS
, LDQS/
LDQS
, UDM and LDM signal via the ODT
control pin.
UDQS
and
LDQS
are terminated only when enabled in the EMR (1) by address bit A10
= 0. The ODT feature is designed to improve signal integrity of the memory channel by allowing the
DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
The ODT function can be used for all active and standby modes. ODT is turned off and not supported
in Self Refresh mode. (Example timing waveforms refer to 11.2, 11.3 ODT Timing for
Active/Standby/Power Down Mode and 11.4, 11.5 ODT timing mode switch at entering/exiting power
down mode diagram in Chapter 11)
DRAM
Input
Buffer
Input
Pin
VDDQ
sw1
Rval3
VDDQ VDDQ
sw2sw3
Rval1 Rval2
Rval1 Rval2 Rval3
sw1sw2sw3
VSSQ VSSQ VSSQ
Switch (sw1, sw2, sw3) is enabled by ODT pin.
Selection among sw1, sw2, and sw3 is determined by “Rtt (nominal)” in EMR (1).
Termination included on all DQs, DM, DQS,
DQS
pins.
Figure 9 Functional Representation of ODT
8.2.5 ODT related timings
8.2.5.1 MRS command to ODT update delay
During normal operation the value of the effective termination resistance can be changed with an
EMRS command. The update of the Rtt setting is done between tMOD,min and tMOD,max, and CKE
must remain HIGH for the entire duration of tMOD window for proper operation. The timings are shown
in the following timing diagram.